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Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2017263e BG |
32 | #include "drmP.h" |
33 | #include "drm.h" | |
4e5359cd | 34 | #include "intel_drv.h" |
e5c65260 | 35 | #include "intel_ringbuffer.h" |
2017263e BG |
36 | #include "i915_drm.h" |
37 | #include "i915_drv.h" | |
38 | ||
39 | #define DRM_I915_RING_DEBUG 1 | |
40 | ||
41 | ||
42 | #if defined(CONFIG_DEBUG_FS) | |
43 | ||
f13d3f73 | 44 | enum { |
69dc4987 | 45 | ACTIVE_LIST, |
f13d3f73 CW |
46 | FLUSHING_LIST, |
47 | INACTIVE_LIST, | |
d21d5975 CW |
48 | PINNED_LIST, |
49 | DEFERRED_FREE_LIST, | |
f13d3f73 | 50 | }; |
2017263e | 51 | |
70d39fe4 CW |
52 | static const char *yesno(int v) |
53 | { | |
54 | return v ? "yes" : "no"; | |
55 | } | |
56 | ||
57 | static int i915_capabilities(struct seq_file *m, void *data) | |
58 | { | |
59 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
60 | struct drm_device *dev = node->minor->dev; | |
61 | const struct intel_device_info *info = INTEL_INFO(dev); | |
62 | ||
63 | seq_printf(m, "gen: %d\n", info->gen); | |
64 | #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) | |
65 | B(is_mobile); | |
70d39fe4 CW |
66 | B(is_i85x); |
67 | B(is_i915g); | |
70d39fe4 | 68 | B(is_i945gm); |
70d39fe4 CW |
69 | B(is_g33); |
70 | B(need_gfx_hws); | |
71 | B(is_g4x); | |
72 | B(is_pineview); | |
73 | B(is_broadwater); | |
74 | B(is_crestline); | |
70d39fe4 | 75 | B(has_fbc); |
70d39fe4 CW |
76 | B(has_pipe_cxsr); |
77 | B(has_hotplug); | |
78 | B(cursor_needs_physical); | |
79 | B(has_overlay); | |
80 | B(overlay_needs_physical); | |
a6c45cf0 | 81 | B(supports_tv); |
549f7365 CW |
82 | B(has_bsd_ring); |
83 | B(has_blt_ring); | |
70d39fe4 CW |
84 | #undef B |
85 | ||
86 | return 0; | |
87 | } | |
2017263e | 88 | |
05394f39 | 89 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 90 | { |
05394f39 | 91 | if (obj->user_pin_count > 0) |
a6172a80 | 92 | return "P"; |
05394f39 | 93 | else if (obj->pin_count > 0) |
a6172a80 CW |
94 | return "p"; |
95 | else | |
96 | return " "; | |
97 | } | |
98 | ||
05394f39 | 99 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 100 | { |
05394f39 | 101 | switch (obj->tiling_mode) { |
a6172a80 CW |
102 | default: |
103 | case I915_TILING_NONE: return " "; | |
104 | case I915_TILING_X: return "X"; | |
105 | case I915_TILING_Y: return "Y"; | |
106 | } | |
107 | } | |
108 | ||
93dfb40c | 109 | static const char *cache_level_str(int type) |
08c18323 CW |
110 | { |
111 | switch (type) { | |
93dfb40c CW |
112 | case I915_CACHE_NONE: return " uncached"; |
113 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
114 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
115 | default: return ""; |
116 | } | |
117 | } | |
118 | ||
37811fcc CW |
119 | static void |
120 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
121 | { | |
08c18323 | 122 | seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s", |
37811fcc CW |
123 | &obj->base, |
124 | get_pin_flag(obj), | |
125 | get_tiling_flag(obj), | |
126 | obj->base.size, | |
127 | obj->base.read_domains, | |
128 | obj->base.write_domain, | |
129 | obj->last_rendering_seqno, | |
caea7476 | 130 | obj->last_fenced_seqno, |
93dfb40c | 131 | cache_level_str(obj->cache_level), |
37811fcc CW |
132 | obj->dirty ? " dirty" : "", |
133 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
134 | if (obj->base.name) | |
135 | seq_printf(m, " (name: %d)", obj->base.name); | |
136 | if (obj->fence_reg != I915_FENCE_REG_NONE) | |
137 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
138 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
139 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
140 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
6299f992 CW |
141 | if (obj->pin_mappable || obj->fault_mappable) { |
142 | char s[3], *t = s; | |
143 | if (obj->pin_mappable) | |
144 | *t++ = 'p'; | |
145 | if (obj->fault_mappable) | |
146 | *t++ = 'f'; | |
147 | *t = '\0'; | |
148 | seq_printf(m, " (%s mappable)", s); | |
149 | } | |
69dc4987 CW |
150 | if (obj->ring != NULL) |
151 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
152 | } |
153 | ||
433e12f7 | 154 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
155 | { |
156 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
157 | uintptr_t list = (uintptr_t) node->info_ent->data; |
158 | struct list_head *head; | |
2017263e BG |
159 | struct drm_device *dev = node->minor->dev; |
160 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 161 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
162 | size_t total_obj_size, total_gtt_size; |
163 | int count, ret; | |
de227ef0 CW |
164 | |
165 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
166 | if (ret) | |
167 | return ret; | |
2017263e | 168 | |
433e12f7 BG |
169 | switch (list) { |
170 | case ACTIVE_LIST: | |
171 | seq_printf(m, "Active:\n"); | |
69dc4987 | 172 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
173 | break; |
174 | case INACTIVE_LIST: | |
a17458fc | 175 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
176 | head = &dev_priv->mm.inactive_list; |
177 | break; | |
f13d3f73 CW |
178 | case PINNED_LIST: |
179 | seq_printf(m, "Pinned:\n"); | |
180 | head = &dev_priv->mm.pinned_list; | |
181 | break; | |
433e12f7 BG |
182 | case FLUSHING_LIST: |
183 | seq_printf(m, "Flushing:\n"); | |
184 | head = &dev_priv->mm.flushing_list; | |
185 | break; | |
d21d5975 CW |
186 | case DEFERRED_FREE_LIST: |
187 | seq_printf(m, "Deferred free:\n"); | |
188 | head = &dev_priv->mm.deferred_free_list; | |
189 | break; | |
433e12f7 | 190 | default: |
de227ef0 CW |
191 | mutex_unlock(&dev->struct_mutex); |
192 | return -EINVAL; | |
2017263e | 193 | } |
2017263e | 194 | |
8f2480fb | 195 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 196 | list_for_each_entry(obj, head, mm_list) { |
37811fcc | 197 | seq_printf(m, " "); |
05394f39 | 198 | describe_obj(m, obj); |
f4ceda89 | 199 | seq_printf(m, "\n"); |
05394f39 CW |
200 | total_obj_size += obj->base.size; |
201 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 202 | count++; |
2017263e | 203 | } |
de227ef0 | 204 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 205 | |
8f2480fb CW |
206 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
207 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
208 | return 0; |
209 | } | |
210 | ||
6299f992 CW |
211 | #define count_objects(list, member) do { \ |
212 | list_for_each_entry(obj, list, member) { \ | |
213 | size += obj->gtt_space->size; \ | |
214 | ++count; \ | |
215 | if (obj->map_and_fenceable) { \ | |
216 | mappable_size += obj->gtt_space->size; \ | |
217 | ++mappable_count; \ | |
218 | } \ | |
219 | } \ | |
220 | } while(0) | |
221 | ||
73aa808f CW |
222 | static int i915_gem_object_info(struct seq_file *m, void* data) |
223 | { | |
224 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
225 | struct drm_device *dev = node->minor->dev; | |
226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6299f992 CW |
227 | u32 count, mappable_count; |
228 | size_t size, mappable_size; | |
229 | struct drm_i915_gem_object *obj; | |
73aa808f CW |
230 | int ret; |
231 | ||
232 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
233 | if (ret) | |
234 | return ret; | |
235 | ||
6299f992 CW |
236 | seq_printf(m, "%u objects, %zu bytes\n", |
237 | dev_priv->mm.object_count, | |
238 | dev_priv->mm.object_memory); | |
239 | ||
240 | size = count = mappable_size = mappable_count = 0; | |
241 | count_objects(&dev_priv->mm.gtt_list, gtt_list); | |
242 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", | |
243 | count, mappable_count, size, mappable_size); | |
244 | ||
245 | size = count = mappable_size = mappable_count = 0; | |
246 | count_objects(&dev_priv->mm.active_list, mm_list); | |
247 | count_objects(&dev_priv->mm.flushing_list, mm_list); | |
248 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", | |
249 | count, mappable_count, size, mappable_size); | |
250 | ||
251 | size = count = mappable_size = mappable_count = 0; | |
252 | count_objects(&dev_priv->mm.pinned_list, mm_list); | |
253 | seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n", | |
254 | count, mappable_count, size, mappable_size); | |
255 | ||
256 | size = count = mappable_size = mappable_count = 0; | |
257 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
258 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
259 | count, mappable_count, size, mappable_size); | |
260 | ||
261 | size = count = mappable_size = mappable_count = 0; | |
262 | count_objects(&dev_priv->mm.deferred_free_list, mm_list); | |
263 | seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n", | |
264 | count, mappable_count, size, mappable_size); | |
265 | ||
266 | size = count = mappable_size = mappable_count = 0; | |
267 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
268 | if (obj->fault_mappable) { | |
269 | size += obj->gtt_space->size; | |
270 | ++count; | |
271 | } | |
272 | if (obj->pin_mappable) { | |
273 | mappable_size += obj->gtt_space->size; | |
274 | ++mappable_count; | |
275 | } | |
276 | } | |
277 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", | |
278 | mappable_count, mappable_size); | |
279 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
280 | count, size); | |
281 | ||
282 | seq_printf(m, "%zu [%zu] gtt total\n", | |
283 | dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); | |
73aa808f CW |
284 | |
285 | mutex_unlock(&dev->struct_mutex); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
08c18323 CW |
290 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
291 | { | |
292 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
293 | struct drm_device *dev = node->minor->dev; | |
294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
295 | struct drm_i915_gem_object *obj; | |
296 | size_t total_obj_size, total_gtt_size; | |
297 | int count, ret; | |
298 | ||
299 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
300 | if (ret) | |
301 | return ret; | |
302 | ||
303 | total_obj_size = total_gtt_size = count = 0; | |
304 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
305 | seq_printf(m, " "); | |
306 | describe_obj(m, obj); | |
307 | seq_printf(m, "\n"); | |
308 | total_obj_size += obj->base.size; | |
309 | total_gtt_size += obj->gtt_space->size; | |
310 | count++; | |
311 | } | |
312 | ||
313 | mutex_unlock(&dev->struct_mutex); | |
314 | ||
315 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
316 | count, total_obj_size, total_gtt_size); | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
73aa808f | 321 | |
4e5359cd SF |
322 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
323 | { | |
324 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
325 | struct drm_device *dev = node->minor->dev; | |
326 | unsigned long flags; | |
327 | struct intel_crtc *crtc; | |
328 | ||
329 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
330 | const char pipe = pipe_name(crtc->pipe); |
331 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
332 | struct intel_unpin_work *work; |
333 | ||
334 | spin_lock_irqsave(&dev->event_lock, flags); | |
335 | work = crtc->unpin_work; | |
336 | if (work == NULL) { | |
9db4a9c7 | 337 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
338 | pipe, plane); |
339 | } else { | |
340 | if (!work->pending) { | |
9db4a9c7 | 341 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
342 | pipe, plane); |
343 | } else { | |
9db4a9c7 | 344 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
345 | pipe, plane); |
346 | } | |
347 | if (work->enable_stall_check) | |
348 | seq_printf(m, "Stall check enabled, "); | |
349 | else | |
350 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
351 | seq_printf(m, "%d prepares\n", work->pending); | |
352 | ||
353 | if (work->old_fb_obj) { | |
05394f39 CW |
354 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
355 | if (obj) | |
356 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
357 | } |
358 | if (work->pending_flip_obj) { | |
05394f39 CW |
359 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
360 | if (obj) | |
361 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
362 | } |
363 | } | |
364 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
365 | } | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
2017263e BG |
370 | static int i915_gem_request_info(struct seq_file *m, void *data) |
371 | { | |
372 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
373 | struct drm_device *dev = node->minor->dev; | |
374 | drm_i915_private_t *dev_priv = dev->dev_private; | |
375 | struct drm_i915_gem_request *gem_request; | |
c2c347a9 | 376 | int ret, count; |
de227ef0 CW |
377 | |
378 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
379 | if (ret) | |
380 | return ret; | |
2017263e | 381 | |
c2c347a9 | 382 | count = 0; |
1ec14ad3 | 383 | if (!list_empty(&dev_priv->ring[RCS].request_list)) { |
c2c347a9 CW |
384 | seq_printf(m, "Render requests:\n"); |
385 | list_for_each_entry(gem_request, | |
1ec14ad3 | 386 | &dev_priv->ring[RCS].request_list, |
c2c347a9 CW |
387 | list) { |
388 | seq_printf(m, " %d @ %d\n", | |
389 | gem_request->seqno, | |
390 | (int) (jiffies - gem_request->emitted_jiffies)); | |
391 | } | |
392 | count++; | |
393 | } | |
1ec14ad3 | 394 | if (!list_empty(&dev_priv->ring[VCS].request_list)) { |
c2c347a9 CW |
395 | seq_printf(m, "BSD requests:\n"); |
396 | list_for_each_entry(gem_request, | |
1ec14ad3 | 397 | &dev_priv->ring[VCS].request_list, |
c2c347a9 CW |
398 | list) { |
399 | seq_printf(m, " %d @ %d\n", | |
400 | gem_request->seqno, | |
401 | (int) (jiffies - gem_request->emitted_jiffies)); | |
402 | } | |
403 | count++; | |
404 | } | |
1ec14ad3 | 405 | if (!list_empty(&dev_priv->ring[BCS].request_list)) { |
c2c347a9 CW |
406 | seq_printf(m, "BLT requests:\n"); |
407 | list_for_each_entry(gem_request, | |
1ec14ad3 | 408 | &dev_priv->ring[BCS].request_list, |
c2c347a9 CW |
409 | list) { |
410 | seq_printf(m, " %d @ %d\n", | |
411 | gem_request->seqno, | |
412 | (int) (jiffies - gem_request->emitted_jiffies)); | |
413 | } | |
414 | count++; | |
2017263e | 415 | } |
de227ef0 CW |
416 | mutex_unlock(&dev->struct_mutex); |
417 | ||
c2c347a9 CW |
418 | if (count == 0) |
419 | seq_printf(m, "No requests\n"); | |
420 | ||
2017263e BG |
421 | return 0; |
422 | } | |
423 | ||
b2223497 CW |
424 | static void i915_ring_seqno_info(struct seq_file *m, |
425 | struct intel_ring_buffer *ring) | |
426 | { | |
427 | if (ring->get_seqno) { | |
428 | seq_printf(m, "Current sequence (%s): %d\n", | |
429 | ring->name, ring->get_seqno(ring)); | |
430 | seq_printf(m, "Waiter sequence (%s): %d\n", | |
431 | ring->name, ring->waiting_seqno); | |
432 | seq_printf(m, "IRQ sequence (%s): %d\n", | |
433 | ring->name, ring->irq_seqno); | |
434 | } | |
435 | } | |
436 | ||
2017263e BG |
437 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
438 | { | |
439 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
440 | struct drm_device *dev = node->minor->dev; | |
441 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 442 | int ret, i; |
de227ef0 CW |
443 | |
444 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
445 | if (ret) | |
446 | return ret; | |
2017263e | 447 | |
1ec14ad3 CW |
448 | for (i = 0; i < I915_NUM_RINGS; i++) |
449 | i915_ring_seqno_info(m, &dev_priv->ring[i]); | |
de227ef0 CW |
450 | |
451 | mutex_unlock(&dev->struct_mutex); | |
452 | ||
2017263e BG |
453 | return 0; |
454 | } | |
455 | ||
456 | ||
457 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
458 | { | |
459 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
460 | struct drm_device *dev = node->minor->dev; | |
461 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9db4a9c7 | 462 | int ret, i, pipe; |
de227ef0 CW |
463 | |
464 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
465 | if (ret) | |
466 | return ret; | |
2017263e | 467 | |
bad720ff | 468 | if (!HAS_PCH_SPLIT(dev)) { |
5f6a1695 ZW |
469 | seq_printf(m, "Interrupt enable: %08x\n", |
470 | I915_READ(IER)); | |
471 | seq_printf(m, "Interrupt identity: %08x\n", | |
472 | I915_READ(IIR)); | |
473 | seq_printf(m, "Interrupt mask: %08x\n", | |
474 | I915_READ(IMR)); | |
9db4a9c7 JB |
475 | for_each_pipe(pipe) |
476 | seq_printf(m, "Pipe %c stat: %08x\n", | |
477 | pipe_name(pipe), | |
478 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
479 | } else { |
480 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
481 | I915_READ(DEIER)); | |
482 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
483 | I915_READ(DEIIR)); | |
484 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
485 | I915_READ(DEIMR)); | |
486 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
487 | I915_READ(SDEIER)); | |
488 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
489 | I915_READ(SDEIIR)); | |
490 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
491 | I915_READ(SDEIMR)); | |
492 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
493 | I915_READ(GTIER)); | |
494 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
495 | I915_READ(GTIIR)); | |
496 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
497 | I915_READ(GTIMR)); | |
498 | } | |
2017263e BG |
499 | seq_printf(m, "Interrupts received: %d\n", |
500 | atomic_read(&dev_priv->irq_received)); | |
9862e600 | 501 | for (i = 0; i < I915_NUM_RINGS; i++) { |
da64c6fc | 502 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
9862e600 CW |
503 | seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", |
504 | dev_priv->ring[i].name, | |
505 | I915_READ_IMR(&dev_priv->ring[i])); | |
506 | } | |
1ec14ad3 | 507 | i915_ring_seqno_info(m, &dev_priv->ring[i]); |
9862e600 | 508 | } |
de227ef0 CW |
509 | mutex_unlock(&dev->struct_mutex); |
510 | ||
2017263e BG |
511 | return 0; |
512 | } | |
513 | ||
a6172a80 CW |
514 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
515 | { | |
516 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
517 | struct drm_device *dev = node->minor->dev; | |
518 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
519 | int i, ret; |
520 | ||
521 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
522 | if (ret) | |
523 | return ret; | |
a6172a80 CW |
524 | |
525 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
526 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
527 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 528 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 529 | |
c2c347a9 CW |
530 | seq_printf(m, "Fenced object[%2d] = ", i); |
531 | if (obj == NULL) | |
532 | seq_printf(m, "unused"); | |
533 | else | |
05394f39 | 534 | describe_obj(m, obj); |
c2c347a9 | 535 | seq_printf(m, "\n"); |
a6172a80 CW |
536 | } |
537 | ||
05394f39 | 538 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
539 | return 0; |
540 | } | |
541 | ||
2017263e BG |
542 | static int i915_hws_info(struct seq_file *m, void *data) |
543 | { | |
544 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
545 | struct drm_device *dev = node->minor->dev; | |
546 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 547 | struct intel_ring_buffer *ring; |
311bd68e | 548 | const volatile u32 __iomem *hws; |
4066c0ae CW |
549 | int i; |
550 | ||
1ec14ad3 | 551 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
311bd68e | 552 | hws = (volatile u32 __iomem *)ring->status_page.page_addr; |
2017263e BG |
553 | if (hws == NULL) |
554 | return 0; | |
555 | ||
556 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
557 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
558 | i * 4, | |
559 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
560 | } | |
561 | return 0; | |
562 | } | |
563 | ||
5cdf5881 CW |
564 | static void i915_dump_object(struct seq_file *m, |
565 | struct io_mapping *mapping, | |
05394f39 | 566 | struct drm_i915_gem_object *obj) |
6911a9b8 | 567 | { |
5cdf5881 | 568 | int page, page_count, i; |
6911a9b8 | 569 | |
05394f39 | 570 | page_count = obj->base.size / PAGE_SIZE; |
6911a9b8 | 571 | for (page = 0; page < page_count; page++) { |
5cdf5881 | 572 | u32 *mem = io_mapping_map_wc(mapping, |
05394f39 | 573 | obj->gtt_offset + page * PAGE_SIZE); |
6911a9b8 BG |
574 | for (i = 0; i < PAGE_SIZE; i += 4) |
575 | seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); | |
5cdf5881 | 576 | io_mapping_unmap(mem); |
6911a9b8 BG |
577 | } |
578 | } | |
579 | ||
580 | static int i915_batchbuffer_info(struct seq_file *m, void *data) | |
581 | { | |
582 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
583 | struct drm_device *dev = node->minor->dev; | |
584 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 585 | struct drm_i915_gem_object *obj; |
6911a9b8 BG |
586 | int ret; |
587 | ||
de227ef0 CW |
588 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
589 | if (ret) | |
590 | return ret; | |
6911a9b8 | 591 | |
05394f39 CW |
592 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
593 | if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) { | |
594 | seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset); | |
595 | i915_dump_object(m, dev_priv->mm.gtt_mapping, obj); | |
6911a9b8 BG |
596 | } |
597 | } | |
598 | ||
de227ef0 | 599 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
600 | return 0; |
601 | } | |
602 | ||
603 | static int i915_ringbuffer_data(struct seq_file *m, void *data) | |
604 | { | |
605 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
606 | struct drm_device *dev = node->minor->dev; | |
607 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c2c347a9 | 608 | struct intel_ring_buffer *ring; |
de227ef0 CW |
609 | int ret; |
610 | ||
611 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
612 | if (ret) | |
613 | return ret; | |
6911a9b8 | 614 | |
1ec14ad3 | 615 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
05394f39 | 616 | if (!ring->obj) { |
6911a9b8 | 617 | seq_printf(m, "No ringbuffer setup\n"); |
de227ef0 | 618 | } else { |
311bd68e | 619 | const u8 __iomem *virt = ring->virtual_start; |
de227ef0 | 620 | uint32_t off; |
6911a9b8 | 621 | |
c2c347a9 | 622 | for (off = 0; off < ring->size; off += 4) { |
de227ef0 CW |
623 | uint32_t *ptr = (uint32_t *)(virt + off); |
624 | seq_printf(m, "%08x : %08x\n", off, *ptr); | |
625 | } | |
6911a9b8 | 626 | } |
de227ef0 | 627 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
628 | |
629 | return 0; | |
630 | } | |
631 | ||
632 | static int i915_ringbuffer_info(struct seq_file *m, void *data) | |
633 | { | |
634 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
635 | struct drm_device *dev = node->minor->dev; | |
636 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c2c347a9 CW |
637 | struct intel_ring_buffer *ring; |
638 | ||
1ec14ad3 | 639 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
c2c347a9 | 640 | if (ring->size == 0) |
1ec14ad3 | 641 | return 0; |
6911a9b8 | 642 | |
c2c347a9 CW |
643 | seq_printf(m, "Ring %s:\n", ring->name); |
644 | seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR); | |
645 | seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR); | |
646 | seq_printf(m, " Size : %08x\n", ring->size); | |
647 | seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring)); | |
1ec14ad3 CW |
648 | seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring)); |
649 | if (IS_GEN6(dev)) { | |
650 | seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring)); | |
651 | seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring)); | |
652 | } | |
c2c347a9 CW |
653 | seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring)); |
654 | seq_printf(m, " Start : %08x\n", I915_READ_START(ring)); | |
6911a9b8 BG |
655 | |
656 | return 0; | |
657 | } | |
658 | ||
e5c65260 CW |
659 | static const char *ring_str(int ring) |
660 | { | |
661 | switch (ring) { | |
3685092b CW |
662 | case RING_RENDER: return " render"; |
663 | case RING_BSD: return " bsd"; | |
664 | case RING_BLT: return " blt"; | |
e5c65260 CW |
665 | default: return ""; |
666 | } | |
667 | } | |
668 | ||
9df30794 CW |
669 | static const char *pin_flag(int pinned) |
670 | { | |
671 | if (pinned > 0) | |
672 | return " P"; | |
673 | else if (pinned < 0) | |
674 | return " p"; | |
675 | else | |
676 | return ""; | |
677 | } | |
678 | ||
679 | static const char *tiling_flag(int tiling) | |
680 | { | |
681 | switch (tiling) { | |
682 | default: | |
683 | case I915_TILING_NONE: return ""; | |
684 | case I915_TILING_X: return " X"; | |
685 | case I915_TILING_Y: return " Y"; | |
686 | } | |
687 | } | |
688 | ||
689 | static const char *dirty_flag(int dirty) | |
690 | { | |
691 | return dirty ? " dirty" : ""; | |
692 | } | |
693 | ||
694 | static const char *purgeable_flag(int purgeable) | |
695 | { | |
696 | return purgeable ? " purgeable" : ""; | |
697 | } | |
698 | ||
c724e8a9 CW |
699 | static void print_error_buffers(struct seq_file *m, |
700 | const char *name, | |
701 | struct drm_i915_error_buffer *err, | |
702 | int count) | |
703 | { | |
704 | seq_printf(m, "%s [%d]:\n", name, count); | |
705 | ||
706 | while (count--) { | |
833bcb00 | 707 | seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s", |
c724e8a9 CW |
708 | err->gtt_offset, |
709 | err->size, | |
710 | err->read_domains, | |
711 | err->write_domain, | |
712 | err->seqno, | |
713 | pin_flag(err->pinned), | |
714 | tiling_flag(err->tiling), | |
715 | dirty_flag(err->dirty), | |
716 | purgeable_flag(err->purgeable), | |
a779e5ab | 717 | ring_str(err->ring), |
93dfb40c | 718 | cache_level_str(err->cache_level)); |
c724e8a9 CW |
719 | |
720 | if (err->name) | |
721 | seq_printf(m, " (name: %d)", err->name); | |
722 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
723 | seq_printf(m, " (fence: %d)", err->fence_reg); | |
724 | ||
725 | seq_printf(m, "\n"); | |
726 | err++; | |
727 | } | |
728 | } | |
729 | ||
63eeaf38 JB |
730 | static int i915_error_state(struct seq_file *m, void *unused) |
731 | { | |
732 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
733 | struct drm_device *dev = node->minor->dev; | |
734 | drm_i915_private_t *dev_priv = dev->dev_private; | |
735 | struct drm_i915_error_state *error; | |
736 | unsigned long flags; | |
9df30794 | 737 | int i, page, offset, elt; |
63eeaf38 JB |
738 | |
739 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
740 | if (!dev_priv->first_error) { | |
741 | seq_printf(m, "no error state collected\n"); | |
742 | goto out; | |
743 | } | |
744 | ||
745 | error = dev_priv->first_error; | |
746 | ||
8a905236 JB |
747 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
748 | error->time.tv_usec); | |
9df30794 | 749 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
1d8f38f4 CW |
750 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
751 | seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); | |
f406839f CW |
752 | if (INTEL_INFO(dev)->gen >= 6) { |
753 | seq_printf(m, "ERROR: 0x%08x\n", error->error); | |
1d8f38f4 CW |
754 | seq_printf(m, "Blitter command stream:\n"); |
755 | seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd); | |
1d8f38f4 | 756 | seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir); |
e5c65260 | 757 | seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr); |
1d8f38f4 CW |
758 | seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone); |
759 | seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno); | |
add354dd CW |
760 | seq_printf(m, "Video (BSD) command stream:\n"); |
761 | seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd); | |
add354dd | 762 | seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir); |
e5c65260 | 763 | seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr); |
add354dd CW |
764 | seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone); |
765 | seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno); | |
f406839f | 766 | } |
1d8f38f4 CW |
767 | seq_printf(m, "Render command stream:\n"); |
768 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); | |
63eeaf38 JB |
769 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); |
770 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); | |
771 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); | |
a6c45cf0 | 772 | if (INTEL_INFO(dev)->gen >= 4) { |
63eeaf38 | 773 | seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); |
1d8f38f4 | 774 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps); |
63eeaf38 | 775 | } |
1d8f38f4 CW |
776 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); |
777 | seq_printf(m, " seqno: 0x%08x\n", error->seqno); | |
9df30794 | 778 | |
bf3301ab | 779 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
780 | seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
781 | ||
c724e8a9 CW |
782 | if (error->active_bo) |
783 | print_error_buffers(m, "Active", | |
784 | error->active_bo, | |
785 | error->active_bo_count); | |
786 | ||
787 | if (error->pinned_bo) | |
788 | print_error_buffers(m, "Pinned", | |
789 | error->pinned_bo, | |
790 | error->pinned_bo_count); | |
9df30794 CW |
791 | |
792 | for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) { | |
793 | if (error->batchbuffer[i]) { | |
794 | struct drm_i915_error_object *obj = error->batchbuffer[i]; | |
795 | ||
bcfb2e28 CW |
796 | seq_printf(m, "%s --- gtt_offset = 0x%08x\n", |
797 | dev_priv->ring[i].name, | |
798 | obj->gtt_offset); | |
9df30794 CW |
799 | offset = 0; |
800 | for (page = 0; page < obj->page_count; page++) { | |
801 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
802 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
803 | offset += 4; | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | ||
e2f973d5 CW |
809 | for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) { |
810 | if (error->ringbuffer[i]) { | |
811 | struct drm_i915_error_object *obj = error->ringbuffer[i]; | |
812 | seq_printf(m, "%s --- ringbuffer = 0x%08x\n", | |
813 | dev_priv->ring[i].name, | |
814 | obj->gtt_offset); | |
815 | offset = 0; | |
816 | for (page = 0; page < obj->page_count; page++) { | |
817 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
818 | seq_printf(m, "%08x : %08x\n", | |
819 | offset, | |
820 | obj->pages[page][elt]); | |
821 | offset += 4; | |
822 | } | |
9df30794 CW |
823 | } |
824 | } | |
825 | } | |
63eeaf38 | 826 | |
6ef3d427 CW |
827 | if (error->overlay) |
828 | intel_overlay_print_error_state(m, error->overlay); | |
829 | ||
c4a1d9e4 CW |
830 | if (error->display) |
831 | intel_display_print_error_state(m, dev, error->display); | |
832 | ||
63eeaf38 JB |
833 | out: |
834 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
835 | ||
836 | return 0; | |
837 | } | |
6911a9b8 | 838 | |
f97108d1 JB |
839 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
840 | { | |
841 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
842 | struct drm_device *dev = node->minor->dev; | |
843 | drm_i915_private_t *dev_priv = dev->dev_private; | |
844 | u16 crstanddelay = I915_READ16(CRSTANDVID); | |
845 | ||
846 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
847 | ||
848 | return 0; | |
849 | } | |
850 | ||
851 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
852 | { | |
853 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
854 | struct drm_device *dev = node->minor->dev; | |
855 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 856 | int ret; |
3b8d8d91 JB |
857 | |
858 | if (IS_GEN5(dev)) { | |
859 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
860 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
861 | ||
862 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
863 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
864 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
865 | MEMSTAT_VID_SHIFT); | |
866 | seq_printf(m, "Current P-state: %d\n", | |
867 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
1c70c0ce | 868 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 JB |
869 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
870 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
871 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
ccab5c82 JB |
872 | u32 rpstat; |
873 | u32 rpupei, rpcurup, rpprevup; | |
874 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
875 | int max_freq; |
876 | ||
877 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
878 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
879 | if (ret) | |
880 | return ret; | |
881 | ||
fcca7926 | 882 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 883 | |
ccab5c82 JB |
884 | rpstat = I915_READ(GEN6_RPSTAT1); |
885 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
886 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
887 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
888 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
889 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
890 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
891 | ||
d1ebd816 BW |
892 | gen6_gt_force_wake_put(dev_priv); |
893 | mutex_unlock(&dev->struct_mutex); | |
894 | ||
3b8d8d91 | 895 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 896 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
897 | seq_printf(m, "Render p-state ratio: %d\n", |
898 | (gt_perf_status & 0xff00) >> 8); | |
899 | seq_printf(m, "Render p-state VID: %d\n", | |
900 | gt_perf_status & 0xff); | |
901 | seq_printf(m, "Render p-state limit: %d\n", | |
902 | rp_state_limits & 0xff); | |
ccab5c82 | 903 | seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> |
e281fcaa | 904 | GEN6_CAGF_SHIFT) * 50); |
ccab5c82 JB |
905 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
906 | GEN6_CURICONT_MASK); | |
907 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
908 | GEN6_CURBSYTAVG_MASK); | |
909 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
910 | GEN6_CURBSYTAVG_MASK); | |
911 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
912 | GEN6_CURIAVG_MASK); | |
913 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
914 | GEN6_CURBSYTAVG_MASK); | |
915 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
916 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
917 | |
918 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
919 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
e281fcaa | 920 | max_freq * 50); |
3b8d8d91 JB |
921 | |
922 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
923 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
e281fcaa | 924 | max_freq * 50); |
3b8d8d91 JB |
925 | |
926 | max_freq = rp_state_cap & 0xff; | |
927 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
e281fcaa | 928 | max_freq * 50); |
3b8d8d91 JB |
929 | } else { |
930 | seq_printf(m, "no P-state info available\n"); | |
931 | } | |
f97108d1 JB |
932 | |
933 | return 0; | |
934 | } | |
935 | ||
936 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
937 | { | |
938 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
939 | struct drm_device *dev = node->minor->dev; | |
940 | drm_i915_private_t *dev_priv = dev->dev_private; | |
941 | u32 delayfreq; | |
942 | int i; | |
943 | ||
944 | for (i = 0; i < 16; i++) { | |
945 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
946 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
947 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
948 | } |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | static inline int MAP_TO_MV(int map) | |
954 | { | |
955 | return 1250 - (map * 25); | |
956 | } | |
957 | ||
958 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
959 | { | |
960 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
961 | struct drm_device *dev = node->minor->dev; | |
962 | drm_i915_private_t *dev_priv = dev->dev_private; | |
963 | u32 inttoext; | |
964 | int i; | |
965 | ||
966 | for (i = 1; i <= 32; i++) { | |
967 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
968 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
969 | } | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
974 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
975 | { | |
976 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
977 | struct drm_device *dev = node->minor->dev; | |
978 | drm_i915_private_t *dev_priv = dev->dev_private; | |
979 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
88271da3 | 980 | u32 rstdbyctl = I915_READ(RSTDBYCTL); |
7648fa99 | 981 | u16 crstandvid = I915_READ16(CRSTANDVID); |
f97108d1 JB |
982 | |
983 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
984 | "yes" : "no"); | |
985 | seq_printf(m, "Boost freq: %d\n", | |
986 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
987 | MEMMODE_BOOST_FREQ_SHIFT); | |
988 | seq_printf(m, "HW control enabled: %s\n", | |
989 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
990 | seq_printf(m, "SW control enabled: %s\n", | |
991 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
992 | seq_printf(m, "Gated voltage change: %s\n", | |
993 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
994 | seq_printf(m, "Starting frequency: P%d\n", | |
995 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 996 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 997 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
998 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
999 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1000 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1001 | seq_printf(m, "Render standby enabled: %s\n", | |
1002 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
88271da3 JB |
1003 | seq_printf(m, "Current RS state: "); |
1004 | switch (rstdbyctl & RSX_STATUS_MASK) { | |
1005 | case RSX_STATUS_ON: | |
1006 | seq_printf(m, "on\n"); | |
1007 | break; | |
1008 | case RSX_STATUS_RC1: | |
1009 | seq_printf(m, "RC1\n"); | |
1010 | break; | |
1011 | case RSX_STATUS_RC1E: | |
1012 | seq_printf(m, "RC1E\n"); | |
1013 | break; | |
1014 | case RSX_STATUS_RS1: | |
1015 | seq_printf(m, "RS1\n"); | |
1016 | break; | |
1017 | case RSX_STATUS_RS2: | |
1018 | seq_printf(m, "RS2 (RC6)\n"); | |
1019 | break; | |
1020 | case RSX_STATUS_RS3: | |
1021 | seq_printf(m, "RC3 (RC6+)\n"); | |
1022 | break; | |
1023 | default: | |
1024 | seq_printf(m, "unknown\n"); | |
1025 | break; | |
1026 | } | |
f97108d1 JB |
1027 | |
1028 | return 0; | |
1029 | } | |
1030 | ||
b5e50c3f JB |
1031 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1032 | { | |
1033 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1034 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1035 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1036 | |
ee5382ae | 1037 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
1038 | seq_printf(m, "FBC unsupported on this chipset\n"); |
1039 | return 0; | |
1040 | } | |
1041 | ||
ee5382ae | 1042 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
1043 | seq_printf(m, "FBC enabled\n"); |
1044 | } else { | |
1045 | seq_printf(m, "FBC disabled: "); | |
1046 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
1047 | case FBC_NO_OUTPUT: |
1048 | seq_printf(m, "no outputs"); | |
1049 | break; | |
b5e50c3f JB |
1050 | case FBC_STOLEN_TOO_SMALL: |
1051 | seq_printf(m, "not enough stolen memory"); | |
1052 | break; | |
1053 | case FBC_UNSUPPORTED_MODE: | |
1054 | seq_printf(m, "mode not supported"); | |
1055 | break; | |
1056 | case FBC_MODE_TOO_LARGE: | |
1057 | seq_printf(m, "mode too large"); | |
1058 | break; | |
1059 | case FBC_BAD_PLANE: | |
1060 | seq_printf(m, "FBC unsupported on plane"); | |
1061 | break; | |
1062 | case FBC_NOT_TILED: | |
1063 | seq_printf(m, "scanout buffer not tiled"); | |
1064 | break; | |
9c928d16 JB |
1065 | case FBC_MULTIPLE_PIPES: |
1066 | seq_printf(m, "multiple pipes are enabled"); | |
1067 | break; | |
c1a9f047 JB |
1068 | case FBC_MODULE_PARAM: |
1069 | seq_printf(m, "disabled per module param (default off)"); | |
1070 | break; | |
b5e50c3f JB |
1071 | default: |
1072 | seq_printf(m, "unknown reason"); | |
1073 | } | |
1074 | seq_printf(m, "\n"); | |
1075 | } | |
1076 | return 0; | |
1077 | } | |
1078 | ||
4a9bef37 JB |
1079 | static int i915_sr_status(struct seq_file *m, void *unused) |
1080 | { | |
1081 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1082 | struct drm_device *dev = node->minor->dev; | |
1083 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1084 | bool sr_enabled = false; | |
1085 | ||
1398261a | 1086 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1087 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1088 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1089 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1090 | else if (IS_I915GM(dev)) | |
1091 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1092 | else if (IS_PINEVIEW(dev)) | |
1093 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1094 | ||
5ba2aaaa CW |
1095 | seq_printf(m, "self-refresh: %s\n", |
1096 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1097 | |
1098 | return 0; | |
1099 | } | |
1100 | ||
7648fa99 JB |
1101 | static int i915_emon_status(struct seq_file *m, void *unused) |
1102 | { | |
1103 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1104 | struct drm_device *dev = node->minor->dev; | |
1105 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1106 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1107 | int ret; |
1108 | ||
1109 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1110 | if (ret) | |
1111 | return ret; | |
7648fa99 JB |
1112 | |
1113 | temp = i915_mch_val(dev_priv); | |
1114 | chipset = i915_chipset_val(dev_priv); | |
1115 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1116 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1117 | |
1118 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1119 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1120 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1121 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
23b2f8bb JB |
1126 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1127 | { | |
1128 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1129 | struct drm_device *dev = node->minor->dev; | |
1130 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1131 | int ret; | |
1132 | int gpu_freq, ia_freq; | |
1133 | ||
1c70c0ce | 1134 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
23b2f8bb JB |
1135 | seq_printf(m, "unsupported on this chipset\n"); |
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1140 | if (ret) | |
1141 | return ret; | |
1142 | ||
1143 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); | |
1144 | ||
1145 | for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay; | |
1146 | gpu_freq++) { | |
1147 | I915_WRITE(GEN6_PCODE_DATA, gpu_freq); | |
1148 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
1149 | GEN6_PCODE_READ_MIN_FREQ_TABLE); | |
1150 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
1151 | GEN6_PCODE_READY) == 0, 10)) { | |
1152 | DRM_ERROR("pcode read of freq table timed out\n"); | |
1153 | continue; | |
1154 | } | |
1155 | ia_freq = I915_READ(GEN6_PCODE_DATA); | |
1156 | seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100); | |
1157 | } | |
1158 | ||
1159 | mutex_unlock(&dev->struct_mutex); | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
7648fa99 JB |
1164 | static int i915_gfxec(struct seq_file *m, void *unused) |
1165 | { | |
1166 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1167 | struct drm_device *dev = node->minor->dev; | |
1168 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1169 | ||
1170 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1171 | ||
1172 | return 0; | |
1173 | } | |
1174 | ||
44834a67 CW |
1175 | static int i915_opregion(struct seq_file *m, void *unused) |
1176 | { | |
1177 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1178 | struct drm_device *dev = node->minor->dev; | |
1179 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1180 | struct intel_opregion *opregion = &dev_priv->opregion; | |
1181 | int ret; | |
1182 | ||
1183 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1184 | if (ret) | |
1185 | return ret; | |
1186 | ||
1187 | if (opregion->header) | |
1188 | seq_write(m, opregion->header, OPREGION_SIZE); | |
1189 | ||
1190 | mutex_unlock(&dev->struct_mutex); | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
37811fcc CW |
1195 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1196 | { | |
1197 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1198 | struct drm_device *dev = node->minor->dev; | |
1199 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1200 | struct intel_fbdev *ifbdev; | |
1201 | struct intel_framebuffer *fb; | |
1202 | int ret; | |
1203 | ||
1204 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1205 | if (ret) | |
1206 | return ret; | |
1207 | ||
1208 | ifbdev = dev_priv->fbdev; | |
1209 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1210 | ||
1211 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", | |
1212 | fb->base.width, | |
1213 | fb->base.height, | |
1214 | fb->base.depth, | |
1215 | fb->base.bits_per_pixel); | |
05394f39 | 1216 | describe_obj(m, fb->obj); |
37811fcc CW |
1217 | seq_printf(m, "\n"); |
1218 | ||
1219 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { | |
1220 | if (&fb->base == ifbdev->helper.fb) | |
1221 | continue; | |
1222 | ||
1223 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", | |
1224 | fb->base.width, | |
1225 | fb->base.height, | |
1226 | fb->base.depth, | |
1227 | fb->base.bits_per_pixel); | |
05394f39 | 1228 | describe_obj(m, fb->obj); |
37811fcc CW |
1229 | seq_printf(m, "\n"); |
1230 | } | |
1231 | ||
1232 | mutex_unlock(&dev->mode_config.mutex); | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
e76d3630 BW |
1237 | static int i915_context_status(struct seq_file *m, void *unused) |
1238 | { | |
1239 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1240 | struct drm_device *dev = node->minor->dev; | |
1241 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1242 | int ret; | |
1243 | ||
1244 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1245 | if (ret) | |
1246 | return ret; | |
1247 | ||
dc501fbc BW |
1248 | if (dev_priv->pwrctx) { |
1249 | seq_printf(m, "power context "); | |
1250 | describe_obj(m, dev_priv->pwrctx); | |
1251 | seq_printf(m, "\n"); | |
1252 | } | |
e76d3630 | 1253 | |
dc501fbc BW |
1254 | if (dev_priv->renderctx) { |
1255 | seq_printf(m, "render context "); | |
1256 | describe_obj(m, dev_priv->renderctx); | |
1257 | seq_printf(m, "\n"); | |
1258 | } | |
e76d3630 BW |
1259 | |
1260 | mutex_unlock(&dev->mode_config.mutex); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
6d794d42 BW |
1265 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1266 | { | |
1267 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1268 | struct drm_device *dev = node->minor->dev; | |
1269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1270 | ||
1271 | seq_printf(m, "forcewake count = %d\n", | |
1272 | atomic_read(&dev_priv->forcewake_count)); | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
f3cd474b CW |
1277 | static int |
1278 | i915_wedged_open(struct inode *inode, | |
1279 | struct file *filp) | |
1280 | { | |
1281 | filp->private_data = inode->i_private; | |
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | static ssize_t | |
1286 | i915_wedged_read(struct file *filp, | |
1287 | char __user *ubuf, | |
1288 | size_t max, | |
1289 | loff_t *ppos) | |
1290 | { | |
1291 | struct drm_device *dev = filp->private_data; | |
1292 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1293 | char buf[80]; | |
1294 | int len; | |
1295 | ||
1296 | len = snprintf(buf, sizeof (buf), | |
1297 | "wedged : %d\n", | |
1298 | atomic_read(&dev_priv->mm.wedged)); | |
1299 | ||
f4433a8d DC |
1300 | if (len > sizeof (buf)) |
1301 | len = sizeof (buf); | |
1302 | ||
f3cd474b CW |
1303 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
1304 | } | |
1305 | ||
1306 | static ssize_t | |
1307 | i915_wedged_write(struct file *filp, | |
1308 | const char __user *ubuf, | |
1309 | size_t cnt, | |
1310 | loff_t *ppos) | |
1311 | { | |
1312 | struct drm_device *dev = filp->private_data; | |
f3cd474b CW |
1313 | char buf[20]; |
1314 | int val = 1; | |
1315 | ||
1316 | if (cnt > 0) { | |
1317 | if (cnt > sizeof (buf) - 1) | |
1318 | return -EINVAL; | |
1319 | ||
1320 | if (copy_from_user(buf, ubuf, cnt)) | |
1321 | return -EFAULT; | |
1322 | buf[cnt] = 0; | |
1323 | ||
1324 | val = simple_strtoul(buf, NULL, 0); | |
1325 | } | |
1326 | ||
1327 | DRM_INFO("Manually setting wedged to %d\n", val); | |
527f9e90 | 1328 | i915_handle_error(dev, val); |
f3cd474b CW |
1329 | |
1330 | return cnt; | |
1331 | } | |
1332 | ||
1333 | static const struct file_operations i915_wedged_fops = { | |
1334 | .owner = THIS_MODULE, | |
1335 | .open = i915_wedged_open, | |
1336 | .read = i915_wedged_read, | |
1337 | .write = i915_wedged_write, | |
6038f373 | 1338 | .llseek = default_llseek, |
f3cd474b CW |
1339 | }; |
1340 | ||
358733e9 JB |
1341 | static int |
1342 | i915_max_freq_open(struct inode *inode, | |
1343 | struct file *filp) | |
1344 | { | |
1345 | filp->private_data = inode->i_private; | |
1346 | return 0; | |
1347 | } | |
1348 | ||
1349 | static ssize_t | |
1350 | i915_max_freq_read(struct file *filp, | |
1351 | char __user *ubuf, | |
1352 | size_t max, | |
1353 | loff_t *ppos) | |
1354 | { | |
1355 | struct drm_device *dev = filp->private_data; | |
1356 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1357 | char buf[80]; | |
1358 | int len; | |
1359 | ||
1360 | len = snprintf(buf, sizeof (buf), | |
1361 | "max freq: %d\n", dev_priv->max_delay * 50); | |
1362 | ||
1363 | if (len > sizeof (buf)) | |
1364 | len = sizeof (buf); | |
1365 | ||
1366 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1367 | } | |
1368 | ||
1369 | static ssize_t | |
1370 | i915_max_freq_write(struct file *filp, | |
1371 | const char __user *ubuf, | |
1372 | size_t cnt, | |
1373 | loff_t *ppos) | |
1374 | { | |
1375 | struct drm_device *dev = filp->private_data; | |
1376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1377 | char buf[20]; | |
1378 | int val = 1; | |
1379 | ||
1380 | if (cnt > 0) { | |
1381 | if (cnt > sizeof (buf) - 1) | |
1382 | return -EINVAL; | |
1383 | ||
1384 | if (copy_from_user(buf, ubuf, cnt)) | |
1385 | return -EFAULT; | |
1386 | buf[cnt] = 0; | |
1387 | ||
1388 | val = simple_strtoul(buf, NULL, 0); | |
1389 | } | |
1390 | ||
1391 | DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); | |
1392 | ||
1393 | /* | |
1394 | * Turbo will still be enabled, but won't go above the set value. | |
1395 | */ | |
1396 | dev_priv->max_delay = val / 50; | |
1397 | ||
1398 | gen6_set_rps(dev, val / 50); | |
1399 | ||
1400 | return cnt; | |
1401 | } | |
1402 | ||
1403 | static const struct file_operations i915_max_freq_fops = { | |
1404 | .owner = THIS_MODULE, | |
1405 | .open = i915_max_freq_open, | |
1406 | .read = i915_max_freq_read, | |
1407 | .write = i915_max_freq_write, | |
1408 | .llseek = default_llseek, | |
1409 | }; | |
1410 | ||
07b7ddd9 JB |
1411 | static int |
1412 | i915_cache_sharing_open(struct inode *inode, | |
1413 | struct file *filp) | |
1414 | { | |
1415 | filp->private_data = inode->i_private; | |
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | static ssize_t | |
1420 | i915_cache_sharing_read(struct file *filp, | |
1421 | char __user *ubuf, | |
1422 | size_t max, | |
1423 | loff_t *ppos) | |
1424 | { | |
1425 | struct drm_device *dev = filp->private_data; | |
1426 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1427 | char buf[80]; | |
1428 | u32 snpcr; | |
1429 | int len; | |
1430 | ||
1431 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1432 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1433 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1434 | ||
1435 | len = snprintf(buf, sizeof (buf), | |
1436 | "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> | |
1437 | GEN6_MBC_SNPCR_SHIFT); | |
1438 | ||
1439 | if (len > sizeof (buf)) | |
1440 | len = sizeof (buf); | |
1441 | ||
1442 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1443 | } | |
1444 | ||
1445 | static ssize_t | |
1446 | i915_cache_sharing_write(struct file *filp, | |
1447 | const char __user *ubuf, | |
1448 | size_t cnt, | |
1449 | loff_t *ppos) | |
1450 | { | |
1451 | struct drm_device *dev = filp->private_data; | |
1452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1453 | char buf[20]; | |
1454 | u32 snpcr; | |
1455 | int val = 1; | |
1456 | ||
1457 | if (cnt > 0) { | |
1458 | if (cnt > sizeof (buf) - 1) | |
1459 | return -EINVAL; | |
1460 | ||
1461 | if (copy_from_user(buf, ubuf, cnt)) | |
1462 | return -EFAULT; | |
1463 | buf[cnt] = 0; | |
1464 | ||
1465 | val = simple_strtoul(buf, NULL, 0); | |
1466 | } | |
1467 | ||
1468 | if (val < 0 || val > 3) | |
1469 | return -EINVAL; | |
1470 | ||
1471 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); | |
1472 | ||
1473 | /* Update the cache sharing policy here as well */ | |
1474 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1475 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1476 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1477 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1478 | ||
1479 | return cnt; | |
1480 | } | |
1481 | ||
1482 | static const struct file_operations i915_cache_sharing_fops = { | |
1483 | .owner = THIS_MODULE, | |
1484 | .open = i915_cache_sharing_open, | |
1485 | .read = i915_cache_sharing_read, | |
1486 | .write = i915_cache_sharing_write, | |
1487 | .llseek = default_llseek, | |
1488 | }; | |
1489 | ||
f3cd474b CW |
1490 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1491 | * allocated we need to hook into the minor for release. */ | |
1492 | static int | |
1493 | drm_add_fake_info_node(struct drm_minor *minor, | |
1494 | struct dentry *ent, | |
1495 | const void *key) | |
1496 | { | |
1497 | struct drm_info_node *node; | |
1498 | ||
1499 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
1500 | if (node == NULL) { | |
1501 | debugfs_remove(ent); | |
1502 | return -ENOMEM; | |
1503 | } | |
1504 | ||
1505 | node->minor = minor; | |
1506 | node->dent = ent; | |
1507 | node->info_ent = (void *) key; | |
1508 | list_add(&node->list, &minor->debugfs_nodes.list); | |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
1513 | static int i915_wedged_create(struct dentry *root, struct drm_minor *minor) | |
1514 | { | |
1515 | struct drm_device *dev = minor->dev; | |
1516 | struct dentry *ent; | |
1517 | ||
1518 | ent = debugfs_create_file("i915_wedged", | |
1519 | S_IRUGO | S_IWUSR, | |
1520 | root, dev, | |
1521 | &i915_wedged_fops); | |
1522 | if (IS_ERR(ent)) | |
1523 | return PTR_ERR(ent); | |
1524 | ||
1525 | return drm_add_fake_info_node(minor, ent, &i915_wedged_fops); | |
1526 | } | |
9e3a6d15 | 1527 | |
6d794d42 BW |
1528 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
1529 | { | |
1530 | struct drm_device *dev = inode->i_private; | |
1531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1532 | int ret; | |
1533 | ||
1534 | if (!IS_GEN6(dev)) | |
1535 | return 0; | |
1536 | ||
1537 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1538 | if (ret) | |
1539 | return ret; | |
1540 | gen6_gt_force_wake_get(dev_priv); | |
1541 | mutex_unlock(&dev->struct_mutex); | |
1542 | ||
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | int i915_forcewake_release(struct inode *inode, struct file *file) | |
1547 | { | |
1548 | struct drm_device *dev = inode->i_private; | |
1549 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1550 | ||
1551 | if (!IS_GEN6(dev)) | |
1552 | return 0; | |
1553 | ||
1554 | /* | |
1555 | * It's bad that we can potentially hang userspace if struct_mutex gets | |
1556 | * forever stuck. However, if we cannot acquire this lock it means that | |
1557 | * almost certainly the driver has hung, is not unload-able. Therefore | |
1558 | * hanging here is probably a minor inconvenience not to be seen my | |
1559 | * almost every user. | |
1560 | */ | |
1561 | mutex_lock(&dev->struct_mutex); | |
1562 | gen6_gt_force_wake_put(dev_priv); | |
1563 | mutex_unlock(&dev->struct_mutex); | |
1564 | ||
1565 | return 0; | |
1566 | } | |
1567 | ||
1568 | static const struct file_operations i915_forcewake_fops = { | |
1569 | .owner = THIS_MODULE, | |
1570 | .open = i915_forcewake_open, | |
1571 | .release = i915_forcewake_release, | |
1572 | }; | |
1573 | ||
1574 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
1575 | { | |
1576 | struct drm_device *dev = minor->dev; | |
1577 | struct dentry *ent; | |
1578 | ||
1579 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 1580 | S_IRUSR, |
6d794d42 BW |
1581 | root, dev, |
1582 | &i915_forcewake_fops); | |
1583 | if (IS_ERR(ent)) | |
1584 | return PTR_ERR(ent); | |
1585 | ||
8eb57294 | 1586 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
1587 | } |
1588 | ||
358733e9 JB |
1589 | static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor) |
1590 | { | |
1591 | struct drm_device *dev = minor->dev; | |
1592 | struct dentry *ent; | |
1593 | ||
1594 | ent = debugfs_create_file("i915_max_freq", | |
1595 | S_IRUGO | S_IWUSR, | |
1596 | root, dev, | |
1597 | &i915_max_freq_fops); | |
1598 | if (IS_ERR(ent)) | |
1599 | return PTR_ERR(ent); | |
1600 | ||
1601 | return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops); | |
1602 | } | |
1603 | ||
07b7ddd9 JB |
1604 | static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor) |
1605 | { | |
1606 | struct drm_device *dev = minor->dev; | |
1607 | struct dentry *ent; | |
1608 | ||
1609 | ent = debugfs_create_file("i915_cache_sharing", | |
1610 | S_IRUGO | S_IWUSR, | |
1611 | root, dev, | |
1612 | &i915_cache_sharing_fops); | |
1613 | if (IS_ERR(ent)) | |
1614 | return PTR_ERR(ent); | |
1615 | ||
1616 | return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops); | |
1617 | } | |
1618 | ||
27c202ad | 1619 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 1620 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 1621 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 1622 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
433e12f7 BG |
1623 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
1624 | {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, | |
1625 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, | |
f13d3f73 | 1626 | {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST}, |
d21d5975 | 1627 | {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST}, |
4e5359cd | 1628 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
1629 | {"i915_gem_request", i915_gem_request_info, 0}, |
1630 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 1631 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 1632 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
1633 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
1634 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
1635 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
1636 | {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS}, | |
1637 | {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS}, | |
1638 | {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS}, | |
1639 | {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS}, | |
1640 | {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS}, | |
1641 | {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS}, | |
6911a9b8 | 1642 | {"i915_batchbuffers", i915_batchbuffer_info, 0}, |
63eeaf38 | 1643 | {"i915_error_state", i915_error_state, 0}, |
f97108d1 JB |
1644 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
1645 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
1646 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
1647 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
1648 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 1649 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 1650 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 1651 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 1652 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 1653 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 1654 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 1655 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 1656 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 1657 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
2017263e | 1658 | }; |
27c202ad | 1659 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 1660 | |
27c202ad | 1661 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 1662 | { |
f3cd474b CW |
1663 | int ret; |
1664 | ||
1665 | ret = i915_wedged_create(minor->debugfs_root, minor); | |
1666 | if (ret) | |
1667 | return ret; | |
1668 | ||
6d794d42 | 1669 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
1670 | if (ret) |
1671 | return ret; | |
1672 | ret = i915_max_freq_create(minor->debugfs_root, minor); | |
07b7ddd9 JB |
1673 | if (ret) |
1674 | return ret; | |
1675 | ret = i915_cache_sharing_create(minor->debugfs_root, minor); | |
6d794d42 BW |
1676 | if (ret) |
1677 | return ret; | |
1678 | ||
27c202ad BG |
1679 | return drm_debugfs_create_files(i915_debugfs_list, |
1680 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
1681 | minor->debugfs_root, minor); |
1682 | } | |
1683 | ||
27c202ad | 1684 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 1685 | { |
27c202ad BG |
1686 | drm_debugfs_remove_files(i915_debugfs_list, |
1687 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
1688 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
1689 | 1, minor); | |
33db679b KH |
1690 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
1691 | 1, minor); | |
358733e9 JB |
1692 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
1693 | 1, minor); | |
07b7ddd9 JB |
1694 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
1695 | 1, minor); | |
2017263e BG |
1696 | } |
1697 | ||
1698 | #endif /* CONFIG_DEBUG_FS */ |