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drm/i915: Show pin mapped status in describe_obj
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
be12a86b 92static const char get_active_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
be12a86b 94 return obj->active ? '*' : ' ';
a6172a80
CW		 95}
96
be12a86b
TU		 97static const char get_pin_flag(struct drm_i915_gem_object *obj)
98{
99 return obj->pin_display ? 'p' : ' ';
100}
101
102static const char get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 103{
0206e353
AJ		 104 switch (obj->tiling_mode) {
105 default:
be12a86b
TU		 106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
0206e353 109 }
a6172a80
CW		 110}
111
be12a86b
TU		 112static inline const char get_global_flag(struct drm_i915_gem_object *obj)
113{
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115}
116
117static inline const char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
1d693bcc 118{
be12a86b 119 return obj->mapping ? 'M' : ' ';
1d693bcc
BW		 120}
121
ca1543be
TU		 122static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123{
124 u64 size = 0;
125 struct i915_vma *vma;
126
1c7f4bca 127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
596c5923 128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
ca1543be
TU		 129 size += vma->node.size;
130 }
131
132 return size;
133}
134
37811fcc
CW		 135static void
136describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137{
b4716185 138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
e2f80391 139 struct intel_engine_cs *engine;
1d693bcc 140 struct i915_vma *vma;
d7f46fc4 141 int pin_count = 0;
c3232b18 142 enum intel_engine_id id;
d7f46fc4 143
188c1ab7
CW		 144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
be12a86b 146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
37811fcc 147 &obj->base,
be12a86b 148 get_active_flag(obj),
37811fcc
CW		 149 get_pin_flag(obj),
150 get_tiling_flag(obj),
1d693bcc 151 get_global_flag(obj),
be12a86b 152 get_pin_mapped_flag(obj),
a05a5862 153 obj->base.size / 1024,
37811fcc 154 obj->base.read_domains,
b4716185 155 obj->base.write_domain);
c3232b18 156 for_each_engine_id(engine, dev_priv, id)
b4716185 157 seq_printf(m, "%x ",
c3232b18 158 i915_gem_request_get_seqno(obj->last_read_req[id]));
b4716185 159 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 160 i915_gem_request_get_seqno(obj->last_write_req),
161 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
1c7f4bca 167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
d7f46fc4
BW		 168 if (vma->pin_count > 0)
169 pin_count++;
ba0635ff
DC		 170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 172 if (obj->pin_display)
173 seq_printf(m, " (display)");
37811fcc
CW		 174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
1c7f4bca 176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
8d2fdc3f 177 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
596c5923 178 vma->is_ggtt ? "g" : "pp",
8d2fdc3f 179 vma->node.start, vma->node.size);
596c5923
CW		 180 if (vma->is_ggtt)
181 seq_printf(m, ", type: %u", vma->ggtt_view.type);
182 seq_puts(m, ")");
1d693bcc 183 }
c1ad11fc 184 if (obj->stolen)
440fd528 185 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 186 if (obj->pin_display || obj->fault_mappable) {
6299f992 187 char s[3], *t = s;
30154650 188 if (obj->pin_display)
6299f992
CW		 189 *t++ = 'p';
190 if (obj->fault_mappable)
191 *t++ = 'f';
192 *t = '\0';
193 seq_printf(m, " (%s mappable)", s);
194 }
b4716185 195 if (obj->last_write_req != NULL)
41c52415 196 seq_printf(m, " (%s)",
666796da 197 i915_gem_request_get_engine(obj->last_write_req)->name);
d5a81ef1
DV		 198 if (obj->frontbuffer_bits)
199 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 200}
201
273497e5 202static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 203{
ea0c76f8 204 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 205 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
206 seq_putc(m, ' ');
207}
208
433e12f7 209static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 210{
9f25d007 211 struct drm_info_node *node = m->private;
433e12f7
BG		 212 uintptr_t list = (uintptr_t) node->info_ent->data;
213 struct list_head *head;
2017263e 214 struct drm_device *dev = node->minor->dev;
72e96d64
JL		 215 struct drm_i915_private *dev_priv = to_i915(dev);
216 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ca191b13 217 struct i915_vma *vma;
c44ef60e 218 u64 total_obj_size, total_gtt_size;
8f2480fb 219 int count, ret;
de227ef0
CW		 220
221 ret = mutex_lock_interruptible(&dev->struct_mutex);
222 if (ret)
223 return ret;
2017263e 224
ca191b13 225 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 226 switch (list) {
227 case ACTIVE_LIST:
267f0c90 228 seq_puts(m, "Active:\n");
72e96d64 229 head = &ggtt->base.active_list;
433e12f7
BG		 230 break;
231 case INACTIVE_LIST:
267f0c90 232 seq_puts(m, "Inactive:\n");
72e96d64 233 head = &ggtt->base.inactive_list;
433e12f7 234 break;
433e12f7 235 default:
de227ef0
CW		 236 mutex_unlock(&dev->struct_mutex);
237 return -EINVAL;
2017263e 238 }
2017263e 239
8f2480fb 240 total_obj_size = total_gtt_size = count = 0;
1c7f4bca 241 list_for_each_entry(vma, head, vm_link) {
ca191b13
BW		 242 seq_printf(m, " ");
243 describe_obj(m, vma->obj);
244 seq_printf(m, "\n");
245 total_obj_size += vma->obj->base.size;
246 total_gtt_size += vma->node.size;
8f2480fb 247 count++;
2017263e 248 }
de227ef0 249 mutex_unlock(&dev->struct_mutex);
5e118f41 250
c44ef60e 251 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 252 count, total_obj_size, total_gtt_size);
2017263e
BG		 253 return 0;
254}
255
6d2b8885
CW		 256static int obj_rank_by_stolen(void *priv,
257 struct list_head *A, struct list_head *B)
258{
259 struct drm_i915_gem_object *a =
b25cb2f8 260 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 261 struct drm_i915_gem_object *b =
b25cb2f8 262 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 263
2d05fa16
RV		 264 if (a->stolen->start < b->stolen->start)
265 return -1;
266 if (a->stolen->start > b->stolen->start)
267 return 1;
268 return 0;
6d2b8885
CW		 269}
270
271static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
272{
9f25d007 273 struct drm_info_node *node = m->private;
6d2b8885
CW		 274 struct drm_device *dev = node->minor->dev;
275 struct drm_i915_private *dev_priv = dev->dev_private;
276 struct drm_i915_gem_object *obj;
c44ef60e 277 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 278 LIST_HEAD(stolen);
279 int count, ret;
280
281 ret = mutex_lock_interruptible(&dev->struct_mutex);
282 if (ret)
283 return ret;
284
285 total_obj_size = total_gtt_size = count = 0;
286 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
287 if (obj->stolen == NULL)
288 continue;
289
b25cb2f8 290 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 291
292 total_obj_size += obj->base.size;
ca1543be 293 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 294 count++;
295 }
296 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
297 if (obj->stolen == NULL)
298 continue;
299
b25cb2f8 300 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 301
302 total_obj_size += obj->base.size;
303 count++;
304 }
305 list_sort(NULL, &stolen, obj_rank_by_stolen);
306 seq_puts(m, "Stolen:\n");
307 while (!list_empty(&stolen)) {
b25cb2f8 308 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 309 seq_puts(m, " ");
310 describe_obj(m, obj);
311 seq_putc(m, '\n');
b25cb2f8 312 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 313 }
314 mutex_unlock(&dev->struct_mutex);
315
c44ef60e 316 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 317 count, total_obj_size, total_gtt_size);
318 return 0;
319}
320
6299f992
CW		 321#define count_objects(list, member) do { \
322 list_for_each_entry(obj, list, member) { \
ca1543be 323 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 324 ++count; \
325 if (obj->map_and_fenceable) { \
f343c5f6 326 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 327 ++mappable_count; \
328 } \
329 } \
0206e353 330} while (0)
6299f992 331
2db8e9d6 332struct file_stats {
6313c204 333 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 334 unsigned long count;
335 u64 total, unbound;
336 u64 global, shared;
337 u64 active, inactive;
2db8e9d6
CW		 338};
339
340static int per_file_stats(int id, void *ptr, void *data)
341{
342 struct drm_i915_gem_object *obj = ptr;
343 struct file_stats *stats = data;
6313c204 344 struct i915_vma *vma;
2db8e9d6
CW		 345
346 stats->count++;
347 stats->total += obj->base.size;
348
c67a17e9
CW		 349 if (obj->base.name || obj->base.dma_buf)
350 stats->shared += obj->base.size;
351
6313c204 352 if (USES_FULL_PPGTT(obj->base.dev)) {
1c7f4bca 353 list_for_each_entry(vma, &obj->vma_list, obj_link) {
6313c204
CW		 354 struct i915_hw_ppgtt *ppgtt;
355
356 if (!drm_mm_node_allocated(&vma->node))
357 continue;
358
596c5923 359 if (vma->is_ggtt) {
6313c204
CW		 360 stats->global += obj->base.size;
361 continue;
362 }
363
364 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 365 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 366 continue;
367
41c52415 368 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 369 stats->active += obj->base.size;
370 else
371 stats->inactive += obj->base.size;
372
373 return 0;
374 }
2db8e9d6 375 } else {
6313c204
CW		 376 if (i915_gem_obj_ggtt_bound(obj)) {
377 stats->global += obj->base.size;
41c52415 378 if (obj->active)
6313c204
CW		 379 stats->active += obj->base.size;
380 else
381 stats->inactive += obj->base.size;
382 return 0;
383 }
2db8e9d6
CW		 384 }
385
6313c204
CW		 386 if (!list_empty(&obj->global_list))
387 stats->unbound += obj->base.size;
388
2db8e9d6
CW		 389 return 0;
390}
391
b0da1b79
CW		 392#define print_file_stats(m, name, stats) do { \
393 if (stats.count) \
c44ef60e 394 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 395 name, \
396 stats.count, \
397 stats.total, \
398 stats.active, \
399 stats.inactive, \
400 stats.global, \
401 stats.shared, \
402 stats.unbound); \
403} while (0)
493018dc
BV		 404
405static void print_batch_pool_stats(struct seq_file *m,
406 struct drm_i915_private *dev_priv)
407{
408 struct drm_i915_gem_object *obj;
409 struct file_stats stats;
e2f80391 410 struct intel_engine_cs *engine;
b4ac5afc 411 int j;
493018dc
BV		 412
413 memset(&stats, 0, sizeof(stats));
414
b4ac5afc 415 for_each_engine(engine, dev_priv) {
e2f80391 416 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744 417 list_for_each_entry(obj,
e2f80391 418 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 419 batch_pool_link)
420 per_file_stats(0, obj, &stats);
421 }
06fbca71 422 }
493018dc 423
b0da1b79 424 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 425}
426
ca191b13
BW		 427#define count_vmas(list, member) do { \
428 list_for_each_entry(vma, list, member) { \
ca1543be 429 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 430 ++count; \
431 if (vma->obj->map_and_fenceable) { \
432 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
433 ++mappable_count; \
434 } \
435 } \
436} while (0)
437
438static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 439{
9f25d007 440 struct drm_info_node *node = m->private;
73aa808f 441 struct drm_device *dev = node->minor->dev;
72e96d64
JL		 442 struct drm_i915_private *dev_priv = to_i915(dev);
443 struct i915_ggtt *ggtt = &dev_priv->ggtt;
b7abb714 444 u32 count, mappable_count, purgeable_count;
c44ef60e 445 u64 size, mappable_size, purgeable_size;
6299f992 446 struct drm_i915_gem_object *obj;
2db8e9d6 447 struct drm_file *file;
ca191b13 448 struct i915_vma *vma;
73aa808f
CW		 449 int ret;
450
451 ret = mutex_lock_interruptible(&dev->struct_mutex);
452 if (ret)
453 return ret;
454
6299f992
CW		 455 seq_printf(m, "%u objects, %zu bytes\n",
456 dev_priv->mm.object_count,
457 dev_priv->mm.object_memory);
458
459 size = count = mappable_size = mappable_count = 0;
35c20a60 460 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 461 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 462 count, mappable_count, size, mappable_size);
463
464 size = count = mappable_size = mappable_count = 0;
72e96d64 465 count_vmas(&ggtt->base.active_list, vm_link);
c44ef60e 466 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 467 count, mappable_count, size, mappable_size);
468
6299f992 469 size = count = mappable_size = mappable_count = 0;
72e96d64 470 count_vmas(&ggtt->base.inactive_list, vm_link);
c44ef60e 471 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 472 count, mappable_count, size, mappable_size);
473
b7abb714 474 size = count = purgeable_size = purgeable_count = 0;
35c20a60 475 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 476 size += obj->base.size, ++count;
b7abb714
CW		 477 if (obj->madv == I915_MADV_DONTNEED)
478 purgeable_size += obj->base.size, ++purgeable_count;
479 }
c44ef60e 480 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 481
6299f992 482 size = count = mappable_size = mappable_count = 0;
35c20a60 483 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 484 if (obj->fault_mappable) {
f343c5f6 485 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 486 ++count;
487 }
30154650 488 if (obj->pin_display) {
f343c5f6 489 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 490 ++mappable_count;
491 }
b7abb714
CW		 492 if (obj->madv == I915_MADV_DONTNEED) {
493 purgeable_size += obj->base.size;
494 ++purgeable_count;
495 }
6299f992 496 }
c44ef60e 497 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 498 purgeable_count, purgeable_size);
c44ef60e 499 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 500 mappable_count, mappable_size);
c44ef60e 501 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 502 count, size);
503
c44ef60e 504 seq_printf(m, "%llu [%llu] gtt total\n",
72e96d64 505 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
73aa808f 506
493018dc
BV		 507 seq_putc(m, '\n');
508 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 509 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
510 struct file_stats stats;
3ec2f427 511 struct task_struct *task;
2db8e9d6
CW		 512
513 memset(&stats, 0, sizeof(stats));
6313c204 514 stats.file_priv = file->driver_priv;
5b5ffff0 515 spin_lock(&file->table_lock);
2db8e9d6 516 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 517 spin_unlock(&file->table_lock);
3ec2f427
TH		 518 /*
519 * Although we have a valid reference on file->pid, that does
520 * not guarantee that the task_struct who called get_pid() is
521 * still alive (e.g. get_pid(current) => fork() => exit()).
522 * Therefore, we need to protect this ->comm access using RCU.
523 */
524 rcu_read_lock();
525 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 526 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 527 rcu_read_unlock();
2db8e9d6
CW		 528 }
529
73aa808f
CW		 530 mutex_unlock(&dev->struct_mutex);
531
532 return 0;
533}
534
aee56cff 535static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 536{
9f25d007 537 struct drm_info_node *node = m->private;
08c18323 538 struct drm_device *dev = node->minor->dev;
1b50247a 539 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 540 struct drm_i915_private *dev_priv = dev->dev_private;
541 struct drm_i915_gem_object *obj;
c44ef60e 542 u64 total_obj_size, total_gtt_size;
08c18323
CW		 543 int count, ret;
544
545 ret = mutex_lock_interruptible(&dev->struct_mutex);
546 if (ret)
547 return ret;
548
549 total_obj_size = total_gtt_size = count = 0;
35c20a60 550 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 551 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 552 continue;
553
267f0c90 554 seq_puts(m, " ");
08c18323 555 describe_obj(m, obj);
267f0c90 556 seq_putc(m, '\n');
08c18323 557 total_obj_size += obj->base.size;
ca1543be 558 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 559 count++;
560 }
561
562 mutex_unlock(&dev->struct_mutex);
563
c44ef60e 564 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 565 count, total_obj_size, total_gtt_size);
566
567 return 0;
568}
569
4e5359cd
SF		 570static int i915_gem_pageflip_info(struct seq_file *m, void *data)
571{
9f25d007 572 struct drm_info_node *node = m->private;
4e5359cd 573 struct drm_device *dev = node->minor->dev;
d6bbafa1 574 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 575 struct intel_crtc *crtc;
8a270ebf
DV		 576 int ret;
577
578 ret = mutex_lock_interruptible(&dev->struct_mutex);
579 if (ret)
580 return ret;
4e5359cd 581
d3fcc808 582 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 583 const char pipe = pipe_name(crtc->pipe);
584 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 585 struct intel_unpin_work *work;
586
5e2d7afc 587 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 588 work = crtc->unpin_work;
589 if (work == NULL) {
9db4a9c7 590 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 591 pipe, plane);
592 } else {
d6bbafa1
CW		 593 u32 addr;
594
e7d841ca 595 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 596 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 597 pipe, plane);
598 } else {
9db4a9c7 599 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 600 pipe, plane);
601 }
3a8a946e 602 if (work->flip_queued_req) {
666796da 603 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
3a8a946e 604
20e28fba 605 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
e2f80391 606 engine->name,
f06cc1b9 607 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 608 dev_priv->next_seqno,
c04e0f3b 609 engine->get_seqno(engine),
1b5a433a 610 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 611 } else
612 seq_printf(m, "Flip not associated with any ring\n");
613 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
614 work->flip_queued_vblank,
615 work->flip_ready_vblank,
1e3feefd 616 drm_crtc_vblank_count(&crtc->base));
4e5359cd 617 if (work->enable_stall_check)
267f0c90 618 seq_puts(m, "Stall check enabled, ");
4e5359cd 619 else
267f0c90 620 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 621 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 622
d6bbafa1
CW		 623 if (INTEL_INFO(dev)->gen >= 4)
624 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
625 else
626 addr = I915_READ(DSPADDR(crtc->plane));
627 seq_printf(m, "Current scanout address 0x%08x\n", addr);
628
4e5359cd 629 if (work->pending_flip_obj) {
d6bbafa1
CW		 630 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
631 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 632 }
633 }
5e2d7afc 634 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 635 }
636
8a270ebf
DV		 637 mutex_unlock(&dev->struct_mutex);
638
4e5359cd
SF		 639 return 0;
640}
641
493018dc
BV		 642static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
643{
644 struct drm_info_node *node = m->private;
645 struct drm_device *dev = node->minor->dev;
646 struct drm_i915_private *dev_priv = dev->dev_private;
647 struct drm_i915_gem_object *obj;
e2f80391 648 struct intel_engine_cs *engine;
8d9d5744 649 int total = 0;
b4ac5afc 650 int ret, j;
493018dc
BV		 651
652 ret = mutex_lock_interruptible(&dev->struct_mutex);
653 if (ret)
654 return ret;
655
b4ac5afc 656 for_each_engine(engine, dev_priv) {
e2f80391 657 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744
CW		 658 int count;
659
660 count = 0;
661 list_for_each_entry(obj,
e2f80391 662 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 663 batch_pool_link)
664 count++;
665 seq_printf(m, "%s cache[%d]: %d objects\n",
e2f80391 666 engine->name, j, count);
8d9d5744
CW		 667
668 list_for_each_entry(obj,
e2f80391 669 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 670 batch_pool_link) {
671 seq_puts(m, " ");
672 describe_obj(m, obj);
673 seq_putc(m, '\n');
674 }
675
676 total += count;
06fbca71 677 }
493018dc
BV		 678 }
679
8d9d5744 680 seq_printf(m, "total: %d\n", total);
493018dc
BV		 681
682 mutex_unlock(&dev->struct_mutex);
683
684 return 0;
685}
686
2017263e
BG		 687static int i915_gem_request_info(struct seq_file *m, void *data)
688{
9f25d007 689 struct drm_info_node *node = m->private;
2017263e 690 struct drm_device *dev = node->minor->dev;
e277a1f8 691 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 692 struct intel_engine_cs *engine;
eed29a5b 693 struct drm_i915_gem_request *req;
b4ac5afc 694 int ret, any;
de227ef0
CW		 695
696 ret = mutex_lock_interruptible(&dev->struct_mutex);
697 if (ret)
698 return ret;
2017263e 699
2d1070b2 700 any = 0;
b4ac5afc 701 for_each_engine(engine, dev_priv) {
2d1070b2
CW		 702 int count;
703
704 count = 0;
e2f80391 705 list_for_each_entry(req, &engine->request_list, list)
2d1070b2
CW		 706 count++;
707 if (count == 0)
a2c7f6fd
CW		 708 continue;
709
e2f80391
TU		 710 seq_printf(m, "%s requests: %d\n", engine->name, count);
711 list_for_each_entry(req, &engine->request_list, list) {
2d1070b2
CW		 712 struct task_struct *task;
713
714 rcu_read_lock();
715 task = NULL;
eed29a5b
DV		 716 if (req->pid)
717 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 718 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 719 req->seqno,
720 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 721 task ? task->comm : "<unknown>",
722 task ? task->pid : -1);
723 rcu_read_unlock();
c2c347a9 724 }
2d1070b2
CW		 725
726 any++;
2017263e 727 }
de227ef0
CW		 728 mutex_unlock(&dev->struct_mutex);
729
2d1070b2 730 if (any == 0)
267f0c90 731 seq_puts(m, "No requests\n");
c2c347a9 732
2017263e
BG		 733 return 0;
734}
735
b2223497 736static void i915_ring_seqno_info(struct seq_file *m,
0bc40be8 737 struct intel_engine_cs *engine)
b2223497 738{
12471ba8
CW		 739 seq_printf(m, "Current sequence (%s): %x\n",
740 engine->name, engine->get_seqno(engine));
741 seq_printf(m, "Current user interrupts (%s): %x\n",
742 engine->name, READ_ONCE(engine->user_interrupts));
b2223497
CW		 743}
744
2017263e
BG		 745static int i915_gem_seqno_info(struct seq_file *m, void *data)
746{
9f25d007 747 struct drm_info_node *node = m->private;
2017263e 748 struct drm_device *dev = node->minor->dev;
e277a1f8 749 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 750 struct intel_engine_cs *engine;
b4ac5afc 751 int ret;
de227ef0
CW		 752
753 ret = mutex_lock_interruptible(&dev->struct_mutex);
754 if (ret)
755 return ret;
c8c8fb33 756 intel_runtime_pm_get(dev_priv);
2017263e 757
b4ac5afc 758 for_each_engine(engine, dev_priv)
e2f80391 759 i915_ring_seqno_info(m, engine);
de227ef0 760
c8c8fb33 761 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 762 mutex_unlock(&dev->struct_mutex);
763
2017263e
BG		 764 return 0;
765}
766
767
768static int i915_interrupt_info(struct seq_file *m, void *data)
769{
9f25d007 770 struct drm_info_node *node = m->private;
2017263e 771 struct drm_device *dev = node->minor->dev;
e277a1f8 772 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 773 struct intel_engine_cs *engine;
9db4a9c7 774 int ret, i, pipe;
de227ef0
CW		 775
776 ret = mutex_lock_interruptible(&dev->struct_mutex);
777 if (ret)
778 return ret;
c8c8fb33 779 intel_runtime_pm_get(dev_priv);
2017263e 780
74e1ca8c 781 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 782 seq_printf(m, "Master Interrupt Control:\t%08x\n",
783 I915_READ(GEN8_MASTER_IRQ));
784
785 seq_printf(m, "Display IER:\t%08x\n",
786 I915_READ(VLV_IER));
787 seq_printf(m, "Display IIR:\t%08x\n",
788 I915_READ(VLV_IIR));
789 seq_printf(m, "Display IIR_RW:\t%08x\n",
790 I915_READ(VLV_IIR_RW));
791 seq_printf(m, "Display IMR:\t%08x\n",
792 I915_READ(VLV_IMR));
055e393f 793 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 794 seq_printf(m, "Pipe %c stat:\t%08x\n",
795 pipe_name(pipe),
796 I915_READ(PIPESTAT(pipe)));
797
798 seq_printf(m, "Port hotplug:\t%08x\n",
799 I915_READ(PORT_HOTPLUG_EN));
800 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
801 I915_READ(VLV_DPFLIPSTAT));
802 seq_printf(m, "DPINVGTT:\t%08x\n",
803 I915_READ(DPINVGTT));
804
805 for (i = 0; i < 4; i++) {
806 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
807 i, I915_READ(GEN8_GT_IMR(i)));
808 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
809 i, I915_READ(GEN8_GT_IIR(i)));
810 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
811 i, I915_READ(GEN8_GT_IER(i)));
812 }
813
814 seq_printf(m, "PCU interrupt mask:\t%08x\n",
815 I915_READ(GEN8_PCU_IMR));
816 seq_printf(m, "PCU interrupt identity:\t%08x\n",
817 I915_READ(GEN8_PCU_IIR));
818 seq_printf(m, "PCU interrupt enable:\t%08x\n",
819 I915_READ(GEN8_PCU_IER));
820 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 821 seq_printf(m, "Master Interrupt Control:\t%08x\n",
822 I915_READ(GEN8_MASTER_IRQ));
823
824 for (i = 0; i < 4; i++) {
825 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
826 i, I915_READ(GEN8_GT_IMR(i)));
827 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
828 i, I915_READ(GEN8_GT_IIR(i)));
829 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
830 i, I915_READ(GEN8_GT_IER(i)));
831 }
832
055e393f 833 for_each_pipe(dev_priv, pipe) {
e129649b
ID		 834 enum intel_display_power_domain power_domain;
835
836 power_domain = POWER_DOMAIN_PIPE(pipe);
837 if (!intel_display_power_get_if_enabled(dev_priv,
838 power_domain)) {
22c59960
PZ		 839 seq_printf(m, "Pipe %c power disabled\n",
840 pipe_name(pipe));
841 continue;
842 }
a123f157 843 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 844 pipe_name(pipe),
845 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 846 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 847 pipe_name(pipe),
848 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 849 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 850 pipe_name(pipe),
851 I915_READ(GEN8_DE_PIPE_IER(pipe)));
e129649b
ID		 852
853 intel_display_power_put(dev_priv, power_domain);
a123f157
BW		 854 }
855
856 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
857 I915_READ(GEN8_DE_PORT_IMR));
858 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
859 I915_READ(GEN8_DE_PORT_IIR));
860 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
861 I915_READ(GEN8_DE_PORT_IER));
862
863 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
864 I915_READ(GEN8_DE_MISC_IMR));
865 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
866 I915_READ(GEN8_DE_MISC_IIR));
867 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
868 I915_READ(GEN8_DE_MISC_IER));
869
870 seq_printf(m, "PCU interrupt mask:\t%08x\n",
871 I915_READ(GEN8_PCU_IMR));
872 seq_printf(m, "PCU interrupt identity:\t%08x\n",
873 I915_READ(GEN8_PCU_IIR));
874 seq_printf(m, "PCU interrupt enable:\t%08x\n",
875 I915_READ(GEN8_PCU_IER));
876 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 877 seq_printf(m, "Display IER:\t%08x\n",
878 I915_READ(VLV_IER));
879 seq_printf(m, "Display IIR:\t%08x\n",
880 I915_READ(VLV_IIR));
881 seq_printf(m, "Display IIR_RW:\t%08x\n",
882 I915_READ(VLV_IIR_RW));
883 seq_printf(m, "Display IMR:\t%08x\n",
884 I915_READ(VLV_IMR));
055e393f 885 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 886 seq_printf(m, "Pipe %c stat:\t%08x\n",
887 pipe_name(pipe),
888 I915_READ(PIPESTAT(pipe)));
889
890 seq_printf(m, "Master IER:\t%08x\n",
891 I915_READ(VLV_MASTER_IER));
892
893 seq_printf(m, "Render IER:\t%08x\n",
894 I915_READ(GTIER));
895 seq_printf(m, "Render IIR:\t%08x\n",
896 I915_READ(GTIIR));
897 seq_printf(m, "Render IMR:\t%08x\n",
898 I915_READ(GTIMR));
899
900 seq_printf(m, "PM IER:\t\t%08x\n",
901 I915_READ(GEN6_PMIER));
902 seq_printf(m, "PM IIR:\t\t%08x\n",
903 I915_READ(GEN6_PMIIR));
904 seq_printf(m, "PM IMR:\t\t%08x\n",
905 I915_READ(GEN6_PMIMR));
906
907 seq_printf(m, "Port hotplug:\t%08x\n",
908 I915_READ(PORT_HOTPLUG_EN));
909 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
910 I915_READ(VLV_DPFLIPSTAT));
911 seq_printf(m, "DPINVGTT:\t%08x\n",
912 I915_READ(DPINVGTT));
913
914 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 915 seq_printf(m, "Interrupt enable: %08x\n",
916 I915_READ(IER));
917 seq_printf(m, "Interrupt identity: %08x\n",
918 I915_READ(IIR));
919 seq_printf(m, "Interrupt mask: %08x\n",
920 I915_READ(IMR));
055e393f 921 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 922 seq_printf(m, "Pipe %c stat: %08x\n",
923 pipe_name(pipe),
924 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 925 } else {
926 seq_printf(m, "North Display Interrupt enable: %08x\n",
927 I915_READ(DEIER));
928 seq_printf(m, "North Display Interrupt identity: %08x\n",
929 I915_READ(DEIIR));
930 seq_printf(m, "North Display Interrupt mask: %08x\n",
931 I915_READ(DEIMR));
932 seq_printf(m, "South Display Interrupt enable: %08x\n",
933 I915_READ(SDEIER));
934 seq_printf(m, "South Display Interrupt identity: %08x\n",
935 I915_READ(SDEIIR));
936 seq_printf(m, "South Display Interrupt mask: %08x\n",
937 I915_READ(SDEIMR));
938 seq_printf(m, "Graphics Interrupt enable: %08x\n",
939 I915_READ(GTIER));
940 seq_printf(m, "Graphics Interrupt identity: %08x\n",
941 I915_READ(GTIIR));
942 seq_printf(m, "Graphics Interrupt mask: %08x\n",
943 I915_READ(GTIMR));
944 }
b4ac5afc 945 for_each_engine(engine, dev_priv) {
a123f157 946 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 947 seq_printf(m,
948 "Graphics Interrupt mask (%s): %08x\n",
e2f80391 949 engine->name, I915_READ_IMR(engine));
9862e600 950 }
e2f80391 951 i915_ring_seqno_info(m, engine);
9862e600 952 }
c8c8fb33 953 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 954 mutex_unlock(&dev->struct_mutex);
955
2017263e
BG		 956 return 0;
957}
958
a6172a80
CW		 959static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
960{
9f25d007 961 struct drm_info_node *node = m->private;
a6172a80 962 struct drm_device *dev = node->minor->dev;
e277a1f8 963 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 964 int i, ret;
965
966 ret = mutex_lock_interruptible(&dev->struct_mutex);
967 if (ret)
968 return ret;
a6172a80 969
a6172a80
CW		 970 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
971 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 972 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 973
6c085a72
CW		 974 seq_printf(m, "Fence %d, pin count = %d, object = ",
975 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 976 if (obj == NULL)
267f0c90 977 seq_puts(m, "unused");
c2c347a9 978 else
05394f39 979 describe_obj(m, obj);
267f0c90 980 seq_putc(m, '\n');
a6172a80
CW		 981 }
982
05394f39 983 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 984 return 0;
985}
986
2017263e
BG		 987static int i915_hws_info(struct seq_file *m, void *data)
988{
9f25d007 989 struct drm_info_node *node = m->private;
2017263e 990 struct drm_device *dev = node->minor->dev;
e277a1f8 991 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 992 struct intel_engine_cs *engine;
1a240d4d 993 const u32 *hws;
4066c0ae
CW		 994 int i;
995
4a570db5 996 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
e2f80391 997 hws = engine->status_page.page_addr;
2017263e
BG		 998 if (hws == NULL)
999 return 0;
1000
1001 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1002 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1003 i * 4,
1004 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1005 }
1006 return 0;
1007}
1008
d5442303
DV		 1009static ssize_t
1010i915_error_state_write(struct file *filp,
1011 const char __user *ubuf,
1012 size_t cnt,
1013 loff_t *ppos)
1014{
edc3d884 1015 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1016 struct drm_device *dev = error_priv->dev;
22bcfc6a 1017 int ret;
d5442303
DV		 1018
1019 DRM_DEBUG_DRIVER("Resetting error state\n");
1020
22bcfc6a
DV		 1021 ret = mutex_lock_interruptible(&dev->struct_mutex);
1022 if (ret)
1023 return ret;
1024
d5442303
DV		 1025 i915_destroy_error_state(dev);
1026 mutex_unlock(&dev->struct_mutex);
1027
1028 return cnt;
1029}
1030
1031static int i915_error_state_open(struct inode *inode, struct file *file)
1032{
1033 struct drm_device *dev = inode->i_private;
d5442303 1034 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1035
1036 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1037 if (!error_priv)
1038 return -ENOMEM;
1039
1040 error_priv->dev = dev;
1041
95d5bfb3 1042 i915_error_state_get(dev, error_priv);
d5442303 1043
edc3d884
MK		 1044 file->private_data = error_priv;
1045
1046 return 0;
d5442303
DV		 1047}
1048
1049static int i915_error_state_release(struct inode *inode, struct file *file)
1050{
edc3d884 1051 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1052
95d5bfb3 1053 i915_error_state_put(error_priv);
d5442303
DV		 1054 kfree(error_priv);
1055
edc3d884
MK		 1056 return 0;
1057}
1058
4dc955f7
MK		 1059static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1060 size_t count, loff_t *pos)
1061{
1062 struct i915_error_state_file_priv *error_priv = file->private_data;
1063 struct drm_i915_error_state_buf error_str;
1064 loff_t tmp_pos = 0;
1065 ssize_t ret_count = 0;
1066 int ret;
1067
0a4cd7c8 1068 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1069 if (ret)
1070 return ret;
edc3d884 1071
fc16b48b 1072 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1073 if (ret)
1074 goto out;
1075
edc3d884
MK		 1076 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1077 error_str.buf,
1078 error_str.bytes);
1079
1080 if (ret_count < 0)
1081 ret = ret_count;
1082 else
1083 *pos = error_str.start + ret_count;
1084out:
4dc955f7 1085 i915_error_state_buf_release(&error_str);
edc3d884 1086 return ret ?: ret_count;
d5442303
DV		 1087}
1088
1089static const struct file_operations i915_error_state_fops = {
1090 .owner = THIS_MODULE,
1091 .open = i915_error_state_open,
edc3d884 1092 .read = i915_error_state_read,
d5442303
DV		 1093 .write = i915_error_state_write,
1094 .llseek = default_llseek,
1095 .release = i915_error_state_release,
1096};
1097
647416f9
KC		 1098static int
1099i915_next_seqno_get(void *data, u64 *val)
40633219 1100{
647416f9 1101 struct drm_device *dev = data;
e277a1f8 1102 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1103 int ret;
1104
1105 ret = mutex_lock_interruptible(&dev->struct_mutex);
1106 if (ret)
1107 return ret;
1108
647416f9 1109 *val = dev_priv->next_seqno;
40633219
MK		 1110 mutex_unlock(&dev->struct_mutex);
1111
647416f9 1112 return 0;
40633219
MK		 1113}
1114
647416f9
KC		 1115static int
1116i915_next_seqno_set(void *data, u64 val)
1117{
1118 struct drm_device *dev = data;
40633219
MK		 1119 int ret;
1120
40633219
MK		 1121 ret = mutex_lock_interruptible(&dev->struct_mutex);
1122 if (ret)
1123 return ret;
1124
e94fbaa8 1125 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1126 mutex_unlock(&dev->struct_mutex);
1127
647416f9 1128 return ret;
40633219
MK		 1129}
1130
647416f9
KC		 1131DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1132 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1133 "0x%llx\n");
40633219 1134
adb4bd12 1135static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1136{
9f25d007 1137 struct drm_info_node *node = m->private;
f97108d1 1138 struct drm_device *dev = node->minor->dev;
e277a1f8 1139 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1140 int ret = 0;
1141
1142 intel_runtime_pm_get(dev_priv);
3b8d8d91 1143
5c9669ce
TR		 1144 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1145
3b8d8d91
JB		 1146 if (IS_GEN5(dev)) {
1147 u16 rgvswctl = I915_READ16(MEMSWCTL);
1148 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1149
1150 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1151 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1152 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1153 MEMSTAT_VID_SHIFT);
1154 seq_printf(m, "Current P-state: %d\n",
1155 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
666a4537
WB		 1156 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1157 u32 freq_sts;
1158
1159 mutex_lock(&dev_priv->rps.hw_lock);
1160 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1161 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1162 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1163
1164 seq_printf(m, "actual GPU freq: %d MHz\n",
1165 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1166
1167 seq_printf(m, "current GPU freq: %d MHz\n",
1168 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1169
1170 seq_printf(m, "max GPU freq: %d MHz\n",
1171 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1172
1173 seq_printf(m, "min GPU freq: %d MHz\n",
1174 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1175
1176 seq_printf(m, "idle GPU freq: %d MHz\n",
1177 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1178
1179 seq_printf(m,
1180 "efficient (RPe) frequency: %d MHz\n",
1181 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1182 mutex_unlock(&dev_priv->rps.hw_lock);
1183 } else if (INTEL_INFO(dev)->gen >= 6) {
35040562
BP		 1184 u32 rp_state_limits;
1185 u32 gt_perf_status;
1186 u32 rp_state_cap;
0d8f9491 1187 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1188 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1189 u32 rpupei, rpcurup, rpprevup;
1190 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1191 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1192 int max_freq;
1193
35040562
BP		 1194 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1195 if (IS_BROXTON(dev)) {
1196 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1197 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1198 } else {
1199 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1200 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1201 }
1202
3b8d8d91 1203 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1204 ret = mutex_lock_interruptible(&dev->struct_mutex);
1205 if (ret)
c8c8fb33 1206 goto out;
d1ebd816 1207
59bad947 1208 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1209
8e8c06cd 1210 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1211 if (IS_GEN9(dev))
1212 reqf >>= 23;
1213 else {
1214 reqf &= ~GEN6_TURBO_DISABLE;
1215 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1216 reqf >>= 24;
1217 else
1218 reqf >>= 25;
1219 }
7c59a9c1 1220 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1221
0d8f9491
CW		 1222 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1223 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1224 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1225
ccab5c82
JB		 1226 rpstat = I915_READ(GEN6_RPSTAT1);
1227 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1228 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1229 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1230 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1231 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1232 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1233 if (IS_GEN9(dev))
1234 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1235 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1236 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1237 else
1238 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1239 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1240
59bad947 1241 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1242 mutex_unlock(&dev->struct_mutex);
1243
9dd3c605
PZ		 1244 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1245 pm_ier = I915_READ(GEN6_PMIER);
1246 pm_imr = I915_READ(GEN6_PMIMR);
1247 pm_isr = I915_READ(GEN6_PMISR);
1248 pm_iir = I915_READ(GEN6_PMIIR);
1249 pm_mask = I915_READ(GEN6_PMINTRMSK);
1250 } else {
1251 pm_ier = I915_READ(GEN8_GT_IER(2));
1252 pm_imr = I915_READ(GEN8_GT_IMR(2));
1253 pm_isr = I915_READ(GEN8_GT_ISR(2));
1254 pm_iir = I915_READ(GEN8_GT_IIR(2));
1255 pm_mask = I915_READ(GEN6_PMINTRMSK);
1256 }
0d8f9491 1257 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1258 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1259 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1260 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1261 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1262 seq_printf(m, "Render p-state VID: %d\n",
1263 gt_perf_status & 0xff);
1264 seq_printf(m, "Render p-state limit: %d\n",
1265 rp_state_limits & 0xff);
0d8f9491
CW		 1266 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1267 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1268 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1269 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1270 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1271 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1272 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1273 GEN6_CURICONT_MASK);
1274 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1275 GEN6_CURBSYTAVG_MASK);
1276 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1277 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1278 seq_printf(m, "Up threshold: %d%%\n",
1279 dev_priv->rps.up_threshold);
1280
ccab5c82
JB		 1281 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1282 GEN6_CURIAVG_MASK);
1283 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1284 GEN6_CURBSYTAVG_MASK);
1285 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1286 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1287 seq_printf(m, "Down threshold: %d%%\n",
1288 dev_priv->rps.down_threshold);
3b8d8d91 1289
35040562
BP		 1290 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1291 rp_state_cap >> 16) & 0xff;
ef11bdb3
RV		 1292 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1293 GEN9_FREQ_SCALER : 1);
3b8d8d91 1294 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1295 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1296
1297 max_freq = (rp_state_cap & 0xff00) >> 8;
ef11bdb3
RV		 1298 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1299 GEN9_FREQ_SCALER : 1);
3b8d8d91 1300 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1301 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1302
35040562
BP		 1303 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1304 rp_state_cap >> 0) & 0xff;
ef11bdb3
RV		 1305 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1306 GEN9_FREQ_SCALER : 1);
3b8d8d91 1307 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1308 intel_gpu_freq(dev_priv, max_freq));
31c77388 1309 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1310 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1311
d86ed34a
CW		 1312 seq_printf(m, "Current freq: %d MHz\n",
1313 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1314 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1315 seq_printf(m, "Idle freq: %d MHz\n",
1316 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1317 seq_printf(m, "Min freq: %d MHz\n",
1318 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1319 seq_printf(m, "Max freq: %d MHz\n",
1320 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1321 seq_printf(m,
1322 "efficient (RPe) frequency: %d MHz\n",
1323 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
3b8d8d91 1324 } else {
267f0c90 1325 seq_puts(m, "no P-state info available\n");
3b8d8d91 1326 }
f97108d1 1327
1170f28c
MK		 1328 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1329 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1330 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1331
c8c8fb33
PZ		 1332out:
1333 intel_runtime_pm_put(dev_priv);
1334 return ret;
f97108d1
JB		 1335}
1336
f654449a
CW		 1337static int i915_hangcheck_info(struct seq_file *m, void *unused)
1338{
1339 struct drm_info_node *node = m->private;
ebbc7546
MK		 1340 struct drm_device *dev = node->minor->dev;
1341 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1342 struct intel_engine_cs *engine;
666796da
TU		 1343 u64 acthd[I915_NUM_ENGINES];
1344 u32 seqno[I915_NUM_ENGINES];
61642ff0 1345 u32 instdone[I915_NUM_INSTDONE_REG];
c3232b18
DG		 1346 enum intel_engine_id id;
1347 int j;
f654449a
CW		 1348
1349 if (!i915.enable_hangcheck) {
1350 seq_printf(m, "Hangcheck disabled\n");
1351 return 0;
1352 }
1353
ebbc7546
MK		 1354 intel_runtime_pm_get(dev_priv);
1355
c3232b18 1356 for_each_engine_id(engine, dev_priv, id) {
c3232b18 1357 acthd[id] = intel_ring_get_active_head(engine);
c04e0f3b 1358 seqno[id] = engine->get_seqno(engine);
ebbc7546
MK		 1359 }
1360
61642ff0
MK		 1361 i915_get_extra_instdone(dev, instdone);
1362
ebbc7546
MK		 1363 intel_runtime_pm_put(dev_priv);
1364
f654449a
CW		 1365 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1366 seq_printf(m, "Hangcheck active, fires in %dms\n",
1367 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1368 jiffies));
1369 } else
1370 seq_printf(m, "Hangcheck inactive\n");
1371
c3232b18 1372 for_each_engine_id(engine, dev_priv, id) {
e2f80391 1373 seq_printf(m, "%s:\n", engine->name);
14fd0d6d
CW		 1374 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1375 engine->hangcheck.seqno,
1376 seqno[id],
1377 engine->last_submitted_seqno);
12471ba8
CW		 1378 seq_printf(m, "\tuser interrupts = %x [current %x]\n",
1379 engine->hangcheck.user_interrupts,
1380 READ_ONCE(engine->user_interrupts));
f654449a 1381 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
e2f80391 1382 (long long)engine->hangcheck.acthd,
c3232b18 1383 (long long)acthd[id]);
e2f80391
TU		 1384 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1385 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
61642ff0 1386
e2f80391 1387 if (engine->id == RCS) {
61642ff0
MK		 1388 seq_puts(m, "\tinstdone read =");
1389
1390 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1391 seq_printf(m, " 0x%08x", instdone[j]);
1392
1393 seq_puts(m, "\n\tinstdone accu =");
1394
1395 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1396 seq_printf(m, " 0x%08x",
e2f80391 1397 engine->hangcheck.instdone[j]);
61642ff0
MK		 1398
1399 seq_puts(m, "\n");
1400 }
f654449a
CW		 1401 }
1402
1403 return 0;
1404}
1405
4d85529d 1406static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1407{
9f25d007 1408 struct drm_info_node *node = m->private;
f97108d1 1409 struct drm_device *dev = node->minor->dev;
e277a1f8 1410 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1411 u32 rgvmodectl, rstdbyctl;
1412 u16 crstandvid;
1413 int ret;
1414
1415 ret = mutex_lock_interruptible(&dev->struct_mutex);
1416 if (ret)
1417 return ret;
c8c8fb33 1418 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1419
1420 rgvmodectl = I915_READ(MEMMODECTL);
1421 rstdbyctl = I915_READ(RSTDBYCTL);
1422 crstandvid = I915_READ16(CRSTANDVID);
1423
c8c8fb33 1424 intel_runtime_pm_put(dev_priv);
616fdb5a 1425 mutex_unlock(&dev->struct_mutex);
f97108d1 1426
742f491d 1427 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1428 seq_printf(m, "Boost freq: %d\n",
1429 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1430 MEMMODE_BOOST_FREQ_SHIFT);
1431 seq_printf(m, "HW control enabled: %s\n",
742f491d 1432 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1433 seq_printf(m, "SW control enabled: %s\n",
742f491d 1434 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1435 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1436 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1437 seq_printf(m, "Starting frequency: P%d\n",
1438 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1439 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1440 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1441 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1442 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1443 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1444 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1445 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1446 seq_puts(m, "Current RS state: ");
88271da3
JB		 1447 switch (rstdbyctl & RSX_STATUS_MASK) {
1448 case RSX_STATUS_ON:
267f0c90 1449 seq_puts(m, "on\n");
88271da3
JB		 1450 break;
1451 case RSX_STATUS_RC1:
267f0c90 1452 seq_puts(m, "RC1\n");
88271da3
JB		 1453 break;
1454 case RSX_STATUS_RC1E:
267f0c90 1455 seq_puts(m, "RC1E\n");
88271da3
JB		 1456 break;
1457 case RSX_STATUS_RS1:
267f0c90 1458 seq_puts(m, "RS1\n");
88271da3
JB		 1459 break;
1460 case RSX_STATUS_RS2:
267f0c90 1461 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1462 break;
1463 case RSX_STATUS_RS3:
267f0c90 1464 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1465 break;
1466 default:
267f0c90 1467 seq_puts(m, "unknown\n");
88271da3
JB		 1468 break;
1469 }
f97108d1
JB		 1470
1471 return 0;
1472}
1473
f65367b5 1474static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1475{
b2cff0db
CW		 1476 struct drm_info_node *node = m->private;
1477 struct drm_device *dev = node->minor->dev;
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1479 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1480
1481 spin_lock_irq(&dev_priv->uncore.lock);
33c582c1 1482 for_each_fw_domain(fw_domain, dev_priv) {
b2cff0db 1483 seq_printf(m, "%s.wake_count = %u\n",
33c582c1 1484 intel_uncore_forcewake_domain_to_str(fw_domain->id),
b2cff0db
CW		 1485 fw_domain->wake_count);
1486 }
1487 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1488
b2cff0db
CW		 1489 return 0;
1490}
1491
1492static int vlv_drpc_info(struct seq_file *m)
1493{
9f25d007 1494 struct drm_info_node *node = m->private;
669ab5aa
D		 1495 struct drm_device *dev = node->minor->dev;
1496 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1497 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1498
d46c0517
ID		 1499 intel_runtime_pm_get(dev_priv);
1500
6b312cd3 1501 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1502 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1503 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1504
d46c0517
ID		 1505 intel_runtime_pm_put(dev_priv);
1506
669ab5aa
D		 1507 seq_printf(m, "Video Turbo Mode: %s\n",
1508 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1509 seq_printf(m, "Turbo enabled: %s\n",
1510 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1511 seq_printf(m, "HW control enabled: %s\n",
1512 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1513 seq_printf(m, "SW control enabled: %s\n",
1514 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1515 GEN6_RP_MEDIA_SW_MODE));
1516 seq_printf(m, "RC6 Enabled: %s\n",
1517 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1518 GEN6_RC_CTL_EI_MODE(1))));
1519 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1520 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1521 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1522 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1523
9cc19be5
ID		 1524 seq_printf(m, "Render RC6 residency since boot: %u\n",
1525 I915_READ(VLV_GT_RENDER_RC6));
1526 seq_printf(m, "Media RC6 residency since boot: %u\n",
1527 I915_READ(VLV_GT_MEDIA_RC6));
1528
f65367b5 1529 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1530}
1531
4d85529d
BW		 1532static int gen6_drpc_info(struct seq_file *m)
1533{
9f25d007 1534 struct drm_info_node *node = m->private;
4d85529d
BW		 1535 struct drm_device *dev = node->minor->dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1537 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1538 unsigned forcewake_count;
aee56cff 1539 int count = 0, ret;
4d85529d
BW		 1540
1541 ret = mutex_lock_interruptible(&dev->struct_mutex);
1542 if (ret)
1543 return ret;
c8c8fb33 1544 intel_runtime_pm_get(dev_priv);
4d85529d 1545
907b28c5 1546 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1547 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1548 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1549
1550 if (forcewake_count) {
267f0c90
DL		 1551 seq_puts(m, "RC information inaccurate because somebody "
1552 "holds a forcewake reference \n");
4d85529d
BW		 1553 } else {
1554 /* NB: we cannot use forcewake, else we read the wrong values */
1555 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1556 udelay(10);
1557 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1558 }
1559
75aa3f63 1560 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1561 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1562
1563 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1564 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1565 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1566 mutex_lock(&dev_priv->rps.hw_lock);
1567 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1568 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1569
c8c8fb33
PZ		 1570 intel_runtime_pm_put(dev_priv);
1571
4d85529d
BW		 1572 seq_printf(m, "Video Turbo Mode: %s\n",
1573 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1574 seq_printf(m, "HW control enabled: %s\n",
1575 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1576 seq_printf(m, "SW control enabled: %s\n",
1577 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1578 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1579 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1580 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1581 seq_printf(m, "RC6 Enabled: %s\n",
1582 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1583 seq_printf(m, "Deep RC6 Enabled: %s\n",
1584 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1585 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1586 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1587 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1588 switch (gt_core_status & GEN6_RCn_MASK) {
1589 case GEN6_RC0:
1590 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1591 seq_puts(m, "Core Power Down\n");
4d85529d 1592 else
267f0c90 1593 seq_puts(m, "on\n");
4d85529d
BW		 1594 break;
1595 case GEN6_RC3:
267f0c90 1596 seq_puts(m, "RC3\n");
4d85529d
BW		 1597 break;
1598 case GEN6_RC6:
267f0c90 1599 seq_puts(m, "RC6\n");
4d85529d
BW		 1600 break;
1601 case GEN6_RC7:
267f0c90 1602 seq_puts(m, "RC7\n");
4d85529d
BW		 1603 break;
1604 default:
267f0c90 1605 seq_puts(m, "Unknown\n");
4d85529d
BW		 1606 break;
1607 }
1608
1609 seq_printf(m, "Core Power Down: %s\n",
1610 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1611
1612 /* Not exactly sure what this is */
1613 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1614 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1615 seq_printf(m, "RC6 residency since boot: %u\n",
1616 I915_READ(GEN6_GT_GFX_RC6));
1617 seq_printf(m, "RC6+ residency since boot: %u\n",
1618 I915_READ(GEN6_GT_GFX_RC6p));
1619 seq_printf(m, "RC6++ residency since boot: %u\n",
1620 I915_READ(GEN6_GT_GFX_RC6pp));
1621
ecd8faea
BW		 1622 seq_printf(m, "RC6 voltage: %dmV\n",
1623 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1624 seq_printf(m, "RC6+ voltage: %dmV\n",
1625 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1626 seq_printf(m, "RC6++ voltage: %dmV\n",
1627 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1628 return 0;
1629}
1630
1631static int i915_drpc_info(struct seq_file *m, void *unused)
1632{
9f25d007 1633 struct drm_info_node *node = m->private;
4d85529d
BW		 1634 struct drm_device *dev = node->minor->dev;
1635
666a4537 1636 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
669ab5aa 1637 return vlv_drpc_info(m);
ac66cf4b 1638 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1639 return gen6_drpc_info(m);
1640 else
1641 return ironlake_drpc_info(m);
1642}
1643
9a851789
DV		 1644static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1645{
1646 struct drm_info_node *node = m->private;
1647 struct drm_device *dev = node->minor->dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649
1650 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1651 dev_priv->fb_tracking.busy_bits);
1652
1653 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1654 dev_priv->fb_tracking.flip_bits);
1655
1656 return 0;
1657}
1658
b5e50c3f
JB		 1659static int i915_fbc_status(struct seq_file *m, void *unused)
1660{
9f25d007 1661 struct drm_info_node *node = m->private;
b5e50c3f 1662 struct drm_device *dev = node->minor->dev;
e277a1f8 1663 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1664
3a77c4c4 1665 if (!HAS_FBC(dev)) {
267f0c90 1666 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1667 return 0;
1668 }
1669
36623ef8 1670 intel_runtime_pm_get(dev_priv);
25ad93fd 1671 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1672
0e631adc 1673 if (intel_fbc_is_active(dev_priv))
267f0c90 1674 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1675 else
1676 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1677 dev_priv->fbc.no_fbc_reason);
36623ef8 1678
31b9df10
PZ		 1679 if (INTEL_INFO(dev_priv)->gen >= 7)
1680 seq_printf(m, "Compressing: %s\n",
1681 yesno(I915_READ(FBC_STATUS2) &
1682 FBC_COMPRESSION_MASK));
1683
25ad93fd 1684 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1685 intel_runtime_pm_put(dev_priv);
1686
b5e50c3f
JB		 1687 return 0;
1688}
1689
da46f936
RV		 1690static int i915_fbc_fc_get(void *data, u64 *val)
1691{
1692 struct drm_device *dev = data;
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694
1695 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1696 return -ENODEV;
1697
da46f936 1698 *val = dev_priv->fbc.false_color;
da46f936
RV		 1699
1700 return 0;
1701}
1702
1703static int i915_fbc_fc_set(void *data, u64 val)
1704{
1705 struct drm_device *dev = data;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 u32 reg;
1708
1709 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1710 return -ENODEV;
1711
25ad93fd 1712 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1713
1714 reg = I915_READ(ILK_DPFC_CONTROL);
1715 dev_priv->fbc.false_color = val;
1716
1717 I915_WRITE(ILK_DPFC_CONTROL, val ?
1718 (reg | FBC_CTL_FALSE_COLOR) :
1719 (reg & ~FBC_CTL_FALSE_COLOR));
1720
25ad93fd 1721 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1722 return 0;
1723}
1724
1725DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1726 i915_fbc_fc_get, i915_fbc_fc_set,
1727 "%llu\n");
1728
92d44621
PZ		 1729static int i915_ips_status(struct seq_file *m, void *unused)
1730{
9f25d007 1731 struct drm_info_node *node = m->private;
92d44621
PZ		 1732 struct drm_device *dev = node->minor->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734
f5adf94e 1735 if (!HAS_IPS(dev)) {
92d44621
PZ		 1736 seq_puts(m, "not supported\n");
1737 return 0;
1738 }
1739
36623ef8
PZ		 1740 intel_runtime_pm_get(dev_priv);
1741
0eaa53f0
RV		 1742 seq_printf(m, "Enabled by kernel parameter: %s\n",
1743 yesno(i915.enable_ips));
1744
1745 if (INTEL_INFO(dev)->gen >= 8) {
1746 seq_puts(m, "Currently: unknown\n");
1747 } else {
1748 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1749 seq_puts(m, "Currently: enabled\n");
1750 else
1751 seq_puts(m, "Currently: disabled\n");
1752 }
92d44621 1753
36623ef8
PZ		 1754 intel_runtime_pm_put(dev_priv);
1755
92d44621
PZ		 1756 return 0;
1757}
1758
4a9bef37
JB		 1759static int i915_sr_status(struct seq_file *m, void *unused)
1760{
9f25d007 1761 struct drm_info_node *node = m->private;
4a9bef37 1762 struct drm_device *dev = node->minor->dev;
e277a1f8 1763 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1764 bool sr_enabled = false;
1765
36623ef8
PZ		 1766 intel_runtime_pm_get(dev_priv);
1767
1398261a 1768 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1769 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1770 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1771 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1772 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1773 else if (IS_I915GM(dev))
1774 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1775 else if (IS_PINEVIEW(dev))
1776 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
666a4537 1777 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
77b64555 1778 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1779
36623ef8
PZ		 1780 intel_runtime_pm_put(dev_priv);
1781
5ba2aaaa
CW		 1782 seq_printf(m, "self-refresh: %s\n",
1783 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1784
1785 return 0;
1786}
1787
7648fa99
JB		 1788static int i915_emon_status(struct seq_file *m, void *unused)
1789{
9f25d007 1790 struct drm_info_node *node = m->private;
7648fa99 1791 struct drm_device *dev = node->minor->dev;
e277a1f8 1792 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1793 unsigned long temp, chipset, gfx;
de227ef0
CW		 1794 int ret;
1795
582be6b4
CW		 1796 if (!IS_GEN5(dev))
1797 return -ENODEV;
1798
de227ef0
CW		 1799 ret = mutex_lock_interruptible(&dev->struct_mutex);
1800 if (ret)
1801 return ret;
7648fa99
JB		 1802
1803 temp = i915_mch_val(dev_priv);
1804 chipset = i915_chipset_val(dev_priv);
1805 gfx = i915_gfx_val(dev_priv);
de227ef0 1806 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1807
1808 seq_printf(m, "GMCH temp: %ld\n", temp);
1809 seq_printf(m, "Chipset power: %ld\n", chipset);
1810 seq_printf(m, "GFX power: %ld\n", gfx);
1811 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1812
1813 return 0;
1814}
1815
23b2f8bb
JB		 1816static int i915_ring_freq_table(struct seq_file *m, void *unused)
1817{
9f25d007 1818 struct drm_info_node *node = m->private;
23b2f8bb 1819 struct drm_device *dev = node->minor->dev;
e277a1f8 1820 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1821 int ret = 0;
23b2f8bb 1822 int gpu_freq, ia_freq;
f936ec34 1823 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1824
97d3308a 1825 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1826 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1827 return 0;
1828 }
1829
5bfa0199
PZ		 1830 intel_runtime_pm_get(dev_priv);
1831
5c9669ce
TR		 1832 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1833
4fc688ce 1834 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1835 if (ret)
5bfa0199 1836 goto out;
23b2f8bb 1837
ef11bdb3 1838 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
f936ec34
AG		 1839 /* Convert GT frequency to 50 HZ units */
1840 min_gpu_freq =
1841 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1842 max_gpu_freq =
1843 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1844 } else {
1845 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1846 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1847 }
1848
267f0c90 1849 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1850
f936ec34 1851 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1852 ia_freq = gpu_freq;
1853 sandybridge_pcode_read(dev_priv,
1854 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1855 &ia_freq);
3ebecd07 1856 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1857 intel_gpu_freq(dev_priv, (gpu_freq *
ef11bdb3
RV		 1858 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1859 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1860 ((ia_freq >> 0) & 0xff) * 100,
1861 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1862 }
1863
4fc688ce 1864 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1865
5bfa0199
PZ		 1866out:
1867 intel_runtime_pm_put(dev_priv);
1868 return ret;
23b2f8bb
JB		 1869}
1870
44834a67
CW		 1871static int i915_opregion(struct seq_file *m, void *unused)
1872{
9f25d007 1873 struct drm_info_node *node = m->private;
44834a67 1874 struct drm_device *dev = node->minor->dev;
e277a1f8 1875 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67
CW		 1876 struct intel_opregion *opregion = &dev_priv->opregion;
1877 int ret;
1878
1879 ret = mutex_lock_interruptible(&dev->struct_mutex);
1880 if (ret)
0d38f009 1881 goto out;
44834a67 1882
2455a8e4
JN		 1883 if (opregion->header)
1884 seq_write(m, opregion->header, OPREGION_SIZE);
44834a67
CW		 1885
1886 mutex_unlock(&dev->struct_mutex);
1887
0d38f009 1888out:
44834a67
CW		 1889 return 0;
1890}
1891
ada8f955
JN		 1892static int i915_vbt(struct seq_file *m, void *unused)
1893{
1894 struct drm_info_node *node = m->private;
1895 struct drm_device *dev = node->minor->dev;
1896 struct drm_i915_private *dev_priv = dev->dev_private;
1897 struct intel_opregion *opregion = &dev_priv->opregion;
1898
1899 if (opregion->vbt)
1900 seq_write(m, opregion->vbt, opregion->vbt_size);
1901
1902 return 0;
1903}
1904
37811fcc
CW		 1905static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1906{
9f25d007 1907 struct drm_info_node *node = m->private;
37811fcc 1908 struct drm_device *dev = node->minor->dev;
b13b8402 1909 struct intel_framebuffer *fbdev_fb = NULL;
3a58ee10 1910 struct drm_framebuffer *drm_fb;
188c1ab7
CW		 1911 int ret;
1912
1913 ret = mutex_lock_interruptible(&dev->struct_mutex);
1914 if (ret)
1915 return ret;
37811fcc 1916
0695726e 1917#ifdef CONFIG_DRM_FBDEV_EMULATION
b13b8402
NS		 1918 if (to_i915(dev)->fbdev) {
1919 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1920
1921 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1922 fbdev_fb->base.width,
1923 fbdev_fb->base.height,
1924 fbdev_fb->base.depth,
1925 fbdev_fb->base.bits_per_pixel,
1926 fbdev_fb->base.modifier[0],
1927 atomic_read(&fbdev_fb->base.refcount.refcount));
1928 describe_obj(m, fbdev_fb->obj);
1929 seq_putc(m, '\n');
1930 }
4520f53a 1931#endif
37811fcc 1932
4b096ac1 1933 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10 1934 drm_for_each_fb(drm_fb, dev) {
b13b8402
NS		 1935 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1936 if (fb == fbdev_fb)
37811fcc
CW		 1937 continue;
1938
c1ca506d 1939 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1940 fb->base.width,
1941 fb->base.height,
1942 fb->base.depth,
623f9783 1943 fb->base.bits_per_pixel,
c1ca506d 1944 fb->base.modifier[0],
623f9783 1945 atomic_read(&fb->base.refcount.refcount));
05394f39 1946 describe_obj(m, fb->obj);
267f0c90 1947 seq_putc(m, '\n');
37811fcc 1948 }
4b096ac1 1949 mutex_unlock(&dev->mode_config.fb_lock);
188c1ab7 1950 mutex_unlock(&dev->struct_mutex);
37811fcc
CW		 1951
1952 return 0;
1953}
1954
c9fe99bd
OM		 1955static void describe_ctx_ringbuf(struct seq_file *m,
1956 struct intel_ringbuffer *ringbuf)
1957{
1958 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1959 ringbuf->space, ringbuf->head, ringbuf->tail,
1960 ringbuf->last_retired_head);
1961}
1962
e76d3630
BW		 1963static int i915_context_status(struct seq_file *m, void *unused)
1964{
9f25d007 1965 struct drm_info_node *node = m->private;
e76d3630 1966 struct drm_device *dev = node->minor->dev;
e277a1f8 1967 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1968 struct intel_engine_cs *engine;
273497e5 1969 struct intel_context *ctx;
c3232b18
DG		 1970 enum intel_engine_id id;
1971 int ret;
e76d3630 1972
f3d28878 1973 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1974 if (ret)
1975 return ret;
1976
a33afea5 1977 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1978 if (!i915.enable_execlists &&
1979 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1980 continue;
1981
a33afea5 1982 seq_puts(m, "HW context ");
3ccfd19d 1983 describe_ctx(m, ctx);
e28e404c
DG		 1984 if (ctx == dev_priv->kernel_context)
1985 seq_printf(m, "(kernel context) ");
c9fe99bd
OM		 1986
1987 if (i915.enable_execlists) {
1988 seq_putc(m, '\n');
c3232b18 1989 for_each_engine_id(engine, dev_priv, id) {
c9fe99bd 1990 struct drm_i915_gem_object *ctx_obj =
c3232b18 1991 ctx->engine[id].state;
c9fe99bd 1992 struct intel_ringbuffer *ringbuf =
c3232b18 1993 ctx->engine[id].ringbuf;
c9fe99bd 1994
e2f80391 1995 seq_printf(m, "%s: ", engine->name);
c9fe99bd
OM		 1996 if (ctx_obj)
1997 describe_obj(m, ctx_obj);
1998 if (ringbuf)
1999 describe_ctx_ringbuf(m, ringbuf);
2000 seq_putc(m, '\n');
2001 }
2002 } else {
2003 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
2004 }
a33afea5 2005
a33afea5 2006 seq_putc(m, '\n');
a168c293
BW		 2007 }
2008
f3d28878 2009 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 2010
2011 return 0;
2012}
2013
064ca1d2 2014static void i915_dump_lrc_obj(struct seq_file *m,
ca82580c 2015 struct intel_context *ctx,
0bc40be8 2016 struct intel_engine_cs *engine)
064ca1d2
TD		 2017{
2018 struct page *page;
2019 uint32_t *reg_state;
2020 int j;
0bc40be8 2021 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
064ca1d2
TD		 2022 unsigned long ggtt_offset = 0;
2023
2024 if (ctx_obj == NULL) {
2025 seq_printf(m, "Context on %s with no gem object\n",
0bc40be8 2026 engine->name);
064ca1d2
TD		 2027 return;
2028 }
2029
0bc40be8
TU		 2030 seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2031 intel_execlists_ctx_id(ctx, engine));
064ca1d2
TD		 2032
2033 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2034 seq_puts(m, "\tNot bound in GGTT\n");
2035 else
2036 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2037
2038 if (i915_gem_object_get_pages(ctx_obj)) {
2039 seq_puts(m, "\tFailed to get pages for context object\n");
2040 return;
2041 }
2042
d1675198 2043 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 2044 if (!WARN_ON(page == NULL)) {
2045 reg_state = kmap_atomic(page);
2046
2047 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2048 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2049 ggtt_offset + 4096 + (j * 4),
2050 reg_state[j], reg_state[j + 1],
2051 reg_state[j + 2], reg_state[j + 3]);
2052 }
2053 kunmap_atomic(reg_state);
2054 }
2055
2056 seq_putc(m, '\n');
2057}
2058
c0ab1ae9
BW		 2059static int i915_dump_lrc(struct seq_file *m, void *unused)
2060{
2061 struct drm_info_node *node = (struct drm_info_node *) m->private;
2062 struct drm_device *dev = node->minor->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2064 struct intel_engine_cs *engine;
c0ab1ae9 2065 struct intel_context *ctx;
b4ac5afc 2066 int ret;
c0ab1ae9
BW		 2067
2068 if (!i915.enable_execlists) {
2069 seq_printf(m, "Logical Ring Contexts are disabled\n");
2070 return 0;
2071 }
2072
2073 ret = mutex_lock_interruptible(&dev->struct_mutex);
2074 if (ret)
2075 return ret;
2076
e28e404c
DG		 2077 list_for_each_entry(ctx, &dev_priv->context_list, link)
2078 if (ctx != dev_priv->kernel_context)
b4ac5afc 2079 for_each_engine(engine, dev_priv)
e2f80391 2080 i915_dump_lrc_obj(m, ctx, engine);
c0ab1ae9
BW		 2081
2082 mutex_unlock(&dev->struct_mutex);
2083
2084 return 0;
2085}
2086
4ba70e44
OM		 2087static int i915_execlists(struct seq_file *m, void *data)
2088{
2089 struct drm_info_node *node = (struct drm_info_node *)m->private;
2090 struct drm_device *dev = node->minor->dev;
2091 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2092 struct intel_engine_cs *engine;
4ba70e44
OM		 2093 u32 status_pointer;
2094 u8 read_pointer;
2095 u8 write_pointer;
2096 u32 status;
2097 u32 ctx_id;
2098 struct list_head *cursor;
b4ac5afc 2099 int i, ret;
4ba70e44
OM		 2100
2101 if (!i915.enable_execlists) {
2102 seq_puts(m, "Logical Ring Contexts are disabled\n");
2103 return 0;
2104 }
2105
2106 ret = mutex_lock_interruptible(&dev->struct_mutex);
2107 if (ret)
2108 return ret;
2109
fc0412ec
MT		 2110 intel_runtime_pm_get(dev_priv);
2111
b4ac5afc 2112 for_each_engine(engine, dev_priv) {
6d3d8274 2113 struct drm_i915_gem_request *head_req = NULL;
4ba70e44 2114 int count = 0;
4ba70e44 2115
e2f80391 2116 seq_printf(m, "%s\n", engine->name);
4ba70e44 2117
e2f80391
TU		 2118 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2119 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
4ba70e44
OM		 2120 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2121 status, ctx_id);
2122
e2f80391 2123 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
4ba70e44
OM		 2124 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2125
e2f80391 2126 read_pointer = engine->next_context_status_buffer;
5590a5f0 2127 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
4ba70e44 2128 if (read_pointer > write_pointer)
5590a5f0 2129 write_pointer += GEN8_CSB_ENTRIES;
4ba70e44
OM		 2130 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2131 read_pointer, write_pointer);
2132
5590a5f0 2133 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
e2f80391
TU		 2134 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2135 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
4ba70e44
OM		 2136
2137 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2138 i, status, ctx_id);
2139 }
2140
27af5eea 2141 spin_lock_bh(&engine->execlist_lock);
e2f80391 2142 list_for_each(cursor, &engine->execlist_queue)
4ba70e44 2143 count++;
e2f80391
TU		 2144 head_req = list_first_entry_or_null(&engine->execlist_queue,
2145 struct drm_i915_gem_request,
2146 execlist_link);
27af5eea 2147 spin_unlock_bh(&engine->execlist_lock);
4ba70e44
OM		 2148
2149 seq_printf(m, "\t%d requests in queue\n", count);
2150 if (head_req) {
4ba70e44 2151 seq_printf(m, "\tHead request id: %u\n",
e2f80391 2152 intel_execlists_ctx_id(head_req->ctx, engine));
4ba70e44 2153 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2154 head_req->tail);
4ba70e44
OM		 2155 }
2156
2157 seq_putc(m, '\n');
2158 }
2159
fc0412ec 2160 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2161 mutex_unlock(&dev->struct_mutex);
2162
2163 return 0;
2164}
2165
ea16a3cd
DV		 2166static const char *swizzle_string(unsigned swizzle)
2167{
aee56cff 2168 switch (swizzle) {
ea16a3cd
DV		 2169 case I915_BIT_6_SWIZZLE_NONE:
2170 return "none";
2171 case I915_BIT_6_SWIZZLE_9:
2172 return "bit9";
2173 case I915_BIT_6_SWIZZLE_9_10:
2174 return "bit9/bit10";
2175 case I915_BIT_6_SWIZZLE_9_11:
2176 return "bit9/bit11";
2177 case I915_BIT_6_SWIZZLE_9_10_11:
2178 return "bit9/bit10/bit11";
2179 case I915_BIT_6_SWIZZLE_9_17:
2180 return "bit9/bit17";
2181 case I915_BIT_6_SWIZZLE_9_10_17:
2182 return "bit9/bit10/bit17";
2183 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2184 return "unknown";
ea16a3cd
DV		 2185 }
2186
2187 return "bug";
2188}
2189
2190static int i915_swizzle_info(struct seq_file *m, void *data)
2191{
9f25d007 2192 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2193 struct drm_device *dev = node->minor->dev;
2194 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2195 int ret;
2196
2197 ret = mutex_lock_interruptible(&dev->struct_mutex);
2198 if (ret)
2199 return ret;
c8c8fb33 2200 intel_runtime_pm_get(dev_priv);
ea16a3cd 2201
ea16a3cd
DV		 2202 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2203 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2204 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2205 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2206
2207 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2208 seq_printf(m, "DDC = 0x%08x\n",
2209 I915_READ(DCC));
656bfa3a
DV		 2210 seq_printf(m, "DDC2 = 0x%08x\n",
2211 I915_READ(DCC2));
ea16a3cd
DV		 2212 seq_printf(m, "C0DRB3 = 0x%04x\n",
2213 I915_READ16(C0DRB3));
2214 seq_printf(m, "C1DRB3 = 0x%04x\n",
2215 I915_READ16(C1DRB3));
9d3203e1 2216 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2217 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2218 I915_READ(MAD_DIMM_C0));
2219 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2220 I915_READ(MAD_DIMM_C1));
2221 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2222 I915_READ(MAD_DIMM_C2));
2223 seq_printf(m, "TILECTL = 0x%08x\n",
2224 I915_READ(TILECTL));
5907f5fb 2225 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2226 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2227 I915_READ(GAMTARBMODE));
2228 else
2229 seq_printf(m, "ARB_MODE = 0x%08x\n",
2230 I915_READ(ARB_MODE));
3fa7d235
DV		 2231 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2232 I915_READ(DISP_ARB_CTL));
ea16a3cd 2233 }
656bfa3a
DV		 2234
2235 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2236 seq_puts(m, "L-shaped memory detected\n");
2237
c8c8fb33 2238 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2239 mutex_unlock(&dev->struct_mutex);
2240
2241 return 0;
2242}
2243
1c60fef5
BW		 2244static int per_file_ctx(int id, void *ptr, void *data)
2245{
273497e5 2246 struct intel_context *ctx = ptr;
1c60fef5 2247 struct seq_file *m = data;
ae6c4806
DV		 2248 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2249
2250 if (!ppgtt) {
2251 seq_printf(m, " no ppgtt for context %d\n",
2252 ctx->user_handle);
2253 return 0;
2254 }
1c60fef5 2255
f83d6518
OM		 2256 if (i915_gem_context_is_default(ctx))
2257 seq_puts(m, " default context:\n");
2258 else
821d66dd 2259 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2260 ppgtt->debug_dump(ppgtt, m);
2261
2262 return 0;
2263}
2264
77df6772 2265static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2266{
3cf17fc5 2267 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2268 struct intel_engine_cs *engine;
77df6772 2269 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
b4ac5afc 2270 int i;
3cf17fc5 2271
77df6772
BW		 2272 if (!ppgtt)
2273 return;
2274
b4ac5afc 2275 for_each_engine(engine, dev_priv) {
e2f80391 2276 seq_printf(m, "%s\n", engine->name);
77df6772 2277 for (i = 0; i < 4; i++) {
e2f80391 2278 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
77df6772 2279 pdp <<= 32;
e2f80391 2280 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
a2a5b15c 2281 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2282 }
2283 }
2284}
2285
2286static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2287{
2288 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2289 struct intel_engine_cs *engine;
3cf17fc5 2290
3cf17fc5
DV		 2291 if (INTEL_INFO(dev)->gen == 6)
2292 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2293
b4ac5afc 2294 for_each_engine(engine, dev_priv) {
e2f80391 2295 seq_printf(m, "%s\n", engine->name);
3cf17fc5 2296 if (INTEL_INFO(dev)->gen == 7)
e2f80391
TU		 2297 seq_printf(m, "GFX_MODE: 0x%08x\n",
2298 I915_READ(RING_MODE_GEN7(engine)));
2299 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2300 I915_READ(RING_PP_DIR_BASE(engine)));
2301 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2302 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2303 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2304 I915_READ(RING_PP_DIR_DCLV(engine)));
3cf17fc5
DV		 2305 }
2306 if (dev_priv->mm.aliasing_ppgtt) {
2307 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2308
267f0c90 2309 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2310 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2311
87d60b63 2312 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2313 }
1c60fef5 2314
3cf17fc5 2315 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2316}
2317
2318static int i915_ppgtt_info(struct seq_file *m, void *data)
2319{
9f25d007 2320 struct drm_info_node *node = m->private;
77df6772 2321 struct drm_device *dev = node->minor->dev;
c8c8fb33 2322 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2323 struct drm_file *file;
77df6772
BW		 2324
2325 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2326 if (ret)
2327 return ret;
c8c8fb33 2328 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2329
2330 if (INTEL_INFO(dev)->gen >= 8)
2331 gen8_ppgtt_info(m, dev);
2332 else if (INTEL_INFO(dev)->gen >= 6)
2333 gen6_ppgtt_info(m, dev);
2334
ea91e401
MT		 2335 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2336 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2337 struct task_struct *task;
ea91e401 2338
7cb5dff8 2339 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2340 if (!task) {
2341 ret = -ESRCH;
2342 goto out_put;
2343 }
7cb5dff8
GT		 2344 seq_printf(m, "\nproc: %s\n", task->comm);
2345 put_task_struct(task);
ea91e401
MT		 2346 idr_for_each(&file_priv->context_idr, per_file_ctx,
2347 (void *)(unsigned long)m);
2348 }
2349
06812760 2350out_put:
c8c8fb33 2351 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2352 mutex_unlock(&dev->struct_mutex);
2353
06812760 2354 return ret;
3cf17fc5
DV		 2355}
2356
f5a4c67d
CW		 2357static int count_irq_waiters(struct drm_i915_private *i915)
2358{
e2f80391 2359 struct intel_engine_cs *engine;
f5a4c67d 2360 int count = 0;
f5a4c67d 2361
b4ac5afc 2362 for_each_engine(engine, i915)
e2f80391 2363 count += engine->irq_refcount;
f5a4c67d
CW		 2364
2365 return count;
2366}
2367
1854d5ca
CW		 2368static int i915_rps_boost_info(struct seq_file *m, void *data)
2369{
2370 struct drm_info_node *node = m->private;
2371 struct drm_device *dev = node->minor->dev;
2372 struct drm_i915_private *dev_priv = dev->dev_private;
2373 struct drm_file *file;
1854d5ca 2374
f5a4c67d
CW		 2375 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2376 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2377 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2378 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2379 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2380 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2381 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2382 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2383 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2384 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2385 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2386 struct drm_i915_file_private *file_priv = file->driver_priv;
2387 struct task_struct *task;
2388
2389 rcu_read_lock();
2390 task = pid_task(file->pid, PIDTYPE_PID);
2391 seq_printf(m, "%s [%d]: %d boosts%s\n",
2392 task ? task->comm : "<unknown>",
2393 task ? task->pid : -1,
2e1b8730
CW		 2394 file_priv->rps.boosts,
2395 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2396 rcu_read_unlock();
2397 }
2e1b8730
CW		 2398 seq_printf(m, "Semaphore boosts: %d%s\n",
2399 dev_priv->rps.semaphores.boosts,
2400 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2401 seq_printf(m, "MMIO flip boosts: %d%s\n",
2402 dev_priv->rps.mmioflips.boosts,
2403 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2404 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2405 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2406
8d3afd7d 2407 return 0;
1854d5ca
CW		 2408}
2409
63573eb7
BW		 2410static int i915_llc(struct seq_file *m, void *data)
2411{
9f25d007 2412 struct drm_info_node *node = m->private;
63573eb7
BW		 2413 struct drm_device *dev = node->minor->dev;
2414 struct drm_i915_private *dev_priv = dev->dev_private;
3accaf7e 2415 const bool edram = INTEL_GEN(dev_priv) > 8;
63573eb7 2416
63573eb7 2417 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
3accaf7e
MK		 2418 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2419 intel_uncore_edram_size(dev_priv)/1024/1024);
63573eb7
BW		 2420
2421 return 0;
2422}
2423
fdf5d357
AD		 2424static int i915_guc_load_status_info(struct seq_file *m, void *data)
2425{
2426 struct drm_info_node *node = m->private;
2427 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2428 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2429 u32 tmp, i;
2430
2d1fe073 2431 if (!HAS_GUC_UCODE(dev_priv))
fdf5d357
AD		 2432 return 0;
2433
2434 seq_printf(m, "GuC firmware status:\n");
2435 seq_printf(m, "\tpath: %s\n",
2436 guc_fw->guc_fw_path);
2437 seq_printf(m, "\tfetch: %s\n",
2438 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2439 seq_printf(m, "\tload: %s\n",
2440 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2441 seq_printf(m, "\tversion wanted: %d.%d\n",
2442 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2443 seq_printf(m, "\tversion found: %d.%d\n",
2444 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2445 seq_printf(m, "\theader: offset is %d; size = %d\n",
2446 guc_fw->header_offset, guc_fw->header_size);
2447 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2448 guc_fw->ucode_offset, guc_fw->ucode_size);
2449 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2450 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2451
2452 tmp = I915_READ(GUC_STATUS);
2453
2454 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2455 seq_printf(m, "\tBootrom status = 0x%x\n",
2456 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2457 seq_printf(m, "\tuKernel status = 0x%x\n",
2458 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2459 seq_printf(m, "\tMIA Core status = 0x%x\n",
2460 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2461 seq_puts(m, "\nScratch registers:\n");
2462 for (i = 0; i < 16; i++)
2463 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2464
2465 return 0;
2466}
2467
8b417c26
DG		 2468static void i915_guc_client_info(struct seq_file *m,
2469 struct drm_i915_private *dev_priv,
2470 struct i915_guc_client *client)
2471{
e2f80391 2472 struct intel_engine_cs *engine;
8b417c26 2473 uint64_t tot = 0;
8b417c26
DG		 2474
2475 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2476 client->priority, client->ctx_index, client->proc_desc_offset);
2477 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2478 client->doorbell_id, client->doorbell_offset, client->cookie);
2479 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2480 client->wq_size, client->wq_offset, client->wq_tail);
2481
2482 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2483 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2484 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2485
b4ac5afc 2486 for_each_engine(engine, dev_priv) {
8b417c26 2487 seq_printf(m, "\tSubmissions: %llu %s\n",
e2f80391
TU		 2488 client->submissions[engine->guc_id],
2489 engine->name);
2490 tot += client->submissions[engine->guc_id];
8b417c26
DG		 2491 }
2492 seq_printf(m, "\tTotal: %llu\n", tot);
2493}
2494
2495static int i915_guc_info(struct seq_file *m, void *data)
2496{
2497 struct drm_info_node *node = m->private;
2498 struct drm_device *dev = node->minor->dev;
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 struct intel_guc guc;
0a0b457f 2501 struct i915_guc_client client = {};
e2f80391 2502 struct intel_engine_cs *engine;
8b417c26
DG		 2503 u64 total = 0;
2504
2d1fe073 2505 if (!HAS_GUC_SCHED(dev_priv))
8b417c26
DG		 2506 return 0;
2507
5a843307
AD		 2508 if (mutex_lock_interruptible(&dev->struct_mutex))
2509 return 0;
2510
8b417c26 2511 /* Take a local copy of the GuC data, so we can dump it at leisure */
8b417c26 2512 guc = dev_priv->guc;
5a843307 2513 if (guc.execbuf_client)
8b417c26 2514 client = *guc.execbuf_client;
5a843307
AD		 2515
2516 mutex_unlock(&dev->struct_mutex);
8b417c26
DG		 2517
2518 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2519 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2520 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2521 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2522 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2523
2524 seq_printf(m, "\nGuC submissions:\n");
b4ac5afc 2525 for_each_engine(engine, dev_priv) {
397097b0 2526 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
e2f80391
TU		 2527 engine->name, guc.submissions[engine->guc_id],
2528 guc.last_seqno[engine->guc_id]);
2529 total += guc.submissions[engine->guc_id];
8b417c26
DG		 2530 }
2531 seq_printf(m, "\t%s: %llu\n", "Total", total);
2532
2533 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2534 i915_guc_client_info(m, dev_priv, &client);
2535
2536 /* Add more as required ... */
2537
2538 return 0;
2539}
2540
4c7e77fc
AD		 2541static int i915_guc_log_dump(struct seq_file *m, void *data)
2542{
2543 struct drm_info_node *node = m->private;
2544 struct drm_device *dev = node->minor->dev;
2545 struct drm_i915_private *dev_priv = dev->dev_private;
2546 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2547 u32 *log;
2548 int i = 0, pg;
2549
2550 if (!log_obj)
2551 return 0;
2552
2553 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2554 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2555
2556 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2557 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2558 *(log + i), *(log + i + 1),
2559 *(log + i + 2), *(log + i + 3));
2560
2561 kunmap_atomic(log);
2562 }
2563
2564 seq_putc(m, '\n');
2565
2566 return 0;
2567}
2568
e91fd8c6
RV		 2569static int i915_edp_psr_status(struct seq_file *m, void *data)
2570{
2571 struct drm_info_node *node = m->private;
2572 struct drm_device *dev = node->minor->dev;
2573 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2574 u32 psrperf = 0;
a6cbdb8e
RV		 2575 u32 stat[3];
2576 enum pipe pipe;
a031d709 2577 bool enabled = false;
e91fd8c6 2578
3553a8ea
DL		 2579 if (!HAS_PSR(dev)) {
2580 seq_puts(m, "PSR not supported\n");
2581 return 0;
2582 }
2583
c8c8fb33
PZ		 2584 intel_runtime_pm_get(dev_priv);
2585
fa128fa6 2586 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2587 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2588 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2589 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2590 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2591 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2592 dev_priv->psr.busy_frontbuffer_bits);
2593 seq_printf(m, "Re-enable work scheduled: %s\n",
2594 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2595
3553a8ea 2596 if (HAS_DDI(dev))
443a389f 2597 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
3553a8ea
DL		 2598 else {
2599 for_each_pipe(dev_priv, pipe) {
2600 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2601 VLV_EDP_PSR_CURR_STATE_MASK;
2602 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2603 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2604 enabled = true;
a6cbdb8e
RV		 2605 }
2606 }
60e5ffe3
RV		 2607
2608 seq_printf(m, "Main link in standby mode: %s\n",
2609 yesno(dev_priv->psr.link_standby));
2610
a6cbdb8e
RV		 2611 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2612
2613 if (!HAS_DDI(dev))
2614 for_each_pipe(dev_priv, pipe) {
2615 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2616 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2617 seq_printf(m, " pipe %c", pipe_name(pipe));
2618 }
2619 seq_puts(m, "\n");
e91fd8c6 2620
05eec3c2
RV		 2621 /*
2622 * VLV/CHV PSR has no kind of performance counter
2623 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2624 */
2625 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443a389f 2626 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
a031d709 2627 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2628
2629 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2630 }
fa128fa6 2631 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2632
c8c8fb33 2633 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2634 return 0;
2635}
2636
d2e216d0
RV		 2637static int i915_sink_crc(struct seq_file *m, void *data)
2638{
2639 struct drm_info_node *node = m->private;
2640 struct drm_device *dev = node->minor->dev;
2641 struct intel_encoder *encoder;
2642 struct intel_connector *connector;
2643 struct intel_dp *intel_dp = NULL;
2644 int ret;
2645 u8 crc[6];
2646
2647 drm_modeset_lock_all(dev);
aca5e361 2648 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2649
2650 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2651 continue;
2652
b6ae3c7c
PZ		 2653 if (!connector->base.encoder)
2654 continue;
2655
d2e216d0
RV		 2656 encoder = to_intel_encoder(connector->base.encoder);
2657 if (encoder->type != INTEL_OUTPUT_EDP)
2658 continue;
2659
2660 intel_dp = enc_to_intel_dp(&encoder->base);
2661
2662 ret = intel_dp_sink_crc(intel_dp, crc);
2663 if (ret)
2664 goto out;
2665
2666 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2667 crc[0], crc[1], crc[2],
2668 crc[3], crc[4], crc[5]);
2669 goto out;
2670 }
2671 ret = -ENODEV;
2672out:
2673 drm_modeset_unlock_all(dev);
2674 return ret;
2675}
2676
ec013e7f
JB		 2677static int i915_energy_uJ(struct seq_file *m, void *data)
2678{
2679 struct drm_info_node *node = m->private;
2680 struct drm_device *dev = node->minor->dev;
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 u64 power;
2683 u32 units;
2684
2685 if (INTEL_INFO(dev)->gen < 6)
2686 return -ENODEV;
2687
36623ef8
PZ		 2688 intel_runtime_pm_get(dev_priv);
2689
ec013e7f
JB		 2690 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2691 power = (power & 0x1f00) >> 8;
2692 units = 1000000 / (1 << power); /* convert to uJ */
2693 power = I915_READ(MCH_SECP_NRG_STTS);
2694 power *= units;
2695
36623ef8
PZ		 2696 intel_runtime_pm_put(dev_priv);
2697
ec013e7f 2698 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2699
2700 return 0;
2701}
2702
6455c870 2703static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2704{
9f25d007 2705 struct drm_info_node *node = m->private;
371db66a
PZ		 2706 struct drm_device *dev = node->minor->dev;
2707 struct drm_i915_private *dev_priv = dev->dev_private;
2708
a156e64d
CW		 2709 if (!HAS_RUNTIME_PM(dev_priv))
2710 seq_puts(m, "Runtime power management not supported\n");
371db66a 2711
86c4ec0d 2712 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2713 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2714 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2715#ifdef CONFIG_PM
a6aaec8b
DL		 2716 seq_printf(m, "Usage count: %d\n",
2717 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2718#else
2719 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2720#endif
a156e64d
CW		 2721 seq_printf(m, "PCI device power state: %s [%d]\n",
2722 pci_power_name(dev_priv->dev->pdev->current_state),
2723 dev_priv->dev->pdev->current_state);
371db66a 2724
ec013e7f
JB		 2725 return 0;
2726}
2727
1da51581
ID		 2728static int i915_power_domain_info(struct seq_file *m, void *unused)
2729{
9f25d007 2730 struct drm_info_node *node = m->private;
1da51581
ID		 2731 struct drm_device *dev = node->minor->dev;
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2734 int i;
2735
2736 mutex_lock(&power_domains->lock);
2737
2738 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2739 for (i = 0; i < power_domains->power_well_count; i++) {
2740 struct i915_power_well *power_well;
2741 enum intel_display_power_domain power_domain;
2742
2743 power_well = &power_domains->power_wells[i];
2744 seq_printf(m, "%-25s %d\n", power_well->name,
2745 power_well->count);
2746
2747 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2748 power_domain++) {
2749 if (!(BIT(power_domain) & power_well->domains))
2750 continue;
2751
2752 seq_printf(m, " %-23s %d\n",
9895ad03 2753 intel_display_power_domain_str(power_domain),
1da51581
ID		 2754 power_domains->domain_use_count[power_domain]);
2755 }
2756 }
2757
2758 mutex_unlock(&power_domains->lock);
2759
2760 return 0;
2761}
2762
b7cec66d
DL		 2763static int i915_dmc_info(struct seq_file *m, void *unused)
2764{
2765 struct drm_info_node *node = m->private;
2766 struct drm_device *dev = node->minor->dev;
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 struct intel_csr *csr;
2769
2770 if (!HAS_CSR(dev)) {
2771 seq_puts(m, "not supported\n");
2772 return 0;
2773 }
2774
2775 csr = &dev_priv->csr;
2776
6fb403de
MK		 2777 intel_runtime_pm_get(dev_priv);
2778
b7cec66d
DL		 2779 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2780 seq_printf(m, "path: %s\n", csr->fw_path);
2781
2782 if (!csr->dmc_payload)
6fb403de 2783 goto out;
b7cec66d
DL		 2784
2785 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2786 CSR_VERSION_MINOR(csr->version));
2787
8337206d
DL		 2788 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2789 seq_printf(m, "DC3 -> DC5 count: %d\n",
2790 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2791 seq_printf(m, "DC5 -> DC6 count: %d\n",
2792 I915_READ(SKL_CSR_DC5_DC6_COUNT));
16e11b99
MK		 2793 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2794 seq_printf(m, "DC3 -> DC5 count: %d\n",
2795 I915_READ(BXT_CSR_DC3_DC5_COUNT));
8337206d
DL		 2796 }
2797
6fb403de
MK		 2798out:
2799 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2800 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2801 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2802
8337206d
DL		 2803 intel_runtime_pm_put(dev_priv);
2804
b7cec66d
DL		 2805 return 0;
2806}
2807
53f5e3ca
JB		 2808static void intel_seq_print_mode(struct seq_file *m, int tabs,
2809 struct drm_display_mode *mode)
2810{
2811 int i;
2812
2813 for (i = 0; i < tabs; i++)
2814 seq_putc(m, '\t');
2815
2816 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2817 mode->base.id, mode->name,
2818 mode->vrefresh, mode->clock,
2819 mode->hdisplay, mode->hsync_start,
2820 mode->hsync_end, mode->htotal,
2821 mode->vdisplay, mode->vsync_start,
2822 mode->vsync_end, mode->vtotal,
2823 mode->type, mode->flags);
2824}
2825
2826static void intel_encoder_info(struct seq_file *m,
2827 struct intel_crtc *intel_crtc,
2828 struct intel_encoder *intel_encoder)
2829{
9f25d007 2830 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2831 struct drm_device *dev = node->minor->dev;
2832 struct drm_crtc *crtc = &intel_crtc->base;
2833 struct intel_connector *intel_connector;
2834 struct drm_encoder *encoder;
2835
2836 encoder = &intel_encoder->base;
2837 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2838 encoder->base.id, encoder->name);
53f5e3ca
JB		 2839 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2840 struct drm_connector *connector = &intel_connector->base;
2841 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2842 connector->base.id,
c23cc417 2843 connector->name,
53f5e3ca
JB		 2844 drm_get_connector_status_name(connector->status));
2845 if (connector->status == connector_status_connected) {
2846 struct drm_display_mode *mode = &crtc->mode;
2847 seq_printf(m, ", mode:\n");
2848 intel_seq_print_mode(m, 2, mode);
2849 } else {
2850 seq_putc(m, '\n');
2851 }
2852 }
2853}
2854
2855static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2856{
9f25d007 2857 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2858 struct drm_device *dev = node->minor->dev;
2859 struct drm_crtc *crtc = &intel_crtc->base;
2860 struct intel_encoder *intel_encoder;
23a48d53
ML		 2861 struct drm_plane_state *plane_state = crtc->primary->state;
2862 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2863
23a48d53 2864 if (fb)
5aa8a937 2865 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2866 fb->base.id, plane_state->src_x >> 16,
2867 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2868 else
2869 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2870 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2871 intel_encoder_info(m, intel_crtc, intel_encoder);
2872}
2873
2874static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2875{
2876 struct drm_display_mode *mode = panel->fixed_mode;
2877
2878 seq_printf(m, "\tfixed mode:\n");
2879 intel_seq_print_mode(m, 2, mode);
2880}
2881
2882static void intel_dp_info(struct seq_file *m,
2883 struct intel_connector *intel_connector)
2884{
2885 struct intel_encoder *intel_encoder = intel_connector->encoder;
2886 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2887
2888 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2889 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
53f5e3ca
JB		 2890 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2891 intel_panel_info(m, &intel_connector->panel);
2892}
2893
3d52ccf5
LY		 2894static void intel_dp_mst_info(struct seq_file *m,
2895 struct intel_connector *intel_connector)
2896{
2897 struct intel_encoder *intel_encoder = intel_connector->encoder;
2898 struct intel_dp_mst_encoder *intel_mst =
2899 enc_to_mst(&intel_encoder->base);
2900 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2901 struct intel_dp *intel_dp = &intel_dig_port->dp;
2902 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2903 intel_connector->port);
2904
2905 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2906}
2907
53f5e3ca
JB		 2908static void intel_hdmi_info(struct seq_file *m,
2909 struct intel_connector *intel_connector)
2910{
2911 struct intel_encoder *intel_encoder = intel_connector->encoder;
2912 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2913
742f491d 2914 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2915}
2916
2917static void intel_lvds_info(struct seq_file *m,
2918 struct intel_connector *intel_connector)
2919{
2920 intel_panel_info(m, &intel_connector->panel);
2921}
2922
2923static void intel_connector_info(struct seq_file *m,
2924 struct drm_connector *connector)
2925{
2926 struct intel_connector *intel_connector = to_intel_connector(connector);
2927 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2928 struct drm_display_mode *mode;
53f5e3ca
JB		 2929
2930 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2931 connector->base.id, connector->name,
53f5e3ca
JB		 2932 drm_get_connector_status_name(connector->status));
2933 if (connector->status == connector_status_connected) {
2934 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2935 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2936 connector->display_info.width_mm,
2937 connector->display_info.height_mm);
2938 seq_printf(m, "\tsubpixel order: %s\n",
2939 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2940 seq_printf(m, "\tCEA rev: %d\n",
2941 connector->display_info.cea_rev);
2942 }
36cd7444
DA		 2943 if (intel_encoder) {
2944 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2945 intel_encoder->type == INTEL_OUTPUT_EDP)
2946 intel_dp_info(m, intel_connector);
2947 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2948 intel_hdmi_info(m, intel_connector);
2949 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2950 intel_lvds_info(m, intel_connector);
3d52ccf5
LY		 2951 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2952 intel_dp_mst_info(m, intel_connector);
36cd7444 2953 }
53f5e3ca 2954
f103fc7d
JB		 2955 seq_printf(m, "\tmodes:\n");
2956 list_for_each_entry(mode, &connector->modes, head)
2957 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2958}
2959
065f2ec2
CW		 2960static bool cursor_active(struct drm_device *dev, int pipe)
2961{
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 u32 state;
2964
2965 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 2966 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2967 else
5efb3e28 2968 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2969
2970 return state;
2971}
2972
2973static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2974{
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2976 u32 pos;
2977
5efb3e28 2978 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2979
2980 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2981 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2982 *x = -*x;
2983
2984 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2985 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2986 *y = -*y;
2987
2988 return cursor_active(dev, pipe);
2989}
2990
3abc4e09
RF		 2991static const char *plane_type(enum drm_plane_type type)
2992{
2993 switch (type) {
2994 case DRM_PLANE_TYPE_OVERLAY:
2995 return "OVL";
2996 case DRM_PLANE_TYPE_PRIMARY:
2997 return "PRI";
2998 case DRM_PLANE_TYPE_CURSOR:
2999 return "CUR";
3000 /*
3001 * Deliberately omitting default: to generate compiler warnings
3002 * when a new drm_plane_type gets added.
3003 */
3004 }
3005
3006 return "unknown";
3007}
3008
3009static const char *plane_rotation(unsigned int rotation)
3010{
3011 static char buf[48];
3012 /*
3013 * According to doc only one DRM_ROTATE_ is allowed but this
3014 * will print them all to visualize if the values are misused
3015 */
3016 snprintf(buf, sizeof(buf),
3017 "%s%s%s%s%s%s(0x%08x)",
3018 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3019 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3020 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3021 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3022 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3023 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3024 rotation);
3025
3026 return buf;
3027}
3028
3029static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3030{
3031 struct drm_info_node *node = m->private;
3032 struct drm_device *dev = node->minor->dev;
3033 struct intel_plane *intel_plane;
3034
3035 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3036 struct drm_plane_state *state;
3037 struct drm_plane *plane = &intel_plane->base;
3038
3039 if (!plane->state) {
3040 seq_puts(m, "plane->state is NULL!\n");
3041 continue;
3042 }
3043
3044 state = plane->state;
3045
3046 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3047 plane->base.id,
3048 plane_type(intel_plane->base.type),
3049 state->crtc_x, state->crtc_y,
3050 state->crtc_w, state->crtc_h,
3051 (state->src_x >> 16),
3052 ((state->src_x & 0xffff) * 15625) >> 10,
3053 (state->src_y >> 16),
3054 ((state->src_y & 0xffff) * 15625) >> 10,
3055 (state->src_w >> 16),
3056 ((state->src_w & 0xffff) * 15625) >> 10,
3057 (state->src_h >> 16),
3058 ((state->src_h & 0xffff) * 15625) >> 10,
3059 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3060 plane_rotation(state->rotation));
3061 }
3062}
3063
3064static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3065{
3066 struct intel_crtc_state *pipe_config;
3067 int num_scalers = intel_crtc->num_scalers;
3068 int i;
3069
3070 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3071
3072 /* Not all platformas have a scaler */
3073 if (num_scalers) {
3074 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3075 num_scalers,
3076 pipe_config->scaler_state.scaler_users,
3077 pipe_config->scaler_state.scaler_id);
3078
3079 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3080 struct intel_scaler *sc =
3081 &pipe_config->scaler_state.scalers[i];
3082
3083 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3084 i, yesno(sc->in_use), sc->mode);
3085 }
3086 seq_puts(m, "\n");
3087 } else {
3088 seq_puts(m, "\tNo scalers available on this platform\n");
3089 }
3090}
3091
53f5e3ca
JB		 3092static int i915_display_info(struct seq_file *m, void *unused)
3093{
9f25d007 3094 struct drm_info_node *node = m->private;
53f5e3ca 3095 struct drm_device *dev = node->minor->dev;
b0e5ddf3 3096 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 3097 struct intel_crtc *crtc;
53f5e3ca
JB		 3098 struct drm_connector *connector;
3099
b0e5ddf3 3100 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3101 drm_modeset_lock_all(dev);
3102 seq_printf(m, "CRTC info\n");
3103 seq_printf(m, "---------\n");
d3fcc808 3104 for_each_intel_crtc(dev, crtc) {
065f2ec2 3105 bool active;
f77076c9 3106 struct intel_crtc_state *pipe_config;
065f2ec2 3107 int x, y;
53f5e3ca 3108
f77076c9
ML		 3109 pipe_config = to_intel_crtc_state(crtc->base.state);
3110
3abc4e09 3111 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3112 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3113 yesno(pipe_config->base.active),
3abc4e09
RF		 3114 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3115 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3116
f77076c9 3117 if (pipe_config->base.active) {
065f2ec2
CW		 3118 intel_crtc_info(m, crtc);
3119
a23dc658 3120 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 3121 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3122 yesno(crtc->cursor_base),
3dd512fb
MR		 3123 x, y, crtc->base.cursor->state->crtc_w,
3124 crtc->base.cursor->state->crtc_h,
57127efa 3125 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3126 intel_scaler_info(m, crtc);
3127 intel_plane_info(m, crtc);
a23dc658 3128 }
cace841c
DV		 3129
3130 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3131 yesno(!crtc->cpu_fifo_underrun_disabled),
3132 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3133 }
3134
3135 seq_printf(m, "\n");
3136 seq_printf(m, "Connector info\n");
3137 seq_printf(m, "--------------\n");
3138 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3139 intel_connector_info(m, connector);
3140 }
3141 drm_modeset_unlock_all(dev);
b0e5ddf3 3142 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3143
3144 return 0;
3145}
3146
e04934cf
BW		 3147static int i915_semaphore_status(struct seq_file *m, void *unused)
3148{
3149 struct drm_info_node *node = (struct drm_info_node *) m->private;
3150 struct drm_device *dev = node->minor->dev;
3151 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 3152 struct intel_engine_cs *engine;
e04934cf 3153 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
c3232b18
DG		 3154 enum intel_engine_id id;
3155 int j, ret;
e04934cf
BW		 3156
3157 if (!i915_semaphore_is_enabled(dev)) {
3158 seq_puts(m, "Semaphores are disabled\n");
3159 return 0;
3160 }
3161
3162 ret = mutex_lock_interruptible(&dev->struct_mutex);
3163 if (ret)
3164 return ret;
03872064 3165 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3166
3167 if (IS_BROADWELL(dev)) {
3168 struct page *page;
3169 uint64_t *seqno;
3170
3171 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3172
3173 seqno = (uint64_t *)kmap_atomic(page);
c3232b18 3174 for_each_engine_id(engine, dev_priv, id) {
e04934cf
BW		 3175 uint64_t offset;
3176
e2f80391 3177 seq_printf(m, "%s\n", engine->name);
e04934cf
BW		 3178
3179 seq_puts(m, " Last signal:");
3180 for (j = 0; j < num_rings; j++) {
c3232b18 3181 offset = id * I915_NUM_ENGINES + j;
e04934cf
BW		 3182 seq_printf(m, "0x%08llx (0x%02llx) ",
3183 seqno[offset], offset * 8);
3184 }
3185 seq_putc(m, '\n');
3186
3187 seq_puts(m, " Last wait: ");
3188 for (j = 0; j < num_rings; j++) {
c3232b18 3189 offset = id + (j * I915_NUM_ENGINES);
e04934cf
BW		 3190 seq_printf(m, "0x%08llx (0x%02llx) ",
3191 seqno[offset], offset * 8);
3192 }
3193 seq_putc(m, '\n');
3194
3195 }
3196 kunmap_atomic(seqno);
3197 } else {
3198 seq_puts(m, " Last signal:");
b4ac5afc 3199 for_each_engine(engine, dev_priv)
e04934cf
BW		 3200 for (j = 0; j < num_rings; j++)
3201 seq_printf(m, "0x%08x\n",
e2f80391 3202 I915_READ(engine->semaphore.mbox.signal[j]));
e04934cf
BW		 3203 seq_putc(m, '\n');
3204 }
3205
3206 seq_puts(m, "\nSync seqno:\n");
b4ac5afc
DG		 3207 for_each_engine(engine, dev_priv) {
3208 for (j = 0; j < num_rings; j++)
e2f80391
TU		 3209 seq_printf(m, " 0x%08x ",
3210 engine->semaphore.sync_seqno[j]);
e04934cf
BW		 3211 seq_putc(m, '\n');
3212 }
3213 seq_putc(m, '\n');
3214
03872064 3215 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3216 mutex_unlock(&dev->struct_mutex);
3217 return 0;
3218}
3219
728e29d7
DV		 3220static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3221{
3222 struct drm_info_node *node = (struct drm_info_node *) m->private;
3223 struct drm_device *dev = node->minor->dev;
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 int i;
3226
3227 drm_modeset_lock_all(dev);
3228 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3229 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3230
3231 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2dd66ebd
ML		 3232 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3233 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
728e29d7 3234 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3235 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3236 seq_printf(m, " dpll_md: 0x%08x\n",
3237 pll->config.hw_state.dpll_md);
3238 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3239 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3240 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3241 }
3242 drm_modeset_unlock_all(dev);
3243
3244 return 0;
3245}
3246
1ed1ef9d 3247static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3248{
3249 int i;
3250 int ret;
e2f80391 3251 struct intel_engine_cs *engine;
888b5995
AS		 3252 struct drm_info_node *node = (struct drm_info_node *) m->private;
3253 struct drm_device *dev = node->minor->dev;
3254 struct drm_i915_private *dev_priv = dev->dev_private;
33136b06 3255 struct i915_workarounds *workarounds = &dev_priv->workarounds;
c3232b18 3256 enum intel_engine_id id;
888b5995 3257
888b5995
AS		 3258 ret = mutex_lock_interruptible(&dev->struct_mutex);
3259 if (ret)
3260 return ret;
3261
3262 intel_runtime_pm_get(dev_priv);
3263
33136b06 3264 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
c3232b18 3265 for_each_engine_id(engine, dev_priv, id)
33136b06 3266 seq_printf(m, "HW whitelist count for %s: %d\n",
c3232b18 3267 engine->name, workarounds->hw_whitelist_count[id]);
33136b06 3268 for (i = 0; i < workarounds->count; ++i) {
f0f59a00
VS		 3269 i915_reg_t addr;
3270 u32 mask, value, read;
2fa60f6d 3271 bool ok;
888b5995 3272
33136b06
AS		 3273 addr = workarounds->reg[i].addr;
3274 mask = workarounds->reg[i].mask;
3275 value = workarounds->reg[i].value;
2fa60f6d
MK		 3276 read = I915_READ(addr);
3277 ok = (value & mask) == (read & mask);
3278 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
f0f59a00 3279 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3280 }
3281
3282 intel_runtime_pm_put(dev_priv);
3283 mutex_unlock(&dev->struct_mutex);
3284
3285 return 0;
3286}
3287
c5511e44
DL		 3288static int i915_ddb_info(struct seq_file *m, void *unused)
3289{
3290 struct drm_info_node *node = m->private;
3291 struct drm_device *dev = node->minor->dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct skl_ddb_allocation *ddb;
3294 struct skl_ddb_entry *entry;
3295 enum pipe pipe;
3296 int plane;
3297
2fcffe19
DL		 3298 if (INTEL_INFO(dev)->gen < 9)
3299 return 0;
3300
c5511e44
DL		 3301 drm_modeset_lock_all(dev);
3302
3303 ddb = &dev_priv->wm.skl_hw.ddb;
3304
3305 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3306
3307 for_each_pipe(dev_priv, pipe) {
3308 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3309
dd740780 3310 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3311 entry = &ddb->plane[pipe][plane];
3312 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3313 entry->start, entry->end,
3314 skl_ddb_entry_size(entry));
3315 }
3316
4969d33e 3317 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3318 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3319 entry->end, skl_ddb_entry_size(entry));
3320 }
3321
3322 drm_modeset_unlock_all(dev);
3323
3324 return 0;
3325}
3326
a54746e3
VK		 3327static void drrs_status_per_crtc(struct seq_file *m,
3328 struct drm_device *dev, struct intel_crtc *intel_crtc)
3329{
3330 struct intel_encoder *intel_encoder;
3331 struct drm_i915_private *dev_priv = dev->dev_private;
3332 struct i915_drrs *drrs = &dev_priv->drrs;
3333 int vrefresh = 0;
3334
3335 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3336 /* Encoder connected on this CRTC */
3337 switch (intel_encoder->type) {
3338 case INTEL_OUTPUT_EDP:
3339 seq_puts(m, "eDP:\n");
3340 break;
3341 case INTEL_OUTPUT_DSI:
3342 seq_puts(m, "DSI:\n");
3343 break;
3344 case INTEL_OUTPUT_HDMI:
3345 seq_puts(m, "HDMI:\n");
3346 break;
3347 case INTEL_OUTPUT_DISPLAYPORT:
3348 seq_puts(m, "DP:\n");
3349 break;
3350 default:
3351 seq_printf(m, "Other encoder (id=%d).\n",
3352 intel_encoder->type);
3353 return;
3354 }
3355 }
3356
3357 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3358 seq_puts(m, "\tVBT: DRRS_type: Static");
3359 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3360 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3361 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3362 seq_puts(m, "\tVBT: DRRS_type: None");
3363 else
3364 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3365
3366 seq_puts(m, "\n\n");
3367
f77076c9 3368 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3369 struct intel_panel *panel;
3370
3371 mutex_lock(&drrs->mutex);
3372 /* DRRS Supported */
3373 seq_puts(m, "\tDRRS Supported: Yes\n");
3374
3375 /* disable_drrs() will make drrs->dp NULL */
3376 if (!drrs->dp) {
3377 seq_puts(m, "Idleness DRRS: Disabled");
3378 mutex_unlock(&drrs->mutex);
3379 return;
3380 }
3381
3382 panel = &drrs->dp->attached_connector->panel;
3383 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3384 drrs->busy_frontbuffer_bits);
3385
3386 seq_puts(m, "\n\t\t");
3387 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3388 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3389 vrefresh = panel->fixed_mode->vrefresh;
3390 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3391 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3392 vrefresh = panel->downclock_mode->vrefresh;
3393 } else {
3394 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3395 drrs->refresh_rate_type);
3396 mutex_unlock(&drrs->mutex);
3397 return;
3398 }
3399 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3400
3401 seq_puts(m, "\n\t\t");
3402 mutex_unlock(&drrs->mutex);
3403 } else {
3404 /* DRRS not supported. Print the VBT parameter*/
3405 seq_puts(m, "\tDRRS Supported : No");
3406 }
3407 seq_puts(m, "\n");
3408}
3409
3410static int i915_drrs_status(struct seq_file *m, void *unused)
3411{
3412 struct drm_info_node *node = m->private;
3413 struct drm_device *dev = node->minor->dev;
3414 struct intel_crtc *intel_crtc;
3415 int active_crtc_cnt = 0;
3416
3417 for_each_intel_crtc(dev, intel_crtc) {
3418 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3419
f77076c9 3420 if (intel_crtc->base.state->active) {
a54746e3
VK		 3421 active_crtc_cnt++;
3422 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3423
3424 drrs_status_per_crtc(m, dev, intel_crtc);
3425 }
3426
3427 drm_modeset_unlock(&intel_crtc->base.mutex);
3428 }
3429
3430 if (!active_crtc_cnt)
3431 seq_puts(m, "No active crtc found\n");
3432
3433 return 0;
3434}
3435
07144428
DL		 3436struct pipe_crc_info {
3437 const char *name;
3438 struct drm_device *dev;
3439 enum pipe pipe;
3440};
3441
11bed958
DA		 3442static int i915_dp_mst_info(struct seq_file *m, void *unused)
3443{
3444 struct drm_info_node *node = (struct drm_info_node *) m->private;
3445 struct drm_device *dev = node->minor->dev;
3446 struct drm_encoder *encoder;
3447 struct intel_encoder *intel_encoder;
3448 struct intel_digital_port *intel_dig_port;
3449 drm_modeset_lock_all(dev);
3450 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3451 intel_encoder = to_intel_encoder(encoder);
3452 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3453 continue;
3454 intel_dig_port = enc_to_dig_port(encoder);
3455 if (!intel_dig_port->dp.can_mst)
3456 continue;
3457
3458 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3459 }
3460 drm_modeset_unlock_all(dev);
3461 return 0;
3462}
3463
07144428
DL		 3464static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3465{
be5c7a90
DL		 3466 struct pipe_crc_info *info = inode->i_private;
3467 struct drm_i915_private *dev_priv = info->dev->dev_private;
3468 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3469
7eb1c496
DV		 3470 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3471 return -ENODEV;
3472
d538bbdf
DL		 3473 spin_lock_irq(&pipe_crc->lock);
3474
3475 if (pipe_crc->opened) {
3476 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3477 return -EBUSY; /* already open */
3478 }
3479
d538bbdf 3480 pipe_crc->opened = true;
07144428
DL		 3481 filep->private_data = inode->i_private;
3482
d538bbdf
DL		 3483 spin_unlock_irq(&pipe_crc->lock);
3484
07144428
DL		 3485 return 0;
3486}
3487
3488static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3489{
be5c7a90
DL		 3490 struct pipe_crc_info *info = inode->i_private;
3491 struct drm_i915_private *dev_priv = info->dev->dev_private;
3492 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3493
d538bbdf
DL		 3494 spin_lock_irq(&pipe_crc->lock);
3495 pipe_crc->opened = false;
3496 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3497
07144428
DL		 3498 return 0;
3499}
3500
3501/* (6 fields, 8 chars each, space separated (5) + '\n') */
3502#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3503/* account for \'0' */
3504#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3505
3506static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3507{
d538bbdf
DL		 3508 assert_spin_locked(&pipe_crc->lock);
3509 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3510 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3511}
3512
3513static ssize_t
3514i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3515 loff_t *pos)
3516{
3517 struct pipe_crc_info *info = filep->private_data;
3518 struct drm_device *dev = info->dev;
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3521 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3522 int n_entries;
07144428
DL		 3523 ssize_t bytes_read;
3524
3525 /*
3526 * Don't allow user space to provide buffers not big enough to hold
3527 * a line of data.
3528 */
3529 if (count < PIPE_CRC_LINE_LEN)
3530 return -EINVAL;
3531
3532 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3533 return 0;
07144428
DL		 3534
3535 /* nothing to read */
d538bbdf 3536 spin_lock_irq(&pipe_crc->lock);
07144428 3537 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3538 int ret;
3539
3540 if (filep->f_flags & O_NONBLOCK) {
3541 spin_unlock_irq(&pipe_crc->lock);
07144428 3542 return -EAGAIN;
d538bbdf 3543 }
07144428 3544
d538bbdf
DL		 3545 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3546 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3547 if (ret) {
3548 spin_unlock_irq(&pipe_crc->lock);
3549 return ret;
3550 }
8bf1e9f1
SH		 3551 }
3552
07144428 3553 /* We now have one or more entries to read */
9ad6d99f 3554 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3555
07144428 3556 bytes_read = 0;
9ad6d99f
VS		 3557 while (n_entries > 0) {
3558 struct intel_pipe_crc_entry *entry =
3559 &pipe_crc->entries[pipe_crc->tail];
07144428 3560 int ret;
8bf1e9f1 3561
9ad6d99f
VS		 3562 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3563 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3564 break;
3565
3566 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3567 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3568
07144428
DL		 3569 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3570 "%8u %8x %8x %8x %8x %8x\n",
3571 entry->frame, entry->crc[0],
3572 entry->crc[1], entry->crc[2],
3573 entry->crc[3], entry->crc[4]);
3574
9ad6d99f
VS		 3575 spin_unlock_irq(&pipe_crc->lock);
3576
3577 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3578 if (ret == PIPE_CRC_LINE_LEN)
3579 return -EFAULT;
b2c88f5b 3580
9ad6d99f
VS		 3581 user_buf += PIPE_CRC_LINE_LEN;
3582 n_entries--;
3583
3584 spin_lock_irq(&pipe_crc->lock);
3585 }
8bf1e9f1 3586
d538bbdf
DL		 3587 spin_unlock_irq(&pipe_crc->lock);
3588
07144428
DL		 3589 return bytes_read;
3590}
3591
3592static const struct file_operations i915_pipe_crc_fops = {
3593 .owner = THIS_MODULE,
3594 .open = i915_pipe_crc_open,
3595 .read = i915_pipe_crc_read,
3596 .release = i915_pipe_crc_release,
3597};
3598
3599static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3600 {
3601 .name = "i915_pipe_A_crc",
3602 .pipe = PIPE_A,
3603 },
3604 {
3605 .name = "i915_pipe_B_crc",
3606 .pipe = PIPE_B,
3607 },
3608 {
3609 .name = "i915_pipe_C_crc",
3610 .pipe = PIPE_C,
3611 },
3612};
3613
3614static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3615 enum pipe pipe)
3616{
3617 struct drm_device *dev = minor->dev;
3618 struct dentry *ent;
3619 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3620
3621 info->dev = dev;
3622 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3623 &i915_pipe_crc_fops);
f3c5fe97
WY		 3624 if (!ent)
3625 return -ENOMEM;
07144428
DL		 3626
3627 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3628}
3629
e8dfcf78 3630static const char * const pipe_crc_sources[] = {
926321d5
DV		 3631 "none",
3632 "plane1",
3633 "plane2",
3634 "pf",
5b3a856b 3635 "pipe",
3d099a05
DV		 3636 "TV",
3637 "DP-B",
3638 "DP-C",
3639 "DP-D",
46a19188 3640 "auto",
926321d5
DV		 3641};
3642
3643static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3644{
3645 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3646 return pipe_crc_sources[source];
3647}
3648
bd9db02f 3649static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3650{
3651 struct drm_device *dev = m->private;
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653 int i;
3654
3655 for (i = 0; i < I915_MAX_PIPES; i++)
3656 seq_printf(m, "%c %s\n", pipe_name(i),
3657 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3658
3659 return 0;
3660}
3661
bd9db02f 3662static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3663{
3664 struct drm_device *dev = inode->i_private;
3665
bd9db02f 3666 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3667}
3668
46a19188 3669static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3670 uint32_t *val)
3671{
46a19188
DV		 3672 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3673 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3674
3675 switch (*source) {
52f843f6
DV		 3676 case INTEL_PIPE_CRC_SOURCE_PIPE:
3677 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3678 break;
3679 case INTEL_PIPE_CRC_SOURCE_NONE:
3680 *val = 0;
3681 break;
3682 default:
3683 return -EINVAL;
3684 }
3685
3686 return 0;
3687}
3688
46a19188
DV		 3689static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3690 enum intel_pipe_crc_source *source)
3691{
3692 struct intel_encoder *encoder;
3693 struct intel_crtc *crtc;
26756809 3694 struct intel_digital_port *dig_port;
46a19188
DV		 3695 int ret = 0;
3696
3697 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3698
6e9f798d 3699 drm_modeset_lock_all(dev);
b2784e15 3700 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3701 if (!encoder->base.crtc)
3702 continue;
3703
3704 crtc = to_intel_crtc(encoder->base.crtc);
3705
3706 if (crtc->pipe != pipe)
3707 continue;
3708
3709 switch (encoder->type) {
3710 case INTEL_OUTPUT_TVOUT:
3711 *source = INTEL_PIPE_CRC_SOURCE_TV;
3712 break;
3713 case INTEL_OUTPUT_DISPLAYPORT:
3714 case INTEL_OUTPUT_EDP:
26756809
DV		 3715 dig_port = enc_to_dig_port(&encoder->base);
3716 switch (dig_port->port) {
3717 case PORT_B:
3718 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3719 break;
3720 case PORT_C:
3721 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3722 break;
3723 case PORT_D:
3724 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3725 break;
3726 default:
3727 WARN(1, "nonexisting DP port %c\n",
3728 port_name(dig_port->port));
3729 break;
3730 }
46a19188 3731 break;
6847d71b
PZ		 3732 default:
3733 break;
46a19188
DV		 3734 }
3735 }
6e9f798d 3736 drm_modeset_unlock_all(dev);
46a19188
DV		 3737
3738 return ret;
3739}
3740
3741static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3742 enum pipe pipe,
3743 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3744 uint32_t *val)
3745{
8d2f24ca
DV		 3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 bool need_stable_symbols = false;
3748
46a19188
DV		 3749 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3750 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3751 if (ret)
3752 return ret;
3753 }
3754
3755 switch (*source) {
7ac0129b
DV		 3756 case INTEL_PIPE_CRC_SOURCE_PIPE:
3757 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3758 break;
3759 case INTEL_PIPE_CRC_SOURCE_DP_B:
3760 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3761 need_stable_symbols = true;
7ac0129b
DV		 3762 break;
3763 case INTEL_PIPE_CRC_SOURCE_DP_C:
3764 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3765 need_stable_symbols = true;
7ac0129b 3766 break;
2be57922
VS		 3767 case INTEL_PIPE_CRC_SOURCE_DP_D:
3768 if (!IS_CHERRYVIEW(dev))
3769 return -EINVAL;
3770 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3771 need_stable_symbols = true;
3772 break;
7ac0129b
DV		 3773 case INTEL_PIPE_CRC_SOURCE_NONE:
3774 *val = 0;
3775 break;
3776 default:
3777 return -EINVAL;
3778 }
3779
8d2f24ca
DV		 3780 /*
3781 * When the pipe CRC tap point is after the transcoders we need
3782 * to tweak symbol-level features to produce a deterministic series of
3783 * symbols for a given frame. We need to reset those features only once
3784 * a frame (instead of every nth symbol):
3785 * - DC-balance: used to ensure a better clock recovery from the data
3786 * link (SDVO)
3787 * - DisplayPort scrambling: used for EMI reduction
3788 */
3789 if (need_stable_symbols) {
3790 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3791
8d2f24ca 3792 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3793 switch (pipe) {
3794 case PIPE_A:
8d2f24ca 3795 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3796 break;
3797 case PIPE_B:
8d2f24ca 3798 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3799 break;
3800 case PIPE_C:
3801 tmp |= PIPE_C_SCRAMBLE_RESET;
3802 break;
3803 default:
3804 return -EINVAL;
3805 }
8d2f24ca
DV		 3806 I915_WRITE(PORT_DFT2_G4X, tmp);
3807 }
3808
7ac0129b
DV		 3809 return 0;
3810}
3811
4b79ebf7 3812static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3813 enum pipe pipe,
3814 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3815 uint32_t *val)
3816{
84093603
DV		 3817 struct drm_i915_private *dev_priv = dev->dev_private;
3818 bool need_stable_symbols = false;
3819
46a19188
DV		 3820 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3821 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3822 if (ret)
3823 return ret;
3824 }
3825
3826 switch (*source) {
4b79ebf7
DV		 3827 case INTEL_PIPE_CRC_SOURCE_PIPE:
3828 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3829 break;
3830 case INTEL_PIPE_CRC_SOURCE_TV:
3831 if (!SUPPORTS_TV(dev))
3832 return -EINVAL;
3833 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3834 break;
3835 case INTEL_PIPE_CRC_SOURCE_DP_B:
3836 if (!IS_G4X(dev))
3837 return -EINVAL;
3838 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3839 need_stable_symbols = true;
4b79ebf7
DV		 3840 break;
3841 case INTEL_PIPE_CRC_SOURCE_DP_C:
3842 if (!IS_G4X(dev))
3843 return -EINVAL;
3844 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3845 need_stable_symbols = true;
4b79ebf7
DV		 3846 break;
3847 case INTEL_PIPE_CRC_SOURCE_DP_D:
3848 if (!IS_G4X(dev))
3849 return -EINVAL;
3850 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3851 need_stable_symbols = true;
4b79ebf7
DV		 3852 break;
3853 case INTEL_PIPE_CRC_SOURCE_NONE:
3854 *val = 0;
3855 break;
3856 default:
3857 return -EINVAL;
3858 }
3859
84093603
DV		 3860 /*
3861 * When the pipe CRC tap point is after the transcoders we need
3862 * to tweak symbol-level features to produce a deterministic series of
3863 * symbols for a given frame. We need to reset those features only once
3864 * a frame (instead of every nth symbol):
3865 * - DC-balance: used to ensure a better clock recovery from the data
3866 * link (SDVO)
3867 * - DisplayPort scrambling: used for EMI reduction
3868 */
3869 if (need_stable_symbols) {
3870 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3871
3872 WARN_ON(!IS_G4X(dev));
3873
3874 I915_WRITE(PORT_DFT_I9XX,
3875 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3876
3877 if (pipe == PIPE_A)
3878 tmp |= PIPE_A_SCRAMBLE_RESET;
3879 else
3880 tmp |= PIPE_B_SCRAMBLE_RESET;
3881
3882 I915_WRITE(PORT_DFT2_G4X, tmp);
3883 }
3884
4b79ebf7
DV		 3885 return 0;
3886}
3887
8d2f24ca
DV		 3888static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3889 enum pipe pipe)
3890{
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3893
eb736679
VS		 3894 switch (pipe) {
3895 case PIPE_A:
8d2f24ca 3896 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3897 break;
3898 case PIPE_B:
8d2f24ca 3899 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3900 break;
3901 case PIPE_C:
3902 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3903 break;
3904 default:
3905 return;
3906 }
8d2f24ca
DV		 3907 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3908 tmp &= ~DC_BALANCE_RESET_VLV;
3909 I915_WRITE(PORT_DFT2_G4X, tmp);
3910
3911}
3912
84093603
DV		 3913static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3914 enum pipe pipe)
3915{
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3918
3919 if (pipe == PIPE_A)
3920 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3921 else
3922 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3923 I915_WRITE(PORT_DFT2_G4X, tmp);
3924
3925 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3926 I915_WRITE(PORT_DFT_I9XX,
3927 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3928 }
3929}
3930
46a19188 3931static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3932 uint32_t *val)
3933{
46a19188
DV		 3934 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3935 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3936
3937 switch (*source) {
5b3a856b
DV		 3938 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3939 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3940 break;
3941 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3942 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3943 break;
5b3a856b
DV		 3944 case INTEL_PIPE_CRC_SOURCE_PIPE:
3945 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3946 break;
3d099a05 3947 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3948 *val = 0;
3949 break;
3d099a05
DV		 3950 default:
3951 return -EINVAL;
5b3a856b
DV		 3952 }
3953
3954 return 0;
3955}
3956
c4e2d043 3957static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3958{
3959 struct drm_i915_private *dev_priv = dev->dev_private;
3960 struct intel_crtc *crtc =
3961 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3962 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3963 struct drm_atomic_state *state;
3964 int ret = 0;
fabf6e51
DV		 3965
3966 drm_modeset_lock_all(dev);
c4e2d043
ML		 3967 state = drm_atomic_state_alloc(dev);
3968 if (!state) {
3969 ret = -ENOMEM;
3970 goto out;
fabf6e51 3971 }
fabf6e51 3972
c4e2d043
ML		 3973 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3974 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3975 if (IS_ERR(pipe_config)) {
3976 ret = PTR_ERR(pipe_config);
3977 goto out;
3978 }
fabf6e51 3979
c4e2d043
ML		 3980 pipe_config->pch_pfit.force_thru = enable;
3981 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3982 pipe_config->pch_pfit.enabled != enable)
3983 pipe_config->base.connectors_changed = true;
1b509259 3984
c4e2d043
ML		 3985 ret = drm_atomic_commit(state);
3986out:
fabf6e51 3987 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3988 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3989 if (ret)
3990 drm_atomic_state_free(state);
fabf6e51
DV		 3991}
3992
3993static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3994 enum pipe pipe,
3995 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3996 uint32_t *val)
3997{
46a19188
DV		 3998 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3999 *source = INTEL_PIPE_CRC_SOURCE_PF;
4000
4001 switch (*source) {
5b3a856b
DV		 4002 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4003 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4004 break;
4005 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4006 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4007 break;
4008 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 4009 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4010 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 4011
5b3a856b
DV		 4012 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4013 break;
3d099a05 4014 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 4015 *val = 0;
4016 break;
3d099a05
DV		 4017 default:
4018 return -EINVAL;
5b3a856b
DV		 4019 }
4020
4021 return 0;
4022}
4023
926321d5
DV		 4024static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4025 enum intel_pipe_crc_source source)
4026{
4027 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 4028 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 4029 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4030 pipe));
e129649b 4031 enum intel_display_power_domain power_domain;
432f3342 4032 u32 val = 0; /* shut up gcc */
5b3a856b 4033 int ret;
926321d5 4034
cc3da175
DL		 4035 if (pipe_crc->source == source)
4036 return 0;
4037
ae676fcd
DL		 4038 /* forbid changing the source without going back to 'none' */
4039 if (pipe_crc->source && source)
4040 return -EINVAL;
4041
e129649b
ID		 4042 power_domain = POWER_DOMAIN_PIPE(pipe);
4043 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9d8b0588
DV		 4044 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4045 return -EIO;
4046 }
4047
52f843f6 4048 if (IS_GEN2(dev))
46a19188 4049 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 4050 else if (INTEL_INFO(dev)->gen < 5)
46a19188 4051 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
666a4537 4052 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
fabf6e51 4053 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 4054 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 4055 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 4056 else
fabf6e51 4057 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 4058
4059 if (ret != 0)
e129649b 4060 goto out;
5b3a856b 4061
4b584369
DL		 4062 /* none -> real source transition */
4063 if (source) {
4252fbc3
VS		 4064 struct intel_pipe_crc_entry *entries;
4065
7cd6ccff
DL		 4066 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4067 pipe_name(pipe), pipe_crc_source_name(source));
4068
3cf54b34
VS		 4069 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4070 sizeof(pipe_crc->entries[0]),
4252fbc3 4071 GFP_KERNEL);
e129649b
ID		 4072 if (!entries) {
4073 ret = -ENOMEM;
4074 goto out;
4075 }
e5f75aca 4076
8c740dce
PZ		 4077 /*
4078 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4079 * enabled and disabled dynamically based on package C states,
4080 * user space can't make reliable use of the CRCs, so let's just
4081 * completely disable it.
4082 */
4083 hsw_disable_ips(crtc);
4084
d538bbdf 4085 spin_lock_irq(&pipe_crc->lock);
64387b61 4086 kfree(pipe_crc->entries);
4252fbc3 4087 pipe_crc->entries = entries;
d538bbdf
DL		 4088 pipe_crc->head = 0;
4089 pipe_crc->tail = 0;
4090 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4091 }
4092
cc3da175 4093 pipe_crc->source = source;
926321d5 4094
926321d5
DV		 4095 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4096 POSTING_READ(PIPE_CRC_CTL(pipe));
4097
e5f75aca
DL		 4098 /* real source -> none transition */
4099 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4100 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4101 struct intel_crtc *crtc =
4102 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4103
7cd6ccff
DL		 4104 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4105 pipe_name(pipe));
4106
a33d7105 4107 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4108 if (crtc->base.state->active)
a33d7105
DV		 4109 intel_wait_for_vblank(dev, pipe);
4110 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4111
d538bbdf
DL		 4112 spin_lock_irq(&pipe_crc->lock);
4113 entries = pipe_crc->entries;
e5f75aca 4114 pipe_crc->entries = NULL;
9ad6d99f
VS		 4115 pipe_crc->head = 0;
4116 pipe_crc->tail = 0;
d538bbdf
DL		 4117 spin_unlock_irq(&pipe_crc->lock);
4118
4119 kfree(entries);
84093603
DV		 4120
4121 if (IS_G4X(dev))
4122 g4x_undo_pipe_scramble_reset(dev, pipe);
666a4537 4123 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
8d2f24ca 4124 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 4125 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4126 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 4127
4128 hsw_enable_ips(crtc);
e5f75aca
DL		 4129 }
4130
e129649b
ID		 4131 ret = 0;
4132
4133out:
4134 intel_display_power_put(dev_priv, power_domain);
4135
4136 return ret;
926321d5
DV		 4137}
4138
4139/*
4140 * Parse pipe CRC command strings:
b94dec87
DL		 4141 * command: wsp* object wsp+ name wsp+ source wsp*
4142 * object: 'pipe'
4143 * name: (A | B | C)
926321d5
DV		 4144 * source: (none | plane1 | plane2 | pf)
4145 * wsp: (#0x20 | #0x9 | #0xA)+
4146 *
4147 * eg.:
b94dec87
DL		 4148 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4149 * "pipe A none" -> Stop CRC
926321d5 4150 */
bd9db02f 4151static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4152{
4153 int n_words = 0;
4154
4155 while (*buf) {
4156 char *end;
4157
4158 /* skip leading white space */
4159 buf = skip_spaces(buf);
4160 if (!*buf)
4161 break; /* end of buffer */
4162
4163 /* find end of word */
4164 for (end = buf; *end && !isspace(*end); end++)
4165 ;
4166
4167 if (n_words == max_words) {
4168 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4169 max_words);
4170 return -EINVAL; /* ran out of words[] before bytes */
4171 }
4172
4173 if (*end)
4174 *end++ = '\0';
4175 words[n_words++] = buf;
4176 buf = end;
4177 }
4178
4179 return n_words;
4180}
4181
b94dec87
DL		 4182enum intel_pipe_crc_object {
4183 PIPE_CRC_OBJECT_PIPE,
4184};
4185
e8dfcf78 4186static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4187 "pipe",
4188};
4189
4190static int
bd9db02f 4191display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4192{
4193 int i;
4194
4195 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4196 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4197 *o = i;
b94dec87
DL		 4198 return 0;
4199 }
4200
4201 return -EINVAL;
4202}
4203
bd9db02f 4204static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4205{
4206 const char name = buf[0];
4207
4208 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4209 return -EINVAL;
4210
4211 *pipe = name - 'A';
4212
4213 return 0;
4214}
4215
4216static int
bd9db02f 4217display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4218{
4219 int i;
4220
4221 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4222 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4223 *s = i;
926321d5
DV		 4224 return 0;
4225 }
4226
4227 return -EINVAL;
4228}
4229
bd9db02f 4230static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4231{
b94dec87 4232#define N_WORDS 3
926321d5 4233 int n_words;
b94dec87 4234 char *words[N_WORDS];
926321d5 4235 enum pipe pipe;
b94dec87 4236 enum intel_pipe_crc_object object;
926321d5
DV		 4237 enum intel_pipe_crc_source source;
4238
bd9db02f 4239 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4240 if (n_words != N_WORDS) {
4241 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4242 N_WORDS);
4243 return -EINVAL;
4244 }
4245
bd9db02f 4246 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4247 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4248 return -EINVAL;
4249 }
4250
bd9db02f 4251 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4252 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4253 return -EINVAL;
4254 }
4255
bd9db02f 4256 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4257 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4258 return -EINVAL;
4259 }
4260
4261 return pipe_crc_set_source(dev, pipe, source);
4262}
4263
bd9db02f
DL		 4264static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4265 size_t len, loff_t *offp)
926321d5
DV		 4266{
4267 struct seq_file *m = file->private_data;
4268 struct drm_device *dev = m->private;
4269 char *tmpbuf;
4270 int ret;
4271
4272 if (len == 0)
4273 return 0;
4274
4275 if (len > PAGE_SIZE - 1) {
4276 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4277 PAGE_SIZE);
4278 return -E2BIG;
4279 }
4280
4281 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4282 if (!tmpbuf)
4283 return -ENOMEM;
4284
4285 if (copy_from_user(tmpbuf, ubuf, len)) {
4286 ret = -EFAULT;
4287 goto out;
4288 }
4289 tmpbuf[len] = '\0';
4290
bd9db02f 4291 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4292
4293out:
4294 kfree(tmpbuf);
4295 if (ret < 0)
4296 return ret;
4297
4298 *offp += len;
4299 return len;
4300}
4301
bd9db02f 4302static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4303 .owner = THIS_MODULE,
bd9db02f 4304 .open = display_crc_ctl_open,
926321d5
DV		 4305 .read = seq_read,
4306 .llseek = seq_lseek,
4307 .release = single_release,
bd9db02f 4308 .write = display_crc_ctl_write
926321d5
DV		 4309};
4310
eb3394fa
TP		 4311static ssize_t i915_displayport_test_active_write(struct file *file,
4312 const char __user *ubuf,
4313 size_t len, loff_t *offp)
4314{
4315 char *input_buffer;
4316 int status = 0;
eb3394fa
TP		 4317 struct drm_device *dev;
4318 struct drm_connector *connector;
4319 struct list_head *connector_list;
4320 struct intel_dp *intel_dp;
4321 int val = 0;
4322
9aaffa34 4323 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4324
eb3394fa
TP		 4325 connector_list = &dev->mode_config.connector_list;
4326
4327 if (len == 0)
4328 return 0;
4329
4330 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4331 if (!input_buffer)
4332 return -ENOMEM;
4333
4334 if (copy_from_user(input_buffer, ubuf, len)) {
4335 status = -EFAULT;
4336 goto out;
4337 }
4338
4339 input_buffer[len] = '\0';
4340 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4341
4342 list_for_each_entry(connector, connector_list, head) {
4343
4344 if (connector->connector_type !=
4345 DRM_MODE_CONNECTOR_DisplayPort)
4346 continue;
4347
b8bb08ec 4348 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4349 connector->encoder != NULL) {
4350 intel_dp = enc_to_intel_dp(connector->encoder);
4351 status = kstrtoint(input_buffer, 10, &val);
4352 if (status < 0)
4353 goto out;
4354 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4355 /* To prevent erroneous activation of the compliance
4356 * testing code, only accept an actual value of 1 here
4357 */
4358 if (val == 1)
4359 intel_dp->compliance_test_active = 1;
4360 else
4361 intel_dp->compliance_test_active = 0;
4362 }
4363 }
4364out:
4365 kfree(input_buffer);
4366 if (status < 0)
4367 return status;
4368
4369 *offp += len;
4370 return len;
4371}
4372
4373static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4374{
4375 struct drm_device *dev = m->private;
4376 struct drm_connector *connector;
4377 struct list_head *connector_list = &dev->mode_config.connector_list;
4378 struct intel_dp *intel_dp;
4379
eb3394fa
TP		 4380 list_for_each_entry(connector, connector_list, head) {
4381
4382 if (connector->connector_type !=
4383 DRM_MODE_CONNECTOR_DisplayPort)
4384 continue;
4385
4386 if (connector->status == connector_status_connected &&
4387 connector->encoder != NULL) {
4388 intel_dp = enc_to_intel_dp(connector->encoder);
4389 if (intel_dp->compliance_test_active)
4390 seq_puts(m, "1");
4391 else
4392 seq_puts(m, "0");
4393 } else
4394 seq_puts(m, "0");
4395 }
4396
4397 return 0;
4398}
4399
4400static int i915_displayport_test_active_open(struct inode *inode,
4401 struct file *file)
4402{
4403 struct drm_device *dev = inode->i_private;
4404
4405 return single_open(file, i915_displayport_test_active_show, dev);
4406}
4407
4408static const struct file_operations i915_displayport_test_active_fops = {
4409 .owner = THIS_MODULE,
4410 .open = i915_displayport_test_active_open,
4411 .read = seq_read,
4412 .llseek = seq_lseek,
4413 .release = single_release,
4414 .write = i915_displayport_test_active_write
4415};
4416
4417static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4418{
4419 struct drm_device *dev = m->private;
4420 struct drm_connector *connector;
4421 struct list_head *connector_list = &dev->mode_config.connector_list;
4422 struct intel_dp *intel_dp;
4423
eb3394fa
TP		 4424 list_for_each_entry(connector, connector_list, head) {
4425
4426 if (connector->connector_type !=
4427 DRM_MODE_CONNECTOR_DisplayPort)
4428 continue;
4429
4430 if (connector->status == connector_status_connected &&
4431 connector->encoder != NULL) {
4432 intel_dp = enc_to_intel_dp(connector->encoder);
4433 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4434 } else
4435 seq_puts(m, "0");
4436 }
4437
4438 return 0;
4439}
4440static int i915_displayport_test_data_open(struct inode *inode,
4441 struct file *file)
4442{
4443 struct drm_device *dev = inode->i_private;
4444
4445 return single_open(file, i915_displayport_test_data_show, dev);
4446}
4447
4448static const struct file_operations i915_displayport_test_data_fops = {
4449 .owner = THIS_MODULE,
4450 .open = i915_displayport_test_data_open,
4451 .read = seq_read,
4452 .llseek = seq_lseek,
4453 .release = single_release
4454};
4455
4456static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4457{
4458 struct drm_device *dev = m->private;
4459 struct drm_connector *connector;
4460 struct list_head *connector_list = &dev->mode_config.connector_list;
4461 struct intel_dp *intel_dp;
4462
eb3394fa
TP		 4463 list_for_each_entry(connector, connector_list, head) {
4464
4465 if (connector->connector_type !=
4466 DRM_MODE_CONNECTOR_DisplayPort)
4467 continue;
4468
4469 if (connector->status == connector_status_connected &&
4470 connector->encoder != NULL) {
4471 intel_dp = enc_to_intel_dp(connector->encoder);
4472 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4473 } else
4474 seq_puts(m, "0");
4475 }
4476
4477 return 0;
4478}
4479
4480static int i915_displayport_test_type_open(struct inode *inode,
4481 struct file *file)
4482{
4483 struct drm_device *dev = inode->i_private;
4484
4485 return single_open(file, i915_displayport_test_type_show, dev);
4486}
4487
4488static const struct file_operations i915_displayport_test_type_fops = {
4489 .owner = THIS_MODULE,
4490 .open = i915_displayport_test_type_open,
4491 .read = seq_read,
4492 .llseek = seq_lseek,
4493 .release = single_release
4494};
4495
97e94b22 4496static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4497{
4498 struct drm_device *dev = m->private;
369a1342 4499 int level;
de38b95c
VS		 4500 int num_levels;
4501
4502 if (IS_CHERRYVIEW(dev))
4503 num_levels = 3;
4504 else if (IS_VALLEYVIEW(dev))
4505 num_levels = 1;
4506 else
4507 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4508
4509 drm_modeset_lock_all(dev);
4510
4511 for (level = 0; level < num_levels; level++) {
4512 unsigned int latency = wm[level];
4513
97e94b22
DL		 4514 /*
4515 * - WM1+ latency values in 0.5us units
de38b95c 4516 * - latencies are in us on gen9/vlv/chv
97e94b22 4517 */
666a4537
WB		 4518 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4519 IS_CHERRYVIEW(dev))
97e94b22
DL		 4520 latency *= 10;
4521 else if (level > 0)
369a1342
VS		 4522 latency *= 5;
4523
4524 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4525 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4526 }
4527
4528 drm_modeset_unlock_all(dev);
4529}
4530
4531static int pri_wm_latency_show(struct seq_file *m, void *data)
4532{
4533 struct drm_device *dev = m->private;
97e94b22
DL		 4534 struct drm_i915_private *dev_priv = dev->dev_private;
4535 const uint16_t *latencies;
4536
4537 if (INTEL_INFO(dev)->gen >= 9)
4538 latencies = dev_priv->wm.skl_latency;
4539 else
4540 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4541
97e94b22 4542 wm_latency_show(m, latencies);
369a1342
VS		 4543
4544 return 0;
4545}
4546
4547static int spr_wm_latency_show(struct seq_file *m, void *data)
4548{
4549 struct drm_device *dev = m->private;
97e94b22
DL		 4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 const uint16_t *latencies;
4552
4553 if (INTEL_INFO(dev)->gen >= 9)
4554 latencies = dev_priv->wm.skl_latency;
4555 else
4556 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4557
97e94b22 4558 wm_latency_show(m, latencies);
369a1342
VS		 4559
4560 return 0;
4561}
4562
4563static int cur_wm_latency_show(struct seq_file *m, void *data)
4564{
4565 struct drm_device *dev = m->private;
97e94b22
DL		 4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567 const uint16_t *latencies;
4568
4569 if (INTEL_INFO(dev)->gen >= 9)
4570 latencies = dev_priv->wm.skl_latency;
4571 else
4572 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4573
97e94b22 4574 wm_latency_show(m, latencies);
369a1342
VS		 4575
4576 return 0;
4577}
4578
4579static int pri_wm_latency_open(struct inode *inode, struct file *file)
4580{
4581 struct drm_device *dev = inode->i_private;
4582
de38b95c 4583 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4584 return -ENODEV;
4585
4586 return single_open(file, pri_wm_latency_show, dev);
4587}
4588
4589static int spr_wm_latency_open(struct inode *inode, struct file *file)
4590{
4591 struct drm_device *dev = inode->i_private;
4592
9ad0257c 4593 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4594 return -ENODEV;
4595
4596 return single_open(file, spr_wm_latency_show, dev);
4597}
4598
4599static int cur_wm_latency_open(struct inode *inode, struct file *file)
4600{
4601 struct drm_device *dev = inode->i_private;
4602
9ad0257c 4603 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4604 return -ENODEV;
4605
4606 return single_open(file, cur_wm_latency_show, dev);
4607}
4608
4609static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4610 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4611{
4612 struct seq_file *m = file->private_data;
4613 struct drm_device *dev = m->private;
97e94b22 4614 uint16_t new[8] = { 0 };
de38b95c 4615 int num_levels;
369a1342
VS		 4616 int level;
4617 int ret;
4618 char tmp[32];
4619
de38b95c
VS		 4620 if (IS_CHERRYVIEW(dev))
4621 num_levels = 3;
4622 else if (IS_VALLEYVIEW(dev))
4623 num_levels = 1;
4624 else
4625 num_levels = ilk_wm_max_level(dev) + 1;
4626
369a1342
VS		 4627 if (len >= sizeof(tmp))
4628 return -EINVAL;
4629
4630 if (copy_from_user(tmp, ubuf, len))
4631 return -EFAULT;
4632
4633 tmp[len] = '\0';
4634
97e94b22
DL		 4635 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4636 &new[0], &new[1], &new[2], &new[3],
4637 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4638 if (ret != num_levels)
4639 return -EINVAL;
4640
4641 drm_modeset_lock_all(dev);
4642
4643 for (level = 0; level < num_levels; level++)
4644 wm[level] = new[level];
4645
4646 drm_modeset_unlock_all(dev);
4647
4648 return len;
4649}
4650
4651
4652static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4653 size_t len, loff_t *offp)
4654{
4655 struct seq_file *m = file->private_data;
4656 struct drm_device *dev = m->private;
97e94b22
DL		 4657 struct drm_i915_private *dev_priv = dev->dev_private;
4658 uint16_t *latencies;
369a1342 4659
97e94b22
DL		 4660 if (INTEL_INFO(dev)->gen >= 9)
4661 latencies = dev_priv->wm.skl_latency;
4662 else
4663 latencies = to_i915(dev)->wm.pri_latency;
4664
4665 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4666}
4667
4668static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4669 size_t len, loff_t *offp)
4670{
4671 struct seq_file *m = file->private_data;
4672 struct drm_device *dev = m->private;
97e94b22
DL		 4673 struct drm_i915_private *dev_priv = dev->dev_private;
4674 uint16_t *latencies;
369a1342 4675
97e94b22
DL		 4676 if (INTEL_INFO(dev)->gen >= 9)
4677 latencies = dev_priv->wm.skl_latency;
4678 else
4679 latencies = to_i915(dev)->wm.spr_latency;
4680
4681 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4682}
4683
4684static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4685 size_t len, loff_t *offp)
4686{
4687 struct seq_file *m = file->private_data;
4688 struct drm_device *dev = m->private;
97e94b22
DL		 4689 struct drm_i915_private *dev_priv = dev->dev_private;
4690 uint16_t *latencies;
4691
4692 if (INTEL_INFO(dev)->gen >= 9)
4693 latencies = dev_priv->wm.skl_latency;
4694 else
4695 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4696
97e94b22 4697 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4698}
4699
4700static const struct file_operations i915_pri_wm_latency_fops = {
4701 .owner = THIS_MODULE,
4702 .open = pri_wm_latency_open,
4703 .read = seq_read,
4704 .llseek = seq_lseek,
4705 .release = single_release,
4706 .write = pri_wm_latency_write
4707};
4708
4709static const struct file_operations i915_spr_wm_latency_fops = {
4710 .owner = THIS_MODULE,
4711 .open = spr_wm_latency_open,
4712 .read = seq_read,
4713 .llseek = seq_lseek,
4714 .release = single_release,
4715 .write = spr_wm_latency_write
4716};
4717
4718static const struct file_operations i915_cur_wm_latency_fops = {
4719 .owner = THIS_MODULE,
4720 .open = cur_wm_latency_open,
4721 .read = seq_read,
4722 .llseek = seq_lseek,
4723 .release = single_release,
4724 .write = cur_wm_latency_write
4725};
4726
647416f9
KC		 4727static int
4728i915_wedged_get(void *data, u64 *val)
f3cd474b 4729{
647416f9 4730 struct drm_device *dev = data;
e277a1f8 4731 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4732
d98c52cf 4733 *val = i915_terminally_wedged(&dev_priv->gpu_error);
f3cd474b 4734
647416f9 4735 return 0;
f3cd474b
CW		 4736}
4737
647416f9
KC		 4738static int
4739i915_wedged_set(void *data, u64 val)
f3cd474b 4740{
647416f9 4741 struct drm_device *dev = data;
d46c0517
ID		 4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743
b8d24a06
MK		 4744 /*
4745 * There is no safeguard against this debugfs entry colliding
4746 * with the hangcheck calling same i915_handle_error() in
4747 * parallel, causing an explosion. For now we assume that the
4748 * test harness is responsible enough not to inject gpu hangs
4749 * while it is writing to 'i915_wedged'
4750 */
4751
d98c52cf 4752 if (i915_reset_in_progress(&dev_priv->gpu_error))
b8d24a06
MK		 4753 return -EAGAIN;
4754
d46c0517 4755 intel_runtime_pm_get(dev_priv);
f3cd474b 4756
58174462
MK		 4757 i915_handle_error(dev, val,
4758 "Manually setting wedged to %llu", val);
d46c0517
ID		 4759
4760 intel_runtime_pm_put(dev_priv);
4761
647416f9 4762 return 0;
f3cd474b
CW		 4763}
4764
647416f9
KC		 4765DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4766 i915_wedged_get, i915_wedged_set,
3a3b4f98 4767 "%llu\n");
f3cd474b 4768
647416f9
KC		 4769static int
4770i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4771{
647416f9 4772 struct drm_device *dev = data;
e277a1f8 4773 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4774
647416f9 4775 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4776
647416f9 4777 return 0;
e5eb3d63
DV		 4778}
4779
647416f9
KC		 4780static int
4781i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4782{
647416f9 4783 struct drm_device *dev = data;
e5eb3d63 4784 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4785 int ret;
e5eb3d63 4786
647416f9 4787 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4788
22bcfc6a
DV		 4789 ret = mutex_lock_interruptible(&dev->struct_mutex);
4790 if (ret)
4791 return ret;
4792
99584db3 4793 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4794 mutex_unlock(&dev->struct_mutex);
4795
647416f9 4796 return 0;
e5eb3d63
DV		 4797}
4798
647416f9
KC		 4799DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4800 i915_ring_stop_get, i915_ring_stop_set,
4801 "0x%08llx\n");
d5442303 4802
094f9a54
CW		 4803static int
4804i915_ring_missed_irq_get(void *data, u64 *val)
4805{
4806 struct drm_device *dev = data;
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4808
4809 *val = dev_priv->gpu_error.missed_irq_rings;
4810 return 0;
4811}
4812
4813static int
4814i915_ring_missed_irq_set(void *data, u64 val)
4815{
4816 struct drm_device *dev = data;
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 int ret;
4819
4820 /* Lock against concurrent debugfs callers */
4821 ret = mutex_lock_interruptible(&dev->struct_mutex);
4822 if (ret)
4823 return ret;
4824 dev_priv->gpu_error.missed_irq_rings = val;
4825 mutex_unlock(&dev->struct_mutex);
4826
4827 return 0;
4828}
4829
4830DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4831 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4832 "0x%08llx\n");
4833
4834static int
4835i915_ring_test_irq_get(void *data, u64 *val)
4836{
4837 struct drm_device *dev = data;
4838 struct drm_i915_private *dev_priv = dev->dev_private;
4839
4840 *val = dev_priv->gpu_error.test_irq_rings;
4841
4842 return 0;
4843}
4844
4845static int
4846i915_ring_test_irq_set(void *data, u64 val)
4847{
4848 struct drm_device *dev = data;
4849 struct drm_i915_private *dev_priv = dev->dev_private;
4850 int ret;
4851
4852 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4853
4854 /* Lock against concurrent debugfs callers */
4855 ret = mutex_lock_interruptible(&dev->struct_mutex);
4856 if (ret)
4857 return ret;
4858
4859 dev_priv->gpu_error.test_irq_rings = val;
4860 mutex_unlock(&dev->struct_mutex);
4861
4862 return 0;
4863}
4864
4865DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4866 i915_ring_test_irq_get, i915_ring_test_irq_set,
4867 "0x%08llx\n");
4868
dd624afd
CW		 4869#define DROP_UNBOUND 0x1
4870#define DROP_BOUND 0x2
4871#define DROP_RETIRE 0x4
4872#define DROP_ACTIVE 0x8
4873#define DROP_ALL (DROP_UNBOUND | \
4874 DROP_BOUND | \
4875 DROP_RETIRE | \
4876 DROP_ACTIVE)
647416f9
KC		 4877static int
4878i915_drop_caches_get(void *data, u64 *val)
dd624afd 4879{
647416f9 4880 *val = DROP_ALL;
dd624afd 4881
647416f9 4882 return 0;
dd624afd
CW		 4883}
4884
647416f9
KC		 4885static int
4886i915_drop_caches_set(void *data, u64 val)
dd624afd 4887{
647416f9 4888 struct drm_device *dev = data;
dd624afd 4889 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4890 int ret;
dd624afd 4891
2f9fe5ff 4892 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4893
4894 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4895 * on ioctls on -EAGAIN. */
4896 ret = mutex_lock_interruptible(&dev->struct_mutex);
4897 if (ret)
4898 return ret;
4899
4900 if (val & DROP_ACTIVE) {
4901 ret = i915_gpu_idle(dev);
4902 if (ret)
4903 goto unlock;
4904 }
4905
4906 if (val & (DROP_RETIRE | DROP_ACTIVE))
4907 i915_gem_retire_requests(dev);
4908
21ab4e74
CW		 4909 if (val & DROP_BOUND)
4910 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4911
21ab4e74
CW		 4912 if (val & DROP_UNBOUND)
4913 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4914
4915unlock:
4916 mutex_unlock(&dev->struct_mutex);
4917
647416f9 4918 return ret;
dd624afd
CW		 4919}
4920
647416f9
KC		 4921DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4922 i915_drop_caches_get, i915_drop_caches_set,
4923 "0x%08llx\n");
dd624afd 4924
647416f9
KC		 4925static int
4926i915_max_freq_get(void *data, u64 *val)
358733e9 4927{
647416f9 4928 struct drm_device *dev = data;
e277a1f8 4929 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4930 int ret;
004777cb 4931
daa3afb2 4932 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4933 return -ENODEV;
4934
5c9669ce
TR		 4935 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4936
4fc688ce 4937 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4938 if (ret)
4939 return ret;
358733e9 4940
7c59a9c1 4941 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4942 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4943
647416f9 4944 return 0;
358733e9
JB		 4945}
4946
647416f9
KC		 4947static int
4948i915_max_freq_set(void *data, u64 val)
358733e9 4949{
647416f9 4950 struct drm_device *dev = data;
358733e9 4951 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4952 u32 hw_max, hw_min;
647416f9 4953 int ret;
004777cb 4954
daa3afb2 4955 if (INTEL_INFO(dev)->gen < 6)
004777cb 4956 return -ENODEV;
358733e9 4957
5c9669ce
TR		 4958 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4959
647416f9 4960 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4961
4fc688ce 4962 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4963 if (ret)
4964 return ret;
4965
358733e9
JB		 4966 /*
4967 * Turbo will still be enabled, but won't go above the set value.
4968 */
bc4d91f6 4969 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4970
bc4d91f6
AG		 4971 hw_max = dev_priv->rps.max_freq;
4972 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4973
b39fb297 4974 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4975 mutex_unlock(&dev_priv->rps.hw_lock);
4976 return -EINVAL;
0a073b84
JB		 4977 }
4978
b39fb297 4979 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4980
ffe02b40 4981 intel_set_rps(dev, val);
dd0a1aa1 4982
4fc688ce 4983 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4984
647416f9 4985 return 0;
358733e9
JB		 4986}
4987
647416f9
KC		 4988DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4989 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4990 "%llu\n");
358733e9 4991
647416f9
KC		 4992static int
4993i915_min_freq_get(void *data, u64 *val)
1523c310 4994{
647416f9 4995 struct drm_device *dev = data;
e277a1f8 4996 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4997 int ret;
004777cb 4998
daa3afb2 4999 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 5000 return -ENODEV;
5001
5c9669ce
TR		 5002 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5003
4fc688ce 5004 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 5005 if (ret)
5006 return ret;
1523c310 5007
7c59a9c1 5008 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 5009 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 5010
647416f9 5011 return 0;
1523c310
JB		 5012}
5013
647416f9
KC		 5014static int
5015i915_min_freq_set(void *data, u64 val)
1523c310 5016{
647416f9 5017 struct drm_device *dev = data;
1523c310 5018 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 5019 u32 hw_max, hw_min;
647416f9 5020 int ret;
004777cb 5021
daa3afb2 5022 if (INTEL_INFO(dev)->gen < 6)
004777cb 5023 return -ENODEV;
1523c310 5024
5c9669ce
TR		 5025 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5026
647416f9 5027 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 5028
4fc688ce 5029 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 5030 if (ret)
5031 return ret;
5032
1523c310
JB		 5033 /*
5034 * Turbo will still be enabled, but won't go below the set value.
5035 */
bc4d91f6 5036 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 5037
bc4d91f6
AG		 5038 hw_max = dev_priv->rps.max_freq;
5039 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 5040
b39fb297 5041 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 5042 mutex_unlock(&dev_priv->rps.hw_lock);
5043 return -EINVAL;
0a073b84 5044 }
dd0a1aa1 5045
b39fb297 5046 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 5047
ffe02b40 5048 intel_set_rps(dev, val);
dd0a1aa1 5049
4fc688ce 5050 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 5051
647416f9 5052 return 0;
1523c310
JB		 5053}
5054
647416f9
KC		 5055DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5056 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 5057 "%llu\n");
1523c310 5058
647416f9
KC		 5059static int
5060i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 5061{
647416f9 5062 struct drm_device *dev = data;
e277a1f8 5063 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5064 u32 snpcr;
647416f9 5065 int ret;
07b7ddd9 5066
004777cb
DV		 5067 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5068 return -ENODEV;
5069
22bcfc6a
DV		 5070 ret = mutex_lock_interruptible(&dev->struct_mutex);
5071 if (ret)
5072 return ret;
c8c8fb33 5073 intel_runtime_pm_get(dev_priv);
22bcfc6a 5074
07b7ddd9 5075 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 5076
5077 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 5078 mutex_unlock(&dev_priv->dev->struct_mutex);
5079
647416f9 5080 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 5081
647416f9 5082 return 0;
07b7ddd9
JB		 5083}
5084
647416f9
KC		 5085static int
5086i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 5087{
647416f9 5088 struct drm_device *dev = data;
07b7ddd9 5089 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5090 u32 snpcr;
07b7ddd9 5091
004777cb
DV		 5092 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5093 return -ENODEV;
5094
647416f9 5095 if (val > 3)
07b7ddd9
JB		 5096 return -EINVAL;
5097
c8c8fb33 5098 intel_runtime_pm_get(dev_priv);
647416f9 5099 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 5100
5101 /* Update the cache sharing policy here as well */
5102 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5103 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5104 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5105 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5106
c8c8fb33 5107 intel_runtime_pm_put(dev_priv);
647416f9 5108 return 0;
07b7ddd9
JB		 5109}
5110
647416f9
KC		 5111DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5112 i915_cache_sharing_get, i915_cache_sharing_set,
5113 "%llu\n");
07b7ddd9 5114
5d39525a
JM		 5115struct sseu_dev_status {
5116 unsigned int slice_total;
5117 unsigned int subslice_total;
5118 unsigned int subslice_per_slice;
5119 unsigned int eu_total;
5120 unsigned int eu_per_subslice;
5121};
5122
5123static void cherryview_sseu_device_status(struct drm_device *dev,
5124 struct sseu_dev_status *stat)
5125{
5126 struct drm_i915_private *dev_priv = dev->dev_private;
0a0b457f 5127 int ss_max = 2;
5d39525a
JM		 5128 int ss;
5129 u32 sig1[ss_max], sig2[ss_max];
5130
5131 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5132 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5133 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5134 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5135
5136 for (ss = 0; ss < ss_max; ss++) {
5137 unsigned int eu_cnt;
5138
5139 if (sig1[ss] & CHV_SS_PG_ENABLE)
5140 /* skip disabled subslice */
5141 continue;
5142
5143 stat->slice_total = 1;
5144 stat->subslice_per_slice++;
5145 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5146 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5147 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5148 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5149 stat->eu_total += eu_cnt;
5150 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5151 }
5152 stat->subslice_total = stat->subslice_per_slice;
5153}
5154
5155static void gen9_sseu_device_status(struct drm_device *dev,
5156 struct sseu_dev_status *stat)
5157{
5158 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 5159 int s_max = 3, ss_max = 4;
5d39525a
JM		 5160 int s, ss;
5161 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5162
1c046bc1
JM		 5163 /* BXT has a single slice and at most 3 subslices. */
5164 if (IS_BROXTON(dev)) {
5165 s_max = 1;
5166 ss_max = 3;
5167 }
5168
5169 for (s = 0; s < s_max; s++) {
5170 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5171 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5172 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5173 }
5174
5d39525a
JM		 5175 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5176 GEN9_PGCTL_SSA_EU19_ACK |
5177 GEN9_PGCTL_SSA_EU210_ACK |
5178 GEN9_PGCTL_SSA_EU311_ACK;
5179 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5180 GEN9_PGCTL_SSB_EU19_ACK |
5181 GEN9_PGCTL_SSB_EU210_ACK |
5182 GEN9_PGCTL_SSB_EU311_ACK;
5183
5184 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5185 unsigned int ss_cnt = 0;
5186
5d39525a
JM		 5187 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5188 /* skip disabled slice */
5189 continue;
5190
5191 stat->slice_total++;
1c046bc1 5192
ef11bdb3 5193 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1c046bc1
JM		 5194 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5195
5d39525a
JM		 5196 for (ss = 0; ss < ss_max; ss++) {
5197 unsigned int eu_cnt;
5198
1c046bc1
JM		 5199 if (IS_BROXTON(dev) &&
5200 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5201 /* skip disabled subslice */
5202 continue;
5203
5204 if (IS_BROXTON(dev))
5205 ss_cnt++;
5206
5d39525a
JM		 5207 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5208 eu_mask[ss%2]);
5209 stat->eu_total += eu_cnt;
5210 stat->eu_per_subslice = max(stat->eu_per_subslice,
5211 eu_cnt);
5212 }
1c046bc1
JM		 5213
5214 stat->subslice_total += ss_cnt;
5215 stat->subslice_per_slice = max(stat->subslice_per_slice,
5216 ss_cnt);
5d39525a
JM		 5217 }
5218}
5219
91bedd34
ŁD		 5220static void broadwell_sseu_device_status(struct drm_device *dev,
5221 struct sseu_dev_status *stat)
5222{
5223 struct drm_i915_private *dev_priv = dev->dev_private;
5224 int s;
5225 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5226
5227 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5228
5229 if (stat->slice_total) {
5230 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5231 stat->subslice_total = stat->slice_total *
5232 stat->subslice_per_slice;
5233 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5234 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5235
5236 /* subtract fused off EU(s) from enabled slice(s) */
5237 for (s = 0; s < stat->slice_total; s++) {
5238 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5239
5240 stat->eu_total -= hweight8(subslice_7eu);
5241 }
5242 }
5243}
5244
3873218f
JM		 5245static int i915_sseu_status(struct seq_file *m, void *unused)
5246{
5247 struct drm_info_node *node = (struct drm_info_node *) m->private;
5248 struct drm_device *dev = node->minor->dev;
5d39525a 5249 struct sseu_dev_status stat;
3873218f 5250
91bedd34 5251 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5252 return -ENODEV;
5253
5254 seq_puts(m, "SSEU Device Info\n");
5255 seq_printf(m, " Available Slice Total: %u\n",
5256 INTEL_INFO(dev)->slice_total);
5257 seq_printf(m, " Available Subslice Total: %u\n",
5258 INTEL_INFO(dev)->subslice_total);
5259 seq_printf(m, " Available Subslice Per Slice: %u\n",
5260 INTEL_INFO(dev)->subslice_per_slice);
5261 seq_printf(m, " Available EU Total: %u\n",
5262 INTEL_INFO(dev)->eu_total);
5263 seq_printf(m, " Available EU Per Subslice: %u\n",
5264 INTEL_INFO(dev)->eu_per_subslice);
5265 seq_printf(m, " Has Slice Power Gating: %s\n",
5266 yesno(INTEL_INFO(dev)->has_slice_pg));
5267 seq_printf(m, " Has Subslice Power Gating: %s\n",
5268 yesno(INTEL_INFO(dev)->has_subslice_pg));
5269 seq_printf(m, " Has EU Power Gating: %s\n",
5270 yesno(INTEL_INFO(dev)->has_eu_pg));
5271
7f992aba 5272 seq_puts(m, "SSEU Device Status\n");
5d39525a 5273 memset(&stat, 0, sizeof(stat));
5575f03a 5274 if (IS_CHERRYVIEW(dev)) {
5d39525a 5275 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5276 } else if (IS_BROADWELL(dev)) {
5277 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5278 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5279 gen9_sseu_device_status(dev, &stat);
7f992aba 5280 }
5d39525a
JM		 5281 seq_printf(m, " Enabled Slice Total: %u\n",
5282 stat.slice_total);
5283 seq_printf(m, " Enabled Subslice Total: %u\n",
5284 stat.subslice_total);
5285 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5286 stat.subslice_per_slice);
5287 seq_printf(m, " Enabled EU Total: %u\n",
5288 stat.eu_total);
5289 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5290 stat.eu_per_subslice);
7f992aba 5291
3873218f
JM		 5292 return 0;
5293}
5294
6d794d42
BW		 5295static int i915_forcewake_open(struct inode *inode, struct file *file)
5296{
5297 struct drm_device *dev = inode->i_private;
5298 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5299
075edca4 5300 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5301 return 0;
5302
6daccb0b 5303 intel_runtime_pm_get(dev_priv);
59bad947 5304 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5305
5306 return 0;
5307}
5308
c43b5634 5309static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5310{
5311 struct drm_device *dev = inode->i_private;
5312 struct drm_i915_private *dev_priv = dev->dev_private;
5313
075edca4 5314 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5315 return 0;
5316
59bad947 5317 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5318 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5319
5320 return 0;
5321}
5322
5323static const struct file_operations i915_forcewake_fops = {
5324 .owner = THIS_MODULE,
5325 .open = i915_forcewake_open,
5326 .release = i915_forcewake_release,
5327};
5328
5329static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5330{
5331 struct drm_device *dev = minor->dev;
5332 struct dentry *ent;
5333
5334 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5335 S_IRUSR,
6d794d42
BW		 5336 root, dev,
5337 &i915_forcewake_fops);
f3c5fe97
WY		 5338 if (!ent)
5339 return -ENOMEM;
6d794d42 5340
8eb57294 5341 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5342}
5343
6a9c308d
DV		 5344static int i915_debugfs_create(struct dentry *root,
5345 struct drm_minor *minor,
5346 const char *name,
5347 const struct file_operations *fops)
07b7ddd9
JB		 5348{
5349 struct drm_device *dev = minor->dev;
5350 struct dentry *ent;
5351
6a9c308d 5352 ent = debugfs_create_file(name,
07b7ddd9
JB		 5353 S_IRUGO | S_IWUSR,
5354 root, dev,
6a9c308d 5355 fops);
f3c5fe97
WY		 5356 if (!ent)
5357 return -ENOMEM;
07b7ddd9 5358
6a9c308d 5359 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5360}
5361
06c5bf8c 5362static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5363 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5364 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5365 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5366 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5367 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5368 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5369 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5370 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5371 {"i915_gem_request", i915_gem_request_info, 0},
5372 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5373 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5374 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5375 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5376 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5377 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5378 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5379 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5380 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5381 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5382 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5383 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5384 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5385 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5386 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5387 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5388 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5389 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5390 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5391 {"i915_sr_status", i915_sr_status, 0},
44834a67 5392 {"i915_opregion", i915_opregion, 0},
ada8f955 5393 {"i915_vbt", i915_vbt, 0},
37811fcc 5394 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5395 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5396 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5397 {"i915_execlists", i915_execlists, 0},
f65367b5 5398 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5399 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5400 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5401 {"i915_llc", i915_llc, 0},
e91fd8c6 5402 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5403 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5404 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5405 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5406 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5407 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5408 {"i915_display_info", i915_display_info, 0},
e04934cf 5409 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5410 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5411 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5412 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5413 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5414 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5415 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5416 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5417};
27c202ad 5418#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5419
06c5bf8c 5420static const struct i915_debugfs_files {
34b9674c
DV		 5421 const char *name;
5422 const struct file_operations *fops;
5423} i915_debugfs_files[] = {
5424 {"i915_wedged", &i915_wedged_fops},
5425 {"i915_max_freq", &i915_max_freq_fops},
5426 {"i915_min_freq", &i915_min_freq_fops},
5427 {"i915_cache_sharing", &i915_cache_sharing_fops},
5428 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5429 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5430 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5431 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5432 {"i915_error_state", &i915_error_state_fops},
5433 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5434 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5435 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5436 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5437 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5438 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5439 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5440 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5441 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5442};
5443
07144428
DL		 5444void intel_display_crc_init(struct drm_device *dev)
5445{
5446 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5447 enum pipe pipe;
07144428 5448
055e393f 5449 for_each_pipe(dev_priv, pipe) {
b378360e 5450 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5451
d538bbdf
DL		 5452 pipe_crc->opened = false;
5453 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5454 init_waitqueue_head(&pipe_crc->wq);
5455 }
5456}
5457
27c202ad 5458int i915_debugfs_init(struct drm_minor *minor)
2017263e 5459{
34b9674c 5460 int ret, i;
f3cd474b 5461
6d794d42 5462 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5463 if (ret)
5464 return ret;
6a9c308d 5465
07144428
DL		 5466 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5467 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5468 if (ret)
5469 return ret;
5470 }
5471
34b9674c
DV		 5472 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5473 ret = i915_debugfs_create(minor->debugfs_root, minor,
5474 i915_debugfs_files[i].name,
5475 i915_debugfs_files[i].fops);
5476 if (ret)
5477 return ret;
5478 }
40633219 5479
27c202ad
BG		 5480 return drm_debugfs_create_files(i915_debugfs_list,
5481 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5482 minor->debugfs_root, minor);
5483}
5484
27c202ad 5485void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5486{
34b9674c
DV		 5487 int i;
5488
27c202ad
BG		 5489 drm_debugfs_remove_files(i915_debugfs_list,
5490 I915_DEBUGFS_ENTRIES, minor);
07144428 5491
6d794d42
BW		 5492 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5493 1, minor);
07144428 5494
e309a997 5495 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5496 struct drm_info_list *info_list =
5497 (struct drm_info_list *)&i915_pipe_crc_data[i];
5498
5499 drm_debugfs_remove_files(info_list, 1, minor);
5500 }
5501
34b9674c
DV		 5502 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5503 struct drm_info_list *info_list =
5504 (struct drm_info_list *) i915_debugfs_files[i].fops;
5505
5506 drm_debugfs_remove_files(info_list, 1, minor);
5507 }
2017263e 5508}
aa7471d2
JN		 5509
5510struct dpcd_block {
5511 /* DPCD dump start address. */
5512 unsigned int offset;
5513 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5514 unsigned int end;
5515 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5516 size_t size;
5517 /* Only valid for eDP. */
5518 bool edp;
5519};
5520
5521static const struct dpcd_block i915_dpcd_debug[] = {
5522 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5523 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5524 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5525 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5526 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5527 { .offset = DP_SET_POWER },
5528 { .offset = DP_EDP_DPCD_REV },
5529 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5530 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5531 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5532};
5533
5534static int i915_dpcd_show(struct seq_file *m, void *data)
5535{
5536 struct drm_connector *connector = m->private;
5537 struct intel_dp *intel_dp =
5538 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5539 uint8_t buf[16];
5540 ssize_t err;
5541 int i;
5542
5c1a8875
MK		 5543 if (connector->status != connector_status_connected)
5544 return -ENODEV;
5545
aa7471d2
JN		 5546 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5547 const struct dpcd_block *b = &i915_dpcd_debug[i];
5548 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5549
5550 if (b->edp &&
5551 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5552 continue;
5553
5554 /* low tech for now */
5555 if (WARN_ON(size > sizeof(buf)))
5556 continue;
5557
5558 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5559 if (err <= 0) {
5560 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5561 size, b->offset, err);
5562 continue;
5563 }
5564
5565 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5566 }
aa7471d2
JN		 5567
5568 return 0;
5569}
5570
5571static int i915_dpcd_open(struct inode *inode, struct file *file)
5572{
5573 return single_open(file, i915_dpcd_show, inode->i_private);
5574}
5575
5576static const struct file_operations i915_dpcd_fops = {
5577 .owner = THIS_MODULE,
5578 .open = i915_dpcd_open,
5579 .read = seq_read,
5580 .llseek = seq_lseek,
5581 .release = single_release,
5582};
5583
5584/**
5585 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5586 * @connector: pointer to a registered drm_connector
5587 *
5588 * Cleanup will be done by drm_connector_unregister() through a call to
5589 * drm_debugfs_connector_remove().
5590 *
5591 * Returns 0 on success, negative error codes on error.
5592 */
5593int i915_debugfs_connector_add(struct drm_connector *connector)
5594{
5595 struct dentry *root = connector->debugfs_entry;
5596
5597 /* The connector must have been registered beforehands. */
5598 if (!root)
5599 return -ENODEV;
5600
5601 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5602 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5603 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5604 &i915_dpcd_fops);
5605
5606 return 0;
5607}
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