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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
2017263e BG |
33 | #include "drmP.h" |
34 | #include "drm.h" | |
4e5359cd | 35 | #include "intel_drv.h" |
e5c65260 | 36 | #include "intel_ringbuffer.h" |
2017263e BG |
37 | #include "i915_drm.h" |
38 | #include "i915_drv.h" | |
39 | ||
40 | #define DRM_I915_RING_DEBUG 1 | |
41 | ||
42 | ||
43 | #if defined(CONFIG_DEBUG_FS) | |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 CW |
47 | FLUSHING_LIST, |
48 | INACTIVE_LIST, | |
d21d5975 | 49 | PINNED_LIST, |
f13d3f73 | 50 | }; |
2017263e | 51 | |
70d39fe4 CW |
52 | static const char *yesno(int v) |
53 | { | |
54 | return v ? "yes" : "no"; | |
55 | } | |
56 | ||
57 | static int i915_capabilities(struct seq_file *m, void *data) | |
58 | { | |
59 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
60 | struct drm_device *dev = node->minor->dev; | |
61 | const struct intel_device_info *info = INTEL_INFO(dev); | |
62 | ||
63 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 64 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
70d39fe4 CW |
65 | #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
66 | B(is_mobile); | |
70d39fe4 CW |
67 | B(is_i85x); |
68 | B(is_i915g); | |
70d39fe4 | 69 | B(is_i945gm); |
70d39fe4 CW |
70 | B(is_g33); |
71 | B(need_gfx_hws); | |
72 | B(is_g4x); | |
73 | B(is_pineview); | |
74 | B(is_broadwater); | |
75 | B(is_crestline); | |
70d39fe4 | 76 | B(has_fbc); |
70d39fe4 CW |
77 | B(has_pipe_cxsr); |
78 | B(has_hotplug); | |
79 | B(cursor_needs_physical); | |
80 | B(has_overlay); | |
81 | B(overlay_needs_physical); | |
a6c45cf0 | 82 | B(supports_tv); |
549f7365 CW |
83 | B(has_bsd_ring); |
84 | B(has_blt_ring); | |
3d29b842 | 85 | B(has_llc); |
70d39fe4 CW |
86 | #undef B |
87 | ||
88 | return 0; | |
89 | } | |
2017263e | 90 | |
05394f39 | 91 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 92 | { |
05394f39 | 93 | if (obj->user_pin_count > 0) |
a6172a80 | 94 | return "P"; |
05394f39 | 95 | else if (obj->pin_count > 0) |
a6172a80 CW |
96 | return "p"; |
97 | else | |
98 | return " "; | |
99 | } | |
100 | ||
05394f39 | 101 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 102 | { |
0206e353 AJ |
103 | switch (obj->tiling_mode) { |
104 | default: | |
105 | case I915_TILING_NONE: return " "; | |
106 | case I915_TILING_X: return "X"; | |
107 | case I915_TILING_Y: return "Y"; | |
108 | } | |
a6172a80 CW |
109 | } |
110 | ||
93dfb40c | 111 | static const char *cache_level_str(int type) |
08c18323 CW |
112 | { |
113 | switch (type) { | |
93dfb40c CW |
114 | case I915_CACHE_NONE: return " uncached"; |
115 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
116 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
117 | default: return ""; |
118 | } | |
119 | } | |
120 | ||
37811fcc CW |
121 | static void |
122 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
123 | { | |
a05a5862 | 124 | seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s", |
37811fcc CW |
125 | &obj->base, |
126 | get_pin_flag(obj), | |
127 | get_tiling_flag(obj), | |
a05a5862 | 128 | obj->base.size / 1024, |
37811fcc CW |
129 | obj->base.read_domains, |
130 | obj->base.write_domain, | |
131 | obj->last_rendering_seqno, | |
caea7476 | 132 | obj->last_fenced_seqno, |
93dfb40c | 133 | cache_level_str(obj->cache_level), |
37811fcc CW |
134 | obj->dirty ? " dirty" : "", |
135 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
136 | if (obj->base.name) | |
137 | seq_printf(m, " (name: %d)", obj->base.name); | |
138 | if (obj->fence_reg != I915_FENCE_REG_NONE) | |
139 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
140 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
141 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
142 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
6299f992 CW |
143 | if (obj->pin_mappable || obj->fault_mappable) { |
144 | char s[3], *t = s; | |
145 | if (obj->pin_mappable) | |
146 | *t++ = 'p'; | |
147 | if (obj->fault_mappable) | |
148 | *t++ = 'f'; | |
149 | *t = '\0'; | |
150 | seq_printf(m, " (%s mappable)", s); | |
151 | } | |
69dc4987 CW |
152 | if (obj->ring != NULL) |
153 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
154 | } |
155 | ||
433e12f7 | 156 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
157 | { |
158 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
159 | uintptr_t list = (uintptr_t) node->info_ent->data; |
160 | struct list_head *head; | |
2017263e BG |
161 | struct drm_device *dev = node->minor->dev; |
162 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 163 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
164 | size_t total_obj_size, total_gtt_size; |
165 | int count, ret; | |
de227ef0 CW |
166 | |
167 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
168 | if (ret) | |
169 | return ret; | |
2017263e | 170 | |
433e12f7 BG |
171 | switch (list) { |
172 | case ACTIVE_LIST: | |
173 | seq_printf(m, "Active:\n"); | |
69dc4987 | 174 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
175 | break; |
176 | case INACTIVE_LIST: | |
a17458fc | 177 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
178 | head = &dev_priv->mm.inactive_list; |
179 | break; | |
180 | case FLUSHING_LIST: | |
181 | seq_printf(m, "Flushing:\n"); | |
182 | head = &dev_priv->mm.flushing_list; | |
183 | break; | |
184 | default: | |
de227ef0 CW |
185 | mutex_unlock(&dev->struct_mutex); |
186 | return -EINVAL; | |
2017263e | 187 | } |
2017263e | 188 | |
8f2480fb | 189 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 190 | list_for_each_entry(obj, head, mm_list) { |
37811fcc | 191 | seq_printf(m, " "); |
05394f39 | 192 | describe_obj(m, obj); |
f4ceda89 | 193 | seq_printf(m, "\n"); |
05394f39 CW |
194 | total_obj_size += obj->base.size; |
195 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 196 | count++; |
2017263e | 197 | } |
de227ef0 | 198 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 199 | |
8f2480fb CW |
200 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
201 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
202 | return 0; |
203 | } | |
204 | ||
6299f992 CW |
205 | #define count_objects(list, member) do { \ |
206 | list_for_each_entry(obj, list, member) { \ | |
207 | size += obj->gtt_space->size; \ | |
208 | ++count; \ | |
209 | if (obj->map_and_fenceable) { \ | |
210 | mappable_size += obj->gtt_space->size; \ | |
211 | ++mappable_count; \ | |
212 | } \ | |
213 | } \ | |
0206e353 | 214 | } while (0) |
6299f992 | 215 | |
73aa808f CW |
216 | static int i915_gem_object_info(struct seq_file *m, void* data) |
217 | { | |
218 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
219 | struct drm_device *dev = node->minor->dev; | |
220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6299f992 CW |
221 | u32 count, mappable_count; |
222 | size_t size, mappable_size; | |
223 | struct drm_i915_gem_object *obj; | |
73aa808f CW |
224 | int ret; |
225 | ||
226 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
227 | if (ret) | |
228 | return ret; | |
229 | ||
6299f992 CW |
230 | seq_printf(m, "%u objects, %zu bytes\n", |
231 | dev_priv->mm.object_count, | |
232 | dev_priv->mm.object_memory); | |
233 | ||
234 | size = count = mappable_size = mappable_count = 0; | |
235 | count_objects(&dev_priv->mm.gtt_list, gtt_list); | |
236 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", | |
237 | count, mappable_count, size, mappable_size); | |
238 | ||
239 | size = count = mappable_size = mappable_count = 0; | |
240 | count_objects(&dev_priv->mm.active_list, mm_list); | |
241 | count_objects(&dev_priv->mm.flushing_list, mm_list); | |
242 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", | |
243 | count, mappable_count, size, mappable_size); | |
244 | ||
6299f992 CW |
245 | size = count = mappable_size = mappable_count = 0; |
246 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
247 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
248 | count, mappable_count, size, mappable_size); | |
249 | ||
6299f992 CW |
250 | size = count = mappable_size = mappable_count = 0; |
251 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
252 | if (obj->fault_mappable) { | |
253 | size += obj->gtt_space->size; | |
254 | ++count; | |
255 | } | |
256 | if (obj->pin_mappable) { | |
257 | mappable_size += obj->gtt_space->size; | |
258 | ++mappable_count; | |
259 | } | |
260 | } | |
261 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", | |
262 | mappable_count, mappable_size); | |
263 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
264 | count, size); | |
265 | ||
266 | seq_printf(m, "%zu [%zu] gtt total\n", | |
267 | dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); | |
73aa808f CW |
268 | |
269 | mutex_unlock(&dev->struct_mutex); | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
08c18323 CW |
274 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
275 | { | |
276 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
277 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 278 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
279 | struct drm_i915_private *dev_priv = dev->dev_private; |
280 | struct drm_i915_gem_object *obj; | |
281 | size_t total_obj_size, total_gtt_size; | |
282 | int count, ret; | |
283 | ||
284 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
285 | if (ret) | |
286 | return ret; | |
287 | ||
288 | total_obj_size = total_gtt_size = count = 0; | |
289 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
1b50247a CW |
290 | if (list == PINNED_LIST && obj->pin_count == 0) |
291 | continue; | |
292 | ||
08c18323 CW |
293 | seq_printf(m, " "); |
294 | describe_obj(m, obj); | |
295 | seq_printf(m, "\n"); | |
296 | total_obj_size += obj->base.size; | |
297 | total_gtt_size += obj->gtt_space->size; | |
298 | count++; | |
299 | } | |
300 | ||
301 | mutex_unlock(&dev->struct_mutex); | |
302 | ||
303 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
304 | count, total_obj_size, total_gtt_size); | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
4e5359cd SF |
309 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
310 | { | |
311 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
312 | struct drm_device *dev = node->minor->dev; | |
313 | unsigned long flags; | |
314 | struct intel_crtc *crtc; | |
315 | ||
316 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
317 | const char pipe = pipe_name(crtc->pipe); |
318 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
319 | struct intel_unpin_work *work; |
320 | ||
321 | spin_lock_irqsave(&dev->event_lock, flags); | |
322 | work = crtc->unpin_work; | |
323 | if (work == NULL) { | |
9db4a9c7 | 324 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
325 | pipe, plane); |
326 | } else { | |
327 | if (!work->pending) { | |
9db4a9c7 | 328 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
329 | pipe, plane); |
330 | } else { | |
9db4a9c7 | 331 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
332 | pipe, plane); |
333 | } | |
334 | if (work->enable_stall_check) | |
335 | seq_printf(m, "Stall check enabled, "); | |
336 | else | |
337 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
338 | seq_printf(m, "%d prepares\n", work->pending); | |
339 | ||
340 | if (work->old_fb_obj) { | |
05394f39 CW |
341 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
342 | if (obj) | |
343 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
344 | } |
345 | if (work->pending_flip_obj) { | |
05394f39 CW |
346 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
347 | if (obj) | |
348 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
349 | } |
350 | } | |
351 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
2017263e BG |
357 | static int i915_gem_request_info(struct seq_file *m, void *data) |
358 | { | |
359 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
360 | struct drm_device *dev = node->minor->dev; | |
361 | drm_i915_private_t *dev_priv = dev->dev_private; | |
362 | struct drm_i915_gem_request *gem_request; | |
c2c347a9 | 363 | int ret, count; |
de227ef0 CW |
364 | |
365 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
366 | if (ret) | |
367 | return ret; | |
2017263e | 368 | |
c2c347a9 | 369 | count = 0; |
1ec14ad3 | 370 | if (!list_empty(&dev_priv->ring[RCS].request_list)) { |
c2c347a9 CW |
371 | seq_printf(m, "Render requests:\n"); |
372 | list_for_each_entry(gem_request, | |
1ec14ad3 | 373 | &dev_priv->ring[RCS].request_list, |
c2c347a9 CW |
374 | list) { |
375 | seq_printf(m, " %d @ %d\n", | |
376 | gem_request->seqno, | |
377 | (int) (jiffies - gem_request->emitted_jiffies)); | |
378 | } | |
379 | count++; | |
380 | } | |
1ec14ad3 | 381 | if (!list_empty(&dev_priv->ring[VCS].request_list)) { |
c2c347a9 CW |
382 | seq_printf(m, "BSD requests:\n"); |
383 | list_for_each_entry(gem_request, | |
1ec14ad3 | 384 | &dev_priv->ring[VCS].request_list, |
c2c347a9 CW |
385 | list) { |
386 | seq_printf(m, " %d @ %d\n", | |
387 | gem_request->seqno, | |
388 | (int) (jiffies - gem_request->emitted_jiffies)); | |
389 | } | |
390 | count++; | |
391 | } | |
1ec14ad3 | 392 | if (!list_empty(&dev_priv->ring[BCS].request_list)) { |
c2c347a9 CW |
393 | seq_printf(m, "BLT requests:\n"); |
394 | list_for_each_entry(gem_request, | |
1ec14ad3 | 395 | &dev_priv->ring[BCS].request_list, |
c2c347a9 CW |
396 | list) { |
397 | seq_printf(m, " %d @ %d\n", | |
398 | gem_request->seqno, | |
399 | (int) (jiffies - gem_request->emitted_jiffies)); | |
400 | } | |
401 | count++; | |
2017263e | 402 | } |
de227ef0 CW |
403 | mutex_unlock(&dev->struct_mutex); |
404 | ||
c2c347a9 CW |
405 | if (count == 0) |
406 | seq_printf(m, "No requests\n"); | |
407 | ||
2017263e BG |
408 | return 0; |
409 | } | |
410 | ||
b2223497 CW |
411 | static void i915_ring_seqno_info(struct seq_file *m, |
412 | struct intel_ring_buffer *ring) | |
413 | { | |
414 | if (ring->get_seqno) { | |
415 | seq_printf(m, "Current sequence (%s): %d\n", | |
416 | ring->name, ring->get_seqno(ring)); | |
417 | seq_printf(m, "Waiter sequence (%s): %d\n", | |
418 | ring->name, ring->waiting_seqno); | |
419 | seq_printf(m, "IRQ sequence (%s): %d\n", | |
420 | ring->name, ring->irq_seqno); | |
421 | } | |
422 | } | |
423 | ||
2017263e BG |
424 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
425 | { | |
426 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
427 | struct drm_device *dev = node->minor->dev; | |
428 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 429 | int ret, i; |
de227ef0 CW |
430 | |
431 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
432 | if (ret) | |
433 | return ret; | |
2017263e | 434 | |
1ec14ad3 CW |
435 | for (i = 0; i < I915_NUM_RINGS; i++) |
436 | i915_ring_seqno_info(m, &dev_priv->ring[i]); | |
de227ef0 CW |
437 | |
438 | mutex_unlock(&dev->struct_mutex); | |
439 | ||
2017263e BG |
440 | return 0; |
441 | } | |
442 | ||
443 | ||
444 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
445 | { | |
446 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
447 | struct drm_device *dev = node->minor->dev; | |
448 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9db4a9c7 | 449 | int ret, i, pipe; |
de227ef0 CW |
450 | |
451 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
452 | if (ret) | |
453 | return ret; | |
2017263e | 454 | |
7e231dbe JB |
455 | if (IS_VALLEYVIEW(dev)) { |
456 | seq_printf(m, "Display IER:\t%08x\n", | |
457 | I915_READ(VLV_IER)); | |
458 | seq_printf(m, "Display IIR:\t%08x\n", | |
459 | I915_READ(VLV_IIR)); | |
460 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
461 | I915_READ(VLV_IIR_RW)); | |
462 | seq_printf(m, "Display IMR:\t%08x\n", | |
463 | I915_READ(VLV_IMR)); | |
464 | for_each_pipe(pipe) | |
465 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
466 | pipe_name(pipe), | |
467 | I915_READ(PIPESTAT(pipe))); | |
468 | ||
469 | seq_printf(m, "Master IER:\t%08x\n", | |
470 | I915_READ(VLV_MASTER_IER)); | |
471 | ||
472 | seq_printf(m, "Render IER:\t%08x\n", | |
473 | I915_READ(GTIER)); | |
474 | seq_printf(m, "Render IIR:\t%08x\n", | |
475 | I915_READ(GTIIR)); | |
476 | seq_printf(m, "Render IMR:\t%08x\n", | |
477 | I915_READ(GTIMR)); | |
478 | ||
479 | seq_printf(m, "PM IER:\t\t%08x\n", | |
480 | I915_READ(GEN6_PMIER)); | |
481 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
482 | I915_READ(GEN6_PMIIR)); | |
483 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
484 | I915_READ(GEN6_PMIMR)); | |
485 | ||
486 | seq_printf(m, "Port hotplug:\t%08x\n", | |
487 | I915_READ(PORT_HOTPLUG_EN)); | |
488 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
489 | I915_READ(VLV_DPFLIPSTAT)); | |
490 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
491 | I915_READ(DPINVGTT)); | |
492 | ||
493 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
494 | seq_printf(m, "Interrupt enable: %08x\n", |
495 | I915_READ(IER)); | |
496 | seq_printf(m, "Interrupt identity: %08x\n", | |
497 | I915_READ(IIR)); | |
498 | seq_printf(m, "Interrupt mask: %08x\n", | |
499 | I915_READ(IMR)); | |
9db4a9c7 JB |
500 | for_each_pipe(pipe) |
501 | seq_printf(m, "Pipe %c stat: %08x\n", | |
502 | pipe_name(pipe), | |
503 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
504 | } else { |
505 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
506 | I915_READ(DEIER)); | |
507 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
508 | I915_READ(DEIIR)); | |
509 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
510 | I915_READ(DEIMR)); | |
511 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
512 | I915_READ(SDEIER)); | |
513 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
514 | I915_READ(SDEIIR)); | |
515 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
516 | I915_READ(SDEIMR)); | |
517 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
518 | I915_READ(GTIER)); | |
519 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
520 | I915_READ(GTIIR)); | |
521 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
522 | I915_READ(GTIMR)); | |
523 | } | |
2017263e BG |
524 | seq_printf(m, "Interrupts received: %d\n", |
525 | atomic_read(&dev_priv->irq_received)); | |
9862e600 | 526 | for (i = 0; i < I915_NUM_RINGS; i++) { |
da64c6fc | 527 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
9862e600 CW |
528 | seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", |
529 | dev_priv->ring[i].name, | |
530 | I915_READ_IMR(&dev_priv->ring[i])); | |
531 | } | |
1ec14ad3 | 532 | i915_ring_seqno_info(m, &dev_priv->ring[i]); |
9862e600 | 533 | } |
de227ef0 CW |
534 | mutex_unlock(&dev->struct_mutex); |
535 | ||
2017263e BG |
536 | return 0; |
537 | } | |
538 | ||
a6172a80 CW |
539 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
540 | { | |
541 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
542 | struct drm_device *dev = node->minor->dev; | |
543 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
544 | int i, ret; |
545 | ||
546 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
547 | if (ret) | |
548 | return ret; | |
a6172a80 CW |
549 | |
550 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
551 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
552 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 553 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 554 | |
c2c347a9 CW |
555 | seq_printf(m, "Fenced object[%2d] = ", i); |
556 | if (obj == NULL) | |
557 | seq_printf(m, "unused"); | |
558 | else | |
05394f39 | 559 | describe_obj(m, obj); |
c2c347a9 | 560 | seq_printf(m, "\n"); |
a6172a80 CW |
561 | } |
562 | ||
05394f39 | 563 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
564 | return 0; |
565 | } | |
566 | ||
2017263e BG |
567 | static int i915_hws_info(struct seq_file *m, void *data) |
568 | { | |
569 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
570 | struct drm_device *dev = node->minor->dev; | |
571 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 572 | struct intel_ring_buffer *ring; |
311bd68e | 573 | const volatile u32 __iomem *hws; |
4066c0ae CW |
574 | int i; |
575 | ||
1ec14ad3 | 576 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
311bd68e | 577 | hws = (volatile u32 __iomem *)ring->status_page.page_addr; |
2017263e BG |
578 | if (hws == NULL) |
579 | return 0; | |
580 | ||
581 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
582 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
583 | i * 4, | |
584 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
585 | } | |
586 | return 0; | |
587 | } | |
588 | ||
e5c65260 CW |
589 | static const char *ring_str(int ring) |
590 | { | |
591 | switch (ring) { | |
96154f2f DV |
592 | case RCS: return "render"; |
593 | case VCS: return "bsd"; | |
594 | case BCS: return "blt"; | |
e5c65260 CW |
595 | default: return ""; |
596 | } | |
597 | } | |
598 | ||
9df30794 CW |
599 | static const char *pin_flag(int pinned) |
600 | { | |
601 | if (pinned > 0) | |
602 | return " P"; | |
603 | else if (pinned < 0) | |
604 | return " p"; | |
605 | else | |
606 | return ""; | |
607 | } | |
608 | ||
609 | static const char *tiling_flag(int tiling) | |
610 | { | |
611 | switch (tiling) { | |
612 | default: | |
613 | case I915_TILING_NONE: return ""; | |
614 | case I915_TILING_X: return " X"; | |
615 | case I915_TILING_Y: return " Y"; | |
616 | } | |
617 | } | |
618 | ||
619 | static const char *dirty_flag(int dirty) | |
620 | { | |
621 | return dirty ? " dirty" : ""; | |
622 | } | |
623 | ||
624 | static const char *purgeable_flag(int purgeable) | |
625 | { | |
626 | return purgeable ? " purgeable" : ""; | |
627 | } | |
628 | ||
c724e8a9 CW |
629 | static void print_error_buffers(struct seq_file *m, |
630 | const char *name, | |
631 | struct drm_i915_error_buffer *err, | |
632 | int count) | |
633 | { | |
634 | seq_printf(m, "%s [%d]:\n", name, count); | |
635 | ||
636 | while (count--) { | |
96154f2f | 637 | seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s%s", |
c724e8a9 CW |
638 | err->gtt_offset, |
639 | err->size, | |
640 | err->read_domains, | |
641 | err->write_domain, | |
642 | err->seqno, | |
643 | pin_flag(err->pinned), | |
644 | tiling_flag(err->tiling), | |
645 | dirty_flag(err->dirty), | |
646 | purgeable_flag(err->purgeable), | |
96154f2f | 647 | err->ring != -1 ? " " : "", |
a779e5ab | 648 | ring_str(err->ring), |
93dfb40c | 649 | cache_level_str(err->cache_level)); |
c724e8a9 CW |
650 | |
651 | if (err->name) | |
652 | seq_printf(m, " (name: %d)", err->name); | |
653 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
654 | seq_printf(m, " (fence: %d)", err->fence_reg); | |
655 | ||
656 | seq_printf(m, "\n"); | |
657 | err++; | |
658 | } | |
659 | } | |
660 | ||
d27b1e0e DV |
661 | static void i915_ring_error_state(struct seq_file *m, |
662 | struct drm_device *dev, | |
663 | struct drm_i915_error_state *error, | |
664 | unsigned ring) | |
665 | { | |
ec34a01d | 666 | BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ |
d27b1e0e | 667 | seq_printf(m, "%s command stream:\n", ring_str(ring)); |
c1cd90ed DV |
668 | seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]); |
669 | seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); | |
d27b1e0e DV |
670 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); |
671 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); | |
672 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); | |
673 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); | |
c1cd90ed DV |
674 | if (ring == RCS && INTEL_INFO(dev)->gen >= 4) { |
675 | seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); | |
676 | seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); | |
d27b1e0e | 677 | } |
c1cd90ed DV |
678 | if (INTEL_INFO(dev)->gen >= 4) |
679 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); | |
680 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); | |
9d2f41fa | 681 | seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); |
33f3f518 | 682 | if (INTEL_INFO(dev)->gen >= 6) { |
33f3f518 | 683 | seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); |
7e3b8737 DV |
684 | seq_printf(m, " SYNC_0: 0x%08x\n", |
685 | error->semaphore_mboxes[ring][0]); | |
686 | seq_printf(m, " SYNC_1: 0x%08x\n", | |
687 | error->semaphore_mboxes[ring][1]); | |
33f3f518 | 688 | } |
d27b1e0e | 689 | seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); |
7e3b8737 DV |
690 | seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); |
691 | seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); | |
d27b1e0e DV |
692 | } |
693 | ||
63eeaf38 JB |
694 | static int i915_error_state(struct seq_file *m, void *unused) |
695 | { | |
696 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
697 | struct drm_device *dev = node->minor->dev; | |
698 | drm_i915_private_t *dev_priv = dev->dev_private; | |
699 | struct drm_i915_error_state *error; | |
700 | unsigned long flags; | |
52d39a21 | 701 | int i, j, page, offset, elt; |
63eeaf38 JB |
702 | |
703 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
704 | if (!dev_priv->first_error) { | |
705 | seq_printf(m, "no error state collected\n"); | |
706 | goto out; | |
707 | } | |
708 | ||
709 | error = dev_priv->first_error; | |
710 | ||
8a905236 JB |
711 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
712 | error->time.tv_usec); | |
9df30794 | 713 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
1d8f38f4 | 714 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
be998e2e | 715 | seq_printf(m, "IER: 0x%08x\n", error->ier); |
1d8f38f4 | 716 | seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); |
9df30794 | 717 | |
bf3301ab | 718 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
719 | seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
720 | ||
33f3f518 | 721 | if (INTEL_INFO(dev)->gen >= 6) { |
d27b1e0e | 722 | seq_printf(m, "ERROR: 0x%08x\n", error->error); |
33f3f518 DV |
723 | seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); |
724 | } | |
d27b1e0e DV |
725 | |
726 | i915_ring_error_state(m, dev, error, RCS); | |
727 | if (HAS_BLT(dev)) | |
728 | i915_ring_error_state(m, dev, error, BCS); | |
729 | if (HAS_BSD(dev)) | |
730 | i915_ring_error_state(m, dev, error, VCS); | |
731 | ||
c724e8a9 CW |
732 | if (error->active_bo) |
733 | print_error_buffers(m, "Active", | |
734 | error->active_bo, | |
735 | error->active_bo_count); | |
736 | ||
737 | if (error->pinned_bo) | |
738 | print_error_buffers(m, "Pinned", | |
739 | error->pinned_bo, | |
740 | error->pinned_bo_count); | |
9df30794 | 741 | |
52d39a21 CW |
742 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
743 | struct drm_i915_error_object *obj; | |
9df30794 | 744 | |
52d39a21 | 745 | if ((obj = error->ring[i].batchbuffer)) { |
bcfb2e28 CW |
746 | seq_printf(m, "%s --- gtt_offset = 0x%08x\n", |
747 | dev_priv->ring[i].name, | |
748 | obj->gtt_offset); | |
9df30794 CW |
749 | offset = 0; |
750 | for (page = 0; page < obj->page_count; page++) { | |
751 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
752 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
753 | offset += 4; | |
754 | } | |
755 | } | |
756 | } | |
9df30794 | 757 | |
52d39a21 CW |
758 | if (error->ring[i].num_requests) { |
759 | seq_printf(m, "%s --- %d requests\n", | |
760 | dev_priv->ring[i].name, | |
761 | error->ring[i].num_requests); | |
762 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
ee4f42b1 | 763 | seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", |
52d39a21 | 764 | error->ring[i].requests[j].seqno, |
ee4f42b1 CW |
765 | error->ring[i].requests[j].jiffies, |
766 | error->ring[i].requests[j].tail); | |
52d39a21 CW |
767 | } |
768 | } | |
769 | ||
770 | if ((obj = error->ring[i].ringbuffer)) { | |
e2f973d5 CW |
771 | seq_printf(m, "%s --- ringbuffer = 0x%08x\n", |
772 | dev_priv->ring[i].name, | |
773 | obj->gtt_offset); | |
774 | offset = 0; | |
775 | for (page = 0; page < obj->page_count; page++) { | |
776 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
777 | seq_printf(m, "%08x : %08x\n", | |
778 | offset, | |
779 | obj->pages[page][elt]); | |
780 | offset += 4; | |
781 | } | |
9df30794 CW |
782 | } |
783 | } | |
784 | } | |
63eeaf38 | 785 | |
6ef3d427 CW |
786 | if (error->overlay) |
787 | intel_overlay_print_error_state(m, error->overlay); | |
788 | ||
c4a1d9e4 CW |
789 | if (error->display) |
790 | intel_display_print_error_state(m, dev, error->display); | |
791 | ||
63eeaf38 JB |
792 | out: |
793 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
794 | ||
795 | return 0; | |
796 | } | |
6911a9b8 | 797 | |
f97108d1 JB |
798 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
799 | { | |
800 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
801 | struct drm_device *dev = node->minor->dev; | |
802 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
803 | u16 crstanddelay; |
804 | int ret; | |
805 | ||
806 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
807 | if (ret) | |
808 | return ret; | |
809 | ||
810 | crstanddelay = I915_READ16(CRSTANDVID); | |
811 | ||
812 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
813 | |
814 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
819 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
820 | { | |
821 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
822 | struct drm_device *dev = node->minor->dev; | |
823 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 824 | int ret; |
3b8d8d91 JB |
825 | |
826 | if (IS_GEN5(dev)) { | |
827 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
828 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
829 | ||
830 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
831 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
832 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
833 | MEMSTAT_VID_SHIFT); | |
834 | seq_printf(m, "Current P-state: %d\n", | |
835 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
1c70c0ce | 836 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 JB |
837 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
838 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
839 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
ccab5c82 JB |
840 | u32 rpstat; |
841 | u32 rpupei, rpcurup, rpprevup; | |
842 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
843 | int max_freq; |
844 | ||
845 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
846 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
847 | if (ret) | |
848 | return ret; | |
849 | ||
fcca7926 | 850 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 851 | |
ccab5c82 JB |
852 | rpstat = I915_READ(GEN6_RPSTAT1); |
853 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
854 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
855 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
856 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
857 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
858 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
859 | ||
d1ebd816 BW |
860 | gen6_gt_force_wake_put(dev_priv); |
861 | mutex_unlock(&dev->struct_mutex); | |
862 | ||
3b8d8d91 | 863 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 864 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
865 | seq_printf(m, "Render p-state ratio: %d\n", |
866 | (gt_perf_status & 0xff00) >> 8); | |
867 | seq_printf(m, "Render p-state VID: %d\n", | |
868 | gt_perf_status & 0xff); | |
869 | seq_printf(m, "Render p-state limit: %d\n", | |
870 | rp_state_limits & 0xff); | |
ccab5c82 | 871 | seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> |
e281fcaa | 872 | GEN6_CAGF_SHIFT) * 50); |
ccab5c82 JB |
873 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
874 | GEN6_CURICONT_MASK); | |
875 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
876 | GEN6_CURBSYTAVG_MASK); | |
877 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
878 | GEN6_CURBSYTAVG_MASK); | |
879 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
880 | GEN6_CURIAVG_MASK); | |
881 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
882 | GEN6_CURBSYTAVG_MASK); | |
883 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
884 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
885 | |
886 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
887 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
e281fcaa | 888 | max_freq * 50); |
3b8d8d91 JB |
889 | |
890 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
891 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
e281fcaa | 892 | max_freq * 50); |
3b8d8d91 JB |
893 | |
894 | max_freq = rp_state_cap & 0xff; | |
895 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
e281fcaa | 896 | max_freq * 50); |
3b8d8d91 JB |
897 | } else { |
898 | seq_printf(m, "no P-state info available\n"); | |
899 | } | |
f97108d1 JB |
900 | |
901 | return 0; | |
902 | } | |
903 | ||
904 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
905 | { | |
906 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
907 | struct drm_device *dev = node->minor->dev; | |
908 | drm_i915_private_t *dev_priv = dev->dev_private; | |
909 | u32 delayfreq; | |
616fdb5a BW |
910 | int ret, i; |
911 | ||
912 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
913 | if (ret) | |
914 | return ret; | |
f97108d1 JB |
915 | |
916 | for (i = 0; i < 16; i++) { | |
917 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
918 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
919 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
920 | } |
921 | ||
616fdb5a BW |
922 | mutex_unlock(&dev->struct_mutex); |
923 | ||
f97108d1 JB |
924 | return 0; |
925 | } | |
926 | ||
927 | static inline int MAP_TO_MV(int map) | |
928 | { | |
929 | return 1250 - (map * 25); | |
930 | } | |
931 | ||
932 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
933 | { | |
934 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
935 | struct drm_device *dev = node->minor->dev; | |
936 | drm_i915_private_t *dev_priv = dev->dev_private; | |
937 | u32 inttoext; | |
616fdb5a BW |
938 | int ret, i; |
939 | ||
940 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
941 | if (ret) | |
942 | return ret; | |
f97108d1 JB |
943 | |
944 | for (i = 1; i <= 32; i++) { | |
945 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
946 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
947 | } | |
948 | ||
616fdb5a BW |
949 | mutex_unlock(&dev->struct_mutex); |
950 | ||
f97108d1 JB |
951 | return 0; |
952 | } | |
953 | ||
4d85529d | 954 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
955 | { |
956 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
957 | struct drm_device *dev = node->minor->dev; | |
958 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
959 | u32 rgvmodectl, rstdbyctl; |
960 | u16 crstandvid; | |
961 | int ret; | |
962 | ||
963 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
964 | if (ret) | |
965 | return ret; | |
966 | ||
967 | rgvmodectl = I915_READ(MEMMODECTL); | |
968 | rstdbyctl = I915_READ(RSTDBYCTL); | |
969 | crstandvid = I915_READ16(CRSTANDVID); | |
970 | ||
971 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
972 | |
973 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
974 | "yes" : "no"); | |
975 | seq_printf(m, "Boost freq: %d\n", | |
976 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
977 | MEMMODE_BOOST_FREQ_SHIFT); | |
978 | seq_printf(m, "HW control enabled: %s\n", | |
979 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
980 | seq_printf(m, "SW control enabled: %s\n", | |
981 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
982 | seq_printf(m, "Gated voltage change: %s\n", | |
983 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
984 | seq_printf(m, "Starting frequency: P%d\n", | |
985 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 986 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 987 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
988 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
989 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
990 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
991 | seq_printf(m, "Render standby enabled: %s\n", | |
992 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
88271da3 JB |
993 | seq_printf(m, "Current RS state: "); |
994 | switch (rstdbyctl & RSX_STATUS_MASK) { | |
995 | case RSX_STATUS_ON: | |
996 | seq_printf(m, "on\n"); | |
997 | break; | |
998 | case RSX_STATUS_RC1: | |
999 | seq_printf(m, "RC1\n"); | |
1000 | break; | |
1001 | case RSX_STATUS_RC1E: | |
1002 | seq_printf(m, "RC1E\n"); | |
1003 | break; | |
1004 | case RSX_STATUS_RS1: | |
1005 | seq_printf(m, "RS1\n"); | |
1006 | break; | |
1007 | case RSX_STATUS_RS2: | |
1008 | seq_printf(m, "RS2 (RC6)\n"); | |
1009 | break; | |
1010 | case RSX_STATUS_RS3: | |
1011 | seq_printf(m, "RC3 (RC6+)\n"); | |
1012 | break; | |
1013 | default: | |
1014 | seq_printf(m, "unknown\n"); | |
1015 | break; | |
1016 | } | |
f97108d1 JB |
1017 | |
1018 | return 0; | |
1019 | } | |
1020 | ||
4d85529d BW |
1021 | static int gen6_drpc_info(struct seq_file *m) |
1022 | { | |
1023 | ||
1024 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1025 | struct drm_device *dev = node->minor->dev; | |
1026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1027 | u32 rpmodectl1, gt_core_status, rcctl1; | |
93b525dc | 1028 | unsigned forcewake_count; |
4d85529d BW |
1029 | int count=0, ret; |
1030 | ||
1031 | ||
1032 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1033 | if (ret) | |
1034 | return ret; | |
1035 | ||
93b525dc DV |
1036 | spin_lock_irq(&dev_priv->gt_lock); |
1037 | forcewake_count = dev_priv->forcewake_count; | |
1038 | spin_unlock_irq(&dev_priv->gt_lock); | |
1039 | ||
1040 | if (forcewake_count) { | |
1041 | seq_printf(m, "RC information inaccurate because somebody " | |
1042 | "holds a forcewake reference \n"); | |
4d85529d BW |
1043 | } else { |
1044 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1045 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1046 | udelay(10); | |
1047 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1048 | } | |
1049 | ||
1050 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
1051 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); | |
1052 | ||
1053 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1054 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1055 | mutex_unlock(&dev->struct_mutex); | |
1056 | ||
1057 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1058 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1059 | seq_printf(m, "HW control enabled: %s\n", | |
1060 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1061 | seq_printf(m, "SW control enabled: %s\n", | |
1062 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1063 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1064 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1065 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1066 | seq_printf(m, "RC6 Enabled: %s\n", | |
1067 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1068 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1069 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1070 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1071 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
1072 | seq_printf(m, "Current RC state: "); | |
1073 | switch (gt_core_status & GEN6_RCn_MASK) { | |
1074 | case GEN6_RC0: | |
1075 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
1076 | seq_printf(m, "Core Power Down\n"); | |
1077 | else | |
1078 | seq_printf(m, "on\n"); | |
1079 | break; | |
1080 | case GEN6_RC3: | |
1081 | seq_printf(m, "RC3\n"); | |
1082 | break; | |
1083 | case GEN6_RC6: | |
1084 | seq_printf(m, "RC6\n"); | |
1085 | break; | |
1086 | case GEN6_RC7: | |
1087 | seq_printf(m, "RC7\n"); | |
1088 | break; | |
1089 | default: | |
1090 | seq_printf(m, "Unknown\n"); | |
1091 | break; | |
1092 | } | |
1093 | ||
1094 | seq_printf(m, "Core Power Down: %s\n", | |
1095 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1096 | |
1097 | /* Not exactly sure what this is */ | |
1098 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1099 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1100 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1101 | I915_READ(GEN6_GT_GFX_RC6)); | |
1102 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1103 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1104 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1105 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1106 | ||
4d85529d BW |
1107 | return 0; |
1108 | } | |
1109 | ||
1110 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1111 | { | |
1112 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1113 | struct drm_device *dev = node->minor->dev; | |
1114 | ||
1115 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1116 | return gen6_drpc_info(m); | |
1117 | else | |
1118 | return ironlake_drpc_info(m); | |
1119 | } | |
1120 | ||
b5e50c3f JB |
1121 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1122 | { | |
1123 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1124 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1125 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1126 | |
ee5382ae | 1127 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
1128 | seq_printf(m, "FBC unsupported on this chipset\n"); |
1129 | return 0; | |
1130 | } | |
1131 | ||
ee5382ae | 1132 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
1133 | seq_printf(m, "FBC enabled\n"); |
1134 | } else { | |
1135 | seq_printf(m, "FBC disabled: "); | |
1136 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
1137 | case FBC_NO_OUTPUT: |
1138 | seq_printf(m, "no outputs"); | |
1139 | break; | |
b5e50c3f JB |
1140 | case FBC_STOLEN_TOO_SMALL: |
1141 | seq_printf(m, "not enough stolen memory"); | |
1142 | break; | |
1143 | case FBC_UNSUPPORTED_MODE: | |
1144 | seq_printf(m, "mode not supported"); | |
1145 | break; | |
1146 | case FBC_MODE_TOO_LARGE: | |
1147 | seq_printf(m, "mode too large"); | |
1148 | break; | |
1149 | case FBC_BAD_PLANE: | |
1150 | seq_printf(m, "FBC unsupported on plane"); | |
1151 | break; | |
1152 | case FBC_NOT_TILED: | |
1153 | seq_printf(m, "scanout buffer not tiled"); | |
1154 | break; | |
9c928d16 JB |
1155 | case FBC_MULTIPLE_PIPES: |
1156 | seq_printf(m, "multiple pipes are enabled"); | |
1157 | break; | |
c1a9f047 JB |
1158 | case FBC_MODULE_PARAM: |
1159 | seq_printf(m, "disabled per module param (default off)"); | |
1160 | break; | |
b5e50c3f JB |
1161 | default: |
1162 | seq_printf(m, "unknown reason"); | |
1163 | } | |
1164 | seq_printf(m, "\n"); | |
1165 | } | |
1166 | return 0; | |
1167 | } | |
1168 | ||
4a9bef37 JB |
1169 | static int i915_sr_status(struct seq_file *m, void *unused) |
1170 | { | |
1171 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1172 | struct drm_device *dev = node->minor->dev; | |
1173 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1174 | bool sr_enabled = false; | |
1175 | ||
1398261a | 1176 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1177 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1178 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1179 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1180 | else if (IS_I915GM(dev)) | |
1181 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1182 | else if (IS_PINEVIEW(dev)) | |
1183 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1184 | ||
5ba2aaaa CW |
1185 | seq_printf(m, "self-refresh: %s\n", |
1186 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1187 | |
1188 | return 0; | |
1189 | } | |
1190 | ||
7648fa99 JB |
1191 | static int i915_emon_status(struct seq_file *m, void *unused) |
1192 | { | |
1193 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1194 | struct drm_device *dev = node->minor->dev; | |
1195 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1196 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1197 | int ret; |
1198 | ||
1199 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1200 | if (ret) | |
1201 | return ret; | |
7648fa99 JB |
1202 | |
1203 | temp = i915_mch_val(dev_priv); | |
1204 | chipset = i915_chipset_val(dev_priv); | |
1205 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1206 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1207 | |
1208 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1209 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1210 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1211 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
23b2f8bb JB |
1216 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1217 | { | |
1218 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1219 | struct drm_device *dev = node->minor->dev; | |
1220 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1221 | int ret; | |
1222 | int gpu_freq, ia_freq; | |
1223 | ||
1c70c0ce | 1224 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
23b2f8bb JB |
1225 | seq_printf(m, "unsupported on this chipset\n"); |
1226 | return 0; | |
1227 | } | |
1228 | ||
1229 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1230 | if (ret) | |
1231 | return ret; | |
1232 | ||
1233 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); | |
1234 | ||
1235 | for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay; | |
1236 | gpu_freq++) { | |
1237 | I915_WRITE(GEN6_PCODE_DATA, gpu_freq); | |
1238 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
1239 | GEN6_PCODE_READ_MIN_FREQ_TABLE); | |
1240 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
1241 | GEN6_PCODE_READY) == 0, 10)) { | |
1242 | DRM_ERROR("pcode read of freq table timed out\n"); | |
1243 | continue; | |
1244 | } | |
1245 | ia_freq = I915_READ(GEN6_PCODE_DATA); | |
1246 | seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100); | |
1247 | } | |
1248 | ||
1249 | mutex_unlock(&dev->struct_mutex); | |
1250 | ||
1251 | return 0; | |
1252 | } | |
1253 | ||
7648fa99 JB |
1254 | static int i915_gfxec(struct seq_file *m, void *unused) |
1255 | { | |
1256 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1257 | struct drm_device *dev = node->minor->dev; | |
1258 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1259 | int ret; |
1260 | ||
1261 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1262 | if (ret) | |
1263 | return ret; | |
7648fa99 JB |
1264 | |
1265 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1266 | ||
616fdb5a BW |
1267 | mutex_unlock(&dev->struct_mutex); |
1268 | ||
7648fa99 JB |
1269 | return 0; |
1270 | } | |
1271 | ||
44834a67 CW |
1272 | static int i915_opregion(struct seq_file *m, void *unused) |
1273 | { | |
1274 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1275 | struct drm_device *dev = node->minor->dev; | |
1276 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1277 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1278 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1279 | int ret; |
1280 | ||
0d38f009 DV |
1281 | if (data == NULL) |
1282 | return -ENOMEM; | |
1283 | ||
44834a67 CW |
1284 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1285 | if (ret) | |
0d38f009 | 1286 | goto out; |
44834a67 | 1287 | |
0d38f009 DV |
1288 | if (opregion->header) { |
1289 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1290 | seq_write(m, data, OPREGION_SIZE); | |
1291 | } | |
44834a67 CW |
1292 | |
1293 | mutex_unlock(&dev->struct_mutex); | |
1294 | ||
0d38f009 DV |
1295 | out: |
1296 | kfree(data); | |
44834a67 CW |
1297 | return 0; |
1298 | } | |
1299 | ||
37811fcc CW |
1300 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1301 | { | |
1302 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1303 | struct drm_device *dev = node->minor->dev; | |
1304 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1305 | struct intel_fbdev *ifbdev; | |
1306 | struct intel_framebuffer *fb; | |
1307 | int ret; | |
1308 | ||
1309 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1310 | if (ret) | |
1311 | return ret; | |
1312 | ||
1313 | ifbdev = dev_priv->fbdev; | |
1314 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1315 | ||
1316 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", | |
1317 | fb->base.width, | |
1318 | fb->base.height, | |
1319 | fb->base.depth, | |
1320 | fb->base.bits_per_pixel); | |
05394f39 | 1321 | describe_obj(m, fb->obj); |
37811fcc CW |
1322 | seq_printf(m, "\n"); |
1323 | ||
1324 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { | |
1325 | if (&fb->base == ifbdev->helper.fb) | |
1326 | continue; | |
1327 | ||
1328 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", | |
1329 | fb->base.width, | |
1330 | fb->base.height, | |
1331 | fb->base.depth, | |
1332 | fb->base.bits_per_pixel); | |
05394f39 | 1333 | describe_obj(m, fb->obj); |
37811fcc CW |
1334 | seq_printf(m, "\n"); |
1335 | } | |
1336 | ||
1337 | mutex_unlock(&dev->mode_config.mutex); | |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | ||
e76d3630 BW |
1342 | static int i915_context_status(struct seq_file *m, void *unused) |
1343 | { | |
1344 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1345 | struct drm_device *dev = node->minor->dev; | |
1346 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1347 | int ret; | |
1348 | ||
1349 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1350 | if (ret) | |
1351 | return ret; | |
1352 | ||
dc501fbc BW |
1353 | if (dev_priv->pwrctx) { |
1354 | seq_printf(m, "power context "); | |
1355 | describe_obj(m, dev_priv->pwrctx); | |
1356 | seq_printf(m, "\n"); | |
1357 | } | |
e76d3630 | 1358 | |
dc501fbc BW |
1359 | if (dev_priv->renderctx) { |
1360 | seq_printf(m, "render context "); | |
1361 | describe_obj(m, dev_priv->renderctx); | |
1362 | seq_printf(m, "\n"); | |
1363 | } | |
e76d3630 BW |
1364 | |
1365 | mutex_unlock(&dev->mode_config.mutex); | |
1366 | ||
1367 | return 0; | |
1368 | } | |
1369 | ||
6d794d42 BW |
1370 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1371 | { | |
1372 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1373 | struct drm_device *dev = node->minor->dev; | |
1374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1375 | unsigned forcewake_count; |
6d794d42 | 1376 | |
9f1f46a4 DV |
1377 | spin_lock_irq(&dev_priv->gt_lock); |
1378 | forcewake_count = dev_priv->forcewake_count; | |
1379 | spin_unlock_irq(&dev_priv->gt_lock); | |
6d794d42 | 1380 | |
9f1f46a4 | 1381 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1382 | |
1383 | return 0; | |
1384 | } | |
1385 | ||
ea16a3cd DV |
1386 | static const char *swizzle_string(unsigned swizzle) |
1387 | { | |
1388 | switch(swizzle) { | |
1389 | case I915_BIT_6_SWIZZLE_NONE: | |
1390 | return "none"; | |
1391 | case I915_BIT_6_SWIZZLE_9: | |
1392 | return "bit9"; | |
1393 | case I915_BIT_6_SWIZZLE_9_10: | |
1394 | return "bit9/bit10"; | |
1395 | case I915_BIT_6_SWIZZLE_9_11: | |
1396 | return "bit9/bit11"; | |
1397 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1398 | return "bit9/bit10/bit11"; | |
1399 | case I915_BIT_6_SWIZZLE_9_17: | |
1400 | return "bit9/bit17"; | |
1401 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1402 | return "bit9/bit10/bit17"; | |
1403 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
1404 | return "unkown"; | |
1405 | } | |
1406 | ||
1407 | return "bug"; | |
1408 | } | |
1409 | ||
1410 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1411 | { | |
1412 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1413 | struct drm_device *dev = node->minor->dev; | |
1414 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1415 | ||
1416 | mutex_lock(&dev->struct_mutex); | |
1417 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", | |
1418 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1419 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1420 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1421 | ||
1422 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1423 | seq_printf(m, "DDC = 0x%08x\n", | |
1424 | I915_READ(DCC)); | |
1425 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1426 | I915_READ16(C0DRB3)); | |
1427 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1428 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1429 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1430 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1431 | I915_READ(MAD_DIMM_C0)); | |
1432 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1433 | I915_READ(MAD_DIMM_C1)); | |
1434 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1435 | I915_READ(MAD_DIMM_C2)); | |
1436 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1437 | I915_READ(TILECTL)); | |
1438 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1439 | I915_READ(ARB_MODE)); | |
1440 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1441 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1442 | } |
1443 | mutex_unlock(&dev->struct_mutex); | |
1444 | ||
1445 | return 0; | |
1446 | } | |
1447 | ||
3cf17fc5 DV |
1448 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1449 | { | |
1450 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1451 | struct drm_device *dev = node->minor->dev; | |
1452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1453 | struct intel_ring_buffer *ring; | |
1454 | int i, ret; | |
1455 | ||
1456 | ||
1457 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1458 | if (ret) | |
1459 | return ret; | |
1460 | if (INTEL_INFO(dev)->gen == 6) | |
1461 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1462 | ||
1463 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1464 | ring = &dev_priv->ring[i]; | |
1465 | ||
1466 | seq_printf(m, "%s\n", ring->name); | |
1467 | if (INTEL_INFO(dev)->gen == 7) | |
1468 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1469 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1470 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1471 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1472 | } | |
1473 | if (dev_priv->mm.aliasing_ppgtt) { | |
1474 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1475 | ||
1476 | seq_printf(m, "aliasing PPGTT:\n"); | |
1477 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); | |
1478 | } | |
1479 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1480 | mutex_unlock(&dev->struct_mutex); | |
1481 | ||
1482 | return 0; | |
1483 | } | |
1484 | ||
57f350b6 JB |
1485 | static int i915_dpio_info(struct seq_file *m, void *data) |
1486 | { | |
1487 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1488 | struct drm_device *dev = node->minor->dev; | |
1489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1490 | int ret; | |
1491 | ||
1492 | ||
1493 | if (!IS_VALLEYVIEW(dev)) { | |
1494 | seq_printf(m, "unsupported\n"); | |
1495 | return 0; | |
1496 | } | |
1497 | ||
1498 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1499 | if (ret) | |
1500 | return ret; | |
1501 | ||
1502 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1503 | ||
1504 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
1505 | intel_dpio_read(dev_priv, _DPIO_DIV_A)); | |
1506 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", | |
1507 | intel_dpio_read(dev_priv, _DPIO_DIV_B)); | |
1508 | ||
1509 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
1510 | intel_dpio_read(dev_priv, _DPIO_REFSFR_A)); | |
1511 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", | |
1512 | intel_dpio_read(dev_priv, _DPIO_REFSFR_B)); | |
1513 | ||
1514 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
1515 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); | |
1516 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", | |
1517 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); | |
1518 | ||
1519 | seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", | |
1520 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); | |
1521 | seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", | |
1522 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); | |
1523 | ||
1524 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
1525 | intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); | |
1526 | ||
1527 | mutex_unlock(&dev->mode_config.mutex); | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
f3cd474b CW |
1532 | static ssize_t |
1533 | i915_wedged_read(struct file *filp, | |
1534 | char __user *ubuf, | |
1535 | size_t max, | |
1536 | loff_t *ppos) | |
1537 | { | |
1538 | struct drm_device *dev = filp->private_data; | |
1539 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1540 | char buf[80]; | |
1541 | int len; | |
1542 | ||
0206e353 | 1543 | len = snprintf(buf, sizeof(buf), |
f3cd474b CW |
1544 | "wedged : %d\n", |
1545 | atomic_read(&dev_priv->mm.wedged)); | |
1546 | ||
0206e353 AJ |
1547 | if (len > sizeof(buf)) |
1548 | len = sizeof(buf); | |
f4433a8d | 1549 | |
f3cd474b CW |
1550 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
1551 | } | |
1552 | ||
1553 | static ssize_t | |
1554 | i915_wedged_write(struct file *filp, | |
1555 | const char __user *ubuf, | |
1556 | size_t cnt, | |
1557 | loff_t *ppos) | |
1558 | { | |
1559 | struct drm_device *dev = filp->private_data; | |
f3cd474b CW |
1560 | char buf[20]; |
1561 | int val = 1; | |
1562 | ||
1563 | if (cnt > 0) { | |
0206e353 | 1564 | if (cnt > sizeof(buf) - 1) |
f3cd474b CW |
1565 | return -EINVAL; |
1566 | ||
1567 | if (copy_from_user(buf, ubuf, cnt)) | |
1568 | return -EFAULT; | |
1569 | buf[cnt] = 0; | |
1570 | ||
1571 | val = simple_strtoul(buf, NULL, 0); | |
1572 | } | |
1573 | ||
1574 | DRM_INFO("Manually setting wedged to %d\n", val); | |
527f9e90 | 1575 | i915_handle_error(dev, val); |
f3cd474b CW |
1576 | |
1577 | return cnt; | |
1578 | } | |
1579 | ||
1580 | static const struct file_operations i915_wedged_fops = { | |
1581 | .owner = THIS_MODULE, | |
234e3405 | 1582 | .open = simple_open, |
f3cd474b CW |
1583 | .read = i915_wedged_read, |
1584 | .write = i915_wedged_write, | |
6038f373 | 1585 | .llseek = default_llseek, |
f3cd474b CW |
1586 | }; |
1587 | ||
358733e9 JB |
1588 | static ssize_t |
1589 | i915_max_freq_read(struct file *filp, | |
1590 | char __user *ubuf, | |
1591 | size_t max, | |
1592 | loff_t *ppos) | |
1593 | { | |
1594 | struct drm_device *dev = filp->private_data; | |
1595 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1596 | char buf[80]; | |
1597 | int len; | |
1598 | ||
0206e353 | 1599 | len = snprintf(buf, sizeof(buf), |
358733e9 JB |
1600 | "max freq: %d\n", dev_priv->max_delay * 50); |
1601 | ||
0206e353 AJ |
1602 | if (len > sizeof(buf)) |
1603 | len = sizeof(buf); | |
358733e9 JB |
1604 | |
1605 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1606 | } | |
1607 | ||
1608 | static ssize_t | |
1609 | i915_max_freq_write(struct file *filp, | |
1610 | const char __user *ubuf, | |
1611 | size_t cnt, | |
1612 | loff_t *ppos) | |
1613 | { | |
1614 | struct drm_device *dev = filp->private_data; | |
1615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1616 | char buf[20]; | |
1617 | int val = 1; | |
1618 | ||
1619 | if (cnt > 0) { | |
0206e353 | 1620 | if (cnt > sizeof(buf) - 1) |
358733e9 JB |
1621 | return -EINVAL; |
1622 | ||
1623 | if (copy_from_user(buf, ubuf, cnt)) | |
1624 | return -EFAULT; | |
1625 | buf[cnt] = 0; | |
1626 | ||
1627 | val = simple_strtoul(buf, NULL, 0); | |
1628 | } | |
1629 | ||
1630 | DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); | |
1631 | ||
1632 | /* | |
1633 | * Turbo will still be enabled, but won't go above the set value. | |
1634 | */ | |
1635 | dev_priv->max_delay = val / 50; | |
1636 | ||
1637 | gen6_set_rps(dev, val / 50); | |
1638 | ||
1639 | return cnt; | |
1640 | } | |
1641 | ||
1642 | static const struct file_operations i915_max_freq_fops = { | |
1643 | .owner = THIS_MODULE, | |
234e3405 | 1644 | .open = simple_open, |
358733e9 JB |
1645 | .read = i915_max_freq_read, |
1646 | .write = i915_max_freq_write, | |
1647 | .llseek = default_llseek, | |
1648 | }; | |
1649 | ||
07b7ddd9 JB |
1650 | static ssize_t |
1651 | i915_cache_sharing_read(struct file *filp, | |
1652 | char __user *ubuf, | |
1653 | size_t max, | |
1654 | loff_t *ppos) | |
1655 | { | |
1656 | struct drm_device *dev = filp->private_data; | |
1657 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1658 | char buf[80]; | |
1659 | u32 snpcr; | |
1660 | int len; | |
1661 | ||
1662 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1663 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1664 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1665 | ||
0206e353 | 1666 | len = snprintf(buf, sizeof(buf), |
07b7ddd9 JB |
1667 | "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> |
1668 | GEN6_MBC_SNPCR_SHIFT); | |
1669 | ||
0206e353 AJ |
1670 | if (len > sizeof(buf)) |
1671 | len = sizeof(buf); | |
07b7ddd9 JB |
1672 | |
1673 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1674 | } | |
1675 | ||
1676 | static ssize_t | |
1677 | i915_cache_sharing_write(struct file *filp, | |
1678 | const char __user *ubuf, | |
1679 | size_t cnt, | |
1680 | loff_t *ppos) | |
1681 | { | |
1682 | struct drm_device *dev = filp->private_data; | |
1683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1684 | char buf[20]; | |
1685 | u32 snpcr; | |
1686 | int val = 1; | |
1687 | ||
1688 | if (cnt > 0) { | |
0206e353 | 1689 | if (cnt > sizeof(buf) - 1) |
07b7ddd9 JB |
1690 | return -EINVAL; |
1691 | ||
1692 | if (copy_from_user(buf, ubuf, cnt)) | |
1693 | return -EFAULT; | |
1694 | buf[cnt] = 0; | |
1695 | ||
1696 | val = simple_strtoul(buf, NULL, 0); | |
1697 | } | |
1698 | ||
1699 | if (val < 0 || val > 3) | |
1700 | return -EINVAL; | |
1701 | ||
1702 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); | |
1703 | ||
1704 | /* Update the cache sharing policy here as well */ | |
1705 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1706 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1707 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1708 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1709 | ||
1710 | return cnt; | |
1711 | } | |
1712 | ||
1713 | static const struct file_operations i915_cache_sharing_fops = { | |
1714 | .owner = THIS_MODULE, | |
234e3405 | 1715 | .open = simple_open, |
07b7ddd9 JB |
1716 | .read = i915_cache_sharing_read, |
1717 | .write = i915_cache_sharing_write, | |
1718 | .llseek = default_llseek, | |
1719 | }; | |
1720 | ||
f3cd474b CW |
1721 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1722 | * allocated we need to hook into the minor for release. */ | |
1723 | static int | |
1724 | drm_add_fake_info_node(struct drm_minor *minor, | |
1725 | struct dentry *ent, | |
1726 | const void *key) | |
1727 | { | |
1728 | struct drm_info_node *node; | |
1729 | ||
1730 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
1731 | if (node == NULL) { | |
1732 | debugfs_remove(ent); | |
1733 | return -ENOMEM; | |
1734 | } | |
1735 | ||
1736 | node->minor = minor; | |
1737 | node->dent = ent; | |
1738 | node->info_ent = (void *) key; | |
b3e067c0 MS |
1739 | |
1740 | mutex_lock(&minor->debugfs_lock); | |
1741 | list_add(&node->list, &minor->debugfs_list); | |
1742 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
1743 | |
1744 | return 0; | |
1745 | } | |
1746 | ||
6d794d42 BW |
1747 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
1748 | { | |
1749 | struct drm_device *dev = inode->i_private; | |
1750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1751 | int ret; | |
1752 | ||
075edca4 | 1753 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1754 | return 0; |
1755 | ||
1756 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1757 | if (ret) | |
1758 | return ret; | |
1759 | gen6_gt_force_wake_get(dev_priv); | |
1760 | mutex_unlock(&dev->struct_mutex); | |
1761 | ||
1762 | return 0; | |
1763 | } | |
1764 | ||
c43b5634 | 1765 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
1766 | { |
1767 | struct drm_device *dev = inode->i_private; | |
1768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1769 | ||
075edca4 | 1770 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1771 | return 0; |
1772 | ||
1773 | /* | |
1774 | * It's bad that we can potentially hang userspace if struct_mutex gets | |
1775 | * forever stuck. However, if we cannot acquire this lock it means that | |
1776 | * almost certainly the driver has hung, is not unload-able. Therefore | |
1777 | * hanging here is probably a minor inconvenience not to be seen my | |
1778 | * almost every user. | |
1779 | */ | |
1780 | mutex_lock(&dev->struct_mutex); | |
1781 | gen6_gt_force_wake_put(dev_priv); | |
1782 | mutex_unlock(&dev->struct_mutex); | |
1783 | ||
1784 | return 0; | |
1785 | } | |
1786 | ||
1787 | static const struct file_operations i915_forcewake_fops = { | |
1788 | .owner = THIS_MODULE, | |
1789 | .open = i915_forcewake_open, | |
1790 | .release = i915_forcewake_release, | |
1791 | }; | |
1792 | ||
1793 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
1794 | { | |
1795 | struct drm_device *dev = minor->dev; | |
1796 | struct dentry *ent; | |
1797 | ||
1798 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 1799 | S_IRUSR, |
6d794d42 BW |
1800 | root, dev, |
1801 | &i915_forcewake_fops); | |
1802 | if (IS_ERR(ent)) | |
1803 | return PTR_ERR(ent); | |
1804 | ||
8eb57294 | 1805 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
1806 | } |
1807 | ||
6a9c308d DV |
1808 | static int i915_debugfs_create(struct dentry *root, |
1809 | struct drm_minor *minor, | |
1810 | const char *name, | |
1811 | const struct file_operations *fops) | |
07b7ddd9 JB |
1812 | { |
1813 | struct drm_device *dev = minor->dev; | |
1814 | struct dentry *ent; | |
1815 | ||
6a9c308d | 1816 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
1817 | S_IRUGO | S_IWUSR, |
1818 | root, dev, | |
6a9c308d | 1819 | fops); |
07b7ddd9 JB |
1820 | if (IS_ERR(ent)) |
1821 | return PTR_ERR(ent); | |
1822 | ||
6a9c308d | 1823 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
1824 | } |
1825 | ||
27c202ad | 1826 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 1827 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 1828 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 1829 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 1830 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 BG |
1831 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
1832 | {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, | |
1833 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, | |
4e5359cd | 1834 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
1835 | {"i915_gem_request", i915_gem_request_info, 0}, |
1836 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 1837 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 1838 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
1839 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
1840 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
1841 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
63eeaf38 | 1842 | {"i915_error_state", i915_error_state, 0}, |
f97108d1 JB |
1843 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
1844 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
1845 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
1846 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
1847 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 1848 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 1849 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 1850 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 1851 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 1852 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 1853 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 1854 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 1855 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 1856 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 1857 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 1858 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 1859 | {"i915_dpio", i915_dpio_info, 0}, |
2017263e | 1860 | }; |
27c202ad | 1861 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 1862 | |
27c202ad | 1863 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 1864 | { |
f3cd474b CW |
1865 | int ret; |
1866 | ||
6a9c308d DV |
1867 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
1868 | "i915_wedged", | |
1869 | &i915_wedged_fops); | |
f3cd474b CW |
1870 | if (ret) |
1871 | return ret; | |
1872 | ||
6d794d42 | 1873 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
1874 | if (ret) |
1875 | return ret; | |
6a9c308d DV |
1876 | |
1877 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
1878 | "i915_max_freq", | |
1879 | &i915_max_freq_fops); | |
07b7ddd9 JB |
1880 | if (ret) |
1881 | return ret; | |
6a9c308d DV |
1882 | |
1883 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
1884 | "i915_cache_sharing", | |
1885 | &i915_cache_sharing_fops); | |
6d794d42 BW |
1886 | if (ret) |
1887 | return ret; | |
1888 | ||
27c202ad BG |
1889 | return drm_debugfs_create_files(i915_debugfs_list, |
1890 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
1891 | minor->debugfs_root, minor); |
1892 | } | |
1893 | ||
27c202ad | 1894 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 1895 | { |
27c202ad BG |
1896 | drm_debugfs_remove_files(i915_debugfs_list, |
1897 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
1898 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
1899 | 1, minor); | |
33db679b KH |
1900 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
1901 | 1, minor); | |
358733e9 JB |
1902 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
1903 | 1, minor); | |
07b7ddd9 JB |
1904 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
1905 | 1, minor); | |
2017263e BG |
1906 | } |
1907 | ||
1908 | #endif /* CONFIG_DEBUG_FS */ |