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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
6d2b8885 | 30 | #include <linux/list_sort.h> |
4e5359cd | 31 | #include "intel_drv.h" |
2017263e | 32 | |
36cdd013 DW |
33 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
34 | { | |
35 | return to_i915(node->minor->dev); | |
36 | } | |
37 | ||
497666d8 DL |
38 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
39 | * allocated we need to hook into the minor for release. */ | |
40 | static int | |
41 | drm_add_fake_info_node(struct drm_minor *minor, | |
42 | struct dentry *ent, | |
43 | const void *key) | |
44 | { | |
45 | struct drm_info_node *node; | |
46 | ||
47 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
48 | if (node == NULL) { | |
49 | debugfs_remove(ent); | |
50 | return -ENOMEM; | |
51 | } | |
52 | ||
53 | node->minor = minor; | |
54 | node->dent = ent; | |
36cdd013 | 55 | node->info_ent = (void *)key; |
497666d8 DL |
56 | |
57 | mutex_lock(&minor->debugfs_lock); | |
58 | list_add(&node->list, &minor->debugfs_list); | |
59 | mutex_unlock(&minor->debugfs_lock); | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
418e3cd8 CW |
64 | static __always_inline void seq_print_param(struct seq_file *m, |
65 | const char *name, | |
66 | const char *type, | |
67 | const void *x) | |
68 | { | |
69 | if (!__builtin_strcmp(type, "bool")) | |
70 | seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x)); | |
71 | else if (!__builtin_strcmp(type, "int")) | |
72 | seq_printf(m, "i915.%s=%d\n", name, *(const int *)x); | |
73 | else if (!__builtin_strcmp(type, "unsigned int")) | |
74 | seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x); | |
1d6aa7a3 CW |
75 | else if (!__builtin_strcmp(type, "char *")) |
76 | seq_printf(m, "i915.%s=%s\n", name, *(const char **)x); | |
418e3cd8 CW |
77 | else |
78 | BUILD_BUG(); | |
79 | } | |
80 | ||
70d39fe4 CW |
81 | static int i915_capabilities(struct seq_file *m, void *data) |
82 | { | |
36cdd013 DW |
83 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
84 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 85 | |
36cdd013 | 86 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 87 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 88 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 89 | |
79fc46df | 90 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 91 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 92 | #undef PRINT_FLAG |
70d39fe4 | 93 | |
418e3cd8 CW |
94 | kernel_param_lock(THIS_MODULE); |
95 | #define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x); | |
96 | I915_PARAMS_FOR_EACH(PRINT_PARAM); | |
97 | #undef PRINT_PARAM | |
98 | kernel_param_unlock(THIS_MODULE); | |
99 | ||
70d39fe4 CW |
100 | return 0; |
101 | } | |
2017263e | 102 | |
a7363de7 | 103 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 104 | { |
573adb39 | 105 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
106 | } |
107 | ||
a7363de7 | 108 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
109 | { |
110 | return obj->pin_display ? 'p' : ' '; | |
111 | } | |
112 | ||
a7363de7 | 113 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 114 | { |
3e510a8e | 115 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 116 | default: |
be12a86b TU |
117 | case I915_TILING_NONE: return ' '; |
118 | case I915_TILING_X: return 'X'; | |
119 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 120 | } |
a6172a80 CW |
121 | } |
122 | ||
a7363de7 | 123 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 124 | { |
275f039d | 125 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
126 | } |
127 | ||
a7363de7 | 128 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 129 | { |
a4f5ea64 | 130 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
131 | } |
132 | ||
ca1543be TU |
133 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
134 | { | |
135 | u64 size = 0; | |
136 | struct i915_vma *vma; | |
137 | ||
1c7f4bca | 138 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 139 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
140 | size += vma->node.size; |
141 | } | |
142 | ||
143 | return size; | |
144 | } | |
145 | ||
37811fcc CW |
146 | static void |
147 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
148 | { | |
b4716185 | 149 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 150 | struct intel_engine_cs *engine; |
1d693bcc | 151 | struct i915_vma *vma; |
faf5bf0a | 152 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
153 | int pin_count = 0; |
154 | ||
188c1ab7 CW |
155 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
156 | ||
d07f0e59 | 157 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 158 | &obj->base, |
be12a86b | 159 | get_active_flag(obj), |
37811fcc CW |
160 | get_pin_flag(obj), |
161 | get_tiling_flag(obj), | |
1d693bcc | 162 | get_global_flag(obj), |
be12a86b | 163 | get_pin_mapped_flag(obj), |
a05a5862 | 164 | obj->base.size / 1024, |
37811fcc | 165 | obj->base.read_domains, |
d07f0e59 | 166 | obj->base.write_domain, |
36cdd013 | 167 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
168 | obj->mm.dirty ? " dirty" : "", |
169 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
170 | if (obj->base.name) |
171 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 172 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 173 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 174 | pin_count++; |
ba0635ff DC |
175 | } |
176 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
177 | if (obj->pin_display) |
178 | seq_printf(m, " (display)"); | |
1c7f4bca | 179 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
180 | if (!drm_mm_node_allocated(&vma->node)) |
181 | continue; | |
182 | ||
8d2fdc3f | 183 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 184 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 185 | vma->node.start, vma->node.size); |
21976853 CW |
186 | if (i915_vma_is_ggtt(vma)) { |
187 | switch (vma->ggtt_view.type) { | |
188 | case I915_GGTT_VIEW_NORMAL: | |
189 | seq_puts(m, ", normal"); | |
190 | break; | |
191 | ||
192 | case I915_GGTT_VIEW_PARTIAL: | |
193 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
194 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
195 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
196 | break; |
197 | ||
198 | case I915_GGTT_VIEW_ROTATED: | |
199 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
200 | vma->ggtt_view.rotated.plane[0].width, |
201 | vma->ggtt_view.rotated.plane[0].height, | |
202 | vma->ggtt_view.rotated.plane[0].stride, | |
203 | vma->ggtt_view.rotated.plane[0].offset, | |
204 | vma->ggtt_view.rotated.plane[1].width, | |
205 | vma->ggtt_view.rotated.plane[1].height, | |
206 | vma->ggtt_view.rotated.plane[1].stride, | |
207 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
208 | break; |
209 | ||
210 | default: | |
211 | MISSING_CASE(vma->ggtt_view.type); | |
212 | break; | |
213 | } | |
214 | } | |
49ef5294 CW |
215 | if (vma->fence) |
216 | seq_printf(m, " , fence: %d%s", | |
217 | vma->fence->id, | |
218 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 219 | seq_puts(m, ")"); |
1d693bcc | 220 | } |
c1ad11fc | 221 | if (obj->stolen) |
440fd528 | 222 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 223 | |
d07f0e59 | 224 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
225 | if (engine) |
226 | seq_printf(m, " (%s)", engine->name); | |
227 | ||
faf5bf0a CW |
228 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
229 | if (frontbuffer_bits) | |
230 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
231 | } |
232 | ||
6d2b8885 CW |
233 | static int obj_rank_by_stolen(void *priv, |
234 | struct list_head *A, struct list_head *B) | |
235 | { | |
236 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 237 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 238 | struct drm_i915_gem_object *b = |
b25cb2f8 | 239 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 240 | |
2d05fa16 RV |
241 | if (a->stolen->start < b->stolen->start) |
242 | return -1; | |
243 | if (a->stolen->start > b->stolen->start) | |
244 | return 1; | |
245 | return 0; | |
6d2b8885 CW |
246 | } |
247 | ||
248 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
249 | { | |
36cdd013 DW |
250 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
251 | struct drm_device *dev = &dev_priv->drm; | |
6d2b8885 | 252 | struct drm_i915_gem_object *obj; |
c44ef60e | 253 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
254 | LIST_HEAD(stolen); |
255 | int count, ret; | |
256 | ||
257 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
258 | if (ret) | |
259 | return ret; | |
260 | ||
261 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 262 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6d2b8885 CW |
263 | if (obj->stolen == NULL) |
264 | continue; | |
265 | ||
b25cb2f8 | 266 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
267 | |
268 | total_obj_size += obj->base.size; | |
ca1543be | 269 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
270 | count++; |
271 | } | |
56cea323 | 272 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
6d2b8885 CW |
273 | if (obj->stolen == NULL) |
274 | continue; | |
275 | ||
b25cb2f8 | 276 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
277 | |
278 | total_obj_size += obj->base.size; | |
279 | count++; | |
280 | } | |
281 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
282 | seq_puts(m, "Stolen:\n"); | |
283 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 284 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
285 | seq_puts(m, " "); |
286 | describe_obj(m, obj); | |
287 | seq_putc(m, '\n'); | |
b25cb2f8 | 288 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
289 | } |
290 | mutex_unlock(&dev->struct_mutex); | |
291 | ||
c44ef60e | 292 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
293 | count, total_obj_size, total_gtt_size); |
294 | return 0; | |
295 | } | |
296 | ||
2db8e9d6 | 297 | struct file_stats { |
6313c204 | 298 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
299 | unsigned long count; |
300 | u64 total, unbound; | |
301 | u64 global, shared; | |
302 | u64 active, inactive; | |
2db8e9d6 CW |
303 | }; |
304 | ||
305 | static int per_file_stats(int id, void *ptr, void *data) | |
306 | { | |
307 | struct drm_i915_gem_object *obj = ptr; | |
308 | struct file_stats *stats = data; | |
6313c204 | 309 | struct i915_vma *vma; |
2db8e9d6 CW |
310 | |
311 | stats->count++; | |
312 | stats->total += obj->base.size; | |
15717de2 CW |
313 | if (!obj->bind_count) |
314 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
315 | if (obj->base.name || obj->base.dma_buf) |
316 | stats->shared += obj->base.size; | |
317 | ||
894eeecc CW |
318 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
319 | if (!drm_mm_node_allocated(&vma->node)) | |
320 | continue; | |
6313c204 | 321 | |
3272db53 | 322 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
323 | stats->global += vma->node.size; |
324 | } else { | |
325 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 326 | |
2bfa996e | 327 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 328 | continue; |
6313c204 | 329 | } |
894eeecc | 330 | |
b0decaf7 | 331 | if (i915_vma_is_active(vma)) |
894eeecc CW |
332 | stats->active += vma->node.size; |
333 | else | |
334 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
335 | } |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
b0da1b79 CW |
340 | #define print_file_stats(m, name, stats) do { \ |
341 | if (stats.count) \ | |
c44ef60e | 342 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
343 | name, \ |
344 | stats.count, \ | |
345 | stats.total, \ | |
346 | stats.active, \ | |
347 | stats.inactive, \ | |
348 | stats.global, \ | |
349 | stats.shared, \ | |
350 | stats.unbound); \ | |
351 | } while (0) | |
493018dc BV |
352 | |
353 | static void print_batch_pool_stats(struct seq_file *m, | |
354 | struct drm_i915_private *dev_priv) | |
355 | { | |
356 | struct drm_i915_gem_object *obj; | |
357 | struct file_stats stats; | |
e2f80391 | 358 | struct intel_engine_cs *engine; |
3b3f1650 | 359 | enum intel_engine_id id; |
b4ac5afc | 360 | int j; |
493018dc BV |
361 | |
362 | memset(&stats, 0, sizeof(stats)); | |
363 | ||
3b3f1650 | 364 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 365 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 366 | list_for_each_entry(obj, |
e2f80391 | 367 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
368 | batch_pool_link) |
369 | per_file_stats(0, obj, &stats); | |
370 | } | |
06fbca71 | 371 | } |
493018dc | 372 | |
b0da1b79 | 373 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
374 | } |
375 | ||
15da9565 CW |
376 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
377 | { | |
378 | struct i915_gem_context *ctx = ptr; | |
379 | int n; | |
380 | ||
381 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
382 | if (ctx->engine[n].state) | |
bf3783e5 | 383 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 384 | if (ctx->engine[n].ring) |
57e88531 | 385 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
386 | } |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | static void print_context_stats(struct seq_file *m, | |
392 | struct drm_i915_private *dev_priv) | |
393 | { | |
36cdd013 | 394 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
395 | struct file_stats stats; |
396 | struct drm_file *file; | |
397 | ||
398 | memset(&stats, 0, sizeof(stats)); | |
399 | ||
36cdd013 | 400 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
401 | if (dev_priv->kernel_context) |
402 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
403 | ||
36cdd013 | 404 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
405 | struct drm_i915_file_private *fpriv = file->driver_priv; |
406 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
407 | } | |
36cdd013 | 408 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
409 | |
410 | print_file_stats(m, "[k]contexts", stats); | |
411 | } | |
412 | ||
36cdd013 | 413 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 414 | { |
36cdd013 DW |
415 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
416 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 417 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
418 | u32 count, mapped_count, purgeable_count, dpy_count; |
419 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 420 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 421 | struct drm_file *file; |
73aa808f CW |
422 | int ret; |
423 | ||
424 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
425 | if (ret) | |
426 | return ret; | |
427 | ||
3ef7f228 | 428 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
429 | dev_priv->mm.object_count, |
430 | dev_priv->mm.object_memory); | |
431 | ||
1544c42e CW |
432 | size = count = 0; |
433 | mapped_size = mapped_count = 0; | |
434 | purgeable_size = purgeable_count = 0; | |
56cea323 | 435 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
436 | size += obj->base.size; |
437 | ++count; | |
438 | ||
a4f5ea64 | 439 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
440 | purgeable_size += obj->base.size; |
441 | ++purgeable_count; | |
442 | } | |
443 | ||
a4f5ea64 | 444 | if (obj->mm.mapping) { |
2bd160a1 CW |
445 | mapped_count++; |
446 | mapped_size += obj->base.size; | |
be19b10d | 447 | } |
b7abb714 | 448 | } |
c44ef60e | 449 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 450 | |
2bd160a1 | 451 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 452 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
453 | size += obj->base.size; |
454 | ++count; | |
455 | ||
30154650 | 456 | if (obj->pin_display) { |
2bd160a1 CW |
457 | dpy_size += obj->base.size; |
458 | ++dpy_count; | |
6299f992 | 459 | } |
2bd160a1 | 460 | |
a4f5ea64 | 461 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
462 | purgeable_size += obj->base.size; |
463 | ++purgeable_count; | |
464 | } | |
2bd160a1 | 465 | |
a4f5ea64 | 466 | if (obj->mm.mapping) { |
2bd160a1 CW |
467 | mapped_count++; |
468 | mapped_size += obj->base.size; | |
be19b10d | 469 | } |
6299f992 | 470 | } |
2bd160a1 CW |
471 | seq_printf(m, "%u bound objects, %llu bytes\n", |
472 | count, size); | |
c44ef60e | 473 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 474 | purgeable_count, purgeable_size); |
2bd160a1 CW |
475 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
476 | mapped_count, mapped_size); | |
477 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
478 | dpy_count, dpy_size); | |
6299f992 | 479 | |
c44ef60e | 480 | seq_printf(m, "%llu [%llu] gtt total\n", |
381b943b | 481 | ggtt->base.total, ggtt->mappable_end); |
73aa808f | 482 | |
493018dc BV |
483 | seq_putc(m, '\n'); |
484 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
485 | mutex_unlock(&dev->struct_mutex); |
486 | ||
487 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 488 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
489 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
490 | struct file_stats stats; | |
c84455b4 CW |
491 | struct drm_i915_file_private *file_priv = file->driver_priv; |
492 | struct drm_i915_gem_request *request; | |
3ec2f427 | 493 | struct task_struct *task; |
2db8e9d6 CW |
494 | |
495 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 496 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 497 | spin_lock(&file->table_lock); |
2db8e9d6 | 498 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 499 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
500 | /* |
501 | * Although we have a valid reference on file->pid, that does | |
502 | * not guarantee that the task_struct who called get_pid() is | |
503 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
504 | * Therefore, we need to protect this ->comm access using RCU. | |
505 | */ | |
c84455b4 CW |
506 | mutex_lock(&dev->struct_mutex); |
507 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
508 | struct drm_i915_gem_request, | |
c8659efa | 509 | client_link); |
3ec2f427 | 510 | rcu_read_lock(); |
c84455b4 CW |
511 | task = pid_task(request && request->ctx->pid ? |
512 | request->ctx->pid : file->pid, | |
513 | PIDTYPE_PID); | |
493018dc | 514 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 515 | rcu_read_unlock(); |
c84455b4 | 516 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 517 | } |
1d2ac403 | 518 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
519 | |
520 | return 0; | |
521 | } | |
522 | ||
aee56cff | 523 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 524 | { |
9f25d007 | 525 | struct drm_info_node *node = m->private; |
36cdd013 DW |
526 | struct drm_i915_private *dev_priv = node_to_i915(node); |
527 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 528 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 529 | struct drm_i915_gem_object *obj; |
c44ef60e | 530 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
531 | int count, ret; |
532 | ||
533 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
534 | if (ret) | |
535 | return ret; | |
536 | ||
537 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 538 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 539 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
540 | continue; |
541 | ||
267f0c90 | 542 | seq_puts(m, " "); |
08c18323 | 543 | describe_obj(m, obj); |
267f0c90 | 544 | seq_putc(m, '\n'); |
08c18323 | 545 | total_obj_size += obj->base.size; |
ca1543be | 546 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
547 | count++; |
548 | } | |
549 | ||
550 | mutex_unlock(&dev->struct_mutex); | |
551 | ||
c44ef60e | 552 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
553 | count, total_obj_size, total_gtt_size); |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
4e5359cd SF |
558 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
559 | { | |
36cdd013 DW |
560 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
561 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 562 | struct intel_crtc *crtc; |
8a270ebf DV |
563 | int ret; |
564 | ||
565 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
566 | if (ret) | |
567 | return ret; | |
4e5359cd | 568 | |
d3fcc808 | 569 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
570 | const char pipe = pipe_name(crtc->pipe); |
571 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 572 | struct intel_flip_work *work; |
4e5359cd | 573 | |
5e2d7afc | 574 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
575 | work = crtc->flip_work; |
576 | if (work == NULL) { | |
9db4a9c7 | 577 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
578 | pipe, plane); |
579 | } else { | |
5a21b665 DV |
580 | u32 pending; |
581 | u32 addr; | |
582 | ||
583 | pending = atomic_read(&work->pending); | |
584 | if (pending) { | |
585 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
586 | pipe, plane); | |
587 | } else { | |
588 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
589 | pipe, plane); | |
590 | } | |
591 | if (work->flip_queued_req) { | |
24327f83 | 592 | struct intel_engine_cs *engine = work->flip_queued_req->engine; |
5a21b665 | 593 | |
312c3c47 | 594 | seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", |
5a21b665 | 595 | engine->name, |
24327f83 | 596 | work->flip_queued_req->global_seqno, |
312c3c47 | 597 | intel_engine_last_submit(engine), |
1b7744e7 | 598 | intel_engine_get_seqno(engine), |
f69a02c9 | 599 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
600 | } else |
601 | seq_printf(m, "Flip not associated with any ring\n"); | |
602 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
603 | work->flip_queued_vblank, | |
604 | work->flip_ready_vblank, | |
605 | intel_crtc_get_vblank_counter(crtc)); | |
606 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
607 | ||
36cdd013 | 608 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
609 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
610 | else | |
611 | addr = I915_READ(DSPADDR(crtc->plane)); | |
612 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
613 | ||
614 | if (work->pending_flip_obj) { | |
615 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
616 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
617 | } |
618 | } | |
5e2d7afc | 619 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
620 | } |
621 | ||
8a270ebf DV |
622 | mutex_unlock(&dev->struct_mutex); |
623 | ||
4e5359cd SF |
624 | return 0; |
625 | } | |
626 | ||
493018dc BV |
627 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
628 | { | |
36cdd013 DW |
629 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
630 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 631 | struct drm_i915_gem_object *obj; |
e2f80391 | 632 | struct intel_engine_cs *engine; |
3b3f1650 | 633 | enum intel_engine_id id; |
8d9d5744 | 634 | int total = 0; |
b4ac5afc | 635 | int ret, j; |
493018dc BV |
636 | |
637 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
638 | if (ret) | |
639 | return ret; | |
640 | ||
3b3f1650 | 641 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 642 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
643 | int count; |
644 | ||
645 | count = 0; | |
646 | list_for_each_entry(obj, | |
e2f80391 | 647 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
648 | batch_pool_link) |
649 | count++; | |
650 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 651 | engine->name, j, count); |
8d9d5744 CW |
652 | |
653 | list_for_each_entry(obj, | |
e2f80391 | 654 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
655 | batch_pool_link) { |
656 | seq_puts(m, " "); | |
657 | describe_obj(m, obj); | |
658 | seq_putc(m, '\n'); | |
659 | } | |
660 | ||
661 | total += count; | |
06fbca71 | 662 | } |
493018dc BV |
663 | } |
664 | ||
8d9d5744 | 665 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
666 | |
667 | mutex_unlock(&dev->struct_mutex); | |
668 | ||
669 | return 0; | |
670 | } | |
671 | ||
1b36595f CW |
672 | static void print_request(struct seq_file *m, |
673 | struct drm_i915_gem_request *rq, | |
674 | const char *prefix) | |
675 | { | |
20311bd3 | 676 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 677 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 678 | rq->priotree.priority, |
1b36595f | 679 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 680 | rq->timeline->common->name); |
1b36595f CW |
681 | } |
682 | ||
2017263e BG |
683 | static int i915_gem_request_info(struct seq_file *m, void *data) |
684 | { | |
36cdd013 DW |
685 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
686 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 687 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
688 | struct intel_engine_cs *engine; |
689 | enum intel_engine_id id; | |
b4ac5afc | 690 | int ret, any; |
de227ef0 CW |
691 | |
692 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
693 | if (ret) | |
694 | return ret; | |
2017263e | 695 | |
2d1070b2 | 696 | any = 0; |
3b3f1650 | 697 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
698 | int count; |
699 | ||
700 | count = 0; | |
73cb9701 | 701 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
702 | count++; |
703 | if (count == 0) | |
a2c7f6fd CW |
704 | continue; |
705 | ||
e2f80391 | 706 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 707 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 708 | print_request(m, req, " "); |
2d1070b2 CW |
709 | |
710 | any++; | |
2017263e | 711 | } |
de227ef0 CW |
712 | mutex_unlock(&dev->struct_mutex); |
713 | ||
2d1070b2 | 714 | if (any == 0) |
267f0c90 | 715 | seq_puts(m, "No requests\n"); |
c2c347a9 | 716 | |
2017263e BG |
717 | return 0; |
718 | } | |
719 | ||
b2223497 | 720 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 721 | struct intel_engine_cs *engine) |
b2223497 | 722 | { |
688e6c72 CW |
723 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
724 | struct rb_node *rb; | |
725 | ||
12471ba8 | 726 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 727 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 728 | |
f6168e33 | 729 | spin_lock_irq(&b->lock); |
688e6c72 | 730 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 731 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
688e6c72 CW |
732 | |
733 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
734 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
735 | } | |
f6168e33 | 736 | spin_unlock_irq(&b->lock); |
b2223497 CW |
737 | } |
738 | ||
2017263e BG |
739 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
740 | { | |
36cdd013 | 741 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 742 | struct intel_engine_cs *engine; |
3b3f1650 | 743 | enum intel_engine_id id; |
2017263e | 744 | |
3b3f1650 | 745 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 746 | i915_ring_seqno_info(m, engine); |
de227ef0 | 747 | |
2017263e BG |
748 | return 0; |
749 | } | |
750 | ||
751 | ||
752 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
753 | { | |
36cdd013 | 754 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 755 | struct intel_engine_cs *engine; |
3b3f1650 | 756 | enum intel_engine_id id; |
4bb05040 | 757 | int i, pipe; |
de227ef0 | 758 | |
c8c8fb33 | 759 | intel_runtime_pm_get(dev_priv); |
2017263e | 760 | |
36cdd013 | 761 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
762 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
763 | I915_READ(GEN8_MASTER_IRQ)); | |
764 | ||
765 | seq_printf(m, "Display IER:\t%08x\n", | |
766 | I915_READ(VLV_IER)); | |
767 | seq_printf(m, "Display IIR:\t%08x\n", | |
768 | I915_READ(VLV_IIR)); | |
769 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
770 | I915_READ(VLV_IIR_RW)); | |
771 | seq_printf(m, "Display IMR:\t%08x\n", | |
772 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
773 | for_each_pipe(dev_priv, pipe) { |
774 | enum intel_display_power_domain power_domain; | |
775 | ||
776 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
777 | if (!intel_display_power_get_if_enabled(dev_priv, | |
778 | power_domain)) { | |
779 | seq_printf(m, "Pipe %c power disabled\n", | |
780 | pipe_name(pipe)); | |
781 | continue; | |
782 | } | |
783 | ||
74e1ca8c VS |
784 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
785 | pipe_name(pipe), | |
786 | I915_READ(PIPESTAT(pipe))); | |
787 | ||
9c870d03 CW |
788 | intel_display_power_put(dev_priv, power_domain); |
789 | } | |
790 | ||
791 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
792 | seq_printf(m, "Port hotplug:\t%08x\n", |
793 | I915_READ(PORT_HOTPLUG_EN)); | |
794 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
795 | I915_READ(VLV_DPFLIPSTAT)); | |
796 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
797 | I915_READ(DPINVGTT)); | |
9c870d03 | 798 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
799 | |
800 | for (i = 0; i < 4; i++) { | |
801 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
802 | i, I915_READ(GEN8_GT_IMR(i))); | |
803 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
804 | i, I915_READ(GEN8_GT_IIR(i))); | |
805 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
806 | i, I915_READ(GEN8_GT_IER(i))); | |
807 | } | |
808 | ||
809 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
810 | I915_READ(GEN8_PCU_IMR)); | |
811 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
812 | I915_READ(GEN8_PCU_IIR)); | |
813 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
814 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 815 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
816 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
817 | I915_READ(GEN8_MASTER_IRQ)); | |
818 | ||
819 | for (i = 0; i < 4; i++) { | |
820 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
821 | i, I915_READ(GEN8_GT_IMR(i))); | |
822 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
823 | i, I915_READ(GEN8_GT_IIR(i))); | |
824 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
825 | i, I915_READ(GEN8_GT_IER(i))); | |
826 | } | |
827 | ||
055e393f | 828 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
829 | enum intel_display_power_domain power_domain; |
830 | ||
831 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
832 | if (!intel_display_power_get_if_enabled(dev_priv, | |
833 | power_domain)) { | |
22c59960 PZ |
834 | seq_printf(m, "Pipe %c power disabled\n", |
835 | pipe_name(pipe)); | |
836 | continue; | |
837 | } | |
a123f157 | 838 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
839 | pipe_name(pipe), |
840 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 841 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
842 | pipe_name(pipe), |
843 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 844 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
845 | pipe_name(pipe), |
846 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
847 | |
848 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
849 | } |
850 | ||
851 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
852 | I915_READ(GEN8_DE_PORT_IMR)); | |
853 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
854 | I915_READ(GEN8_DE_PORT_IIR)); | |
855 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
856 | I915_READ(GEN8_DE_PORT_IER)); | |
857 | ||
858 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
859 | I915_READ(GEN8_DE_MISC_IMR)); | |
860 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
861 | I915_READ(GEN8_DE_MISC_IIR)); | |
862 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
863 | I915_READ(GEN8_DE_MISC_IER)); | |
864 | ||
865 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
866 | I915_READ(GEN8_PCU_IMR)); | |
867 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
868 | I915_READ(GEN8_PCU_IIR)); | |
869 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
870 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 871 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
872 | seq_printf(m, "Display IER:\t%08x\n", |
873 | I915_READ(VLV_IER)); | |
874 | seq_printf(m, "Display IIR:\t%08x\n", | |
875 | I915_READ(VLV_IIR)); | |
876 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
877 | I915_READ(VLV_IIR_RW)); | |
878 | seq_printf(m, "Display IMR:\t%08x\n", | |
879 | I915_READ(VLV_IMR)); | |
4f4631af CW |
880 | for_each_pipe(dev_priv, pipe) { |
881 | enum intel_display_power_domain power_domain; | |
882 | ||
883 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
884 | if (!intel_display_power_get_if_enabled(dev_priv, | |
885 | power_domain)) { | |
886 | seq_printf(m, "Pipe %c power disabled\n", | |
887 | pipe_name(pipe)); | |
888 | continue; | |
889 | } | |
890 | ||
7e231dbe JB |
891 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
892 | pipe_name(pipe), | |
893 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
894 | intel_display_power_put(dev_priv, power_domain); |
895 | } | |
7e231dbe JB |
896 | |
897 | seq_printf(m, "Master IER:\t%08x\n", | |
898 | I915_READ(VLV_MASTER_IER)); | |
899 | ||
900 | seq_printf(m, "Render IER:\t%08x\n", | |
901 | I915_READ(GTIER)); | |
902 | seq_printf(m, "Render IIR:\t%08x\n", | |
903 | I915_READ(GTIIR)); | |
904 | seq_printf(m, "Render IMR:\t%08x\n", | |
905 | I915_READ(GTIMR)); | |
906 | ||
907 | seq_printf(m, "PM IER:\t\t%08x\n", | |
908 | I915_READ(GEN6_PMIER)); | |
909 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
910 | I915_READ(GEN6_PMIIR)); | |
911 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
912 | I915_READ(GEN6_PMIMR)); | |
913 | ||
914 | seq_printf(m, "Port hotplug:\t%08x\n", | |
915 | I915_READ(PORT_HOTPLUG_EN)); | |
916 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
917 | I915_READ(VLV_DPFLIPSTAT)); | |
918 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
919 | I915_READ(DPINVGTT)); | |
920 | ||
36cdd013 | 921 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
922 | seq_printf(m, "Interrupt enable: %08x\n", |
923 | I915_READ(IER)); | |
924 | seq_printf(m, "Interrupt identity: %08x\n", | |
925 | I915_READ(IIR)); | |
926 | seq_printf(m, "Interrupt mask: %08x\n", | |
927 | I915_READ(IMR)); | |
055e393f | 928 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
929 | seq_printf(m, "Pipe %c stat: %08x\n", |
930 | pipe_name(pipe), | |
931 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
932 | } else { |
933 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
934 | I915_READ(DEIER)); | |
935 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
936 | I915_READ(DEIIR)); | |
937 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
938 | I915_READ(DEIMR)); | |
939 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
940 | I915_READ(SDEIER)); | |
941 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
942 | I915_READ(SDEIIR)); | |
943 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
944 | I915_READ(SDEIMR)); | |
945 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
946 | I915_READ(GTIER)); | |
947 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
948 | I915_READ(GTIIR)); | |
949 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
950 | I915_READ(GTIMR)); | |
951 | } | |
3b3f1650 | 952 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 953 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
954 | seq_printf(m, |
955 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 956 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 957 | } |
e2f80391 | 958 | i915_ring_seqno_info(m, engine); |
9862e600 | 959 | } |
c8c8fb33 | 960 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 961 | |
2017263e BG |
962 | return 0; |
963 | } | |
964 | ||
a6172a80 CW |
965 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
966 | { | |
36cdd013 DW |
967 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
968 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
969 | int i, ret; |
970 | ||
971 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
972 | if (ret) | |
973 | return ret; | |
a6172a80 | 974 | |
a6172a80 CW |
975 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
976 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 977 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 978 | |
6c085a72 CW |
979 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
980 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 981 | if (!vma) |
267f0c90 | 982 | seq_puts(m, "unused"); |
c2c347a9 | 983 | else |
49ef5294 | 984 | describe_obj(m, vma->obj); |
267f0c90 | 985 | seq_putc(m, '\n'); |
a6172a80 CW |
986 | } |
987 | ||
05394f39 | 988 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
989 | return 0; |
990 | } | |
991 | ||
98a2f411 | 992 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
993 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
994 | size_t count, loff_t *pos) | |
d5442303 | 995 | { |
5a4c6f1b CW |
996 | struct i915_gpu_state *error = file->private_data; |
997 | struct drm_i915_error_state_buf str; | |
998 | ssize_t ret; | |
999 | loff_t tmp; | |
d5442303 | 1000 | |
5a4c6f1b CW |
1001 | if (!error) |
1002 | return 0; | |
d5442303 | 1003 | |
5a4c6f1b CW |
1004 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
1005 | if (ret) | |
1006 | return ret; | |
d5442303 | 1007 | |
5a4c6f1b CW |
1008 | ret = i915_error_state_to_str(&str, error); |
1009 | if (ret) | |
1010 | goto out; | |
d5442303 | 1011 | |
5a4c6f1b CW |
1012 | tmp = 0; |
1013 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
1014 | if (ret < 0) | |
1015 | goto out; | |
d5442303 | 1016 | |
5a4c6f1b CW |
1017 | *pos = str.start + ret; |
1018 | out: | |
1019 | i915_error_state_buf_release(&str); | |
1020 | return ret; | |
1021 | } | |
edc3d884 | 1022 | |
5a4c6f1b CW |
1023 | static int gpu_state_release(struct inode *inode, struct file *file) |
1024 | { | |
1025 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 1026 | return 0; |
d5442303 DV |
1027 | } |
1028 | ||
5a4c6f1b | 1029 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 1030 | { |
5a4c6f1b | 1031 | struct i915_gpu_state *gpu; |
d5442303 | 1032 | |
5a4c6f1b CW |
1033 | gpu = i915_capture_gpu_state(inode->i_private); |
1034 | if (!gpu) | |
1035 | return -ENOMEM; | |
d5442303 | 1036 | |
5a4c6f1b | 1037 | file->private_data = gpu; |
edc3d884 MK |
1038 | return 0; |
1039 | } | |
1040 | ||
5a4c6f1b CW |
1041 | static const struct file_operations i915_gpu_info_fops = { |
1042 | .owner = THIS_MODULE, | |
1043 | .open = i915_gpu_info_open, | |
1044 | .read = gpu_state_read, | |
1045 | .llseek = default_llseek, | |
1046 | .release = gpu_state_release, | |
1047 | }; | |
1048 | ||
1049 | static ssize_t | |
1050 | i915_error_state_write(struct file *filp, | |
1051 | const char __user *ubuf, | |
1052 | size_t cnt, | |
1053 | loff_t *ppos) | |
4dc955f7 | 1054 | { |
5a4c6f1b | 1055 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 1056 | |
5a4c6f1b CW |
1057 | if (!error) |
1058 | return 0; | |
edc3d884 | 1059 | |
5a4c6f1b CW |
1060 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
1061 | i915_reset_error_state(error->i915); | |
edc3d884 | 1062 | |
5a4c6f1b CW |
1063 | return cnt; |
1064 | } | |
edc3d884 | 1065 | |
5a4c6f1b CW |
1066 | static int i915_error_state_open(struct inode *inode, struct file *file) |
1067 | { | |
1068 | file->private_data = i915_first_error_state(inode->i_private); | |
1069 | return 0; | |
d5442303 DV |
1070 | } |
1071 | ||
1072 | static const struct file_operations i915_error_state_fops = { | |
1073 | .owner = THIS_MODULE, | |
1074 | .open = i915_error_state_open, | |
5a4c6f1b | 1075 | .read = gpu_state_read, |
d5442303 DV |
1076 | .write = i915_error_state_write, |
1077 | .llseek = default_llseek, | |
5a4c6f1b | 1078 | .release = gpu_state_release, |
d5442303 | 1079 | }; |
98a2f411 CW |
1080 | #endif |
1081 | ||
647416f9 KC |
1082 | static int |
1083 | i915_next_seqno_set(void *data, u64 val) | |
1084 | { | |
36cdd013 DW |
1085 | struct drm_i915_private *dev_priv = data; |
1086 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1087 | int ret; |
1088 | ||
40633219 MK |
1089 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1090 | if (ret) | |
1091 | return ret; | |
1092 | ||
73cb9701 | 1093 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1094 | mutex_unlock(&dev->struct_mutex); |
1095 | ||
647416f9 | 1096 | return ret; |
40633219 MK |
1097 | } |
1098 | ||
647416f9 | 1099 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
9b6586ae | 1100 | NULL, i915_next_seqno_set, |
3a3b4f98 | 1101 | "0x%llx\n"); |
40633219 | 1102 | |
adb4bd12 | 1103 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1104 | { |
36cdd013 | 1105 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
c8c8fb33 PZ |
1106 | int ret = 0; |
1107 | ||
1108 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1109 | |
36cdd013 | 1110 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1111 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1112 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1113 | ||
1114 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1115 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1116 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1117 | MEMSTAT_VID_SHIFT); | |
1118 | seq_printf(m, "Current P-state: %d\n", | |
1119 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1120 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1121 | u32 freq_sts; |
1122 | ||
1123 | mutex_lock(&dev_priv->rps.hw_lock); | |
1124 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1125 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1126 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1127 | ||
1128 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1129 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1130 | ||
1131 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1132 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1133 | ||
1134 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1135 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1136 | ||
1137 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1138 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1139 | ||
1140 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1141 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1142 | ||
1143 | seq_printf(m, | |
1144 | "efficient (RPe) frequency: %d MHz\n", | |
1145 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1146 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1147 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1148 | u32 rp_state_limits; |
1149 | u32 gt_perf_status; | |
1150 | u32 rp_state_cap; | |
0d8f9491 | 1151 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1152 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1153 | u32 rpupei, rpcurup, rpprevup; |
1154 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1155 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1156 | int max_freq; |
1157 | ||
35040562 | 1158 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1159 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1160 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1161 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1162 | } else { | |
1163 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1164 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1165 | } | |
1166 | ||
3b8d8d91 | 1167 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1168 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1169 | |
8e8c06cd | 1170 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1171 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1172 | reqf >>= 23; |
1173 | else { | |
1174 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1175 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1176 | reqf >>= 24; |
1177 | else | |
1178 | reqf >>= 25; | |
1179 | } | |
7c59a9c1 | 1180 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1181 | |
0d8f9491 CW |
1182 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1183 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1184 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1185 | ||
ccab5c82 | 1186 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1187 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1188 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1189 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1190 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1191 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1192 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1193 | if (IS_GEN9(dev_priv)) |
60260a5b | 1194 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1195 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1196 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1197 | else | |
1198 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1199 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1200 | |
59bad947 | 1201 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1202 | |
36cdd013 | 1203 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1204 | pm_ier = I915_READ(GEN6_PMIER); |
1205 | pm_imr = I915_READ(GEN6_PMIMR); | |
1206 | pm_isr = I915_READ(GEN6_PMISR); | |
1207 | pm_iir = I915_READ(GEN6_PMIIR); | |
1208 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1209 | } else { | |
1210 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1211 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1212 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1213 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1214 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1215 | } | |
0d8f9491 | 1216 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1217 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1218 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1219 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1220 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1221 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1222 | seq_printf(m, "Render p-state VID: %d\n", |
1223 | gt_perf_status & 0xff); | |
1224 | seq_printf(m, "Render p-state limit: %d\n", | |
1225 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1226 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1227 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1228 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1229 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1230 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1231 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1232 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1233 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1234 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1235 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1236 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1237 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1238 | seq_printf(m, "Up threshold: %d%%\n", |
1239 | dev_priv->rps.up_threshold); | |
1240 | ||
d6cda9c7 AG |
1241 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1242 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1243 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1244 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1245 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1246 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1247 | seq_printf(m, "Down threshold: %d%%\n", |
1248 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1249 | |
cc3f90f0 | 1250 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1251 | rp_state_cap >> 16) & 0xff; |
b976dc53 | 1252 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1253 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1254 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1255 | |
1256 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
b976dc53 | 1257 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1258 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1259 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1260 | |
cc3f90f0 | 1261 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1262 | rp_state_cap >> 0) & 0xff; |
b976dc53 | 1263 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1264 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1265 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1266 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1267 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1268 | |
d86ed34a CW |
1269 | seq_printf(m, "Current freq: %d MHz\n", |
1270 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1271 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1272 | seq_printf(m, "Idle freq: %d MHz\n", |
1273 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1274 | seq_printf(m, "Min freq: %d MHz\n", |
1275 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1276 | seq_printf(m, "Boost freq: %d MHz\n", |
1277 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1278 | seq_printf(m, "Max freq: %d MHz\n", |
1279 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1280 | seq_printf(m, | |
1281 | "efficient (RPe) frequency: %d MHz\n", | |
1282 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1283 | } else { |
267f0c90 | 1284 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1285 | } |
f97108d1 | 1286 | |
49cd97a3 | 1287 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1288 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1289 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1290 | ||
c8c8fb33 PZ |
1291 | intel_runtime_pm_put(dev_priv); |
1292 | return ret; | |
f97108d1 JB |
1293 | } |
1294 | ||
d636951e BW |
1295 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1296 | struct seq_file *m, | |
1297 | struct intel_instdone *instdone) | |
1298 | { | |
f9e61372 BW |
1299 | int slice; |
1300 | int subslice; | |
1301 | ||
d636951e BW |
1302 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1303 | instdone->instdone); | |
1304 | ||
1305 | if (INTEL_GEN(dev_priv) <= 3) | |
1306 | return; | |
1307 | ||
1308 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1309 | instdone->slice_common); | |
1310 | ||
1311 | if (INTEL_GEN(dev_priv) <= 6) | |
1312 | return; | |
1313 | ||
f9e61372 BW |
1314 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1315 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1316 | slice, subslice, instdone->sampler[slice][subslice]); | |
1317 | ||
1318 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1319 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1320 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1321 | } |
1322 | ||
f654449a CW |
1323 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1324 | { | |
36cdd013 | 1325 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1326 | struct intel_engine_cs *engine; |
666796da TU |
1327 | u64 acthd[I915_NUM_ENGINES]; |
1328 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1329 | struct intel_instdone instdone; |
c3232b18 | 1330 | enum intel_engine_id id; |
f654449a | 1331 | |
8af29b0c CW |
1332 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
1333 | seq_printf(m, "Wedged\n"); | |
1334 | if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags)) | |
1335 | seq_printf(m, "Reset in progress\n"); | |
1336 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) | |
1337 | seq_printf(m, "Waiter holding struct mutex\n"); | |
1338 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) | |
1339 | seq_printf(m, "struct_mutex blocked for reset\n"); | |
1340 | ||
f654449a CW |
1341 | if (!i915.enable_hangcheck) { |
1342 | seq_printf(m, "Hangcheck disabled\n"); | |
1343 | return 0; | |
1344 | } | |
1345 | ||
ebbc7546 MK |
1346 | intel_runtime_pm_get(dev_priv); |
1347 | ||
3b3f1650 | 1348 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1349 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1350 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1351 | } |
1352 | ||
3b3f1650 | 1353 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1354 | |
ebbc7546 MK |
1355 | intel_runtime_pm_put(dev_priv); |
1356 | ||
f654449a CW |
1357 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1358 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1359 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1360 | jiffies)); | |
1361 | } else | |
1362 | seq_printf(m, "Hangcheck inactive\n"); | |
1363 | ||
f73b5674 CW |
1364 | seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); |
1365 | ||
3b3f1650 | 1366 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1367 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1368 | struct rb_node *rb; | |
1369 | ||
e2f80391 | 1370 | seq_printf(m, "%s:\n", engine->name); |
f73b5674 | 1371 | seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n", |
cb399eab | 1372 | engine->hangcheck.seqno, seqno[id], |
f73b5674 CW |
1373 | intel_engine_last_submit(engine), |
1374 | engine->timeline->inflight_seqnos); | |
3fe3b030 | 1375 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1376 | yesno(intel_engine_has_waiter(engine)), |
1377 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1378 | &dev_priv->gpu_error.missed_irq_rings)), |
1379 | yesno(engine->hangcheck.stalled)); | |
1380 | ||
f6168e33 | 1381 | spin_lock_irq(&b->lock); |
33f53719 | 1382 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1383 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1384 | |
1385 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1386 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1387 | } | |
f6168e33 | 1388 | spin_unlock_irq(&b->lock); |
33f53719 | 1389 | |
f654449a | 1390 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1391 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1392 | (long long)acthd[id]); |
3fe3b030 MK |
1393 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1394 | hangcheck_action_to_str(engine->hangcheck.action), | |
1395 | engine->hangcheck.action, | |
1396 | jiffies_to_msecs(jiffies - | |
1397 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1398 | |
e2f80391 | 1399 | if (engine->id == RCS) { |
d636951e | 1400 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1401 | |
d636951e | 1402 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1403 | |
d636951e | 1404 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1405 | |
d636951e BW |
1406 | i915_instdone_info(dev_priv, m, |
1407 | &engine->hangcheck.instdone); | |
61642ff0 | 1408 | } |
f654449a CW |
1409 | } |
1410 | ||
1411 | return 0; | |
1412 | } | |
1413 | ||
4d85529d | 1414 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1415 | { |
36cdd013 | 1416 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1417 | u32 rgvmodectl, rstdbyctl; |
1418 | u16 crstandvid; | |
616fdb5a | 1419 | |
c8c8fb33 | 1420 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1421 | |
1422 | rgvmodectl = I915_READ(MEMMODECTL); | |
1423 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1424 | crstandvid = I915_READ16(CRSTANDVID); | |
1425 | ||
c8c8fb33 | 1426 | intel_runtime_pm_put(dev_priv); |
f97108d1 | 1427 | |
742f491d | 1428 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1429 | seq_printf(m, "Boost freq: %d\n", |
1430 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1431 | MEMMODE_BOOST_FREQ_SHIFT); | |
1432 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1433 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1434 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1435 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1436 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1437 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1438 | seq_printf(m, "Starting frequency: P%d\n", |
1439 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1440 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1441 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1442 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1443 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1444 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1445 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1446 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1447 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1448 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1449 | case RSX_STATUS_ON: | |
267f0c90 | 1450 | seq_puts(m, "on\n"); |
88271da3 JB |
1451 | break; |
1452 | case RSX_STATUS_RC1: | |
267f0c90 | 1453 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1454 | break; |
1455 | case RSX_STATUS_RC1E: | |
267f0c90 | 1456 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1457 | break; |
1458 | case RSX_STATUS_RS1: | |
267f0c90 | 1459 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1460 | break; |
1461 | case RSX_STATUS_RS2: | |
267f0c90 | 1462 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1463 | break; |
1464 | case RSX_STATUS_RS3: | |
267f0c90 | 1465 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1466 | break; |
1467 | default: | |
267f0c90 | 1468 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1469 | break; |
1470 | } | |
f97108d1 JB |
1471 | |
1472 | return 0; | |
1473 | } | |
1474 | ||
f65367b5 | 1475 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1476 | { |
36cdd013 | 1477 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1478 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1479 | |
1480 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1481 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1482 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1483 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1484 | fw_domain->wake_count); |
1485 | } | |
1486 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1487 | |
b2cff0db CW |
1488 | return 0; |
1489 | } | |
1490 | ||
1491 | static int vlv_drpc_info(struct seq_file *m) | |
1492 | { | |
36cdd013 | 1493 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1494 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1495 | |
d46c0517 ID |
1496 | intel_runtime_pm_get(dev_priv); |
1497 | ||
6b312cd3 | 1498 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1499 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1500 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1501 | ||
d46c0517 ID |
1502 | intel_runtime_pm_put(dev_priv); |
1503 | ||
669ab5aa D |
1504 | seq_printf(m, "Video Turbo Mode: %s\n", |
1505 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1506 | seq_printf(m, "Turbo enabled: %s\n", | |
1507 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1508 | seq_printf(m, "HW control enabled: %s\n", | |
1509 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1510 | seq_printf(m, "SW control enabled: %s\n", | |
1511 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1512 | GEN6_RP_MEDIA_SW_MODE)); | |
1513 | seq_printf(m, "RC6 Enabled: %s\n", | |
1514 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1515 | GEN6_RC_CTL_EI_MODE(1)))); | |
1516 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1517 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1518 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1519 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1520 | |
9cc19be5 ID |
1521 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1522 | I915_READ(VLV_GT_RENDER_RC6)); | |
1523 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1524 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1525 | ||
f65367b5 | 1526 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1527 | } |
1528 | ||
4d85529d BW |
1529 | static int gen6_drpc_info(struct seq_file *m) |
1530 | { | |
36cdd013 DW |
1531 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1532 | struct drm_device *dev = &dev_priv->drm; | |
ecd8faea | 1533 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1534 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1535 | unsigned forcewake_count; |
aee56cff | 1536 | int count = 0, ret; |
4d85529d BW |
1537 | |
1538 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1539 | if (ret) | |
1540 | return ret; | |
c8c8fb33 | 1541 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1542 | |
907b28c5 | 1543 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1544 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1545 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1546 | |
1547 | if (forcewake_count) { | |
267f0c90 DL |
1548 | seq_puts(m, "RC information inaccurate because somebody " |
1549 | "holds a forcewake reference \n"); | |
4d85529d BW |
1550 | } else { |
1551 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1552 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1553 | udelay(10); | |
1554 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1555 | } | |
1556 | ||
75aa3f63 | 1557 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1558 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1559 | |
1560 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1561 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1562 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1563 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1564 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1565 | } | |
4d85529d | 1566 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1567 | mutex_lock(&dev_priv->rps.hw_lock); |
1568 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1569 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1570 | |
c8c8fb33 PZ |
1571 | intel_runtime_pm_put(dev_priv); |
1572 | ||
4d85529d BW |
1573 | seq_printf(m, "Video Turbo Mode: %s\n", |
1574 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1575 | seq_printf(m, "HW control enabled: %s\n", | |
1576 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1577 | seq_printf(m, "SW control enabled: %s\n", | |
1578 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1579 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1580 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1581 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1582 | seq_printf(m, "RC6 Enabled: %s\n", | |
1583 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1584 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1585 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1586 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1587 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1588 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1589 | } | |
4d85529d BW |
1590 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1591 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1592 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1593 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1594 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1595 | switch (gt_core_status & GEN6_RCn_MASK) { |
1596 | case GEN6_RC0: | |
1597 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1598 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1599 | else |
267f0c90 | 1600 | seq_puts(m, "on\n"); |
4d85529d BW |
1601 | break; |
1602 | case GEN6_RC3: | |
267f0c90 | 1603 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1604 | break; |
1605 | case GEN6_RC6: | |
267f0c90 | 1606 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1607 | break; |
1608 | case GEN6_RC7: | |
267f0c90 | 1609 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1610 | break; |
1611 | default: | |
267f0c90 | 1612 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1613 | break; |
1614 | } | |
1615 | ||
1616 | seq_printf(m, "Core Power Down: %s\n", | |
1617 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1618 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1619 | seq_printf(m, "Render Power Well: %s\n", |
1620 | (gen9_powergate_status & | |
1621 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1622 | seq_printf(m, "Media Power Well: %s\n", | |
1623 | (gen9_powergate_status & | |
1624 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1625 | } | |
cce66a28 BW |
1626 | |
1627 | /* Not exactly sure what this is */ | |
1628 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1629 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1630 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1631 | I915_READ(GEN6_GT_GFX_RC6)); | |
1632 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1633 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1634 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1635 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1636 | ||
ecd8faea BW |
1637 | seq_printf(m, "RC6 voltage: %dmV\n", |
1638 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1639 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1640 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1641 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1642 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1643 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1644 | } |
1645 | ||
1646 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1647 | { | |
36cdd013 | 1648 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4d85529d | 1649 | |
36cdd013 | 1650 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
669ab5aa | 1651 | return vlv_drpc_info(m); |
36cdd013 | 1652 | else if (INTEL_GEN(dev_priv) >= 6) |
4d85529d BW |
1653 | return gen6_drpc_info(m); |
1654 | else | |
1655 | return ironlake_drpc_info(m); | |
1656 | } | |
1657 | ||
9a851789 DV |
1658 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1659 | { | |
36cdd013 | 1660 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1661 | |
1662 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1663 | dev_priv->fb_tracking.busy_bits); | |
1664 | ||
1665 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1666 | dev_priv->fb_tracking.flip_bits); | |
1667 | ||
1668 | return 0; | |
1669 | } | |
1670 | ||
b5e50c3f JB |
1671 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1672 | { | |
36cdd013 | 1673 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1674 | |
36cdd013 | 1675 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1676 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1677 | return 0; |
1678 | } | |
1679 | ||
36623ef8 | 1680 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1681 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1682 | |
0e631adc | 1683 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1684 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1685 | else |
1686 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1687 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1688 | |
0fc6a9dc PZ |
1689 | if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { |
1690 | uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? | |
1691 | BDW_FBC_COMPRESSION_MASK : | |
1692 | IVB_FBC_COMPRESSION_MASK; | |
31b9df10 | 1693 | seq_printf(m, "Compressing: %s\n", |
0fc6a9dc PZ |
1694 | yesno(I915_READ(FBC_STATUS2) & mask)); |
1695 | } | |
31b9df10 | 1696 | |
25ad93fd | 1697 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1698 | intel_runtime_pm_put(dev_priv); |
1699 | ||
b5e50c3f JB |
1700 | return 0; |
1701 | } | |
1702 | ||
da46f936 RV |
1703 | static int i915_fbc_fc_get(void *data, u64 *val) |
1704 | { | |
36cdd013 | 1705 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1706 | |
36cdd013 | 1707 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1708 | return -ENODEV; |
1709 | ||
da46f936 | 1710 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1711 | |
1712 | return 0; | |
1713 | } | |
1714 | ||
1715 | static int i915_fbc_fc_set(void *data, u64 val) | |
1716 | { | |
36cdd013 | 1717 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1718 | u32 reg; |
1719 | ||
36cdd013 | 1720 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1721 | return -ENODEV; |
1722 | ||
25ad93fd | 1723 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1724 | |
1725 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1726 | dev_priv->fbc.false_color = val; | |
1727 | ||
1728 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1729 | (reg | FBC_CTL_FALSE_COLOR) : | |
1730 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1731 | ||
25ad93fd | 1732 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1733 | return 0; |
1734 | } | |
1735 | ||
1736 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1737 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1738 | "%llu\n"); | |
1739 | ||
92d44621 PZ |
1740 | static int i915_ips_status(struct seq_file *m, void *unused) |
1741 | { | |
36cdd013 | 1742 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1743 | |
36cdd013 | 1744 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1745 | seq_puts(m, "not supported\n"); |
1746 | return 0; | |
1747 | } | |
1748 | ||
36623ef8 PZ |
1749 | intel_runtime_pm_get(dev_priv); |
1750 | ||
0eaa53f0 RV |
1751 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1752 | yesno(i915.enable_ips)); | |
1753 | ||
36cdd013 | 1754 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1755 | seq_puts(m, "Currently: unknown\n"); |
1756 | } else { | |
1757 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1758 | seq_puts(m, "Currently: enabled\n"); | |
1759 | else | |
1760 | seq_puts(m, "Currently: disabled\n"); | |
1761 | } | |
92d44621 | 1762 | |
36623ef8 PZ |
1763 | intel_runtime_pm_put(dev_priv); |
1764 | ||
92d44621 PZ |
1765 | return 0; |
1766 | } | |
1767 | ||
4a9bef37 JB |
1768 | static int i915_sr_status(struct seq_file *m, void *unused) |
1769 | { | |
36cdd013 | 1770 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1771 | bool sr_enabled = false; |
1772 | ||
36623ef8 | 1773 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1774 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1775 | |
36cdd013 | 1776 | if (HAS_PCH_SPLIT(dev_priv)) |
5ba2aaaa | 1777 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1778 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1779 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1780 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1781 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1782 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1783 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1784 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1785 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1786 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1787 | |
9c870d03 | 1788 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1789 | intel_runtime_pm_put(dev_priv); |
1790 | ||
08c4d7fc | 1791 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1792 | |
1793 | return 0; | |
1794 | } | |
1795 | ||
7648fa99 JB |
1796 | static int i915_emon_status(struct seq_file *m, void *unused) |
1797 | { | |
36cdd013 DW |
1798 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1799 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1800 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1801 | int ret; |
1802 | ||
36cdd013 | 1803 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1804 | return -ENODEV; |
1805 | ||
de227ef0 CW |
1806 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1807 | if (ret) | |
1808 | return ret; | |
7648fa99 JB |
1809 | |
1810 | temp = i915_mch_val(dev_priv); | |
1811 | chipset = i915_chipset_val(dev_priv); | |
1812 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1813 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1814 | |
1815 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1816 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1817 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1818 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1819 | ||
1820 | return 0; | |
1821 | } | |
1822 | ||
23b2f8bb JB |
1823 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1824 | { | |
36cdd013 | 1825 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1826 | int ret = 0; |
23b2f8bb | 1827 | int gpu_freq, ia_freq; |
f936ec34 | 1828 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1829 | |
26310346 | 1830 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1831 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1832 | return 0; |
1833 | } | |
1834 | ||
5bfa0199 PZ |
1835 | intel_runtime_pm_get(dev_priv); |
1836 | ||
4fc688ce | 1837 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1838 | if (ret) |
5bfa0199 | 1839 | goto out; |
23b2f8bb | 1840 | |
b976dc53 | 1841 | if (IS_GEN9_BC(dev_priv)) { |
f936ec34 AG |
1842 | /* Convert GT frequency to 50 HZ units */ |
1843 | min_gpu_freq = | |
1844 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1845 | max_gpu_freq = | |
1846 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1847 | } else { | |
1848 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1849 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1850 | } | |
1851 | ||
267f0c90 | 1852 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1853 | |
f936ec34 | 1854 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1855 | ia_freq = gpu_freq; |
1856 | sandybridge_pcode_read(dev_priv, | |
1857 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1858 | &ia_freq); | |
3ebecd07 | 1859 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1860 | intel_gpu_freq(dev_priv, (gpu_freq * |
b976dc53 RV |
1861 | (IS_GEN9_BC(dev_priv) ? |
1862 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1863 | ((ia_freq >> 0) & 0xff) * 100, |
1864 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1865 | } |
1866 | ||
4fc688ce | 1867 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1868 | |
5bfa0199 PZ |
1869 | out: |
1870 | intel_runtime_pm_put(dev_priv); | |
1871 | return ret; | |
23b2f8bb JB |
1872 | } |
1873 | ||
44834a67 CW |
1874 | static int i915_opregion(struct seq_file *m, void *unused) |
1875 | { | |
36cdd013 DW |
1876 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1877 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1878 | struct intel_opregion *opregion = &dev_priv->opregion; |
1879 | int ret; | |
1880 | ||
1881 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1882 | if (ret) | |
0d38f009 | 1883 | goto out; |
44834a67 | 1884 | |
2455a8e4 JN |
1885 | if (opregion->header) |
1886 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1887 | |
1888 | mutex_unlock(&dev->struct_mutex); | |
1889 | ||
0d38f009 | 1890 | out: |
44834a67 CW |
1891 | return 0; |
1892 | } | |
1893 | ||
ada8f955 JN |
1894 | static int i915_vbt(struct seq_file *m, void *unused) |
1895 | { | |
36cdd013 | 1896 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1897 | |
1898 | if (opregion->vbt) | |
1899 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1900 | ||
1901 | return 0; | |
1902 | } | |
1903 | ||
37811fcc CW |
1904 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1905 | { | |
36cdd013 DW |
1906 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1907 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1908 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1909 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1910 | int ret; |
1911 | ||
1912 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1913 | if (ret) | |
1914 | return ret; | |
37811fcc | 1915 | |
0695726e | 1916 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1917 | if (dev_priv->fbdev) { |
1918 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1919 | |
1920 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1921 | fbdev_fb->base.width, | |
1922 | fbdev_fb->base.height, | |
b00c600e | 1923 | fbdev_fb->base.format->depth, |
272725c7 | 1924 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1925 | fbdev_fb->base.modifier, |
25bcce94 CW |
1926 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1927 | describe_obj(m, fbdev_fb->obj); | |
1928 | seq_putc(m, '\n'); | |
1929 | } | |
4520f53a | 1930 | #endif |
37811fcc | 1931 | |
4b096ac1 | 1932 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1933 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1934 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1935 | if (fb == fbdev_fb) | |
37811fcc CW |
1936 | continue; |
1937 | ||
c1ca506d | 1938 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1939 | fb->base.width, |
1940 | fb->base.height, | |
b00c600e | 1941 | fb->base.format->depth, |
272725c7 | 1942 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1943 | fb->base.modifier, |
747a598f | 1944 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1945 | describe_obj(m, fb->obj); |
267f0c90 | 1946 | seq_putc(m, '\n'); |
37811fcc | 1947 | } |
4b096ac1 | 1948 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1949 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1950 | |
1951 | return 0; | |
1952 | } | |
1953 | ||
7e37f889 | 1954 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1955 | { |
1956 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1957 | ring->space, ring->head, ring->tail, |
1958 | ring->last_retired_head); | |
c9fe99bd OM |
1959 | } |
1960 | ||
e76d3630 BW |
1961 | static int i915_context_status(struct seq_file *m, void *unused) |
1962 | { | |
36cdd013 DW |
1963 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1964 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1965 | struct intel_engine_cs *engine; |
e2efd130 | 1966 | struct i915_gem_context *ctx; |
3b3f1650 | 1967 | enum intel_engine_id id; |
c3232b18 | 1968 | int ret; |
e76d3630 | 1969 | |
f3d28878 | 1970 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1971 | if (ret) |
1972 | return ret; | |
1973 | ||
a33afea5 | 1974 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1975 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1976 | if (ctx->pid) { |
d28b99ab CW |
1977 | struct task_struct *task; |
1978 | ||
c84455b4 | 1979 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1980 | if (task) { |
1981 | seq_printf(m, "(%s [%d]) ", | |
1982 | task->comm, task->pid); | |
1983 | put_task_struct(task); | |
1984 | } | |
c84455b4 CW |
1985 | } else if (IS_ERR(ctx->file_priv)) { |
1986 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1987 | } else { |
1988 | seq_puts(m, "(kernel) "); | |
1989 | } | |
1990 | ||
bca44d80 CW |
1991 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1992 | seq_putc(m, '\n'); | |
c9fe99bd | 1993 | |
3b3f1650 | 1994 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1995 | struct intel_context *ce = &ctx->engine[engine->id]; |
1996 | ||
1997 | seq_printf(m, "%s: ", engine->name); | |
1998 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1999 | if (ce->state) | |
bf3783e5 | 2000 | describe_obj(m, ce->state->obj); |
dca33ecc | 2001 | if (ce->ring) |
7e37f889 | 2002 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 2003 | seq_putc(m, '\n'); |
c9fe99bd | 2004 | } |
a33afea5 | 2005 | |
a33afea5 | 2006 | seq_putc(m, '\n'); |
a168c293 BW |
2007 | } |
2008 | ||
f3d28878 | 2009 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
2010 | |
2011 | return 0; | |
2012 | } | |
2013 | ||
064ca1d2 | 2014 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 2015 | struct i915_gem_context *ctx, |
0bc40be8 | 2016 | struct intel_engine_cs *engine) |
064ca1d2 | 2017 | { |
bf3783e5 | 2018 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 2019 | struct page *page; |
064ca1d2 | 2020 | int j; |
064ca1d2 | 2021 | |
7069b144 CW |
2022 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2023 | ||
bf3783e5 CW |
2024 | if (!vma) { |
2025 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2026 | return; |
2027 | } | |
2028 | ||
bf3783e5 CW |
2029 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2030 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 2031 | i915_ggtt_offset(vma)); |
064ca1d2 | 2032 | |
a4f5ea64 | 2033 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 2034 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
2035 | return; |
2036 | } | |
2037 | ||
bf3783e5 CW |
2038 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2039 | if (page) { | |
2040 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2041 | |
2042 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2043 | seq_printf(m, |
2044 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2045 | j * 4, | |
064ca1d2 TD |
2046 | reg_state[j], reg_state[j + 1], |
2047 | reg_state[j + 2], reg_state[j + 3]); | |
2048 | } | |
2049 | kunmap_atomic(reg_state); | |
2050 | } | |
2051 | ||
a4f5ea64 | 2052 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2053 | seq_putc(m, '\n'); |
2054 | } | |
2055 | ||
c0ab1ae9 BW |
2056 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2057 | { | |
36cdd013 DW |
2058 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2059 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2060 | struct intel_engine_cs *engine; |
e2efd130 | 2061 | struct i915_gem_context *ctx; |
3b3f1650 | 2062 | enum intel_engine_id id; |
b4ac5afc | 2063 | int ret; |
c0ab1ae9 BW |
2064 | |
2065 | if (!i915.enable_execlists) { | |
2066 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2067 | return 0; | |
2068 | } | |
2069 | ||
2070 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2071 | if (ret) | |
2072 | return ret; | |
2073 | ||
e28e404c | 2074 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3b3f1650 | 2075 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2076 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2077 | |
2078 | mutex_unlock(&dev->struct_mutex); | |
2079 | ||
2080 | return 0; | |
2081 | } | |
2082 | ||
ea16a3cd DV |
2083 | static const char *swizzle_string(unsigned swizzle) |
2084 | { | |
aee56cff | 2085 | switch (swizzle) { |
ea16a3cd DV |
2086 | case I915_BIT_6_SWIZZLE_NONE: |
2087 | return "none"; | |
2088 | case I915_BIT_6_SWIZZLE_9: | |
2089 | return "bit9"; | |
2090 | case I915_BIT_6_SWIZZLE_9_10: | |
2091 | return "bit9/bit10"; | |
2092 | case I915_BIT_6_SWIZZLE_9_11: | |
2093 | return "bit9/bit11"; | |
2094 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2095 | return "bit9/bit10/bit11"; | |
2096 | case I915_BIT_6_SWIZZLE_9_17: | |
2097 | return "bit9/bit17"; | |
2098 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2099 | return "bit9/bit10/bit17"; | |
2100 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2101 | return "unknown"; |
ea16a3cd DV |
2102 | } |
2103 | ||
2104 | return "bug"; | |
2105 | } | |
2106 | ||
2107 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2108 | { | |
36cdd013 | 2109 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2110 | |
c8c8fb33 | 2111 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2112 | |
ea16a3cd DV |
2113 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2114 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2115 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2116 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2117 | ||
36cdd013 | 2118 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2119 | seq_printf(m, "DDC = 0x%08x\n", |
2120 | I915_READ(DCC)); | |
656bfa3a DV |
2121 | seq_printf(m, "DDC2 = 0x%08x\n", |
2122 | I915_READ(DCC2)); | |
ea16a3cd DV |
2123 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2124 | I915_READ16(C0DRB3)); | |
2125 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2126 | I915_READ16(C1DRB3)); | |
36cdd013 | 2127 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2128 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2129 | I915_READ(MAD_DIMM_C0)); | |
2130 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2131 | I915_READ(MAD_DIMM_C1)); | |
2132 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2133 | I915_READ(MAD_DIMM_C2)); | |
2134 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2135 | I915_READ(TILECTL)); | |
36cdd013 | 2136 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2137 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2138 | I915_READ(GAMTARBMODE)); | |
2139 | else | |
2140 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2141 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2142 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2143 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2144 | } |
656bfa3a DV |
2145 | |
2146 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2147 | seq_puts(m, "L-shaped memory detected\n"); | |
2148 | ||
c8c8fb33 | 2149 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2150 | |
2151 | return 0; | |
2152 | } | |
2153 | ||
1c60fef5 BW |
2154 | static int per_file_ctx(int id, void *ptr, void *data) |
2155 | { | |
e2efd130 | 2156 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2157 | struct seq_file *m = data; |
ae6c4806 DV |
2158 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2159 | ||
2160 | if (!ppgtt) { | |
2161 | seq_printf(m, " no ppgtt for context %d\n", | |
2162 | ctx->user_handle); | |
2163 | return 0; | |
2164 | } | |
1c60fef5 | 2165 | |
f83d6518 OM |
2166 | if (i915_gem_context_is_default(ctx)) |
2167 | seq_puts(m, " default context:\n"); | |
2168 | else | |
821d66dd | 2169 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2170 | ppgtt->debug_dump(ppgtt, m); |
2171 | ||
2172 | return 0; | |
2173 | } | |
2174 | ||
36cdd013 DW |
2175 | static void gen8_ppgtt_info(struct seq_file *m, |
2176 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2177 | { |
77df6772 | 2178 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2179 | struct intel_engine_cs *engine; |
2180 | enum intel_engine_id id; | |
b4ac5afc | 2181 | int i; |
3cf17fc5 | 2182 | |
77df6772 BW |
2183 | if (!ppgtt) |
2184 | return; | |
2185 | ||
3b3f1650 | 2186 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2187 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2188 | for (i = 0; i < 4; i++) { |
e2f80391 | 2189 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2190 | pdp <<= 32; |
e2f80391 | 2191 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2192 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2193 | } |
2194 | } | |
2195 | } | |
2196 | ||
36cdd013 DW |
2197 | static void gen6_ppgtt_info(struct seq_file *m, |
2198 | struct drm_i915_private *dev_priv) | |
77df6772 | 2199 | { |
e2f80391 | 2200 | struct intel_engine_cs *engine; |
3b3f1650 | 2201 | enum intel_engine_id id; |
3cf17fc5 | 2202 | |
7e22dbbb | 2203 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2204 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2205 | ||
3b3f1650 | 2206 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2207 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2208 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2209 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2210 | I915_READ(RING_MODE_GEN7(engine))); | |
2211 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2212 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2213 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2214 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2215 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2216 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2217 | } |
2218 | if (dev_priv->mm.aliasing_ppgtt) { | |
2219 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2220 | ||
267f0c90 | 2221 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2222 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2223 | |
87d60b63 | 2224 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2225 | } |
1c60fef5 | 2226 | |
3cf17fc5 | 2227 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2228 | } |
2229 | ||
2230 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2231 | { | |
36cdd013 DW |
2232 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2233 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2234 | struct drm_file *file; |
637ee29e | 2235 | int ret; |
77df6772 | 2236 | |
637ee29e CW |
2237 | mutex_lock(&dev->filelist_mutex); |
2238 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2239 | if (ret) |
637ee29e CW |
2240 | goto out_unlock; |
2241 | ||
c8c8fb33 | 2242 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2243 | |
36cdd013 DW |
2244 | if (INTEL_GEN(dev_priv) >= 8) |
2245 | gen8_ppgtt_info(m, dev_priv); | |
2246 | else if (INTEL_GEN(dev_priv) >= 6) | |
2247 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2248 | |
ea91e401 MT |
2249 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2250 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2251 | struct task_struct *task; |
ea91e401 | 2252 | |
7cb5dff8 | 2253 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2254 | if (!task) { |
2255 | ret = -ESRCH; | |
637ee29e | 2256 | goto out_rpm; |
06812760 | 2257 | } |
7cb5dff8 GT |
2258 | seq_printf(m, "\nproc: %s\n", task->comm); |
2259 | put_task_struct(task); | |
ea91e401 MT |
2260 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2261 | (void *)(unsigned long)m); | |
2262 | } | |
2263 | ||
637ee29e | 2264 | out_rpm: |
c8c8fb33 | 2265 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2266 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2267 | out_unlock: |
2268 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2269 | return ret; |
3cf17fc5 DV |
2270 | } |
2271 | ||
f5a4c67d CW |
2272 | static int count_irq_waiters(struct drm_i915_private *i915) |
2273 | { | |
e2f80391 | 2274 | struct intel_engine_cs *engine; |
3b3f1650 | 2275 | enum intel_engine_id id; |
f5a4c67d | 2276 | int count = 0; |
f5a4c67d | 2277 | |
3b3f1650 | 2278 | for_each_engine(engine, i915, id) |
688e6c72 | 2279 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2280 | |
2281 | return count; | |
2282 | } | |
2283 | ||
7466c291 CW |
2284 | static const char *rps_power_to_str(unsigned int power) |
2285 | { | |
2286 | static const char * const strings[] = { | |
2287 | [LOW_POWER] = "low power", | |
2288 | [BETWEEN] = "mixed", | |
2289 | [HIGH_POWER] = "high power", | |
2290 | }; | |
2291 | ||
2292 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2293 | return "unknown"; | |
2294 | ||
2295 | return strings[power]; | |
2296 | } | |
2297 | ||
1854d5ca CW |
2298 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2299 | { | |
36cdd013 DW |
2300 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2301 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2302 | struct drm_file *file; |
1854d5ca | 2303 | |
f5a4c67d | 2304 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2305 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2306 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2307 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2308 | seq_printf(m, "Frequency requested %d\n", |
2309 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2310 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2311 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2312 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2313 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2314 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2315 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2316 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2317 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2318 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2319 | |
2320 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2321 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2322 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2323 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2324 | struct task_struct *task; | |
2325 | ||
2326 | rcu_read_lock(); | |
2327 | task = pid_task(file->pid, PIDTYPE_PID); | |
2328 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2329 | task ? task->comm : "<unknown>", | |
2330 | task ? task->pid : -1, | |
2e1b8730 CW |
2331 | file_priv->rps.boosts, |
2332 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2333 | rcu_read_unlock(); |
2334 | } | |
197be2ae | 2335 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2336 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2337 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2338 | |
7466c291 CW |
2339 | if (INTEL_GEN(dev_priv) >= 6 && |
2340 | dev_priv->rps.enabled && | |
28176ef4 | 2341 | dev_priv->gt.active_requests) { |
7466c291 CW |
2342 | u32 rpup, rpupei; |
2343 | u32 rpdown, rpdownei; | |
2344 | ||
2345 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2346 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2347 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2348 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2349 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2350 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2351 | ||
2352 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2353 | rps_power_to_str(dev_priv->rps.power)); | |
2354 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
23f4a287 | 2355 | rpup && rpupei ? 100 * rpup / rpupei : 0, |
7466c291 CW |
2356 | dev_priv->rps.up_threshold); |
2357 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
23f4a287 | 2358 | rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, |
7466c291 CW |
2359 | dev_priv->rps.down_threshold); |
2360 | } else { | |
2361 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2362 | } | |
2363 | ||
8d3afd7d | 2364 | return 0; |
1854d5ca CW |
2365 | } |
2366 | ||
63573eb7 BW |
2367 | static int i915_llc(struct seq_file *m, void *data) |
2368 | { | |
36cdd013 | 2369 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2370 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2371 | |
36cdd013 | 2372 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2373 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2374 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2375 | |
2376 | return 0; | |
2377 | } | |
2378 | ||
0509ead1 AS |
2379 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2380 | { | |
2381 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2382 | struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; | |
2383 | ||
2384 | if (!HAS_HUC_UCODE(dev_priv)) | |
2385 | return 0; | |
2386 | ||
2387 | seq_puts(m, "HuC firmware status:\n"); | |
2388 | seq_printf(m, "\tpath: %s\n", huc_fw->path); | |
2389 | seq_printf(m, "\tfetch: %s\n", | |
2390 | intel_uc_fw_status_repr(huc_fw->fetch_status)); | |
2391 | seq_printf(m, "\tload: %s\n", | |
2392 | intel_uc_fw_status_repr(huc_fw->load_status)); | |
2393 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2394 | huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted); | |
2395 | seq_printf(m, "\tversion found: %d.%d\n", | |
2396 | huc_fw->major_ver_found, huc_fw->minor_ver_found); | |
2397 | seq_printf(m, "\theader: offset is %d; size = %d\n", | |
2398 | huc_fw->header_offset, huc_fw->header_size); | |
2399 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2400 | huc_fw->ucode_offset, huc_fw->ucode_size); | |
2401 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2402 | huc_fw->rsa_offset, huc_fw->rsa_size); | |
2403 | ||
3582ad13 | 2404 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2405 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2406 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2407 | |
2408 | return 0; | |
2409 | } | |
2410 | ||
fdf5d357 AD |
2411 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2412 | { | |
36cdd013 | 2413 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
db0a091b | 2414 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
fdf5d357 AD |
2415 | u32 tmp, i; |
2416 | ||
2d1fe073 | 2417 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2418 | return 0; |
2419 | ||
2420 | seq_printf(m, "GuC firmware status:\n"); | |
2421 | seq_printf(m, "\tpath: %s\n", | |
db0a091b | 2422 | guc_fw->path); |
fdf5d357 | 2423 | seq_printf(m, "\tfetch: %s\n", |
db0a091b | 2424 | intel_uc_fw_status_repr(guc_fw->fetch_status)); |
fdf5d357 | 2425 | seq_printf(m, "\tload: %s\n", |
db0a091b | 2426 | intel_uc_fw_status_repr(guc_fw->load_status)); |
fdf5d357 | 2427 | seq_printf(m, "\tversion wanted: %d.%d\n", |
db0a091b | 2428 | guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted); |
fdf5d357 | 2429 | seq_printf(m, "\tversion found: %d.%d\n", |
db0a091b | 2430 | guc_fw->major_ver_found, guc_fw->minor_ver_found); |
feda33ef AD |
2431 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2432 | guc_fw->header_offset, guc_fw->header_size); | |
2433 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2434 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2435 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2436 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 | 2437 | |
3582ad13 | 2438 | intel_runtime_pm_get(dev_priv); |
2439 | ||
fdf5d357 AD |
2440 | tmp = I915_READ(GUC_STATUS); |
2441 | ||
2442 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2443 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2444 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2445 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2446 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2447 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2448 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2449 | seq_puts(m, "\nScratch registers:\n"); | |
2450 | for (i = 0; i < 16; i++) | |
2451 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2452 | ||
3582ad13 | 2453 | intel_runtime_pm_put(dev_priv); |
2454 | ||
fdf5d357 AD |
2455 | return 0; |
2456 | } | |
2457 | ||
5aa1ee4b AG |
2458 | static void i915_guc_log_info(struct seq_file *m, |
2459 | struct drm_i915_private *dev_priv) | |
2460 | { | |
2461 | struct intel_guc *guc = &dev_priv->guc; | |
2462 | ||
2463 | seq_puts(m, "\nGuC logging stats:\n"); | |
2464 | ||
2465 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2466 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2467 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2468 | ||
2469 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2470 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2471 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2472 | ||
2473 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2474 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2475 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2476 | ||
2477 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2478 | guc->log.flush_interrupt_count); | |
2479 | ||
2480 | seq_printf(m, "\tCapture miss count: %u\n", | |
2481 | guc->log.capture_miss_count); | |
2482 | } | |
2483 | ||
8b417c26 DG |
2484 | static void i915_guc_client_info(struct seq_file *m, |
2485 | struct drm_i915_private *dev_priv, | |
2486 | struct i915_guc_client *client) | |
2487 | { | |
e2f80391 | 2488 | struct intel_engine_cs *engine; |
c18468c4 | 2489 | enum intel_engine_id id; |
8b417c26 | 2490 | uint64_t tot = 0; |
8b417c26 DG |
2491 | |
2492 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2493 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2494 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
357248bf | 2495 | client->doorbell_id, client->doorbell_offset, client->doorbell_cookie); |
8b417c26 DG |
2496 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", |
2497 | client->wq_size, client->wq_offset, client->wq_tail); | |
2498 | ||
551aaecd | 2499 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2500 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2501 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2502 | ||
3b3f1650 | 2503 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2504 | u64 submissions = client->submissions[id]; |
2505 | tot += submissions; | |
8b417c26 | 2506 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2507 | submissions, engine->name); |
8b417c26 DG |
2508 | } |
2509 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2510 | } | |
2511 | ||
2512 | static int i915_guc_info(struct seq_file *m, void *data) | |
2513 | { | |
36cdd013 | 2514 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
334636c6 | 2515 | const struct intel_guc *guc = &dev_priv->guc; |
e2f80391 | 2516 | struct intel_engine_cs *engine; |
c18468c4 | 2517 | enum intel_engine_id id; |
334636c6 | 2518 | u64 total; |
8b417c26 | 2519 | |
334636c6 CW |
2520 | if (!guc->execbuf_client) { |
2521 | seq_printf(m, "GuC submission %s\n", | |
2522 | HAS_GUC_SCHED(dev_priv) ? | |
2523 | "disabled" : | |
2524 | "not supported"); | |
5a843307 | 2525 | return 0; |
334636c6 | 2526 | } |
8b417c26 | 2527 | |
9636f6db | 2528 | seq_printf(m, "Doorbell map:\n"); |
334636c6 CW |
2529 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc->doorbell_bitmap); |
2530 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); | |
9636f6db | 2531 | |
334636c6 CW |
2532 | seq_printf(m, "GuC total action count: %llu\n", guc->action_count); |
2533 | seq_printf(m, "GuC action failure count: %u\n", guc->action_fail); | |
2534 | seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd); | |
2535 | seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status); | |
2536 | seq_printf(m, "GuC last action error code: %d\n", guc->action_err); | |
8b417c26 | 2537 | |
334636c6 | 2538 | total = 0; |
8b417c26 | 2539 | seq_printf(m, "\nGuC submissions:\n"); |
3b3f1650 | 2540 | for_each_engine(engine, dev_priv, id) { |
334636c6 | 2541 | u64 submissions = guc->submissions[id]; |
c18468c4 | 2542 | total += submissions; |
397097b0 | 2543 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
334636c6 | 2544 | engine->name, submissions, guc->last_seqno[id]); |
8b417c26 DG |
2545 | } |
2546 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2547 | ||
334636c6 CW |
2548 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2549 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
8b417c26 | 2550 | |
5aa1ee4b AG |
2551 | i915_guc_log_info(m, dev_priv); |
2552 | ||
8b417c26 DG |
2553 | /* Add more as required ... */ |
2554 | ||
2555 | return 0; | |
2556 | } | |
2557 | ||
4c7e77fc AD |
2558 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2559 | { | |
36cdd013 | 2560 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2561 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2562 | int i = 0, pg; |
2563 | ||
d6b40b4b | 2564 | if (!dev_priv->guc.log.vma) |
4c7e77fc AD |
2565 | return 0; |
2566 | ||
d6b40b4b | 2567 | obj = dev_priv->guc.log.vma->obj; |
8b797af1 CW |
2568 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { |
2569 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2570 | |
2571 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2572 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2573 | *(log + i), *(log + i + 1), | |
2574 | *(log + i + 2), *(log + i + 3)); | |
2575 | ||
2576 | kunmap_atomic(log); | |
2577 | } | |
2578 | ||
2579 | seq_putc(m, '\n'); | |
2580 | ||
2581 | return 0; | |
2582 | } | |
2583 | ||
685534ef SAK |
2584 | static int i915_guc_log_control_get(void *data, u64 *val) |
2585 | { | |
2586 | struct drm_device *dev = data; | |
2587 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2588 | ||
2589 | if (!dev_priv->guc.log.vma) | |
2590 | return -EINVAL; | |
2591 | ||
2592 | *val = i915.guc_log_level; | |
2593 | ||
2594 | return 0; | |
2595 | } | |
2596 | ||
2597 | static int i915_guc_log_control_set(void *data, u64 val) | |
2598 | { | |
2599 | struct drm_device *dev = data; | |
2600 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2601 | int ret; | |
2602 | ||
2603 | if (!dev_priv->guc.log.vma) | |
2604 | return -EINVAL; | |
2605 | ||
2606 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2607 | if (ret) | |
2608 | return ret; | |
2609 | ||
2610 | intel_runtime_pm_get(dev_priv); | |
2611 | ret = i915_guc_log_control(dev_priv, val); | |
2612 | intel_runtime_pm_put(dev_priv); | |
2613 | ||
2614 | mutex_unlock(&dev->struct_mutex); | |
2615 | return ret; | |
2616 | } | |
2617 | ||
2618 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2619 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2620 | "%lld\n"); | |
2621 | ||
b86bef20 CW |
2622 | static const char *psr2_live_status(u32 val) |
2623 | { | |
2624 | static const char * const live_status[] = { | |
2625 | "IDLE", | |
2626 | "CAPTURE", | |
2627 | "CAPTURE_FS", | |
2628 | "SLEEP", | |
2629 | "BUFON_FW", | |
2630 | "ML_UP", | |
2631 | "SU_STANDBY", | |
2632 | "FAST_SLEEP", | |
2633 | "DEEP_SLEEP", | |
2634 | "BUF_ON", | |
2635 | "TG_ON" | |
2636 | }; | |
2637 | ||
2638 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2639 | if (val < ARRAY_SIZE(live_status)) | |
2640 | return live_status[val]; | |
2641 | ||
2642 | return "unknown"; | |
2643 | } | |
2644 | ||
e91fd8c6 RV |
2645 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2646 | { | |
36cdd013 | 2647 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2648 | u32 psrperf = 0; |
a6cbdb8e RV |
2649 | u32 stat[3]; |
2650 | enum pipe pipe; | |
a031d709 | 2651 | bool enabled = false; |
e91fd8c6 | 2652 | |
36cdd013 | 2653 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2654 | seq_puts(m, "PSR not supported\n"); |
2655 | return 0; | |
2656 | } | |
2657 | ||
c8c8fb33 PZ |
2658 | intel_runtime_pm_get(dev_priv); |
2659 | ||
fa128fa6 | 2660 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2661 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2662 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2663 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2664 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2665 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2666 | dev_priv->psr.busy_frontbuffer_bits); | |
2667 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2668 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2669 | |
7e3eb599 NV |
2670 | if (HAS_DDI(dev_priv)) { |
2671 | if (dev_priv->psr.psr2_support) | |
2672 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2673 | else | |
2674 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2675 | } else { | |
3553a8ea | 2676 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2677 | enum transcoder cpu_transcoder = |
2678 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2679 | enum intel_display_power_domain power_domain; | |
2680 | ||
2681 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2682 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2683 | power_domain)) | |
2684 | continue; | |
2685 | ||
3553a8ea DL |
2686 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2687 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2688 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2689 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2690 | enabled = true; | |
9c870d03 CW |
2691 | |
2692 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2693 | } |
2694 | } | |
60e5ffe3 RV |
2695 | |
2696 | seq_printf(m, "Main link in standby mode: %s\n", | |
2697 | yesno(dev_priv->psr.link_standby)); | |
2698 | ||
a6cbdb8e RV |
2699 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2700 | ||
36cdd013 | 2701 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2702 | for_each_pipe(dev_priv, pipe) { |
2703 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2704 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2705 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2706 | } | |
2707 | seq_puts(m, "\n"); | |
e91fd8c6 | 2708 | |
05eec3c2 RV |
2709 | /* |
2710 | * VLV/CHV PSR has no kind of performance counter | |
2711 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2712 | */ | |
36cdd013 | 2713 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2714 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2715 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2716 | |
2717 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2718 | } | |
6ba1f9e1 | 2719 | if (dev_priv->psr.psr2_support) { |
b86bef20 CW |
2720 | u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL); |
2721 | ||
2722 | seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n", | |
2723 | psr2, psr2_live_status(psr2)); | |
6ba1f9e1 | 2724 | } |
fa128fa6 | 2725 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2726 | |
c8c8fb33 | 2727 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2728 | return 0; |
2729 | } | |
2730 | ||
d2e216d0 RV |
2731 | static int i915_sink_crc(struct seq_file *m, void *data) |
2732 | { | |
36cdd013 DW |
2733 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2734 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 RV |
2735 | struct intel_connector *connector; |
2736 | struct intel_dp *intel_dp = NULL; | |
2737 | int ret; | |
2738 | u8 crc[6]; | |
2739 | ||
2740 | drm_modeset_lock_all(dev); | |
aca5e361 | 2741 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2742 | struct drm_crtc *crtc; |
d2e216d0 | 2743 | |
26c17cf6 | 2744 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2745 | continue; |
2746 | ||
26c17cf6 ML |
2747 | crtc = connector->base.state->crtc; |
2748 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2749 | continue; |
2750 | ||
26c17cf6 | 2751 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2752 | continue; |
2753 | ||
26c17cf6 | 2754 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2755 | |
2756 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2757 | if (ret) | |
2758 | goto out; | |
2759 | ||
2760 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2761 | crc[0], crc[1], crc[2], | |
2762 | crc[3], crc[4], crc[5]); | |
2763 | goto out; | |
2764 | } | |
2765 | ret = -ENODEV; | |
2766 | out: | |
2767 | drm_modeset_unlock_all(dev); | |
2768 | return ret; | |
2769 | } | |
2770 | ||
ec013e7f JB |
2771 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2772 | { | |
36cdd013 | 2773 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2774 | u64 power; |
2775 | u32 units; | |
2776 | ||
36cdd013 | 2777 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2778 | return -ENODEV; |
2779 | ||
36623ef8 PZ |
2780 | intel_runtime_pm_get(dev_priv); |
2781 | ||
ec013e7f JB |
2782 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2783 | power = (power & 0x1f00) >> 8; | |
2784 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2785 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2786 | power *= units; | |
2787 | ||
36623ef8 PZ |
2788 | intel_runtime_pm_put(dev_priv); |
2789 | ||
ec013e7f | 2790 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2791 | |
2792 | return 0; | |
2793 | } | |
2794 | ||
6455c870 | 2795 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2796 | { |
36cdd013 | 2797 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2798 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2799 | |
a156e64d CW |
2800 | if (!HAS_RUNTIME_PM(dev_priv)) |
2801 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2802 | |
67d97da3 | 2803 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2804 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2805 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2806 | #ifdef CONFIG_PM |
a6aaec8b | 2807 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2808 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2809 | #else |
2810 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2811 | #endif | |
a156e64d | 2812 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2813 | pci_power_name(pdev->current_state), |
2814 | pdev->current_state); | |
371db66a | 2815 | |
ec013e7f JB |
2816 | return 0; |
2817 | } | |
2818 | ||
1da51581 ID |
2819 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2820 | { | |
36cdd013 | 2821 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2822 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2823 | int i; | |
2824 | ||
2825 | mutex_lock(&power_domains->lock); | |
2826 | ||
2827 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2828 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2829 | struct i915_power_well *power_well; | |
2830 | enum intel_display_power_domain power_domain; | |
2831 | ||
2832 | power_well = &power_domains->power_wells[i]; | |
2833 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2834 | power_well->count); | |
2835 | ||
8385c2ec | 2836 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2837 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2838 | intel_display_power_domain_str(power_domain), |
1da51581 | 2839 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2840 | } |
2841 | ||
2842 | mutex_unlock(&power_domains->lock); | |
2843 | ||
2844 | return 0; | |
2845 | } | |
2846 | ||
b7cec66d DL |
2847 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2848 | { | |
36cdd013 | 2849 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2850 | struct intel_csr *csr; |
2851 | ||
36cdd013 | 2852 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2853 | seq_puts(m, "not supported\n"); |
2854 | return 0; | |
2855 | } | |
2856 | ||
2857 | csr = &dev_priv->csr; | |
2858 | ||
6fb403de MK |
2859 | intel_runtime_pm_get(dev_priv); |
2860 | ||
b7cec66d DL |
2861 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2862 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2863 | ||
2864 | if (!csr->dmc_payload) | |
6fb403de | 2865 | goto out; |
b7cec66d DL |
2866 | |
2867 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2868 | CSR_VERSION_MINOR(csr->version)); | |
2869 | ||
36cdd013 | 2870 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2871 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2872 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2873 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2874 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2875 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2876 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2877 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2878 | } |
2879 | ||
6fb403de MK |
2880 | out: |
2881 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2882 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2883 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2884 | ||
8337206d DL |
2885 | intel_runtime_pm_put(dev_priv); |
2886 | ||
b7cec66d DL |
2887 | return 0; |
2888 | } | |
2889 | ||
53f5e3ca JB |
2890 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2891 | struct drm_display_mode *mode) | |
2892 | { | |
2893 | int i; | |
2894 | ||
2895 | for (i = 0; i < tabs; i++) | |
2896 | seq_putc(m, '\t'); | |
2897 | ||
2898 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2899 | mode->base.id, mode->name, | |
2900 | mode->vrefresh, mode->clock, | |
2901 | mode->hdisplay, mode->hsync_start, | |
2902 | mode->hsync_end, mode->htotal, | |
2903 | mode->vdisplay, mode->vsync_start, | |
2904 | mode->vsync_end, mode->vtotal, | |
2905 | mode->type, mode->flags); | |
2906 | } | |
2907 | ||
2908 | static void intel_encoder_info(struct seq_file *m, | |
2909 | struct intel_crtc *intel_crtc, | |
2910 | struct intel_encoder *intel_encoder) | |
2911 | { | |
36cdd013 DW |
2912 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2913 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2914 | struct drm_crtc *crtc = &intel_crtc->base; |
2915 | struct intel_connector *intel_connector; | |
2916 | struct drm_encoder *encoder; | |
2917 | ||
2918 | encoder = &intel_encoder->base; | |
2919 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2920 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2921 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2922 | struct drm_connector *connector = &intel_connector->base; | |
2923 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2924 | connector->base.id, | |
c23cc417 | 2925 | connector->name, |
53f5e3ca JB |
2926 | drm_get_connector_status_name(connector->status)); |
2927 | if (connector->status == connector_status_connected) { | |
2928 | struct drm_display_mode *mode = &crtc->mode; | |
2929 | seq_printf(m, ", mode:\n"); | |
2930 | intel_seq_print_mode(m, 2, mode); | |
2931 | } else { | |
2932 | seq_putc(m, '\n'); | |
2933 | } | |
2934 | } | |
2935 | } | |
2936 | ||
2937 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2938 | { | |
36cdd013 DW |
2939 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2940 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2941 | struct drm_crtc *crtc = &intel_crtc->base; |
2942 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2943 | struct drm_plane_state *plane_state = crtc->primary->state; |
2944 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2945 | |
23a48d53 | 2946 | if (fb) |
5aa8a937 | 2947 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2948 | fb->base.id, plane_state->src_x >> 16, |
2949 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2950 | else |
2951 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2952 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2953 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2954 | } | |
2955 | ||
2956 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2957 | { | |
2958 | struct drm_display_mode *mode = panel->fixed_mode; | |
2959 | ||
2960 | seq_printf(m, "\tfixed mode:\n"); | |
2961 | intel_seq_print_mode(m, 2, mode); | |
2962 | } | |
2963 | ||
2964 | static void intel_dp_info(struct seq_file *m, | |
2965 | struct intel_connector *intel_connector) | |
2966 | { | |
2967 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2968 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2969 | ||
2970 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2971 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2972 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2973 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2974 | |
2975 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2976 | &intel_dp->aux); | |
53f5e3ca JB |
2977 | } |
2978 | ||
9a148a96 LY |
2979 | static void intel_dp_mst_info(struct seq_file *m, |
2980 | struct intel_connector *intel_connector) | |
2981 | { | |
2982 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2983 | struct intel_dp_mst_encoder *intel_mst = | |
2984 | enc_to_mst(&intel_encoder->base); | |
2985 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2986 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2987 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2988 | intel_connector->port); | |
2989 | ||
2990 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2991 | } | |
2992 | ||
53f5e3ca JB |
2993 | static void intel_hdmi_info(struct seq_file *m, |
2994 | struct intel_connector *intel_connector) | |
2995 | { | |
2996 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2997 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2998 | ||
742f491d | 2999 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
3000 | } |
3001 | ||
3002 | static void intel_lvds_info(struct seq_file *m, | |
3003 | struct intel_connector *intel_connector) | |
3004 | { | |
3005 | intel_panel_info(m, &intel_connector->panel); | |
3006 | } | |
3007 | ||
3008 | static void intel_connector_info(struct seq_file *m, | |
3009 | struct drm_connector *connector) | |
3010 | { | |
3011 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3012 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 3013 | struct drm_display_mode *mode; |
53f5e3ca JB |
3014 | |
3015 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 3016 | connector->base.id, connector->name, |
53f5e3ca JB |
3017 | drm_get_connector_status_name(connector->status)); |
3018 | if (connector->status == connector_status_connected) { | |
3019 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
3020 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
3021 | connector->display_info.width_mm, | |
3022 | connector->display_info.height_mm); | |
3023 | seq_printf(m, "\tsubpixel order: %s\n", | |
3024 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
3025 | seq_printf(m, "\tCEA rev: %d\n", | |
3026 | connector->display_info.cea_rev); | |
3027 | } | |
ee648a74 ML |
3028 | |
3029 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3030 | return; | |
3031 | ||
3032 | switch (connector->connector_type) { | |
3033 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3034 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
3035 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
3036 | intel_dp_mst_info(m, intel_connector); | |
3037 | else | |
3038 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
3039 | break; |
3040 | case DRM_MODE_CONNECTOR_LVDS: | |
3041 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 3042 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
3043 | break; |
3044 | case DRM_MODE_CONNECTOR_HDMIA: | |
3045 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
3046 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
3047 | intel_hdmi_info(m, intel_connector); | |
3048 | break; | |
3049 | default: | |
3050 | break; | |
36cd7444 | 3051 | } |
53f5e3ca | 3052 | |
f103fc7d JB |
3053 | seq_printf(m, "\tmodes:\n"); |
3054 | list_for_each_entry(mode, &connector->modes, head) | |
3055 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3056 | } |
3057 | ||
36cdd013 | 3058 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 3059 | { |
065f2ec2 CW |
3060 | u32 state; |
3061 | ||
2a307c2e | 3062 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 3063 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 3064 | else |
5efb3e28 | 3065 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
3066 | |
3067 | return state; | |
3068 | } | |
3069 | ||
36cdd013 DW |
3070 | static bool cursor_position(struct drm_i915_private *dev_priv, |
3071 | int pipe, int *x, int *y) | |
065f2ec2 | 3072 | { |
065f2ec2 CW |
3073 | u32 pos; |
3074 | ||
5efb3e28 | 3075 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
3076 | |
3077 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3078 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3079 | *x = -*x; | |
3080 | ||
3081 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3082 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3083 | *y = -*y; | |
3084 | ||
36cdd013 | 3085 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
3086 | } |
3087 | ||
3abc4e09 RF |
3088 | static const char *plane_type(enum drm_plane_type type) |
3089 | { | |
3090 | switch (type) { | |
3091 | case DRM_PLANE_TYPE_OVERLAY: | |
3092 | return "OVL"; | |
3093 | case DRM_PLANE_TYPE_PRIMARY: | |
3094 | return "PRI"; | |
3095 | case DRM_PLANE_TYPE_CURSOR: | |
3096 | return "CUR"; | |
3097 | /* | |
3098 | * Deliberately omitting default: to generate compiler warnings | |
3099 | * when a new drm_plane_type gets added. | |
3100 | */ | |
3101 | } | |
3102 | ||
3103 | return "unknown"; | |
3104 | } | |
3105 | ||
3106 | static const char *plane_rotation(unsigned int rotation) | |
3107 | { | |
3108 | static char buf[48]; | |
3109 | /* | |
3110 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3111 | * will print them all to visualize if the values are misused | |
3112 | */ | |
3113 | snprintf(buf, sizeof(buf), | |
3114 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3115 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3116 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3117 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3118 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3119 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3120 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3121 | rotation); |
3122 | ||
3123 | return buf; | |
3124 | } | |
3125 | ||
3126 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3127 | { | |
36cdd013 DW |
3128 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3129 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3130 | struct intel_plane *intel_plane; |
3131 | ||
3132 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3133 | struct drm_plane_state *state; | |
3134 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3135 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3136 | |
3137 | if (!plane->state) { | |
3138 | seq_puts(m, "plane->state is NULL!\n"); | |
3139 | continue; | |
3140 | } | |
3141 | ||
3142 | state = plane->state; | |
3143 | ||
90844f00 | 3144 | if (state->fb) { |
438b74a5 VS |
3145 | drm_get_format_name(state->fb->format->format, |
3146 | &format_name); | |
90844f00 | 3147 | } else { |
b3c11ac2 | 3148 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3149 | } |
3150 | ||
3abc4e09 RF |
3151 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3152 | plane->base.id, | |
3153 | plane_type(intel_plane->base.type), | |
3154 | state->crtc_x, state->crtc_y, | |
3155 | state->crtc_w, state->crtc_h, | |
3156 | (state->src_x >> 16), | |
3157 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3158 | (state->src_y >> 16), | |
3159 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3160 | (state->src_w >> 16), | |
3161 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3162 | (state->src_h >> 16), | |
3163 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3164 | format_name.str, |
3abc4e09 RF |
3165 | plane_rotation(state->rotation)); |
3166 | } | |
3167 | } | |
3168 | ||
3169 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3170 | { | |
3171 | struct intel_crtc_state *pipe_config; | |
3172 | int num_scalers = intel_crtc->num_scalers; | |
3173 | int i; | |
3174 | ||
3175 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3176 | ||
3177 | /* Not all platformas have a scaler */ | |
3178 | if (num_scalers) { | |
3179 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3180 | num_scalers, | |
3181 | pipe_config->scaler_state.scaler_users, | |
3182 | pipe_config->scaler_state.scaler_id); | |
3183 | ||
58415918 | 3184 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3185 | struct intel_scaler *sc = |
3186 | &pipe_config->scaler_state.scalers[i]; | |
3187 | ||
3188 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3189 | i, yesno(sc->in_use), sc->mode); | |
3190 | } | |
3191 | seq_puts(m, "\n"); | |
3192 | } else { | |
3193 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3194 | } | |
3195 | } | |
3196 | ||
53f5e3ca JB |
3197 | static int i915_display_info(struct seq_file *m, void *unused) |
3198 | { | |
36cdd013 DW |
3199 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3200 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3201 | struct intel_crtc *crtc; |
53f5e3ca JB |
3202 | struct drm_connector *connector; |
3203 | ||
b0e5ddf3 | 3204 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3205 | drm_modeset_lock_all(dev); |
3206 | seq_printf(m, "CRTC info\n"); | |
3207 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3208 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3209 | bool active; |
f77076c9 | 3210 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3211 | int x, y; |
53f5e3ca | 3212 | |
f77076c9 ML |
3213 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3214 | ||
3abc4e09 | 3215 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3216 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3217 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3218 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3219 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3220 | ||
f77076c9 | 3221 | if (pipe_config->base.active) { |
065f2ec2 CW |
3222 | intel_crtc_info(m, crtc); |
3223 | ||
36cdd013 | 3224 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3225 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3226 | yesno(crtc->cursor_base), |
3dd512fb MR |
3227 | x, y, crtc->base.cursor->state->crtc_w, |
3228 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3229 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3230 | intel_scaler_info(m, crtc); |
3231 | intel_plane_info(m, crtc); | |
a23dc658 | 3232 | } |
cace841c DV |
3233 | |
3234 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3235 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3236 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3237 | } |
3238 | ||
3239 | seq_printf(m, "\n"); | |
3240 | seq_printf(m, "Connector info\n"); | |
3241 | seq_printf(m, "--------------\n"); | |
3242 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3243 | intel_connector_info(m, connector); | |
3244 | } | |
3245 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3246 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3247 | |
3248 | return 0; | |
3249 | } | |
3250 | ||
1b36595f CW |
3251 | static int i915_engine_info(struct seq_file *m, void *unused) |
3252 | { | |
3253 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3254 | struct intel_engine_cs *engine; | |
3b3f1650 | 3255 | enum intel_engine_id id; |
1b36595f | 3256 | |
9c870d03 CW |
3257 | intel_runtime_pm_get(dev_priv); |
3258 | ||
f73b5674 CW |
3259 | seq_printf(m, "GT awake? %s\n", |
3260 | yesno(dev_priv->gt.awake)); | |
3261 | seq_printf(m, "Global active requests: %d\n", | |
3262 | dev_priv->gt.active_requests); | |
3263 | ||
3b3f1650 | 3264 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3265 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3266 | struct drm_i915_gem_request *rq; | |
3267 | struct rb_node *rb; | |
3268 | u64 addr; | |
3269 | ||
3270 | seq_printf(m, "%s\n", engine->name); | |
f73b5674 | 3271 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n", |
1b36595f | 3272 | intel_engine_get_seqno(engine), |
cb399eab | 3273 | intel_engine_last_submit(engine), |
1b36595f | 3274 | engine->hangcheck.seqno, |
f73b5674 CW |
3275 | jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp), |
3276 | engine->timeline->inflight_seqnos); | |
1b36595f CW |
3277 | |
3278 | rcu_read_lock(); | |
3279 | ||
3280 | seq_printf(m, "\tRequests:\n"); | |
3281 | ||
73cb9701 CW |
3282 | rq = list_first_entry(&engine->timeline->requests, |
3283 | struct drm_i915_gem_request, link); | |
3284 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3285 | print_request(m, rq, "\t\tfirst "); |
3286 | ||
73cb9701 CW |
3287 | rq = list_last_entry(&engine->timeline->requests, |
3288 | struct drm_i915_gem_request, link); | |
3289 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3290 | print_request(m, rq, "\t\tlast "); |
3291 | ||
3292 | rq = i915_gem_find_active_request(engine); | |
3293 | if (rq) { | |
3294 | print_request(m, rq, "\t\tactive "); | |
3295 | seq_printf(m, | |
3296 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3297 | rq->head, rq->postfix, rq->tail, | |
3298 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3299 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3300 | } | |
3301 | ||
3302 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3303 | I915_READ(RING_START(engine->mmio_base)), | |
3304 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3305 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3306 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3307 | rq ? rq->ring->head : 0); | |
3308 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3309 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3310 | rq ? rq->ring->tail : 0); | |
3311 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3312 | I915_READ(RING_CTL(engine->mmio_base)), | |
3313 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3314 | ||
3315 | rcu_read_unlock(); | |
3316 | ||
3317 | addr = intel_engine_get_active_head(engine); | |
3318 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3319 | upper_32_bits(addr), lower_32_bits(addr)); | |
3320 | addr = intel_engine_get_last_batch_head(engine); | |
3321 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3322 | upper_32_bits(addr), lower_32_bits(addr)); | |
3323 | ||
3324 | if (i915.enable_execlists) { | |
3325 | u32 ptr, read, write; | |
20311bd3 | 3326 | struct rb_node *rb; |
1b36595f CW |
3327 | |
3328 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3329 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3330 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3331 | ||
3332 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3333 | read = GEN8_CSB_READ_PTR(ptr); | |
3334 | write = GEN8_CSB_WRITE_PTR(ptr); | |
3335 | seq_printf(m, "\tExeclist CSB read %d, write %d\n", | |
3336 | read, write); | |
3337 | if (read >= GEN8_CSB_ENTRIES) | |
3338 | read = 0; | |
3339 | if (write >= GEN8_CSB_ENTRIES) | |
3340 | write = 0; | |
3341 | if (read > write) | |
3342 | write += GEN8_CSB_ENTRIES; | |
3343 | while (read < write) { | |
3344 | unsigned int idx = ++read % GEN8_CSB_ENTRIES; | |
3345 | ||
3346 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", | |
3347 | idx, | |
3348 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3349 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3350 | } | |
3351 | ||
3352 | rcu_read_lock(); | |
3353 | rq = READ_ONCE(engine->execlist_port[0].request); | |
816ee798 CW |
3354 | if (rq) { |
3355 | seq_printf(m, "\t\tELSP[0] count=%d, ", | |
3356 | engine->execlist_port[0].count); | |
3357 | print_request(m, rq, "rq: "); | |
3358 | } else { | |
1b36595f | 3359 | seq_printf(m, "\t\tELSP[0] idle\n"); |
816ee798 | 3360 | } |
1b36595f | 3361 | rq = READ_ONCE(engine->execlist_port[1].request); |
816ee798 CW |
3362 | if (rq) { |
3363 | seq_printf(m, "\t\tELSP[1] count=%d, ", | |
3364 | engine->execlist_port[1].count); | |
3365 | print_request(m, rq, "rq: "); | |
3366 | } else { | |
1b36595f | 3367 | seq_printf(m, "\t\tELSP[1] idle\n"); |
816ee798 | 3368 | } |
1b36595f | 3369 | rcu_read_unlock(); |
c8247c06 | 3370 | |
663f71e7 | 3371 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 CW |
3372 | for (rb = engine->execlist_first; rb; rb = rb_next(rb)) { |
3373 | rq = rb_entry(rb, typeof(*rq), priotree.node); | |
c8247c06 CW |
3374 | print_request(m, rq, "\t\tQ "); |
3375 | } | |
663f71e7 | 3376 | spin_unlock_irq(&engine->timeline->lock); |
1b36595f CW |
3377 | } else if (INTEL_GEN(dev_priv) > 6) { |
3378 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3379 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3380 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3381 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3382 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3383 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3384 | } | |
3385 | ||
f6168e33 | 3386 | spin_lock_irq(&b->lock); |
1b36595f | 3387 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 3388 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
1b36595f CW |
3389 | |
3390 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3391 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3392 | } | |
f6168e33 | 3393 | spin_unlock_irq(&b->lock); |
1b36595f CW |
3394 | |
3395 | seq_puts(m, "\n"); | |
3396 | } | |
3397 | ||
9c870d03 CW |
3398 | intel_runtime_pm_put(dev_priv); |
3399 | ||
1b36595f CW |
3400 | return 0; |
3401 | } | |
3402 | ||
e04934cf BW |
3403 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3404 | { | |
36cdd013 DW |
3405 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3406 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3407 | struct intel_engine_cs *engine; |
36cdd013 | 3408 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3409 | enum intel_engine_id id; |
3410 | int j, ret; | |
e04934cf | 3411 | |
39df9190 | 3412 | if (!i915.semaphores) { |
e04934cf BW |
3413 | seq_puts(m, "Semaphores are disabled\n"); |
3414 | return 0; | |
3415 | } | |
3416 | ||
3417 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3418 | if (ret) | |
3419 | return ret; | |
03872064 | 3420 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3421 | |
36cdd013 | 3422 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3423 | struct page *page; |
3424 | uint64_t *seqno; | |
3425 | ||
51d545d0 | 3426 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3427 | |
3428 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3429 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3430 | uint64_t offset; |
3431 | ||
e2f80391 | 3432 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3433 | |
3434 | seq_puts(m, " Last signal:"); | |
3435 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3436 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3437 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3438 | seqno[offset], offset * 8); | |
3439 | } | |
3440 | seq_putc(m, '\n'); | |
3441 | ||
3442 | seq_puts(m, " Last wait: "); | |
3443 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3444 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3445 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3446 | seqno[offset], offset * 8); | |
3447 | } | |
3448 | seq_putc(m, '\n'); | |
3449 | ||
3450 | } | |
3451 | kunmap_atomic(seqno); | |
3452 | } else { | |
3453 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3454 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3455 | for (j = 0; j < num_rings; j++) |
3456 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3457 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3458 | seq_putc(m, '\n'); |
3459 | } | |
3460 | ||
03872064 | 3461 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3462 | mutex_unlock(&dev->struct_mutex); |
3463 | return 0; | |
3464 | } | |
3465 | ||
728e29d7 DV |
3466 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3467 | { | |
36cdd013 DW |
3468 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3469 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3470 | int i; |
3471 | ||
3472 | drm_modeset_lock_all(dev); | |
3473 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3474 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3475 | ||
3476 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3477 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3478 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3479 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3480 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3481 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3482 | pll->state.hw_state.dpll_md); |
3483 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3484 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3485 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3486 | } |
3487 | drm_modeset_unlock_all(dev); | |
3488 | ||
3489 | return 0; | |
3490 | } | |
3491 | ||
1ed1ef9d | 3492 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3493 | { |
3494 | int i; | |
3495 | int ret; | |
e2f80391 | 3496 | struct intel_engine_cs *engine; |
36cdd013 DW |
3497 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3498 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3499 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3500 | enum intel_engine_id id; |
888b5995 | 3501 | |
888b5995 AS |
3502 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3503 | if (ret) | |
3504 | return ret; | |
3505 | ||
3506 | intel_runtime_pm_get(dev_priv); | |
3507 | ||
33136b06 | 3508 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3509 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3510 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3511 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3512 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3513 | i915_reg_t addr; |
3514 | u32 mask, value, read; | |
2fa60f6d | 3515 | bool ok; |
888b5995 | 3516 | |
33136b06 AS |
3517 | addr = workarounds->reg[i].addr; |
3518 | mask = workarounds->reg[i].mask; | |
3519 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3520 | read = I915_READ(addr); |
3521 | ok = (value & mask) == (read & mask); | |
3522 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3523 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3524 | } |
3525 | ||
3526 | intel_runtime_pm_put(dev_priv); | |
3527 | mutex_unlock(&dev->struct_mutex); | |
3528 | ||
3529 | return 0; | |
3530 | } | |
3531 | ||
c5511e44 DL |
3532 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3533 | { | |
36cdd013 DW |
3534 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3535 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3536 | struct skl_ddb_allocation *ddb; |
3537 | struct skl_ddb_entry *entry; | |
3538 | enum pipe pipe; | |
3539 | int plane; | |
3540 | ||
36cdd013 | 3541 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3542 | return 0; |
3543 | ||
c5511e44 DL |
3544 | drm_modeset_lock_all(dev); |
3545 | ||
3546 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3547 | ||
3548 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3549 | ||
3550 | for_each_pipe(dev_priv, pipe) { | |
3551 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3552 | ||
8b364b41 | 3553 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3554 | entry = &ddb->plane[pipe][plane]; |
3555 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3556 | entry->start, entry->end, | |
3557 | skl_ddb_entry_size(entry)); | |
3558 | } | |
3559 | ||
4969d33e | 3560 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3561 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3562 | entry->end, skl_ddb_entry_size(entry)); | |
3563 | } | |
3564 | ||
3565 | drm_modeset_unlock_all(dev); | |
3566 | ||
3567 | return 0; | |
3568 | } | |
3569 | ||
a54746e3 | 3570 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3571 | struct drm_device *dev, |
3572 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3573 | { |
fac5e23e | 3574 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3575 | struct i915_drrs *drrs = &dev_priv->drrs; |
3576 | int vrefresh = 0; | |
26875fe5 | 3577 | struct drm_connector *connector; |
a54746e3 | 3578 | |
26875fe5 ML |
3579 | drm_for_each_connector(connector, dev) { |
3580 | if (connector->state->crtc != &intel_crtc->base) | |
3581 | continue; | |
3582 | ||
3583 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3584 | } |
3585 | ||
3586 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3587 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3588 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3589 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3590 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3591 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3592 | else | |
3593 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3594 | ||
3595 | seq_puts(m, "\n\n"); | |
3596 | ||
f77076c9 | 3597 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3598 | struct intel_panel *panel; |
3599 | ||
3600 | mutex_lock(&drrs->mutex); | |
3601 | /* DRRS Supported */ | |
3602 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3603 | ||
3604 | /* disable_drrs() will make drrs->dp NULL */ | |
3605 | if (!drrs->dp) { | |
3606 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3607 | mutex_unlock(&drrs->mutex); | |
3608 | return; | |
3609 | } | |
3610 | ||
3611 | panel = &drrs->dp->attached_connector->panel; | |
3612 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3613 | drrs->busy_frontbuffer_bits); | |
3614 | ||
3615 | seq_puts(m, "\n\t\t"); | |
3616 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3617 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3618 | vrefresh = panel->fixed_mode->vrefresh; | |
3619 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3620 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3621 | vrefresh = panel->downclock_mode->vrefresh; | |
3622 | } else { | |
3623 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3624 | drrs->refresh_rate_type); | |
3625 | mutex_unlock(&drrs->mutex); | |
3626 | return; | |
3627 | } | |
3628 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3629 | ||
3630 | seq_puts(m, "\n\t\t"); | |
3631 | mutex_unlock(&drrs->mutex); | |
3632 | } else { | |
3633 | /* DRRS not supported. Print the VBT parameter*/ | |
3634 | seq_puts(m, "\tDRRS Supported : No"); | |
3635 | } | |
3636 | seq_puts(m, "\n"); | |
3637 | } | |
3638 | ||
3639 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3640 | { | |
36cdd013 DW |
3641 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3642 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3643 | struct intel_crtc *intel_crtc; |
3644 | int active_crtc_cnt = 0; | |
3645 | ||
26875fe5 | 3646 | drm_modeset_lock_all(dev); |
a54746e3 | 3647 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3648 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3649 | active_crtc_cnt++; |
3650 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3651 | ||
3652 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3653 | } | |
a54746e3 | 3654 | } |
26875fe5 | 3655 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3656 | |
3657 | if (!active_crtc_cnt) | |
3658 | seq_puts(m, "No active crtc found\n"); | |
3659 | ||
3660 | return 0; | |
3661 | } | |
3662 | ||
11bed958 DA |
3663 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3664 | { | |
36cdd013 DW |
3665 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3666 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3667 | struct intel_encoder *intel_encoder; |
3668 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3669 | struct drm_connector *connector; |
3670 | ||
11bed958 | 3671 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3672 | drm_for_each_connector(connector, dev) { |
3673 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3674 | continue; |
b6dabe3b ML |
3675 | |
3676 | intel_encoder = intel_attached_encoder(connector); | |
3677 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3678 | continue; | |
3679 | ||
3680 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3681 | if (!intel_dig_port->dp.can_mst) |
3682 | continue; | |
b6dabe3b | 3683 | |
40ae80cc JB |
3684 | seq_printf(m, "MST Source Port %c\n", |
3685 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3686 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3687 | } | |
3688 | drm_modeset_unlock_all(dev); | |
3689 | return 0; | |
3690 | } | |
3691 | ||
eb3394fa | 3692 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3693 | const char __user *ubuf, |
3694 | size_t len, loff_t *offp) | |
eb3394fa TP |
3695 | { |
3696 | char *input_buffer; | |
3697 | int status = 0; | |
eb3394fa TP |
3698 | struct drm_device *dev; |
3699 | struct drm_connector *connector; | |
3700 | struct list_head *connector_list; | |
3701 | struct intel_dp *intel_dp; | |
3702 | int val = 0; | |
3703 | ||
9aaffa34 | 3704 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3705 | |
eb3394fa TP |
3706 | connector_list = &dev->mode_config.connector_list; |
3707 | ||
3708 | if (len == 0) | |
3709 | return 0; | |
3710 | ||
3711 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
3712 | if (!input_buffer) | |
3713 | return -ENOMEM; | |
3714 | ||
3715 | if (copy_from_user(input_buffer, ubuf, len)) { | |
3716 | status = -EFAULT; | |
3717 | goto out; | |
3718 | } | |
3719 | ||
3720 | input_buffer[len] = '\0'; | |
3721 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
3722 | ||
3723 | list_for_each_entry(connector, connector_list, head) { | |
eb3394fa TP |
3724 | if (connector->connector_type != |
3725 | DRM_MODE_CONNECTOR_DisplayPort) | |
3726 | continue; | |
3727 | ||
b8bb08ec | 3728 | if (connector->status == connector_status_connected && |
eb3394fa TP |
3729 | connector->encoder != NULL) { |
3730 | intel_dp = enc_to_intel_dp(connector->encoder); | |
3731 | status = kstrtoint(input_buffer, 10, &val); | |
3732 | if (status < 0) | |
3733 | goto out; | |
3734 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
3735 | /* To prevent erroneous activation of the compliance | |
3736 | * testing code, only accept an actual value of 1 here | |
3737 | */ | |
3738 | if (val == 1) | |
c1617abc | 3739 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3740 | else |
c1617abc | 3741 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3742 | } |
3743 | } | |
3744 | out: | |
3745 | kfree(input_buffer); | |
3746 | if (status < 0) | |
3747 | return status; | |
3748 | ||
3749 | *offp += len; | |
3750 | return len; | |
3751 | } | |
3752 | ||
3753 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3754 | { | |
3755 | struct drm_device *dev = m->private; | |
3756 | struct drm_connector *connector; | |
3757 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3758 | struct intel_dp *intel_dp; | |
3759 | ||
eb3394fa | 3760 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3761 | if (connector->connector_type != |
3762 | DRM_MODE_CONNECTOR_DisplayPort) | |
3763 | continue; | |
3764 | ||
3765 | if (connector->status == connector_status_connected && | |
3766 | connector->encoder != NULL) { | |
3767 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3768 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3769 | seq_puts(m, "1"); |
3770 | else | |
3771 | seq_puts(m, "0"); | |
3772 | } else | |
3773 | seq_puts(m, "0"); | |
3774 | } | |
3775 | ||
3776 | return 0; | |
3777 | } | |
3778 | ||
3779 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3780 | struct file *file) |
eb3394fa | 3781 | { |
36cdd013 | 3782 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3783 | |
36cdd013 DW |
3784 | return single_open(file, i915_displayport_test_active_show, |
3785 | &dev_priv->drm); | |
eb3394fa TP |
3786 | } |
3787 | ||
3788 | static const struct file_operations i915_displayport_test_active_fops = { | |
3789 | .owner = THIS_MODULE, | |
3790 | .open = i915_displayport_test_active_open, | |
3791 | .read = seq_read, | |
3792 | .llseek = seq_lseek, | |
3793 | .release = single_release, | |
3794 | .write = i915_displayport_test_active_write | |
3795 | }; | |
3796 | ||
3797 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3798 | { | |
3799 | struct drm_device *dev = m->private; | |
3800 | struct drm_connector *connector; | |
3801 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3802 | struct intel_dp *intel_dp; | |
3803 | ||
eb3394fa | 3804 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3805 | if (connector->connector_type != |
3806 | DRM_MODE_CONNECTOR_DisplayPort) | |
3807 | continue; | |
3808 | ||
3809 | if (connector->status == connector_status_connected && | |
3810 | connector->encoder != NULL) { | |
3811 | intel_dp = enc_to_intel_dp(connector->encoder); | |
b48a5ba9 MN |
3812 | if (intel_dp->compliance.test_type == |
3813 | DP_TEST_LINK_EDID_READ) | |
3814 | seq_printf(m, "%lx", | |
3815 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3816 | else if (intel_dp->compliance.test_type == |
3817 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3818 | seq_printf(m, "hdisplay: %d\n", | |
3819 | intel_dp->compliance.test_data.hdisplay); | |
3820 | seq_printf(m, "vdisplay: %d\n", | |
3821 | intel_dp->compliance.test_data.vdisplay); | |
3822 | seq_printf(m, "bpc: %u\n", | |
3823 | intel_dp->compliance.test_data.bpc); | |
3824 | } | |
eb3394fa TP |
3825 | } else |
3826 | seq_puts(m, "0"); | |
3827 | } | |
3828 | ||
3829 | return 0; | |
3830 | } | |
3831 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3832 | struct file *file) |
eb3394fa | 3833 | { |
36cdd013 | 3834 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3835 | |
36cdd013 DW |
3836 | return single_open(file, i915_displayport_test_data_show, |
3837 | &dev_priv->drm); | |
eb3394fa TP |
3838 | } |
3839 | ||
3840 | static const struct file_operations i915_displayport_test_data_fops = { | |
3841 | .owner = THIS_MODULE, | |
3842 | .open = i915_displayport_test_data_open, | |
3843 | .read = seq_read, | |
3844 | .llseek = seq_lseek, | |
3845 | .release = single_release | |
3846 | }; | |
3847 | ||
3848 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3849 | { | |
3850 | struct drm_device *dev = m->private; | |
3851 | struct drm_connector *connector; | |
3852 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3853 | struct intel_dp *intel_dp; | |
3854 | ||
eb3394fa | 3855 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3856 | if (connector->connector_type != |
3857 | DRM_MODE_CONNECTOR_DisplayPort) | |
3858 | continue; | |
3859 | ||
3860 | if (connector->status == connector_status_connected && | |
3861 | connector->encoder != NULL) { | |
3862 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3863 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3864 | } else |
3865 | seq_puts(m, "0"); | |
3866 | } | |
3867 | ||
3868 | return 0; | |
3869 | } | |
3870 | ||
3871 | static int i915_displayport_test_type_open(struct inode *inode, | |
3872 | struct file *file) | |
3873 | { | |
36cdd013 | 3874 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3875 | |
36cdd013 DW |
3876 | return single_open(file, i915_displayport_test_type_show, |
3877 | &dev_priv->drm); | |
eb3394fa TP |
3878 | } |
3879 | ||
3880 | static const struct file_operations i915_displayport_test_type_fops = { | |
3881 | .owner = THIS_MODULE, | |
3882 | .open = i915_displayport_test_type_open, | |
3883 | .read = seq_read, | |
3884 | .llseek = seq_lseek, | |
3885 | .release = single_release | |
3886 | }; | |
3887 | ||
97e94b22 | 3888 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3889 | { |
36cdd013 DW |
3890 | struct drm_i915_private *dev_priv = m->private; |
3891 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3892 | int level; |
de38b95c VS |
3893 | int num_levels; |
3894 | ||
36cdd013 | 3895 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3896 | num_levels = 3; |
36cdd013 | 3897 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
3898 | num_levels = 1; |
3899 | else | |
5db94019 | 3900 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3901 | |
3902 | drm_modeset_lock_all(dev); | |
3903 | ||
3904 | for (level = 0; level < num_levels; level++) { | |
3905 | unsigned int latency = wm[level]; | |
3906 | ||
97e94b22 DL |
3907 | /* |
3908 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3909 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3910 | */ |
36cdd013 DW |
3911 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
3912 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
3913 | latency *= 10; |
3914 | else if (level > 0) | |
369a1342 VS |
3915 | latency *= 5; |
3916 | ||
3917 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3918 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3919 | } |
3920 | ||
3921 | drm_modeset_unlock_all(dev); | |
3922 | } | |
3923 | ||
3924 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3925 | { | |
36cdd013 | 3926 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3927 | const uint16_t *latencies; |
3928 | ||
36cdd013 | 3929 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3930 | latencies = dev_priv->wm.skl_latency; |
3931 | else | |
36cdd013 | 3932 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3933 | |
97e94b22 | 3934 | wm_latency_show(m, latencies); |
369a1342 VS |
3935 | |
3936 | return 0; | |
3937 | } | |
3938 | ||
3939 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3940 | { | |
36cdd013 | 3941 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3942 | const uint16_t *latencies; |
3943 | ||
36cdd013 | 3944 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3945 | latencies = dev_priv->wm.skl_latency; |
3946 | else | |
36cdd013 | 3947 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3948 | |
97e94b22 | 3949 | wm_latency_show(m, latencies); |
369a1342 VS |
3950 | |
3951 | return 0; | |
3952 | } | |
3953 | ||
3954 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3955 | { | |
36cdd013 | 3956 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3957 | const uint16_t *latencies; |
3958 | ||
36cdd013 | 3959 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3960 | latencies = dev_priv->wm.skl_latency; |
3961 | else | |
36cdd013 | 3962 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3963 | |
97e94b22 | 3964 | wm_latency_show(m, latencies); |
369a1342 VS |
3965 | |
3966 | return 0; | |
3967 | } | |
3968 | ||
3969 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3970 | { | |
36cdd013 | 3971 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3972 | |
36cdd013 | 3973 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
3974 | return -ENODEV; |
3975 | ||
36cdd013 | 3976 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3977 | } |
3978 | ||
3979 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3980 | { | |
36cdd013 | 3981 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3982 | |
36cdd013 | 3983 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3984 | return -ENODEV; |
3985 | ||
36cdd013 | 3986 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3987 | } |
3988 | ||
3989 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3990 | { | |
36cdd013 | 3991 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3992 | |
36cdd013 | 3993 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3994 | return -ENODEV; |
3995 | ||
36cdd013 | 3996 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3997 | } |
3998 | ||
3999 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4000 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4001 | { |
4002 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
4003 | struct drm_i915_private *dev_priv = m->private; |
4004 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 4005 | uint16_t new[8] = { 0 }; |
de38b95c | 4006 | int num_levels; |
369a1342 VS |
4007 | int level; |
4008 | int ret; | |
4009 | char tmp[32]; | |
4010 | ||
36cdd013 | 4011 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4012 | num_levels = 3; |
36cdd013 | 4013 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4014 | num_levels = 1; |
4015 | else | |
5db94019 | 4016 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 4017 | |
369a1342 VS |
4018 | if (len >= sizeof(tmp)) |
4019 | return -EINVAL; | |
4020 | ||
4021 | if (copy_from_user(tmp, ubuf, len)) | |
4022 | return -EFAULT; | |
4023 | ||
4024 | tmp[len] = '\0'; | |
4025 | ||
97e94b22 DL |
4026 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4027 | &new[0], &new[1], &new[2], &new[3], | |
4028 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4029 | if (ret != num_levels) |
4030 | return -EINVAL; | |
4031 | ||
4032 | drm_modeset_lock_all(dev); | |
4033 | ||
4034 | for (level = 0; level < num_levels; level++) | |
4035 | wm[level] = new[level]; | |
4036 | ||
4037 | drm_modeset_unlock_all(dev); | |
4038 | ||
4039 | return len; | |
4040 | } | |
4041 | ||
4042 | ||
4043 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4044 | size_t len, loff_t *offp) | |
4045 | { | |
4046 | struct seq_file *m = file->private_data; | |
36cdd013 | 4047 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4048 | uint16_t *latencies; |
369a1342 | 4049 | |
36cdd013 | 4050 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4051 | latencies = dev_priv->wm.skl_latency; |
4052 | else | |
36cdd013 | 4053 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4054 | |
4055 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4056 | } |
4057 | ||
4058 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4059 | size_t len, loff_t *offp) | |
4060 | { | |
4061 | struct seq_file *m = file->private_data; | |
36cdd013 | 4062 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4063 | uint16_t *latencies; |
369a1342 | 4064 | |
36cdd013 | 4065 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4066 | latencies = dev_priv->wm.skl_latency; |
4067 | else | |
36cdd013 | 4068 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4069 | |
4070 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4071 | } |
4072 | ||
4073 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4074 | size_t len, loff_t *offp) | |
4075 | { | |
4076 | struct seq_file *m = file->private_data; | |
36cdd013 | 4077 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4078 | uint16_t *latencies; |
4079 | ||
36cdd013 | 4080 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4081 | latencies = dev_priv->wm.skl_latency; |
4082 | else | |
36cdd013 | 4083 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4084 | |
97e94b22 | 4085 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4086 | } |
4087 | ||
4088 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4089 | .owner = THIS_MODULE, | |
4090 | .open = pri_wm_latency_open, | |
4091 | .read = seq_read, | |
4092 | .llseek = seq_lseek, | |
4093 | .release = single_release, | |
4094 | .write = pri_wm_latency_write | |
4095 | }; | |
4096 | ||
4097 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4098 | .owner = THIS_MODULE, | |
4099 | .open = spr_wm_latency_open, | |
4100 | .read = seq_read, | |
4101 | .llseek = seq_lseek, | |
4102 | .release = single_release, | |
4103 | .write = spr_wm_latency_write | |
4104 | }; | |
4105 | ||
4106 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4107 | .owner = THIS_MODULE, | |
4108 | .open = cur_wm_latency_open, | |
4109 | .read = seq_read, | |
4110 | .llseek = seq_lseek, | |
4111 | .release = single_release, | |
4112 | .write = cur_wm_latency_write | |
4113 | }; | |
4114 | ||
647416f9 KC |
4115 | static int |
4116 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4117 | { |
36cdd013 | 4118 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4119 | |
d98c52cf | 4120 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4121 | |
647416f9 | 4122 | return 0; |
f3cd474b CW |
4123 | } |
4124 | ||
647416f9 KC |
4125 | static int |
4126 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4127 | { |
36cdd013 | 4128 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 4129 | |
b8d24a06 MK |
4130 | /* |
4131 | * There is no safeguard against this debugfs entry colliding | |
4132 | * with the hangcheck calling same i915_handle_error() in | |
4133 | * parallel, causing an explosion. For now we assume that the | |
4134 | * test harness is responsible enough not to inject gpu hangs | |
4135 | * while it is writing to 'i915_wedged' | |
4136 | */ | |
4137 | ||
d98c52cf | 4138 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4139 | return -EAGAIN; |
4140 | ||
c033666a | 4141 | i915_handle_error(dev_priv, val, |
58174462 | 4142 | "Manually setting wedged to %llu", val); |
d46c0517 | 4143 | |
647416f9 | 4144 | return 0; |
f3cd474b CW |
4145 | } |
4146 | ||
647416f9 KC |
4147 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4148 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4149 | "%llu\n"); |
f3cd474b | 4150 | |
094f9a54 CW |
4151 | static int |
4152 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4153 | { | |
36cdd013 | 4154 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4155 | |
4156 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4157 | return 0; | |
4158 | } | |
4159 | ||
4160 | static int | |
4161 | i915_ring_missed_irq_set(void *data, u64 val) | |
4162 | { | |
36cdd013 DW |
4163 | struct drm_i915_private *dev_priv = data; |
4164 | struct drm_device *dev = &dev_priv->drm; | |
094f9a54 CW |
4165 | int ret; |
4166 | ||
4167 | /* Lock against concurrent debugfs callers */ | |
4168 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4169 | if (ret) | |
4170 | return ret; | |
4171 | dev_priv->gpu_error.missed_irq_rings = val; | |
4172 | mutex_unlock(&dev->struct_mutex); | |
4173 | ||
4174 | return 0; | |
4175 | } | |
4176 | ||
4177 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4178 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4179 | "0x%08llx\n"); | |
4180 | ||
4181 | static int | |
4182 | i915_ring_test_irq_get(void *data, u64 *val) | |
4183 | { | |
36cdd013 | 4184 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4185 | |
4186 | *val = dev_priv->gpu_error.test_irq_rings; | |
4187 | ||
4188 | return 0; | |
4189 | } | |
4190 | ||
4191 | static int | |
4192 | i915_ring_test_irq_set(void *data, u64 val) | |
4193 | { | |
36cdd013 | 4194 | struct drm_i915_private *dev_priv = data; |
094f9a54 | 4195 | |
3a122c27 | 4196 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4197 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4198 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4199 | |
4200 | return 0; | |
4201 | } | |
4202 | ||
4203 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4204 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4205 | "0x%08llx\n"); | |
4206 | ||
dd624afd CW |
4207 | #define DROP_UNBOUND 0x1 |
4208 | #define DROP_BOUND 0x2 | |
4209 | #define DROP_RETIRE 0x4 | |
4210 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 CW |
4211 | #define DROP_FREED 0x10 |
4212 | #define DROP_ALL (DROP_UNBOUND | \ | |
4213 | DROP_BOUND | \ | |
4214 | DROP_RETIRE | \ | |
4215 | DROP_ACTIVE | \ | |
4216 | DROP_FREED) | |
647416f9 KC |
4217 | static int |
4218 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4219 | { |
647416f9 | 4220 | *val = DROP_ALL; |
dd624afd | 4221 | |
647416f9 | 4222 | return 0; |
dd624afd CW |
4223 | } |
4224 | ||
647416f9 KC |
4225 | static int |
4226 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4227 | { |
36cdd013 DW |
4228 | struct drm_i915_private *dev_priv = data; |
4229 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4230 | int ret; |
dd624afd | 4231 | |
2f9fe5ff | 4232 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4233 | |
4234 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4235 | * on ioctls on -EAGAIN. */ | |
4236 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4237 | if (ret) | |
4238 | return ret; | |
4239 | ||
4240 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4241 | ret = i915_gem_wait_for_idle(dev_priv, |
4242 | I915_WAIT_INTERRUPTIBLE | | |
4243 | I915_WAIT_LOCKED); | |
dd624afd CW |
4244 | if (ret) |
4245 | goto unlock; | |
4246 | } | |
4247 | ||
4248 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4249 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4250 | |
21ab4e74 CW |
4251 | if (val & DROP_BOUND) |
4252 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4253 | |
21ab4e74 CW |
4254 | if (val & DROP_UNBOUND) |
4255 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4256 | |
4257 | unlock: | |
4258 | mutex_unlock(&dev->struct_mutex); | |
4259 | ||
fbbd37b3 CW |
4260 | if (val & DROP_FREED) { |
4261 | synchronize_rcu(); | |
bdeb9785 | 4262 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4263 | } |
4264 | ||
647416f9 | 4265 | return ret; |
dd624afd CW |
4266 | } |
4267 | ||
647416f9 KC |
4268 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4269 | i915_drop_caches_get, i915_drop_caches_set, | |
4270 | "0x%08llx\n"); | |
dd624afd | 4271 | |
647416f9 KC |
4272 | static int |
4273 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4274 | { |
36cdd013 | 4275 | struct drm_i915_private *dev_priv = data; |
004777cb | 4276 | |
36cdd013 | 4277 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4278 | return -ENODEV; |
4279 | ||
7c59a9c1 | 4280 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4281 | return 0; |
358733e9 JB |
4282 | } |
4283 | ||
647416f9 KC |
4284 | static int |
4285 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4286 | { |
36cdd013 | 4287 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4288 | u32 hw_max, hw_min; |
647416f9 | 4289 | int ret; |
004777cb | 4290 | |
36cdd013 | 4291 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4292 | return -ENODEV; |
358733e9 | 4293 | |
647416f9 | 4294 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4295 | |
4fc688ce | 4296 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4297 | if (ret) |
4298 | return ret; | |
4299 | ||
358733e9 JB |
4300 | /* |
4301 | * Turbo will still be enabled, but won't go above the set value. | |
4302 | */ | |
bc4d91f6 | 4303 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4304 | |
bc4d91f6 AG |
4305 | hw_max = dev_priv->rps.max_freq; |
4306 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4307 | |
b39fb297 | 4308 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4309 | mutex_unlock(&dev_priv->rps.hw_lock); |
4310 | return -EINVAL; | |
0a073b84 JB |
4311 | } |
4312 | ||
b39fb297 | 4313 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4314 | |
9fcee2f7 CW |
4315 | if (intel_set_rps(dev_priv, val)) |
4316 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4317 | |
4fc688ce | 4318 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4319 | |
647416f9 | 4320 | return 0; |
358733e9 JB |
4321 | } |
4322 | ||
647416f9 KC |
4323 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4324 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4325 | "%llu\n"); |
358733e9 | 4326 | |
647416f9 KC |
4327 | static int |
4328 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4329 | { |
36cdd013 | 4330 | struct drm_i915_private *dev_priv = data; |
004777cb | 4331 | |
62e1baa1 | 4332 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4333 | return -ENODEV; |
4334 | ||
7c59a9c1 | 4335 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4336 | return 0; |
1523c310 JB |
4337 | } |
4338 | ||
647416f9 KC |
4339 | static int |
4340 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4341 | { |
36cdd013 | 4342 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4343 | u32 hw_max, hw_min; |
647416f9 | 4344 | int ret; |
004777cb | 4345 | |
62e1baa1 | 4346 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4347 | return -ENODEV; |
1523c310 | 4348 | |
647416f9 | 4349 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4350 | |
4fc688ce | 4351 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4352 | if (ret) |
4353 | return ret; | |
4354 | ||
1523c310 JB |
4355 | /* |
4356 | * Turbo will still be enabled, but won't go below the set value. | |
4357 | */ | |
bc4d91f6 | 4358 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4359 | |
bc4d91f6 AG |
4360 | hw_max = dev_priv->rps.max_freq; |
4361 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4362 | |
36cdd013 DW |
4363 | if (val < hw_min || |
4364 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4365 | mutex_unlock(&dev_priv->rps.hw_lock); |
4366 | return -EINVAL; | |
0a073b84 | 4367 | } |
dd0a1aa1 | 4368 | |
b39fb297 | 4369 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4370 | |
9fcee2f7 CW |
4371 | if (intel_set_rps(dev_priv, val)) |
4372 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4373 | |
4fc688ce | 4374 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4375 | |
647416f9 | 4376 | return 0; |
1523c310 JB |
4377 | } |
4378 | ||
647416f9 KC |
4379 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4380 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4381 | "%llu\n"); |
1523c310 | 4382 | |
647416f9 KC |
4383 | static int |
4384 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4385 | { |
36cdd013 | 4386 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4387 | u32 snpcr; |
07b7ddd9 | 4388 | |
36cdd013 | 4389 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4390 | return -ENODEV; |
4391 | ||
c8c8fb33 | 4392 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4393 | |
07b7ddd9 | 4394 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4395 | |
4396 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4397 | |
647416f9 | 4398 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4399 | |
647416f9 | 4400 | return 0; |
07b7ddd9 JB |
4401 | } |
4402 | ||
647416f9 KC |
4403 | static int |
4404 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4405 | { |
36cdd013 | 4406 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4407 | u32 snpcr; |
07b7ddd9 | 4408 | |
36cdd013 | 4409 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4410 | return -ENODEV; |
4411 | ||
647416f9 | 4412 | if (val > 3) |
07b7ddd9 JB |
4413 | return -EINVAL; |
4414 | ||
c8c8fb33 | 4415 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4416 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4417 | |
4418 | /* Update the cache sharing policy here as well */ | |
4419 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4420 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4421 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4422 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4423 | ||
c8c8fb33 | 4424 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4425 | return 0; |
07b7ddd9 JB |
4426 | } |
4427 | ||
647416f9 KC |
4428 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4429 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4430 | "%llu\n"); | |
07b7ddd9 | 4431 | |
36cdd013 | 4432 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4433 | struct sseu_dev_info *sseu) |
5d39525a | 4434 | { |
0a0b457f | 4435 | int ss_max = 2; |
5d39525a JM |
4436 | int ss; |
4437 | u32 sig1[ss_max], sig2[ss_max]; | |
4438 | ||
4439 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4440 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4441 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4442 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4443 | ||
4444 | for (ss = 0; ss < ss_max; ss++) { | |
4445 | unsigned int eu_cnt; | |
4446 | ||
4447 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4448 | /* skip disabled subslice */ | |
4449 | continue; | |
4450 | ||
f08a0c92 | 4451 | sseu->slice_mask = BIT(0); |
57ec171e | 4452 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4453 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4454 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4455 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4456 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4457 | sseu->eu_total += eu_cnt; |
4458 | sseu->eu_per_subslice = max_t(unsigned int, | |
4459 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4460 | } |
5d39525a JM |
4461 | } |
4462 | ||
36cdd013 | 4463 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4464 | struct sseu_dev_info *sseu) |
5d39525a | 4465 | { |
1c046bc1 | 4466 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4467 | int s, ss; |
4468 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4469 | ||
1c046bc1 | 4470 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4471 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4472 | s_max = 1; |
4473 | ss_max = 3; | |
4474 | } | |
4475 | ||
4476 | for (s = 0; s < s_max; s++) { | |
4477 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4478 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4479 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4480 | } | |
4481 | ||
5d39525a JM |
4482 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4483 | GEN9_PGCTL_SSA_EU19_ACK | | |
4484 | GEN9_PGCTL_SSA_EU210_ACK | | |
4485 | GEN9_PGCTL_SSA_EU311_ACK; | |
4486 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4487 | GEN9_PGCTL_SSB_EU19_ACK | | |
4488 | GEN9_PGCTL_SSB_EU210_ACK | | |
4489 | GEN9_PGCTL_SSB_EU311_ACK; | |
4490 | ||
4491 | for (s = 0; s < s_max; s++) { | |
4492 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4493 | /* skip disabled slice */ | |
4494 | continue; | |
4495 | ||
f08a0c92 | 4496 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4497 | |
b976dc53 | 4498 | if (IS_GEN9_BC(dev_priv)) |
57ec171e ID |
4499 | sseu->subslice_mask = |
4500 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4501 | |
5d39525a JM |
4502 | for (ss = 0; ss < ss_max; ss++) { |
4503 | unsigned int eu_cnt; | |
4504 | ||
cc3f90f0 | 4505 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4506 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4507 | /* skip disabled subslice */ | |
4508 | continue; | |
1c046bc1 | 4509 | |
57ec171e ID |
4510 | sseu->subslice_mask |= BIT(ss); |
4511 | } | |
1c046bc1 | 4512 | |
5d39525a JM |
4513 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4514 | eu_mask[ss%2]); | |
915490d5 ID |
4515 | sseu->eu_total += eu_cnt; |
4516 | sseu->eu_per_subslice = max_t(unsigned int, | |
4517 | sseu->eu_per_subslice, | |
4518 | eu_cnt); | |
5d39525a JM |
4519 | } |
4520 | } | |
4521 | } | |
4522 | ||
36cdd013 | 4523 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4524 | struct sseu_dev_info *sseu) |
91bedd34 | 4525 | { |
91bedd34 | 4526 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4527 | int s; |
91bedd34 | 4528 | |
f08a0c92 | 4529 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4530 | |
f08a0c92 | 4531 | if (sseu->slice_mask) { |
57ec171e | 4532 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4533 | sseu->eu_per_subslice = |
4534 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4535 | sseu->eu_total = sseu->eu_per_subslice * |
4536 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4537 | |
4538 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4539 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4540 | u8 subslice_7eu = |
4541 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4542 | |
915490d5 | 4543 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4544 | } |
4545 | } | |
4546 | } | |
4547 | ||
615d8908 ID |
4548 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4549 | const struct sseu_dev_info *sseu) | |
4550 | { | |
4551 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4552 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4553 | ||
c67ba538 ID |
4554 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4555 | sseu->slice_mask); | |
615d8908 | 4556 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4557 | hweight8(sseu->slice_mask)); |
615d8908 | 4558 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4559 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4560 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4561 | sseu->subslice_mask); | |
615d8908 | 4562 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4563 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4564 | seq_printf(m, " %s EU Total: %u\n", type, |
4565 | sseu->eu_total); | |
4566 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4567 | sseu->eu_per_subslice); | |
4568 | ||
4569 | if (!is_available_info) | |
4570 | return; | |
4571 | ||
4572 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4573 | if (HAS_POOLED_EU(dev_priv)) | |
4574 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4575 | ||
4576 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4577 | yesno(sseu->has_slice_pg)); | |
4578 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4579 | yesno(sseu->has_subslice_pg)); | |
4580 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4581 | yesno(sseu->has_eu_pg)); | |
4582 | } | |
4583 | ||
3873218f JM |
4584 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4585 | { | |
36cdd013 | 4586 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4587 | struct sseu_dev_info sseu; |
3873218f | 4588 | |
36cdd013 | 4589 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4590 | return -ENODEV; |
4591 | ||
4592 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4593 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4594 | |
7f992aba | 4595 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4596 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4597 | |
4598 | intel_runtime_pm_get(dev_priv); | |
4599 | ||
36cdd013 | 4600 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4601 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4602 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4603 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4604 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 4605 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 4606 | } |
238010ed DW |
4607 | |
4608 | intel_runtime_pm_put(dev_priv); | |
4609 | ||
615d8908 | 4610 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4611 | |
3873218f JM |
4612 | return 0; |
4613 | } | |
4614 | ||
6d794d42 BW |
4615 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4616 | { | |
36cdd013 | 4617 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4618 | |
36cdd013 | 4619 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4620 | return 0; |
4621 | ||
6daccb0b | 4622 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4623 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4624 | |
4625 | return 0; | |
4626 | } | |
4627 | ||
c43b5634 | 4628 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4629 | { |
36cdd013 | 4630 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4631 | |
36cdd013 | 4632 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4633 | return 0; |
4634 | ||
59bad947 | 4635 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4636 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4637 | |
4638 | return 0; | |
4639 | } | |
4640 | ||
4641 | static const struct file_operations i915_forcewake_fops = { | |
4642 | .owner = THIS_MODULE, | |
4643 | .open = i915_forcewake_open, | |
4644 | .release = i915_forcewake_release, | |
4645 | }; | |
4646 | ||
4647 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
4648 | { | |
6d794d42 BW |
4649 | struct dentry *ent; |
4650 | ||
4651 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 4652 | S_IRUSR, |
36cdd013 | 4653 | root, to_i915(minor->dev), |
6d794d42 | 4654 | &i915_forcewake_fops); |
f3c5fe97 WY |
4655 | if (!ent) |
4656 | return -ENOMEM; | |
6d794d42 | 4657 | |
8eb57294 | 4658 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
4659 | } |
4660 | ||
317eaa95 L |
4661 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4662 | { | |
4663 | struct drm_i915_private *dev_priv = m->private; | |
4664 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4665 | ||
4666 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4667 | seq_printf(m, "Detected: %s\n", | |
4668 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4669 | ||
4670 | return 0; | |
4671 | } | |
4672 | ||
4673 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4674 | const char __user *ubuf, size_t len, | |
4675 | loff_t *offp) | |
4676 | { | |
4677 | struct seq_file *m = file->private_data; | |
4678 | struct drm_i915_private *dev_priv = m->private; | |
4679 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4680 | unsigned int new_threshold; | |
4681 | int i; | |
4682 | char *newline; | |
4683 | char tmp[16]; | |
4684 | ||
4685 | if (len >= sizeof(tmp)) | |
4686 | return -EINVAL; | |
4687 | ||
4688 | if (copy_from_user(tmp, ubuf, len)) | |
4689 | return -EFAULT; | |
4690 | ||
4691 | tmp[len] = '\0'; | |
4692 | ||
4693 | /* Strip newline, if any */ | |
4694 | newline = strchr(tmp, '\n'); | |
4695 | if (newline) | |
4696 | *newline = '\0'; | |
4697 | ||
4698 | if (strcmp(tmp, "reset") == 0) | |
4699 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4700 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4701 | return -EINVAL; | |
4702 | ||
4703 | if (new_threshold > 0) | |
4704 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4705 | new_threshold); | |
4706 | else | |
4707 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4708 | ||
4709 | spin_lock_irq(&dev_priv->irq_lock); | |
4710 | hotplug->hpd_storm_threshold = new_threshold; | |
4711 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4712 | for_each_hpd_pin(i) | |
4713 | hotplug->stats[i].count = 0; | |
4714 | spin_unlock_irq(&dev_priv->irq_lock); | |
4715 | ||
4716 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4717 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4718 | ||
4719 | return len; | |
4720 | } | |
4721 | ||
4722 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4723 | { | |
4724 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4725 | } | |
4726 | ||
4727 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4728 | .owner = THIS_MODULE, | |
4729 | .open = i915_hpd_storm_ctl_open, | |
4730 | .read = seq_read, | |
4731 | .llseek = seq_lseek, | |
4732 | .release = single_release, | |
4733 | .write = i915_hpd_storm_ctl_write | |
4734 | }; | |
4735 | ||
6a9c308d DV |
4736 | static int i915_debugfs_create(struct dentry *root, |
4737 | struct drm_minor *minor, | |
4738 | const char *name, | |
4739 | const struct file_operations *fops) | |
07b7ddd9 | 4740 | { |
07b7ddd9 JB |
4741 | struct dentry *ent; |
4742 | ||
6a9c308d | 4743 | ent = debugfs_create_file(name, |
07b7ddd9 | 4744 | S_IRUGO | S_IWUSR, |
36cdd013 | 4745 | root, to_i915(minor->dev), |
6a9c308d | 4746 | fops); |
f3c5fe97 WY |
4747 | if (!ent) |
4748 | return -ENOMEM; | |
07b7ddd9 | 4749 | |
6a9c308d | 4750 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
4751 | } |
4752 | ||
06c5bf8c | 4753 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4754 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4755 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4756 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 4757 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 4758 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 4759 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
4760 | {"i915_gem_request", i915_gem_request_info, 0}, |
4761 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4762 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4763 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4764 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4765 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4766 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4767 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
0509ead1 | 4768 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4769 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4770 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 4771 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4772 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4773 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4774 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4775 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4776 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4777 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4778 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4779 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4780 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4781 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4782 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 4783 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4784 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4785 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4786 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4787 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4788 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4789 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4790 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4791 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4792 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4793 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4794 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 4795 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4796 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4797 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4798 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4799 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4800 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4801 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4802 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4803 | }; |
27c202ad | 4804 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4805 | |
06c5bf8c | 4806 | static const struct i915_debugfs_files { |
34b9674c DV |
4807 | const char *name; |
4808 | const struct file_operations *fops; | |
4809 | } i915_debugfs_files[] = { | |
4810 | {"i915_wedged", &i915_wedged_fops}, | |
4811 | {"i915_max_freq", &i915_max_freq_fops}, | |
4812 | {"i915_min_freq", &i915_min_freq_fops}, | |
4813 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4814 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4815 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4816 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4817 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4818 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4819 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4820 | #endif |
34b9674c | 4821 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4822 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4823 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4824 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4825 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4826 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
4827 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4828 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4829 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
317eaa95 L |
4830 | {"i915_guc_log_control", &i915_guc_log_control_fops}, |
4831 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops} | |
34b9674c DV |
4832 | }; |
4833 | ||
1dac891c | 4834 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4835 | { |
91c8a326 | 4836 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 4837 | int ret, i; |
f3cd474b | 4838 | |
6d794d42 | 4839 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
4840 | if (ret) |
4841 | return ret; | |
6a9c308d | 4842 | |
731035fe TV |
4843 | ret = intel_pipe_crc_create(minor); |
4844 | if (ret) | |
4845 | return ret; | |
07144428 | 4846 | |
34b9674c DV |
4847 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4848 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
4849 | i915_debugfs_files[i].name, | |
4850 | i915_debugfs_files[i].fops); | |
4851 | if (ret) | |
4852 | return ret; | |
4853 | } | |
40633219 | 4854 | |
27c202ad BG |
4855 | return drm_debugfs_create_files(i915_debugfs_list, |
4856 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4857 | minor->debugfs_root, minor); |
4858 | } | |
4859 | ||
1dac891c | 4860 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 4861 | { |
91c8a326 | 4862 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
4863 | int i; |
4864 | ||
27c202ad BG |
4865 | drm_debugfs_remove_files(i915_debugfs_list, |
4866 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 4867 | |
36cdd013 | 4868 | drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, |
6d794d42 | 4869 | 1, minor); |
07144428 | 4870 | |
731035fe | 4871 | intel_pipe_crc_cleanup(minor); |
07144428 | 4872 | |
34b9674c DV |
4873 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4874 | struct drm_info_list *info_list = | |
36cdd013 | 4875 | (struct drm_info_list *)i915_debugfs_files[i].fops; |
34b9674c DV |
4876 | |
4877 | drm_debugfs_remove_files(info_list, 1, minor); | |
4878 | } | |
2017263e | 4879 | } |
aa7471d2 JN |
4880 | |
4881 | struct dpcd_block { | |
4882 | /* DPCD dump start address. */ | |
4883 | unsigned int offset; | |
4884 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4885 | unsigned int end; | |
4886 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4887 | size_t size; | |
4888 | /* Only valid for eDP. */ | |
4889 | bool edp; | |
4890 | }; | |
4891 | ||
4892 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4893 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4894 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4895 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4896 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4897 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4898 | { .offset = DP_SET_POWER }, | |
4899 | { .offset = DP_EDP_DPCD_REV }, | |
4900 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4901 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4902 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4903 | }; | |
4904 | ||
4905 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4906 | { | |
4907 | struct drm_connector *connector = m->private; | |
4908 | struct intel_dp *intel_dp = | |
4909 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4910 | uint8_t buf[16]; | |
4911 | ssize_t err; | |
4912 | int i; | |
4913 | ||
5c1a8875 MK |
4914 | if (connector->status != connector_status_connected) |
4915 | return -ENODEV; | |
4916 | ||
aa7471d2 JN |
4917 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4918 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4919 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4920 | ||
4921 | if (b->edp && | |
4922 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4923 | continue; | |
4924 | ||
4925 | /* low tech for now */ | |
4926 | if (WARN_ON(size > sizeof(buf))) | |
4927 | continue; | |
4928 | ||
4929 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4930 | if (err <= 0) { | |
4931 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4932 | size, b->offset, err); | |
4933 | continue; | |
4934 | } | |
4935 | ||
4936 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4937 | } |
aa7471d2 JN |
4938 | |
4939 | return 0; | |
4940 | } | |
4941 | ||
4942 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4943 | { | |
4944 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4945 | } | |
4946 | ||
4947 | static const struct file_operations i915_dpcd_fops = { | |
4948 | .owner = THIS_MODULE, | |
4949 | .open = i915_dpcd_open, | |
4950 | .read = seq_read, | |
4951 | .llseek = seq_lseek, | |
4952 | .release = single_release, | |
4953 | }; | |
4954 | ||
ecbd6781 DW |
4955 | static int i915_panel_show(struct seq_file *m, void *data) |
4956 | { | |
4957 | struct drm_connector *connector = m->private; | |
4958 | struct intel_dp *intel_dp = | |
4959 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4960 | ||
4961 | if (connector->status != connector_status_connected) | |
4962 | return -ENODEV; | |
4963 | ||
4964 | seq_printf(m, "Panel power up delay: %d\n", | |
4965 | intel_dp->panel_power_up_delay); | |
4966 | seq_printf(m, "Panel power down delay: %d\n", | |
4967 | intel_dp->panel_power_down_delay); | |
4968 | seq_printf(m, "Backlight on delay: %d\n", | |
4969 | intel_dp->backlight_on_delay); | |
4970 | seq_printf(m, "Backlight off delay: %d\n", | |
4971 | intel_dp->backlight_off_delay); | |
4972 | ||
4973 | return 0; | |
4974 | } | |
4975 | ||
4976 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4977 | { | |
4978 | return single_open(file, i915_panel_show, inode->i_private); | |
4979 | } | |
4980 | ||
4981 | static const struct file_operations i915_panel_fops = { | |
4982 | .owner = THIS_MODULE, | |
4983 | .open = i915_panel_open, | |
4984 | .read = seq_read, | |
4985 | .llseek = seq_lseek, | |
4986 | .release = single_release, | |
4987 | }; | |
4988 | ||
aa7471d2 JN |
4989 | /** |
4990 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4991 | * @connector: pointer to a registered drm_connector | |
4992 | * | |
4993 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4994 | * drm_debugfs_connector_remove(). | |
4995 | * | |
4996 | * Returns 0 on success, negative error codes on error. | |
4997 | */ | |
4998 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4999 | { | |
5000 | struct dentry *root = connector->debugfs_entry; | |
5001 | ||
5002 | /* The connector must have been registered beforehands. */ | |
5003 | if (!root) | |
5004 | return -ENODEV; | |
5005 | ||
5006 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5007 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
5008 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
5009 | connector, &i915_dpcd_fops); | |
5010 | ||
5011 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5012 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
5013 | connector, &i915_panel_fops); | |
aa7471d2 JN |
5014 | |
5015 | return 0; | |
5016 | } |