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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
e637d2cb | 30 | #include <linux/sort.h> |
4e5359cd | 31 | #include "intel_drv.h" |
2017263e | 32 | |
36cdd013 DW |
33 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
34 | { | |
35 | return to_i915(node->minor->dev); | |
36 | } | |
37 | ||
418e3cd8 CW |
38 | static __always_inline void seq_print_param(struct seq_file *m, |
39 | const char *name, | |
40 | const char *type, | |
41 | const void *x) | |
42 | { | |
43 | if (!__builtin_strcmp(type, "bool")) | |
44 | seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x)); | |
45 | else if (!__builtin_strcmp(type, "int")) | |
46 | seq_printf(m, "i915.%s=%d\n", name, *(const int *)x); | |
47 | else if (!__builtin_strcmp(type, "unsigned int")) | |
48 | seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x); | |
1d6aa7a3 CW |
49 | else if (!__builtin_strcmp(type, "char *")) |
50 | seq_printf(m, "i915.%s=%s\n", name, *(const char **)x); | |
418e3cd8 CW |
51 | else |
52 | BUILD_BUG(); | |
53 | } | |
54 | ||
70d39fe4 CW |
55 | static int i915_capabilities(struct seq_file *m, void *data) |
56 | { | |
36cdd013 DW |
57 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
58 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 59 | |
36cdd013 | 60 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 61 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 63 | |
79fc46df | 64 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 65 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 66 | #undef PRINT_FLAG |
70d39fe4 | 67 | |
418e3cd8 CW |
68 | kernel_param_lock(THIS_MODULE); |
69 | #define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x); | |
70 | I915_PARAMS_FOR_EACH(PRINT_PARAM); | |
71 | #undef PRINT_PARAM | |
72 | kernel_param_unlock(THIS_MODULE); | |
73 | ||
70d39fe4 CW |
74 | return 0; |
75 | } | |
2017263e | 76 | |
a7363de7 | 77 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 78 | { |
573adb39 | 79 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
80 | } |
81 | ||
a7363de7 | 82 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
83 | { |
84 | return obj->pin_display ? 'p' : ' '; | |
85 | } | |
86 | ||
a7363de7 | 87 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 88 | { |
3e510a8e | 89 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 90 | default: |
be12a86b TU |
91 | case I915_TILING_NONE: return ' '; |
92 | case I915_TILING_X: return 'X'; | |
93 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 94 | } |
a6172a80 CW |
95 | } |
96 | ||
a7363de7 | 97 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 98 | { |
275f039d | 99 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
100 | } |
101 | ||
a7363de7 | 102 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 103 | { |
a4f5ea64 | 104 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
105 | } |
106 | ||
ca1543be TU |
107 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
108 | { | |
109 | u64 size = 0; | |
110 | struct i915_vma *vma; | |
111 | ||
1c7f4bca | 112 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 113 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
114 | size += vma->node.size; |
115 | } | |
116 | ||
117 | return size; | |
118 | } | |
119 | ||
37811fcc CW |
120 | static void |
121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
122 | { | |
b4716185 | 123 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 124 | struct intel_engine_cs *engine; |
1d693bcc | 125 | struct i915_vma *vma; |
faf5bf0a | 126 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
127 | int pin_count = 0; |
128 | ||
188c1ab7 CW |
129 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
130 | ||
d07f0e59 | 131 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 132 | &obj->base, |
be12a86b | 133 | get_active_flag(obj), |
37811fcc CW |
134 | get_pin_flag(obj), |
135 | get_tiling_flag(obj), | |
1d693bcc | 136 | get_global_flag(obj), |
be12a86b | 137 | get_pin_mapped_flag(obj), |
a05a5862 | 138 | obj->base.size / 1024, |
37811fcc | 139 | obj->base.read_domains, |
d07f0e59 | 140 | obj->base.write_domain, |
36cdd013 | 141 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
142 | obj->mm.dirty ? " dirty" : "", |
143 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
144 | if (obj->base.name) |
145 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 146 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 147 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 148 | pin_count++; |
ba0635ff DC |
149 | } |
150 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
151 | if (obj->pin_display) |
152 | seq_printf(m, " (display)"); | |
1c7f4bca | 153 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
154 | if (!drm_mm_node_allocated(&vma->node)) |
155 | continue; | |
156 | ||
8d2fdc3f | 157 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 158 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 159 | vma->node.start, vma->node.size); |
21976853 CW |
160 | if (i915_vma_is_ggtt(vma)) { |
161 | switch (vma->ggtt_view.type) { | |
162 | case I915_GGTT_VIEW_NORMAL: | |
163 | seq_puts(m, ", normal"); | |
164 | break; | |
165 | ||
166 | case I915_GGTT_VIEW_PARTIAL: | |
167 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
168 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
169 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
170 | break; |
171 | ||
172 | case I915_GGTT_VIEW_ROTATED: | |
173 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
174 | vma->ggtt_view.rotated.plane[0].width, |
175 | vma->ggtt_view.rotated.plane[0].height, | |
176 | vma->ggtt_view.rotated.plane[0].stride, | |
177 | vma->ggtt_view.rotated.plane[0].offset, | |
178 | vma->ggtt_view.rotated.plane[1].width, | |
179 | vma->ggtt_view.rotated.plane[1].height, | |
180 | vma->ggtt_view.rotated.plane[1].stride, | |
181 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
182 | break; |
183 | ||
184 | default: | |
185 | MISSING_CASE(vma->ggtt_view.type); | |
186 | break; | |
187 | } | |
188 | } | |
49ef5294 CW |
189 | if (vma->fence) |
190 | seq_printf(m, " , fence: %d%s", | |
191 | vma->fence->id, | |
192 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 193 | seq_puts(m, ")"); |
1d693bcc | 194 | } |
c1ad11fc | 195 | if (obj->stolen) |
440fd528 | 196 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 197 | |
d07f0e59 | 198 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
199 | if (engine) |
200 | seq_printf(m, " (%s)", engine->name); | |
201 | ||
faf5bf0a CW |
202 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
203 | if (frontbuffer_bits) | |
204 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
205 | } |
206 | ||
e637d2cb | 207 | static int obj_rank_by_stolen(const void *A, const void *B) |
6d2b8885 | 208 | { |
e637d2cb CW |
209 | const struct drm_i915_gem_object *a = |
210 | *(const struct drm_i915_gem_object **)A; | |
211 | const struct drm_i915_gem_object *b = | |
212 | *(const struct drm_i915_gem_object **)B; | |
6d2b8885 | 213 | |
2d05fa16 RV |
214 | if (a->stolen->start < b->stolen->start) |
215 | return -1; | |
216 | if (a->stolen->start > b->stolen->start) | |
217 | return 1; | |
218 | return 0; | |
6d2b8885 CW |
219 | } |
220 | ||
221 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
222 | { | |
36cdd013 DW |
223 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
224 | struct drm_device *dev = &dev_priv->drm; | |
e637d2cb | 225 | struct drm_i915_gem_object **objects; |
6d2b8885 | 226 | struct drm_i915_gem_object *obj; |
c44ef60e | 227 | u64 total_obj_size, total_gtt_size; |
e637d2cb CW |
228 | unsigned long total, count, n; |
229 | int ret; | |
230 | ||
231 | total = READ_ONCE(dev_priv->mm.object_count); | |
232 | objects = drm_malloc_ab(total, sizeof(*objects)); | |
233 | if (!objects) | |
234 | return -ENOMEM; | |
6d2b8885 CW |
235 | |
236 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
237 | if (ret) | |
e637d2cb | 238 | goto out; |
6d2b8885 CW |
239 | |
240 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 241 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
e637d2cb CW |
242 | if (count == total) |
243 | break; | |
244 | ||
6d2b8885 CW |
245 | if (obj->stolen == NULL) |
246 | continue; | |
247 | ||
e637d2cb | 248 | objects[count++] = obj; |
6d2b8885 | 249 | total_obj_size += obj->base.size; |
ca1543be | 250 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
e637d2cb | 251 | |
6d2b8885 | 252 | } |
56cea323 | 253 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
e637d2cb CW |
254 | if (count == total) |
255 | break; | |
256 | ||
6d2b8885 CW |
257 | if (obj->stolen == NULL) |
258 | continue; | |
259 | ||
e637d2cb | 260 | objects[count++] = obj; |
6d2b8885 | 261 | total_obj_size += obj->base.size; |
6d2b8885 | 262 | } |
e637d2cb CW |
263 | |
264 | sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL); | |
265 | ||
6d2b8885 | 266 | seq_puts(m, "Stolen:\n"); |
e637d2cb | 267 | for (n = 0; n < count; n++) { |
6d2b8885 | 268 | seq_puts(m, " "); |
e637d2cb | 269 | describe_obj(m, objects[n]); |
6d2b8885 | 270 | seq_putc(m, '\n'); |
6d2b8885 | 271 | } |
e637d2cb | 272 | seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n", |
6d2b8885 | 273 | count, total_obj_size, total_gtt_size); |
e637d2cb CW |
274 | |
275 | mutex_unlock(&dev->struct_mutex); | |
276 | out: | |
277 | drm_free_large(objects); | |
278 | return ret; | |
6d2b8885 CW |
279 | } |
280 | ||
2db8e9d6 | 281 | struct file_stats { |
6313c204 | 282 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
283 | unsigned long count; |
284 | u64 total, unbound; | |
285 | u64 global, shared; | |
286 | u64 active, inactive; | |
2db8e9d6 CW |
287 | }; |
288 | ||
289 | static int per_file_stats(int id, void *ptr, void *data) | |
290 | { | |
291 | struct drm_i915_gem_object *obj = ptr; | |
292 | struct file_stats *stats = data; | |
6313c204 | 293 | struct i915_vma *vma; |
2db8e9d6 CW |
294 | |
295 | stats->count++; | |
296 | stats->total += obj->base.size; | |
15717de2 CW |
297 | if (!obj->bind_count) |
298 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
299 | if (obj->base.name || obj->base.dma_buf) |
300 | stats->shared += obj->base.size; | |
301 | ||
894eeecc CW |
302 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
303 | if (!drm_mm_node_allocated(&vma->node)) | |
304 | continue; | |
6313c204 | 305 | |
3272db53 | 306 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
307 | stats->global += vma->node.size; |
308 | } else { | |
309 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 310 | |
2bfa996e | 311 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 312 | continue; |
6313c204 | 313 | } |
894eeecc | 314 | |
b0decaf7 | 315 | if (i915_vma_is_active(vma)) |
894eeecc CW |
316 | stats->active += vma->node.size; |
317 | else | |
318 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
319 | } |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
b0da1b79 CW |
324 | #define print_file_stats(m, name, stats) do { \ |
325 | if (stats.count) \ | |
c44ef60e | 326 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
327 | name, \ |
328 | stats.count, \ | |
329 | stats.total, \ | |
330 | stats.active, \ | |
331 | stats.inactive, \ | |
332 | stats.global, \ | |
333 | stats.shared, \ | |
334 | stats.unbound); \ | |
335 | } while (0) | |
493018dc BV |
336 | |
337 | static void print_batch_pool_stats(struct seq_file *m, | |
338 | struct drm_i915_private *dev_priv) | |
339 | { | |
340 | struct drm_i915_gem_object *obj; | |
341 | struct file_stats stats; | |
e2f80391 | 342 | struct intel_engine_cs *engine; |
3b3f1650 | 343 | enum intel_engine_id id; |
b4ac5afc | 344 | int j; |
493018dc BV |
345 | |
346 | memset(&stats, 0, sizeof(stats)); | |
347 | ||
3b3f1650 | 348 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 349 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 350 | list_for_each_entry(obj, |
e2f80391 | 351 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
352 | batch_pool_link) |
353 | per_file_stats(0, obj, &stats); | |
354 | } | |
06fbca71 | 355 | } |
493018dc | 356 | |
b0da1b79 | 357 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
358 | } |
359 | ||
15da9565 CW |
360 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
361 | { | |
362 | struct i915_gem_context *ctx = ptr; | |
363 | int n; | |
364 | ||
365 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
366 | if (ctx->engine[n].state) | |
bf3783e5 | 367 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 368 | if (ctx->engine[n].ring) |
57e88531 | 369 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
370 | } |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | static void print_context_stats(struct seq_file *m, | |
376 | struct drm_i915_private *dev_priv) | |
377 | { | |
36cdd013 | 378 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
379 | struct file_stats stats; |
380 | struct drm_file *file; | |
381 | ||
382 | memset(&stats, 0, sizeof(stats)); | |
383 | ||
36cdd013 | 384 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
385 | if (dev_priv->kernel_context) |
386 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
387 | ||
36cdd013 | 388 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
389 | struct drm_i915_file_private *fpriv = file->driver_priv; |
390 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
391 | } | |
36cdd013 | 392 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
393 | |
394 | print_file_stats(m, "[k]contexts", stats); | |
395 | } | |
396 | ||
36cdd013 | 397 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 398 | { |
36cdd013 DW |
399 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
400 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 401 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
402 | u32 count, mapped_count, purgeable_count, dpy_count; |
403 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 404 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 405 | struct drm_file *file; |
73aa808f CW |
406 | int ret; |
407 | ||
408 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
409 | if (ret) | |
410 | return ret; | |
411 | ||
3ef7f228 | 412 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
413 | dev_priv->mm.object_count, |
414 | dev_priv->mm.object_memory); | |
415 | ||
1544c42e CW |
416 | size = count = 0; |
417 | mapped_size = mapped_count = 0; | |
418 | purgeable_size = purgeable_count = 0; | |
56cea323 | 419 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
420 | size += obj->base.size; |
421 | ++count; | |
422 | ||
a4f5ea64 | 423 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
424 | purgeable_size += obj->base.size; |
425 | ++purgeable_count; | |
426 | } | |
427 | ||
a4f5ea64 | 428 | if (obj->mm.mapping) { |
2bd160a1 CW |
429 | mapped_count++; |
430 | mapped_size += obj->base.size; | |
be19b10d | 431 | } |
b7abb714 | 432 | } |
c44ef60e | 433 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 434 | |
2bd160a1 | 435 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 436 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
437 | size += obj->base.size; |
438 | ++count; | |
439 | ||
30154650 | 440 | if (obj->pin_display) { |
2bd160a1 CW |
441 | dpy_size += obj->base.size; |
442 | ++dpy_count; | |
6299f992 | 443 | } |
2bd160a1 | 444 | |
a4f5ea64 | 445 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
446 | purgeable_size += obj->base.size; |
447 | ++purgeable_count; | |
448 | } | |
2bd160a1 | 449 | |
a4f5ea64 | 450 | if (obj->mm.mapping) { |
2bd160a1 CW |
451 | mapped_count++; |
452 | mapped_size += obj->base.size; | |
be19b10d | 453 | } |
6299f992 | 454 | } |
2bd160a1 CW |
455 | seq_printf(m, "%u bound objects, %llu bytes\n", |
456 | count, size); | |
c44ef60e | 457 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 458 | purgeable_count, purgeable_size); |
2bd160a1 CW |
459 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
460 | mapped_count, mapped_size); | |
461 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
462 | dpy_count, dpy_size); | |
6299f992 | 463 | |
c44ef60e | 464 | seq_printf(m, "%llu [%llu] gtt total\n", |
381b943b | 465 | ggtt->base.total, ggtt->mappable_end); |
73aa808f | 466 | |
493018dc BV |
467 | seq_putc(m, '\n'); |
468 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
469 | mutex_unlock(&dev->struct_mutex); |
470 | ||
471 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 472 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
473 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
474 | struct file_stats stats; | |
c84455b4 CW |
475 | struct drm_i915_file_private *file_priv = file->driver_priv; |
476 | struct drm_i915_gem_request *request; | |
3ec2f427 | 477 | struct task_struct *task; |
2db8e9d6 CW |
478 | |
479 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 480 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 481 | spin_lock(&file->table_lock); |
2db8e9d6 | 482 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 483 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
484 | /* |
485 | * Although we have a valid reference on file->pid, that does | |
486 | * not guarantee that the task_struct who called get_pid() is | |
487 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
488 | * Therefore, we need to protect this ->comm access using RCU. | |
489 | */ | |
c84455b4 CW |
490 | mutex_lock(&dev->struct_mutex); |
491 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
492 | struct drm_i915_gem_request, | |
c8659efa | 493 | client_link); |
3ec2f427 | 494 | rcu_read_lock(); |
c84455b4 CW |
495 | task = pid_task(request && request->ctx->pid ? |
496 | request->ctx->pid : file->pid, | |
497 | PIDTYPE_PID); | |
493018dc | 498 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 499 | rcu_read_unlock(); |
c84455b4 | 500 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 501 | } |
1d2ac403 | 502 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
503 | |
504 | return 0; | |
505 | } | |
506 | ||
aee56cff | 507 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 508 | { |
9f25d007 | 509 | struct drm_info_node *node = m->private; |
36cdd013 DW |
510 | struct drm_i915_private *dev_priv = node_to_i915(node); |
511 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 512 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 513 | struct drm_i915_gem_object *obj; |
c44ef60e | 514 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
515 | int count, ret; |
516 | ||
517 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
518 | if (ret) | |
519 | return ret; | |
520 | ||
521 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 522 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 523 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
524 | continue; |
525 | ||
267f0c90 | 526 | seq_puts(m, " "); |
08c18323 | 527 | describe_obj(m, obj); |
267f0c90 | 528 | seq_putc(m, '\n'); |
08c18323 | 529 | total_obj_size += obj->base.size; |
ca1543be | 530 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
531 | count++; |
532 | } | |
533 | ||
534 | mutex_unlock(&dev->struct_mutex); | |
535 | ||
c44ef60e | 536 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
537 | count, total_obj_size, total_gtt_size); |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
4e5359cd SF |
542 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
543 | { | |
36cdd013 DW |
544 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
545 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 546 | struct intel_crtc *crtc; |
8a270ebf DV |
547 | int ret; |
548 | ||
549 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
550 | if (ret) | |
551 | return ret; | |
4e5359cd | 552 | |
d3fcc808 | 553 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
554 | const char pipe = pipe_name(crtc->pipe); |
555 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 556 | struct intel_flip_work *work; |
4e5359cd | 557 | |
5e2d7afc | 558 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
559 | work = crtc->flip_work; |
560 | if (work == NULL) { | |
9db4a9c7 | 561 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
562 | pipe, plane); |
563 | } else { | |
5a21b665 DV |
564 | u32 pending; |
565 | u32 addr; | |
566 | ||
567 | pending = atomic_read(&work->pending); | |
568 | if (pending) { | |
569 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
570 | pipe, plane); | |
571 | } else { | |
572 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
573 | pipe, plane); | |
574 | } | |
575 | if (work->flip_queued_req) { | |
24327f83 | 576 | struct intel_engine_cs *engine = work->flip_queued_req->engine; |
5a21b665 | 577 | |
312c3c47 | 578 | seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", |
5a21b665 | 579 | engine->name, |
24327f83 | 580 | work->flip_queued_req->global_seqno, |
312c3c47 | 581 | intel_engine_last_submit(engine), |
1b7744e7 | 582 | intel_engine_get_seqno(engine), |
f69a02c9 | 583 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
584 | } else |
585 | seq_printf(m, "Flip not associated with any ring\n"); | |
586 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
587 | work->flip_queued_vblank, | |
588 | work->flip_ready_vblank, | |
589 | intel_crtc_get_vblank_counter(crtc)); | |
590 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
591 | ||
36cdd013 | 592 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
593 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
594 | else | |
595 | addr = I915_READ(DSPADDR(crtc->plane)); | |
596 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
597 | ||
598 | if (work->pending_flip_obj) { | |
599 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
600 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
601 | } |
602 | } | |
5e2d7afc | 603 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
604 | } |
605 | ||
8a270ebf DV |
606 | mutex_unlock(&dev->struct_mutex); |
607 | ||
4e5359cd SF |
608 | return 0; |
609 | } | |
610 | ||
493018dc BV |
611 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
612 | { | |
36cdd013 DW |
613 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
614 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 615 | struct drm_i915_gem_object *obj; |
e2f80391 | 616 | struct intel_engine_cs *engine; |
3b3f1650 | 617 | enum intel_engine_id id; |
8d9d5744 | 618 | int total = 0; |
b4ac5afc | 619 | int ret, j; |
493018dc BV |
620 | |
621 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
622 | if (ret) | |
623 | return ret; | |
624 | ||
3b3f1650 | 625 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 626 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
627 | int count; |
628 | ||
629 | count = 0; | |
630 | list_for_each_entry(obj, | |
e2f80391 | 631 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
632 | batch_pool_link) |
633 | count++; | |
634 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 635 | engine->name, j, count); |
8d9d5744 CW |
636 | |
637 | list_for_each_entry(obj, | |
e2f80391 | 638 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
639 | batch_pool_link) { |
640 | seq_puts(m, " "); | |
641 | describe_obj(m, obj); | |
642 | seq_putc(m, '\n'); | |
643 | } | |
644 | ||
645 | total += count; | |
06fbca71 | 646 | } |
493018dc BV |
647 | } |
648 | ||
8d9d5744 | 649 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
650 | |
651 | mutex_unlock(&dev->struct_mutex); | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
1b36595f CW |
656 | static void print_request(struct seq_file *m, |
657 | struct drm_i915_gem_request *rq, | |
658 | const char *prefix) | |
659 | { | |
20311bd3 | 660 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 661 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 662 | rq->priotree.priority, |
1b36595f | 663 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 664 | rq->timeline->common->name); |
1b36595f CW |
665 | } |
666 | ||
2017263e BG |
667 | static int i915_gem_request_info(struct seq_file *m, void *data) |
668 | { | |
36cdd013 DW |
669 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
670 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 671 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
672 | struct intel_engine_cs *engine; |
673 | enum intel_engine_id id; | |
b4ac5afc | 674 | int ret, any; |
de227ef0 CW |
675 | |
676 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
677 | if (ret) | |
678 | return ret; | |
2017263e | 679 | |
2d1070b2 | 680 | any = 0; |
3b3f1650 | 681 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
682 | int count; |
683 | ||
684 | count = 0; | |
73cb9701 | 685 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
686 | count++; |
687 | if (count == 0) | |
a2c7f6fd CW |
688 | continue; |
689 | ||
e2f80391 | 690 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 691 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 692 | print_request(m, req, " "); |
2d1070b2 CW |
693 | |
694 | any++; | |
2017263e | 695 | } |
de227ef0 CW |
696 | mutex_unlock(&dev->struct_mutex); |
697 | ||
2d1070b2 | 698 | if (any == 0) |
267f0c90 | 699 | seq_puts(m, "No requests\n"); |
c2c347a9 | 700 | |
2017263e BG |
701 | return 0; |
702 | } | |
703 | ||
b2223497 | 704 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 705 | struct intel_engine_cs *engine) |
b2223497 | 706 | { |
688e6c72 CW |
707 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
708 | struct rb_node *rb; | |
709 | ||
12471ba8 | 710 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 711 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 712 | |
61d3dc70 | 713 | spin_lock_irq(&b->rb_lock); |
688e6c72 | 714 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 715 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
688e6c72 CW |
716 | |
717 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
718 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
719 | } | |
61d3dc70 | 720 | spin_unlock_irq(&b->rb_lock); |
b2223497 CW |
721 | } |
722 | ||
2017263e BG |
723 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
724 | { | |
36cdd013 | 725 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 726 | struct intel_engine_cs *engine; |
3b3f1650 | 727 | enum intel_engine_id id; |
2017263e | 728 | |
3b3f1650 | 729 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 730 | i915_ring_seqno_info(m, engine); |
de227ef0 | 731 | |
2017263e BG |
732 | return 0; |
733 | } | |
734 | ||
735 | ||
736 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
737 | { | |
36cdd013 | 738 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 739 | struct intel_engine_cs *engine; |
3b3f1650 | 740 | enum intel_engine_id id; |
4bb05040 | 741 | int i, pipe; |
de227ef0 | 742 | |
c8c8fb33 | 743 | intel_runtime_pm_get(dev_priv); |
2017263e | 744 | |
36cdd013 | 745 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
746 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
747 | I915_READ(GEN8_MASTER_IRQ)); | |
748 | ||
749 | seq_printf(m, "Display IER:\t%08x\n", | |
750 | I915_READ(VLV_IER)); | |
751 | seq_printf(m, "Display IIR:\t%08x\n", | |
752 | I915_READ(VLV_IIR)); | |
753 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
754 | I915_READ(VLV_IIR_RW)); | |
755 | seq_printf(m, "Display IMR:\t%08x\n", | |
756 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
757 | for_each_pipe(dev_priv, pipe) { |
758 | enum intel_display_power_domain power_domain; | |
759 | ||
760 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
761 | if (!intel_display_power_get_if_enabled(dev_priv, | |
762 | power_domain)) { | |
763 | seq_printf(m, "Pipe %c power disabled\n", | |
764 | pipe_name(pipe)); | |
765 | continue; | |
766 | } | |
767 | ||
74e1ca8c VS |
768 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
769 | pipe_name(pipe), | |
770 | I915_READ(PIPESTAT(pipe))); | |
771 | ||
9c870d03 CW |
772 | intel_display_power_put(dev_priv, power_domain); |
773 | } | |
774 | ||
775 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
776 | seq_printf(m, "Port hotplug:\t%08x\n", |
777 | I915_READ(PORT_HOTPLUG_EN)); | |
778 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
779 | I915_READ(VLV_DPFLIPSTAT)); | |
780 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
781 | I915_READ(DPINVGTT)); | |
9c870d03 | 782 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
783 | |
784 | for (i = 0; i < 4; i++) { | |
785 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
786 | i, I915_READ(GEN8_GT_IMR(i))); | |
787 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
788 | i, I915_READ(GEN8_GT_IIR(i))); | |
789 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
790 | i, I915_READ(GEN8_GT_IER(i))); | |
791 | } | |
792 | ||
793 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
794 | I915_READ(GEN8_PCU_IMR)); | |
795 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
796 | I915_READ(GEN8_PCU_IIR)); | |
797 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
798 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 799 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
800 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
801 | I915_READ(GEN8_MASTER_IRQ)); | |
802 | ||
803 | for (i = 0; i < 4; i++) { | |
804 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
805 | i, I915_READ(GEN8_GT_IMR(i))); | |
806 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
807 | i, I915_READ(GEN8_GT_IIR(i))); | |
808 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
809 | i, I915_READ(GEN8_GT_IER(i))); | |
810 | } | |
811 | ||
055e393f | 812 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
813 | enum intel_display_power_domain power_domain; |
814 | ||
815 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
816 | if (!intel_display_power_get_if_enabled(dev_priv, | |
817 | power_domain)) { | |
22c59960 PZ |
818 | seq_printf(m, "Pipe %c power disabled\n", |
819 | pipe_name(pipe)); | |
820 | continue; | |
821 | } | |
a123f157 | 822 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
823 | pipe_name(pipe), |
824 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 825 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
826 | pipe_name(pipe), |
827 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 828 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
829 | pipe_name(pipe), |
830 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
831 | |
832 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
833 | } |
834 | ||
835 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
836 | I915_READ(GEN8_DE_PORT_IMR)); | |
837 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
838 | I915_READ(GEN8_DE_PORT_IIR)); | |
839 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
840 | I915_READ(GEN8_DE_PORT_IER)); | |
841 | ||
842 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
843 | I915_READ(GEN8_DE_MISC_IMR)); | |
844 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
845 | I915_READ(GEN8_DE_MISC_IIR)); | |
846 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
847 | I915_READ(GEN8_DE_MISC_IER)); | |
848 | ||
849 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
850 | I915_READ(GEN8_PCU_IMR)); | |
851 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
852 | I915_READ(GEN8_PCU_IIR)); | |
853 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
854 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 855 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
856 | seq_printf(m, "Display IER:\t%08x\n", |
857 | I915_READ(VLV_IER)); | |
858 | seq_printf(m, "Display IIR:\t%08x\n", | |
859 | I915_READ(VLV_IIR)); | |
860 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
861 | I915_READ(VLV_IIR_RW)); | |
862 | seq_printf(m, "Display IMR:\t%08x\n", | |
863 | I915_READ(VLV_IMR)); | |
4f4631af CW |
864 | for_each_pipe(dev_priv, pipe) { |
865 | enum intel_display_power_domain power_domain; | |
866 | ||
867 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
868 | if (!intel_display_power_get_if_enabled(dev_priv, | |
869 | power_domain)) { | |
870 | seq_printf(m, "Pipe %c power disabled\n", | |
871 | pipe_name(pipe)); | |
872 | continue; | |
873 | } | |
874 | ||
7e231dbe JB |
875 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
876 | pipe_name(pipe), | |
877 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
878 | intel_display_power_put(dev_priv, power_domain); |
879 | } | |
7e231dbe JB |
880 | |
881 | seq_printf(m, "Master IER:\t%08x\n", | |
882 | I915_READ(VLV_MASTER_IER)); | |
883 | ||
884 | seq_printf(m, "Render IER:\t%08x\n", | |
885 | I915_READ(GTIER)); | |
886 | seq_printf(m, "Render IIR:\t%08x\n", | |
887 | I915_READ(GTIIR)); | |
888 | seq_printf(m, "Render IMR:\t%08x\n", | |
889 | I915_READ(GTIMR)); | |
890 | ||
891 | seq_printf(m, "PM IER:\t\t%08x\n", | |
892 | I915_READ(GEN6_PMIER)); | |
893 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
894 | I915_READ(GEN6_PMIIR)); | |
895 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
896 | I915_READ(GEN6_PMIMR)); | |
897 | ||
898 | seq_printf(m, "Port hotplug:\t%08x\n", | |
899 | I915_READ(PORT_HOTPLUG_EN)); | |
900 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
901 | I915_READ(VLV_DPFLIPSTAT)); | |
902 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
903 | I915_READ(DPINVGTT)); | |
904 | ||
36cdd013 | 905 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
906 | seq_printf(m, "Interrupt enable: %08x\n", |
907 | I915_READ(IER)); | |
908 | seq_printf(m, "Interrupt identity: %08x\n", | |
909 | I915_READ(IIR)); | |
910 | seq_printf(m, "Interrupt mask: %08x\n", | |
911 | I915_READ(IMR)); | |
055e393f | 912 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
913 | seq_printf(m, "Pipe %c stat: %08x\n", |
914 | pipe_name(pipe), | |
915 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
916 | } else { |
917 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
918 | I915_READ(DEIER)); | |
919 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
920 | I915_READ(DEIIR)); | |
921 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
922 | I915_READ(DEIMR)); | |
923 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
924 | I915_READ(SDEIER)); | |
925 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
926 | I915_READ(SDEIIR)); | |
927 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
928 | I915_READ(SDEIMR)); | |
929 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
930 | I915_READ(GTIER)); | |
931 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
932 | I915_READ(GTIIR)); | |
933 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
934 | I915_READ(GTIMR)); | |
935 | } | |
3b3f1650 | 936 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 937 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
938 | seq_printf(m, |
939 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 940 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 941 | } |
e2f80391 | 942 | i915_ring_seqno_info(m, engine); |
9862e600 | 943 | } |
c8c8fb33 | 944 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 945 | |
2017263e BG |
946 | return 0; |
947 | } | |
948 | ||
a6172a80 CW |
949 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
950 | { | |
36cdd013 DW |
951 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
952 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
953 | int i, ret; |
954 | ||
955 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
956 | if (ret) | |
957 | return ret; | |
a6172a80 | 958 | |
a6172a80 CW |
959 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
960 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 961 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 962 | |
6c085a72 CW |
963 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
964 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 965 | if (!vma) |
267f0c90 | 966 | seq_puts(m, "unused"); |
c2c347a9 | 967 | else |
49ef5294 | 968 | describe_obj(m, vma->obj); |
267f0c90 | 969 | seq_putc(m, '\n'); |
a6172a80 CW |
970 | } |
971 | ||
05394f39 | 972 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
973 | return 0; |
974 | } | |
975 | ||
98a2f411 | 976 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
977 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
978 | size_t count, loff_t *pos) | |
d5442303 | 979 | { |
5a4c6f1b CW |
980 | struct i915_gpu_state *error = file->private_data; |
981 | struct drm_i915_error_state_buf str; | |
982 | ssize_t ret; | |
983 | loff_t tmp; | |
d5442303 | 984 | |
5a4c6f1b CW |
985 | if (!error) |
986 | return 0; | |
d5442303 | 987 | |
5a4c6f1b CW |
988 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
989 | if (ret) | |
990 | return ret; | |
d5442303 | 991 | |
5a4c6f1b CW |
992 | ret = i915_error_state_to_str(&str, error); |
993 | if (ret) | |
994 | goto out; | |
d5442303 | 995 | |
5a4c6f1b CW |
996 | tmp = 0; |
997 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
998 | if (ret < 0) | |
999 | goto out; | |
d5442303 | 1000 | |
5a4c6f1b CW |
1001 | *pos = str.start + ret; |
1002 | out: | |
1003 | i915_error_state_buf_release(&str); | |
1004 | return ret; | |
1005 | } | |
edc3d884 | 1006 | |
5a4c6f1b CW |
1007 | static int gpu_state_release(struct inode *inode, struct file *file) |
1008 | { | |
1009 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 1010 | return 0; |
d5442303 DV |
1011 | } |
1012 | ||
5a4c6f1b | 1013 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 1014 | { |
5a4c6f1b | 1015 | struct i915_gpu_state *gpu; |
d5442303 | 1016 | |
5a4c6f1b CW |
1017 | gpu = i915_capture_gpu_state(inode->i_private); |
1018 | if (!gpu) | |
1019 | return -ENOMEM; | |
d5442303 | 1020 | |
5a4c6f1b | 1021 | file->private_data = gpu; |
edc3d884 MK |
1022 | return 0; |
1023 | } | |
1024 | ||
5a4c6f1b CW |
1025 | static const struct file_operations i915_gpu_info_fops = { |
1026 | .owner = THIS_MODULE, | |
1027 | .open = i915_gpu_info_open, | |
1028 | .read = gpu_state_read, | |
1029 | .llseek = default_llseek, | |
1030 | .release = gpu_state_release, | |
1031 | }; | |
1032 | ||
1033 | static ssize_t | |
1034 | i915_error_state_write(struct file *filp, | |
1035 | const char __user *ubuf, | |
1036 | size_t cnt, | |
1037 | loff_t *ppos) | |
4dc955f7 | 1038 | { |
5a4c6f1b | 1039 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 1040 | |
5a4c6f1b CW |
1041 | if (!error) |
1042 | return 0; | |
edc3d884 | 1043 | |
5a4c6f1b CW |
1044 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
1045 | i915_reset_error_state(error->i915); | |
edc3d884 | 1046 | |
5a4c6f1b CW |
1047 | return cnt; |
1048 | } | |
edc3d884 | 1049 | |
5a4c6f1b CW |
1050 | static int i915_error_state_open(struct inode *inode, struct file *file) |
1051 | { | |
1052 | file->private_data = i915_first_error_state(inode->i_private); | |
1053 | return 0; | |
d5442303 DV |
1054 | } |
1055 | ||
1056 | static const struct file_operations i915_error_state_fops = { | |
1057 | .owner = THIS_MODULE, | |
1058 | .open = i915_error_state_open, | |
5a4c6f1b | 1059 | .read = gpu_state_read, |
d5442303 DV |
1060 | .write = i915_error_state_write, |
1061 | .llseek = default_llseek, | |
5a4c6f1b | 1062 | .release = gpu_state_release, |
d5442303 | 1063 | }; |
98a2f411 CW |
1064 | #endif |
1065 | ||
647416f9 KC |
1066 | static int |
1067 | i915_next_seqno_set(void *data, u64 val) | |
1068 | { | |
36cdd013 DW |
1069 | struct drm_i915_private *dev_priv = data; |
1070 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1071 | int ret; |
1072 | ||
40633219 MK |
1073 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1074 | if (ret) | |
1075 | return ret; | |
1076 | ||
73cb9701 | 1077 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1078 | mutex_unlock(&dev->struct_mutex); |
1079 | ||
647416f9 | 1080 | return ret; |
40633219 MK |
1081 | } |
1082 | ||
647416f9 | 1083 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
9b6586ae | 1084 | NULL, i915_next_seqno_set, |
3a3b4f98 | 1085 | "0x%llx\n"); |
40633219 | 1086 | |
adb4bd12 | 1087 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1088 | { |
36cdd013 | 1089 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
c8c8fb33 PZ |
1090 | int ret = 0; |
1091 | ||
1092 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1093 | |
36cdd013 | 1094 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1095 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1096 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1097 | ||
1098 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1099 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1100 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1101 | MEMSTAT_VID_SHIFT); | |
1102 | seq_printf(m, "Current P-state: %d\n", | |
1103 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1104 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1105 | u32 freq_sts; |
1106 | ||
1107 | mutex_lock(&dev_priv->rps.hw_lock); | |
1108 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1109 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1110 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1111 | ||
1112 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1113 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1114 | ||
1115 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1116 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1117 | ||
1118 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1119 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1120 | ||
1121 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1122 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1123 | ||
1124 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1125 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1126 | ||
1127 | seq_printf(m, | |
1128 | "efficient (RPe) frequency: %d MHz\n", | |
1129 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1130 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1131 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1132 | u32 rp_state_limits; |
1133 | u32 gt_perf_status; | |
1134 | u32 rp_state_cap; | |
0d8f9491 | 1135 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1136 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1137 | u32 rpupei, rpcurup, rpprevup; |
1138 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1139 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1140 | int max_freq; |
1141 | ||
35040562 | 1142 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1143 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1144 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1145 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1146 | } else { | |
1147 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1148 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1149 | } | |
1150 | ||
3b8d8d91 | 1151 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1152 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1153 | |
8e8c06cd | 1154 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1155 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1156 | reqf >>= 23; |
1157 | else { | |
1158 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1159 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1160 | reqf >>= 24; |
1161 | else | |
1162 | reqf >>= 25; | |
1163 | } | |
7c59a9c1 | 1164 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1165 | |
0d8f9491 CW |
1166 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1167 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1168 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1169 | ||
ccab5c82 | 1170 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1171 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1172 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1173 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1174 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1175 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1176 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1177 | if (IS_GEN9(dev_priv)) |
60260a5b | 1178 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1179 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1180 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1181 | else | |
1182 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1183 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1184 | |
59bad947 | 1185 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1186 | |
36cdd013 | 1187 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1188 | pm_ier = I915_READ(GEN6_PMIER); |
1189 | pm_imr = I915_READ(GEN6_PMIMR); | |
1190 | pm_isr = I915_READ(GEN6_PMISR); | |
1191 | pm_iir = I915_READ(GEN6_PMIIR); | |
1192 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1193 | } else { | |
1194 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1195 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1196 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1197 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1198 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1199 | } | |
0d8f9491 | 1200 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1201 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
5dd04556 SAK |
1202 | seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", |
1203 | dev_priv->rps.pm_intrmsk_mbz); | |
3b8d8d91 | 1204 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1205 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1206 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1207 | seq_printf(m, "Render p-state VID: %d\n", |
1208 | gt_perf_status & 0xff); | |
1209 | seq_printf(m, "Render p-state limit: %d\n", | |
1210 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1211 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1212 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1213 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1214 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1215 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1216 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1217 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1218 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1219 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1220 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1221 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1222 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1223 | seq_printf(m, "Up threshold: %d%%\n", |
1224 | dev_priv->rps.up_threshold); | |
1225 | ||
d6cda9c7 AG |
1226 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1227 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1228 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1229 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1230 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1231 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1232 | seq_printf(m, "Down threshold: %d%%\n", |
1233 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1234 | |
cc3f90f0 | 1235 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1236 | rp_state_cap >> 16) & 0xff; |
b976dc53 | 1237 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1238 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1239 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1240 | |
1241 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
b976dc53 | 1242 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1243 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1244 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1245 | |
cc3f90f0 | 1246 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1247 | rp_state_cap >> 0) & 0xff; |
b976dc53 | 1248 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1249 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1250 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1251 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1252 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1253 | |
d86ed34a CW |
1254 | seq_printf(m, "Current freq: %d MHz\n", |
1255 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1256 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1257 | seq_printf(m, "Idle freq: %d MHz\n", |
1258 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1259 | seq_printf(m, "Min freq: %d MHz\n", |
1260 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1261 | seq_printf(m, "Boost freq: %d MHz\n", |
1262 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1263 | seq_printf(m, "Max freq: %d MHz\n", |
1264 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1265 | seq_printf(m, | |
1266 | "efficient (RPe) frequency: %d MHz\n", | |
1267 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1268 | } else { |
267f0c90 | 1269 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1270 | } |
f97108d1 | 1271 | |
49cd97a3 | 1272 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1273 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1274 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1275 | ||
c8c8fb33 PZ |
1276 | intel_runtime_pm_put(dev_priv); |
1277 | return ret; | |
f97108d1 JB |
1278 | } |
1279 | ||
d636951e BW |
1280 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1281 | struct seq_file *m, | |
1282 | struct intel_instdone *instdone) | |
1283 | { | |
f9e61372 BW |
1284 | int slice; |
1285 | int subslice; | |
1286 | ||
d636951e BW |
1287 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1288 | instdone->instdone); | |
1289 | ||
1290 | if (INTEL_GEN(dev_priv) <= 3) | |
1291 | return; | |
1292 | ||
1293 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1294 | instdone->slice_common); | |
1295 | ||
1296 | if (INTEL_GEN(dev_priv) <= 6) | |
1297 | return; | |
1298 | ||
f9e61372 BW |
1299 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1300 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1301 | slice, subslice, instdone->sampler[slice][subslice]); | |
1302 | ||
1303 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1304 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1305 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1306 | } |
1307 | ||
f654449a CW |
1308 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1309 | { | |
36cdd013 | 1310 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1311 | struct intel_engine_cs *engine; |
666796da TU |
1312 | u64 acthd[I915_NUM_ENGINES]; |
1313 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1314 | struct intel_instdone instdone; |
c3232b18 | 1315 | enum intel_engine_id id; |
f654449a | 1316 | |
8af29b0c | 1317 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8c185eca CW |
1318 | seq_puts(m, "Wedged\n"); |
1319 | if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) | |
1320 | seq_puts(m, "Reset in progress: struct_mutex backoff\n"); | |
1321 | if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags)) | |
1322 | seq_puts(m, "Reset in progress: reset handoff to waiter\n"); | |
8af29b0c | 1323 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) |
8c185eca | 1324 | seq_puts(m, "Waiter holding struct mutex\n"); |
8af29b0c | 1325 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) |
8c185eca | 1326 | seq_puts(m, "struct_mutex blocked for reset\n"); |
8af29b0c | 1327 | |
f654449a | 1328 | if (!i915.enable_hangcheck) { |
8c185eca | 1329 | seq_puts(m, "Hangcheck disabled\n"); |
f654449a CW |
1330 | return 0; |
1331 | } | |
1332 | ||
ebbc7546 MK |
1333 | intel_runtime_pm_get(dev_priv); |
1334 | ||
3b3f1650 | 1335 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1336 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1337 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1338 | } |
1339 | ||
3b3f1650 | 1340 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1341 | |
ebbc7546 MK |
1342 | intel_runtime_pm_put(dev_priv); |
1343 | ||
8352aea3 CW |
1344 | if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer)) |
1345 | seq_printf(m, "Hangcheck active, timer fires in %dms\n", | |
f654449a CW |
1346 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - |
1347 | jiffies)); | |
8352aea3 CW |
1348 | else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) |
1349 | seq_puts(m, "Hangcheck active, work pending\n"); | |
1350 | else | |
1351 | seq_puts(m, "Hangcheck inactive\n"); | |
f654449a | 1352 | |
f73b5674 CW |
1353 | seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); |
1354 | ||
3b3f1650 | 1355 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1356 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1357 | struct rb_node *rb; | |
1358 | ||
e2f80391 | 1359 | seq_printf(m, "%s:\n", engine->name); |
f73b5674 | 1360 | seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n", |
cb399eab | 1361 | engine->hangcheck.seqno, seqno[id], |
f73b5674 CW |
1362 | intel_engine_last_submit(engine), |
1363 | engine->timeline->inflight_seqnos); | |
3fe3b030 | 1364 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1365 | yesno(intel_engine_has_waiter(engine)), |
1366 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1367 | &dev_priv->gpu_error.missed_irq_rings)), |
1368 | yesno(engine->hangcheck.stalled)); | |
1369 | ||
61d3dc70 | 1370 | spin_lock_irq(&b->rb_lock); |
33f53719 | 1371 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1372 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1373 | |
1374 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1375 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1376 | } | |
61d3dc70 | 1377 | spin_unlock_irq(&b->rb_lock); |
33f53719 | 1378 | |
f654449a | 1379 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1380 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1381 | (long long)acthd[id]); |
3fe3b030 MK |
1382 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1383 | hangcheck_action_to_str(engine->hangcheck.action), | |
1384 | engine->hangcheck.action, | |
1385 | jiffies_to_msecs(jiffies - | |
1386 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1387 | |
e2f80391 | 1388 | if (engine->id == RCS) { |
d636951e | 1389 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1390 | |
d636951e | 1391 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1392 | |
d636951e | 1393 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1394 | |
d636951e BW |
1395 | i915_instdone_info(dev_priv, m, |
1396 | &engine->hangcheck.instdone); | |
61642ff0 | 1397 | } |
f654449a CW |
1398 | } |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
4d85529d | 1403 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1404 | { |
36cdd013 | 1405 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1406 | u32 rgvmodectl, rstdbyctl; |
1407 | u16 crstandvid; | |
616fdb5a | 1408 | |
616fdb5a BW |
1409 | rgvmodectl = I915_READ(MEMMODECTL); |
1410 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1411 | crstandvid = I915_READ16(CRSTANDVID); | |
1412 | ||
742f491d | 1413 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1414 | seq_printf(m, "Boost freq: %d\n", |
1415 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1416 | MEMMODE_BOOST_FREQ_SHIFT); | |
1417 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1418 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1419 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1420 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1421 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1422 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1423 | seq_printf(m, "Starting frequency: P%d\n", |
1424 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1425 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1426 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1427 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1428 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1429 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1430 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1431 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1432 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1433 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1434 | case RSX_STATUS_ON: | |
267f0c90 | 1435 | seq_puts(m, "on\n"); |
88271da3 JB |
1436 | break; |
1437 | case RSX_STATUS_RC1: | |
267f0c90 | 1438 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1439 | break; |
1440 | case RSX_STATUS_RC1E: | |
267f0c90 | 1441 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1442 | break; |
1443 | case RSX_STATUS_RS1: | |
267f0c90 | 1444 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1445 | break; |
1446 | case RSX_STATUS_RS2: | |
267f0c90 | 1447 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1448 | break; |
1449 | case RSX_STATUS_RS3: | |
267f0c90 | 1450 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1451 | break; |
1452 | default: | |
267f0c90 | 1453 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1454 | break; |
1455 | } | |
f97108d1 JB |
1456 | |
1457 | return 0; | |
1458 | } | |
1459 | ||
f65367b5 | 1460 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1461 | { |
36cdd013 | 1462 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1463 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1464 | |
1465 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1466 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1467 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1468 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1469 | fw_domain->wake_count); |
1470 | } | |
1471 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1472 | |
b2cff0db CW |
1473 | return 0; |
1474 | } | |
1475 | ||
1362877e MK |
1476 | static void print_rc6_res(struct seq_file *m, |
1477 | const char *title, | |
1478 | const i915_reg_t reg) | |
1479 | { | |
1480 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1481 | ||
1482 | seq_printf(m, "%s %u (%llu us)\n", | |
1483 | title, I915_READ(reg), | |
1484 | intel_rc6_residency_us(dev_priv, reg)); | |
1485 | } | |
1486 | ||
b2cff0db CW |
1487 | static int vlv_drpc_info(struct seq_file *m) |
1488 | { | |
36cdd013 | 1489 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1490 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1491 | |
6b312cd3 | 1492 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1493 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1494 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1495 | ||
1496 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1497 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1498 | seq_printf(m, "Turbo enabled: %s\n", | |
1499 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1500 | seq_printf(m, "HW control enabled: %s\n", | |
1501 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1502 | seq_printf(m, "SW control enabled: %s\n", | |
1503 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1504 | GEN6_RP_MEDIA_SW_MODE)); | |
1505 | seq_printf(m, "RC6 Enabled: %s\n", | |
1506 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1507 | GEN6_RC_CTL_EI_MODE(1)))); | |
1508 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1509 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1510 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1511 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1512 | |
1362877e MK |
1513 | print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); |
1514 | print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); | |
9cc19be5 | 1515 | |
f65367b5 | 1516 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1517 | } |
1518 | ||
4d85529d BW |
1519 | static int gen6_drpc_info(struct seq_file *m) |
1520 | { | |
36cdd013 | 1521 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ecd8faea | 1522 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1523 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1524 | unsigned forcewake_count; |
cf632bd6 | 1525 | int count = 0; |
93b525dc | 1526 | |
cf632bd6 | 1527 | forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count); |
93b525dc | 1528 | if (forcewake_count) { |
267f0c90 DL |
1529 | seq_puts(m, "RC information inaccurate because somebody " |
1530 | "holds a forcewake reference \n"); | |
4d85529d BW |
1531 | } else { |
1532 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1533 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1534 | udelay(10); | |
1535 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1536 | } | |
1537 | ||
75aa3f63 | 1538 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1539 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1540 | |
1541 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1542 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1543 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1544 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1545 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1546 | } | |
cf632bd6 | 1547 | |
44cbd338 BW |
1548 | mutex_lock(&dev_priv->rps.hw_lock); |
1549 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1550 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1551 | |
1552 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1553 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1554 | seq_printf(m, "HW control enabled: %s\n", | |
1555 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1556 | seq_printf(m, "SW control enabled: %s\n", | |
1557 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1558 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1559 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1560 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1561 | seq_printf(m, "RC6 Enabled: %s\n", | |
1562 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1563 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1564 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1565 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1566 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1567 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1568 | } | |
4d85529d BW |
1569 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1570 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1571 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1572 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1573 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1574 | switch (gt_core_status & GEN6_RCn_MASK) { |
1575 | case GEN6_RC0: | |
1576 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1577 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1578 | else |
267f0c90 | 1579 | seq_puts(m, "on\n"); |
4d85529d BW |
1580 | break; |
1581 | case GEN6_RC3: | |
267f0c90 | 1582 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1583 | break; |
1584 | case GEN6_RC6: | |
267f0c90 | 1585 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1586 | break; |
1587 | case GEN6_RC7: | |
267f0c90 | 1588 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1589 | break; |
1590 | default: | |
267f0c90 | 1591 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1592 | break; |
1593 | } | |
1594 | ||
1595 | seq_printf(m, "Core Power Down: %s\n", | |
1596 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1597 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1598 | seq_printf(m, "Render Power Well: %s\n", |
1599 | (gen9_powergate_status & | |
1600 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1601 | seq_printf(m, "Media Power Well: %s\n", | |
1602 | (gen9_powergate_status & | |
1603 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1604 | } | |
cce66a28 BW |
1605 | |
1606 | /* Not exactly sure what this is */ | |
1362877e MK |
1607 | print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", |
1608 | GEN6_GT_GFX_RC6_LOCKED); | |
1609 | print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); | |
1610 | print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); | |
1611 | print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); | |
cce66a28 | 1612 | |
ecd8faea BW |
1613 | seq_printf(m, "RC6 voltage: %dmV\n", |
1614 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1615 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1616 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1617 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1618 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1619 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1620 | } |
1621 | ||
1622 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1623 | { | |
36cdd013 | 1624 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
cf632bd6 CW |
1625 | int err; |
1626 | ||
1627 | intel_runtime_pm_get(dev_priv); | |
4d85529d | 1628 | |
36cdd013 | 1629 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
cf632bd6 | 1630 | err = vlv_drpc_info(m); |
36cdd013 | 1631 | else if (INTEL_GEN(dev_priv) >= 6) |
cf632bd6 | 1632 | err = gen6_drpc_info(m); |
4d85529d | 1633 | else |
cf632bd6 CW |
1634 | err = ironlake_drpc_info(m); |
1635 | ||
1636 | intel_runtime_pm_put(dev_priv); | |
1637 | ||
1638 | return err; | |
4d85529d BW |
1639 | } |
1640 | ||
9a851789 DV |
1641 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1642 | { | |
36cdd013 | 1643 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1644 | |
1645 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1646 | dev_priv->fb_tracking.busy_bits); | |
1647 | ||
1648 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1649 | dev_priv->fb_tracking.flip_bits); | |
1650 | ||
1651 | return 0; | |
1652 | } | |
1653 | ||
b5e50c3f JB |
1654 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1655 | { | |
36cdd013 | 1656 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1657 | |
36cdd013 | 1658 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1659 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1660 | return 0; |
1661 | } | |
1662 | ||
36623ef8 | 1663 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1664 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1665 | |
0e631adc | 1666 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1667 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1668 | else |
1669 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1670 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1671 | |
0fc6a9dc PZ |
1672 | if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { |
1673 | uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? | |
1674 | BDW_FBC_COMPRESSION_MASK : | |
1675 | IVB_FBC_COMPRESSION_MASK; | |
31b9df10 | 1676 | seq_printf(m, "Compressing: %s\n", |
0fc6a9dc PZ |
1677 | yesno(I915_READ(FBC_STATUS2) & mask)); |
1678 | } | |
31b9df10 | 1679 | |
25ad93fd | 1680 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1681 | intel_runtime_pm_put(dev_priv); |
1682 | ||
b5e50c3f JB |
1683 | return 0; |
1684 | } | |
1685 | ||
da46f936 RV |
1686 | static int i915_fbc_fc_get(void *data, u64 *val) |
1687 | { | |
36cdd013 | 1688 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1689 | |
36cdd013 | 1690 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1691 | return -ENODEV; |
1692 | ||
da46f936 | 1693 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1694 | |
1695 | return 0; | |
1696 | } | |
1697 | ||
1698 | static int i915_fbc_fc_set(void *data, u64 val) | |
1699 | { | |
36cdd013 | 1700 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1701 | u32 reg; |
1702 | ||
36cdd013 | 1703 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1704 | return -ENODEV; |
1705 | ||
25ad93fd | 1706 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1707 | |
1708 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1709 | dev_priv->fbc.false_color = val; | |
1710 | ||
1711 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1712 | (reg | FBC_CTL_FALSE_COLOR) : | |
1713 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1714 | ||
25ad93fd | 1715 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1716 | return 0; |
1717 | } | |
1718 | ||
1719 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1720 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1721 | "%llu\n"); | |
1722 | ||
92d44621 PZ |
1723 | static int i915_ips_status(struct seq_file *m, void *unused) |
1724 | { | |
36cdd013 | 1725 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1726 | |
36cdd013 | 1727 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1728 | seq_puts(m, "not supported\n"); |
1729 | return 0; | |
1730 | } | |
1731 | ||
36623ef8 PZ |
1732 | intel_runtime_pm_get(dev_priv); |
1733 | ||
0eaa53f0 RV |
1734 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1735 | yesno(i915.enable_ips)); | |
1736 | ||
36cdd013 | 1737 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1738 | seq_puts(m, "Currently: unknown\n"); |
1739 | } else { | |
1740 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1741 | seq_puts(m, "Currently: enabled\n"); | |
1742 | else | |
1743 | seq_puts(m, "Currently: disabled\n"); | |
1744 | } | |
92d44621 | 1745 | |
36623ef8 PZ |
1746 | intel_runtime_pm_put(dev_priv); |
1747 | ||
92d44621 PZ |
1748 | return 0; |
1749 | } | |
1750 | ||
4a9bef37 JB |
1751 | static int i915_sr_status(struct seq_file *m, void *unused) |
1752 | { | |
36cdd013 | 1753 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1754 | bool sr_enabled = false; |
1755 | ||
36623ef8 | 1756 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1757 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1758 | |
7342a72c CW |
1759 | if (INTEL_GEN(dev_priv) >= 9) |
1760 | /* no global SR status; inspect per-plane WM */; | |
1761 | else if (HAS_PCH_SPLIT(dev_priv)) | |
5ba2aaaa | 1762 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1763 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1764 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1765 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1766 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1767 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1768 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1769 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1770 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1771 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1772 | |
9c870d03 | 1773 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1774 | intel_runtime_pm_put(dev_priv); |
1775 | ||
08c4d7fc | 1776 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1777 | |
1778 | return 0; | |
1779 | } | |
1780 | ||
7648fa99 JB |
1781 | static int i915_emon_status(struct seq_file *m, void *unused) |
1782 | { | |
36cdd013 DW |
1783 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1784 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1785 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1786 | int ret; |
1787 | ||
36cdd013 | 1788 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1789 | return -ENODEV; |
1790 | ||
de227ef0 CW |
1791 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1792 | if (ret) | |
1793 | return ret; | |
7648fa99 JB |
1794 | |
1795 | temp = i915_mch_val(dev_priv); | |
1796 | chipset = i915_chipset_val(dev_priv); | |
1797 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1798 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1799 | |
1800 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1801 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1802 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1803 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1804 | ||
1805 | return 0; | |
1806 | } | |
1807 | ||
23b2f8bb JB |
1808 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1809 | { | |
36cdd013 | 1810 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1811 | int ret = 0; |
23b2f8bb | 1812 | int gpu_freq, ia_freq; |
f936ec34 | 1813 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1814 | |
26310346 | 1815 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1816 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1817 | return 0; |
1818 | } | |
1819 | ||
5bfa0199 PZ |
1820 | intel_runtime_pm_get(dev_priv); |
1821 | ||
4fc688ce | 1822 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1823 | if (ret) |
5bfa0199 | 1824 | goto out; |
23b2f8bb | 1825 | |
b976dc53 | 1826 | if (IS_GEN9_BC(dev_priv)) { |
f936ec34 AG |
1827 | /* Convert GT frequency to 50 HZ units */ |
1828 | min_gpu_freq = | |
1829 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1830 | max_gpu_freq = | |
1831 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1832 | } else { | |
1833 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1834 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1835 | } | |
1836 | ||
267f0c90 | 1837 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1838 | |
f936ec34 | 1839 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1840 | ia_freq = gpu_freq; |
1841 | sandybridge_pcode_read(dev_priv, | |
1842 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1843 | &ia_freq); | |
3ebecd07 | 1844 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1845 | intel_gpu_freq(dev_priv, (gpu_freq * |
b976dc53 RV |
1846 | (IS_GEN9_BC(dev_priv) ? |
1847 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1848 | ((ia_freq >> 0) & 0xff) * 100, |
1849 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1850 | } |
1851 | ||
4fc688ce | 1852 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1853 | |
5bfa0199 PZ |
1854 | out: |
1855 | intel_runtime_pm_put(dev_priv); | |
1856 | return ret; | |
23b2f8bb JB |
1857 | } |
1858 | ||
44834a67 CW |
1859 | static int i915_opregion(struct seq_file *m, void *unused) |
1860 | { | |
36cdd013 DW |
1861 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1862 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1863 | struct intel_opregion *opregion = &dev_priv->opregion; |
1864 | int ret; | |
1865 | ||
1866 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1867 | if (ret) | |
0d38f009 | 1868 | goto out; |
44834a67 | 1869 | |
2455a8e4 JN |
1870 | if (opregion->header) |
1871 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1872 | |
1873 | mutex_unlock(&dev->struct_mutex); | |
1874 | ||
0d38f009 | 1875 | out: |
44834a67 CW |
1876 | return 0; |
1877 | } | |
1878 | ||
ada8f955 JN |
1879 | static int i915_vbt(struct seq_file *m, void *unused) |
1880 | { | |
36cdd013 | 1881 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1882 | |
1883 | if (opregion->vbt) | |
1884 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | ||
37811fcc CW |
1889 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1890 | { | |
36cdd013 DW |
1891 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1892 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1893 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1894 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1895 | int ret; |
1896 | ||
1897 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1898 | if (ret) | |
1899 | return ret; | |
37811fcc | 1900 | |
0695726e | 1901 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1902 | if (dev_priv->fbdev) { |
1903 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1904 | |
1905 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1906 | fbdev_fb->base.width, | |
1907 | fbdev_fb->base.height, | |
b00c600e | 1908 | fbdev_fb->base.format->depth, |
272725c7 | 1909 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1910 | fbdev_fb->base.modifier, |
25bcce94 CW |
1911 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1912 | describe_obj(m, fbdev_fb->obj); | |
1913 | seq_putc(m, '\n'); | |
1914 | } | |
4520f53a | 1915 | #endif |
37811fcc | 1916 | |
4b096ac1 | 1917 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1918 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1919 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1920 | if (fb == fbdev_fb) | |
37811fcc CW |
1921 | continue; |
1922 | ||
c1ca506d | 1923 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1924 | fb->base.width, |
1925 | fb->base.height, | |
b00c600e | 1926 | fb->base.format->depth, |
272725c7 | 1927 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1928 | fb->base.modifier, |
747a598f | 1929 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1930 | describe_obj(m, fb->obj); |
267f0c90 | 1931 | seq_putc(m, '\n'); |
37811fcc | 1932 | } |
4b096ac1 | 1933 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1934 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1935 | |
1936 | return 0; | |
1937 | } | |
1938 | ||
7e37f889 | 1939 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd | 1940 | { |
fe085f13 CW |
1941 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)", |
1942 | ring->space, ring->head, ring->tail); | |
c9fe99bd OM |
1943 | } |
1944 | ||
e76d3630 BW |
1945 | static int i915_context_status(struct seq_file *m, void *unused) |
1946 | { | |
36cdd013 DW |
1947 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1948 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1949 | struct intel_engine_cs *engine; |
e2efd130 | 1950 | struct i915_gem_context *ctx; |
3b3f1650 | 1951 | enum intel_engine_id id; |
c3232b18 | 1952 | int ret; |
e76d3630 | 1953 | |
f3d28878 | 1954 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1955 | if (ret) |
1956 | return ret; | |
1957 | ||
a33afea5 | 1958 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1959 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1960 | if (ctx->pid) { |
d28b99ab CW |
1961 | struct task_struct *task; |
1962 | ||
c84455b4 | 1963 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1964 | if (task) { |
1965 | seq_printf(m, "(%s [%d]) ", | |
1966 | task->comm, task->pid); | |
1967 | put_task_struct(task); | |
1968 | } | |
c84455b4 CW |
1969 | } else if (IS_ERR(ctx->file_priv)) { |
1970 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1971 | } else { |
1972 | seq_puts(m, "(kernel) "); | |
1973 | } | |
1974 | ||
bca44d80 CW |
1975 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1976 | seq_putc(m, '\n'); | |
c9fe99bd | 1977 | |
3b3f1650 | 1978 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1979 | struct intel_context *ce = &ctx->engine[engine->id]; |
1980 | ||
1981 | seq_printf(m, "%s: ", engine->name); | |
1982 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1983 | if (ce->state) | |
bf3783e5 | 1984 | describe_obj(m, ce->state->obj); |
dca33ecc | 1985 | if (ce->ring) |
7e37f889 | 1986 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1987 | seq_putc(m, '\n'); |
c9fe99bd | 1988 | } |
a33afea5 | 1989 | |
a33afea5 | 1990 | seq_putc(m, '\n'); |
a168c293 BW |
1991 | } |
1992 | ||
f3d28878 | 1993 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1994 | |
1995 | return 0; | |
1996 | } | |
1997 | ||
064ca1d2 | 1998 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 1999 | struct i915_gem_context *ctx, |
0bc40be8 | 2000 | struct intel_engine_cs *engine) |
064ca1d2 | 2001 | { |
bf3783e5 | 2002 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 2003 | struct page *page; |
064ca1d2 | 2004 | int j; |
064ca1d2 | 2005 | |
7069b144 CW |
2006 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2007 | ||
bf3783e5 CW |
2008 | if (!vma) { |
2009 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2010 | return; |
2011 | } | |
2012 | ||
bf3783e5 CW |
2013 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2014 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 2015 | i915_ggtt_offset(vma)); |
064ca1d2 | 2016 | |
a4f5ea64 | 2017 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 2018 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
2019 | return; |
2020 | } | |
2021 | ||
bf3783e5 CW |
2022 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2023 | if (page) { | |
2024 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2025 | |
2026 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2027 | seq_printf(m, |
2028 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2029 | j * 4, | |
064ca1d2 TD |
2030 | reg_state[j], reg_state[j + 1], |
2031 | reg_state[j + 2], reg_state[j + 3]); | |
2032 | } | |
2033 | kunmap_atomic(reg_state); | |
2034 | } | |
2035 | ||
a4f5ea64 | 2036 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2037 | seq_putc(m, '\n'); |
2038 | } | |
2039 | ||
c0ab1ae9 BW |
2040 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2041 | { | |
36cdd013 DW |
2042 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2043 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2044 | struct intel_engine_cs *engine; |
e2efd130 | 2045 | struct i915_gem_context *ctx; |
3b3f1650 | 2046 | enum intel_engine_id id; |
b4ac5afc | 2047 | int ret; |
c0ab1ae9 BW |
2048 | |
2049 | if (!i915.enable_execlists) { | |
2050 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2051 | return 0; | |
2052 | } | |
2053 | ||
2054 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2055 | if (ret) | |
2056 | return ret; | |
2057 | ||
e28e404c | 2058 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3b3f1650 | 2059 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2060 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2061 | |
2062 | mutex_unlock(&dev->struct_mutex); | |
2063 | ||
2064 | return 0; | |
2065 | } | |
2066 | ||
ea16a3cd DV |
2067 | static const char *swizzle_string(unsigned swizzle) |
2068 | { | |
aee56cff | 2069 | switch (swizzle) { |
ea16a3cd DV |
2070 | case I915_BIT_6_SWIZZLE_NONE: |
2071 | return "none"; | |
2072 | case I915_BIT_6_SWIZZLE_9: | |
2073 | return "bit9"; | |
2074 | case I915_BIT_6_SWIZZLE_9_10: | |
2075 | return "bit9/bit10"; | |
2076 | case I915_BIT_6_SWIZZLE_9_11: | |
2077 | return "bit9/bit11"; | |
2078 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2079 | return "bit9/bit10/bit11"; | |
2080 | case I915_BIT_6_SWIZZLE_9_17: | |
2081 | return "bit9/bit17"; | |
2082 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2083 | return "bit9/bit10/bit17"; | |
2084 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2085 | return "unknown"; |
ea16a3cd DV |
2086 | } |
2087 | ||
2088 | return "bug"; | |
2089 | } | |
2090 | ||
2091 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2092 | { | |
36cdd013 | 2093 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2094 | |
c8c8fb33 | 2095 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2096 | |
ea16a3cd DV |
2097 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2098 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2099 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2100 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2101 | ||
36cdd013 | 2102 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2103 | seq_printf(m, "DDC = 0x%08x\n", |
2104 | I915_READ(DCC)); | |
656bfa3a DV |
2105 | seq_printf(m, "DDC2 = 0x%08x\n", |
2106 | I915_READ(DCC2)); | |
ea16a3cd DV |
2107 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2108 | I915_READ16(C0DRB3)); | |
2109 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2110 | I915_READ16(C1DRB3)); | |
36cdd013 | 2111 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2112 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2113 | I915_READ(MAD_DIMM_C0)); | |
2114 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2115 | I915_READ(MAD_DIMM_C1)); | |
2116 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2117 | I915_READ(MAD_DIMM_C2)); | |
2118 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2119 | I915_READ(TILECTL)); | |
36cdd013 | 2120 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2121 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2122 | I915_READ(GAMTARBMODE)); | |
2123 | else | |
2124 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2125 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2126 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2127 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2128 | } |
656bfa3a DV |
2129 | |
2130 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2131 | seq_puts(m, "L-shaped memory detected\n"); | |
2132 | ||
c8c8fb33 | 2133 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2134 | |
2135 | return 0; | |
2136 | } | |
2137 | ||
1c60fef5 BW |
2138 | static int per_file_ctx(int id, void *ptr, void *data) |
2139 | { | |
e2efd130 | 2140 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2141 | struct seq_file *m = data; |
ae6c4806 DV |
2142 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2143 | ||
2144 | if (!ppgtt) { | |
2145 | seq_printf(m, " no ppgtt for context %d\n", | |
2146 | ctx->user_handle); | |
2147 | return 0; | |
2148 | } | |
1c60fef5 | 2149 | |
f83d6518 OM |
2150 | if (i915_gem_context_is_default(ctx)) |
2151 | seq_puts(m, " default context:\n"); | |
2152 | else | |
821d66dd | 2153 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2154 | ppgtt->debug_dump(ppgtt, m); |
2155 | ||
2156 | return 0; | |
2157 | } | |
2158 | ||
36cdd013 DW |
2159 | static void gen8_ppgtt_info(struct seq_file *m, |
2160 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2161 | { |
77df6772 | 2162 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2163 | struct intel_engine_cs *engine; |
2164 | enum intel_engine_id id; | |
b4ac5afc | 2165 | int i; |
3cf17fc5 | 2166 | |
77df6772 BW |
2167 | if (!ppgtt) |
2168 | return; | |
2169 | ||
3b3f1650 | 2170 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2171 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2172 | for (i = 0; i < 4; i++) { |
e2f80391 | 2173 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2174 | pdp <<= 32; |
e2f80391 | 2175 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2176 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2177 | } |
2178 | } | |
2179 | } | |
2180 | ||
36cdd013 DW |
2181 | static void gen6_ppgtt_info(struct seq_file *m, |
2182 | struct drm_i915_private *dev_priv) | |
77df6772 | 2183 | { |
e2f80391 | 2184 | struct intel_engine_cs *engine; |
3b3f1650 | 2185 | enum intel_engine_id id; |
3cf17fc5 | 2186 | |
7e22dbbb | 2187 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2188 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2189 | ||
3b3f1650 | 2190 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2191 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2192 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2193 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2194 | I915_READ(RING_MODE_GEN7(engine))); | |
2195 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2196 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2197 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2198 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2199 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2200 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2201 | } |
2202 | if (dev_priv->mm.aliasing_ppgtt) { | |
2203 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2204 | ||
267f0c90 | 2205 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2206 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2207 | |
87d60b63 | 2208 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2209 | } |
1c60fef5 | 2210 | |
3cf17fc5 | 2211 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2212 | } |
2213 | ||
2214 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2215 | { | |
36cdd013 DW |
2216 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2217 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2218 | struct drm_file *file; |
637ee29e | 2219 | int ret; |
77df6772 | 2220 | |
637ee29e CW |
2221 | mutex_lock(&dev->filelist_mutex); |
2222 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2223 | if (ret) |
637ee29e CW |
2224 | goto out_unlock; |
2225 | ||
c8c8fb33 | 2226 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2227 | |
36cdd013 DW |
2228 | if (INTEL_GEN(dev_priv) >= 8) |
2229 | gen8_ppgtt_info(m, dev_priv); | |
2230 | else if (INTEL_GEN(dev_priv) >= 6) | |
2231 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2232 | |
ea91e401 MT |
2233 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2234 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2235 | struct task_struct *task; |
ea91e401 | 2236 | |
7cb5dff8 | 2237 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2238 | if (!task) { |
2239 | ret = -ESRCH; | |
637ee29e | 2240 | goto out_rpm; |
06812760 | 2241 | } |
7cb5dff8 GT |
2242 | seq_printf(m, "\nproc: %s\n", task->comm); |
2243 | put_task_struct(task); | |
ea91e401 MT |
2244 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2245 | (void *)(unsigned long)m); | |
2246 | } | |
2247 | ||
637ee29e | 2248 | out_rpm: |
c8c8fb33 | 2249 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2250 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2251 | out_unlock: |
2252 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2253 | return ret; |
3cf17fc5 DV |
2254 | } |
2255 | ||
f5a4c67d CW |
2256 | static int count_irq_waiters(struct drm_i915_private *i915) |
2257 | { | |
e2f80391 | 2258 | struct intel_engine_cs *engine; |
3b3f1650 | 2259 | enum intel_engine_id id; |
f5a4c67d | 2260 | int count = 0; |
f5a4c67d | 2261 | |
3b3f1650 | 2262 | for_each_engine(engine, i915, id) |
688e6c72 | 2263 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2264 | |
2265 | return count; | |
2266 | } | |
2267 | ||
7466c291 CW |
2268 | static const char *rps_power_to_str(unsigned int power) |
2269 | { | |
2270 | static const char * const strings[] = { | |
2271 | [LOW_POWER] = "low power", | |
2272 | [BETWEEN] = "mixed", | |
2273 | [HIGH_POWER] = "high power", | |
2274 | }; | |
2275 | ||
2276 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2277 | return "unknown"; | |
2278 | ||
2279 | return strings[power]; | |
2280 | } | |
2281 | ||
1854d5ca CW |
2282 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2283 | { | |
36cdd013 DW |
2284 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2285 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2286 | struct drm_file *file; |
1854d5ca | 2287 | |
f5a4c67d | 2288 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2289 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2290 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2291 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2292 | seq_printf(m, "Frequency requested %d\n", |
2293 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2294 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2295 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2296 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2297 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2298 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2299 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2300 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2301 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2302 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2303 | |
2304 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2305 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2306 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2307 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2308 | struct task_struct *task; | |
2309 | ||
2310 | rcu_read_lock(); | |
2311 | task = pid_task(file->pid, PIDTYPE_PID); | |
2312 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2313 | task ? task->comm : "<unknown>", | |
2314 | task ? task->pid : -1, | |
2e1b8730 CW |
2315 | file_priv->rps.boosts, |
2316 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2317 | rcu_read_unlock(); |
2318 | } | |
197be2ae | 2319 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2320 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2321 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2322 | |
7466c291 CW |
2323 | if (INTEL_GEN(dev_priv) >= 6 && |
2324 | dev_priv->rps.enabled && | |
28176ef4 | 2325 | dev_priv->gt.active_requests) { |
7466c291 CW |
2326 | u32 rpup, rpupei; |
2327 | u32 rpdown, rpdownei; | |
2328 | ||
2329 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2330 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2331 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2332 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2333 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2334 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2335 | ||
2336 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2337 | rps_power_to_str(dev_priv->rps.power)); | |
2338 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
23f4a287 | 2339 | rpup && rpupei ? 100 * rpup / rpupei : 0, |
7466c291 CW |
2340 | dev_priv->rps.up_threshold); |
2341 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
23f4a287 | 2342 | rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, |
7466c291 CW |
2343 | dev_priv->rps.down_threshold); |
2344 | } else { | |
2345 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2346 | } | |
2347 | ||
8d3afd7d | 2348 | return 0; |
1854d5ca CW |
2349 | } |
2350 | ||
63573eb7 BW |
2351 | static int i915_llc(struct seq_file *m, void *data) |
2352 | { | |
36cdd013 | 2353 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2354 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2355 | |
36cdd013 | 2356 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2357 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2358 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2359 | |
2360 | return 0; | |
2361 | } | |
2362 | ||
0509ead1 AS |
2363 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2364 | { | |
2365 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2366 | struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; | |
2367 | ||
2368 | if (!HAS_HUC_UCODE(dev_priv)) | |
2369 | return 0; | |
2370 | ||
2371 | seq_puts(m, "HuC firmware status:\n"); | |
2372 | seq_printf(m, "\tpath: %s\n", huc_fw->path); | |
2373 | seq_printf(m, "\tfetch: %s\n", | |
2374 | intel_uc_fw_status_repr(huc_fw->fetch_status)); | |
2375 | seq_printf(m, "\tload: %s\n", | |
2376 | intel_uc_fw_status_repr(huc_fw->load_status)); | |
2377 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2378 | huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted); | |
2379 | seq_printf(m, "\tversion found: %d.%d\n", | |
2380 | huc_fw->major_ver_found, huc_fw->minor_ver_found); | |
2381 | seq_printf(m, "\theader: offset is %d; size = %d\n", | |
2382 | huc_fw->header_offset, huc_fw->header_size); | |
2383 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2384 | huc_fw->ucode_offset, huc_fw->ucode_size); | |
2385 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2386 | huc_fw->rsa_offset, huc_fw->rsa_size); | |
2387 | ||
3582ad13 | 2388 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2389 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2390 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2391 | |
2392 | return 0; | |
2393 | } | |
2394 | ||
fdf5d357 AD |
2395 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2396 | { | |
36cdd013 | 2397 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
db0a091b | 2398 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
fdf5d357 AD |
2399 | u32 tmp, i; |
2400 | ||
2d1fe073 | 2401 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2402 | return 0; |
2403 | ||
2404 | seq_printf(m, "GuC firmware status:\n"); | |
2405 | seq_printf(m, "\tpath: %s\n", | |
db0a091b | 2406 | guc_fw->path); |
fdf5d357 | 2407 | seq_printf(m, "\tfetch: %s\n", |
db0a091b | 2408 | intel_uc_fw_status_repr(guc_fw->fetch_status)); |
fdf5d357 | 2409 | seq_printf(m, "\tload: %s\n", |
db0a091b | 2410 | intel_uc_fw_status_repr(guc_fw->load_status)); |
fdf5d357 | 2411 | seq_printf(m, "\tversion wanted: %d.%d\n", |
db0a091b | 2412 | guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted); |
fdf5d357 | 2413 | seq_printf(m, "\tversion found: %d.%d\n", |
db0a091b | 2414 | guc_fw->major_ver_found, guc_fw->minor_ver_found); |
feda33ef AD |
2415 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2416 | guc_fw->header_offset, guc_fw->header_size); | |
2417 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2418 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2419 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2420 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 | 2421 | |
3582ad13 | 2422 | intel_runtime_pm_get(dev_priv); |
2423 | ||
fdf5d357 AD |
2424 | tmp = I915_READ(GUC_STATUS); |
2425 | ||
2426 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2427 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2428 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2429 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2430 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2431 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2432 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2433 | seq_puts(m, "\nScratch registers:\n"); | |
2434 | for (i = 0; i < 16; i++) | |
2435 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2436 | ||
3582ad13 | 2437 | intel_runtime_pm_put(dev_priv); |
2438 | ||
fdf5d357 AD |
2439 | return 0; |
2440 | } | |
2441 | ||
5aa1ee4b AG |
2442 | static void i915_guc_log_info(struct seq_file *m, |
2443 | struct drm_i915_private *dev_priv) | |
2444 | { | |
2445 | struct intel_guc *guc = &dev_priv->guc; | |
2446 | ||
2447 | seq_puts(m, "\nGuC logging stats:\n"); | |
2448 | ||
2449 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2450 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2451 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2452 | ||
2453 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2454 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2455 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2456 | ||
2457 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2458 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2459 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2460 | ||
2461 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2462 | guc->log.flush_interrupt_count); | |
2463 | ||
2464 | seq_printf(m, "\tCapture miss count: %u\n", | |
2465 | guc->log.capture_miss_count); | |
2466 | } | |
2467 | ||
8b417c26 DG |
2468 | static void i915_guc_client_info(struct seq_file *m, |
2469 | struct drm_i915_private *dev_priv, | |
2470 | struct i915_guc_client *client) | |
2471 | { | |
e2f80391 | 2472 | struct intel_engine_cs *engine; |
c18468c4 | 2473 | enum intel_engine_id id; |
8b417c26 | 2474 | uint64_t tot = 0; |
8b417c26 DG |
2475 | |
2476 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2477 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2478 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
357248bf | 2479 | client->doorbell_id, client->doorbell_offset, client->doorbell_cookie); |
8b417c26 DG |
2480 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", |
2481 | client->wq_size, client->wq_offset, client->wq_tail); | |
2482 | ||
551aaecd | 2483 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2484 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2485 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2486 | ||
3b3f1650 | 2487 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2488 | u64 submissions = client->submissions[id]; |
2489 | tot += submissions; | |
8b417c26 | 2490 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2491 | submissions, engine->name); |
8b417c26 DG |
2492 | } |
2493 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2494 | } | |
2495 | ||
2496 | static int i915_guc_info(struct seq_file *m, void *data) | |
2497 | { | |
36cdd013 | 2498 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
334636c6 | 2499 | const struct intel_guc *guc = &dev_priv->guc; |
e2f80391 | 2500 | struct intel_engine_cs *engine; |
c18468c4 | 2501 | enum intel_engine_id id; |
334636c6 | 2502 | u64 total; |
8b417c26 | 2503 | |
334636c6 CW |
2504 | if (!guc->execbuf_client) { |
2505 | seq_printf(m, "GuC submission %s\n", | |
2506 | HAS_GUC_SCHED(dev_priv) ? | |
2507 | "disabled" : | |
2508 | "not supported"); | |
5a843307 | 2509 | return 0; |
334636c6 | 2510 | } |
8b417c26 | 2511 | |
9636f6db | 2512 | seq_printf(m, "Doorbell map:\n"); |
334636c6 CW |
2513 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc->doorbell_bitmap); |
2514 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); | |
9636f6db | 2515 | |
334636c6 CW |
2516 | seq_printf(m, "GuC total action count: %llu\n", guc->action_count); |
2517 | seq_printf(m, "GuC action failure count: %u\n", guc->action_fail); | |
2518 | seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd); | |
2519 | seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status); | |
2520 | seq_printf(m, "GuC last action error code: %d\n", guc->action_err); | |
8b417c26 | 2521 | |
334636c6 | 2522 | total = 0; |
8b417c26 | 2523 | seq_printf(m, "\nGuC submissions:\n"); |
3b3f1650 | 2524 | for_each_engine(engine, dev_priv, id) { |
334636c6 | 2525 | u64 submissions = guc->submissions[id]; |
c18468c4 | 2526 | total += submissions; |
397097b0 | 2527 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
334636c6 | 2528 | engine->name, submissions, guc->last_seqno[id]); |
8b417c26 DG |
2529 | } |
2530 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2531 | ||
334636c6 CW |
2532 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2533 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
8b417c26 | 2534 | |
5aa1ee4b AG |
2535 | i915_guc_log_info(m, dev_priv); |
2536 | ||
8b417c26 DG |
2537 | /* Add more as required ... */ |
2538 | ||
2539 | return 0; | |
2540 | } | |
2541 | ||
4c7e77fc AD |
2542 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2543 | { | |
36cdd013 | 2544 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2545 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2546 | int i = 0, pg; |
2547 | ||
d6b40b4b | 2548 | if (!dev_priv->guc.log.vma) |
4c7e77fc AD |
2549 | return 0; |
2550 | ||
d6b40b4b | 2551 | obj = dev_priv->guc.log.vma->obj; |
8b797af1 CW |
2552 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { |
2553 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2554 | |
2555 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2556 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2557 | *(log + i), *(log + i + 1), | |
2558 | *(log + i + 2), *(log + i + 3)); | |
2559 | ||
2560 | kunmap_atomic(log); | |
2561 | } | |
2562 | ||
2563 | seq_putc(m, '\n'); | |
2564 | ||
2565 | return 0; | |
2566 | } | |
2567 | ||
685534ef SAK |
2568 | static int i915_guc_log_control_get(void *data, u64 *val) |
2569 | { | |
2570 | struct drm_device *dev = data; | |
2571 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2572 | ||
2573 | if (!dev_priv->guc.log.vma) | |
2574 | return -EINVAL; | |
2575 | ||
2576 | *val = i915.guc_log_level; | |
2577 | ||
2578 | return 0; | |
2579 | } | |
2580 | ||
2581 | static int i915_guc_log_control_set(void *data, u64 val) | |
2582 | { | |
2583 | struct drm_device *dev = data; | |
2584 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2585 | int ret; | |
2586 | ||
2587 | if (!dev_priv->guc.log.vma) | |
2588 | return -EINVAL; | |
2589 | ||
2590 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2591 | if (ret) | |
2592 | return ret; | |
2593 | ||
2594 | intel_runtime_pm_get(dev_priv); | |
2595 | ret = i915_guc_log_control(dev_priv, val); | |
2596 | intel_runtime_pm_put(dev_priv); | |
2597 | ||
2598 | mutex_unlock(&dev->struct_mutex); | |
2599 | return ret; | |
2600 | } | |
2601 | ||
2602 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2603 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2604 | "%lld\n"); | |
2605 | ||
b86bef20 CW |
2606 | static const char *psr2_live_status(u32 val) |
2607 | { | |
2608 | static const char * const live_status[] = { | |
2609 | "IDLE", | |
2610 | "CAPTURE", | |
2611 | "CAPTURE_FS", | |
2612 | "SLEEP", | |
2613 | "BUFON_FW", | |
2614 | "ML_UP", | |
2615 | "SU_STANDBY", | |
2616 | "FAST_SLEEP", | |
2617 | "DEEP_SLEEP", | |
2618 | "BUF_ON", | |
2619 | "TG_ON" | |
2620 | }; | |
2621 | ||
2622 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2623 | if (val < ARRAY_SIZE(live_status)) | |
2624 | return live_status[val]; | |
2625 | ||
2626 | return "unknown"; | |
2627 | } | |
2628 | ||
e91fd8c6 RV |
2629 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2630 | { | |
36cdd013 | 2631 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2632 | u32 psrperf = 0; |
a6cbdb8e RV |
2633 | u32 stat[3]; |
2634 | enum pipe pipe; | |
a031d709 | 2635 | bool enabled = false; |
e91fd8c6 | 2636 | |
36cdd013 | 2637 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2638 | seq_puts(m, "PSR not supported\n"); |
2639 | return 0; | |
2640 | } | |
2641 | ||
c8c8fb33 PZ |
2642 | intel_runtime_pm_get(dev_priv); |
2643 | ||
fa128fa6 | 2644 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2645 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2646 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2647 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2648 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2649 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2650 | dev_priv->psr.busy_frontbuffer_bits); | |
2651 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2652 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2653 | |
7e3eb599 NV |
2654 | if (HAS_DDI(dev_priv)) { |
2655 | if (dev_priv->psr.psr2_support) | |
2656 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2657 | else | |
2658 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2659 | } else { | |
3553a8ea | 2660 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2661 | enum transcoder cpu_transcoder = |
2662 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2663 | enum intel_display_power_domain power_domain; | |
2664 | ||
2665 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2666 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2667 | power_domain)) | |
2668 | continue; | |
2669 | ||
3553a8ea DL |
2670 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2671 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2672 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2673 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2674 | enabled = true; | |
9c870d03 CW |
2675 | |
2676 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2677 | } |
2678 | } | |
60e5ffe3 RV |
2679 | |
2680 | seq_printf(m, "Main link in standby mode: %s\n", | |
2681 | yesno(dev_priv->psr.link_standby)); | |
2682 | ||
a6cbdb8e RV |
2683 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2684 | ||
36cdd013 | 2685 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2686 | for_each_pipe(dev_priv, pipe) { |
2687 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2688 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2689 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2690 | } | |
2691 | seq_puts(m, "\n"); | |
e91fd8c6 | 2692 | |
05eec3c2 RV |
2693 | /* |
2694 | * VLV/CHV PSR has no kind of performance counter | |
2695 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2696 | */ | |
36cdd013 | 2697 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2698 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2699 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2700 | |
2701 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2702 | } | |
6ba1f9e1 | 2703 | if (dev_priv->psr.psr2_support) { |
b86bef20 CW |
2704 | u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL); |
2705 | ||
2706 | seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n", | |
2707 | psr2, psr2_live_status(psr2)); | |
6ba1f9e1 | 2708 | } |
fa128fa6 | 2709 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2710 | |
c8c8fb33 | 2711 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2712 | return 0; |
2713 | } | |
2714 | ||
d2e216d0 RV |
2715 | static int i915_sink_crc(struct seq_file *m, void *data) |
2716 | { | |
36cdd013 DW |
2717 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2718 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 | 2719 | struct intel_connector *connector; |
3f6a5e1e | 2720 | struct drm_connector_list_iter conn_iter; |
d2e216d0 RV |
2721 | struct intel_dp *intel_dp = NULL; |
2722 | int ret; | |
2723 | u8 crc[6]; | |
2724 | ||
2725 | drm_modeset_lock_all(dev); | |
3f6a5e1e DV |
2726 | drm_connector_list_iter_begin(dev, &conn_iter); |
2727 | for_each_intel_connector_iter(connector, &conn_iter) { | |
26c17cf6 | 2728 | struct drm_crtc *crtc; |
d2e216d0 | 2729 | |
26c17cf6 | 2730 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2731 | continue; |
2732 | ||
26c17cf6 ML |
2733 | crtc = connector->base.state->crtc; |
2734 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2735 | continue; |
2736 | ||
26c17cf6 | 2737 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2738 | continue; |
2739 | ||
26c17cf6 | 2740 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2741 | |
2742 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2743 | if (ret) | |
2744 | goto out; | |
2745 | ||
2746 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2747 | crc[0], crc[1], crc[2], | |
2748 | crc[3], crc[4], crc[5]); | |
2749 | goto out; | |
2750 | } | |
2751 | ret = -ENODEV; | |
2752 | out: | |
3f6a5e1e | 2753 | drm_connector_list_iter_end(&conn_iter); |
d2e216d0 RV |
2754 | drm_modeset_unlock_all(dev); |
2755 | return ret; | |
2756 | } | |
2757 | ||
ec013e7f JB |
2758 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2759 | { | |
36cdd013 | 2760 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2761 | u64 power; |
2762 | u32 units; | |
2763 | ||
36cdd013 | 2764 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2765 | return -ENODEV; |
2766 | ||
36623ef8 PZ |
2767 | intel_runtime_pm_get(dev_priv); |
2768 | ||
ec013e7f JB |
2769 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2770 | power = (power & 0x1f00) >> 8; | |
2771 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2772 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2773 | power *= units; | |
2774 | ||
36623ef8 PZ |
2775 | intel_runtime_pm_put(dev_priv); |
2776 | ||
ec013e7f | 2777 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2778 | |
2779 | return 0; | |
2780 | } | |
2781 | ||
6455c870 | 2782 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2783 | { |
36cdd013 | 2784 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2785 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2786 | |
a156e64d CW |
2787 | if (!HAS_RUNTIME_PM(dev_priv)) |
2788 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2789 | |
67d97da3 | 2790 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2791 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2792 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2793 | #ifdef CONFIG_PM |
a6aaec8b | 2794 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2795 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2796 | #else |
2797 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2798 | #endif | |
a156e64d | 2799 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2800 | pci_power_name(pdev->current_state), |
2801 | pdev->current_state); | |
371db66a | 2802 | |
ec013e7f JB |
2803 | return 0; |
2804 | } | |
2805 | ||
1da51581 ID |
2806 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2807 | { | |
36cdd013 | 2808 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2809 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2810 | int i; | |
2811 | ||
2812 | mutex_lock(&power_domains->lock); | |
2813 | ||
2814 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2815 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2816 | struct i915_power_well *power_well; | |
2817 | enum intel_display_power_domain power_domain; | |
2818 | ||
2819 | power_well = &power_domains->power_wells[i]; | |
2820 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2821 | power_well->count); | |
2822 | ||
8385c2ec | 2823 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2824 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2825 | intel_display_power_domain_str(power_domain), |
1da51581 | 2826 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2827 | } |
2828 | ||
2829 | mutex_unlock(&power_domains->lock); | |
2830 | ||
2831 | return 0; | |
2832 | } | |
2833 | ||
b7cec66d DL |
2834 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2835 | { | |
36cdd013 | 2836 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2837 | struct intel_csr *csr; |
2838 | ||
36cdd013 | 2839 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2840 | seq_puts(m, "not supported\n"); |
2841 | return 0; | |
2842 | } | |
2843 | ||
2844 | csr = &dev_priv->csr; | |
2845 | ||
6fb403de MK |
2846 | intel_runtime_pm_get(dev_priv); |
2847 | ||
b7cec66d DL |
2848 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2849 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2850 | ||
2851 | if (!csr->dmc_payload) | |
6fb403de | 2852 | goto out; |
b7cec66d DL |
2853 | |
2854 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2855 | CSR_VERSION_MINOR(csr->version)); | |
2856 | ||
36cdd013 | 2857 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2858 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2859 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2860 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2861 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2862 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2863 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2864 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2865 | } |
2866 | ||
6fb403de MK |
2867 | out: |
2868 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2869 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2870 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2871 | ||
8337206d DL |
2872 | intel_runtime_pm_put(dev_priv); |
2873 | ||
b7cec66d DL |
2874 | return 0; |
2875 | } | |
2876 | ||
53f5e3ca JB |
2877 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2878 | struct drm_display_mode *mode) | |
2879 | { | |
2880 | int i; | |
2881 | ||
2882 | for (i = 0; i < tabs; i++) | |
2883 | seq_putc(m, '\t'); | |
2884 | ||
2885 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2886 | mode->base.id, mode->name, | |
2887 | mode->vrefresh, mode->clock, | |
2888 | mode->hdisplay, mode->hsync_start, | |
2889 | mode->hsync_end, mode->htotal, | |
2890 | mode->vdisplay, mode->vsync_start, | |
2891 | mode->vsync_end, mode->vtotal, | |
2892 | mode->type, mode->flags); | |
2893 | } | |
2894 | ||
2895 | static void intel_encoder_info(struct seq_file *m, | |
2896 | struct intel_crtc *intel_crtc, | |
2897 | struct intel_encoder *intel_encoder) | |
2898 | { | |
36cdd013 DW |
2899 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2900 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2901 | struct drm_crtc *crtc = &intel_crtc->base; |
2902 | struct intel_connector *intel_connector; | |
2903 | struct drm_encoder *encoder; | |
2904 | ||
2905 | encoder = &intel_encoder->base; | |
2906 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2907 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2908 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2909 | struct drm_connector *connector = &intel_connector->base; | |
2910 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2911 | connector->base.id, | |
c23cc417 | 2912 | connector->name, |
53f5e3ca JB |
2913 | drm_get_connector_status_name(connector->status)); |
2914 | if (connector->status == connector_status_connected) { | |
2915 | struct drm_display_mode *mode = &crtc->mode; | |
2916 | seq_printf(m, ", mode:\n"); | |
2917 | intel_seq_print_mode(m, 2, mode); | |
2918 | } else { | |
2919 | seq_putc(m, '\n'); | |
2920 | } | |
2921 | } | |
2922 | } | |
2923 | ||
2924 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2925 | { | |
36cdd013 DW |
2926 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2927 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2928 | struct drm_crtc *crtc = &intel_crtc->base; |
2929 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2930 | struct drm_plane_state *plane_state = crtc->primary->state; |
2931 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2932 | |
23a48d53 | 2933 | if (fb) |
5aa8a937 | 2934 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2935 | fb->base.id, plane_state->src_x >> 16, |
2936 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2937 | else |
2938 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2939 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2940 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2941 | } | |
2942 | ||
2943 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2944 | { | |
2945 | struct drm_display_mode *mode = panel->fixed_mode; | |
2946 | ||
2947 | seq_printf(m, "\tfixed mode:\n"); | |
2948 | intel_seq_print_mode(m, 2, mode); | |
2949 | } | |
2950 | ||
2951 | static void intel_dp_info(struct seq_file *m, | |
2952 | struct intel_connector *intel_connector) | |
2953 | { | |
2954 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2955 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2956 | ||
2957 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2958 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2959 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2960 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2961 | |
2962 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2963 | &intel_dp->aux); | |
53f5e3ca JB |
2964 | } |
2965 | ||
9a148a96 LY |
2966 | static void intel_dp_mst_info(struct seq_file *m, |
2967 | struct intel_connector *intel_connector) | |
2968 | { | |
2969 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2970 | struct intel_dp_mst_encoder *intel_mst = | |
2971 | enc_to_mst(&intel_encoder->base); | |
2972 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2973 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2974 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2975 | intel_connector->port); | |
2976 | ||
2977 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2978 | } | |
2979 | ||
53f5e3ca JB |
2980 | static void intel_hdmi_info(struct seq_file *m, |
2981 | struct intel_connector *intel_connector) | |
2982 | { | |
2983 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2984 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2985 | ||
742f491d | 2986 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2987 | } |
2988 | ||
2989 | static void intel_lvds_info(struct seq_file *m, | |
2990 | struct intel_connector *intel_connector) | |
2991 | { | |
2992 | intel_panel_info(m, &intel_connector->panel); | |
2993 | } | |
2994 | ||
2995 | static void intel_connector_info(struct seq_file *m, | |
2996 | struct drm_connector *connector) | |
2997 | { | |
2998 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2999 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 3000 | struct drm_display_mode *mode; |
53f5e3ca JB |
3001 | |
3002 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 3003 | connector->base.id, connector->name, |
53f5e3ca JB |
3004 | drm_get_connector_status_name(connector->status)); |
3005 | if (connector->status == connector_status_connected) { | |
3006 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
3007 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
3008 | connector->display_info.width_mm, | |
3009 | connector->display_info.height_mm); | |
3010 | seq_printf(m, "\tsubpixel order: %s\n", | |
3011 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
3012 | seq_printf(m, "\tCEA rev: %d\n", | |
3013 | connector->display_info.cea_rev); | |
3014 | } | |
ee648a74 ML |
3015 | |
3016 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3017 | return; | |
3018 | ||
3019 | switch (connector->connector_type) { | |
3020 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3021 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
3022 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
3023 | intel_dp_mst_info(m, intel_connector); | |
3024 | else | |
3025 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
3026 | break; |
3027 | case DRM_MODE_CONNECTOR_LVDS: | |
3028 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 3029 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
3030 | break; |
3031 | case DRM_MODE_CONNECTOR_HDMIA: | |
3032 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
3033 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
3034 | intel_hdmi_info(m, intel_connector); | |
3035 | break; | |
3036 | default: | |
3037 | break; | |
36cd7444 | 3038 | } |
53f5e3ca | 3039 | |
f103fc7d JB |
3040 | seq_printf(m, "\tmodes:\n"); |
3041 | list_for_each_entry(mode, &connector->modes, head) | |
3042 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3043 | } |
3044 | ||
36cdd013 | 3045 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 3046 | { |
065f2ec2 CW |
3047 | u32 state; |
3048 | ||
2a307c2e | 3049 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 3050 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 3051 | else |
5efb3e28 | 3052 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
3053 | |
3054 | return state; | |
3055 | } | |
3056 | ||
36cdd013 DW |
3057 | static bool cursor_position(struct drm_i915_private *dev_priv, |
3058 | int pipe, int *x, int *y) | |
065f2ec2 | 3059 | { |
065f2ec2 CW |
3060 | u32 pos; |
3061 | ||
5efb3e28 | 3062 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
3063 | |
3064 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3065 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3066 | *x = -*x; | |
3067 | ||
3068 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3069 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3070 | *y = -*y; | |
3071 | ||
36cdd013 | 3072 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
3073 | } |
3074 | ||
3abc4e09 RF |
3075 | static const char *plane_type(enum drm_plane_type type) |
3076 | { | |
3077 | switch (type) { | |
3078 | case DRM_PLANE_TYPE_OVERLAY: | |
3079 | return "OVL"; | |
3080 | case DRM_PLANE_TYPE_PRIMARY: | |
3081 | return "PRI"; | |
3082 | case DRM_PLANE_TYPE_CURSOR: | |
3083 | return "CUR"; | |
3084 | /* | |
3085 | * Deliberately omitting default: to generate compiler warnings | |
3086 | * when a new drm_plane_type gets added. | |
3087 | */ | |
3088 | } | |
3089 | ||
3090 | return "unknown"; | |
3091 | } | |
3092 | ||
3093 | static const char *plane_rotation(unsigned int rotation) | |
3094 | { | |
3095 | static char buf[48]; | |
3096 | /* | |
3097 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3098 | * will print them all to visualize if the values are misused | |
3099 | */ | |
3100 | snprintf(buf, sizeof(buf), | |
3101 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3102 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3103 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3104 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3105 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3106 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3107 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3108 | rotation); |
3109 | ||
3110 | return buf; | |
3111 | } | |
3112 | ||
3113 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3114 | { | |
36cdd013 DW |
3115 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3116 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3117 | struct intel_plane *intel_plane; |
3118 | ||
3119 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3120 | struct drm_plane_state *state; | |
3121 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3122 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3123 | |
3124 | if (!plane->state) { | |
3125 | seq_puts(m, "plane->state is NULL!\n"); | |
3126 | continue; | |
3127 | } | |
3128 | ||
3129 | state = plane->state; | |
3130 | ||
90844f00 | 3131 | if (state->fb) { |
438b74a5 VS |
3132 | drm_get_format_name(state->fb->format->format, |
3133 | &format_name); | |
90844f00 | 3134 | } else { |
b3c11ac2 | 3135 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3136 | } |
3137 | ||
3abc4e09 RF |
3138 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3139 | plane->base.id, | |
3140 | plane_type(intel_plane->base.type), | |
3141 | state->crtc_x, state->crtc_y, | |
3142 | state->crtc_w, state->crtc_h, | |
3143 | (state->src_x >> 16), | |
3144 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3145 | (state->src_y >> 16), | |
3146 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3147 | (state->src_w >> 16), | |
3148 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3149 | (state->src_h >> 16), | |
3150 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3151 | format_name.str, |
3abc4e09 RF |
3152 | plane_rotation(state->rotation)); |
3153 | } | |
3154 | } | |
3155 | ||
3156 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3157 | { | |
3158 | struct intel_crtc_state *pipe_config; | |
3159 | int num_scalers = intel_crtc->num_scalers; | |
3160 | int i; | |
3161 | ||
3162 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3163 | ||
3164 | /* Not all platformas have a scaler */ | |
3165 | if (num_scalers) { | |
3166 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3167 | num_scalers, | |
3168 | pipe_config->scaler_state.scaler_users, | |
3169 | pipe_config->scaler_state.scaler_id); | |
3170 | ||
58415918 | 3171 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3172 | struct intel_scaler *sc = |
3173 | &pipe_config->scaler_state.scalers[i]; | |
3174 | ||
3175 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3176 | i, yesno(sc->in_use), sc->mode); | |
3177 | } | |
3178 | seq_puts(m, "\n"); | |
3179 | } else { | |
3180 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3181 | } | |
3182 | } | |
3183 | ||
53f5e3ca JB |
3184 | static int i915_display_info(struct seq_file *m, void *unused) |
3185 | { | |
36cdd013 DW |
3186 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3187 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3188 | struct intel_crtc *crtc; |
53f5e3ca | 3189 | struct drm_connector *connector; |
3f6a5e1e | 3190 | struct drm_connector_list_iter conn_iter; |
53f5e3ca | 3191 | |
b0e5ddf3 | 3192 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3193 | seq_printf(m, "CRTC info\n"); |
3194 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3195 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3196 | bool active; |
f77076c9 | 3197 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3198 | int x, y; |
53f5e3ca | 3199 | |
3f6a5e1e | 3200 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 ML |
3201 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3202 | ||
3abc4e09 | 3203 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3204 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3205 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3206 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3207 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3208 | ||
f77076c9 | 3209 | if (pipe_config->base.active) { |
065f2ec2 CW |
3210 | intel_crtc_info(m, crtc); |
3211 | ||
36cdd013 | 3212 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3213 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3214 | yesno(crtc->cursor_base), |
3dd512fb MR |
3215 | x, y, crtc->base.cursor->state->crtc_w, |
3216 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3217 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3218 | intel_scaler_info(m, crtc); |
3219 | intel_plane_info(m, crtc); | |
a23dc658 | 3220 | } |
cace841c DV |
3221 | |
3222 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3223 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3224 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
3f6a5e1e | 3225 | drm_modeset_unlock(&crtc->base.mutex); |
53f5e3ca JB |
3226 | } |
3227 | ||
3228 | seq_printf(m, "\n"); | |
3229 | seq_printf(m, "Connector info\n"); | |
3230 | seq_printf(m, "--------------\n"); | |
3f6a5e1e DV |
3231 | mutex_lock(&dev->mode_config.mutex); |
3232 | drm_connector_list_iter_begin(dev, &conn_iter); | |
3233 | drm_for_each_connector_iter(connector, &conn_iter) | |
53f5e3ca | 3234 | intel_connector_info(m, connector); |
3f6a5e1e DV |
3235 | drm_connector_list_iter_end(&conn_iter); |
3236 | mutex_unlock(&dev->mode_config.mutex); | |
3237 | ||
b0e5ddf3 | 3238 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3239 | |
3240 | return 0; | |
3241 | } | |
3242 | ||
1b36595f CW |
3243 | static int i915_engine_info(struct seq_file *m, void *unused) |
3244 | { | |
3245 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3246 | struct intel_engine_cs *engine; | |
3b3f1650 | 3247 | enum intel_engine_id id; |
1b36595f | 3248 | |
9c870d03 CW |
3249 | intel_runtime_pm_get(dev_priv); |
3250 | ||
f73b5674 CW |
3251 | seq_printf(m, "GT awake? %s\n", |
3252 | yesno(dev_priv->gt.awake)); | |
3253 | seq_printf(m, "Global active requests: %d\n", | |
3254 | dev_priv->gt.active_requests); | |
3255 | ||
3b3f1650 | 3256 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3257 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3258 | struct drm_i915_gem_request *rq; | |
3259 | struct rb_node *rb; | |
3260 | u64 addr; | |
3261 | ||
3262 | seq_printf(m, "%s\n", engine->name); | |
f73b5674 | 3263 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n", |
1b36595f | 3264 | intel_engine_get_seqno(engine), |
cb399eab | 3265 | intel_engine_last_submit(engine), |
1b36595f | 3266 | engine->hangcheck.seqno, |
f73b5674 CW |
3267 | jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp), |
3268 | engine->timeline->inflight_seqnos); | |
1b36595f CW |
3269 | |
3270 | rcu_read_lock(); | |
3271 | ||
3272 | seq_printf(m, "\tRequests:\n"); | |
3273 | ||
73cb9701 CW |
3274 | rq = list_first_entry(&engine->timeline->requests, |
3275 | struct drm_i915_gem_request, link); | |
3276 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3277 | print_request(m, rq, "\t\tfirst "); |
3278 | ||
73cb9701 CW |
3279 | rq = list_last_entry(&engine->timeline->requests, |
3280 | struct drm_i915_gem_request, link); | |
3281 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3282 | print_request(m, rq, "\t\tlast "); |
3283 | ||
3284 | rq = i915_gem_find_active_request(engine); | |
3285 | if (rq) { | |
3286 | print_request(m, rq, "\t\tactive "); | |
3287 | seq_printf(m, | |
3288 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3289 | rq->head, rq->postfix, rq->tail, | |
3290 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3291 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3292 | } | |
3293 | ||
3294 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3295 | I915_READ(RING_START(engine->mmio_base)), | |
3296 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3297 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3298 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3299 | rq ? rq->ring->head : 0); | |
3300 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3301 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3302 | rq ? rq->ring->tail : 0); | |
3303 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3304 | I915_READ(RING_CTL(engine->mmio_base)), | |
3305 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3306 | ||
3307 | rcu_read_unlock(); | |
3308 | ||
3309 | addr = intel_engine_get_active_head(engine); | |
3310 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3311 | upper_32_bits(addr), lower_32_bits(addr)); | |
3312 | addr = intel_engine_get_last_batch_head(engine); | |
3313 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3314 | upper_32_bits(addr), lower_32_bits(addr)); | |
3315 | ||
3316 | if (i915.enable_execlists) { | |
3317 | u32 ptr, read, write; | |
20311bd3 | 3318 | struct rb_node *rb; |
1b36595f CW |
3319 | |
3320 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3321 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3322 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3323 | ||
3324 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3325 | read = GEN8_CSB_READ_PTR(ptr); | |
3326 | write = GEN8_CSB_WRITE_PTR(ptr); | |
3327 | seq_printf(m, "\tExeclist CSB read %d, write %d\n", | |
3328 | read, write); | |
3329 | if (read >= GEN8_CSB_ENTRIES) | |
3330 | read = 0; | |
3331 | if (write >= GEN8_CSB_ENTRIES) | |
3332 | write = 0; | |
3333 | if (read > write) | |
3334 | write += GEN8_CSB_ENTRIES; | |
3335 | while (read < write) { | |
3336 | unsigned int idx = ++read % GEN8_CSB_ENTRIES; | |
3337 | ||
3338 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", | |
3339 | idx, | |
3340 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3341 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3342 | } | |
3343 | ||
3344 | rcu_read_lock(); | |
3345 | rq = READ_ONCE(engine->execlist_port[0].request); | |
816ee798 CW |
3346 | if (rq) { |
3347 | seq_printf(m, "\t\tELSP[0] count=%d, ", | |
3348 | engine->execlist_port[0].count); | |
3349 | print_request(m, rq, "rq: "); | |
3350 | } else { | |
1b36595f | 3351 | seq_printf(m, "\t\tELSP[0] idle\n"); |
816ee798 | 3352 | } |
1b36595f | 3353 | rq = READ_ONCE(engine->execlist_port[1].request); |
816ee798 CW |
3354 | if (rq) { |
3355 | seq_printf(m, "\t\tELSP[1] count=%d, ", | |
3356 | engine->execlist_port[1].count); | |
3357 | print_request(m, rq, "rq: "); | |
3358 | } else { | |
1b36595f | 3359 | seq_printf(m, "\t\tELSP[1] idle\n"); |
816ee798 | 3360 | } |
1b36595f | 3361 | rcu_read_unlock(); |
c8247c06 | 3362 | |
663f71e7 | 3363 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 CW |
3364 | for (rb = engine->execlist_first; rb; rb = rb_next(rb)) { |
3365 | rq = rb_entry(rb, typeof(*rq), priotree.node); | |
c8247c06 CW |
3366 | print_request(m, rq, "\t\tQ "); |
3367 | } | |
663f71e7 | 3368 | spin_unlock_irq(&engine->timeline->lock); |
1b36595f CW |
3369 | } else if (INTEL_GEN(dev_priv) > 6) { |
3370 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3371 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3372 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3373 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3374 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3375 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3376 | } | |
3377 | ||
61d3dc70 | 3378 | spin_lock_irq(&b->rb_lock); |
1b36595f | 3379 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 3380 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
1b36595f CW |
3381 | |
3382 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3383 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3384 | } | |
61d3dc70 | 3385 | spin_unlock_irq(&b->rb_lock); |
1b36595f CW |
3386 | |
3387 | seq_puts(m, "\n"); | |
3388 | } | |
3389 | ||
9c870d03 CW |
3390 | intel_runtime_pm_put(dev_priv); |
3391 | ||
1b36595f CW |
3392 | return 0; |
3393 | } | |
3394 | ||
e04934cf BW |
3395 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3396 | { | |
36cdd013 DW |
3397 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3398 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3399 | struct intel_engine_cs *engine; |
36cdd013 | 3400 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3401 | enum intel_engine_id id; |
3402 | int j, ret; | |
e04934cf | 3403 | |
39df9190 | 3404 | if (!i915.semaphores) { |
e04934cf BW |
3405 | seq_puts(m, "Semaphores are disabled\n"); |
3406 | return 0; | |
3407 | } | |
3408 | ||
3409 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3410 | if (ret) | |
3411 | return ret; | |
03872064 | 3412 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3413 | |
36cdd013 | 3414 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3415 | struct page *page; |
3416 | uint64_t *seqno; | |
3417 | ||
51d545d0 | 3418 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3419 | |
3420 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3421 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3422 | uint64_t offset; |
3423 | ||
e2f80391 | 3424 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3425 | |
3426 | seq_puts(m, " Last signal:"); | |
3427 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3428 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3429 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3430 | seqno[offset], offset * 8); | |
3431 | } | |
3432 | seq_putc(m, '\n'); | |
3433 | ||
3434 | seq_puts(m, " Last wait: "); | |
3435 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3436 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3437 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3438 | seqno[offset], offset * 8); | |
3439 | } | |
3440 | seq_putc(m, '\n'); | |
3441 | ||
3442 | } | |
3443 | kunmap_atomic(seqno); | |
3444 | } else { | |
3445 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3446 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3447 | for (j = 0; j < num_rings; j++) |
3448 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3449 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3450 | seq_putc(m, '\n'); |
3451 | } | |
3452 | ||
03872064 | 3453 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3454 | mutex_unlock(&dev->struct_mutex); |
3455 | return 0; | |
3456 | } | |
3457 | ||
728e29d7 DV |
3458 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3459 | { | |
36cdd013 DW |
3460 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3461 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3462 | int i; |
3463 | ||
3464 | drm_modeset_lock_all(dev); | |
3465 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3466 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3467 | ||
3468 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3469 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3470 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3471 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3472 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3473 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3474 | pll->state.hw_state.dpll_md); |
3475 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3476 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3477 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3478 | } |
3479 | drm_modeset_unlock_all(dev); | |
3480 | ||
3481 | return 0; | |
3482 | } | |
3483 | ||
1ed1ef9d | 3484 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3485 | { |
3486 | int i; | |
3487 | int ret; | |
e2f80391 | 3488 | struct intel_engine_cs *engine; |
36cdd013 DW |
3489 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3490 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3491 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3492 | enum intel_engine_id id; |
888b5995 | 3493 | |
888b5995 AS |
3494 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3495 | if (ret) | |
3496 | return ret; | |
3497 | ||
3498 | intel_runtime_pm_get(dev_priv); | |
3499 | ||
33136b06 | 3500 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3501 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3502 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3503 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3504 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3505 | i915_reg_t addr; |
3506 | u32 mask, value, read; | |
2fa60f6d | 3507 | bool ok; |
888b5995 | 3508 | |
33136b06 AS |
3509 | addr = workarounds->reg[i].addr; |
3510 | mask = workarounds->reg[i].mask; | |
3511 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3512 | read = I915_READ(addr); |
3513 | ok = (value & mask) == (read & mask); | |
3514 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3515 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3516 | } |
3517 | ||
3518 | intel_runtime_pm_put(dev_priv); | |
3519 | mutex_unlock(&dev->struct_mutex); | |
3520 | ||
3521 | return 0; | |
3522 | } | |
3523 | ||
c5511e44 DL |
3524 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3525 | { | |
36cdd013 DW |
3526 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3527 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3528 | struct skl_ddb_allocation *ddb; |
3529 | struct skl_ddb_entry *entry; | |
3530 | enum pipe pipe; | |
3531 | int plane; | |
3532 | ||
36cdd013 | 3533 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3534 | return 0; |
3535 | ||
c5511e44 DL |
3536 | drm_modeset_lock_all(dev); |
3537 | ||
3538 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3539 | ||
3540 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3541 | ||
3542 | for_each_pipe(dev_priv, pipe) { | |
3543 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3544 | ||
8b364b41 | 3545 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3546 | entry = &ddb->plane[pipe][plane]; |
3547 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3548 | entry->start, entry->end, | |
3549 | skl_ddb_entry_size(entry)); | |
3550 | } | |
3551 | ||
4969d33e | 3552 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3553 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3554 | entry->end, skl_ddb_entry_size(entry)); | |
3555 | } | |
3556 | ||
3557 | drm_modeset_unlock_all(dev); | |
3558 | ||
3559 | return 0; | |
3560 | } | |
3561 | ||
a54746e3 | 3562 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3563 | struct drm_device *dev, |
3564 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3565 | { |
fac5e23e | 3566 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3567 | struct i915_drrs *drrs = &dev_priv->drrs; |
3568 | int vrefresh = 0; | |
26875fe5 | 3569 | struct drm_connector *connector; |
3f6a5e1e | 3570 | struct drm_connector_list_iter conn_iter; |
a54746e3 | 3571 | |
3f6a5e1e DV |
3572 | drm_connector_list_iter_begin(dev, &conn_iter); |
3573 | drm_for_each_connector_iter(connector, &conn_iter) { | |
26875fe5 ML |
3574 | if (connector->state->crtc != &intel_crtc->base) |
3575 | continue; | |
3576 | ||
3577 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 | 3578 | } |
3f6a5e1e | 3579 | drm_connector_list_iter_end(&conn_iter); |
a54746e3 VK |
3580 | |
3581 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3582 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3583 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3584 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3585 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3586 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3587 | else | |
3588 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3589 | ||
3590 | seq_puts(m, "\n\n"); | |
3591 | ||
f77076c9 | 3592 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3593 | struct intel_panel *panel; |
3594 | ||
3595 | mutex_lock(&drrs->mutex); | |
3596 | /* DRRS Supported */ | |
3597 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3598 | ||
3599 | /* disable_drrs() will make drrs->dp NULL */ | |
3600 | if (!drrs->dp) { | |
3601 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3602 | mutex_unlock(&drrs->mutex); | |
3603 | return; | |
3604 | } | |
3605 | ||
3606 | panel = &drrs->dp->attached_connector->panel; | |
3607 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3608 | drrs->busy_frontbuffer_bits); | |
3609 | ||
3610 | seq_puts(m, "\n\t\t"); | |
3611 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3612 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3613 | vrefresh = panel->fixed_mode->vrefresh; | |
3614 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3615 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3616 | vrefresh = panel->downclock_mode->vrefresh; | |
3617 | } else { | |
3618 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3619 | drrs->refresh_rate_type); | |
3620 | mutex_unlock(&drrs->mutex); | |
3621 | return; | |
3622 | } | |
3623 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3624 | ||
3625 | seq_puts(m, "\n\t\t"); | |
3626 | mutex_unlock(&drrs->mutex); | |
3627 | } else { | |
3628 | /* DRRS not supported. Print the VBT parameter*/ | |
3629 | seq_puts(m, "\tDRRS Supported : No"); | |
3630 | } | |
3631 | seq_puts(m, "\n"); | |
3632 | } | |
3633 | ||
3634 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3635 | { | |
36cdd013 DW |
3636 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3637 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3638 | struct intel_crtc *intel_crtc; |
3639 | int active_crtc_cnt = 0; | |
3640 | ||
26875fe5 | 3641 | drm_modeset_lock_all(dev); |
a54746e3 | 3642 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3643 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3644 | active_crtc_cnt++; |
3645 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3646 | ||
3647 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3648 | } | |
a54746e3 | 3649 | } |
26875fe5 | 3650 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3651 | |
3652 | if (!active_crtc_cnt) | |
3653 | seq_puts(m, "No active crtc found\n"); | |
3654 | ||
3655 | return 0; | |
3656 | } | |
3657 | ||
11bed958 DA |
3658 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3659 | { | |
36cdd013 DW |
3660 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3661 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3662 | struct intel_encoder *intel_encoder; |
3663 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b | 3664 | struct drm_connector *connector; |
3f6a5e1e | 3665 | struct drm_connector_list_iter conn_iter; |
b6dabe3b | 3666 | |
3f6a5e1e DV |
3667 | drm_connector_list_iter_begin(dev, &conn_iter); |
3668 | drm_for_each_connector_iter(connector, &conn_iter) { | |
b6dabe3b | 3669 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
11bed958 | 3670 | continue; |
b6dabe3b ML |
3671 | |
3672 | intel_encoder = intel_attached_encoder(connector); | |
3673 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3674 | continue; | |
3675 | ||
3676 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3677 | if (!intel_dig_port->dp.can_mst) |
3678 | continue; | |
b6dabe3b | 3679 | |
40ae80cc JB |
3680 | seq_printf(m, "MST Source Port %c\n", |
3681 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3682 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3683 | } | |
3f6a5e1e DV |
3684 | drm_connector_list_iter_end(&conn_iter); |
3685 | ||
11bed958 DA |
3686 | return 0; |
3687 | } | |
3688 | ||
eb3394fa | 3689 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3690 | const char __user *ubuf, |
3691 | size_t len, loff_t *offp) | |
eb3394fa TP |
3692 | { |
3693 | char *input_buffer; | |
3694 | int status = 0; | |
eb3394fa TP |
3695 | struct drm_device *dev; |
3696 | struct drm_connector *connector; | |
3f6a5e1e | 3697 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3698 | struct intel_dp *intel_dp; |
3699 | int val = 0; | |
3700 | ||
9aaffa34 | 3701 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3702 | |
eb3394fa TP |
3703 | if (len == 0) |
3704 | return 0; | |
3705 | ||
3706 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
3707 | if (!input_buffer) | |
3708 | return -ENOMEM; | |
3709 | ||
3710 | if (copy_from_user(input_buffer, ubuf, len)) { | |
3711 | status = -EFAULT; | |
3712 | goto out; | |
3713 | } | |
3714 | ||
3715 | input_buffer[len] = '\0'; | |
3716 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
3717 | ||
3f6a5e1e DV |
3718 | drm_connector_list_iter_begin(dev, &conn_iter); |
3719 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3720 | if (connector->connector_type != |
3721 | DRM_MODE_CONNECTOR_DisplayPort) | |
3722 | continue; | |
3723 | ||
b8bb08ec | 3724 | if (connector->status == connector_status_connected && |
eb3394fa TP |
3725 | connector->encoder != NULL) { |
3726 | intel_dp = enc_to_intel_dp(connector->encoder); | |
3727 | status = kstrtoint(input_buffer, 10, &val); | |
3728 | if (status < 0) | |
3f6a5e1e | 3729 | break; |
eb3394fa TP |
3730 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); |
3731 | /* To prevent erroneous activation of the compliance | |
3732 | * testing code, only accept an actual value of 1 here | |
3733 | */ | |
3734 | if (val == 1) | |
c1617abc | 3735 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3736 | else |
c1617abc | 3737 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3738 | } |
3739 | } | |
3f6a5e1e | 3740 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3741 | out: |
3742 | kfree(input_buffer); | |
3743 | if (status < 0) | |
3744 | return status; | |
3745 | ||
3746 | *offp += len; | |
3747 | return len; | |
3748 | } | |
3749 | ||
3750 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3751 | { | |
3752 | struct drm_device *dev = m->private; | |
3753 | struct drm_connector *connector; | |
3f6a5e1e | 3754 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3755 | struct intel_dp *intel_dp; |
3756 | ||
3f6a5e1e DV |
3757 | drm_connector_list_iter_begin(dev, &conn_iter); |
3758 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3759 | if (connector->connector_type != |
3760 | DRM_MODE_CONNECTOR_DisplayPort) | |
3761 | continue; | |
3762 | ||
3763 | if (connector->status == connector_status_connected && | |
3764 | connector->encoder != NULL) { | |
3765 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3766 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3767 | seq_puts(m, "1"); |
3768 | else | |
3769 | seq_puts(m, "0"); | |
3770 | } else | |
3771 | seq_puts(m, "0"); | |
3772 | } | |
3f6a5e1e | 3773 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3774 | |
3775 | return 0; | |
3776 | } | |
3777 | ||
3778 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3779 | struct file *file) |
eb3394fa | 3780 | { |
36cdd013 | 3781 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3782 | |
36cdd013 DW |
3783 | return single_open(file, i915_displayport_test_active_show, |
3784 | &dev_priv->drm); | |
eb3394fa TP |
3785 | } |
3786 | ||
3787 | static const struct file_operations i915_displayport_test_active_fops = { | |
3788 | .owner = THIS_MODULE, | |
3789 | .open = i915_displayport_test_active_open, | |
3790 | .read = seq_read, | |
3791 | .llseek = seq_lseek, | |
3792 | .release = single_release, | |
3793 | .write = i915_displayport_test_active_write | |
3794 | }; | |
3795 | ||
3796 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3797 | { | |
3798 | struct drm_device *dev = m->private; | |
3799 | struct drm_connector *connector; | |
3f6a5e1e | 3800 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3801 | struct intel_dp *intel_dp; |
3802 | ||
3f6a5e1e DV |
3803 | drm_connector_list_iter_begin(dev, &conn_iter); |
3804 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3805 | if (connector->connector_type != |
3806 | DRM_MODE_CONNECTOR_DisplayPort) | |
3807 | continue; | |
3808 | ||
3809 | if (connector->status == connector_status_connected && | |
3810 | connector->encoder != NULL) { | |
3811 | intel_dp = enc_to_intel_dp(connector->encoder); | |
b48a5ba9 MN |
3812 | if (intel_dp->compliance.test_type == |
3813 | DP_TEST_LINK_EDID_READ) | |
3814 | seq_printf(m, "%lx", | |
3815 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3816 | else if (intel_dp->compliance.test_type == |
3817 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3818 | seq_printf(m, "hdisplay: %d\n", | |
3819 | intel_dp->compliance.test_data.hdisplay); | |
3820 | seq_printf(m, "vdisplay: %d\n", | |
3821 | intel_dp->compliance.test_data.vdisplay); | |
3822 | seq_printf(m, "bpc: %u\n", | |
3823 | intel_dp->compliance.test_data.bpc); | |
3824 | } | |
eb3394fa TP |
3825 | } else |
3826 | seq_puts(m, "0"); | |
3827 | } | |
3f6a5e1e | 3828 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3829 | |
3830 | return 0; | |
3831 | } | |
3832 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3833 | struct file *file) |
eb3394fa | 3834 | { |
36cdd013 | 3835 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3836 | |
36cdd013 DW |
3837 | return single_open(file, i915_displayport_test_data_show, |
3838 | &dev_priv->drm); | |
eb3394fa TP |
3839 | } |
3840 | ||
3841 | static const struct file_operations i915_displayport_test_data_fops = { | |
3842 | .owner = THIS_MODULE, | |
3843 | .open = i915_displayport_test_data_open, | |
3844 | .read = seq_read, | |
3845 | .llseek = seq_lseek, | |
3846 | .release = single_release | |
3847 | }; | |
3848 | ||
3849 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3850 | { | |
3851 | struct drm_device *dev = m->private; | |
3852 | struct drm_connector *connector; | |
3f6a5e1e | 3853 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3854 | struct intel_dp *intel_dp; |
3855 | ||
3f6a5e1e DV |
3856 | drm_connector_list_iter_begin(dev, &conn_iter); |
3857 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3858 | if (connector->connector_type != |
3859 | DRM_MODE_CONNECTOR_DisplayPort) | |
3860 | continue; | |
3861 | ||
3862 | if (connector->status == connector_status_connected && | |
3863 | connector->encoder != NULL) { | |
3864 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3865 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3866 | } else |
3867 | seq_puts(m, "0"); | |
3868 | } | |
3f6a5e1e | 3869 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3870 | |
3871 | return 0; | |
3872 | } | |
3873 | ||
3874 | static int i915_displayport_test_type_open(struct inode *inode, | |
3875 | struct file *file) | |
3876 | { | |
36cdd013 | 3877 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3878 | |
36cdd013 DW |
3879 | return single_open(file, i915_displayport_test_type_show, |
3880 | &dev_priv->drm); | |
eb3394fa TP |
3881 | } |
3882 | ||
3883 | static const struct file_operations i915_displayport_test_type_fops = { | |
3884 | .owner = THIS_MODULE, | |
3885 | .open = i915_displayport_test_type_open, | |
3886 | .read = seq_read, | |
3887 | .llseek = seq_lseek, | |
3888 | .release = single_release | |
3889 | }; | |
3890 | ||
97e94b22 | 3891 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3892 | { |
36cdd013 DW |
3893 | struct drm_i915_private *dev_priv = m->private; |
3894 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3895 | int level; |
de38b95c VS |
3896 | int num_levels; |
3897 | ||
36cdd013 | 3898 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3899 | num_levels = 3; |
36cdd013 | 3900 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
3901 | num_levels = 1; |
3902 | else | |
5db94019 | 3903 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3904 | |
3905 | drm_modeset_lock_all(dev); | |
3906 | ||
3907 | for (level = 0; level < num_levels; level++) { | |
3908 | unsigned int latency = wm[level]; | |
3909 | ||
97e94b22 DL |
3910 | /* |
3911 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3912 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3913 | */ |
36cdd013 DW |
3914 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
3915 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
3916 | latency *= 10; |
3917 | else if (level > 0) | |
369a1342 VS |
3918 | latency *= 5; |
3919 | ||
3920 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3921 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3922 | } |
3923 | ||
3924 | drm_modeset_unlock_all(dev); | |
3925 | } | |
3926 | ||
3927 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3928 | { | |
36cdd013 | 3929 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3930 | const uint16_t *latencies; |
3931 | ||
36cdd013 | 3932 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3933 | latencies = dev_priv->wm.skl_latency; |
3934 | else | |
36cdd013 | 3935 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3936 | |
97e94b22 | 3937 | wm_latency_show(m, latencies); |
369a1342 VS |
3938 | |
3939 | return 0; | |
3940 | } | |
3941 | ||
3942 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3943 | { | |
36cdd013 | 3944 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3945 | const uint16_t *latencies; |
3946 | ||
36cdd013 | 3947 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3948 | latencies = dev_priv->wm.skl_latency; |
3949 | else | |
36cdd013 | 3950 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3951 | |
97e94b22 | 3952 | wm_latency_show(m, latencies); |
369a1342 VS |
3953 | |
3954 | return 0; | |
3955 | } | |
3956 | ||
3957 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3958 | { | |
36cdd013 | 3959 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3960 | const uint16_t *latencies; |
3961 | ||
36cdd013 | 3962 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3963 | latencies = dev_priv->wm.skl_latency; |
3964 | else | |
36cdd013 | 3965 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3966 | |
97e94b22 | 3967 | wm_latency_show(m, latencies); |
369a1342 VS |
3968 | |
3969 | return 0; | |
3970 | } | |
3971 | ||
3972 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3973 | { | |
36cdd013 | 3974 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3975 | |
36cdd013 | 3976 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
3977 | return -ENODEV; |
3978 | ||
36cdd013 | 3979 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3980 | } |
3981 | ||
3982 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3983 | { | |
36cdd013 | 3984 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3985 | |
36cdd013 | 3986 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3987 | return -ENODEV; |
3988 | ||
36cdd013 | 3989 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3990 | } |
3991 | ||
3992 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3993 | { | |
36cdd013 | 3994 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3995 | |
36cdd013 | 3996 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3997 | return -ENODEV; |
3998 | ||
36cdd013 | 3999 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
4000 | } |
4001 | ||
4002 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4003 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4004 | { |
4005 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
4006 | struct drm_i915_private *dev_priv = m->private; |
4007 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 4008 | uint16_t new[8] = { 0 }; |
de38b95c | 4009 | int num_levels; |
369a1342 VS |
4010 | int level; |
4011 | int ret; | |
4012 | char tmp[32]; | |
4013 | ||
36cdd013 | 4014 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4015 | num_levels = 3; |
36cdd013 | 4016 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4017 | num_levels = 1; |
4018 | else | |
5db94019 | 4019 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 4020 | |
369a1342 VS |
4021 | if (len >= sizeof(tmp)) |
4022 | return -EINVAL; | |
4023 | ||
4024 | if (copy_from_user(tmp, ubuf, len)) | |
4025 | return -EFAULT; | |
4026 | ||
4027 | tmp[len] = '\0'; | |
4028 | ||
97e94b22 DL |
4029 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4030 | &new[0], &new[1], &new[2], &new[3], | |
4031 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4032 | if (ret != num_levels) |
4033 | return -EINVAL; | |
4034 | ||
4035 | drm_modeset_lock_all(dev); | |
4036 | ||
4037 | for (level = 0; level < num_levels; level++) | |
4038 | wm[level] = new[level]; | |
4039 | ||
4040 | drm_modeset_unlock_all(dev); | |
4041 | ||
4042 | return len; | |
4043 | } | |
4044 | ||
4045 | ||
4046 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4047 | size_t len, loff_t *offp) | |
4048 | { | |
4049 | struct seq_file *m = file->private_data; | |
36cdd013 | 4050 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4051 | uint16_t *latencies; |
369a1342 | 4052 | |
36cdd013 | 4053 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4054 | latencies = dev_priv->wm.skl_latency; |
4055 | else | |
36cdd013 | 4056 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4057 | |
4058 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4059 | } |
4060 | ||
4061 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4062 | size_t len, loff_t *offp) | |
4063 | { | |
4064 | struct seq_file *m = file->private_data; | |
36cdd013 | 4065 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4066 | uint16_t *latencies; |
369a1342 | 4067 | |
36cdd013 | 4068 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4069 | latencies = dev_priv->wm.skl_latency; |
4070 | else | |
36cdd013 | 4071 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4072 | |
4073 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4074 | } |
4075 | ||
4076 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4077 | size_t len, loff_t *offp) | |
4078 | { | |
4079 | struct seq_file *m = file->private_data; | |
36cdd013 | 4080 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4081 | uint16_t *latencies; |
4082 | ||
36cdd013 | 4083 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4084 | latencies = dev_priv->wm.skl_latency; |
4085 | else | |
36cdd013 | 4086 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4087 | |
97e94b22 | 4088 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4089 | } |
4090 | ||
4091 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4092 | .owner = THIS_MODULE, | |
4093 | .open = pri_wm_latency_open, | |
4094 | .read = seq_read, | |
4095 | .llseek = seq_lseek, | |
4096 | .release = single_release, | |
4097 | .write = pri_wm_latency_write | |
4098 | }; | |
4099 | ||
4100 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4101 | .owner = THIS_MODULE, | |
4102 | .open = spr_wm_latency_open, | |
4103 | .read = seq_read, | |
4104 | .llseek = seq_lseek, | |
4105 | .release = single_release, | |
4106 | .write = spr_wm_latency_write | |
4107 | }; | |
4108 | ||
4109 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4110 | .owner = THIS_MODULE, | |
4111 | .open = cur_wm_latency_open, | |
4112 | .read = seq_read, | |
4113 | .llseek = seq_lseek, | |
4114 | .release = single_release, | |
4115 | .write = cur_wm_latency_write | |
4116 | }; | |
4117 | ||
647416f9 KC |
4118 | static int |
4119 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4120 | { |
36cdd013 | 4121 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4122 | |
d98c52cf | 4123 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4124 | |
647416f9 | 4125 | return 0; |
f3cd474b CW |
4126 | } |
4127 | ||
647416f9 KC |
4128 | static int |
4129 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4130 | { |
36cdd013 | 4131 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 4132 | |
b8d24a06 MK |
4133 | /* |
4134 | * There is no safeguard against this debugfs entry colliding | |
4135 | * with the hangcheck calling same i915_handle_error() in | |
4136 | * parallel, causing an explosion. For now we assume that the | |
4137 | * test harness is responsible enough not to inject gpu hangs | |
4138 | * while it is writing to 'i915_wedged' | |
4139 | */ | |
4140 | ||
8c185eca | 4141 | if (i915_reset_backoff(&dev_priv->gpu_error)) |
b8d24a06 MK |
4142 | return -EAGAIN; |
4143 | ||
c033666a | 4144 | i915_handle_error(dev_priv, val, |
58174462 | 4145 | "Manually setting wedged to %llu", val); |
d46c0517 | 4146 | |
d3df42b7 CW |
4147 | wait_on_bit(&dev_priv->gpu_error.flags, |
4148 | I915_RESET_HANDOFF, | |
4149 | TASK_UNINTERRUPTIBLE); | |
4150 | ||
647416f9 | 4151 | return 0; |
f3cd474b CW |
4152 | } |
4153 | ||
647416f9 KC |
4154 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4155 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4156 | "%llu\n"); |
f3cd474b | 4157 | |
64486ae7 CW |
4158 | static int |
4159 | fault_irq_set(struct drm_i915_private *i915, | |
4160 | unsigned long *irq, | |
4161 | unsigned long val) | |
4162 | { | |
4163 | int err; | |
4164 | ||
4165 | err = mutex_lock_interruptible(&i915->drm.struct_mutex); | |
4166 | if (err) | |
4167 | return err; | |
4168 | ||
4169 | err = i915_gem_wait_for_idle(i915, | |
4170 | I915_WAIT_LOCKED | | |
4171 | I915_WAIT_INTERRUPTIBLE); | |
4172 | if (err) | |
4173 | goto err_unlock; | |
4174 | ||
4175 | /* Retire to kick idle work */ | |
4176 | i915_gem_retire_requests(i915); | |
4177 | GEM_BUG_ON(i915->gt.active_requests); | |
4178 | ||
4179 | *irq = val; | |
4180 | mutex_unlock(&i915->drm.struct_mutex); | |
4181 | ||
4182 | /* Flush idle worker to disarm irq */ | |
4183 | while (flush_delayed_work(&i915->gt.idle_work)) | |
4184 | ; | |
4185 | ||
4186 | return 0; | |
4187 | ||
4188 | err_unlock: | |
4189 | mutex_unlock(&i915->drm.struct_mutex); | |
4190 | return err; | |
4191 | } | |
4192 | ||
094f9a54 CW |
4193 | static int |
4194 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4195 | { | |
36cdd013 | 4196 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4197 | |
4198 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4199 | return 0; | |
4200 | } | |
4201 | ||
4202 | static int | |
4203 | i915_ring_missed_irq_set(void *data, u64 val) | |
4204 | { | |
64486ae7 | 4205 | struct drm_i915_private *i915 = data; |
094f9a54 | 4206 | |
64486ae7 | 4207 | return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val); |
094f9a54 CW |
4208 | } |
4209 | ||
4210 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4211 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4212 | "0x%08llx\n"); | |
4213 | ||
4214 | static int | |
4215 | i915_ring_test_irq_get(void *data, u64 *val) | |
4216 | { | |
36cdd013 | 4217 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4218 | |
4219 | *val = dev_priv->gpu_error.test_irq_rings; | |
4220 | ||
4221 | return 0; | |
4222 | } | |
4223 | ||
4224 | static int | |
4225 | i915_ring_test_irq_set(void *data, u64 val) | |
4226 | { | |
64486ae7 | 4227 | struct drm_i915_private *i915 = data; |
094f9a54 | 4228 | |
64486ae7 | 4229 | val &= INTEL_INFO(i915)->ring_mask; |
094f9a54 | 4230 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4231 | |
64486ae7 | 4232 | return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val); |
094f9a54 CW |
4233 | } |
4234 | ||
4235 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4236 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4237 | "0x%08llx\n"); | |
4238 | ||
dd624afd CW |
4239 | #define DROP_UNBOUND 0x1 |
4240 | #define DROP_BOUND 0x2 | |
4241 | #define DROP_RETIRE 0x4 | |
4242 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 | 4243 | #define DROP_FREED 0x10 |
8eadc19b | 4244 | #define DROP_SHRINK_ALL 0x20 |
fbbd37b3 CW |
4245 | #define DROP_ALL (DROP_UNBOUND | \ |
4246 | DROP_BOUND | \ | |
4247 | DROP_RETIRE | \ | |
4248 | DROP_ACTIVE | \ | |
8eadc19b CW |
4249 | DROP_FREED | \ |
4250 | DROP_SHRINK_ALL) | |
647416f9 KC |
4251 | static int |
4252 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4253 | { |
647416f9 | 4254 | *val = DROP_ALL; |
dd624afd | 4255 | |
647416f9 | 4256 | return 0; |
dd624afd CW |
4257 | } |
4258 | ||
647416f9 KC |
4259 | static int |
4260 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4261 | { |
36cdd013 DW |
4262 | struct drm_i915_private *dev_priv = data; |
4263 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4264 | int ret; |
dd624afd | 4265 | |
2f9fe5ff | 4266 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4267 | |
4268 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4269 | * on ioctls on -EAGAIN. */ | |
4270 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4271 | if (ret) | |
4272 | return ret; | |
4273 | ||
4274 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4275 | ret = i915_gem_wait_for_idle(dev_priv, |
4276 | I915_WAIT_INTERRUPTIBLE | | |
4277 | I915_WAIT_LOCKED); | |
dd624afd CW |
4278 | if (ret) |
4279 | goto unlock; | |
4280 | } | |
4281 | ||
4282 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4283 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4284 | |
05df49e7 | 4285 | lockdep_set_current_reclaim_state(GFP_KERNEL); |
21ab4e74 CW |
4286 | if (val & DROP_BOUND) |
4287 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4288 | |
21ab4e74 CW |
4289 | if (val & DROP_UNBOUND) |
4290 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd | 4291 | |
8eadc19b CW |
4292 | if (val & DROP_SHRINK_ALL) |
4293 | i915_gem_shrink_all(dev_priv); | |
05df49e7 | 4294 | lockdep_clear_current_reclaim_state(); |
8eadc19b | 4295 | |
dd624afd CW |
4296 | unlock: |
4297 | mutex_unlock(&dev->struct_mutex); | |
4298 | ||
fbbd37b3 CW |
4299 | if (val & DROP_FREED) { |
4300 | synchronize_rcu(); | |
bdeb9785 | 4301 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4302 | } |
4303 | ||
647416f9 | 4304 | return ret; |
dd624afd CW |
4305 | } |
4306 | ||
647416f9 KC |
4307 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4308 | i915_drop_caches_get, i915_drop_caches_set, | |
4309 | "0x%08llx\n"); | |
dd624afd | 4310 | |
647416f9 KC |
4311 | static int |
4312 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4313 | { |
36cdd013 | 4314 | struct drm_i915_private *dev_priv = data; |
004777cb | 4315 | |
36cdd013 | 4316 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4317 | return -ENODEV; |
4318 | ||
7c59a9c1 | 4319 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4320 | return 0; |
358733e9 JB |
4321 | } |
4322 | ||
647416f9 KC |
4323 | static int |
4324 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4325 | { |
36cdd013 | 4326 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4327 | u32 hw_max, hw_min; |
647416f9 | 4328 | int ret; |
004777cb | 4329 | |
36cdd013 | 4330 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4331 | return -ENODEV; |
358733e9 | 4332 | |
647416f9 | 4333 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4334 | |
4fc688ce | 4335 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4336 | if (ret) |
4337 | return ret; | |
4338 | ||
358733e9 JB |
4339 | /* |
4340 | * Turbo will still be enabled, but won't go above the set value. | |
4341 | */ | |
bc4d91f6 | 4342 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4343 | |
bc4d91f6 AG |
4344 | hw_max = dev_priv->rps.max_freq; |
4345 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4346 | |
b39fb297 | 4347 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4348 | mutex_unlock(&dev_priv->rps.hw_lock); |
4349 | return -EINVAL; | |
0a073b84 JB |
4350 | } |
4351 | ||
b39fb297 | 4352 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4353 | |
9fcee2f7 CW |
4354 | if (intel_set_rps(dev_priv, val)) |
4355 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4356 | |
4fc688ce | 4357 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4358 | |
647416f9 | 4359 | return 0; |
358733e9 JB |
4360 | } |
4361 | ||
647416f9 KC |
4362 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4363 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4364 | "%llu\n"); |
358733e9 | 4365 | |
647416f9 KC |
4366 | static int |
4367 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4368 | { |
36cdd013 | 4369 | struct drm_i915_private *dev_priv = data; |
004777cb | 4370 | |
62e1baa1 | 4371 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4372 | return -ENODEV; |
4373 | ||
7c59a9c1 | 4374 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4375 | return 0; |
1523c310 JB |
4376 | } |
4377 | ||
647416f9 KC |
4378 | static int |
4379 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4380 | { |
36cdd013 | 4381 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4382 | u32 hw_max, hw_min; |
647416f9 | 4383 | int ret; |
004777cb | 4384 | |
62e1baa1 | 4385 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4386 | return -ENODEV; |
1523c310 | 4387 | |
647416f9 | 4388 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4389 | |
4fc688ce | 4390 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4391 | if (ret) |
4392 | return ret; | |
4393 | ||
1523c310 JB |
4394 | /* |
4395 | * Turbo will still be enabled, but won't go below the set value. | |
4396 | */ | |
bc4d91f6 | 4397 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4398 | |
bc4d91f6 AG |
4399 | hw_max = dev_priv->rps.max_freq; |
4400 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4401 | |
36cdd013 DW |
4402 | if (val < hw_min || |
4403 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4404 | mutex_unlock(&dev_priv->rps.hw_lock); |
4405 | return -EINVAL; | |
0a073b84 | 4406 | } |
dd0a1aa1 | 4407 | |
b39fb297 | 4408 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4409 | |
9fcee2f7 CW |
4410 | if (intel_set_rps(dev_priv, val)) |
4411 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4412 | |
4fc688ce | 4413 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4414 | |
647416f9 | 4415 | return 0; |
1523c310 JB |
4416 | } |
4417 | ||
647416f9 KC |
4418 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4419 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4420 | "%llu\n"); |
1523c310 | 4421 | |
647416f9 KC |
4422 | static int |
4423 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4424 | { |
36cdd013 | 4425 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4426 | u32 snpcr; |
07b7ddd9 | 4427 | |
36cdd013 | 4428 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4429 | return -ENODEV; |
4430 | ||
c8c8fb33 | 4431 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4432 | |
07b7ddd9 | 4433 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4434 | |
4435 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4436 | |
647416f9 | 4437 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4438 | |
647416f9 | 4439 | return 0; |
07b7ddd9 JB |
4440 | } |
4441 | ||
647416f9 KC |
4442 | static int |
4443 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4444 | { |
36cdd013 | 4445 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4446 | u32 snpcr; |
07b7ddd9 | 4447 | |
36cdd013 | 4448 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4449 | return -ENODEV; |
4450 | ||
647416f9 | 4451 | if (val > 3) |
07b7ddd9 JB |
4452 | return -EINVAL; |
4453 | ||
c8c8fb33 | 4454 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4455 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4456 | |
4457 | /* Update the cache sharing policy here as well */ | |
4458 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4459 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4460 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4461 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4462 | ||
c8c8fb33 | 4463 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4464 | return 0; |
07b7ddd9 JB |
4465 | } |
4466 | ||
647416f9 KC |
4467 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4468 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4469 | "%llu\n"); | |
07b7ddd9 | 4470 | |
36cdd013 | 4471 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4472 | struct sseu_dev_info *sseu) |
5d39525a | 4473 | { |
0a0b457f | 4474 | int ss_max = 2; |
5d39525a JM |
4475 | int ss; |
4476 | u32 sig1[ss_max], sig2[ss_max]; | |
4477 | ||
4478 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4479 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4480 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4481 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4482 | ||
4483 | for (ss = 0; ss < ss_max; ss++) { | |
4484 | unsigned int eu_cnt; | |
4485 | ||
4486 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4487 | /* skip disabled subslice */ | |
4488 | continue; | |
4489 | ||
f08a0c92 | 4490 | sseu->slice_mask = BIT(0); |
57ec171e | 4491 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4492 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4493 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4494 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4495 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4496 | sseu->eu_total += eu_cnt; |
4497 | sseu->eu_per_subslice = max_t(unsigned int, | |
4498 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4499 | } |
5d39525a JM |
4500 | } |
4501 | ||
36cdd013 | 4502 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4503 | struct sseu_dev_info *sseu) |
5d39525a | 4504 | { |
1c046bc1 | 4505 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4506 | int s, ss; |
4507 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4508 | ||
1c046bc1 | 4509 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4510 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4511 | s_max = 1; |
4512 | ss_max = 3; | |
4513 | } | |
4514 | ||
4515 | for (s = 0; s < s_max; s++) { | |
4516 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4517 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4518 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4519 | } | |
4520 | ||
5d39525a JM |
4521 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4522 | GEN9_PGCTL_SSA_EU19_ACK | | |
4523 | GEN9_PGCTL_SSA_EU210_ACK | | |
4524 | GEN9_PGCTL_SSA_EU311_ACK; | |
4525 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4526 | GEN9_PGCTL_SSB_EU19_ACK | | |
4527 | GEN9_PGCTL_SSB_EU210_ACK | | |
4528 | GEN9_PGCTL_SSB_EU311_ACK; | |
4529 | ||
4530 | for (s = 0; s < s_max; s++) { | |
4531 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4532 | /* skip disabled slice */ | |
4533 | continue; | |
4534 | ||
f08a0c92 | 4535 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4536 | |
b976dc53 | 4537 | if (IS_GEN9_BC(dev_priv)) |
57ec171e ID |
4538 | sseu->subslice_mask = |
4539 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4540 | |
5d39525a JM |
4541 | for (ss = 0; ss < ss_max; ss++) { |
4542 | unsigned int eu_cnt; | |
4543 | ||
cc3f90f0 | 4544 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4545 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4546 | /* skip disabled subslice */ | |
4547 | continue; | |
1c046bc1 | 4548 | |
57ec171e ID |
4549 | sseu->subslice_mask |= BIT(ss); |
4550 | } | |
1c046bc1 | 4551 | |
5d39525a JM |
4552 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4553 | eu_mask[ss%2]); | |
915490d5 ID |
4554 | sseu->eu_total += eu_cnt; |
4555 | sseu->eu_per_subslice = max_t(unsigned int, | |
4556 | sseu->eu_per_subslice, | |
4557 | eu_cnt); | |
5d39525a JM |
4558 | } |
4559 | } | |
4560 | } | |
4561 | ||
36cdd013 | 4562 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4563 | struct sseu_dev_info *sseu) |
91bedd34 | 4564 | { |
91bedd34 | 4565 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4566 | int s; |
91bedd34 | 4567 | |
f08a0c92 | 4568 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4569 | |
f08a0c92 | 4570 | if (sseu->slice_mask) { |
57ec171e | 4571 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4572 | sseu->eu_per_subslice = |
4573 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4574 | sseu->eu_total = sseu->eu_per_subslice * |
4575 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4576 | |
4577 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4578 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4579 | u8 subslice_7eu = |
4580 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4581 | |
915490d5 | 4582 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4583 | } |
4584 | } | |
4585 | } | |
4586 | ||
615d8908 ID |
4587 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4588 | const struct sseu_dev_info *sseu) | |
4589 | { | |
4590 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4591 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4592 | ||
c67ba538 ID |
4593 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4594 | sseu->slice_mask); | |
615d8908 | 4595 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4596 | hweight8(sseu->slice_mask)); |
615d8908 | 4597 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4598 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4599 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4600 | sseu->subslice_mask); | |
615d8908 | 4601 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4602 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4603 | seq_printf(m, " %s EU Total: %u\n", type, |
4604 | sseu->eu_total); | |
4605 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4606 | sseu->eu_per_subslice); | |
4607 | ||
4608 | if (!is_available_info) | |
4609 | return; | |
4610 | ||
4611 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4612 | if (HAS_POOLED_EU(dev_priv)) | |
4613 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4614 | ||
4615 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4616 | yesno(sseu->has_slice_pg)); | |
4617 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4618 | yesno(sseu->has_subslice_pg)); | |
4619 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4620 | yesno(sseu->has_eu_pg)); | |
4621 | } | |
4622 | ||
3873218f JM |
4623 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4624 | { | |
36cdd013 | 4625 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4626 | struct sseu_dev_info sseu; |
3873218f | 4627 | |
36cdd013 | 4628 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4629 | return -ENODEV; |
4630 | ||
4631 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4632 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4633 | |
7f992aba | 4634 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4635 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4636 | |
4637 | intel_runtime_pm_get(dev_priv); | |
4638 | ||
36cdd013 | 4639 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4640 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4641 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4642 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4643 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 4644 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 4645 | } |
238010ed DW |
4646 | |
4647 | intel_runtime_pm_put(dev_priv); | |
4648 | ||
615d8908 | 4649 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4650 | |
3873218f JM |
4651 | return 0; |
4652 | } | |
4653 | ||
6d794d42 BW |
4654 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4655 | { | |
36cdd013 | 4656 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4657 | |
36cdd013 | 4658 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4659 | return 0; |
4660 | ||
6daccb0b | 4661 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4662 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4663 | |
4664 | return 0; | |
4665 | } | |
4666 | ||
c43b5634 | 4667 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4668 | { |
36cdd013 | 4669 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4670 | |
36cdd013 | 4671 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4672 | return 0; |
4673 | ||
59bad947 | 4674 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4675 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4676 | |
4677 | return 0; | |
4678 | } | |
4679 | ||
4680 | static const struct file_operations i915_forcewake_fops = { | |
4681 | .owner = THIS_MODULE, | |
4682 | .open = i915_forcewake_open, | |
4683 | .release = i915_forcewake_release, | |
4684 | }; | |
4685 | ||
317eaa95 L |
4686 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4687 | { | |
4688 | struct drm_i915_private *dev_priv = m->private; | |
4689 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4690 | ||
4691 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4692 | seq_printf(m, "Detected: %s\n", | |
4693 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4694 | ||
4695 | return 0; | |
4696 | } | |
4697 | ||
4698 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4699 | const char __user *ubuf, size_t len, | |
4700 | loff_t *offp) | |
4701 | { | |
4702 | struct seq_file *m = file->private_data; | |
4703 | struct drm_i915_private *dev_priv = m->private; | |
4704 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4705 | unsigned int new_threshold; | |
4706 | int i; | |
4707 | char *newline; | |
4708 | char tmp[16]; | |
4709 | ||
4710 | if (len >= sizeof(tmp)) | |
4711 | return -EINVAL; | |
4712 | ||
4713 | if (copy_from_user(tmp, ubuf, len)) | |
4714 | return -EFAULT; | |
4715 | ||
4716 | tmp[len] = '\0'; | |
4717 | ||
4718 | /* Strip newline, if any */ | |
4719 | newline = strchr(tmp, '\n'); | |
4720 | if (newline) | |
4721 | *newline = '\0'; | |
4722 | ||
4723 | if (strcmp(tmp, "reset") == 0) | |
4724 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4725 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4726 | return -EINVAL; | |
4727 | ||
4728 | if (new_threshold > 0) | |
4729 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4730 | new_threshold); | |
4731 | else | |
4732 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4733 | ||
4734 | spin_lock_irq(&dev_priv->irq_lock); | |
4735 | hotplug->hpd_storm_threshold = new_threshold; | |
4736 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4737 | for_each_hpd_pin(i) | |
4738 | hotplug->stats[i].count = 0; | |
4739 | spin_unlock_irq(&dev_priv->irq_lock); | |
4740 | ||
4741 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4742 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4743 | ||
4744 | return len; | |
4745 | } | |
4746 | ||
4747 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4748 | { | |
4749 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4750 | } | |
4751 | ||
4752 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4753 | .owner = THIS_MODULE, | |
4754 | .open = i915_hpd_storm_ctl_open, | |
4755 | .read = seq_read, | |
4756 | .llseek = seq_lseek, | |
4757 | .release = single_release, | |
4758 | .write = i915_hpd_storm_ctl_write | |
4759 | }; | |
4760 | ||
06c5bf8c | 4761 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4762 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4763 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4764 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 4765 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 4766 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 4767 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
4768 | {"i915_gem_request", i915_gem_request_info, 0}, |
4769 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4770 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4771 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4772 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4773 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4774 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4775 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
0509ead1 | 4776 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4777 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4778 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 4779 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4780 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4781 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4782 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4783 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4784 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4785 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4786 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4787 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4788 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4789 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4790 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 4791 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4792 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4793 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4794 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4795 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4796 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4797 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4798 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4799 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4800 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4801 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4802 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 4803 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4804 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4805 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4806 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4807 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4808 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4809 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4810 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4811 | }; |
27c202ad | 4812 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4813 | |
06c5bf8c | 4814 | static const struct i915_debugfs_files { |
34b9674c DV |
4815 | const char *name; |
4816 | const struct file_operations *fops; | |
4817 | } i915_debugfs_files[] = { | |
4818 | {"i915_wedged", &i915_wedged_fops}, | |
4819 | {"i915_max_freq", &i915_max_freq_fops}, | |
4820 | {"i915_min_freq", &i915_min_freq_fops}, | |
4821 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4822 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4823 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4824 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4825 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4826 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4827 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4828 | #endif |
34b9674c | 4829 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4830 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4831 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4832 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4833 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4834 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
4835 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4836 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4837 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
317eaa95 L |
4838 | {"i915_guc_log_control", &i915_guc_log_control_fops}, |
4839 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops} | |
34b9674c DV |
4840 | }; |
4841 | ||
1dac891c | 4842 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4843 | { |
91c8a326 | 4844 | struct drm_minor *minor = dev_priv->drm.primary; |
b05eeb0f | 4845 | struct dentry *ent; |
34b9674c | 4846 | int ret, i; |
f3cd474b | 4847 | |
b05eeb0f NT |
4848 | ent = debugfs_create_file("i915_forcewake_user", S_IRUSR, |
4849 | minor->debugfs_root, to_i915(minor->dev), | |
4850 | &i915_forcewake_fops); | |
4851 | if (!ent) | |
4852 | return -ENOMEM; | |
6a9c308d | 4853 | |
731035fe TV |
4854 | ret = intel_pipe_crc_create(minor); |
4855 | if (ret) | |
4856 | return ret; | |
07144428 | 4857 | |
34b9674c | 4858 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
b05eeb0f NT |
4859 | ent = debugfs_create_file(i915_debugfs_files[i].name, |
4860 | S_IRUGO | S_IWUSR, | |
4861 | minor->debugfs_root, | |
4862 | to_i915(minor->dev), | |
34b9674c | 4863 | i915_debugfs_files[i].fops); |
b05eeb0f NT |
4864 | if (!ent) |
4865 | return -ENOMEM; | |
34b9674c | 4866 | } |
40633219 | 4867 | |
27c202ad BG |
4868 | return drm_debugfs_create_files(i915_debugfs_list, |
4869 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4870 | minor->debugfs_root, minor); |
4871 | } | |
4872 | ||
aa7471d2 JN |
4873 | struct dpcd_block { |
4874 | /* DPCD dump start address. */ | |
4875 | unsigned int offset; | |
4876 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4877 | unsigned int end; | |
4878 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4879 | size_t size; | |
4880 | /* Only valid for eDP. */ | |
4881 | bool edp; | |
4882 | }; | |
4883 | ||
4884 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4885 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4886 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4887 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4888 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4889 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4890 | { .offset = DP_SET_POWER }, | |
4891 | { .offset = DP_EDP_DPCD_REV }, | |
4892 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4893 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4894 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4895 | }; | |
4896 | ||
4897 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4898 | { | |
4899 | struct drm_connector *connector = m->private; | |
4900 | struct intel_dp *intel_dp = | |
4901 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4902 | uint8_t buf[16]; | |
4903 | ssize_t err; | |
4904 | int i; | |
4905 | ||
5c1a8875 MK |
4906 | if (connector->status != connector_status_connected) |
4907 | return -ENODEV; | |
4908 | ||
aa7471d2 JN |
4909 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4910 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4911 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4912 | ||
4913 | if (b->edp && | |
4914 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4915 | continue; | |
4916 | ||
4917 | /* low tech for now */ | |
4918 | if (WARN_ON(size > sizeof(buf))) | |
4919 | continue; | |
4920 | ||
4921 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4922 | if (err <= 0) { | |
4923 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4924 | size, b->offset, err); | |
4925 | continue; | |
4926 | } | |
4927 | ||
4928 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4929 | } |
aa7471d2 JN |
4930 | |
4931 | return 0; | |
4932 | } | |
4933 | ||
4934 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4935 | { | |
4936 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4937 | } | |
4938 | ||
4939 | static const struct file_operations i915_dpcd_fops = { | |
4940 | .owner = THIS_MODULE, | |
4941 | .open = i915_dpcd_open, | |
4942 | .read = seq_read, | |
4943 | .llseek = seq_lseek, | |
4944 | .release = single_release, | |
4945 | }; | |
4946 | ||
ecbd6781 DW |
4947 | static int i915_panel_show(struct seq_file *m, void *data) |
4948 | { | |
4949 | struct drm_connector *connector = m->private; | |
4950 | struct intel_dp *intel_dp = | |
4951 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4952 | ||
4953 | if (connector->status != connector_status_connected) | |
4954 | return -ENODEV; | |
4955 | ||
4956 | seq_printf(m, "Panel power up delay: %d\n", | |
4957 | intel_dp->panel_power_up_delay); | |
4958 | seq_printf(m, "Panel power down delay: %d\n", | |
4959 | intel_dp->panel_power_down_delay); | |
4960 | seq_printf(m, "Backlight on delay: %d\n", | |
4961 | intel_dp->backlight_on_delay); | |
4962 | seq_printf(m, "Backlight off delay: %d\n", | |
4963 | intel_dp->backlight_off_delay); | |
4964 | ||
4965 | return 0; | |
4966 | } | |
4967 | ||
4968 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4969 | { | |
4970 | return single_open(file, i915_panel_show, inode->i_private); | |
4971 | } | |
4972 | ||
4973 | static const struct file_operations i915_panel_fops = { | |
4974 | .owner = THIS_MODULE, | |
4975 | .open = i915_panel_open, | |
4976 | .read = seq_read, | |
4977 | .llseek = seq_lseek, | |
4978 | .release = single_release, | |
4979 | }; | |
4980 | ||
aa7471d2 JN |
4981 | /** |
4982 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4983 | * @connector: pointer to a registered drm_connector | |
4984 | * | |
4985 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4986 | * drm_debugfs_connector_remove(). | |
4987 | * | |
4988 | * Returns 0 on success, negative error codes on error. | |
4989 | */ | |
4990 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4991 | { | |
4992 | struct dentry *root = connector->debugfs_entry; | |
4993 | ||
4994 | /* The connector must have been registered beforehands. */ | |
4995 | if (!root) | |
4996 | return -ENODEV; | |
4997 | ||
4998 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
4999 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
5000 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
5001 | connector, &i915_dpcd_fops); | |
5002 | ||
5003 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5004 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
5005 | connector, &i915_panel_fops); | |
aa7471d2 JN |
5006 | |
5007 | return 0; | |
5008 | } |