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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
497666d8 DL |
54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
55 | * allocated we need to hook into the minor for release. */ | |
56 | static int | |
57 | drm_add_fake_info_node(struct drm_minor *minor, | |
58 | struct dentry *ent, | |
59 | const void *key) | |
60 | { | |
61 | struct drm_info_node *node; | |
62 | ||
63 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
64 | if (node == NULL) { | |
65 | debugfs_remove(ent); | |
66 | return -ENOMEM; | |
67 | } | |
68 | ||
69 | node->minor = minor; | |
70 | node->dent = ent; | |
71 | node->info_ent = (void *) key; | |
72 | ||
73 | mutex_lock(&minor->debugfs_lock); | |
74 | list_add(&node->list, &minor->debugfs_list); | |
75 | mutex_unlock(&minor->debugfs_lock); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
70d39fe4 CW |
80 | static int i915_capabilities(struct seq_file *m, void *data) |
81 | { | |
82 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
83 | struct drm_device *dev = node->minor->dev; | |
84 | const struct intel_device_info *info = INTEL_INFO(dev); | |
85 | ||
86 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
89 | #define SEP_SEMICOLON ; | |
90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
91 | #undef PRINT_FLAG | |
92 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
93 | |
94 | return 0; | |
95 | } | |
2017263e | 96 | |
05394f39 | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 98 | { |
05394f39 | 99 | if (obj->user_pin_count > 0) |
a6172a80 | 100 | return "P"; |
05394f39 | 101 | else if (obj->pin_count > 0) |
a6172a80 CW |
102 | return "p"; |
103 | else | |
104 | return " "; | |
105 | } | |
106 | ||
05394f39 | 107 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 108 | { |
0206e353 AJ |
109 | switch (obj->tiling_mode) { |
110 | default: | |
111 | case I915_TILING_NONE: return " "; | |
112 | case I915_TILING_X: return "X"; | |
113 | case I915_TILING_Y: return "Y"; | |
114 | } | |
a6172a80 CW |
115 | } |
116 | ||
1d693bcc BW |
117 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
118 | { | |
119 | return obj->has_global_gtt_mapping ? "g" : " "; | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
1d693bcc | 125 | struct i915_vma *vma; |
fb1ae911 | 126 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
127 | &obj->base, |
128 | get_pin_flag(obj), | |
129 | get_tiling_flag(obj), | |
1d693bcc | 130 | get_global_flag(obj), |
a05a5862 | 131 | obj->base.size / 1024, |
37811fcc CW |
132 | obj->base.read_domains, |
133 | obj->base.write_domain, | |
0201f1ec CW |
134 | obj->last_read_seqno, |
135 | obj->last_write_seqno, | |
caea7476 | 136 | obj->last_fenced_seqno, |
84734a04 | 137 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
138 | obj->dirty ? " dirty" : "", |
139 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
140 | if (obj->base.name) | |
141 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
142 | if (obj->pin_count) |
143 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
144 | if (obj->pin_display) |
145 | seq_printf(m, " (display)"); | |
37811fcc CW |
146 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
147 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
148 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
149 | if (!i915_is_ggtt(vma->vm)) | |
150 | seq_puts(m, " (pp"); | |
151 | else | |
152 | seq_puts(m, " (g"); | |
153 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
154 | vma->node.start, vma->node.size); | |
155 | } | |
c1ad11fc CW |
156 | if (obj->stolen) |
157 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
158 | if (obj->pin_mappable || obj->fault_mappable) { |
159 | char s[3], *t = s; | |
160 | if (obj->pin_mappable) | |
161 | *t++ = 'p'; | |
162 | if (obj->fault_mappable) | |
163 | *t++ = 'f'; | |
164 | *t = '\0'; | |
165 | seq_printf(m, " (%s mappable)", s); | |
166 | } | |
69dc4987 CW |
167 | if (obj->ring != NULL) |
168 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
169 | } |
170 | ||
3ccfd19d BW |
171 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
172 | { | |
173 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
174 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
175 | seq_putc(m, ' '); | |
176 | } | |
177 | ||
433e12f7 | 178 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
179 | { |
180 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
181 | uintptr_t list = (uintptr_t) node->info_ent->data; |
182 | struct list_head *head; | |
2017263e | 183 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
184 | struct drm_i915_private *dev_priv = dev->dev_private; |
185 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 186 | struct i915_vma *vma; |
8f2480fb CW |
187 | size_t total_obj_size, total_gtt_size; |
188 | int count, ret; | |
de227ef0 CW |
189 | |
190 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
191 | if (ret) | |
192 | return ret; | |
2017263e | 193 | |
ca191b13 | 194 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
195 | switch (list) { |
196 | case ACTIVE_LIST: | |
267f0c90 | 197 | seq_puts(m, "Active:\n"); |
5cef07e1 | 198 | head = &vm->active_list; |
433e12f7 BG |
199 | break; |
200 | case INACTIVE_LIST: | |
267f0c90 | 201 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 202 | head = &vm->inactive_list; |
433e12f7 | 203 | break; |
433e12f7 | 204 | default: |
de227ef0 CW |
205 | mutex_unlock(&dev->struct_mutex); |
206 | return -EINVAL; | |
2017263e | 207 | } |
2017263e | 208 | |
8f2480fb | 209 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
210 | list_for_each_entry(vma, head, mm_list) { |
211 | seq_printf(m, " "); | |
212 | describe_obj(m, vma->obj); | |
213 | seq_printf(m, "\n"); | |
214 | total_obj_size += vma->obj->base.size; | |
215 | total_gtt_size += vma->node.size; | |
8f2480fb | 216 | count++; |
2017263e | 217 | } |
de227ef0 | 218 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 219 | |
8f2480fb CW |
220 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
221 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
222 | return 0; |
223 | } | |
224 | ||
6d2b8885 CW |
225 | static int obj_rank_by_stolen(void *priv, |
226 | struct list_head *A, struct list_head *B) | |
227 | { | |
228 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 229 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 230 | struct drm_i915_gem_object *b = |
b25cb2f8 | 231 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
232 | |
233 | return a->stolen->start - b->stolen->start; | |
234 | } | |
235 | ||
236 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
237 | { | |
238 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
239 | struct drm_device *dev = node->minor->dev; | |
240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241 | struct drm_i915_gem_object *obj; | |
242 | size_t total_obj_size, total_gtt_size; | |
243 | LIST_HEAD(stolen); | |
244 | int count, ret; | |
245 | ||
246 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
247 | if (ret) | |
248 | return ret; | |
249 | ||
250 | total_obj_size = total_gtt_size = count = 0; | |
251 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
252 | if (obj->stolen == NULL) | |
253 | continue; | |
254 | ||
b25cb2f8 | 255 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
256 | |
257 | total_obj_size += obj->base.size; | |
258 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
259 | count++; | |
260 | } | |
261 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
262 | if (obj->stolen == NULL) | |
263 | continue; | |
264 | ||
b25cb2f8 | 265 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
266 | |
267 | total_obj_size += obj->base.size; | |
268 | count++; | |
269 | } | |
270 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
271 | seq_puts(m, "Stolen:\n"); | |
272 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 273 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
274 | seq_puts(m, " "); |
275 | describe_obj(m, obj); | |
276 | seq_putc(m, '\n'); | |
b25cb2f8 | 277 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
278 | } |
279 | mutex_unlock(&dev->struct_mutex); | |
280 | ||
281 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
282 | count, total_obj_size, total_gtt_size); | |
283 | return 0; | |
284 | } | |
285 | ||
6299f992 CW |
286 | #define count_objects(list, member) do { \ |
287 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 288 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
289 | ++count; \ |
290 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 291 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
292 | ++mappable_count; \ |
293 | } \ | |
294 | } \ | |
0206e353 | 295 | } while (0) |
6299f992 | 296 | |
2db8e9d6 CW |
297 | struct file_stats { |
298 | int count; | |
299 | size_t total, active, inactive, unbound; | |
300 | }; | |
301 | ||
302 | static int per_file_stats(int id, void *ptr, void *data) | |
303 | { | |
304 | struct drm_i915_gem_object *obj = ptr; | |
305 | struct file_stats *stats = data; | |
306 | ||
307 | stats->count++; | |
308 | stats->total += obj->base.size; | |
309 | ||
f343c5f6 | 310 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
311 | if (!list_empty(&obj->ring_list)) |
312 | stats->active += obj->base.size; | |
313 | else | |
314 | stats->inactive += obj->base.size; | |
315 | } else { | |
316 | if (!list_empty(&obj->global_list)) | |
317 | stats->unbound += obj->base.size; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
ca191b13 BW |
323 | #define count_vmas(list, member) do { \ |
324 | list_for_each_entry(vma, list, member) { \ | |
325 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
326 | ++count; \ | |
327 | if (vma->obj->map_and_fenceable) { \ | |
328 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
329 | ++mappable_count; \ | |
330 | } \ | |
331 | } \ | |
332 | } while (0) | |
333 | ||
334 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
335 | { |
336 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
337 | struct drm_device *dev = node->minor->dev; | |
338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
339 | u32 count, mappable_count, purgeable_count; |
340 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 341 | struct drm_i915_gem_object *obj; |
5cef07e1 | 342 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 343 | struct drm_file *file; |
ca191b13 | 344 | struct i915_vma *vma; |
73aa808f CW |
345 | int ret; |
346 | ||
347 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
348 | if (ret) | |
349 | return ret; | |
350 | ||
6299f992 CW |
351 | seq_printf(m, "%u objects, %zu bytes\n", |
352 | dev_priv->mm.object_count, | |
353 | dev_priv->mm.object_memory); | |
354 | ||
355 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 356 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
357 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
358 | count, mappable_count, size, mappable_size); | |
359 | ||
360 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 361 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
362 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
363 | count, mappable_count, size, mappable_size); | |
364 | ||
6299f992 | 365 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 366 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
367 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
368 | count, mappable_count, size, mappable_size); | |
369 | ||
b7abb714 | 370 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 371 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 372 | size += obj->base.size, ++count; |
b7abb714 CW |
373 | if (obj->madv == I915_MADV_DONTNEED) |
374 | purgeable_size += obj->base.size, ++purgeable_count; | |
375 | } | |
6c085a72 CW |
376 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
377 | ||
6299f992 | 378 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 379 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 380 | if (obj->fault_mappable) { |
f343c5f6 | 381 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
382 | ++count; |
383 | } | |
384 | if (obj->pin_mappable) { | |
f343c5f6 | 385 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
386 | ++mappable_count; |
387 | } | |
b7abb714 CW |
388 | if (obj->madv == I915_MADV_DONTNEED) { |
389 | purgeable_size += obj->base.size; | |
390 | ++purgeable_count; | |
391 | } | |
6299f992 | 392 | } |
b7abb714 CW |
393 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
394 | purgeable_count, purgeable_size); | |
6299f992 CW |
395 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
396 | mappable_count, mappable_size); | |
397 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
398 | count, size); | |
399 | ||
93d18799 | 400 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
401 | dev_priv->gtt.base.total, |
402 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 403 | |
267f0c90 | 404 | seq_putc(m, '\n'); |
2db8e9d6 CW |
405 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
406 | struct file_stats stats; | |
3ec2f427 | 407 | struct task_struct *task; |
2db8e9d6 CW |
408 | |
409 | memset(&stats, 0, sizeof(stats)); | |
410 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
3ec2f427 TH |
411 | /* |
412 | * Although we have a valid reference on file->pid, that does | |
413 | * not guarantee that the task_struct who called get_pid() is | |
414 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
415 | * Therefore, we need to protect this ->comm access using RCU. | |
416 | */ | |
417 | rcu_read_lock(); | |
418 | task = pid_task(file->pid, PIDTYPE_PID); | |
2db8e9d6 | 419 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", |
3ec2f427 | 420 | task ? task->comm : "<unknown>", |
2db8e9d6 CW |
421 | stats.count, |
422 | stats.total, | |
423 | stats.active, | |
424 | stats.inactive, | |
425 | stats.unbound); | |
3ec2f427 | 426 | rcu_read_unlock(); |
2db8e9d6 CW |
427 | } |
428 | ||
73aa808f CW |
429 | mutex_unlock(&dev->struct_mutex); |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
aee56cff | 434 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
435 | { |
436 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
437 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 438 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
439 | struct drm_i915_private *dev_priv = dev->dev_private; |
440 | struct drm_i915_gem_object *obj; | |
441 | size_t total_obj_size, total_gtt_size; | |
442 | int count, ret; | |
443 | ||
444 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
445 | if (ret) | |
446 | return ret; | |
447 | ||
448 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 449 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
450 | if (list == PINNED_LIST && obj->pin_count == 0) |
451 | continue; | |
452 | ||
267f0c90 | 453 | seq_puts(m, " "); |
08c18323 | 454 | describe_obj(m, obj); |
267f0c90 | 455 | seq_putc(m, '\n'); |
08c18323 | 456 | total_obj_size += obj->base.size; |
f343c5f6 | 457 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
458 | count++; |
459 | } | |
460 | ||
461 | mutex_unlock(&dev->struct_mutex); | |
462 | ||
463 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
464 | count, total_obj_size, total_gtt_size); | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
4e5359cd SF |
469 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
470 | { | |
471 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
472 | struct drm_device *dev = node->minor->dev; | |
473 | unsigned long flags; | |
474 | struct intel_crtc *crtc; | |
475 | ||
476 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
477 | const char pipe = pipe_name(crtc->pipe); |
478 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
479 | struct intel_unpin_work *work; |
480 | ||
481 | spin_lock_irqsave(&dev->event_lock, flags); | |
482 | work = crtc->unpin_work; | |
483 | if (work == NULL) { | |
9db4a9c7 | 484 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
485 | pipe, plane); |
486 | } else { | |
e7d841ca | 487 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 488 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
489 | pipe, plane); |
490 | } else { | |
9db4a9c7 | 491 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
492 | pipe, plane); |
493 | } | |
494 | if (work->enable_stall_check) | |
267f0c90 | 495 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 496 | else |
267f0c90 | 497 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 498 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
499 | |
500 | if (work->old_fb_obj) { | |
05394f39 CW |
501 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
502 | if (obj) | |
f343c5f6 BW |
503 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
504 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
505 | } |
506 | if (work->pending_flip_obj) { | |
05394f39 CW |
507 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
508 | if (obj) | |
f343c5f6 BW |
509 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
510 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
511 | } |
512 | } | |
513 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
514 | } | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
2017263e BG |
519 | static int i915_gem_request_info(struct seq_file *m, void *data) |
520 | { | |
521 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
522 | struct drm_device *dev = node->minor->dev; | |
523 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 524 | struct intel_ring_buffer *ring; |
2017263e | 525 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 526 | int ret, count, i; |
de227ef0 CW |
527 | |
528 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
529 | if (ret) | |
530 | return ret; | |
2017263e | 531 | |
c2c347a9 | 532 | count = 0; |
a2c7f6fd CW |
533 | for_each_ring(ring, dev_priv, i) { |
534 | if (list_empty(&ring->request_list)) | |
535 | continue; | |
536 | ||
537 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 538 | list_for_each_entry(gem_request, |
a2c7f6fd | 539 | &ring->request_list, |
c2c347a9 CW |
540 | list) { |
541 | seq_printf(m, " %d @ %d\n", | |
542 | gem_request->seqno, | |
543 | (int) (jiffies - gem_request->emitted_jiffies)); | |
544 | } | |
545 | count++; | |
2017263e | 546 | } |
de227ef0 CW |
547 | mutex_unlock(&dev->struct_mutex); |
548 | ||
c2c347a9 | 549 | if (count == 0) |
267f0c90 | 550 | seq_puts(m, "No requests\n"); |
c2c347a9 | 551 | |
2017263e BG |
552 | return 0; |
553 | } | |
554 | ||
b2223497 CW |
555 | static void i915_ring_seqno_info(struct seq_file *m, |
556 | struct intel_ring_buffer *ring) | |
557 | { | |
558 | if (ring->get_seqno) { | |
43a7b924 | 559 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 560 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
561 | } |
562 | } | |
563 | ||
2017263e BG |
564 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
565 | { | |
566 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
567 | struct drm_device *dev = node->minor->dev; | |
568 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 569 | struct intel_ring_buffer *ring; |
1ec14ad3 | 570 | int ret, i; |
de227ef0 CW |
571 | |
572 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
573 | if (ret) | |
574 | return ret; | |
c8c8fb33 | 575 | intel_runtime_pm_get(dev_priv); |
2017263e | 576 | |
a2c7f6fd CW |
577 | for_each_ring(ring, dev_priv, i) |
578 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 579 | |
c8c8fb33 | 580 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
581 | mutex_unlock(&dev->struct_mutex); |
582 | ||
2017263e BG |
583 | return 0; |
584 | } | |
585 | ||
586 | ||
587 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
588 | { | |
589 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
590 | struct drm_device *dev = node->minor->dev; | |
591 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 592 | struct intel_ring_buffer *ring; |
9db4a9c7 | 593 | int ret, i, pipe; |
de227ef0 CW |
594 | |
595 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
596 | if (ret) | |
597 | return ret; | |
c8c8fb33 | 598 | intel_runtime_pm_get(dev_priv); |
2017263e | 599 | |
a123f157 BW |
600 | if (INTEL_INFO(dev)->gen >= 8) { |
601 | int i; | |
602 | seq_printf(m, "Master Interrupt Control:\t%08x\n", | |
603 | I915_READ(GEN8_MASTER_IRQ)); | |
604 | ||
605 | for (i = 0; i < 4; i++) { | |
606 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
607 | i, I915_READ(GEN8_GT_IMR(i))); | |
608 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
609 | i, I915_READ(GEN8_GT_IIR(i))); | |
610 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
611 | i, I915_READ(GEN8_GT_IER(i))); | |
612 | } | |
613 | ||
614 | for_each_pipe(i) { | |
615 | seq_printf(m, "Pipe %c IMR:\t%08x\n", | |
616 | pipe_name(i), | |
617 | I915_READ(GEN8_DE_PIPE_IMR(i))); | |
618 | seq_printf(m, "Pipe %c IIR:\t%08x\n", | |
619 | pipe_name(i), | |
620 | I915_READ(GEN8_DE_PIPE_IIR(i))); | |
621 | seq_printf(m, "Pipe %c IER:\t%08x\n", | |
622 | pipe_name(i), | |
623 | I915_READ(GEN8_DE_PIPE_IER(i))); | |
624 | } | |
625 | ||
626 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
627 | I915_READ(GEN8_DE_PORT_IMR)); | |
628 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
629 | I915_READ(GEN8_DE_PORT_IIR)); | |
630 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
631 | I915_READ(GEN8_DE_PORT_IER)); | |
632 | ||
633 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
634 | I915_READ(GEN8_DE_MISC_IMR)); | |
635 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
636 | I915_READ(GEN8_DE_MISC_IIR)); | |
637 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
638 | I915_READ(GEN8_DE_MISC_IER)); | |
639 | ||
640 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
641 | I915_READ(GEN8_PCU_IMR)); | |
642 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
643 | I915_READ(GEN8_PCU_IIR)); | |
644 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
645 | I915_READ(GEN8_PCU_IER)); | |
646 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
647 | seq_printf(m, "Display IER:\t%08x\n", |
648 | I915_READ(VLV_IER)); | |
649 | seq_printf(m, "Display IIR:\t%08x\n", | |
650 | I915_READ(VLV_IIR)); | |
651 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
652 | I915_READ(VLV_IIR_RW)); | |
653 | seq_printf(m, "Display IMR:\t%08x\n", | |
654 | I915_READ(VLV_IMR)); | |
655 | for_each_pipe(pipe) | |
656 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
657 | pipe_name(pipe), | |
658 | I915_READ(PIPESTAT(pipe))); | |
659 | ||
660 | seq_printf(m, "Master IER:\t%08x\n", | |
661 | I915_READ(VLV_MASTER_IER)); | |
662 | ||
663 | seq_printf(m, "Render IER:\t%08x\n", | |
664 | I915_READ(GTIER)); | |
665 | seq_printf(m, "Render IIR:\t%08x\n", | |
666 | I915_READ(GTIIR)); | |
667 | seq_printf(m, "Render IMR:\t%08x\n", | |
668 | I915_READ(GTIMR)); | |
669 | ||
670 | seq_printf(m, "PM IER:\t\t%08x\n", | |
671 | I915_READ(GEN6_PMIER)); | |
672 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
673 | I915_READ(GEN6_PMIIR)); | |
674 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
675 | I915_READ(GEN6_PMIMR)); | |
676 | ||
677 | seq_printf(m, "Port hotplug:\t%08x\n", | |
678 | I915_READ(PORT_HOTPLUG_EN)); | |
679 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
680 | I915_READ(VLV_DPFLIPSTAT)); | |
681 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
682 | I915_READ(DPINVGTT)); | |
683 | ||
684 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
685 | seq_printf(m, "Interrupt enable: %08x\n", |
686 | I915_READ(IER)); | |
687 | seq_printf(m, "Interrupt identity: %08x\n", | |
688 | I915_READ(IIR)); | |
689 | seq_printf(m, "Interrupt mask: %08x\n", | |
690 | I915_READ(IMR)); | |
9db4a9c7 JB |
691 | for_each_pipe(pipe) |
692 | seq_printf(m, "Pipe %c stat: %08x\n", | |
693 | pipe_name(pipe), | |
694 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
695 | } else { |
696 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
697 | I915_READ(DEIER)); | |
698 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
699 | I915_READ(DEIIR)); | |
700 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
701 | I915_READ(DEIMR)); | |
702 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
703 | I915_READ(SDEIER)); | |
704 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
705 | I915_READ(SDEIIR)); | |
706 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
707 | I915_READ(SDEIMR)); | |
708 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
709 | I915_READ(GTIER)); | |
710 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
711 | I915_READ(GTIIR)); | |
712 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
713 | I915_READ(GTIMR)); | |
714 | } | |
2017263e BG |
715 | seq_printf(m, "Interrupts received: %d\n", |
716 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 717 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 718 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
719 | seq_printf(m, |
720 | "Graphics Interrupt mask (%s): %08x\n", | |
721 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 722 | } |
a2c7f6fd | 723 | i915_ring_seqno_info(m, ring); |
9862e600 | 724 | } |
c8c8fb33 | 725 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
726 | mutex_unlock(&dev->struct_mutex); |
727 | ||
2017263e BG |
728 | return 0; |
729 | } | |
730 | ||
a6172a80 CW |
731 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
732 | { | |
733 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
734 | struct drm_device *dev = node->minor->dev; | |
735 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
736 | int i, ret; |
737 | ||
738 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
739 | if (ret) | |
740 | return ret; | |
a6172a80 CW |
741 | |
742 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
743 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
744 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 745 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 746 | |
6c085a72 CW |
747 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
748 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 749 | if (obj == NULL) |
267f0c90 | 750 | seq_puts(m, "unused"); |
c2c347a9 | 751 | else |
05394f39 | 752 | describe_obj(m, obj); |
267f0c90 | 753 | seq_putc(m, '\n'); |
a6172a80 CW |
754 | } |
755 | ||
05394f39 | 756 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
757 | return 0; |
758 | } | |
759 | ||
2017263e BG |
760 | static int i915_hws_info(struct seq_file *m, void *data) |
761 | { | |
762 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
763 | struct drm_device *dev = node->minor->dev; | |
764 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 765 | struct intel_ring_buffer *ring; |
1a240d4d | 766 | const u32 *hws; |
4066c0ae CW |
767 | int i; |
768 | ||
1ec14ad3 | 769 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 770 | hws = ring->status_page.page_addr; |
2017263e BG |
771 | if (hws == NULL) |
772 | return 0; | |
773 | ||
774 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
775 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
776 | i * 4, | |
777 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
778 | } | |
779 | return 0; | |
780 | } | |
781 | ||
d5442303 DV |
782 | static ssize_t |
783 | i915_error_state_write(struct file *filp, | |
784 | const char __user *ubuf, | |
785 | size_t cnt, | |
786 | loff_t *ppos) | |
787 | { | |
edc3d884 | 788 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 789 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 790 | int ret; |
d5442303 DV |
791 | |
792 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
793 | ||
22bcfc6a DV |
794 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
795 | if (ret) | |
796 | return ret; | |
797 | ||
d5442303 DV |
798 | i915_destroy_error_state(dev); |
799 | mutex_unlock(&dev->struct_mutex); | |
800 | ||
801 | return cnt; | |
802 | } | |
803 | ||
804 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
805 | { | |
806 | struct drm_device *dev = inode->i_private; | |
d5442303 | 807 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
808 | |
809 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
810 | if (!error_priv) | |
811 | return -ENOMEM; | |
812 | ||
813 | error_priv->dev = dev; | |
814 | ||
95d5bfb3 | 815 | i915_error_state_get(dev, error_priv); |
d5442303 | 816 | |
edc3d884 MK |
817 | file->private_data = error_priv; |
818 | ||
819 | return 0; | |
d5442303 DV |
820 | } |
821 | ||
822 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
823 | { | |
edc3d884 | 824 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 825 | |
95d5bfb3 | 826 | i915_error_state_put(error_priv); |
d5442303 DV |
827 | kfree(error_priv); |
828 | ||
edc3d884 MK |
829 | return 0; |
830 | } | |
831 | ||
4dc955f7 MK |
832 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
833 | size_t count, loff_t *pos) | |
834 | { | |
835 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
836 | struct drm_i915_error_state_buf error_str; | |
837 | loff_t tmp_pos = 0; | |
838 | ssize_t ret_count = 0; | |
839 | int ret; | |
840 | ||
841 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
842 | if (ret) | |
843 | return ret; | |
edc3d884 | 844 | |
fc16b48b | 845 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
846 | if (ret) |
847 | goto out; | |
848 | ||
edc3d884 MK |
849 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
850 | error_str.buf, | |
851 | error_str.bytes); | |
852 | ||
853 | if (ret_count < 0) | |
854 | ret = ret_count; | |
855 | else | |
856 | *pos = error_str.start + ret_count; | |
857 | out: | |
4dc955f7 | 858 | i915_error_state_buf_release(&error_str); |
edc3d884 | 859 | return ret ?: ret_count; |
d5442303 DV |
860 | } |
861 | ||
862 | static const struct file_operations i915_error_state_fops = { | |
863 | .owner = THIS_MODULE, | |
864 | .open = i915_error_state_open, | |
edc3d884 | 865 | .read = i915_error_state_read, |
d5442303 DV |
866 | .write = i915_error_state_write, |
867 | .llseek = default_llseek, | |
868 | .release = i915_error_state_release, | |
869 | }; | |
870 | ||
647416f9 KC |
871 | static int |
872 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 873 | { |
647416f9 | 874 | struct drm_device *dev = data; |
40633219 | 875 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
876 | int ret; |
877 | ||
878 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
879 | if (ret) | |
880 | return ret; | |
881 | ||
647416f9 | 882 | *val = dev_priv->next_seqno; |
40633219 MK |
883 | mutex_unlock(&dev->struct_mutex); |
884 | ||
647416f9 | 885 | return 0; |
40633219 MK |
886 | } |
887 | ||
647416f9 KC |
888 | static int |
889 | i915_next_seqno_set(void *data, u64 val) | |
890 | { | |
891 | struct drm_device *dev = data; | |
40633219 MK |
892 | int ret; |
893 | ||
40633219 MK |
894 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
895 | if (ret) | |
896 | return ret; | |
897 | ||
e94fbaa8 | 898 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
899 | mutex_unlock(&dev->struct_mutex); |
900 | ||
647416f9 | 901 | return ret; |
40633219 MK |
902 | } |
903 | ||
647416f9 KC |
904 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
905 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 906 | "0x%llx\n"); |
40633219 | 907 | |
f97108d1 JB |
908 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
909 | { | |
910 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
911 | struct drm_device *dev = node->minor->dev; | |
912 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
913 | u16 crstanddelay; |
914 | int ret; | |
915 | ||
916 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
917 | if (ret) | |
918 | return ret; | |
c8c8fb33 | 919 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
920 | |
921 | crstanddelay = I915_READ16(CRSTANDVID); | |
922 | ||
c8c8fb33 | 923 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 924 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
925 | |
926 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
931 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
932 | { | |
933 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
934 | struct drm_device *dev = node->minor->dev; | |
935 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c8c8fb33 PZ |
936 | int ret = 0; |
937 | ||
938 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 939 | |
5c9669ce TR |
940 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
941 | ||
3b8d8d91 JB |
942 | if (IS_GEN5(dev)) { |
943 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
944 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
945 | ||
946 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
947 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
948 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
949 | MEMSTAT_VID_SHIFT); | |
950 | seq_printf(m, "Current P-state: %d\n", | |
951 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 952 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
953 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
954 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
955 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 956 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
957 | u32 rpupei, rpcurup, rpprevup; |
958 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
959 | int max_freq; |
960 | ||
961 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
962 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
963 | if (ret) | |
c8c8fb33 | 964 | goto out; |
d1ebd816 | 965 | |
c8d9a590 | 966 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 967 | |
8e8c06cd CW |
968 | reqf = I915_READ(GEN6_RPNSWREQ); |
969 | reqf &= ~GEN6_TURBO_DISABLE; | |
970 | if (IS_HASWELL(dev)) | |
971 | reqf >>= 24; | |
972 | else | |
973 | reqf >>= 25; | |
974 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
975 | ||
ccab5c82 JB |
976 | rpstat = I915_READ(GEN6_RPSTAT1); |
977 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
978 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
979 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
980 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
981 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
982 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
983 | if (IS_HASWELL(dev)) |
984 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
985 | else | |
986 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
987 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 988 | |
c8d9a590 | 989 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
990 | mutex_unlock(&dev->struct_mutex); |
991 | ||
3b8d8d91 | 992 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 993 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
994 | seq_printf(m, "Render p-state ratio: %d\n", |
995 | (gt_perf_status & 0xff00) >> 8); | |
996 | seq_printf(m, "Render p-state VID: %d\n", | |
997 | gt_perf_status & 0xff); | |
998 | seq_printf(m, "Render p-state limit: %d\n", | |
999 | rp_state_limits & 0xff); | |
8e8c06cd | 1000 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1001 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1002 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1003 | GEN6_CURICONT_MASK); | |
1004 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1005 | GEN6_CURBSYTAVG_MASK); | |
1006 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1007 | GEN6_CURBSYTAVG_MASK); | |
1008 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1009 | GEN6_CURIAVG_MASK); | |
1010 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1011 | GEN6_CURBSYTAVG_MASK); | |
1012 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1013 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1014 | |
1015 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1016 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1017 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1018 | |
1019 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1020 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1021 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1022 | |
1023 | max_freq = rp_state_cap & 0xff; | |
1024 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1025 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
1026 | |
1027 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
1028 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
1029 | } else if (IS_VALLEYVIEW(dev)) { |
1030 | u32 freq_sts, val; | |
1031 | ||
259bd5d4 | 1032 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1033 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1034 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1035 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1036 | ||
c5bd2bf6 | 1037 | val = valleyview_rps_max_freq(dev_priv); |
0a073b84 | 1038 | seq_printf(m, "max GPU freq: %d MHz\n", |
2ec3815f | 1039 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 | 1040 | |
c5bd2bf6 | 1041 | val = valleyview_rps_min_freq(dev_priv); |
0a073b84 | 1042 | seq_printf(m, "min GPU freq: %d MHz\n", |
2ec3815f | 1043 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 JB |
1044 | |
1045 | seq_printf(m, "current GPU freq: %d MHz\n", | |
2ec3815f | 1046 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
259bd5d4 | 1047 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1048 | } else { |
267f0c90 | 1049 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1050 | } |
f97108d1 | 1051 | |
c8c8fb33 PZ |
1052 | out: |
1053 | intel_runtime_pm_put(dev_priv); | |
1054 | return ret; | |
f97108d1 JB |
1055 | } |
1056 | ||
1057 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
1058 | { | |
1059 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1060 | struct drm_device *dev = node->minor->dev; | |
1061 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1062 | u32 delayfreq; | |
616fdb5a BW |
1063 | int ret, i; |
1064 | ||
1065 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1066 | if (ret) | |
1067 | return ret; | |
c8c8fb33 | 1068 | intel_runtime_pm_get(dev_priv); |
f97108d1 JB |
1069 | |
1070 | for (i = 0; i < 16; i++) { | |
1071 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
1072 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
1073 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
1074 | } |
1075 | ||
c8c8fb33 PZ |
1076 | intel_runtime_pm_put(dev_priv); |
1077 | ||
616fdb5a BW |
1078 | mutex_unlock(&dev->struct_mutex); |
1079 | ||
f97108d1 JB |
1080 | return 0; |
1081 | } | |
1082 | ||
1083 | static inline int MAP_TO_MV(int map) | |
1084 | { | |
1085 | return 1250 - (map * 25); | |
1086 | } | |
1087 | ||
1088 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
1089 | { | |
1090 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1091 | struct drm_device *dev = node->minor->dev; | |
1092 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1093 | u32 inttoext; | |
616fdb5a BW |
1094 | int ret, i; |
1095 | ||
1096 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1097 | if (ret) | |
1098 | return ret; | |
c8c8fb33 | 1099 | intel_runtime_pm_get(dev_priv); |
f97108d1 JB |
1100 | |
1101 | for (i = 1; i <= 32; i++) { | |
1102 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1103 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1104 | } | |
1105 | ||
c8c8fb33 | 1106 | intel_runtime_pm_put(dev_priv); |
616fdb5a BW |
1107 | mutex_unlock(&dev->struct_mutex); |
1108 | ||
f97108d1 JB |
1109 | return 0; |
1110 | } | |
1111 | ||
4d85529d | 1112 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1113 | { |
1114 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1115 | struct drm_device *dev = node->minor->dev; | |
1116 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1117 | u32 rgvmodectl, rstdbyctl; |
1118 | u16 crstandvid; | |
1119 | int ret; | |
1120 | ||
1121 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1122 | if (ret) | |
1123 | return ret; | |
c8c8fb33 | 1124 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1125 | |
1126 | rgvmodectl = I915_READ(MEMMODECTL); | |
1127 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1128 | crstandvid = I915_READ16(CRSTANDVID); | |
1129 | ||
c8c8fb33 | 1130 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1131 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1132 | |
1133 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1134 | "yes" : "no"); | |
1135 | seq_printf(m, "Boost freq: %d\n", | |
1136 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1137 | MEMMODE_BOOST_FREQ_SHIFT); | |
1138 | seq_printf(m, "HW control enabled: %s\n", | |
1139 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1140 | seq_printf(m, "SW control enabled: %s\n", | |
1141 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1142 | seq_printf(m, "Gated voltage change: %s\n", | |
1143 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1144 | seq_printf(m, "Starting frequency: P%d\n", | |
1145 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1146 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1147 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1148 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1149 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1150 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1151 | seq_printf(m, "Render standby enabled: %s\n", | |
1152 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1153 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1154 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1155 | case RSX_STATUS_ON: | |
267f0c90 | 1156 | seq_puts(m, "on\n"); |
88271da3 JB |
1157 | break; |
1158 | case RSX_STATUS_RC1: | |
267f0c90 | 1159 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1160 | break; |
1161 | case RSX_STATUS_RC1E: | |
267f0c90 | 1162 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1163 | break; |
1164 | case RSX_STATUS_RS1: | |
267f0c90 | 1165 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1166 | break; |
1167 | case RSX_STATUS_RS2: | |
267f0c90 | 1168 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1169 | break; |
1170 | case RSX_STATUS_RS3: | |
267f0c90 | 1171 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1172 | break; |
1173 | default: | |
267f0c90 | 1174 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1175 | break; |
1176 | } | |
f97108d1 JB |
1177 | |
1178 | return 0; | |
1179 | } | |
1180 | ||
4d85529d BW |
1181 | static int gen6_drpc_info(struct seq_file *m) |
1182 | { | |
1183 | ||
1184 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1185 | struct drm_device *dev = node->minor->dev; | |
1186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1187 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1188 | unsigned forcewake_count; |
aee56cff | 1189 | int count = 0, ret; |
4d85529d BW |
1190 | |
1191 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1192 | if (ret) | |
1193 | return ret; | |
c8c8fb33 | 1194 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1195 | |
907b28c5 CW |
1196 | spin_lock_irq(&dev_priv->uncore.lock); |
1197 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1198 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1199 | |
1200 | if (forcewake_count) { | |
267f0c90 DL |
1201 | seq_puts(m, "RC information inaccurate because somebody " |
1202 | "holds a forcewake reference \n"); | |
4d85529d BW |
1203 | } else { |
1204 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1205 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1206 | udelay(10); | |
1207 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1208 | } | |
1209 | ||
1210 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1211 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1212 | |
1213 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1214 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1215 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1216 | mutex_lock(&dev_priv->rps.hw_lock); |
1217 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1218 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1219 | |
c8c8fb33 PZ |
1220 | intel_runtime_pm_put(dev_priv); |
1221 | ||
4d85529d BW |
1222 | seq_printf(m, "Video Turbo Mode: %s\n", |
1223 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1224 | seq_printf(m, "HW control enabled: %s\n", | |
1225 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1226 | seq_printf(m, "SW control enabled: %s\n", | |
1227 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1228 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1229 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1230 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1231 | seq_printf(m, "RC6 Enabled: %s\n", | |
1232 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1233 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1234 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1235 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1236 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1237 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1238 | switch (gt_core_status & GEN6_RCn_MASK) { |
1239 | case GEN6_RC0: | |
1240 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1241 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1242 | else |
267f0c90 | 1243 | seq_puts(m, "on\n"); |
4d85529d BW |
1244 | break; |
1245 | case GEN6_RC3: | |
267f0c90 | 1246 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1247 | break; |
1248 | case GEN6_RC6: | |
267f0c90 | 1249 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1250 | break; |
1251 | case GEN6_RC7: | |
267f0c90 | 1252 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1253 | break; |
1254 | default: | |
267f0c90 | 1255 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1256 | break; |
1257 | } | |
1258 | ||
1259 | seq_printf(m, "Core Power Down: %s\n", | |
1260 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1261 | |
1262 | /* Not exactly sure what this is */ | |
1263 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1264 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1265 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1266 | I915_READ(GEN6_GT_GFX_RC6)); | |
1267 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1268 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1269 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1270 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1271 | ||
ecd8faea BW |
1272 | seq_printf(m, "RC6 voltage: %dmV\n", |
1273 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1274 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1275 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1276 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1277 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1278 | return 0; |
1279 | } | |
1280 | ||
1281 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1282 | { | |
1283 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1284 | struct drm_device *dev = node->minor->dev; | |
1285 | ||
1286 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1287 | return gen6_drpc_info(m); | |
1288 | else | |
1289 | return ironlake_drpc_info(m); | |
1290 | } | |
1291 | ||
b5e50c3f JB |
1292 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1293 | { | |
1294 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1295 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1296 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1297 | |
3a77c4c4 | 1298 | if (!HAS_FBC(dev)) { |
267f0c90 | 1299 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1300 | return 0; |
1301 | } | |
1302 | ||
ee5382ae | 1303 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1304 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1305 | } else { |
267f0c90 | 1306 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1307 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1308 | case FBC_OK: |
1309 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1310 | break; | |
1311 | case FBC_UNSUPPORTED: | |
1312 | seq_puts(m, "unsupported by this chipset"); | |
1313 | break; | |
bed4a673 | 1314 | case FBC_NO_OUTPUT: |
267f0c90 | 1315 | seq_puts(m, "no outputs"); |
bed4a673 | 1316 | break; |
b5e50c3f | 1317 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1318 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1319 | break; |
1320 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1321 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1322 | break; |
1323 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1324 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1325 | break; |
1326 | case FBC_BAD_PLANE: | |
267f0c90 | 1327 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1328 | break; |
1329 | case FBC_NOT_TILED: | |
267f0c90 | 1330 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1331 | break; |
9c928d16 | 1332 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1333 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1334 | break; |
c1a9f047 | 1335 | case FBC_MODULE_PARAM: |
267f0c90 | 1336 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1337 | break; |
8a5729a3 | 1338 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1339 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1340 | break; |
b5e50c3f | 1341 | default: |
267f0c90 | 1342 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1343 | } |
267f0c90 | 1344 | seq_putc(m, '\n'); |
b5e50c3f JB |
1345 | } |
1346 | return 0; | |
1347 | } | |
1348 | ||
92d44621 PZ |
1349 | static int i915_ips_status(struct seq_file *m, void *unused) |
1350 | { | |
1351 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1352 | struct drm_device *dev = node->minor->dev; | |
1353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1354 | ||
f5adf94e | 1355 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1356 | seq_puts(m, "not supported\n"); |
1357 | return 0; | |
1358 | } | |
1359 | ||
e59150dc | 1360 | if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE) |
92d44621 PZ |
1361 | seq_puts(m, "enabled\n"); |
1362 | else | |
1363 | seq_puts(m, "disabled\n"); | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
4a9bef37 JB |
1368 | static int i915_sr_status(struct seq_file *m, void *unused) |
1369 | { | |
1370 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1371 | struct drm_device *dev = node->minor->dev; | |
1372 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1373 | bool sr_enabled = false; | |
1374 | ||
1398261a | 1375 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1376 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1377 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1378 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1379 | else if (IS_I915GM(dev)) | |
1380 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1381 | else if (IS_PINEVIEW(dev)) | |
1382 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1383 | ||
5ba2aaaa CW |
1384 | seq_printf(m, "self-refresh: %s\n", |
1385 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1386 | |
1387 | return 0; | |
1388 | } | |
1389 | ||
7648fa99 JB |
1390 | static int i915_emon_status(struct seq_file *m, void *unused) |
1391 | { | |
1392 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1393 | struct drm_device *dev = node->minor->dev; | |
1394 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1395 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1396 | int ret; |
1397 | ||
582be6b4 CW |
1398 | if (!IS_GEN5(dev)) |
1399 | return -ENODEV; | |
1400 | ||
de227ef0 CW |
1401 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1402 | if (ret) | |
1403 | return ret; | |
7648fa99 JB |
1404 | |
1405 | temp = i915_mch_val(dev_priv); | |
1406 | chipset = i915_chipset_val(dev_priv); | |
1407 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1408 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1409 | |
1410 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1411 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1412 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1413 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1414 | ||
1415 | return 0; | |
1416 | } | |
1417 | ||
23b2f8bb JB |
1418 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1419 | { | |
1420 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1421 | struct drm_device *dev = node->minor->dev; | |
1422 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1423 | int ret; | |
1424 | int gpu_freq, ia_freq; | |
1425 | ||
1c70c0ce | 1426 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1427 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1428 | return 0; |
1429 | } | |
1430 | ||
5c9669ce TR |
1431 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1432 | ||
4fc688ce | 1433 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1434 | if (ret) |
1435 | return ret; | |
c8c8fb33 | 1436 | intel_runtime_pm_get(dev_priv); |
23b2f8bb | 1437 | |
267f0c90 | 1438 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1439 | |
c6a828d3 DV |
1440 | for (gpu_freq = dev_priv->rps.min_delay; |
1441 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1442 | gpu_freq++) { |
42c0526c BW |
1443 | ia_freq = gpu_freq; |
1444 | sandybridge_pcode_read(dev_priv, | |
1445 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1446 | &ia_freq); | |
3ebecd07 CW |
1447 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1448 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1449 | ((ia_freq >> 0) & 0xff) * 100, | |
1450 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1451 | } |
1452 | ||
c8c8fb33 | 1453 | intel_runtime_pm_put(dev_priv); |
4fc688ce | 1454 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1455 | |
1456 | return 0; | |
1457 | } | |
1458 | ||
7648fa99 JB |
1459 | static int i915_gfxec(struct seq_file *m, void *unused) |
1460 | { | |
1461 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1462 | struct drm_device *dev = node->minor->dev; | |
1463 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1464 | int ret; |
1465 | ||
1466 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1467 | if (ret) | |
1468 | return ret; | |
c8c8fb33 | 1469 | intel_runtime_pm_get(dev_priv); |
7648fa99 JB |
1470 | |
1471 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
c8c8fb33 | 1472 | intel_runtime_pm_put(dev_priv); |
7648fa99 | 1473 | |
616fdb5a BW |
1474 | mutex_unlock(&dev->struct_mutex); |
1475 | ||
7648fa99 JB |
1476 | return 0; |
1477 | } | |
1478 | ||
44834a67 CW |
1479 | static int i915_opregion(struct seq_file *m, void *unused) |
1480 | { | |
1481 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1482 | struct drm_device *dev = node->minor->dev; | |
1483 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1484 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1485 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1486 | int ret; |
1487 | ||
0d38f009 DV |
1488 | if (data == NULL) |
1489 | return -ENOMEM; | |
1490 | ||
44834a67 CW |
1491 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1492 | if (ret) | |
0d38f009 | 1493 | goto out; |
44834a67 | 1494 | |
0d38f009 DV |
1495 | if (opregion->header) { |
1496 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1497 | seq_write(m, data, OPREGION_SIZE); | |
1498 | } | |
44834a67 CW |
1499 | |
1500 | mutex_unlock(&dev->struct_mutex); | |
1501 | ||
0d38f009 DV |
1502 | out: |
1503 | kfree(data); | |
44834a67 CW |
1504 | return 0; |
1505 | } | |
1506 | ||
37811fcc CW |
1507 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1508 | { | |
1509 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1510 | struct drm_device *dev = node->minor->dev; | |
4520f53a | 1511 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1512 | struct intel_framebuffer *fb; |
37811fcc | 1513 | |
4520f53a DV |
1514 | #ifdef CONFIG_DRM_I915_FBDEV |
1515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1516 | int ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
37811fcc CW |
1517 | if (ret) |
1518 | return ret; | |
1519 | ||
1520 | ifbdev = dev_priv->fbdev; | |
1521 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1522 | ||
623f9783 | 1523 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1524 | fb->base.width, |
1525 | fb->base.height, | |
1526 | fb->base.depth, | |
623f9783 DV |
1527 | fb->base.bits_per_pixel, |
1528 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1529 | describe_obj(m, fb->obj); |
267f0c90 | 1530 | seq_putc(m, '\n'); |
4b096ac1 | 1531 | mutex_unlock(&dev->mode_config.mutex); |
4520f53a | 1532 | #endif |
37811fcc | 1533 | |
4b096ac1 | 1534 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1535 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1536 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1537 | continue; |
1538 | ||
623f9783 | 1539 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1540 | fb->base.width, |
1541 | fb->base.height, | |
1542 | fb->base.depth, | |
623f9783 DV |
1543 | fb->base.bits_per_pixel, |
1544 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1545 | describe_obj(m, fb->obj); |
267f0c90 | 1546 | seq_putc(m, '\n'); |
37811fcc | 1547 | } |
4b096ac1 | 1548 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1549 | |
1550 | return 0; | |
1551 | } | |
1552 | ||
e76d3630 BW |
1553 | static int i915_context_status(struct seq_file *m, void *unused) |
1554 | { | |
1555 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1556 | struct drm_device *dev = node->minor->dev; | |
1557 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 | 1558 | struct intel_ring_buffer *ring; |
a33afea5 | 1559 | struct i915_hw_context *ctx; |
a168c293 | 1560 | int ret, i; |
e76d3630 BW |
1561 | |
1562 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1563 | if (ret) | |
1564 | return ret; | |
1565 | ||
3e373948 | 1566 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1567 | seq_puts(m, "power context "); |
3e373948 | 1568 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1569 | seq_putc(m, '\n'); |
dc501fbc | 1570 | } |
e76d3630 | 1571 | |
3e373948 | 1572 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1573 | seq_puts(m, "render context "); |
3e373948 | 1574 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1575 | seq_putc(m, '\n'); |
dc501fbc | 1576 | } |
e76d3630 | 1577 | |
a33afea5 BW |
1578 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
1579 | seq_puts(m, "HW context "); | |
3ccfd19d | 1580 | describe_ctx(m, ctx); |
a33afea5 BW |
1581 | for_each_ring(ring, dev_priv, i) |
1582 | if (ring->default_context == ctx) | |
1583 | seq_printf(m, "(default context %s) ", ring->name); | |
1584 | ||
1585 | describe_obj(m, ctx->obj); | |
1586 | seq_putc(m, '\n'); | |
a168c293 BW |
1587 | } |
1588 | ||
e76d3630 BW |
1589 | mutex_unlock(&dev->mode_config.mutex); |
1590 | ||
1591 | return 0; | |
1592 | } | |
1593 | ||
6d794d42 BW |
1594 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1595 | { | |
1596 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1597 | struct drm_device *dev = node->minor->dev; | |
1598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43709ba0 | 1599 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
6d794d42 | 1600 | |
907b28c5 | 1601 | spin_lock_irq(&dev_priv->uncore.lock); |
43709ba0 D |
1602 | if (IS_VALLEYVIEW(dev)) { |
1603 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1604 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1605 | } else | |
1606 | forcewake_count = dev_priv->uncore.forcewake_count; | |
907b28c5 | 1607 | spin_unlock_irq(&dev_priv->uncore.lock); |
6d794d42 | 1608 | |
43709ba0 D |
1609 | if (IS_VALLEYVIEW(dev)) { |
1610 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); | |
1611 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); | |
1612 | } else | |
1613 | seq_printf(m, "forcewake count = %u\n", forcewake_count); | |
6d794d42 BW |
1614 | |
1615 | return 0; | |
1616 | } | |
1617 | ||
ea16a3cd DV |
1618 | static const char *swizzle_string(unsigned swizzle) |
1619 | { | |
aee56cff | 1620 | switch (swizzle) { |
ea16a3cd DV |
1621 | case I915_BIT_6_SWIZZLE_NONE: |
1622 | return "none"; | |
1623 | case I915_BIT_6_SWIZZLE_9: | |
1624 | return "bit9"; | |
1625 | case I915_BIT_6_SWIZZLE_9_10: | |
1626 | return "bit9/bit10"; | |
1627 | case I915_BIT_6_SWIZZLE_9_11: | |
1628 | return "bit9/bit11"; | |
1629 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1630 | return "bit9/bit10/bit11"; | |
1631 | case I915_BIT_6_SWIZZLE_9_17: | |
1632 | return "bit9/bit17"; | |
1633 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1634 | return "bit9/bit10/bit17"; | |
1635 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1636 | return "unknown"; |
ea16a3cd DV |
1637 | } |
1638 | ||
1639 | return "bug"; | |
1640 | } | |
1641 | ||
1642 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1643 | { | |
1644 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1645 | struct drm_device *dev = node->minor->dev; | |
1646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1647 | int ret; |
1648 | ||
1649 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1650 | if (ret) | |
1651 | return ret; | |
c8c8fb33 | 1652 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 1653 | |
ea16a3cd DV |
1654 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1655 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1656 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1657 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1658 | ||
1659 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1660 | seq_printf(m, "DDC = 0x%08x\n", | |
1661 | I915_READ(DCC)); | |
1662 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1663 | I915_READ16(C0DRB3)); | |
1664 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1665 | I915_READ16(C1DRB3)); | |
9d3203e1 | 1666 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
1667 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
1668 | I915_READ(MAD_DIMM_C0)); | |
1669 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1670 | I915_READ(MAD_DIMM_C1)); | |
1671 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1672 | I915_READ(MAD_DIMM_C2)); | |
1673 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1674 | I915_READ(TILECTL)); | |
9d3203e1 BW |
1675 | if (IS_GEN8(dev)) |
1676 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", | |
1677 | I915_READ(GAMTARBMODE)); | |
1678 | else | |
1679 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1680 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
1681 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
1682 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 1683 | } |
c8c8fb33 | 1684 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
1685 | mutex_unlock(&dev->struct_mutex); |
1686 | ||
1687 | return 0; | |
1688 | } | |
1689 | ||
77df6772 | 1690 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 1691 | { |
3cf17fc5 DV |
1692 | struct drm_i915_private *dev_priv = dev->dev_private; |
1693 | struct intel_ring_buffer *ring; | |
77df6772 BW |
1694 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1695 | int unused, i; | |
3cf17fc5 | 1696 | |
77df6772 BW |
1697 | if (!ppgtt) |
1698 | return; | |
1699 | ||
1700 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); | |
1701 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages); | |
1702 | for_each_ring(ring, dev_priv, unused) { | |
1703 | seq_printf(m, "%s\n", ring->name); | |
1704 | for (i = 0; i < 4; i++) { | |
1705 | u32 offset = 0x270 + i * 8; | |
1706 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
1707 | pdp <<= 32; | |
1708 | pdp |= I915_READ(ring->mmio_base + offset); | |
1709 | for (i = 0; i < 4; i++) | |
1710 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); | |
1711 | } | |
1712 | } | |
1713 | } | |
1714 | ||
1715 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
1716 | { | |
1717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1718 | struct intel_ring_buffer *ring; | |
1719 | int i; | |
3cf17fc5 | 1720 | |
3cf17fc5 DV |
1721 | if (INTEL_INFO(dev)->gen == 6) |
1722 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1723 | ||
a2c7f6fd | 1724 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1725 | seq_printf(m, "%s\n", ring->name); |
1726 | if (INTEL_INFO(dev)->gen == 7) | |
1727 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1728 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1729 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1730 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1731 | } | |
1732 | if (dev_priv->mm.aliasing_ppgtt) { | |
1733 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1734 | ||
267f0c90 | 1735 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1736 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1737 | } | |
1738 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
1739 | } |
1740 | ||
1741 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
1742 | { | |
1743 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1744 | struct drm_device *dev = node->minor->dev; | |
c8c8fb33 | 1745 | struct drm_i915_private *dev_priv = dev->dev_private; |
77df6772 BW |
1746 | |
1747 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1748 | if (ret) | |
1749 | return ret; | |
c8c8fb33 | 1750 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
1751 | |
1752 | if (INTEL_INFO(dev)->gen >= 8) | |
1753 | gen8_ppgtt_info(m, dev); | |
1754 | else if (INTEL_INFO(dev)->gen >= 6) | |
1755 | gen6_ppgtt_info(m, dev); | |
1756 | ||
c8c8fb33 | 1757 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
1758 | mutex_unlock(&dev->struct_mutex); |
1759 | ||
1760 | return 0; | |
1761 | } | |
1762 | ||
57f350b6 JB |
1763 | static int i915_dpio_info(struct seq_file *m, void *data) |
1764 | { | |
1765 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1766 | struct drm_device *dev = node->minor->dev; | |
1767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1768 | int ret; | |
1769 | ||
1770 | ||
1771 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1772 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1773 | return 0; |
1774 | } | |
1775 | ||
09153000 | 1776 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1777 | if (ret) |
1778 | return ret; | |
1779 | ||
1780 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1781 | ||
ab3c759a CML |
1782 | seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n", |
1783 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0))); | |
1784 | seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n", | |
1785 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1))); | |
1786 | ||
1787 | seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n", | |
1788 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0))); | |
1789 | seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n", | |
1790 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1))); | |
1791 | ||
1792 | seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n", | |
1793 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0))); | |
1794 | seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n", | |
1795 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1))); | |
1796 | ||
1797 | seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n", | |
1798 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0))); | |
1799 | seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n", | |
1800 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1))); | |
57f350b6 JB |
1801 | |
1802 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
ab3c759a | 1803 | vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0)); |
57f350b6 | 1804 | |
09153000 | 1805 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1806 | |
1807 | return 0; | |
1808 | } | |
1809 | ||
63573eb7 BW |
1810 | static int i915_llc(struct seq_file *m, void *data) |
1811 | { | |
1812 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1813 | struct drm_device *dev = node->minor->dev; | |
1814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1815 | ||
1816 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1817 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1818 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1819 | ||
1820 | return 0; | |
1821 | } | |
1822 | ||
e91fd8c6 RV |
1823 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1824 | { | |
1825 | struct drm_info_node *node = m->private; | |
1826 | struct drm_device *dev = node->minor->dev; | |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1828 | u32 psrperf = 0; |
1829 | bool enabled = false; | |
e91fd8c6 | 1830 | |
c8c8fb33 PZ |
1831 | intel_runtime_pm_get(dev_priv); |
1832 | ||
a031d709 RV |
1833 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1834 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1835 | |
a031d709 RV |
1836 | enabled = HAS_PSR(dev) && |
1837 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1838 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1839 | |
a031d709 RV |
1840 | if (HAS_PSR(dev)) |
1841 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1842 | EDP_PSR_PERF_CNT_MASK; | |
1843 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 | 1844 | |
c8c8fb33 | 1845 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
1846 | return 0; |
1847 | } | |
1848 | ||
ec013e7f JB |
1849 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1850 | { | |
1851 | struct drm_info_node *node = m->private; | |
1852 | struct drm_device *dev = node->minor->dev; | |
1853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1854 | u64 power; | |
1855 | u32 units; | |
1856 | ||
1857 | if (INTEL_INFO(dev)->gen < 6) | |
1858 | return -ENODEV; | |
1859 | ||
1860 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1861 | power = (power & 0x1f00) >> 8; | |
1862 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1863 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1864 | power *= units; | |
1865 | ||
1866 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1867 | |
1868 | return 0; | |
1869 | } | |
1870 | ||
1871 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1872 | { | |
1873 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1874 | struct drm_device *dev = node->minor->dev; | |
1875 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1876 | ||
1877 | if (!IS_HASWELL(dev)) { | |
1878 | seq_puts(m, "not supported\n"); | |
1879 | return 0; | |
1880 | } | |
1881 | ||
1882 | mutex_lock(&dev_priv->pc8.lock); | |
1883 | seq_printf(m, "Requirements met: %s\n", | |
1884 | yesno(dev_priv->pc8.requirements_met)); | |
1885 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1886 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1887 | seq_printf(m, "IRQs disabled: %s\n", | |
1888 | yesno(dev_priv->pc8.irqs_disabled)); | |
1889 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
1890 | mutex_unlock(&dev_priv->pc8.lock); | |
1891 | ||
ec013e7f JB |
1892 | return 0; |
1893 | } | |
1894 | ||
1da51581 ID |
1895 | static const char *power_domain_str(enum intel_display_power_domain domain) |
1896 | { | |
1897 | switch (domain) { | |
1898 | case POWER_DOMAIN_PIPE_A: | |
1899 | return "PIPE_A"; | |
1900 | case POWER_DOMAIN_PIPE_B: | |
1901 | return "PIPE_B"; | |
1902 | case POWER_DOMAIN_PIPE_C: | |
1903 | return "PIPE_C"; | |
1904 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
1905 | return "PIPE_A_PANEL_FITTER"; | |
1906 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
1907 | return "PIPE_B_PANEL_FITTER"; | |
1908 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
1909 | return "PIPE_C_PANEL_FITTER"; | |
1910 | case POWER_DOMAIN_TRANSCODER_A: | |
1911 | return "TRANSCODER_A"; | |
1912 | case POWER_DOMAIN_TRANSCODER_B: | |
1913 | return "TRANSCODER_B"; | |
1914 | case POWER_DOMAIN_TRANSCODER_C: | |
1915 | return "TRANSCODER_C"; | |
1916 | case POWER_DOMAIN_TRANSCODER_EDP: | |
1917 | return "TRANSCODER_EDP"; | |
1918 | case POWER_DOMAIN_VGA: | |
1919 | return "VGA"; | |
1920 | case POWER_DOMAIN_AUDIO: | |
1921 | return "AUDIO"; | |
1922 | case POWER_DOMAIN_INIT: | |
1923 | return "INIT"; | |
1924 | default: | |
1925 | WARN_ON(1); | |
1926 | return "?"; | |
1927 | } | |
1928 | } | |
1929 | ||
1930 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
1931 | { | |
1932 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1933 | struct drm_device *dev = node->minor->dev; | |
1934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1935 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1936 | int i; | |
1937 | ||
1938 | mutex_lock(&power_domains->lock); | |
1939 | ||
1940 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
1941 | for (i = 0; i < power_domains->power_well_count; i++) { | |
1942 | struct i915_power_well *power_well; | |
1943 | enum intel_display_power_domain power_domain; | |
1944 | ||
1945 | power_well = &power_domains->power_wells[i]; | |
1946 | seq_printf(m, "%-25s %d\n", power_well->name, | |
1947 | power_well->count); | |
1948 | ||
1949 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
1950 | power_domain++) { | |
1951 | if (!(BIT(power_domain) & power_well->domains)) | |
1952 | continue; | |
1953 | ||
1954 | seq_printf(m, " %-23s %d\n", | |
1955 | power_domain_str(power_domain), | |
1956 | power_domains->domain_use_count[power_domain]); | |
1957 | } | |
1958 | } | |
1959 | ||
1960 | mutex_unlock(&power_domains->lock); | |
1961 | ||
1962 | return 0; | |
1963 | } | |
1964 | ||
07144428 DL |
1965 | struct pipe_crc_info { |
1966 | const char *name; | |
1967 | struct drm_device *dev; | |
1968 | enum pipe pipe; | |
1969 | }; | |
1970 | ||
1971 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) | |
1972 | { | |
be5c7a90 DL |
1973 | struct pipe_crc_info *info = inode->i_private; |
1974 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
1975 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
1976 | ||
7eb1c496 DV |
1977 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
1978 | return -ENODEV; | |
1979 | ||
d538bbdf DL |
1980 | spin_lock_irq(&pipe_crc->lock); |
1981 | ||
1982 | if (pipe_crc->opened) { | |
1983 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
1984 | return -EBUSY; /* already open */ |
1985 | } | |
1986 | ||
d538bbdf | 1987 | pipe_crc->opened = true; |
07144428 DL |
1988 | filep->private_data = inode->i_private; |
1989 | ||
d538bbdf DL |
1990 | spin_unlock_irq(&pipe_crc->lock); |
1991 | ||
07144428 DL |
1992 | return 0; |
1993 | } | |
1994 | ||
1995 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
1996 | { | |
be5c7a90 DL |
1997 | struct pipe_crc_info *info = inode->i_private; |
1998 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
1999 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2000 | ||
d538bbdf DL |
2001 | spin_lock_irq(&pipe_crc->lock); |
2002 | pipe_crc->opened = false; | |
2003 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 2004 | |
07144428 DL |
2005 | return 0; |
2006 | } | |
2007 | ||
2008 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
2009 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
2010 | /* account for \'0' */ | |
2011 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
2012 | ||
2013 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 2014 | { |
d538bbdf DL |
2015 | assert_spin_locked(&pipe_crc->lock); |
2016 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
2017 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
2018 | } |
2019 | ||
2020 | static ssize_t | |
2021 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
2022 | loff_t *pos) | |
2023 | { | |
2024 | struct pipe_crc_info *info = filep->private_data; | |
2025 | struct drm_device *dev = info->dev; | |
2026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2027 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2028 | char buf[PIPE_CRC_BUFFER_LEN]; | |
2029 | int head, tail, n_entries, n; | |
2030 | ssize_t bytes_read; | |
2031 | ||
2032 | /* | |
2033 | * Don't allow user space to provide buffers not big enough to hold | |
2034 | * a line of data. | |
2035 | */ | |
2036 | if (count < PIPE_CRC_LINE_LEN) | |
2037 | return -EINVAL; | |
2038 | ||
2039 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 2040 | return 0; |
07144428 DL |
2041 | |
2042 | /* nothing to read */ | |
d538bbdf | 2043 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 2044 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
2045 | int ret; |
2046 | ||
2047 | if (filep->f_flags & O_NONBLOCK) { | |
2048 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 2049 | return -EAGAIN; |
d538bbdf | 2050 | } |
07144428 | 2051 | |
d538bbdf DL |
2052 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
2053 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
2054 | if (ret) { | |
2055 | spin_unlock_irq(&pipe_crc->lock); | |
2056 | return ret; | |
2057 | } | |
8bf1e9f1 SH |
2058 | } |
2059 | ||
07144428 | 2060 | /* We now have one or more entries to read */ |
d538bbdf DL |
2061 | head = pipe_crc->head; |
2062 | tail = pipe_crc->tail; | |
07144428 DL |
2063 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
2064 | count / PIPE_CRC_LINE_LEN); | |
d538bbdf DL |
2065 | spin_unlock_irq(&pipe_crc->lock); |
2066 | ||
07144428 DL |
2067 | bytes_read = 0; |
2068 | n = 0; | |
2069 | do { | |
b2c88f5b | 2070 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
07144428 | 2071 | int ret; |
8bf1e9f1 | 2072 | |
07144428 DL |
2073 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
2074 | "%8u %8x %8x %8x %8x %8x\n", | |
2075 | entry->frame, entry->crc[0], | |
2076 | entry->crc[1], entry->crc[2], | |
2077 | entry->crc[3], entry->crc[4]); | |
2078 | ||
2079 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, | |
2080 | buf, PIPE_CRC_LINE_LEN); | |
2081 | if (ret == PIPE_CRC_LINE_LEN) | |
2082 | return -EFAULT; | |
b2c88f5b DL |
2083 | |
2084 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
2085 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
07144428 DL |
2086 | n++; |
2087 | } while (--n_entries); | |
8bf1e9f1 | 2088 | |
d538bbdf DL |
2089 | spin_lock_irq(&pipe_crc->lock); |
2090 | pipe_crc->tail = tail; | |
2091 | spin_unlock_irq(&pipe_crc->lock); | |
2092 | ||
07144428 DL |
2093 | return bytes_read; |
2094 | } | |
2095 | ||
2096 | static const struct file_operations i915_pipe_crc_fops = { | |
2097 | .owner = THIS_MODULE, | |
2098 | .open = i915_pipe_crc_open, | |
2099 | .read = i915_pipe_crc_read, | |
2100 | .release = i915_pipe_crc_release, | |
2101 | }; | |
2102 | ||
2103 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
2104 | { | |
2105 | .name = "i915_pipe_A_crc", | |
2106 | .pipe = PIPE_A, | |
2107 | }, | |
2108 | { | |
2109 | .name = "i915_pipe_B_crc", | |
2110 | .pipe = PIPE_B, | |
2111 | }, | |
2112 | { | |
2113 | .name = "i915_pipe_C_crc", | |
2114 | .pipe = PIPE_C, | |
2115 | }, | |
2116 | }; | |
2117 | ||
2118 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
2119 | enum pipe pipe) | |
2120 | { | |
2121 | struct drm_device *dev = minor->dev; | |
2122 | struct dentry *ent; | |
2123 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
2124 | ||
2125 | info->dev = dev; | |
2126 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
2127 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
2128 | if (!ent) |
2129 | return -ENOMEM; | |
07144428 DL |
2130 | |
2131 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
2132 | } |
2133 | ||
e8dfcf78 | 2134 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
2135 | "none", |
2136 | "plane1", | |
2137 | "plane2", | |
2138 | "pf", | |
5b3a856b | 2139 | "pipe", |
3d099a05 DV |
2140 | "TV", |
2141 | "DP-B", | |
2142 | "DP-C", | |
2143 | "DP-D", | |
46a19188 | 2144 | "auto", |
926321d5 DV |
2145 | }; |
2146 | ||
2147 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
2148 | { | |
2149 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
2150 | return pipe_crc_sources[source]; | |
2151 | } | |
2152 | ||
bd9db02f | 2153 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
2154 | { |
2155 | struct drm_device *dev = m->private; | |
2156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2157 | int i; | |
2158 | ||
2159 | for (i = 0; i < I915_MAX_PIPES; i++) | |
2160 | seq_printf(m, "%c %s\n", pipe_name(i), | |
2161 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
2162 | ||
2163 | return 0; | |
2164 | } | |
2165 | ||
bd9db02f | 2166 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
2167 | { |
2168 | struct drm_device *dev = inode->i_private; | |
2169 | ||
bd9db02f | 2170 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
2171 | } |
2172 | ||
46a19188 | 2173 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
2174 | uint32_t *val) |
2175 | { | |
46a19188 DV |
2176 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2177 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2178 | ||
2179 | switch (*source) { | |
52f843f6 DV |
2180 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2181 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
2182 | break; | |
2183 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2184 | *val = 0; | |
2185 | break; | |
2186 | default: | |
2187 | return -EINVAL; | |
2188 | } | |
2189 | ||
2190 | return 0; | |
2191 | } | |
2192 | ||
46a19188 DV |
2193 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
2194 | enum intel_pipe_crc_source *source) | |
2195 | { | |
2196 | struct intel_encoder *encoder; | |
2197 | struct intel_crtc *crtc; | |
26756809 | 2198 | struct intel_digital_port *dig_port; |
46a19188 DV |
2199 | int ret = 0; |
2200 | ||
2201 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2202 | ||
2203 | mutex_lock(&dev->mode_config.mutex); | |
2204 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
2205 | base.head) { | |
2206 | if (!encoder->base.crtc) | |
2207 | continue; | |
2208 | ||
2209 | crtc = to_intel_crtc(encoder->base.crtc); | |
2210 | ||
2211 | if (crtc->pipe != pipe) | |
2212 | continue; | |
2213 | ||
2214 | switch (encoder->type) { | |
2215 | case INTEL_OUTPUT_TVOUT: | |
2216 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
2217 | break; | |
2218 | case INTEL_OUTPUT_DISPLAYPORT: | |
2219 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
2220 | dig_port = enc_to_dig_port(&encoder->base); |
2221 | switch (dig_port->port) { | |
2222 | case PORT_B: | |
2223 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
2224 | break; | |
2225 | case PORT_C: | |
2226 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
2227 | break; | |
2228 | case PORT_D: | |
2229 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
2230 | break; | |
2231 | default: | |
2232 | WARN(1, "nonexisting DP port %c\n", | |
2233 | port_name(dig_port->port)); | |
2234 | break; | |
2235 | } | |
46a19188 DV |
2236 | break; |
2237 | } | |
2238 | } | |
2239 | mutex_unlock(&dev->mode_config.mutex); | |
2240 | ||
2241 | return ret; | |
2242 | } | |
2243 | ||
2244 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
2245 | enum pipe pipe, | |
2246 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
2247 | uint32_t *val) |
2248 | { | |
8d2f24ca DV |
2249 | struct drm_i915_private *dev_priv = dev->dev_private; |
2250 | bool need_stable_symbols = false; | |
2251 | ||
46a19188 DV |
2252 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2253 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2254 | if (ret) | |
2255 | return ret; | |
2256 | } | |
2257 | ||
2258 | switch (*source) { | |
7ac0129b DV |
2259 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2260 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
2261 | break; | |
2262 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2263 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 2264 | need_stable_symbols = true; |
7ac0129b DV |
2265 | break; |
2266 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2267 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 2268 | need_stable_symbols = true; |
7ac0129b DV |
2269 | break; |
2270 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2271 | *val = 0; | |
2272 | break; | |
2273 | default: | |
2274 | return -EINVAL; | |
2275 | } | |
2276 | ||
8d2f24ca DV |
2277 | /* |
2278 | * When the pipe CRC tap point is after the transcoders we need | |
2279 | * to tweak symbol-level features to produce a deterministic series of | |
2280 | * symbols for a given frame. We need to reset those features only once | |
2281 | * a frame (instead of every nth symbol): | |
2282 | * - DC-balance: used to ensure a better clock recovery from the data | |
2283 | * link (SDVO) | |
2284 | * - DisplayPort scrambling: used for EMI reduction | |
2285 | */ | |
2286 | if (need_stable_symbols) { | |
2287 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2288 | ||
2289 | WARN_ON(!IS_G4X(dev)); | |
2290 | ||
2291 | tmp |= DC_BALANCE_RESET_VLV; | |
2292 | if (pipe == PIPE_A) | |
2293 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2294 | else | |
2295 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2296 | ||
2297 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2298 | } | |
2299 | ||
7ac0129b DV |
2300 | return 0; |
2301 | } | |
2302 | ||
4b79ebf7 | 2303 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
2304 | enum pipe pipe, |
2305 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
2306 | uint32_t *val) |
2307 | { | |
84093603 DV |
2308 | struct drm_i915_private *dev_priv = dev->dev_private; |
2309 | bool need_stable_symbols = false; | |
2310 | ||
46a19188 DV |
2311 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2312 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2313 | if (ret) | |
2314 | return ret; | |
2315 | } | |
2316 | ||
2317 | switch (*source) { | |
4b79ebf7 DV |
2318 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2319 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
2320 | break; | |
2321 | case INTEL_PIPE_CRC_SOURCE_TV: | |
2322 | if (!SUPPORTS_TV(dev)) | |
2323 | return -EINVAL; | |
2324 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
2325 | break; | |
2326 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2327 | if (!IS_G4X(dev)) | |
2328 | return -EINVAL; | |
2329 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 2330 | need_stable_symbols = true; |
4b79ebf7 DV |
2331 | break; |
2332 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2333 | if (!IS_G4X(dev)) | |
2334 | return -EINVAL; | |
2335 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 2336 | need_stable_symbols = true; |
4b79ebf7 DV |
2337 | break; |
2338 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
2339 | if (!IS_G4X(dev)) | |
2340 | return -EINVAL; | |
2341 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 2342 | need_stable_symbols = true; |
4b79ebf7 DV |
2343 | break; |
2344 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2345 | *val = 0; | |
2346 | break; | |
2347 | default: | |
2348 | return -EINVAL; | |
2349 | } | |
2350 | ||
84093603 DV |
2351 | /* |
2352 | * When the pipe CRC tap point is after the transcoders we need | |
2353 | * to tweak symbol-level features to produce a deterministic series of | |
2354 | * symbols for a given frame. We need to reset those features only once | |
2355 | * a frame (instead of every nth symbol): | |
2356 | * - DC-balance: used to ensure a better clock recovery from the data | |
2357 | * link (SDVO) | |
2358 | * - DisplayPort scrambling: used for EMI reduction | |
2359 | */ | |
2360 | if (need_stable_symbols) { | |
2361 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2362 | ||
2363 | WARN_ON(!IS_G4X(dev)); | |
2364 | ||
2365 | I915_WRITE(PORT_DFT_I9XX, | |
2366 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
2367 | ||
2368 | if (pipe == PIPE_A) | |
2369 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2370 | else | |
2371 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2372 | ||
2373 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2374 | } | |
2375 | ||
4b79ebf7 DV |
2376 | return 0; |
2377 | } | |
2378 | ||
8d2f24ca DV |
2379 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
2380 | enum pipe pipe) | |
2381 | { | |
2382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2383 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2384 | ||
2385 | if (pipe == PIPE_A) | |
2386 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2387 | else | |
2388 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2389 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) | |
2390 | tmp &= ~DC_BALANCE_RESET_VLV; | |
2391 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2392 | ||
2393 | } | |
2394 | ||
84093603 DV |
2395 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
2396 | enum pipe pipe) | |
2397 | { | |
2398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2399 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2400 | ||
2401 | if (pipe == PIPE_A) | |
2402 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2403 | else | |
2404 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2405 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2406 | ||
2407 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
2408 | I915_WRITE(PORT_DFT_I9XX, | |
2409 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
2410 | } | |
2411 | } | |
2412 | ||
46a19188 | 2413 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2414 | uint32_t *val) |
2415 | { | |
46a19188 DV |
2416 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2417 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2418 | ||
2419 | switch (*source) { | |
5b3a856b DV |
2420 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2421 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
2422 | break; | |
2423 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2424 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
2425 | break; | |
5b3a856b DV |
2426 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2427 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
2428 | break; | |
3d099a05 | 2429 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2430 | *val = 0; |
2431 | break; | |
3d099a05 DV |
2432 | default: |
2433 | return -EINVAL; | |
5b3a856b DV |
2434 | } |
2435 | ||
2436 | return 0; | |
2437 | } | |
2438 | ||
46a19188 | 2439 | static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2440 | uint32_t *val) |
2441 | { | |
46a19188 DV |
2442 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2443 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
2444 | ||
2445 | switch (*source) { | |
5b3a856b DV |
2446 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2447 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
2448 | break; | |
2449 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2450 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
2451 | break; | |
2452 | case INTEL_PIPE_CRC_SOURCE_PF: | |
2453 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; | |
2454 | break; | |
3d099a05 | 2455 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2456 | *val = 0; |
2457 | break; | |
3d099a05 DV |
2458 | default: |
2459 | return -EINVAL; | |
5b3a856b DV |
2460 | } |
2461 | ||
2462 | return 0; | |
2463 | } | |
2464 | ||
926321d5 DV |
2465 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
2466 | enum intel_pipe_crc_source source) | |
2467 | { | |
2468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 2469 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
432f3342 | 2470 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 2471 | int ret; |
926321d5 | 2472 | |
cc3da175 DL |
2473 | if (pipe_crc->source == source) |
2474 | return 0; | |
2475 | ||
ae676fcd DL |
2476 | /* forbid changing the source without going back to 'none' */ |
2477 | if (pipe_crc->source && source) | |
2478 | return -EINVAL; | |
2479 | ||
52f843f6 | 2480 | if (IS_GEN2(dev)) |
46a19188 | 2481 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 2482 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 2483 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 2484 | else if (IS_VALLEYVIEW(dev)) |
46a19188 | 2485 | ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val); |
4b79ebf7 | 2486 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 2487 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 2488 | else |
46a19188 | 2489 | ret = ivb_pipe_crc_ctl_reg(&source, &val); |
5b3a856b DV |
2490 | |
2491 | if (ret != 0) | |
2492 | return ret; | |
2493 | ||
4b584369 DL |
2494 | /* none -> real source transition */ |
2495 | if (source) { | |
7cd6ccff DL |
2496 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
2497 | pipe_name(pipe), pipe_crc_source_name(source)); | |
2498 | ||
e5f75aca DL |
2499 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
2500 | INTEL_PIPE_CRC_ENTRIES_NR, | |
2501 | GFP_KERNEL); | |
2502 | if (!pipe_crc->entries) | |
2503 | return -ENOMEM; | |
2504 | ||
d538bbdf DL |
2505 | spin_lock_irq(&pipe_crc->lock); |
2506 | pipe_crc->head = 0; | |
2507 | pipe_crc->tail = 0; | |
2508 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
2509 | } |
2510 | ||
cc3da175 | 2511 | pipe_crc->source = source; |
926321d5 | 2512 | |
926321d5 DV |
2513 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
2514 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
2515 | ||
e5f75aca DL |
2516 | /* real source -> none transition */ |
2517 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf DL |
2518 | struct intel_pipe_crc_entry *entries; |
2519 | ||
7cd6ccff DL |
2520 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
2521 | pipe_name(pipe)); | |
2522 | ||
bcf17ab2 DV |
2523 | intel_wait_for_vblank(dev, pipe); |
2524 | ||
d538bbdf DL |
2525 | spin_lock_irq(&pipe_crc->lock); |
2526 | entries = pipe_crc->entries; | |
e5f75aca | 2527 | pipe_crc->entries = NULL; |
d538bbdf DL |
2528 | spin_unlock_irq(&pipe_crc->lock); |
2529 | ||
2530 | kfree(entries); | |
84093603 DV |
2531 | |
2532 | if (IS_G4X(dev)) | |
2533 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
2534 | else if (IS_VALLEYVIEW(dev)) |
2535 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
e5f75aca DL |
2536 | } |
2537 | ||
926321d5 DV |
2538 | return 0; |
2539 | } | |
2540 | ||
2541 | /* | |
2542 | * Parse pipe CRC command strings: | |
b94dec87 DL |
2543 | * command: wsp* object wsp+ name wsp+ source wsp* |
2544 | * object: 'pipe' | |
2545 | * name: (A | B | C) | |
926321d5 DV |
2546 | * source: (none | plane1 | plane2 | pf) |
2547 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
2548 | * | |
2549 | * eg.: | |
b94dec87 DL |
2550 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
2551 | * "pipe A none" -> Stop CRC | |
926321d5 | 2552 | */ |
bd9db02f | 2553 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
2554 | { |
2555 | int n_words = 0; | |
2556 | ||
2557 | while (*buf) { | |
2558 | char *end; | |
2559 | ||
2560 | /* skip leading white space */ | |
2561 | buf = skip_spaces(buf); | |
2562 | if (!*buf) | |
2563 | break; /* end of buffer */ | |
2564 | ||
2565 | /* find end of word */ | |
2566 | for (end = buf; *end && !isspace(*end); end++) | |
2567 | ; | |
2568 | ||
2569 | if (n_words == max_words) { | |
2570 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
2571 | max_words); | |
2572 | return -EINVAL; /* ran out of words[] before bytes */ | |
2573 | } | |
2574 | ||
2575 | if (*end) | |
2576 | *end++ = '\0'; | |
2577 | words[n_words++] = buf; | |
2578 | buf = end; | |
2579 | } | |
2580 | ||
2581 | return n_words; | |
2582 | } | |
2583 | ||
b94dec87 DL |
2584 | enum intel_pipe_crc_object { |
2585 | PIPE_CRC_OBJECT_PIPE, | |
2586 | }; | |
2587 | ||
e8dfcf78 | 2588 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
2589 | "pipe", |
2590 | }; | |
2591 | ||
2592 | static int | |
bd9db02f | 2593 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
2594 | { |
2595 | int i; | |
2596 | ||
2597 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
2598 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 2599 | *o = i; |
b94dec87 DL |
2600 | return 0; |
2601 | } | |
2602 | ||
2603 | return -EINVAL; | |
2604 | } | |
2605 | ||
bd9db02f | 2606 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
2607 | { |
2608 | const char name = buf[0]; | |
2609 | ||
2610 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
2611 | return -EINVAL; | |
2612 | ||
2613 | *pipe = name - 'A'; | |
2614 | ||
2615 | return 0; | |
2616 | } | |
2617 | ||
2618 | static int | |
bd9db02f | 2619 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
2620 | { |
2621 | int i; | |
2622 | ||
2623 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
2624 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 2625 | *s = i; |
926321d5 DV |
2626 | return 0; |
2627 | } | |
2628 | ||
2629 | return -EINVAL; | |
2630 | } | |
2631 | ||
bd9db02f | 2632 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 2633 | { |
b94dec87 | 2634 | #define N_WORDS 3 |
926321d5 | 2635 | int n_words; |
b94dec87 | 2636 | char *words[N_WORDS]; |
926321d5 | 2637 | enum pipe pipe; |
b94dec87 | 2638 | enum intel_pipe_crc_object object; |
926321d5 DV |
2639 | enum intel_pipe_crc_source source; |
2640 | ||
bd9db02f | 2641 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
2642 | if (n_words != N_WORDS) { |
2643 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
2644 | N_WORDS); | |
2645 | return -EINVAL; | |
2646 | } | |
2647 | ||
bd9db02f | 2648 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 2649 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
2650 | return -EINVAL; |
2651 | } | |
2652 | ||
bd9db02f | 2653 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 2654 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
2655 | return -EINVAL; |
2656 | } | |
2657 | ||
bd9db02f | 2658 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 2659 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
2660 | return -EINVAL; |
2661 | } | |
2662 | ||
2663 | return pipe_crc_set_source(dev, pipe, source); | |
2664 | } | |
2665 | ||
bd9db02f DL |
2666 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
2667 | size_t len, loff_t *offp) | |
926321d5 DV |
2668 | { |
2669 | struct seq_file *m = file->private_data; | |
2670 | struct drm_device *dev = m->private; | |
2671 | char *tmpbuf; | |
2672 | int ret; | |
2673 | ||
2674 | if (len == 0) | |
2675 | return 0; | |
2676 | ||
2677 | if (len > PAGE_SIZE - 1) { | |
2678 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
2679 | PAGE_SIZE); | |
2680 | return -E2BIG; | |
2681 | } | |
2682 | ||
2683 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
2684 | if (!tmpbuf) | |
2685 | return -ENOMEM; | |
2686 | ||
2687 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
2688 | ret = -EFAULT; | |
2689 | goto out; | |
2690 | } | |
2691 | tmpbuf[len] = '\0'; | |
2692 | ||
bd9db02f | 2693 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
2694 | |
2695 | out: | |
2696 | kfree(tmpbuf); | |
2697 | if (ret < 0) | |
2698 | return ret; | |
2699 | ||
2700 | *offp += len; | |
2701 | return len; | |
2702 | } | |
2703 | ||
bd9db02f | 2704 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 2705 | .owner = THIS_MODULE, |
bd9db02f | 2706 | .open = display_crc_ctl_open, |
926321d5 DV |
2707 | .read = seq_read, |
2708 | .llseek = seq_lseek, | |
2709 | .release = single_release, | |
bd9db02f | 2710 | .write = display_crc_ctl_write |
926321d5 DV |
2711 | }; |
2712 | ||
647416f9 KC |
2713 | static int |
2714 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 2715 | { |
647416f9 | 2716 | struct drm_device *dev = data; |
f3cd474b | 2717 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 2718 | |
647416f9 | 2719 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 2720 | |
647416f9 | 2721 | return 0; |
f3cd474b CW |
2722 | } |
2723 | ||
647416f9 KC |
2724 | static int |
2725 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 2726 | { |
647416f9 | 2727 | struct drm_device *dev = data; |
f3cd474b | 2728 | |
647416f9 | 2729 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 2730 | i915_handle_error(dev, val); |
f3cd474b | 2731 | |
647416f9 | 2732 | return 0; |
f3cd474b CW |
2733 | } |
2734 | ||
647416f9 KC |
2735 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
2736 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 2737 | "%llu\n"); |
f3cd474b | 2738 | |
647416f9 KC |
2739 | static int |
2740 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 2741 | { |
647416f9 | 2742 | struct drm_device *dev = data; |
e5eb3d63 | 2743 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 2744 | |
647416f9 | 2745 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 2746 | |
647416f9 | 2747 | return 0; |
e5eb3d63 DV |
2748 | } |
2749 | ||
647416f9 KC |
2750 | static int |
2751 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 2752 | { |
647416f9 | 2753 | struct drm_device *dev = data; |
e5eb3d63 | 2754 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2755 | int ret; |
e5eb3d63 | 2756 | |
647416f9 | 2757 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 2758 | |
22bcfc6a DV |
2759 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2760 | if (ret) | |
2761 | return ret; | |
2762 | ||
99584db3 | 2763 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
2764 | mutex_unlock(&dev->struct_mutex); |
2765 | ||
647416f9 | 2766 | return 0; |
e5eb3d63 DV |
2767 | } |
2768 | ||
647416f9 KC |
2769 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
2770 | i915_ring_stop_get, i915_ring_stop_set, | |
2771 | "0x%08llx\n"); | |
d5442303 | 2772 | |
094f9a54 CW |
2773 | static int |
2774 | i915_ring_missed_irq_get(void *data, u64 *val) | |
2775 | { | |
2776 | struct drm_device *dev = data; | |
2777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2778 | ||
2779 | *val = dev_priv->gpu_error.missed_irq_rings; | |
2780 | return 0; | |
2781 | } | |
2782 | ||
2783 | static int | |
2784 | i915_ring_missed_irq_set(void *data, u64 val) | |
2785 | { | |
2786 | struct drm_device *dev = data; | |
2787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2788 | int ret; | |
2789 | ||
2790 | /* Lock against concurrent debugfs callers */ | |
2791 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2792 | if (ret) | |
2793 | return ret; | |
2794 | dev_priv->gpu_error.missed_irq_rings = val; | |
2795 | mutex_unlock(&dev->struct_mutex); | |
2796 | ||
2797 | return 0; | |
2798 | } | |
2799 | ||
2800 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
2801 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
2802 | "0x%08llx\n"); | |
2803 | ||
2804 | static int | |
2805 | i915_ring_test_irq_get(void *data, u64 *val) | |
2806 | { | |
2807 | struct drm_device *dev = data; | |
2808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2809 | ||
2810 | *val = dev_priv->gpu_error.test_irq_rings; | |
2811 | ||
2812 | return 0; | |
2813 | } | |
2814 | ||
2815 | static int | |
2816 | i915_ring_test_irq_set(void *data, u64 val) | |
2817 | { | |
2818 | struct drm_device *dev = data; | |
2819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2820 | int ret; | |
2821 | ||
2822 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
2823 | ||
2824 | /* Lock against concurrent debugfs callers */ | |
2825 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2826 | if (ret) | |
2827 | return ret; | |
2828 | ||
2829 | dev_priv->gpu_error.test_irq_rings = val; | |
2830 | mutex_unlock(&dev->struct_mutex); | |
2831 | ||
2832 | return 0; | |
2833 | } | |
2834 | ||
2835 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
2836 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
2837 | "0x%08llx\n"); | |
2838 | ||
dd624afd CW |
2839 | #define DROP_UNBOUND 0x1 |
2840 | #define DROP_BOUND 0x2 | |
2841 | #define DROP_RETIRE 0x4 | |
2842 | #define DROP_ACTIVE 0x8 | |
2843 | #define DROP_ALL (DROP_UNBOUND | \ | |
2844 | DROP_BOUND | \ | |
2845 | DROP_RETIRE | \ | |
2846 | DROP_ACTIVE) | |
647416f9 KC |
2847 | static int |
2848 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 2849 | { |
647416f9 | 2850 | *val = DROP_ALL; |
dd624afd | 2851 | |
647416f9 | 2852 | return 0; |
dd624afd CW |
2853 | } |
2854 | ||
647416f9 KC |
2855 | static int |
2856 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 2857 | { |
647416f9 | 2858 | struct drm_device *dev = data; |
dd624afd CW |
2859 | struct drm_i915_private *dev_priv = dev->dev_private; |
2860 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
2861 | struct i915_address_space *vm; |
2862 | struct i915_vma *vma, *x; | |
647416f9 | 2863 | int ret; |
dd624afd | 2864 | |
2f9fe5ff | 2865 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
2866 | |
2867 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
2868 | * on ioctls on -EAGAIN. */ | |
2869 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2870 | if (ret) | |
2871 | return ret; | |
2872 | ||
2873 | if (val & DROP_ACTIVE) { | |
2874 | ret = i915_gpu_idle(dev); | |
2875 | if (ret) | |
2876 | goto unlock; | |
2877 | } | |
2878 | ||
2879 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
2880 | i915_gem_retire_requests(dev); | |
2881 | ||
2882 | if (val & DROP_BOUND) { | |
ca191b13 BW |
2883 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2884 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
2885 | mm_list) { | |
2886 | if (vma->obj->pin_count) | |
2887 | continue; | |
2888 | ||
2889 | ret = i915_vma_unbind(vma); | |
2890 | if (ret) | |
2891 | goto unlock; | |
2892 | } | |
31a46c9c | 2893 | } |
dd624afd CW |
2894 | } |
2895 | ||
2896 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
2897 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
2898 | global_list) | |
dd624afd CW |
2899 | if (obj->pages_pin_count == 0) { |
2900 | ret = i915_gem_object_put_pages(obj); | |
2901 | if (ret) | |
2902 | goto unlock; | |
2903 | } | |
2904 | } | |
2905 | ||
2906 | unlock: | |
2907 | mutex_unlock(&dev->struct_mutex); | |
2908 | ||
647416f9 | 2909 | return ret; |
dd624afd CW |
2910 | } |
2911 | ||
647416f9 KC |
2912 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
2913 | i915_drop_caches_get, i915_drop_caches_set, | |
2914 | "0x%08llx\n"); | |
dd624afd | 2915 | |
647416f9 KC |
2916 | static int |
2917 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 2918 | { |
647416f9 | 2919 | struct drm_device *dev = data; |
358733e9 | 2920 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2921 | int ret; |
004777cb DV |
2922 | |
2923 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2924 | return -ENODEV; | |
2925 | ||
5c9669ce TR |
2926 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2927 | ||
4fc688ce | 2928 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2929 | if (ret) |
2930 | return ret; | |
358733e9 | 2931 | |
0a073b84 | 2932 | if (IS_VALLEYVIEW(dev)) |
2ec3815f | 2933 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay); |
0a073b84 JB |
2934 | else |
2935 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2936 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2937 | |
647416f9 | 2938 | return 0; |
358733e9 JB |
2939 | } |
2940 | ||
647416f9 KC |
2941 | static int |
2942 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 2943 | { |
647416f9 | 2944 | struct drm_device *dev = data; |
358733e9 | 2945 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2946 | int ret; |
004777cb DV |
2947 | |
2948 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2949 | return -ENODEV; | |
358733e9 | 2950 | |
5c9669ce TR |
2951 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2952 | ||
647416f9 | 2953 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 2954 | |
4fc688ce | 2955 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2956 | if (ret) |
2957 | return ret; | |
2958 | ||
358733e9 JB |
2959 | /* |
2960 | * Turbo will still be enabled, but won't go above the set value. | |
2961 | */ | |
0a073b84 | 2962 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 2963 | val = vlv_freq_opcode(dev_priv, val); |
0a073b84 | 2964 | dev_priv->rps.max_delay = val; |
6917c7b9 | 2965 | valleyview_set_rps(dev, val); |
0a073b84 JB |
2966 | } else { |
2967 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2968 | dev_priv->rps.max_delay = val; | |
2969 | gen6_set_rps(dev, val); | |
2970 | } | |
2971 | ||
4fc688ce | 2972 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2973 | |
647416f9 | 2974 | return 0; |
358733e9 JB |
2975 | } |
2976 | ||
647416f9 KC |
2977 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
2978 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 2979 | "%llu\n"); |
358733e9 | 2980 | |
647416f9 KC |
2981 | static int |
2982 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 2983 | { |
647416f9 | 2984 | struct drm_device *dev = data; |
1523c310 | 2985 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2986 | int ret; |
004777cb DV |
2987 | |
2988 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2989 | return -ENODEV; | |
2990 | ||
5c9669ce TR |
2991 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2992 | ||
4fc688ce | 2993 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2994 | if (ret) |
2995 | return ret; | |
1523c310 | 2996 | |
0a073b84 | 2997 | if (IS_VALLEYVIEW(dev)) |
2ec3815f | 2998 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay); |
0a073b84 JB |
2999 | else |
3000 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 3001 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3002 | |
647416f9 | 3003 | return 0; |
1523c310 JB |
3004 | } |
3005 | ||
647416f9 KC |
3006 | static int |
3007 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 3008 | { |
647416f9 | 3009 | struct drm_device *dev = data; |
1523c310 | 3010 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3011 | int ret; |
004777cb DV |
3012 | |
3013 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
3014 | return -ENODEV; | |
1523c310 | 3015 | |
5c9669ce TR |
3016 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3017 | ||
647416f9 | 3018 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 3019 | |
4fc688ce | 3020 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3021 | if (ret) |
3022 | return ret; | |
3023 | ||
1523c310 JB |
3024 | /* |
3025 | * Turbo will still be enabled, but won't go below the set value. | |
3026 | */ | |
0a073b84 | 3027 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3028 | val = vlv_freq_opcode(dev_priv, val); |
0a073b84 JB |
3029 | dev_priv->rps.min_delay = val; |
3030 | valleyview_set_rps(dev, val); | |
3031 | } else { | |
3032 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
3033 | dev_priv->rps.min_delay = val; | |
3034 | gen6_set_rps(dev, val); | |
3035 | } | |
4fc688ce | 3036 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3037 | |
647416f9 | 3038 | return 0; |
1523c310 JB |
3039 | } |
3040 | ||
647416f9 KC |
3041 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
3042 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 3043 | "%llu\n"); |
1523c310 | 3044 | |
647416f9 KC |
3045 | static int |
3046 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 3047 | { |
647416f9 | 3048 | struct drm_device *dev = data; |
07b7ddd9 | 3049 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 3050 | u32 snpcr; |
647416f9 | 3051 | int ret; |
07b7ddd9 | 3052 | |
004777cb DV |
3053 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3054 | return -ENODEV; | |
3055 | ||
22bcfc6a DV |
3056 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3057 | if (ret) | |
3058 | return ret; | |
c8c8fb33 | 3059 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 3060 | |
07b7ddd9 | 3061 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
3062 | |
3063 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
3064 | mutex_unlock(&dev_priv->dev->struct_mutex); |
3065 | ||
647416f9 | 3066 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 3067 | |
647416f9 | 3068 | return 0; |
07b7ddd9 JB |
3069 | } |
3070 | ||
647416f9 KC |
3071 | static int |
3072 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 3073 | { |
647416f9 | 3074 | struct drm_device *dev = data; |
07b7ddd9 | 3075 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3076 | u32 snpcr; |
07b7ddd9 | 3077 | |
004777cb DV |
3078 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3079 | return -ENODEV; | |
3080 | ||
647416f9 | 3081 | if (val > 3) |
07b7ddd9 JB |
3082 | return -EINVAL; |
3083 | ||
c8c8fb33 | 3084 | intel_runtime_pm_get(dev_priv); |
647416f9 | 3085 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
3086 | |
3087 | /* Update the cache sharing policy here as well */ | |
3088 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
3089 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
3090 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
3091 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3092 | ||
c8c8fb33 | 3093 | intel_runtime_pm_put(dev_priv); |
647416f9 | 3094 | return 0; |
07b7ddd9 JB |
3095 | } |
3096 | ||
647416f9 KC |
3097 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
3098 | i915_cache_sharing_get, i915_cache_sharing_set, | |
3099 | "%llu\n"); | |
07b7ddd9 | 3100 | |
6d794d42 BW |
3101 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
3102 | { | |
3103 | struct drm_device *dev = inode->i_private; | |
3104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 3105 | |
075edca4 | 3106 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3107 | return 0; |
3108 | ||
c8c8fb33 | 3109 | intel_runtime_pm_get(dev_priv); |
c8d9a590 | 3110 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3111 | |
3112 | return 0; | |
3113 | } | |
3114 | ||
c43b5634 | 3115 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
3116 | { |
3117 | struct drm_device *dev = inode->i_private; | |
3118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3119 | ||
075edca4 | 3120 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3121 | return 0; |
3122 | ||
c8d9a590 | 3123 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
c8c8fb33 | 3124 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
3125 | |
3126 | return 0; | |
3127 | } | |
3128 | ||
3129 | static const struct file_operations i915_forcewake_fops = { | |
3130 | .owner = THIS_MODULE, | |
3131 | .open = i915_forcewake_open, | |
3132 | .release = i915_forcewake_release, | |
3133 | }; | |
3134 | ||
3135 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
3136 | { | |
3137 | struct drm_device *dev = minor->dev; | |
3138 | struct dentry *ent; | |
3139 | ||
3140 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 3141 | S_IRUSR, |
6d794d42 BW |
3142 | root, dev, |
3143 | &i915_forcewake_fops); | |
f3c5fe97 WY |
3144 | if (!ent) |
3145 | return -ENOMEM; | |
6d794d42 | 3146 | |
8eb57294 | 3147 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
3148 | } |
3149 | ||
6a9c308d DV |
3150 | static int i915_debugfs_create(struct dentry *root, |
3151 | struct drm_minor *minor, | |
3152 | const char *name, | |
3153 | const struct file_operations *fops) | |
07b7ddd9 JB |
3154 | { |
3155 | struct drm_device *dev = minor->dev; | |
3156 | struct dentry *ent; | |
3157 | ||
6a9c308d | 3158 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
3159 | S_IRUGO | S_IWUSR, |
3160 | root, dev, | |
6a9c308d | 3161 | fops); |
f3c5fe97 WY |
3162 | if (!ent) |
3163 | return -ENOMEM; | |
07b7ddd9 | 3164 | |
6a9c308d | 3165 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
3166 | } |
3167 | ||
06c5bf8c | 3168 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 3169 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 3170 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 3171 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 3172 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 3173 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 3174 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 3175 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 3176 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
3177 | {"i915_gem_request", i915_gem_request_info, 0}, |
3178 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 3179 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 3180 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
3181 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
3182 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
3183 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 3184 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
3185 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
3186 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
3187 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
3188 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
3189 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 3190 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 3191 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 3192 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 3193 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 3194 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 3195 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 3196 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 3197 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 3198 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 3199 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 3200 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 3201 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 3202 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 3203 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 3204 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
ec013e7f | 3205 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 3206 | {"i915_pc8_status", i915_pc8_status, 0}, |
1da51581 | 3207 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
2017263e | 3208 | }; |
27c202ad | 3209 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 3210 | |
06c5bf8c | 3211 | static const struct i915_debugfs_files { |
34b9674c DV |
3212 | const char *name; |
3213 | const struct file_operations *fops; | |
3214 | } i915_debugfs_files[] = { | |
3215 | {"i915_wedged", &i915_wedged_fops}, | |
3216 | {"i915_max_freq", &i915_max_freq_fops}, | |
3217 | {"i915_min_freq", &i915_min_freq_fops}, | |
3218 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
3219 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
3220 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
3221 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
3222 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
3223 | {"i915_error_state", &i915_error_state_fops}, | |
3224 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 3225 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
34b9674c DV |
3226 | }; |
3227 | ||
07144428 DL |
3228 | void intel_display_crc_init(struct drm_device *dev) |
3229 | { | |
3230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 3231 | enum pipe pipe; |
07144428 | 3232 | |
b378360e DV |
3233 | for_each_pipe(pipe) { |
3234 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
07144428 | 3235 | |
d538bbdf DL |
3236 | pipe_crc->opened = false; |
3237 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
3238 | init_waitqueue_head(&pipe_crc->wq); |
3239 | } | |
3240 | } | |
3241 | ||
27c202ad | 3242 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 3243 | { |
34b9674c | 3244 | int ret, i; |
f3cd474b | 3245 | |
6d794d42 | 3246 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
3247 | if (ret) |
3248 | return ret; | |
6a9c308d | 3249 | |
07144428 DL |
3250 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
3251 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
3252 | if (ret) | |
3253 | return ret; | |
3254 | } | |
3255 | ||
34b9674c DV |
3256 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3257 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
3258 | i915_debugfs_files[i].name, | |
3259 | i915_debugfs_files[i].fops); | |
3260 | if (ret) | |
3261 | return ret; | |
3262 | } | |
40633219 | 3263 | |
27c202ad BG |
3264 | return drm_debugfs_create_files(i915_debugfs_list, |
3265 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
3266 | minor->debugfs_root, minor); |
3267 | } | |
3268 | ||
27c202ad | 3269 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 3270 | { |
34b9674c DV |
3271 | int i; |
3272 | ||
27c202ad BG |
3273 | drm_debugfs_remove_files(i915_debugfs_list, |
3274 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 3275 | |
6d794d42 BW |
3276 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
3277 | 1, minor); | |
07144428 | 3278 | |
e309a997 | 3279 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
3280 | struct drm_info_list *info_list = |
3281 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
3282 | ||
3283 | drm_debugfs_remove_files(info_list, 1, minor); | |
3284 | } | |
3285 | ||
34b9674c DV |
3286 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3287 | struct drm_info_list *info_list = | |
3288 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
3289 | ||
3290 | drm_debugfs_remove_files(info_list, 1, minor); | |
3291 | } | |
2017263e | 3292 | } |