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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
e637d2cb | 30 | #include <linux/sort.h> |
d92a8cfc | 31 | #include <linux/sched/mm.h> |
4e5359cd | 32 | #include "intel_drv.h" |
a2695744 | 33 | #include "intel_guc_submission.h" |
2017263e | 34 | |
36cdd013 DW |
35 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
36 | { | |
37 | return to_i915(node->minor->dev); | |
38 | } | |
39 | ||
70d39fe4 CW |
40 | static int i915_capabilities(struct seq_file *m, void *data) |
41 | { | |
36cdd013 DW |
42 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
43 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
a8c9b849 | 44 | struct drm_printer p = drm_seq_file_printer(m); |
70d39fe4 | 45 | |
36cdd013 | 46 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 47 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 48 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 49 | |
a8c9b849 | 50 | intel_device_info_dump_flags(info, &p); |
5fbbe8d4 | 51 | intel_device_info_dump_runtime(info, &p); |
3fed1808 | 52 | intel_driver_caps_print(&dev_priv->caps, &p); |
70d39fe4 | 53 | |
418e3cd8 | 54 | kernel_param_lock(THIS_MODULE); |
acfb9973 | 55 | i915_params_dump(&i915_modparams, &p); |
418e3cd8 CW |
56 | kernel_param_unlock(THIS_MODULE); |
57 | ||
70d39fe4 CW |
58 | return 0; |
59 | } | |
2017263e | 60 | |
a7363de7 | 61 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 62 | { |
573adb39 | 63 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
64 | } |
65 | ||
a7363de7 | 66 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b | 67 | { |
bd3d2252 | 68 | return obj->pin_global ? 'p' : ' '; |
be12a86b TU |
69 | } |
70 | ||
a7363de7 | 71 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 72 | { |
3e510a8e | 73 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 74 | default: |
be12a86b TU |
75 | case I915_TILING_NONE: return ' '; |
76 | case I915_TILING_X: return 'X'; | |
77 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 78 | } |
a6172a80 CW |
79 | } |
80 | ||
a7363de7 | 81 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 82 | { |
a65adaf8 | 83 | return obj->userfault_count ? 'g' : ' '; |
be12a86b TU |
84 | } |
85 | ||
a7363de7 | 86 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 87 | { |
a4f5ea64 | 88 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
89 | } |
90 | ||
ca1543be TU |
91 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
92 | { | |
93 | u64 size = 0; | |
94 | struct i915_vma *vma; | |
95 | ||
e2189dd0 CW |
96 | for_each_ggtt_vma(vma, obj) { |
97 | if (drm_mm_node_allocated(&vma->node)) | |
ca1543be TU |
98 | size += vma->node.size; |
99 | } | |
100 | ||
101 | return size; | |
102 | } | |
103 | ||
7393b7ee MA |
104 | static const char * |
105 | stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) | |
106 | { | |
107 | size_t x = 0; | |
108 | ||
109 | switch (page_sizes) { | |
110 | case 0: | |
111 | return ""; | |
112 | case I915_GTT_PAGE_SIZE_4K: | |
113 | return "4K"; | |
114 | case I915_GTT_PAGE_SIZE_64K: | |
115 | return "64K"; | |
116 | case I915_GTT_PAGE_SIZE_2M: | |
117 | return "2M"; | |
118 | default: | |
119 | if (!buf) | |
120 | return "M"; | |
121 | ||
122 | if (page_sizes & I915_GTT_PAGE_SIZE_2M) | |
123 | x += snprintf(buf + x, len - x, "2M, "); | |
124 | if (page_sizes & I915_GTT_PAGE_SIZE_64K) | |
125 | x += snprintf(buf + x, len - x, "64K, "); | |
126 | if (page_sizes & I915_GTT_PAGE_SIZE_4K) | |
127 | x += snprintf(buf + x, len - x, "4K, "); | |
128 | buf[x-2] = '\0'; | |
129 | ||
130 | return buf; | |
131 | } | |
132 | } | |
133 | ||
37811fcc CW |
134 | static void |
135 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
136 | { | |
b4716185 | 137 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 138 | struct intel_engine_cs *engine; |
1d693bcc | 139 | struct i915_vma *vma; |
faf5bf0a | 140 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
141 | int pin_count = 0; |
142 | ||
188c1ab7 CW |
143 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
144 | ||
d07f0e59 | 145 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 146 | &obj->base, |
be12a86b | 147 | get_active_flag(obj), |
37811fcc CW |
148 | get_pin_flag(obj), |
149 | get_tiling_flag(obj), | |
1d693bcc | 150 | get_global_flag(obj), |
be12a86b | 151 | get_pin_mapped_flag(obj), |
a05a5862 | 152 | obj->base.size / 1024, |
c0a51fd0 CK |
153 | obj->read_domains, |
154 | obj->write_domain, | |
36cdd013 | 155 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
156 | obj->mm.dirty ? " dirty" : "", |
157 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
158 | if (obj->base.name) |
159 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 160 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 161 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 162 | pin_count++; |
ba0635ff DC |
163 | } |
164 | seq_printf(m, " (pinned x %d)", pin_count); | |
bd3d2252 CW |
165 | if (obj->pin_global) |
166 | seq_printf(m, " (global)"); | |
1c7f4bca | 167 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
168 | if (!drm_mm_node_allocated(&vma->node)) |
169 | continue; | |
170 | ||
7393b7ee | 171 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s", |
3272db53 | 172 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
7393b7ee MA |
173 | vma->node.start, vma->node.size, |
174 | stringify_page_sizes(vma->page_sizes.gtt, NULL, 0)); | |
21976853 CW |
175 | if (i915_vma_is_ggtt(vma)) { |
176 | switch (vma->ggtt_view.type) { | |
177 | case I915_GGTT_VIEW_NORMAL: | |
178 | seq_puts(m, ", normal"); | |
179 | break; | |
180 | ||
181 | case I915_GGTT_VIEW_PARTIAL: | |
182 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
183 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
184 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
185 | break; |
186 | ||
187 | case I915_GGTT_VIEW_ROTATED: | |
188 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
189 | vma->ggtt_view.rotated.plane[0].width, |
190 | vma->ggtt_view.rotated.plane[0].height, | |
191 | vma->ggtt_view.rotated.plane[0].stride, | |
192 | vma->ggtt_view.rotated.plane[0].offset, | |
193 | vma->ggtt_view.rotated.plane[1].width, | |
194 | vma->ggtt_view.rotated.plane[1].height, | |
195 | vma->ggtt_view.rotated.plane[1].stride, | |
196 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
197 | break; |
198 | ||
199 | default: | |
200 | MISSING_CASE(vma->ggtt_view.type); | |
201 | break; | |
202 | } | |
203 | } | |
49ef5294 CW |
204 | if (vma->fence) |
205 | seq_printf(m, " , fence: %d%s", | |
206 | vma->fence->id, | |
207 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 208 | seq_puts(m, ")"); |
1d693bcc | 209 | } |
c1ad11fc | 210 | if (obj->stolen) |
440fd528 | 211 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 212 | |
d07f0e59 | 213 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
214 | if (engine) |
215 | seq_printf(m, " (%s)", engine->name); | |
216 | ||
faf5bf0a CW |
217 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
218 | if (frontbuffer_bits) | |
219 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
220 | } |
221 | ||
e637d2cb | 222 | static int obj_rank_by_stolen(const void *A, const void *B) |
6d2b8885 | 223 | { |
e637d2cb CW |
224 | const struct drm_i915_gem_object *a = |
225 | *(const struct drm_i915_gem_object **)A; | |
226 | const struct drm_i915_gem_object *b = | |
227 | *(const struct drm_i915_gem_object **)B; | |
6d2b8885 | 228 | |
2d05fa16 RV |
229 | if (a->stolen->start < b->stolen->start) |
230 | return -1; | |
231 | if (a->stolen->start > b->stolen->start) | |
232 | return 1; | |
233 | return 0; | |
6d2b8885 CW |
234 | } |
235 | ||
236 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
237 | { | |
36cdd013 DW |
238 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
239 | struct drm_device *dev = &dev_priv->drm; | |
e637d2cb | 240 | struct drm_i915_gem_object **objects; |
6d2b8885 | 241 | struct drm_i915_gem_object *obj; |
c44ef60e | 242 | u64 total_obj_size, total_gtt_size; |
e637d2cb CW |
243 | unsigned long total, count, n; |
244 | int ret; | |
245 | ||
246 | total = READ_ONCE(dev_priv->mm.object_count); | |
2098105e | 247 | objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL); |
e637d2cb CW |
248 | if (!objects) |
249 | return -ENOMEM; | |
6d2b8885 CW |
250 | |
251 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
252 | if (ret) | |
e637d2cb | 253 | goto out; |
6d2b8885 CW |
254 | |
255 | total_obj_size = total_gtt_size = count = 0; | |
f2123818 CW |
256 | |
257 | spin_lock(&dev_priv->mm.obj_lock); | |
258 | list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { | |
e637d2cb CW |
259 | if (count == total) |
260 | break; | |
261 | ||
6d2b8885 CW |
262 | if (obj->stolen == NULL) |
263 | continue; | |
264 | ||
e637d2cb | 265 | objects[count++] = obj; |
6d2b8885 | 266 | total_obj_size += obj->base.size; |
ca1543be | 267 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
e637d2cb | 268 | |
6d2b8885 | 269 | } |
f2123818 | 270 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) { |
e637d2cb CW |
271 | if (count == total) |
272 | break; | |
273 | ||
6d2b8885 CW |
274 | if (obj->stolen == NULL) |
275 | continue; | |
276 | ||
e637d2cb | 277 | objects[count++] = obj; |
6d2b8885 | 278 | total_obj_size += obj->base.size; |
6d2b8885 | 279 | } |
f2123818 | 280 | spin_unlock(&dev_priv->mm.obj_lock); |
e637d2cb CW |
281 | |
282 | sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL); | |
283 | ||
6d2b8885 | 284 | seq_puts(m, "Stolen:\n"); |
e637d2cb | 285 | for (n = 0; n < count; n++) { |
6d2b8885 | 286 | seq_puts(m, " "); |
e637d2cb | 287 | describe_obj(m, objects[n]); |
6d2b8885 | 288 | seq_putc(m, '\n'); |
6d2b8885 | 289 | } |
e637d2cb | 290 | seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n", |
6d2b8885 | 291 | count, total_obj_size, total_gtt_size); |
e637d2cb CW |
292 | |
293 | mutex_unlock(&dev->struct_mutex); | |
294 | out: | |
2098105e | 295 | kvfree(objects); |
e637d2cb | 296 | return ret; |
6d2b8885 CW |
297 | } |
298 | ||
2db8e9d6 | 299 | struct file_stats { |
6313c204 | 300 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
301 | unsigned long count; |
302 | u64 total, unbound; | |
303 | u64 global, shared; | |
304 | u64 active, inactive; | |
2db8e9d6 CW |
305 | }; |
306 | ||
307 | static int per_file_stats(int id, void *ptr, void *data) | |
308 | { | |
309 | struct drm_i915_gem_object *obj = ptr; | |
310 | struct file_stats *stats = data; | |
6313c204 | 311 | struct i915_vma *vma; |
2db8e9d6 | 312 | |
0caf81b5 CW |
313 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
314 | ||
2db8e9d6 CW |
315 | stats->count++; |
316 | stats->total += obj->base.size; | |
15717de2 CW |
317 | if (!obj->bind_count) |
318 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
319 | if (obj->base.name || obj->base.dma_buf) |
320 | stats->shared += obj->base.size; | |
321 | ||
894eeecc CW |
322 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
323 | if (!drm_mm_node_allocated(&vma->node)) | |
324 | continue; | |
6313c204 | 325 | |
3272db53 | 326 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
327 | stats->global += vma->node.size; |
328 | } else { | |
329 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 330 | |
2bfa996e | 331 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 332 | continue; |
6313c204 | 333 | } |
894eeecc | 334 | |
b0decaf7 | 335 | if (i915_vma_is_active(vma)) |
894eeecc CW |
336 | stats->active += vma->node.size; |
337 | else | |
338 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
339 | } |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
b0da1b79 CW |
344 | #define print_file_stats(m, name, stats) do { \ |
345 | if (stats.count) \ | |
c44ef60e | 346 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
347 | name, \ |
348 | stats.count, \ | |
349 | stats.total, \ | |
350 | stats.active, \ | |
351 | stats.inactive, \ | |
352 | stats.global, \ | |
353 | stats.shared, \ | |
354 | stats.unbound); \ | |
355 | } while (0) | |
493018dc BV |
356 | |
357 | static void print_batch_pool_stats(struct seq_file *m, | |
358 | struct drm_i915_private *dev_priv) | |
359 | { | |
360 | struct drm_i915_gem_object *obj; | |
361 | struct file_stats stats; | |
e2f80391 | 362 | struct intel_engine_cs *engine; |
3b3f1650 | 363 | enum intel_engine_id id; |
b4ac5afc | 364 | int j; |
493018dc BV |
365 | |
366 | memset(&stats, 0, sizeof(stats)); | |
367 | ||
3b3f1650 | 368 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 369 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 370 | list_for_each_entry(obj, |
e2f80391 | 371 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
372 | batch_pool_link) |
373 | per_file_stats(0, obj, &stats); | |
374 | } | |
06fbca71 | 375 | } |
493018dc | 376 | |
b0da1b79 | 377 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
378 | } |
379 | ||
15da9565 CW |
380 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
381 | { | |
382 | struct i915_gem_context *ctx = ptr; | |
383 | int n; | |
384 | ||
385 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
386 | if (ctx->engine[n].state) | |
bf3783e5 | 387 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 388 | if (ctx->engine[n].ring) |
57e88531 | 389 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
390 | } |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | static void print_context_stats(struct seq_file *m, | |
396 | struct drm_i915_private *dev_priv) | |
397 | { | |
36cdd013 | 398 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
399 | struct file_stats stats; |
400 | struct drm_file *file; | |
401 | ||
402 | memset(&stats, 0, sizeof(stats)); | |
403 | ||
36cdd013 | 404 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
405 | if (dev_priv->kernel_context) |
406 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
407 | ||
36cdd013 | 408 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
409 | struct drm_i915_file_private *fpriv = file->driver_priv; |
410 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
411 | } | |
36cdd013 | 412 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
413 | |
414 | print_file_stats(m, "[k]contexts", stats); | |
415 | } | |
416 | ||
36cdd013 | 417 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 418 | { |
36cdd013 DW |
419 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
420 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 421 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
7393b7ee MA |
422 | u32 count, mapped_count, purgeable_count, dpy_count, huge_count; |
423 | u64 size, mapped_size, purgeable_size, dpy_size, huge_size; | |
6299f992 | 424 | struct drm_i915_gem_object *obj; |
7393b7ee | 425 | unsigned int page_sizes = 0; |
2db8e9d6 | 426 | struct drm_file *file; |
7393b7ee | 427 | char buf[80]; |
73aa808f CW |
428 | int ret; |
429 | ||
430 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
431 | if (ret) | |
432 | return ret; | |
433 | ||
3ef7f228 | 434 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
435 | dev_priv->mm.object_count, |
436 | dev_priv->mm.object_memory); | |
437 | ||
1544c42e CW |
438 | size = count = 0; |
439 | mapped_size = mapped_count = 0; | |
440 | purgeable_size = purgeable_count = 0; | |
7393b7ee | 441 | huge_size = huge_count = 0; |
f2123818 CW |
442 | |
443 | spin_lock(&dev_priv->mm.obj_lock); | |
444 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) { | |
2bd160a1 CW |
445 | size += obj->base.size; |
446 | ++count; | |
447 | ||
a4f5ea64 | 448 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
449 | purgeable_size += obj->base.size; |
450 | ++purgeable_count; | |
451 | } | |
452 | ||
a4f5ea64 | 453 | if (obj->mm.mapping) { |
2bd160a1 CW |
454 | mapped_count++; |
455 | mapped_size += obj->base.size; | |
be19b10d | 456 | } |
7393b7ee MA |
457 | |
458 | if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { | |
459 | huge_count++; | |
460 | huge_size += obj->base.size; | |
461 | page_sizes |= obj->mm.page_sizes.sg; | |
462 | } | |
b7abb714 | 463 | } |
c44ef60e | 464 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 465 | |
2bd160a1 | 466 | size = count = dpy_size = dpy_count = 0; |
f2123818 | 467 | list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { |
2bd160a1 CW |
468 | size += obj->base.size; |
469 | ++count; | |
470 | ||
bd3d2252 | 471 | if (obj->pin_global) { |
2bd160a1 CW |
472 | dpy_size += obj->base.size; |
473 | ++dpy_count; | |
6299f992 | 474 | } |
2bd160a1 | 475 | |
a4f5ea64 | 476 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
477 | purgeable_size += obj->base.size; |
478 | ++purgeable_count; | |
479 | } | |
2bd160a1 | 480 | |
a4f5ea64 | 481 | if (obj->mm.mapping) { |
2bd160a1 CW |
482 | mapped_count++; |
483 | mapped_size += obj->base.size; | |
be19b10d | 484 | } |
7393b7ee MA |
485 | |
486 | if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { | |
487 | huge_count++; | |
488 | huge_size += obj->base.size; | |
489 | page_sizes |= obj->mm.page_sizes.sg; | |
490 | } | |
6299f992 | 491 | } |
f2123818 CW |
492 | spin_unlock(&dev_priv->mm.obj_lock); |
493 | ||
2bd160a1 CW |
494 | seq_printf(m, "%u bound objects, %llu bytes\n", |
495 | count, size); | |
c44ef60e | 496 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 497 | purgeable_count, purgeable_size); |
2bd160a1 CW |
498 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
499 | mapped_count, mapped_size); | |
7393b7ee MA |
500 | seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n", |
501 | huge_count, | |
502 | stringify_page_sizes(page_sizes, buf, sizeof(buf)), | |
503 | huge_size); | |
bd3d2252 | 504 | seq_printf(m, "%u display objects (globally pinned), %llu bytes\n", |
2bd160a1 | 505 | dpy_count, dpy_size); |
6299f992 | 506 | |
b7128ef1 MA |
507 | seq_printf(m, "%llu [%pa] gtt total\n", |
508 | ggtt->base.total, &ggtt->mappable_end); | |
7393b7ee MA |
509 | seq_printf(m, "Supported page sizes: %s\n", |
510 | stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes, | |
511 | buf, sizeof(buf))); | |
73aa808f | 512 | |
493018dc BV |
513 | seq_putc(m, '\n'); |
514 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
515 | mutex_unlock(&dev->struct_mutex); |
516 | ||
517 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 518 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
519 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
520 | struct file_stats stats; | |
c84455b4 CW |
521 | struct drm_i915_file_private *file_priv = file->driver_priv; |
522 | struct drm_i915_gem_request *request; | |
3ec2f427 | 523 | struct task_struct *task; |
2db8e9d6 | 524 | |
0caf81b5 CW |
525 | mutex_lock(&dev->struct_mutex); |
526 | ||
2db8e9d6 | 527 | memset(&stats, 0, sizeof(stats)); |
6313c204 | 528 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 529 | spin_lock(&file->table_lock); |
2db8e9d6 | 530 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 531 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
532 | /* |
533 | * Although we have a valid reference on file->pid, that does | |
534 | * not guarantee that the task_struct who called get_pid() is | |
535 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
536 | * Therefore, we need to protect this ->comm access using RCU. | |
537 | */ | |
c84455b4 CW |
538 | request = list_first_entry_or_null(&file_priv->mm.request_list, |
539 | struct drm_i915_gem_request, | |
c8659efa | 540 | client_link); |
3ec2f427 | 541 | rcu_read_lock(); |
c84455b4 CW |
542 | task = pid_task(request && request->ctx->pid ? |
543 | request->ctx->pid : file->pid, | |
544 | PIDTYPE_PID); | |
493018dc | 545 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 546 | rcu_read_unlock(); |
0caf81b5 | 547 | |
c84455b4 | 548 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 549 | } |
1d2ac403 | 550 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
551 | |
552 | return 0; | |
553 | } | |
554 | ||
aee56cff | 555 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 556 | { |
9f25d007 | 557 | struct drm_info_node *node = m->private; |
36cdd013 DW |
558 | struct drm_i915_private *dev_priv = node_to_i915(node); |
559 | struct drm_device *dev = &dev_priv->drm; | |
f2123818 | 560 | struct drm_i915_gem_object **objects; |
08c18323 | 561 | struct drm_i915_gem_object *obj; |
c44ef60e | 562 | u64 total_obj_size, total_gtt_size; |
f2123818 | 563 | unsigned long nobject, n; |
08c18323 CW |
564 | int count, ret; |
565 | ||
f2123818 CW |
566 | nobject = READ_ONCE(dev_priv->mm.object_count); |
567 | objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL); | |
568 | if (!objects) | |
569 | return -ENOMEM; | |
570 | ||
08c18323 CW |
571 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
572 | if (ret) | |
573 | return ret; | |
574 | ||
f2123818 CW |
575 | count = 0; |
576 | spin_lock(&dev_priv->mm.obj_lock); | |
577 | list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { | |
578 | objects[count++] = obj; | |
579 | if (count == nobject) | |
580 | break; | |
581 | } | |
582 | spin_unlock(&dev_priv->mm.obj_lock); | |
583 | ||
584 | total_obj_size = total_gtt_size = 0; | |
585 | for (n = 0; n < count; n++) { | |
586 | obj = objects[n]; | |
587 | ||
267f0c90 | 588 | seq_puts(m, " "); |
08c18323 | 589 | describe_obj(m, obj); |
267f0c90 | 590 | seq_putc(m, '\n'); |
08c18323 | 591 | total_obj_size += obj->base.size; |
ca1543be | 592 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
593 | } |
594 | ||
595 | mutex_unlock(&dev->struct_mutex); | |
596 | ||
c44ef60e | 597 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 | 598 | count, total_obj_size, total_gtt_size); |
f2123818 | 599 | kvfree(objects); |
08c18323 CW |
600 | |
601 | return 0; | |
602 | } | |
603 | ||
493018dc BV |
604 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
605 | { | |
36cdd013 DW |
606 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
607 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 608 | struct drm_i915_gem_object *obj; |
e2f80391 | 609 | struct intel_engine_cs *engine; |
3b3f1650 | 610 | enum intel_engine_id id; |
8d9d5744 | 611 | int total = 0; |
b4ac5afc | 612 | int ret, j; |
493018dc BV |
613 | |
614 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
615 | if (ret) | |
616 | return ret; | |
617 | ||
3b3f1650 | 618 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 619 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
620 | int count; |
621 | ||
622 | count = 0; | |
623 | list_for_each_entry(obj, | |
e2f80391 | 624 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
625 | batch_pool_link) |
626 | count++; | |
627 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 628 | engine->name, j, count); |
8d9d5744 CW |
629 | |
630 | list_for_each_entry(obj, | |
e2f80391 | 631 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
632 | batch_pool_link) { |
633 | seq_puts(m, " "); | |
634 | describe_obj(m, obj); | |
635 | seq_putc(m, '\n'); | |
636 | } | |
637 | ||
638 | total += count; | |
06fbca71 | 639 | } |
493018dc BV |
640 | } |
641 | ||
8d9d5744 | 642 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
643 | |
644 | mutex_unlock(&dev->struct_mutex); | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
2017263e BG |
649 | static int i915_interrupt_info(struct seq_file *m, void *data) |
650 | { | |
36cdd013 | 651 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 652 | struct intel_engine_cs *engine; |
3b3f1650 | 653 | enum intel_engine_id id; |
4bb05040 | 654 | int i, pipe; |
de227ef0 | 655 | |
c8c8fb33 | 656 | intel_runtime_pm_get(dev_priv); |
2017263e | 657 | |
36cdd013 | 658 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
659 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
660 | I915_READ(GEN8_MASTER_IRQ)); | |
661 | ||
662 | seq_printf(m, "Display IER:\t%08x\n", | |
663 | I915_READ(VLV_IER)); | |
664 | seq_printf(m, "Display IIR:\t%08x\n", | |
665 | I915_READ(VLV_IIR)); | |
666 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
667 | I915_READ(VLV_IIR_RW)); | |
668 | seq_printf(m, "Display IMR:\t%08x\n", | |
669 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
670 | for_each_pipe(dev_priv, pipe) { |
671 | enum intel_display_power_domain power_domain; | |
672 | ||
673 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
674 | if (!intel_display_power_get_if_enabled(dev_priv, | |
675 | power_domain)) { | |
676 | seq_printf(m, "Pipe %c power disabled\n", | |
677 | pipe_name(pipe)); | |
678 | continue; | |
679 | } | |
680 | ||
74e1ca8c VS |
681 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
682 | pipe_name(pipe), | |
683 | I915_READ(PIPESTAT(pipe))); | |
684 | ||
9c870d03 CW |
685 | intel_display_power_put(dev_priv, power_domain); |
686 | } | |
687 | ||
688 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
689 | seq_printf(m, "Port hotplug:\t%08x\n", |
690 | I915_READ(PORT_HOTPLUG_EN)); | |
691 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
692 | I915_READ(VLV_DPFLIPSTAT)); | |
693 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
694 | I915_READ(DPINVGTT)); | |
9c870d03 | 695 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
696 | |
697 | for (i = 0; i < 4; i++) { | |
698 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
699 | i, I915_READ(GEN8_GT_IMR(i))); | |
700 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
701 | i, I915_READ(GEN8_GT_IIR(i))); | |
702 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
703 | i, I915_READ(GEN8_GT_IER(i))); | |
704 | } | |
705 | ||
706 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
707 | I915_READ(GEN8_PCU_IMR)); | |
708 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
709 | I915_READ(GEN8_PCU_IIR)); | |
710 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
711 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 712 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
713 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
714 | I915_READ(GEN8_MASTER_IRQ)); | |
715 | ||
716 | for (i = 0; i < 4; i++) { | |
717 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
718 | i, I915_READ(GEN8_GT_IMR(i))); | |
719 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
720 | i, I915_READ(GEN8_GT_IIR(i))); | |
721 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
722 | i, I915_READ(GEN8_GT_IER(i))); | |
723 | } | |
724 | ||
055e393f | 725 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
726 | enum intel_display_power_domain power_domain; |
727 | ||
728 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
729 | if (!intel_display_power_get_if_enabled(dev_priv, | |
730 | power_domain)) { | |
22c59960 PZ |
731 | seq_printf(m, "Pipe %c power disabled\n", |
732 | pipe_name(pipe)); | |
733 | continue; | |
734 | } | |
a123f157 | 735 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
736 | pipe_name(pipe), |
737 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 738 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
739 | pipe_name(pipe), |
740 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 741 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
742 | pipe_name(pipe), |
743 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
744 | |
745 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
746 | } |
747 | ||
748 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
749 | I915_READ(GEN8_DE_PORT_IMR)); | |
750 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
751 | I915_READ(GEN8_DE_PORT_IIR)); | |
752 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
753 | I915_READ(GEN8_DE_PORT_IER)); | |
754 | ||
755 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
756 | I915_READ(GEN8_DE_MISC_IMR)); | |
757 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
758 | I915_READ(GEN8_DE_MISC_IIR)); | |
759 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
760 | I915_READ(GEN8_DE_MISC_IER)); | |
761 | ||
762 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
763 | I915_READ(GEN8_PCU_IMR)); | |
764 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
765 | I915_READ(GEN8_PCU_IIR)); | |
766 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
767 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 768 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
769 | seq_printf(m, "Display IER:\t%08x\n", |
770 | I915_READ(VLV_IER)); | |
771 | seq_printf(m, "Display IIR:\t%08x\n", | |
772 | I915_READ(VLV_IIR)); | |
773 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
774 | I915_READ(VLV_IIR_RW)); | |
775 | seq_printf(m, "Display IMR:\t%08x\n", | |
776 | I915_READ(VLV_IMR)); | |
4f4631af CW |
777 | for_each_pipe(dev_priv, pipe) { |
778 | enum intel_display_power_domain power_domain; | |
779 | ||
780 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
781 | if (!intel_display_power_get_if_enabled(dev_priv, | |
782 | power_domain)) { | |
783 | seq_printf(m, "Pipe %c power disabled\n", | |
784 | pipe_name(pipe)); | |
785 | continue; | |
786 | } | |
787 | ||
7e231dbe JB |
788 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
789 | pipe_name(pipe), | |
790 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
791 | intel_display_power_put(dev_priv, power_domain); |
792 | } | |
7e231dbe JB |
793 | |
794 | seq_printf(m, "Master IER:\t%08x\n", | |
795 | I915_READ(VLV_MASTER_IER)); | |
796 | ||
797 | seq_printf(m, "Render IER:\t%08x\n", | |
798 | I915_READ(GTIER)); | |
799 | seq_printf(m, "Render IIR:\t%08x\n", | |
800 | I915_READ(GTIIR)); | |
801 | seq_printf(m, "Render IMR:\t%08x\n", | |
802 | I915_READ(GTIMR)); | |
803 | ||
804 | seq_printf(m, "PM IER:\t\t%08x\n", | |
805 | I915_READ(GEN6_PMIER)); | |
806 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
807 | I915_READ(GEN6_PMIIR)); | |
808 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
809 | I915_READ(GEN6_PMIMR)); | |
810 | ||
811 | seq_printf(m, "Port hotplug:\t%08x\n", | |
812 | I915_READ(PORT_HOTPLUG_EN)); | |
813 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
814 | I915_READ(VLV_DPFLIPSTAT)); | |
815 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
816 | I915_READ(DPINVGTT)); | |
817 | ||
36cdd013 | 818 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
819 | seq_printf(m, "Interrupt enable: %08x\n", |
820 | I915_READ(IER)); | |
821 | seq_printf(m, "Interrupt identity: %08x\n", | |
822 | I915_READ(IIR)); | |
823 | seq_printf(m, "Interrupt mask: %08x\n", | |
824 | I915_READ(IMR)); | |
055e393f | 825 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
826 | seq_printf(m, "Pipe %c stat: %08x\n", |
827 | pipe_name(pipe), | |
828 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
829 | } else { |
830 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
831 | I915_READ(DEIER)); | |
832 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
833 | I915_READ(DEIIR)); | |
834 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
835 | I915_READ(DEIMR)); | |
836 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
837 | I915_READ(SDEIER)); | |
838 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
839 | I915_READ(SDEIIR)); | |
840 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
841 | I915_READ(SDEIMR)); | |
842 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
843 | I915_READ(GTIER)); | |
844 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
845 | I915_READ(GTIIR)); | |
846 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
847 | I915_READ(GTIMR)); | |
848 | } | |
d5acadfe CW |
849 | if (INTEL_GEN(dev_priv) >= 6) { |
850 | for_each_engine(engine, dev_priv, id) { | |
a2c7f6fd CW |
851 | seq_printf(m, |
852 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 853 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 854 | } |
9862e600 | 855 | } |
c8c8fb33 | 856 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 857 | |
2017263e BG |
858 | return 0; |
859 | } | |
860 | ||
a6172a80 CW |
861 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
862 | { | |
36cdd013 DW |
863 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
864 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
865 | int i, ret; |
866 | ||
867 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
868 | if (ret) | |
869 | return ret; | |
a6172a80 | 870 | |
a6172a80 CW |
871 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
872 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 873 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 874 | |
6c085a72 CW |
875 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
876 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 877 | if (!vma) |
267f0c90 | 878 | seq_puts(m, "unused"); |
c2c347a9 | 879 | else |
49ef5294 | 880 | describe_obj(m, vma->obj); |
267f0c90 | 881 | seq_putc(m, '\n'); |
a6172a80 CW |
882 | } |
883 | ||
05394f39 | 884 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
885 | return 0; |
886 | } | |
887 | ||
98a2f411 | 888 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
889 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
890 | size_t count, loff_t *pos) | |
d5442303 | 891 | { |
5a4c6f1b CW |
892 | struct i915_gpu_state *error = file->private_data; |
893 | struct drm_i915_error_state_buf str; | |
894 | ssize_t ret; | |
895 | loff_t tmp; | |
d5442303 | 896 | |
5a4c6f1b CW |
897 | if (!error) |
898 | return 0; | |
d5442303 | 899 | |
5a4c6f1b CW |
900 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
901 | if (ret) | |
902 | return ret; | |
d5442303 | 903 | |
5a4c6f1b CW |
904 | ret = i915_error_state_to_str(&str, error); |
905 | if (ret) | |
906 | goto out; | |
d5442303 | 907 | |
5a4c6f1b CW |
908 | tmp = 0; |
909 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
910 | if (ret < 0) | |
911 | goto out; | |
d5442303 | 912 | |
5a4c6f1b CW |
913 | *pos = str.start + ret; |
914 | out: | |
915 | i915_error_state_buf_release(&str); | |
916 | return ret; | |
917 | } | |
edc3d884 | 918 | |
5a4c6f1b CW |
919 | static int gpu_state_release(struct inode *inode, struct file *file) |
920 | { | |
921 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 922 | return 0; |
d5442303 DV |
923 | } |
924 | ||
5a4c6f1b | 925 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 926 | { |
090e5fe3 | 927 | struct drm_i915_private *i915 = inode->i_private; |
5a4c6f1b | 928 | struct i915_gpu_state *gpu; |
d5442303 | 929 | |
090e5fe3 CW |
930 | intel_runtime_pm_get(i915); |
931 | gpu = i915_capture_gpu_state(i915); | |
932 | intel_runtime_pm_put(i915); | |
5a4c6f1b CW |
933 | if (!gpu) |
934 | return -ENOMEM; | |
d5442303 | 935 | |
5a4c6f1b | 936 | file->private_data = gpu; |
edc3d884 MK |
937 | return 0; |
938 | } | |
939 | ||
5a4c6f1b CW |
940 | static const struct file_operations i915_gpu_info_fops = { |
941 | .owner = THIS_MODULE, | |
942 | .open = i915_gpu_info_open, | |
943 | .read = gpu_state_read, | |
944 | .llseek = default_llseek, | |
945 | .release = gpu_state_release, | |
946 | }; | |
947 | ||
948 | static ssize_t | |
949 | i915_error_state_write(struct file *filp, | |
950 | const char __user *ubuf, | |
951 | size_t cnt, | |
952 | loff_t *ppos) | |
4dc955f7 | 953 | { |
5a4c6f1b | 954 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 955 | |
5a4c6f1b CW |
956 | if (!error) |
957 | return 0; | |
edc3d884 | 958 | |
5a4c6f1b CW |
959 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
960 | i915_reset_error_state(error->i915); | |
edc3d884 | 961 | |
5a4c6f1b CW |
962 | return cnt; |
963 | } | |
edc3d884 | 964 | |
5a4c6f1b CW |
965 | static int i915_error_state_open(struct inode *inode, struct file *file) |
966 | { | |
967 | file->private_data = i915_first_error_state(inode->i_private); | |
968 | return 0; | |
d5442303 DV |
969 | } |
970 | ||
971 | static const struct file_operations i915_error_state_fops = { | |
972 | .owner = THIS_MODULE, | |
973 | .open = i915_error_state_open, | |
5a4c6f1b | 974 | .read = gpu_state_read, |
d5442303 DV |
975 | .write = i915_error_state_write, |
976 | .llseek = default_llseek, | |
5a4c6f1b | 977 | .release = gpu_state_release, |
d5442303 | 978 | }; |
98a2f411 CW |
979 | #endif |
980 | ||
647416f9 KC |
981 | static int |
982 | i915_next_seqno_set(void *data, u64 val) | |
983 | { | |
36cdd013 DW |
984 | struct drm_i915_private *dev_priv = data; |
985 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
986 | int ret; |
987 | ||
40633219 MK |
988 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
989 | if (ret) | |
990 | return ret; | |
991 | ||
65c475c6 | 992 | intel_runtime_pm_get(dev_priv); |
73cb9701 | 993 | ret = i915_gem_set_global_seqno(dev, val); |
65c475c6 CW |
994 | intel_runtime_pm_put(dev_priv); |
995 | ||
40633219 MK |
996 | mutex_unlock(&dev->struct_mutex); |
997 | ||
647416f9 | 998 | return ret; |
40633219 MK |
999 | } |
1000 | ||
647416f9 | 1001 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
9b6586ae | 1002 | NULL, i915_next_seqno_set, |
3a3b4f98 | 1003 | "0x%llx\n"); |
40633219 | 1004 | |
adb4bd12 | 1005 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1006 | { |
36cdd013 | 1007 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
562d9bae | 1008 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
c8c8fb33 PZ |
1009 | int ret = 0; |
1010 | ||
1011 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1012 | |
36cdd013 | 1013 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1014 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1015 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1016 | ||
1017 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1018 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1019 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1020 | MEMSTAT_VID_SHIFT); | |
1021 | seq_printf(m, "Current P-state: %d\n", | |
1022 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1023 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
0d6fc92a | 1024 | u32 rpmodectl, freq_sts; |
666a4537 | 1025 | |
9f817501 | 1026 | mutex_lock(&dev_priv->pcu_lock); |
0d6fc92a SAK |
1027 | |
1028 | rpmodectl = I915_READ(GEN6_RP_CONTROL); | |
1029 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1030 | yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); | |
1031 | seq_printf(m, "HW control enabled: %s\n", | |
1032 | yesno(rpmodectl & GEN6_RP_ENABLE)); | |
1033 | seq_printf(m, "SW control enabled: %s\n", | |
1034 | yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == | |
1035 | GEN6_RP_MEDIA_SW_MODE)); | |
1036 | ||
666a4537 WB |
1037 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
1038 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1039 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1040 | ||
1041 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1042 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1043 | ||
1044 | seq_printf(m, "current GPU freq: %d MHz\n", | |
562d9bae | 1045 | intel_gpu_freq(dev_priv, rps->cur_freq)); |
666a4537 WB |
1046 | |
1047 | seq_printf(m, "max GPU freq: %d MHz\n", | |
562d9bae | 1048 | intel_gpu_freq(dev_priv, rps->max_freq)); |
666a4537 WB |
1049 | |
1050 | seq_printf(m, "min GPU freq: %d MHz\n", | |
562d9bae | 1051 | intel_gpu_freq(dev_priv, rps->min_freq)); |
666a4537 WB |
1052 | |
1053 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
562d9bae | 1054 | intel_gpu_freq(dev_priv, rps->idle_freq)); |
666a4537 WB |
1055 | |
1056 | seq_printf(m, | |
1057 | "efficient (RPe) frequency: %d MHz\n", | |
562d9bae | 1058 | intel_gpu_freq(dev_priv, rps->efficient_freq)); |
9f817501 | 1059 | mutex_unlock(&dev_priv->pcu_lock); |
36cdd013 | 1060 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1061 | u32 rp_state_limits; |
1062 | u32 gt_perf_status; | |
1063 | u32 rp_state_cap; | |
0d8f9491 | 1064 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1065 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1066 | u32 rpupei, rpcurup, rpprevup; |
1067 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1068 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1069 | int max_freq; |
1070 | ||
35040562 | 1071 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1072 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1073 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1074 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1075 | } else { | |
1076 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1077 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1078 | } | |
1079 | ||
3b8d8d91 | 1080 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1081 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1082 | |
8e8c06cd | 1083 | reqf = I915_READ(GEN6_RPNSWREQ); |
35ceabf3 | 1084 | if (INTEL_GEN(dev_priv) >= 9) |
60260a5b AG |
1085 | reqf >>= 23; |
1086 | else { | |
1087 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1088 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1089 | reqf >>= 24; |
1090 | else | |
1091 | reqf >>= 25; | |
1092 | } | |
7c59a9c1 | 1093 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1094 | |
0d8f9491 CW |
1095 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1096 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1097 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1098 | ||
ccab5c82 | 1099 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1100 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1101 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1102 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1103 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1104 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1105 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
c84b2705 TU |
1106 | cagf = intel_gpu_freq(dev_priv, |
1107 | intel_get_cagf(dev_priv, rpstat)); | |
ccab5c82 | 1108 | |
59bad947 | 1109 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1110 | |
36cdd013 | 1111 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1112 | pm_ier = I915_READ(GEN6_PMIER); |
1113 | pm_imr = I915_READ(GEN6_PMIMR); | |
1114 | pm_isr = I915_READ(GEN6_PMISR); | |
1115 | pm_iir = I915_READ(GEN6_PMIIR); | |
1116 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1117 | } else { | |
1118 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1119 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1120 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1121 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1122 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1123 | } | |
960e5465 SAK |
1124 | seq_printf(m, "Video Turbo Mode: %s\n", |
1125 | yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); | |
1126 | seq_printf(m, "HW control enabled: %s\n", | |
1127 | yesno(rpmodectl & GEN6_RP_ENABLE)); | |
1128 | seq_printf(m, "SW control enabled: %s\n", | |
1129 | yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == | |
1130 | GEN6_RP_MEDIA_SW_MODE)); | |
0d8f9491 | 1131 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1132 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
5dd04556 | 1133 | seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", |
562d9bae | 1134 | rps->pm_intrmsk_mbz); |
3b8d8d91 | 1135 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1136 | seq_printf(m, "Render p-state ratio: %d\n", |
35ceabf3 | 1137 | (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1138 | seq_printf(m, "Render p-state VID: %d\n", |
1139 | gt_perf_status & 0xff); | |
1140 | seq_printf(m, "Render p-state limit: %d\n", | |
1141 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1142 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1143 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1144 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1145 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1146 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1147 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1148 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1149 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1150 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1151 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1152 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1153 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
562d9bae | 1154 | seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold); |
d86ed34a | 1155 | |
d6cda9c7 AG |
1156 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1157 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1158 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1159 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1160 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1161 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
562d9bae | 1162 | seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold); |
3b8d8d91 | 1163 | |
cc3f90f0 | 1164 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1165 | rp_state_cap >> 16) & 0xff; |
35ceabf3 RV |
1166 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1167 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1168 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1169 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1170 | |
1171 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
35ceabf3 RV |
1172 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1173 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1174 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1175 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1176 | |
cc3f90f0 | 1177 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1178 | rp_state_cap >> 0) & 0xff; |
35ceabf3 RV |
1179 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1180 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1181 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1182 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1183 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
562d9bae | 1184 | intel_gpu_freq(dev_priv, rps->max_freq)); |
aed242ff | 1185 | |
d86ed34a | 1186 | seq_printf(m, "Current freq: %d MHz\n", |
562d9bae | 1187 | intel_gpu_freq(dev_priv, rps->cur_freq)); |
d86ed34a | 1188 | seq_printf(m, "Actual freq: %d MHz\n", cagf); |
aed242ff | 1189 | seq_printf(m, "Idle freq: %d MHz\n", |
562d9bae | 1190 | intel_gpu_freq(dev_priv, rps->idle_freq)); |
d86ed34a | 1191 | seq_printf(m, "Min freq: %d MHz\n", |
562d9bae | 1192 | intel_gpu_freq(dev_priv, rps->min_freq)); |
29ecd78d | 1193 | seq_printf(m, "Boost freq: %d MHz\n", |
562d9bae | 1194 | intel_gpu_freq(dev_priv, rps->boost_freq)); |
d86ed34a | 1195 | seq_printf(m, "Max freq: %d MHz\n", |
562d9bae | 1196 | intel_gpu_freq(dev_priv, rps->max_freq)); |
d86ed34a CW |
1197 | seq_printf(m, |
1198 | "efficient (RPe) frequency: %d MHz\n", | |
562d9bae | 1199 | intel_gpu_freq(dev_priv, rps->efficient_freq)); |
3b8d8d91 | 1200 | } else { |
267f0c90 | 1201 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1202 | } |
f97108d1 | 1203 | |
49cd97a3 | 1204 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1205 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1206 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1207 | ||
c8c8fb33 PZ |
1208 | intel_runtime_pm_put(dev_priv); |
1209 | return ret; | |
f97108d1 JB |
1210 | } |
1211 | ||
d636951e BW |
1212 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1213 | struct seq_file *m, | |
1214 | struct intel_instdone *instdone) | |
1215 | { | |
f9e61372 BW |
1216 | int slice; |
1217 | int subslice; | |
1218 | ||
d636951e BW |
1219 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1220 | instdone->instdone); | |
1221 | ||
1222 | if (INTEL_GEN(dev_priv) <= 3) | |
1223 | return; | |
1224 | ||
1225 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1226 | instdone->slice_common); | |
1227 | ||
1228 | if (INTEL_GEN(dev_priv) <= 6) | |
1229 | return; | |
1230 | ||
f9e61372 BW |
1231 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1232 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1233 | slice, subslice, instdone->sampler[slice][subslice]); | |
1234 | ||
1235 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1236 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1237 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1238 | } |
1239 | ||
f654449a CW |
1240 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1241 | { | |
36cdd013 | 1242 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1243 | struct intel_engine_cs *engine; |
666796da TU |
1244 | u64 acthd[I915_NUM_ENGINES]; |
1245 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1246 | struct intel_instdone instdone; |
c3232b18 | 1247 | enum intel_engine_id id; |
f654449a | 1248 | |
8af29b0c | 1249 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8c185eca CW |
1250 | seq_puts(m, "Wedged\n"); |
1251 | if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) | |
1252 | seq_puts(m, "Reset in progress: struct_mutex backoff\n"); | |
1253 | if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags)) | |
1254 | seq_puts(m, "Reset in progress: reset handoff to waiter\n"); | |
8af29b0c | 1255 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) |
8c185eca | 1256 | seq_puts(m, "Waiter holding struct mutex\n"); |
8af29b0c | 1257 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) |
8c185eca | 1258 | seq_puts(m, "struct_mutex blocked for reset\n"); |
8af29b0c | 1259 | |
4f044a88 | 1260 | if (!i915_modparams.enable_hangcheck) { |
8c185eca | 1261 | seq_puts(m, "Hangcheck disabled\n"); |
f654449a CW |
1262 | return 0; |
1263 | } | |
1264 | ||
ebbc7546 MK |
1265 | intel_runtime_pm_get(dev_priv); |
1266 | ||
3b3f1650 | 1267 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1268 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1269 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1270 | } |
1271 | ||
3b3f1650 | 1272 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1273 | |
ebbc7546 MK |
1274 | intel_runtime_pm_put(dev_priv); |
1275 | ||
8352aea3 CW |
1276 | if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer)) |
1277 | seq_printf(m, "Hangcheck active, timer fires in %dms\n", | |
f654449a CW |
1278 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - |
1279 | jiffies)); | |
8352aea3 CW |
1280 | else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) |
1281 | seq_puts(m, "Hangcheck active, work pending\n"); | |
1282 | else | |
1283 | seq_puts(m, "Hangcheck inactive\n"); | |
f654449a | 1284 | |
f73b5674 CW |
1285 | seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); |
1286 | ||
3b3f1650 | 1287 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1288 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1289 | struct rb_node *rb; | |
1290 | ||
e2f80391 | 1291 | seq_printf(m, "%s:\n", engine->name); |
f73b5674 | 1292 | seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n", |
cb399eab | 1293 | engine->hangcheck.seqno, seqno[id], |
f73b5674 CW |
1294 | intel_engine_last_submit(engine), |
1295 | engine->timeline->inflight_seqnos); | |
3fe3b030 | 1296 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1297 | yesno(intel_engine_has_waiter(engine)), |
1298 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1299 | &dev_priv->gpu_error.missed_irq_rings)), |
1300 | yesno(engine->hangcheck.stalled)); | |
1301 | ||
61d3dc70 | 1302 | spin_lock_irq(&b->rb_lock); |
33f53719 | 1303 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1304 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1305 | |
1306 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1307 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1308 | } | |
61d3dc70 | 1309 | spin_unlock_irq(&b->rb_lock); |
33f53719 | 1310 | |
f654449a | 1311 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1312 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1313 | (long long)acthd[id]); |
3fe3b030 MK |
1314 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1315 | hangcheck_action_to_str(engine->hangcheck.action), | |
1316 | engine->hangcheck.action, | |
1317 | jiffies_to_msecs(jiffies - | |
1318 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1319 | |
e2f80391 | 1320 | if (engine->id == RCS) { |
d636951e | 1321 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1322 | |
d636951e | 1323 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1324 | |
d636951e | 1325 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1326 | |
d636951e BW |
1327 | i915_instdone_info(dev_priv, m, |
1328 | &engine->hangcheck.instdone); | |
61642ff0 | 1329 | } |
f654449a CW |
1330 | } |
1331 | ||
1332 | return 0; | |
1333 | } | |
1334 | ||
061d06a2 MT |
1335 | static int i915_reset_info(struct seq_file *m, void *unused) |
1336 | { | |
1337 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1338 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
1339 | struct intel_engine_cs *engine; | |
1340 | enum intel_engine_id id; | |
1341 | ||
1342 | seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error)); | |
1343 | ||
1344 | for_each_engine(engine, dev_priv, id) { | |
1345 | seq_printf(m, "%s = %u\n", engine->name, | |
1346 | i915_reset_engine_count(error, engine)); | |
1347 | } | |
1348 | ||
1349 | return 0; | |
1350 | } | |
1351 | ||
4d85529d | 1352 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1353 | { |
36cdd013 | 1354 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1355 | u32 rgvmodectl, rstdbyctl; |
1356 | u16 crstandvid; | |
616fdb5a | 1357 | |
616fdb5a BW |
1358 | rgvmodectl = I915_READ(MEMMODECTL); |
1359 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1360 | crstandvid = I915_READ16(CRSTANDVID); | |
1361 | ||
742f491d | 1362 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1363 | seq_printf(m, "Boost freq: %d\n", |
1364 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1365 | MEMMODE_BOOST_FREQ_SHIFT); | |
1366 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1367 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1368 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1369 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1370 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1371 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1372 | seq_printf(m, "Starting frequency: P%d\n", |
1373 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1374 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1375 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1376 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1377 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1378 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1379 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1380 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1381 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1382 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1383 | case RSX_STATUS_ON: | |
267f0c90 | 1384 | seq_puts(m, "on\n"); |
88271da3 JB |
1385 | break; |
1386 | case RSX_STATUS_RC1: | |
267f0c90 | 1387 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1388 | break; |
1389 | case RSX_STATUS_RC1E: | |
267f0c90 | 1390 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1391 | break; |
1392 | case RSX_STATUS_RS1: | |
267f0c90 | 1393 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1394 | break; |
1395 | case RSX_STATUS_RS2: | |
267f0c90 | 1396 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1397 | break; |
1398 | case RSX_STATUS_RS3: | |
267f0c90 | 1399 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1400 | break; |
1401 | default: | |
267f0c90 | 1402 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1403 | break; |
1404 | } | |
f97108d1 JB |
1405 | |
1406 | return 0; | |
1407 | } | |
1408 | ||
f65367b5 | 1409 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1410 | { |
233ebf57 | 1411 | struct drm_i915_private *i915 = node_to_i915(m->private); |
b2cff0db | 1412 | struct intel_uncore_forcewake_domain *fw_domain; |
d2dc94bc | 1413 | unsigned int tmp; |
b2cff0db | 1414 | |
d7a133d8 CW |
1415 | seq_printf(m, "user.bypass_count = %u\n", |
1416 | i915->uncore.user_forcewake.count); | |
1417 | ||
233ebf57 | 1418 | for_each_fw_domain(fw_domain, i915, tmp) |
b2cff0db | 1419 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1420 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
233ebf57 | 1421 | READ_ONCE(fw_domain->wake_count)); |
669ab5aa | 1422 | |
b2cff0db CW |
1423 | return 0; |
1424 | } | |
1425 | ||
1362877e MK |
1426 | static void print_rc6_res(struct seq_file *m, |
1427 | const char *title, | |
1428 | const i915_reg_t reg) | |
1429 | { | |
1430 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1431 | ||
1432 | seq_printf(m, "%s %u (%llu us)\n", | |
1433 | title, I915_READ(reg), | |
1434 | intel_rc6_residency_us(dev_priv, reg)); | |
1435 | } | |
1436 | ||
b2cff0db CW |
1437 | static int vlv_drpc_info(struct seq_file *m) |
1438 | { | |
36cdd013 | 1439 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
0d6fc92a | 1440 | u32 rcctl1, pw_status; |
669ab5aa | 1441 | |
6b312cd3 | 1442 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1443 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
1444 | ||
669ab5aa D |
1445 | seq_printf(m, "RC6 Enabled: %s\n", |
1446 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1447 | GEN6_RC_CTL_EI_MODE(1)))); | |
1448 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1449 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1450 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1451 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1452 | |
1362877e MK |
1453 | print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); |
1454 | print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); | |
9cc19be5 | 1455 | |
f65367b5 | 1456 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1457 | } |
1458 | ||
4d85529d BW |
1459 | static int gen6_drpc_info(struct seq_file *m) |
1460 | { | |
36cdd013 | 1461 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
960e5465 | 1462 | u32 gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1463 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
4d85529d | 1464 | |
75aa3f63 | 1465 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1466 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d | 1467 | |
4d85529d | 1468 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
36cdd013 | 1469 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1470 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1471 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1472 | } | |
cf632bd6 | 1473 | |
51cc9ade ID |
1474 | if (INTEL_GEN(dev_priv) <= 7) { |
1475 | mutex_lock(&dev_priv->pcu_lock); | |
1476 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, | |
1477 | &rc6vids); | |
1478 | mutex_unlock(&dev_priv->pcu_lock); | |
1479 | } | |
4d85529d | 1480 | |
fff24e21 | 1481 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1482 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1483 | seq_printf(m, "RC6 Enabled: %s\n", | |
1484 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1485 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1486 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1487 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1488 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1489 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1490 | } | |
4d85529d BW |
1491 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1492 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1493 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1494 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1495 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1496 | switch (gt_core_status & GEN6_RCn_MASK) { |
1497 | case GEN6_RC0: | |
1498 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1499 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1500 | else |
267f0c90 | 1501 | seq_puts(m, "on\n"); |
4d85529d BW |
1502 | break; |
1503 | case GEN6_RC3: | |
267f0c90 | 1504 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1505 | break; |
1506 | case GEN6_RC6: | |
267f0c90 | 1507 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1508 | break; |
1509 | case GEN6_RC7: | |
267f0c90 | 1510 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1511 | break; |
1512 | default: | |
267f0c90 | 1513 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1514 | break; |
1515 | } | |
1516 | ||
1517 | seq_printf(m, "Core Power Down: %s\n", | |
1518 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1519 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1520 | seq_printf(m, "Render Power Well: %s\n", |
1521 | (gen9_powergate_status & | |
1522 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1523 | seq_printf(m, "Media Power Well: %s\n", | |
1524 | (gen9_powergate_status & | |
1525 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1526 | } | |
cce66a28 BW |
1527 | |
1528 | /* Not exactly sure what this is */ | |
1362877e MK |
1529 | print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", |
1530 | GEN6_GT_GFX_RC6_LOCKED); | |
1531 | print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); | |
1532 | print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); | |
1533 | print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); | |
cce66a28 | 1534 | |
51cc9ade ID |
1535 | if (INTEL_GEN(dev_priv) <= 7) { |
1536 | seq_printf(m, "RC6 voltage: %dmV\n", | |
1537 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1538 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1539 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1540 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1541 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
1542 | } | |
1543 | ||
f2dd7578 | 1544 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1545 | } |
1546 | ||
1547 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1548 | { | |
36cdd013 | 1549 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
cf632bd6 CW |
1550 | int err; |
1551 | ||
1552 | intel_runtime_pm_get(dev_priv); | |
4d85529d | 1553 | |
36cdd013 | 1554 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
cf632bd6 | 1555 | err = vlv_drpc_info(m); |
36cdd013 | 1556 | else if (INTEL_GEN(dev_priv) >= 6) |
cf632bd6 | 1557 | err = gen6_drpc_info(m); |
4d85529d | 1558 | else |
cf632bd6 CW |
1559 | err = ironlake_drpc_info(m); |
1560 | ||
1561 | intel_runtime_pm_put(dev_priv); | |
1562 | ||
1563 | return err; | |
4d85529d BW |
1564 | } |
1565 | ||
9a851789 DV |
1566 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1567 | { | |
36cdd013 | 1568 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1569 | |
1570 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1571 | dev_priv->fb_tracking.busy_bits); | |
1572 | ||
1573 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1574 | dev_priv->fb_tracking.flip_bits); | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
b5e50c3f JB |
1579 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1580 | { | |
36cdd013 | 1581 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3138872c | 1582 | struct intel_fbc *fbc = &dev_priv->fbc; |
b5e50c3f | 1583 | |
ab309a6a MW |
1584 | if (!HAS_FBC(dev_priv)) |
1585 | return -ENODEV; | |
b5e50c3f | 1586 | |
36623ef8 | 1587 | intel_runtime_pm_get(dev_priv); |
3138872c | 1588 | mutex_lock(&fbc->lock); |
36623ef8 | 1589 | |
0e631adc | 1590 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1591 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 | 1592 | else |
3138872c CW |
1593 | seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); |
1594 | ||
1595 | if (fbc->work.scheduled) | |
1b29b7ca | 1596 | seq_printf(m, "FBC worker scheduled on vblank %llu, now %llu\n", |
3138872c CW |
1597 | fbc->work.scheduled_vblank, |
1598 | drm_crtc_vblank_count(&fbc->crtc->base)); | |
36623ef8 | 1599 | |
3fd5d1ec VS |
1600 | if (intel_fbc_is_active(dev_priv)) { |
1601 | u32 mask; | |
1602 | ||
1603 | if (INTEL_GEN(dev_priv) >= 8) | |
1604 | mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; | |
1605 | else if (INTEL_GEN(dev_priv) >= 7) | |
1606 | mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; | |
1607 | else if (INTEL_GEN(dev_priv) >= 5) | |
1608 | mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; | |
1609 | else if (IS_G4X(dev_priv)) | |
1610 | mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK; | |
1611 | else | |
1612 | mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING | | |
1613 | FBC_STAT_COMPRESSED); | |
1614 | ||
1615 | seq_printf(m, "Compressing: %s\n", yesno(mask)); | |
0fc6a9dc | 1616 | } |
31b9df10 | 1617 | |
3138872c | 1618 | mutex_unlock(&fbc->lock); |
36623ef8 PZ |
1619 | intel_runtime_pm_put(dev_priv); |
1620 | ||
b5e50c3f JB |
1621 | return 0; |
1622 | } | |
1623 | ||
4127dc43 | 1624 | static int i915_fbc_false_color_get(void *data, u64 *val) |
da46f936 | 1625 | { |
36cdd013 | 1626 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1627 | |
36cdd013 | 1628 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1629 | return -ENODEV; |
1630 | ||
da46f936 | 1631 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1632 | |
1633 | return 0; | |
1634 | } | |
1635 | ||
4127dc43 | 1636 | static int i915_fbc_false_color_set(void *data, u64 val) |
da46f936 | 1637 | { |
36cdd013 | 1638 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1639 | u32 reg; |
1640 | ||
36cdd013 | 1641 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1642 | return -ENODEV; |
1643 | ||
25ad93fd | 1644 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1645 | |
1646 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1647 | dev_priv->fbc.false_color = val; | |
1648 | ||
1649 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1650 | (reg | FBC_CTL_FALSE_COLOR) : | |
1651 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1652 | ||
25ad93fd | 1653 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1654 | return 0; |
1655 | } | |
1656 | ||
4127dc43 VS |
1657 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops, |
1658 | i915_fbc_false_color_get, i915_fbc_false_color_set, | |
da46f936 RV |
1659 | "%llu\n"); |
1660 | ||
92d44621 PZ |
1661 | static int i915_ips_status(struct seq_file *m, void *unused) |
1662 | { | |
36cdd013 | 1663 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1664 | |
ab309a6a MW |
1665 | if (!HAS_IPS(dev_priv)) |
1666 | return -ENODEV; | |
92d44621 | 1667 | |
36623ef8 PZ |
1668 | intel_runtime_pm_get(dev_priv); |
1669 | ||
0eaa53f0 | 1670 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
4f044a88 | 1671 | yesno(i915_modparams.enable_ips)); |
0eaa53f0 | 1672 | |
36cdd013 | 1673 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1674 | seq_puts(m, "Currently: unknown\n"); |
1675 | } else { | |
1676 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1677 | seq_puts(m, "Currently: enabled\n"); | |
1678 | else | |
1679 | seq_puts(m, "Currently: disabled\n"); | |
1680 | } | |
92d44621 | 1681 | |
36623ef8 PZ |
1682 | intel_runtime_pm_put(dev_priv); |
1683 | ||
92d44621 PZ |
1684 | return 0; |
1685 | } | |
1686 | ||
4a9bef37 JB |
1687 | static int i915_sr_status(struct seq_file *m, void *unused) |
1688 | { | |
36cdd013 | 1689 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1690 | bool sr_enabled = false; |
1691 | ||
36623ef8 | 1692 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1693 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1694 | |
7342a72c CW |
1695 | if (INTEL_GEN(dev_priv) >= 9) |
1696 | /* no global SR status; inspect per-plane WM */; | |
1697 | else if (HAS_PCH_SPLIT(dev_priv)) | |
5ba2aaaa | 1698 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1699 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1700 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1701 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1702 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1703 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1704 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1705 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1706 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1707 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1708 | |
9c870d03 | 1709 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1710 | intel_runtime_pm_put(dev_priv); |
1711 | ||
08c4d7fc | 1712 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1713 | |
1714 | return 0; | |
1715 | } | |
1716 | ||
7648fa99 JB |
1717 | static int i915_emon_status(struct seq_file *m, void *unused) |
1718 | { | |
36cdd013 DW |
1719 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1720 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1721 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1722 | int ret; |
1723 | ||
36cdd013 | 1724 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1725 | return -ENODEV; |
1726 | ||
de227ef0 CW |
1727 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1728 | if (ret) | |
1729 | return ret; | |
7648fa99 JB |
1730 | |
1731 | temp = i915_mch_val(dev_priv); | |
1732 | chipset = i915_chipset_val(dev_priv); | |
1733 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1734 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1735 | |
1736 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1737 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1738 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1739 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1740 | ||
1741 | return 0; | |
1742 | } | |
1743 | ||
23b2f8bb JB |
1744 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1745 | { | |
36cdd013 | 1746 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
562d9bae | 1747 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
5bfa0199 | 1748 | int ret = 0; |
23b2f8bb | 1749 | int gpu_freq, ia_freq; |
f936ec34 | 1750 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1751 | |
ab309a6a MW |
1752 | if (!HAS_LLC(dev_priv)) |
1753 | return -ENODEV; | |
23b2f8bb | 1754 | |
5bfa0199 PZ |
1755 | intel_runtime_pm_get(dev_priv); |
1756 | ||
9f817501 | 1757 | ret = mutex_lock_interruptible(&dev_priv->pcu_lock); |
23b2f8bb | 1758 | if (ret) |
5bfa0199 | 1759 | goto out; |
23b2f8bb | 1760 | |
35ceabf3 | 1761 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
f936ec34 | 1762 | /* Convert GT frequency to 50 HZ units */ |
562d9bae SAK |
1763 | min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER; |
1764 | max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER; | |
f936ec34 | 1765 | } else { |
562d9bae SAK |
1766 | min_gpu_freq = rps->min_freq_softlimit; |
1767 | max_gpu_freq = rps->max_freq_softlimit; | |
f936ec34 AG |
1768 | } |
1769 | ||
267f0c90 | 1770 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1771 | |
f936ec34 | 1772 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1773 | ia_freq = gpu_freq; |
1774 | sandybridge_pcode_read(dev_priv, | |
1775 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1776 | &ia_freq); | |
3ebecd07 | 1777 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1778 | intel_gpu_freq(dev_priv, (gpu_freq * |
35ceabf3 RV |
1779 | (IS_GEN9_BC(dev_priv) || |
1780 | IS_CANNONLAKE(dev_priv) ? | |
b976dc53 | 1781 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1782 | ((ia_freq >> 0) & 0xff) * 100, |
1783 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1784 | } |
1785 | ||
9f817501 | 1786 | mutex_unlock(&dev_priv->pcu_lock); |
23b2f8bb | 1787 | |
5bfa0199 PZ |
1788 | out: |
1789 | intel_runtime_pm_put(dev_priv); | |
1790 | return ret; | |
23b2f8bb JB |
1791 | } |
1792 | ||
44834a67 CW |
1793 | static int i915_opregion(struct seq_file *m, void *unused) |
1794 | { | |
36cdd013 DW |
1795 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1796 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1797 | struct intel_opregion *opregion = &dev_priv->opregion; |
1798 | int ret; | |
1799 | ||
1800 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1801 | if (ret) | |
0d38f009 | 1802 | goto out; |
44834a67 | 1803 | |
2455a8e4 JN |
1804 | if (opregion->header) |
1805 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1806 | |
1807 | mutex_unlock(&dev->struct_mutex); | |
1808 | ||
0d38f009 | 1809 | out: |
44834a67 CW |
1810 | return 0; |
1811 | } | |
1812 | ||
ada8f955 JN |
1813 | static int i915_vbt(struct seq_file *m, void *unused) |
1814 | { | |
36cdd013 | 1815 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1816 | |
1817 | if (opregion->vbt) | |
1818 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1819 | ||
1820 | return 0; | |
1821 | } | |
1822 | ||
37811fcc CW |
1823 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1824 | { | |
36cdd013 DW |
1825 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1826 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1827 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1828 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1829 | int ret; |
1830 | ||
1831 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1832 | if (ret) | |
1833 | return ret; | |
37811fcc | 1834 | |
0695726e | 1835 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
346fb4e0 | 1836 | if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) { |
36cdd013 | 1837 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); |
25bcce94 CW |
1838 | |
1839 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1840 | fbdev_fb->base.width, | |
1841 | fbdev_fb->base.height, | |
b00c600e | 1842 | fbdev_fb->base.format->depth, |
272725c7 | 1843 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1844 | fbdev_fb->base.modifier, |
25bcce94 CW |
1845 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1846 | describe_obj(m, fbdev_fb->obj); | |
1847 | seq_putc(m, '\n'); | |
1848 | } | |
4520f53a | 1849 | #endif |
37811fcc | 1850 | |
4b096ac1 | 1851 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1852 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1853 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1854 | if (fb == fbdev_fb) | |
37811fcc CW |
1855 | continue; |
1856 | ||
c1ca506d | 1857 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1858 | fb->base.width, |
1859 | fb->base.height, | |
b00c600e | 1860 | fb->base.format->depth, |
272725c7 | 1861 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1862 | fb->base.modifier, |
747a598f | 1863 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1864 | describe_obj(m, fb->obj); |
267f0c90 | 1865 | seq_putc(m, '\n'); |
37811fcc | 1866 | } |
4b096ac1 | 1867 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1868 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1869 | |
1870 | return 0; | |
1871 | } | |
1872 | ||
7e37f889 | 1873 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd | 1874 | { |
fe085f13 CW |
1875 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)", |
1876 | ring->space, ring->head, ring->tail); | |
c9fe99bd OM |
1877 | } |
1878 | ||
e76d3630 BW |
1879 | static int i915_context_status(struct seq_file *m, void *unused) |
1880 | { | |
36cdd013 DW |
1881 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1882 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1883 | struct intel_engine_cs *engine; |
e2efd130 | 1884 | struct i915_gem_context *ctx; |
3b3f1650 | 1885 | enum intel_engine_id id; |
c3232b18 | 1886 | int ret; |
e76d3630 | 1887 | |
f3d28878 | 1888 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1889 | if (ret) |
1890 | return ret; | |
1891 | ||
829a0af2 | 1892 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
5d1808ec | 1893 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1894 | if (ctx->pid) { |
d28b99ab CW |
1895 | struct task_struct *task; |
1896 | ||
c84455b4 | 1897 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1898 | if (task) { |
1899 | seq_printf(m, "(%s [%d]) ", | |
1900 | task->comm, task->pid); | |
1901 | put_task_struct(task); | |
1902 | } | |
c84455b4 CW |
1903 | } else if (IS_ERR(ctx->file_priv)) { |
1904 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1905 | } else { |
1906 | seq_puts(m, "(kernel) "); | |
1907 | } | |
1908 | ||
bca44d80 CW |
1909 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1910 | seq_putc(m, '\n'); | |
c9fe99bd | 1911 | |
3b3f1650 | 1912 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1913 | struct intel_context *ce = &ctx->engine[engine->id]; |
1914 | ||
1915 | seq_printf(m, "%s: ", engine->name); | |
bca44d80 | 1916 | if (ce->state) |
bf3783e5 | 1917 | describe_obj(m, ce->state->obj); |
dca33ecc | 1918 | if (ce->ring) |
7e37f889 | 1919 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1920 | seq_putc(m, '\n'); |
c9fe99bd | 1921 | } |
a33afea5 | 1922 | |
a33afea5 | 1923 | seq_putc(m, '\n'); |
a168c293 BW |
1924 | } |
1925 | ||
f3d28878 | 1926 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1927 | |
1928 | return 0; | |
1929 | } | |
1930 | ||
ea16a3cd DV |
1931 | static const char *swizzle_string(unsigned swizzle) |
1932 | { | |
aee56cff | 1933 | switch (swizzle) { |
ea16a3cd DV |
1934 | case I915_BIT_6_SWIZZLE_NONE: |
1935 | return "none"; | |
1936 | case I915_BIT_6_SWIZZLE_9: | |
1937 | return "bit9"; | |
1938 | case I915_BIT_6_SWIZZLE_9_10: | |
1939 | return "bit9/bit10"; | |
1940 | case I915_BIT_6_SWIZZLE_9_11: | |
1941 | return "bit9/bit11"; | |
1942 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1943 | return "bit9/bit10/bit11"; | |
1944 | case I915_BIT_6_SWIZZLE_9_17: | |
1945 | return "bit9/bit17"; | |
1946 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1947 | return "bit9/bit10/bit17"; | |
1948 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1949 | return "unknown"; |
ea16a3cd DV |
1950 | } |
1951 | ||
1952 | return "bug"; | |
1953 | } | |
1954 | ||
1955 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1956 | { | |
36cdd013 | 1957 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 1958 | |
c8c8fb33 | 1959 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 1960 | |
ea16a3cd DV |
1961 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1962 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1963 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1964 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1965 | ||
36cdd013 | 1966 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
1967 | seq_printf(m, "DDC = 0x%08x\n", |
1968 | I915_READ(DCC)); | |
656bfa3a DV |
1969 | seq_printf(m, "DDC2 = 0x%08x\n", |
1970 | I915_READ(DCC2)); | |
ea16a3cd DV |
1971 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
1972 | I915_READ16(C0DRB3)); | |
1973 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1974 | I915_READ16(C1DRB3)); | |
36cdd013 | 1975 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
1976 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
1977 | I915_READ(MAD_DIMM_C0)); | |
1978 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1979 | I915_READ(MAD_DIMM_C1)); | |
1980 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1981 | I915_READ(MAD_DIMM_C2)); | |
1982 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1983 | I915_READ(TILECTL)); | |
36cdd013 | 1984 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
1985 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
1986 | I915_READ(GAMTARBMODE)); | |
1987 | else | |
1988 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1989 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
1990 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
1991 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 1992 | } |
656bfa3a DV |
1993 | |
1994 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
1995 | seq_puts(m, "L-shaped memory detected\n"); | |
1996 | ||
c8c8fb33 | 1997 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
1998 | |
1999 | return 0; | |
2000 | } | |
2001 | ||
1c60fef5 BW |
2002 | static int per_file_ctx(int id, void *ptr, void *data) |
2003 | { | |
e2efd130 | 2004 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2005 | struct seq_file *m = data; |
ae6c4806 DV |
2006 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2007 | ||
2008 | if (!ppgtt) { | |
2009 | seq_printf(m, " no ppgtt for context %d\n", | |
2010 | ctx->user_handle); | |
2011 | return 0; | |
2012 | } | |
1c60fef5 | 2013 | |
f83d6518 OM |
2014 | if (i915_gem_context_is_default(ctx)) |
2015 | seq_puts(m, " default context:\n"); | |
2016 | else | |
821d66dd | 2017 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2018 | ppgtt->debug_dump(ppgtt, m); |
2019 | ||
2020 | return 0; | |
2021 | } | |
2022 | ||
36cdd013 DW |
2023 | static void gen8_ppgtt_info(struct seq_file *m, |
2024 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2025 | { |
77df6772 | 2026 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2027 | struct intel_engine_cs *engine; |
2028 | enum intel_engine_id id; | |
b4ac5afc | 2029 | int i; |
3cf17fc5 | 2030 | |
77df6772 BW |
2031 | if (!ppgtt) |
2032 | return; | |
2033 | ||
3b3f1650 | 2034 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2035 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2036 | for (i = 0; i < 4; i++) { |
e2f80391 | 2037 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2038 | pdp <<= 32; |
e2f80391 | 2039 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2040 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2041 | } |
2042 | } | |
2043 | } | |
2044 | ||
36cdd013 DW |
2045 | static void gen6_ppgtt_info(struct seq_file *m, |
2046 | struct drm_i915_private *dev_priv) | |
77df6772 | 2047 | { |
e2f80391 | 2048 | struct intel_engine_cs *engine; |
3b3f1650 | 2049 | enum intel_engine_id id; |
3cf17fc5 | 2050 | |
7e22dbbb | 2051 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2052 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2053 | ||
3b3f1650 | 2054 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2055 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2056 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2057 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2058 | I915_READ(RING_MODE_GEN7(engine))); | |
2059 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2060 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2061 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2062 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2063 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2064 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2065 | } |
2066 | if (dev_priv->mm.aliasing_ppgtt) { | |
2067 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2068 | ||
267f0c90 | 2069 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2070 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2071 | |
87d60b63 | 2072 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2073 | } |
1c60fef5 | 2074 | |
3cf17fc5 | 2075 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2076 | } |
2077 | ||
2078 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2079 | { | |
36cdd013 DW |
2080 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2081 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2082 | struct drm_file *file; |
637ee29e | 2083 | int ret; |
77df6772 | 2084 | |
637ee29e CW |
2085 | mutex_lock(&dev->filelist_mutex); |
2086 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2087 | if (ret) |
637ee29e CW |
2088 | goto out_unlock; |
2089 | ||
c8c8fb33 | 2090 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2091 | |
36cdd013 DW |
2092 | if (INTEL_GEN(dev_priv) >= 8) |
2093 | gen8_ppgtt_info(m, dev_priv); | |
2094 | else if (INTEL_GEN(dev_priv) >= 6) | |
2095 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2096 | |
ea91e401 MT |
2097 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2098 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2099 | struct task_struct *task; |
ea91e401 | 2100 | |
7cb5dff8 | 2101 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2102 | if (!task) { |
2103 | ret = -ESRCH; | |
637ee29e | 2104 | goto out_rpm; |
06812760 | 2105 | } |
7cb5dff8 GT |
2106 | seq_printf(m, "\nproc: %s\n", task->comm); |
2107 | put_task_struct(task); | |
ea91e401 MT |
2108 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2109 | (void *)(unsigned long)m); | |
2110 | } | |
2111 | ||
637ee29e | 2112 | out_rpm: |
c8c8fb33 | 2113 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2114 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2115 | out_unlock: |
2116 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2117 | return ret; |
3cf17fc5 DV |
2118 | } |
2119 | ||
f5a4c67d CW |
2120 | static int count_irq_waiters(struct drm_i915_private *i915) |
2121 | { | |
e2f80391 | 2122 | struct intel_engine_cs *engine; |
3b3f1650 | 2123 | enum intel_engine_id id; |
f5a4c67d | 2124 | int count = 0; |
f5a4c67d | 2125 | |
3b3f1650 | 2126 | for_each_engine(engine, i915, id) |
688e6c72 | 2127 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2128 | |
2129 | return count; | |
2130 | } | |
2131 | ||
7466c291 CW |
2132 | static const char *rps_power_to_str(unsigned int power) |
2133 | { | |
2134 | static const char * const strings[] = { | |
2135 | [LOW_POWER] = "low power", | |
2136 | [BETWEEN] = "mixed", | |
2137 | [HIGH_POWER] = "high power", | |
2138 | }; | |
2139 | ||
2140 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2141 | return "unknown"; | |
2142 | ||
2143 | return strings[power]; | |
2144 | } | |
2145 | ||
1854d5ca CW |
2146 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2147 | { | |
36cdd013 DW |
2148 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2149 | struct drm_device *dev = &dev_priv->drm; | |
562d9bae | 2150 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
1854d5ca | 2151 | struct drm_file *file; |
1854d5ca | 2152 | |
562d9bae | 2153 | seq_printf(m, "RPS enabled? %d\n", rps->enabled); |
28176ef4 CW |
2154 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2155 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2156 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7b92c1bd | 2157 | seq_printf(m, "Boosts outstanding? %d\n", |
562d9bae | 2158 | atomic_read(&rps->num_waiters)); |
7466c291 | 2159 | seq_printf(m, "Frequency requested %d\n", |
562d9bae | 2160 | intel_gpu_freq(dev_priv, rps->cur_freq)); |
7466c291 | 2161 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", |
562d9bae SAK |
2162 | intel_gpu_freq(dev_priv, rps->min_freq), |
2163 | intel_gpu_freq(dev_priv, rps->min_freq_softlimit), | |
2164 | intel_gpu_freq(dev_priv, rps->max_freq_softlimit), | |
2165 | intel_gpu_freq(dev_priv, rps->max_freq)); | |
7466c291 | 2166 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
562d9bae SAK |
2167 | intel_gpu_freq(dev_priv, rps->idle_freq), |
2168 | intel_gpu_freq(dev_priv, rps->efficient_freq), | |
2169 | intel_gpu_freq(dev_priv, rps->boost_freq)); | |
1d2ac403 DV |
2170 | |
2171 | mutex_lock(&dev->filelist_mutex); | |
1854d5ca CW |
2172 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2173 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2174 | struct task_struct *task; | |
2175 | ||
2176 | rcu_read_lock(); | |
2177 | task = pid_task(file->pid, PIDTYPE_PID); | |
7b92c1bd | 2178 | seq_printf(m, "%s [%d]: %d boosts\n", |
1854d5ca CW |
2179 | task ? task->comm : "<unknown>", |
2180 | task ? task->pid : -1, | |
562d9bae | 2181 | atomic_read(&file_priv->rps_client.boosts)); |
1854d5ca CW |
2182 | rcu_read_unlock(); |
2183 | } | |
7b92c1bd | 2184 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", |
562d9bae | 2185 | atomic_read(&rps->boosts)); |
1d2ac403 | 2186 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2187 | |
7466c291 | 2188 | if (INTEL_GEN(dev_priv) >= 6 && |
562d9bae | 2189 | rps->enabled && |
28176ef4 | 2190 | dev_priv->gt.active_requests) { |
7466c291 CW |
2191 | u32 rpup, rpupei; |
2192 | u32 rpdown, rpdownei; | |
2193 | ||
2194 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2195 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2196 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2197 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2198 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2199 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2200 | ||
2201 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
562d9bae | 2202 | rps_power_to_str(rps->power)); |
7466c291 | 2203 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", |
23f4a287 | 2204 | rpup && rpupei ? 100 * rpup / rpupei : 0, |
562d9bae | 2205 | rps->up_threshold); |
7466c291 | 2206 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", |
23f4a287 | 2207 | rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, |
562d9bae | 2208 | rps->down_threshold); |
7466c291 CW |
2209 | } else { |
2210 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2211 | } | |
2212 | ||
8d3afd7d | 2213 | return 0; |
1854d5ca CW |
2214 | } |
2215 | ||
63573eb7 BW |
2216 | static int i915_llc(struct seq_file *m, void *data) |
2217 | { | |
36cdd013 | 2218 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2219 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2220 | |
36cdd013 | 2221 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2222 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2223 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2224 | |
2225 | return 0; | |
2226 | } | |
2227 | ||
0509ead1 AS |
2228 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2229 | { | |
2230 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
56ffc742 | 2231 | struct drm_printer p; |
0509ead1 | 2232 | |
ab309a6a MW |
2233 | if (!HAS_HUC(dev_priv)) |
2234 | return -ENODEV; | |
0509ead1 | 2235 | |
56ffc742 MW |
2236 | p = drm_seq_file_printer(m); |
2237 | intel_uc_fw_dump(&dev_priv->huc.fw, &p); | |
0509ead1 | 2238 | |
3582ad13 | 2239 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2240 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2241 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2242 | |
2243 | return 0; | |
2244 | } | |
2245 | ||
fdf5d357 AD |
2246 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2247 | { | |
36cdd013 | 2248 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
56ffc742 | 2249 | struct drm_printer p; |
fdf5d357 AD |
2250 | u32 tmp, i; |
2251 | ||
ab309a6a MW |
2252 | if (!HAS_GUC(dev_priv)) |
2253 | return -ENODEV; | |
fdf5d357 | 2254 | |
56ffc742 MW |
2255 | p = drm_seq_file_printer(m); |
2256 | intel_uc_fw_dump(&dev_priv->guc.fw, &p); | |
fdf5d357 | 2257 | |
3582ad13 | 2258 | intel_runtime_pm_get(dev_priv); |
2259 | ||
fdf5d357 AD |
2260 | tmp = I915_READ(GUC_STATUS); |
2261 | ||
2262 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2263 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2264 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2265 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2266 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2267 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2268 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2269 | seq_puts(m, "\nScratch registers:\n"); | |
2270 | for (i = 0; i < 16; i++) | |
2271 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2272 | ||
3582ad13 | 2273 | intel_runtime_pm_put(dev_priv); |
2274 | ||
fdf5d357 AD |
2275 | return 0; |
2276 | } | |
2277 | ||
5aa1ee4b AG |
2278 | static void i915_guc_log_info(struct seq_file *m, |
2279 | struct drm_i915_private *dev_priv) | |
2280 | { | |
2281 | struct intel_guc *guc = &dev_priv->guc; | |
2282 | ||
2283 | seq_puts(m, "\nGuC logging stats:\n"); | |
2284 | ||
2285 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2286 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2287 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2288 | ||
2289 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2290 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2291 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2292 | ||
2293 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2294 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2295 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2296 | ||
2297 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2298 | guc->log.flush_interrupt_count); | |
2299 | ||
2300 | seq_printf(m, "\tCapture miss count: %u\n", | |
2301 | guc->log.capture_miss_count); | |
2302 | } | |
2303 | ||
8b417c26 DG |
2304 | static void i915_guc_client_info(struct seq_file *m, |
2305 | struct drm_i915_private *dev_priv, | |
5afc8b49 | 2306 | struct intel_guc_client *client) |
8b417c26 | 2307 | { |
e2f80391 | 2308 | struct intel_engine_cs *engine; |
c18468c4 | 2309 | enum intel_engine_id id; |
8b417c26 | 2310 | uint64_t tot = 0; |
8b417c26 | 2311 | |
b09935a6 OM |
2312 | seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n", |
2313 | client->priority, client->stage_id, client->proc_desc_offset); | |
59db36cf MW |
2314 | seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n", |
2315 | client->doorbell_id, client->doorbell_offset); | |
8b417c26 | 2316 | |
3b3f1650 | 2317 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2318 | u64 submissions = client->submissions[id]; |
2319 | tot += submissions; | |
8b417c26 | 2320 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2321 | submissions, engine->name); |
8b417c26 DG |
2322 | } |
2323 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2324 | } | |
2325 | ||
a8b9370f OM |
2326 | static int i915_guc_info(struct seq_file *m, void *data) |
2327 | { | |
2328 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2329 | const struct intel_guc *guc = &dev_priv->guc; | |
a8b9370f | 2330 | |
ab309a6a MW |
2331 | if (!USES_GUC_SUBMISSION(dev_priv)) |
2332 | return -ENODEV; | |
2333 | ||
2334 | GEM_BUG_ON(!guc->execbuf_client); | |
a8b9370f | 2335 | |
9636f6db | 2336 | seq_printf(m, "Doorbell map:\n"); |
abddffdf | 2337 | seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); |
334636c6 | 2338 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); |
9636f6db | 2339 | |
334636c6 CW |
2340 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2341 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
e78c9175 CW |
2342 | if (guc->preempt_client) { |
2343 | seq_printf(m, "\nGuC preempt client @ %p:\n", | |
2344 | guc->preempt_client); | |
2345 | i915_guc_client_info(m, dev_priv, guc->preempt_client); | |
2346 | } | |
8b417c26 | 2347 | |
5aa1ee4b AG |
2348 | i915_guc_log_info(m, dev_priv); |
2349 | ||
8b417c26 DG |
2350 | /* Add more as required ... */ |
2351 | ||
2352 | return 0; | |
2353 | } | |
2354 | ||
a8b9370f | 2355 | static int i915_guc_stage_pool(struct seq_file *m, void *data) |
4c7e77fc | 2356 | { |
36cdd013 | 2357 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a8b9370f OM |
2358 | const struct intel_guc *guc = &dev_priv->guc; |
2359 | struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; | |
5afc8b49 | 2360 | struct intel_guc_client *client = guc->execbuf_client; |
a8b9370f OM |
2361 | unsigned int tmp; |
2362 | int index; | |
4c7e77fc | 2363 | |
ab309a6a MW |
2364 | if (!USES_GUC_SUBMISSION(dev_priv)) |
2365 | return -ENODEV; | |
4c7e77fc | 2366 | |
a8b9370f OM |
2367 | for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) { |
2368 | struct intel_engine_cs *engine; | |
2369 | ||
2370 | if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE)) | |
2371 | continue; | |
2372 | ||
2373 | seq_printf(m, "GuC stage descriptor %u:\n", index); | |
2374 | seq_printf(m, "\tIndex: %u\n", desc->stage_id); | |
2375 | seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute); | |
2376 | seq_printf(m, "\tPriority: %d\n", desc->priority); | |
2377 | seq_printf(m, "\tDoorbell id: %d\n", desc->db_id); | |
2378 | seq_printf(m, "\tEngines used: 0x%x\n", | |
2379 | desc->engines_used); | |
2380 | seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n", | |
2381 | desc->db_trigger_phy, | |
2382 | desc->db_trigger_cpu, | |
2383 | desc->db_trigger_uk); | |
2384 | seq_printf(m, "\tProcess descriptor: 0x%x\n", | |
2385 | desc->process_desc); | |
9a09485d | 2386 | seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n", |
a8b9370f OM |
2387 | desc->wq_addr, desc->wq_size); |
2388 | seq_putc(m, '\n'); | |
2389 | ||
2390 | for_each_engine_masked(engine, dev_priv, client->engines, tmp) { | |
2391 | u32 guc_engine_id = engine->guc_id; | |
2392 | struct guc_execlist_context *lrc = | |
2393 | &desc->lrc[guc_engine_id]; | |
2394 | ||
2395 | seq_printf(m, "\t%s LRC:\n", engine->name); | |
2396 | seq_printf(m, "\t\tContext desc: 0x%x\n", | |
2397 | lrc->context_desc); | |
2398 | seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id); | |
2399 | seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca); | |
2400 | seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin); | |
2401 | seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end); | |
2402 | seq_putc(m, '\n'); | |
2403 | } | |
2404 | } | |
2405 | ||
2406 | return 0; | |
2407 | } | |
2408 | ||
4c7e77fc AD |
2409 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2410 | { | |
ac58d2ab DCS |
2411 | struct drm_info_node *node = m->private; |
2412 | struct drm_i915_private *dev_priv = node_to_i915(node); | |
2413 | bool dump_load_err = !!node->info_ent->data; | |
2414 | struct drm_i915_gem_object *obj = NULL; | |
2415 | u32 *log; | |
2416 | int i = 0; | |
4c7e77fc | 2417 | |
ab309a6a MW |
2418 | if (!HAS_GUC(dev_priv)) |
2419 | return -ENODEV; | |
2420 | ||
ac58d2ab DCS |
2421 | if (dump_load_err) |
2422 | obj = dev_priv->guc.load_err_log; | |
2423 | else if (dev_priv->guc.log.vma) | |
2424 | obj = dev_priv->guc.log.vma->obj; | |
4c7e77fc | 2425 | |
ac58d2ab DCS |
2426 | if (!obj) |
2427 | return 0; | |
4c7e77fc | 2428 | |
ac58d2ab DCS |
2429 | log = i915_gem_object_pin_map(obj, I915_MAP_WC); |
2430 | if (IS_ERR(log)) { | |
2431 | DRM_DEBUG("Failed to pin object\n"); | |
2432 | seq_puts(m, "(log data unaccessible)\n"); | |
2433 | return PTR_ERR(log); | |
4c7e77fc AD |
2434 | } |
2435 | ||
ac58d2ab DCS |
2436 | for (i = 0; i < obj->base.size / sizeof(u32); i += 4) |
2437 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2438 | *(log + i), *(log + i + 1), | |
2439 | *(log + i + 2), *(log + i + 3)); | |
2440 | ||
4c7e77fc AD |
2441 | seq_putc(m, '\n'); |
2442 | ||
ac58d2ab DCS |
2443 | i915_gem_object_unpin_map(obj); |
2444 | ||
4c7e77fc AD |
2445 | return 0; |
2446 | } | |
2447 | ||
685534ef SAK |
2448 | static int i915_guc_log_control_get(void *data, u64 *val) |
2449 | { | |
bcc36d8a | 2450 | struct drm_i915_private *dev_priv = data; |
685534ef | 2451 | |
ab309a6a MW |
2452 | if (!HAS_GUC(dev_priv)) |
2453 | return -ENODEV; | |
2454 | ||
685534ef SAK |
2455 | if (!dev_priv->guc.log.vma) |
2456 | return -EINVAL; | |
2457 | ||
4f044a88 | 2458 | *val = i915_modparams.guc_log_level; |
685534ef SAK |
2459 | |
2460 | return 0; | |
2461 | } | |
2462 | ||
2463 | static int i915_guc_log_control_set(void *data, u64 val) | |
2464 | { | |
bcc36d8a | 2465 | struct drm_i915_private *dev_priv = data; |
685534ef | 2466 | |
ab309a6a MW |
2467 | if (!HAS_GUC(dev_priv)) |
2468 | return -ENODEV; | |
2469 | ||
065dd5ad | 2470 | return intel_guc_log_control(&dev_priv->guc, val); |
685534ef SAK |
2471 | } |
2472 | ||
2473 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2474 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2475 | "%lld\n"); | |
2476 | ||
b86bef20 CW |
2477 | static const char *psr2_live_status(u32 val) |
2478 | { | |
2479 | static const char * const live_status[] = { | |
2480 | "IDLE", | |
2481 | "CAPTURE", | |
2482 | "CAPTURE_FS", | |
2483 | "SLEEP", | |
2484 | "BUFON_FW", | |
2485 | "ML_UP", | |
2486 | "SU_STANDBY", | |
2487 | "FAST_SLEEP", | |
2488 | "DEEP_SLEEP", | |
2489 | "BUF_ON", | |
2490 | "TG_ON" | |
2491 | }; | |
2492 | ||
2493 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2494 | if (val < ARRAY_SIZE(live_status)) | |
2495 | return live_status[val]; | |
2496 | ||
2497 | return "unknown"; | |
2498 | } | |
2499 | ||
e91fd8c6 RV |
2500 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2501 | { | |
36cdd013 | 2502 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2503 | u32 psrperf = 0; |
a6cbdb8e RV |
2504 | u32 stat[3]; |
2505 | enum pipe pipe; | |
a031d709 | 2506 | bool enabled = false; |
c9ef291a | 2507 | bool sink_support; |
e91fd8c6 | 2508 | |
ab309a6a MW |
2509 | if (!HAS_PSR(dev_priv)) |
2510 | return -ENODEV; | |
3553a8ea | 2511 | |
c9ef291a DP |
2512 | sink_support = dev_priv->psr.sink_support; |
2513 | seq_printf(m, "Sink_Support: %s\n", yesno(sink_support)); | |
2514 | if (!sink_support) | |
2515 | return 0; | |
2516 | ||
c8c8fb33 PZ |
2517 | intel_runtime_pm_get(dev_priv); |
2518 | ||
fa128fa6 | 2519 | mutex_lock(&dev_priv->psr.lock); |
2807cf69 | 2520 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2521 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2522 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2523 | dev_priv->psr.busy_frontbuffer_bits); | |
2524 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2525 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2526 | |
7e3eb599 NV |
2527 | if (HAS_DDI(dev_priv)) { |
2528 | if (dev_priv->psr.psr2_support) | |
2529 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2530 | else | |
2531 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2532 | } else { | |
3553a8ea | 2533 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2534 | enum transcoder cpu_transcoder = |
2535 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2536 | enum intel_display_power_domain power_domain; | |
2537 | ||
2538 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2539 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2540 | power_domain)) | |
2541 | continue; | |
2542 | ||
3553a8ea DL |
2543 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2544 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2545 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2546 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2547 | enabled = true; | |
9c870d03 CW |
2548 | |
2549 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2550 | } |
2551 | } | |
60e5ffe3 RV |
2552 | |
2553 | seq_printf(m, "Main link in standby mode: %s\n", | |
2554 | yesno(dev_priv->psr.link_standby)); | |
2555 | ||
a6cbdb8e RV |
2556 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2557 | ||
36cdd013 | 2558 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2559 | for_each_pipe(dev_priv, pipe) { |
2560 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2561 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2562 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2563 | } | |
2564 | seq_puts(m, "\n"); | |
e91fd8c6 | 2565 | |
05eec3c2 RV |
2566 | /* |
2567 | * VLV/CHV PSR has no kind of performance counter | |
2568 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2569 | */ | |
36cdd013 | 2570 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2571 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2572 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2573 | |
2574 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2575 | } | |
6ba1f9e1 | 2576 | if (dev_priv->psr.psr2_support) { |
861023e0 | 2577 | u32 psr2 = I915_READ(EDP_PSR2_STATUS); |
b86bef20 | 2578 | |
861023e0 | 2579 | seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n", |
b86bef20 | 2580 | psr2, psr2_live_status(psr2)); |
6ba1f9e1 | 2581 | } |
fa128fa6 | 2582 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2583 | |
c8c8fb33 | 2584 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2585 | return 0; |
2586 | } | |
2587 | ||
d2e216d0 RV |
2588 | static int i915_sink_crc(struct seq_file *m, void *data) |
2589 | { | |
36cdd013 DW |
2590 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2591 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 | 2592 | struct intel_connector *connector; |
3f6a5e1e | 2593 | struct drm_connector_list_iter conn_iter; |
d2e216d0 | 2594 | struct intel_dp *intel_dp = NULL; |
10bf0a38 | 2595 | struct drm_modeset_acquire_ctx ctx; |
d2e216d0 RV |
2596 | int ret; |
2597 | u8 crc[6]; | |
2598 | ||
10bf0a38 ML |
2599 | drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); |
2600 | ||
3f6a5e1e | 2601 | drm_connector_list_iter_begin(dev, &conn_iter); |
10bf0a38 | 2602 | |
3f6a5e1e | 2603 | for_each_intel_connector_iter(connector, &conn_iter) { |
26c17cf6 | 2604 | struct drm_crtc *crtc; |
10bf0a38 | 2605 | struct drm_connector_state *state; |
93313538 | 2606 | struct intel_crtc_state *crtc_state; |
d2e216d0 | 2607 | |
10bf0a38 | 2608 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2609 | continue; |
2610 | ||
10bf0a38 ML |
2611 | retry: |
2612 | ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); | |
2613 | if (ret) | |
2614 | goto err; | |
2615 | ||
2616 | state = connector->base.state; | |
2617 | if (!state->best_encoder) | |
b6ae3c7c PZ |
2618 | continue; |
2619 | ||
10bf0a38 ML |
2620 | crtc = state->crtc; |
2621 | ret = drm_modeset_lock(&crtc->mutex, &ctx); | |
2622 | if (ret) | |
2623 | goto err; | |
2624 | ||
93313538 ML |
2625 | crtc_state = to_intel_crtc_state(crtc->state); |
2626 | if (!crtc_state->base.active) | |
d2e216d0 RV |
2627 | continue; |
2628 | ||
93313538 ML |
2629 | /* |
2630 | * We need to wait for all crtc updates to complete, to make | |
2631 | * sure any pending modesets and plane updates are completed. | |
2632 | */ | |
2633 | if (crtc_state->base.commit) { | |
2634 | ret = wait_for_completion_interruptible(&crtc_state->base.commit->hw_done); | |
2635 | ||
2636 | if (ret) | |
2637 | goto err; | |
2638 | } | |
2639 | ||
10bf0a38 | 2640 | intel_dp = enc_to_intel_dp(state->best_encoder); |
d2e216d0 | 2641 | |
93313538 | 2642 | ret = intel_dp_sink_crc(intel_dp, crtc_state, crc); |
d2e216d0 | 2643 | if (ret) |
10bf0a38 | 2644 | goto err; |
d2e216d0 RV |
2645 | |
2646 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2647 | crc[0], crc[1], crc[2], | |
2648 | crc[3], crc[4], crc[5]); | |
2649 | goto out; | |
10bf0a38 ML |
2650 | |
2651 | err: | |
2652 | if (ret == -EDEADLK) { | |
2653 | ret = drm_modeset_backoff(&ctx); | |
2654 | if (!ret) | |
2655 | goto retry; | |
2656 | } | |
2657 | goto out; | |
d2e216d0 RV |
2658 | } |
2659 | ret = -ENODEV; | |
2660 | out: | |
3f6a5e1e | 2661 | drm_connector_list_iter_end(&conn_iter); |
10bf0a38 ML |
2662 | drm_modeset_drop_locks(&ctx); |
2663 | drm_modeset_acquire_fini(&ctx); | |
2664 | ||
d2e216d0 RV |
2665 | return ret; |
2666 | } | |
2667 | ||
ec013e7f JB |
2668 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2669 | { | |
36cdd013 | 2670 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
d38014ea | 2671 | unsigned long long power; |
ec013e7f JB |
2672 | u32 units; |
2673 | ||
36cdd013 | 2674 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2675 | return -ENODEV; |
2676 | ||
36623ef8 PZ |
2677 | intel_runtime_pm_get(dev_priv); |
2678 | ||
d38014ea GKB |
2679 | if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) { |
2680 | intel_runtime_pm_put(dev_priv); | |
2681 | return -ENODEV; | |
2682 | } | |
2683 | ||
2684 | units = (power & 0x1f00) >> 8; | |
ec013e7f | 2685 | power = I915_READ(MCH_SECP_NRG_STTS); |
d38014ea | 2686 | power = (1000000 * power) >> units; /* convert to uJ */ |
ec013e7f | 2687 | |
36623ef8 PZ |
2688 | intel_runtime_pm_put(dev_priv); |
2689 | ||
d38014ea | 2690 | seq_printf(m, "%llu", power); |
371db66a PZ |
2691 | |
2692 | return 0; | |
2693 | } | |
2694 | ||
6455c870 | 2695 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2696 | { |
36cdd013 | 2697 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2698 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2699 | |
a156e64d CW |
2700 | if (!HAS_RUNTIME_PM(dev_priv)) |
2701 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2702 | |
6f56103d CW |
2703 | seq_printf(m, "GPU idle: %s (epoch %u)\n", |
2704 | yesno(!dev_priv->gt.awake), dev_priv->gt.epoch); | |
371db66a | 2705 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2706 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2707 | #ifdef CONFIG_PM |
a6aaec8b | 2708 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2709 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2710 | #else |
2711 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2712 | #endif | |
a156e64d | 2713 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2714 | pci_power_name(pdev->current_state), |
2715 | pdev->current_state); | |
371db66a | 2716 | |
ec013e7f JB |
2717 | return 0; |
2718 | } | |
2719 | ||
1da51581 ID |
2720 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2721 | { | |
36cdd013 | 2722 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2723 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2724 | int i; | |
2725 | ||
2726 | mutex_lock(&power_domains->lock); | |
2727 | ||
2728 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2729 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2730 | struct i915_power_well *power_well; | |
2731 | enum intel_display_power_domain power_domain; | |
2732 | ||
2733 | power_well = &power_domains->power_wells[i]; | |
2734 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2735 | power_well->count); | |
2736 | ||
8385c2ec | 2737 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2738 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2739 | intel_display_power_domain_str(power_domain), |
1da51581 | 2740 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2741 | } |
2742 | ||
2743 | mutex_unlock(&power_domains->lock); | |
2744 | ||
2745 | return 0; | |
2746 | } | |
2747 | ||
b7cec66d DL |
2748 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2749 | { | |
36cdd013 | 2750 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2751 | struct intel_csr *csr; |
2752 | ||
ab309a6a MW |
2753 | if (!HAS_CSR(dev_priv)) |
2754 | return -ENODEV; | |
b7cec66d DL |
2755 | |
2756 | csr = &dev_priv->csr; | |
2757 | ||
6fb403de MK |
2758 | intel_runtime_pm_get(dev_priv); |
2759 | ||
b7cec66d DL |
2760 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2761 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2762 | ||
2763 | if (!csr->dmc_payload) | |
6fb403de | 2764 | goto out; |
b7cec66d DL |
2765 | |
2766 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2767 | CSR_VERSION_MINOR(csr->version)); | |
2768 | ||
48de568c MK |
2769 | if (IS_KABYLAKE(dev_priv) || |
2770 | (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) { | |
8337206d DL |
2771 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2772 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2773 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2774 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2775 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2776 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2777 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2778 | } |
2779 | ||
6fb403de MK |
2780 | out: |
2781 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2782 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2783 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2784 | ||
8337206d DL |
2785 | intel_runtime_pm_put(dev_priv); |
2786 | ||
b7cec66d DL |
2787 | return 0; |
2788 | } | |
2789 | ||
53f5e3ca JB |
2790 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2791 | struct drm_display_mode *mode) | |
2792 | { | |
2793 | int i; | |
2794 | ||
2795 | for (i = 0; i < tabs; i++) | |
2796 | seq_putc(m, '\t'); | |
2797 | ||
2798 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2799 | mode->base.id, mode->name, | |
2800 | mode->vrefresh, mode->clock, | |
2801 | mode->hdisplay, mode->hsync_start, | |
2802 | mode->hsync_end, mode->htotal, | |
2803 | mode->vdisplay, mode->vsync_start, | |
2804 | mode->vsync_end, mode->vtotal, | |
2805 | mode->type, mode->flags); | |
2806 | } | |
2807 | ||
2808 | static void intel_encoder_info(struct seq_file *m, | |
2809 | struct intel_crtc *intel_crtc, | |
2810 | struct intel_encoder *intel_encoder) | |
2811 | { | |
36cdd013 DW |
2812 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2813 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2814 | struct drm_crtc *crtc = &intel_crtc->base; |
2815 | struct intel_connector *intel_connector; | |
2816 | struct drm_encoder *encoder; | |
2817 | ||
2818 | encoder = &intel_encoder->base; | |
2819 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2820 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2821 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2822 | struct drm_connector *connector = &intel_connector->base; | |
2823 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2824 | connector->base.id, | |
c23cc417 | 2825 | connector->name, |
53f5e3ca JB |
2826 | drm_get_connector_status_name(connector->status)); |
2827 | if (connector->status == connector_status_connected) { | |
2828 | struct drm_display_mode *mode = &crtc->mode; | |
2829 | seq_printf(m, ", mode:\n"); | |
2830 | intel_seq_print_mode(m, 2, mode); | |
2831 | } else { | |
2832 | seq_putc(m, '\n'); | |
2833 | } | |
2834 | } | |
2835 | } | |
2836 | ||
2837 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2838 | { | |
36cdd013 DW |
2839 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2840 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2841 | struct drm_crtc *crtc = &intel_crtc->base; |
2842 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2843 | struct drm_plane_state *plane_state = crtc->primary->state; |
2844 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2845 | |
23a48d53 | 2846 | if (fb) |
5aa8a937 | 2847 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2848 | fb->base.id, plane_state->src_x >> 16, |
2849 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2850 | else |
2851 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2852 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2853 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2854 | } | |
2855 | ||
2856 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2857 | { | |
2858 | struct drm_display_mode *mode = panel->fixed_mode; | |
2859 | ||
2860 | seq_printf(m, "\tfixed mode:\n"); | |
2861 | intel_seq_print_mode(m, 2, mode); | |
2862 | } | |
2863 | ||
2864 | static void intel_dp_info(struct seq_file *m, | |
2865 | struct intel_connector *intel_connector) | |
2866 | { | |
2867 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2868 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2869 | ||
2870 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2871 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2872 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2873 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2874 | |
2875 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2876 | &intel_dp->aux); | |
53f5e3ca JB |
2877 | } |
2878 | ||
9a148a96 LY |
2879 | static void intel_dp_mst_info(struct seq_file *m, |
2880 | struct intel_connector *intel_connector) | |
2881 | { | |
2882 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2883 | struct intel_dp_mst_encoder *intel_mst = | |
2884 | enc_to_mst(&intel_encoder->base); | |
2885 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2886 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2887 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2888 | intel_connector->port); | |
2889 | ||
2890 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2891 | } | |
2892 | ||
53f5e3ca JB |
2893 | static void intel_hdmi_info(struct seq_file *m, |
2894 | struct intel_connector *intel_connector) | |
2895 | { | |
2896 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2897 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2898 | ||
742f491d | 2899 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2900 | } |
2901 | ||
2902 | static void intel_lvds_info(struct seq_file *m, | |
2903 | struct intel_connector *intel_connector) | |
2904 | { | |
2905 | intel_panel_info(m, &intel_connector->panel); | |
2906 | } | |
2907 | ||
2908 | static void intel_connector_info(struct seq_file *m, | |
2909 | struct drm_connector *connector) | |
2910 | { | |
2911 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2912 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2913 | struct drm_display_mode *mode; |
53f5e3ca JB |
2914 | |
2915 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2916 | connector->base.id, connector->name, |
53f5e3ca JB |
2917 | drm_get_connector_status_name(connector->status)); |
2918 | if (connector->status == connector_status_connected) { | |
2919 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2920 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2921 | connector->display_info.width_mm, | |
2922 | connector->display_info.height_mm); | |
2923 | seq_printf(m, "\tsubpixel order: %s\n", | |
2924 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2925 | seq_printf(m, "\tCEA rev: %d\n", | |
2926 | connector->display_info.cea_rev); | |
2927 | } | |
ee648a74 | 2928 | |
77d1f615 | 2929 | if (!intel_encoder) |
ee648a74 ML |
2930 | return; |
2931 | ||
2932 | switch (connector->connector_type) { | |
2933 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2934 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
2935 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
2936 | intel_dp_mst_info(m, intel_connector); | |
2937 | else | |
2938 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
2939 | break; |
2940 | case DRM_MODE_CONNECTOR_LVDS: | |
2941 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 2942 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
2943 | break; |
2944 | case DRM_MODE_CONNECTOR_HDMIA: | |
2945 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
7e732cac | 2946 | intel_encoder->type == INTEL_OUTPUT_DDI) |
ee648a74 ML |
2947 | intel_hdmi_info(m, intel_connector); |
2948 | break; | |
2949 | default: | |
2950 | break; | |
36cd7444 | 2951 | } |
53f5e3ca | 2952 | |
f103fc7d JB |
2953 | seq_printf(m, "\tmodes:\n"); |
2954 | list_for_each_entry(mode, &connector->modes, head) | |
2955 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2956 | } |
2957 | ||
3abc4e09 RF |
2958 | static const char *plane_type(enum drm_plane_type type) |
2959 | { | |
2960 | switch (type) { | |
2961 | case DRM_PLANE_TYPE_OVERLAY: | |
2962 | return "OVL"; | |
2963 | case DRM_PLANE_TYPE_PRIMARY: | |
2964 | return "PRI"; | |
2965 | case DRM_PLANE_TYPE_CURSOR: | |
2966 | return "CUR"; | |
2967 | /* | |
2968 | * Deliberately omitting default: to generate compiler warnings | |
2969 | * when a new drm_plane_type gets added. | |
2970 | */ | |
2971 | } | |
2972 | ||
2973 | return "unknown"; | |
2974 | } | |
2975 | ||
2976 | static const char *plane_rotation(unsigned int rotation) | |
2977 | { | |
2978 | static char buf[48]; | |
2979 | /* | |
c2c446ad | 2980 | * According to doc only one DRM_MODE_ROTATE_ is allowed but this |
3abc4e09 RF |
2981 | * will print them all to visualize if the values are misused |
2982 | */ | |
2983 | snprintf(buf, sizeof(buf), | |
2984 | "%s%s%s%s%s%s(0x%08x)", | |
c2c446ad RF |
2985 | (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", |
2986 | (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", | |
2987 | (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", | |
2988 | (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", | |
2989 | (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", | |
2990 | (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
2991 | rotation); |
2992 | ||
2993 | return buf; | |
2994 | } | |
2995 | ||
2996 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2997 | { | |
36cdd013 DW |
2998 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2999 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3000 | struct intel_plane *intel_plane; |
3001 | ||
3002 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3003 | struct drm_plane_state *state; | |
3004 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3005 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3006 | |
3007 | if (!plane->state) { | |
3008 | seq_puts(m, "plane->state is NULL!\n"); | |
3009 | continue; | |
3010 | } | |
3011 | ||
3012 | state = plane->state; | |
3013 | ||
90844f00 | 3014 | if (state->fb) { |
438b74a5 VS |
3015 | drm_get_format_name(state->fb->format->format, |
3016 | &format_name); | |
90844f00 | 3017 | } else { |
b3c11ac2 | 3018 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3019 | } |
3020 | ||
3abc4e09 RF |
3021 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3022 | plane->base.id, | |
3023 | plane_type(intel_plane->base.type), | |
3024 | state->crtc_x, state->crtc_y, | |
3025 | state->crtc_w, state->crtc_h, | |
3026 | (state->src_x >> 16), | |
3027 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3028 | (state->src_y >> 16), | |
3029 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3030 | (state->src_w >> 16), | |
3031 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3032 | (state->src_h >> 16), | |
3033 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3034 | format_name.str, |
3abc4e09 RF |
3035 | plane_rotation(state->rotation)); |
3036 | } | |
3037 | } | |
3038 | ||
3039 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3040 | { | |
3041 | struct intel_crtc_state *pipe_config; | |
3042 | int num_scalers = intel_crtc->num_scalers; | |
3043 | int i; | |
3044 | ||
3045 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3046 | ||
3047 | /* Not all platformas have a scaler */ | |
3048 | if (num_scalers) { | |
3049 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3050 | num_scalers, | |
3051 | pipe_config->scaler_state.scaler_users, | |
3052 | pipe_config->scaler_state.scaler_id); | |
3053 | ||
58415918 | 3054 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3055 | struct intel_scaler *sc = |
3056 | &pipe_config->scaler_state.scalers[i]; | |
3057 | ||
3058 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3059 | i, yesno(sc->in_use), sc->mode); | |
3060 | } | |
3061 | seq_puts(m, "\n"); | |
3062 | } else { | |
3063 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3064 | } | |
3065 | } | |
3066 | ||
53f5e3ca JB |
3067 | static int i915_display_info(struct seq_file *m, void *unused) |
3068 | { | |
36cdd013 DW |
3069 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3070 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3071 | struct intel_crtc *crtc; |
53f5e3ca | 3072 | struct drm_connector *connector; |
3f6a5e1e | 3073 | struct drm_connector_list_iter conn_iter; |
53f5e3ca | 3074 | |
b0e5ddf3 | 3075 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3076 | seq_printf(m, "CRTC info\n"); |
3077 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3078 | for_each_intel_crtc(dev, crtc) { |
f77076c9 | 3079 | struct intel_crtc_state *pipe_config; |
53f5e3ca | 3080 | |
3f6a5e1e | 3081 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 ML |
3082 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3083 | ||
3abc4e09 | 3084 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3085 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3086 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3087 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3088 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3089 | ||
f77076c9 | 3090 | if (pipe_config->base.active) { |
cd5dcbf1 VS |
3091 | struct intel_plane *cursor = |
3092 | to_intel_plane(crtc->base.cursor); | |
3093 | ||
065f2ec2 CW |
3094 | intel_crtc_info(m, crtc); |
3095 | ||
cd5dcbf1 VS |
3096 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n", |
3097 | yesno(cursor->base.state->visible), | |
3098 | cursor->base.state->crtc_x, | |
3099 | cursor->base.state->crtc_y, | |
3100 | cursor->base.state->crtc_w, | |
3101 | cursor->base.state->crtc_h, | |
3102 | cursor->cursor.base); | |
3abc4e09 RF |
3103 | intel_scaler_info(m, crtc); |
3104 | intel_plane_info(m, crtc); | |
a23dc658 | 3105 | } |
cace841c DV |
3106 | |
3107 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3108 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3109 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
3f6a5e1e | 3110 | drm_modeset_unlock(&crtc->base.mutex); |
53f5e3ca JB |
3111 | } |
3112 | ||
3113 | seq_printf(m, "\n"); | |
3114 | seq_printf(m, "Connector info\n"); | |
3115 | seq_printf(m, "--------------\n"); | |
3f6a5e1e DV |
3116 | mutex_lock(&dev->mode_config.mutex); |
3117 | drm_connector_list_iter_begin(dev, &conn_iter); | |
3118 | drm_for_each_connector_iter(connector, &conn_iter) | |
53f5e3ca | 3119 | intel_connector_info(m, connector); |
3f6a5e1e DV |
3120 | drm_connector_list_iter_end(&conn_iter); |
3121 | mutex_unlock(&dev->mode_config.mutex); | |
3122 | ||
b0e5ddf3 | 3123 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3124 | |
3125 | return 0; | |
3126 | } | |
3127 | ||
1b36595f CW |
3128 | static int i915_engine_info(struct seq_file *m, void *unused) |
3129 | { | |
3130 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3131 | struct intel_engine_cs *engine; | |
3b3f1650 | 3132 | enum intel_engine_id id; |
f636edb2 | 3133 | struct drm_printer p; |
1b36595f | 3134 | |
9c870d03 CW |
3135 | intel_runtime_pm_get(dev_priv); |
3136 | ||
6f56103d CW |
3137 | seq_printf(m, "GT awake? %s (epoch %u)\n", |
3138 | yesno(dev_priv->gt.awake), dev_priv->gt.epoch); | |
f73b5674 CW |
3139 | seq_printf(m, "Global active requests: %d\n", |
3140 | dev_priv->gt.active_requests); | |
f577a03b LL |
3141 | seq_printf(m, "CS timestamp frequency: %u kHz\n", |
3142 | dev_priv->info.cs_timestamp_frequency_khz); | |
f73b5674 | 3143 | |
f636edb2 CW |
3144 | p = drm_seq_file_printer(m); |
3145 | for_each_engine(engine, dev_priv, id) | |
0db18b17 | 3146 | intel_engine_dump(engine, &p, "%s\n", engine->name); |
1b36595f | 3147 | |
9c870d03 CW |
3148 | intel_runtime_pm_put(dev_priv); |
3149 | ||
1b36595f CW |
3150 | return 0; |
3151 | } | |
3152 | ||
c5418a8b CW |
3153 | static int i915_shrinker_info(struct seq_file *m, void *unused) |
3154 | { | |
3155 | struct drm_i915_private *i915 = node_to_i915(m->private); | |
3156 | ||
3157 | seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks); | |
3158 | seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch); | |
3159 | ||
3160 | return 0; | |
3161 | } | |
3162 | ||
728e29d7 DV |
3163 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3164 | { | |
36cdd013 DW |
3165 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3166 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3167 | int i; |
3168 | ||
3169 | drm_modeset_lock_all(dev); | |
3170 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3171 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3172 | ||
3173 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3174 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3175 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3176 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3177 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3178 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3179 | pll->state.hw_state.dpll_md); |
3180 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3181 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3182 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3183 | } |
3184 | drm_modeset_unlock_all(dev); | |
3185 | ||
3186 | return 0; | |
3187 | } | |
3188 | ||
1ed1ef9d | 3189 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3190 | { |
3191 | int i; | |
3192 | int ret; | |
e2f80391 | 3193 | struct intel_engine_cs *engine; |
36cdd013 DW |
3194 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3195 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3196 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3197 | enum intel_engine_id id; |
888b5995 | 3198 | |
888b5995 AS |
3199 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3200 | if (ret) | |
3201 | return ret; | |
3202 | ||
3203 | intel_runtime_pm_get(dev_priv); | |
3204 | ||
33136b06 | 3205 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3206 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3207 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3208 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3209 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3210 | i915_reg_t addr; |
3211 | u32 mask, value, read; | |
2fa60f6d | 3212 | bool ok; |
888b5995 | 3213 | |
33136b06 AS |
3214 | addr = workarounds->reg[i].addr; |
3215 | mask = workarounds->reg[i].mask; | |
3216 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3217 | read = I915_READ(addr); |
3218 | ok = (value & mask) == (read & mask); | |
3219 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3220 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3221 | } |
3222 | ||
3223 | intel_runtime_pm_put(dev_priv); | |
3224 | mutex_unlock(&dev->struct_mutex); | |
3225 | ||
3226 | return 0; | |
3227 | } | |
3228 | ||
d2d4f39b KM |
3229 | static int i915_ipc_status_show(struct seq_file *m, void *data) |
3230 | { | |
3231 | struct drm_i915_private *dev_priv = m->private; | |
3232 | ||
3233 | seq_printf(m, "Isochronous Priority Control: %s\n", | |
3234 | yesno(dev_priv->ipc_enabled)); | |
3235 | return 0; | |
3236 | } | |
3237 | ||
3238 | static int i915_ipc_status_open(struct inode *inode, struct file *file) | |
3239 | { | |
3240 | struct drm_i915_private *dev_priv = inode->i_private; | |
3241 | ||
3242 | if (!HAS_IPC(dev_priv)) | |
3243 | return -ENODEV; | |
3244 | ||
3245 | return single_open(file, i915_ipc_status_show, dev_priv); | |
3246 | } | |
3247 | ||
3248 | static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, | |
3249 | size_t len, loff_t *offp) | |
3250 | { | |
3251 | struct seq_file *m = file->private_data; | |
3252 | struct drm_i915_private *dev_priv = m->private; | |
3253 | int ret; | |
3254 | bool enable; | |
3255 | ||
3256 | ret = kstrtobool_from_user(ubuf, len, &enable); | |
3257 | if (ret < 0) | |
3258 | return ret; | |
3259 | ||
3260 | intel_runtime_pm_get(dev_priv); | |
3261 | if (!dev_priv->ipc_enabled && enable) | |
3262 | DRM_INFO("Enabling IPC: WM will be proper only after next commit\n"); | |
3263 | dev_priv->wm.distrust_bios_wm = true; | |
3264 | dev_priv->ipc_enabled = enable; | |
3265 | intel_enable_ipc(dev_priv); | |
3266 | intel_runtime_pm_put(dev_priv); | |
3267 | ||
3268 | return len; | |
3269 | } | |
3270 | ||
3271 | static const struct file_operations i915_ipc_status_fops = { | |
3272 | .owner = THIS_MODULE, | |
3273 | .open = i915_ipc_status_open, | |
3274 | .read = seq_read, | |
3275 | .llseek = seq_lseek, | |
3276 | .release = single_release, | |
3277 | .write = i915_ipc_status_write | |
3278 | }; | |
3279 | ||
c5511e44 DL |
3280 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3281 | { | |
36cdd013 DW |
3282 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3283 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3284 | struct skl_ddb_allocation *ddb; |
3285 | struct skl_ddb_entry *entry; | |
3286 | enum pipe pipe; | |
3287 | int plane; | |
3288 | ||
36cdd013 | 3289 | if (INTEL_GEN(dev_priv) < 9) |
ab309a6a | 3290 | return -ENODEV; |
2fcffe19 | 3291 | |
c5511e44 DL |
3292 | drm_modeset_lock_all(dev); |
3293 | ||
3294 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3295 | ||
3296 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3297 | ||
3298 | for_each_pipe(dev_priv, pipe) { | |
3299 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3300 | ||
8b364b41 | 3301 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3302 | entry = &ddb->plane[pipe][plane]; |
3303 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3304 | entry->start, entry->end, | |
3305 | skl_ddb_entry_size(entry)); | |
3306 | } | |
3307 | ||
4969d33e | 3308 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3309 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3310 | entry->end, skl_ddb_entry_size(entry)); | |
3311 | } | |
3312 | ||
3313 | drm_modeset_unlock_all(dev); | |
3314 | ||
3315 | return 0; | |
3316 | } | |
3317 | ||
a54746e3 | 3318 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3319 | struct drm_device *dev, |
3320 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3321 | { |
fac5e23e | 3322 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3323 | struct i915_drrs *drrs = &dev_priv->drrs; |
3324 | int vrefresh = 0; | |
26875fe5 | 3325 | struct drm_connector *connector; |
3f6a5e1e | 3326 | struct drm_connector_list_iter conn_iter; |
a54746e3 | 3327 | |
3f6a5e1e DV |
3328 | drm_connector_list_iter_begin(dev, &conn_iter); |
3329 | drm_for_each_connector_iter(connector, &conn_iter) { | |
26875fe5 ML |
3330 | if (connector->state->crtc != &intel_crtc->base) |
3331 | continue; | |
3332 | ||
3333 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 | 3334 | } |
3f6a5e1e | 3335 | drm_connector_list_iter_end(&conn_iter); |
a54746e3 VK |
3336 | |
3337 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3338 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3339 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3340 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3341 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3342 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3343 | else | |
3344 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3345 | ||
3346 | seq_puts(m, "\n\n"); | |
3347 | ||
f77076c9 | 3348 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3349 | struct intel_panel *panel; |
3350 | ||
3351 | mutex_lock(&drrs->mutex); | |
3352 | /* DRRS Supported */ | |
3353 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3354 | ||
3355 | /* disable_drrs() will make drrs->dp NULL */ | |
3356 | if (!drrs->dp) { | |
ce6e2137 R |
3357 | seq_puts(m, "Idleness DRRS: Disabled\n"); |
3358 | if (dev_priv->psr.enabled) | |
3359 | seq_puts(m, | |
3360 | "\tAs PSR is enabled, DRRS is not enabled\n"); | |
a54746e3 VK |
3361 | mutex_unlock(&drrs->mutex); |
3362 | return; | |
3363 | } | |
3364 | ||
3365 | panel = &drrs->dp->attached_connector->panel; | |
3366 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3367 | drrs->busy_frontbuffer_bits); | |
3368 | ||
3369 | seq_puts(m, "\n\t\t"); | |
3370 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3371 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3372 | vrefresh = panel->fixed_mode->vrefresh; | |
3373 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3374 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3375 | vrefresh = panel->downclock_mode->vrefresh; | |
3376 | } else { | |
3377 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3378 | drrs->refresh_rate_type); | |
3379 | mutex_unlock(&drrs->mutex); | |
3380 | return; | |
3381 | } | |
3382 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3383 | ||
3384 | seq_puts(m, "\n\t\t"); | |
3385 | mutex_unlock(&drrs->mutex); | |
3386 | } else { | |
3387 | /* DRRS not supported. Print the VBT parameter*/ | |
3388 | seq_puts(m, "\tDRRS Supported : No"); | |
3389 | } | |
3390 | seq_puts(m, "\n"); | |
3391 | } | |
3392 | ||
3393 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3394 | { | |
36cdd013 DW |
3395 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3396 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3397 | struct intel_crtc *intel_crtc; |
3398 | int active_crtc_cnt = 0; | |
3399 | ||
26875fe5 | 3400 | drm_modeset_lock_all(dev); |
a54746e3 | 3401 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3402 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3403 | active_crtc_cnt++; |
3404 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3405 | ||
3406 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3407 | } | |
a54746e3 | 3408 | } |
26875fe5 | 3409 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3410 | |
3411 | if (!active_crtc_cnt) | |
3412 | seq_puts(m, "No active crtc found\n"); | |
3413 | ||
3414 | return 0; | |
3415 | } | |
3416 | ||
11bed958 DA |
3417 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3418 | { | |
36cdd013 DW |
3419 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3420 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3421 | struct intel_encoder *intel_encoder; |
3422 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b | 3423 | struct drm_connector *connector; |
3f6a5e1e | 3424 | struct drm_connector_list_iter conn_iter; |
b6dabe3b | 3425 | |
3f6a5e1e DV |
3426 | drm_connector_list_iter_begin(dev, &conn_iter); |
3427 | drm_for_each_connector_iter(connector, &conn_iter) { | |
b6dabe3b | 3428 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
11bed958 | 3429 | continue; |
b6dabe3b ML |
3430 | |
3431 | intel_encoder = intel_attached_encoder(connector); | |
3432 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3433 | continue; | |
3434 | ||
3435 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3436 | if (!intel_dig_port->dp.can_mst) |
3437 | continue; | |
b6dabe3b | 3438 | |
40ae80cc | 3439 | seq_printf(m, "MST Source Port %c\n", |
8f4f2797 | 3440 | port_name(intel_dig_port->base.port)); |
11bed958 DA |
3441 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3442 | } | |
3f6a5e1e DV |
3443 | drm_connector_list_iter_end(&conn_iter); |
3444 | ||
11bed958 DA |
3445 | return 0; |
3446 | } | |
3447 | ||
eb3394fa | 3448 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3449 | const char __user *ubuf, |
3450 | size_t len, loff_t *offp) | |
eb3394fa TP |
3451 | { |
3452 | char *input_buffer; | |
3453 | int status = 0; | |
eb3394fa TP |
3454 | struct drm_device *dev; |
3455 | struct drm_connector *connector; | |
3f6a5e1e | 3456 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3457 | struct intel_dp *intel_dp; |
3458 | int val = 0; | |
3459 | ||
9aaffa34 | 3460 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3461 | |
eb3394fa TP |
3462 | if (len == 0) |
3463 | return 0; | |
3464 | ||
261aeba8 GT |
3465 | input_buffer = memdup_user_nul(ubuf, len); |
3466 | if (IS_ERR(input_buffer)) | |
3467 | return PTR_ERR(input_buffer); | |
eb3394fa | 3468 | |
eb3394fa TP |
3469 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); |
3470 | ||
3f6a5e1e DV |
3471 | drm_connector_list_iter_begin(dev, &conn_iter); |
3472 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3473 | struct intel_encoder *encoder; |
3474 | ||
eb3394fa TP |
3475 | if (connector->connector_type != |
3476 | DRM_MODE_CONNECTOR_DisplayPort) | |
3477 | continue; | |
3478 | ||
a874b6a3 ML |
3479 | encoder = to_intel_encoder(connector->encoder); |
3480 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3481 | continue; | |
3482 | ||
3483 | if (encoder && connector->status == connector_status_connected) { | |
3484 | intel_dp = enc_to_intel_dp(&encoder->base); | |
eb3394fa TP |
3485 | status = kstrtoint(input_buffer, 10, &val); |
3486 | if (status < 0) | |
3f6a5e1e | 3487 | break; |
eb3394fa TP |
3488 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); |
3489 | /* To prevent erroneous activation of the compliance | |
3490 | * testing code, only accept an actual value of 1 here | |
3491 | */ | |
3492 | if (val == 1) | |
c1617abc | 3493 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3494 | else |
c1617abc | 3495 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3496 | } |
3497 | } | |
3f6a5e1e | 3498 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3499 | kfree(input_buffer); |
3500 | if (status < 0) | |
3501 | return status; | |
3502 | ||
3503 | *offp += len; | |
3504 | return len; | |
3505 | } | |
3506 | ||
3507 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3508 | { | |
3509 | struct drm_device *dev = m->private; | |
3510 | struct drm_connector *connector; | |
3f6a5e1e | 3511 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3512 | struct intel_dp *intel_dp; |
3513 | ||
3f6a5e1e DV |
3514 | drm_connector_list_iter_begin(dev, &conn_iter); |
3515 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3516 | struct intel_encoder *encoder; |
3517 | ||
eb3394fa TP |
3518 | if (connector->connector_type != |
3519 | DRM_MODE_CONNECTOR_DisplayPort) | |
3520 | continue; | |
3521 | ||
a874b6a3 ML |
3522 | encoder = to_intel_encoder(connector->encoder); |
3523 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3524 | continue; | |
3525 | ||
3526 | if (encoder && connector->status == connector_status_connected) { | |
3527 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3528 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3529 | seq_puts(m, "1"); |
3530 | else | |
3531 | seq_puts(m, "0"); | |
3532 | } else | |
3533 | seq_puts(m, "0"); | |
3534 | } | |
3f6a5e1e | 3535 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3536 | |
3537 | return 0; | |
3538 | } | |
3539 | ||
3540 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3541 | struct file *file) |
eb3394fa | 3542 | { |
36cdd013 | 3543 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3544 | |
36cdd013 DW |
3545 | return single_open(file, i915_displayport_test_active_show, |
3546 | &dev_priv->drm); | |
eb3394fa TP |
3547 | } |
3548 | ||
3549 | static const struct file_operations i915_displayport_test_active_fops = { | |
3550 | .owner = THIS_MODULE, | |
3551 | .open = i915_displayport_test_active_open, | |
3552 | .read = seq_read, | |
3553 | .llseek = seq_lseek, | |
3554 | .release = single_release, | |
3555 | .write = i915_displayport_test_active_write | |
3556 | }; | |
3557 | ||
3558 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3559 | { | |
3560 | struct drm_device *dev = m->private; | |
3561 | struct drm_connector *connector; | |
3f6a5e1e | 3562 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3563 | struct intel_dp *intel_dp; |
3564 | ||
3f6a5e1e DV |
3565 | drm_connector_list_iter_begin(dev, &conn_iter); |
3566 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3567 | struct intel_encoder *encoder; |
3568 | ||
eb3394fa TP |
3569 | if (connector->connector_type != |
3570 | DRM_MODE_CONNECTOR_DisplayPort) | |
3571 | continue; | |
3572 | ||
a874b6a3 ML |
3573 | encoder = to_intel_encoder(connector->encoder); |
3574 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3575 | continue; | |
3576 | ||
3577 | if (encoder && connector->status == connector_status_connected) { | |
3578 | intel_dp = enc_to_intel_dp(&encoder->base); | |
b48a5ba9 MN |
3579 | if (intel_dp->compliance.test_type == |
3580 | DP_TEST_LINK_EDID_READ) | |
3581 | seq_printf(m, "%lx", | |
3582 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3583 | else if (intel_dp->compliance.test_type == |
3584 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3585 | seq_printf(m, "hdisplay: %d\n", | |
3586 | intel_dp->compliance.test_data.hdisplay); | |
3587 | seq_printf(m, "vdisplay: %d\n", | |
3588 | intel_dp->compliance.test_data.vdisplay); | |
3589 | seq_printf(m, "bpc: %u\n", | |
3590 | intel_dp->compliance.test_data.bpc); | |
3591 | } | |
eb3394fa TP |
3592 | } else |
3593 | seq_puts(m, "0"); | |
3594 | } | |
3f6a5e1e | 3595 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3596 | |
3597 | return 0; | |
3598 | } | |
3599 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3600 | struct file *file) |
eb3394fa | 3601 | { |
36cdd013 | 3602 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3603 | |
36cdd013 DW |
3604 | return single_open(file, i915_displayport_test_data_show, |
3605 | &dev_priv->drm); | |
eb3394fa TP |
3606 | } |
3607 | ||
3608 | static const struct file_operations i915_displayport_test_data_fops = { | |
3609 | .owner = THIS_MODULE, | |
3610 | .open = i915_displayport_test_data_open, | |
3611 | .read = seq_read, | |
3612 | .llseek = seq_lseek, | |
3613 | .release = single_release | |
3614 | }; | |
3615 | ||
3616 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3617 | { | |
3618 | struct drm_device *dev = m->private; | |
3619 | struct drm_connector *connector; | |
3f6a5e1e | 3620 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3621 | struct intel_dp *intel_dp; |
3622 | ||
3f6a5e1e DV |
3623 | drm_connector_list_iter_begin(dev, &conn_iter); |
3624 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3625 | struct intel_encoder *encoder; |
3626 | ||
eb3394fa TP |
3627 | if (connector->connector_type != |
3628 | DRM_MODE_CONNECTOR_DisplayPort) | |
3629 | continue; | |
3630 | ||
a874b6a3 ML |
3631 | encoder = to_intel_encoder(connector->encoder); |
3632 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3633 | continue; | |
3634 | ||
3635 | if (encoder && connector->status == connector_status_connected) { | |
3636 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3637 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3638 | } else |
3639 | seq_puts(m, "0"); | |
3640 | } | |
3f6a5e1e | 3641 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3642 | |
3643 | return 0; | |
3644 | } | |
3645 | ||
3646 | static int i915_displayport_test_type_open(struct inode *inode, | |
3647 | struct file *file) | |
3648 | { | |
36cdd013 | 3649 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3650 | |
36cdd013 DW |
3651 | return single_open(file, i915_displayport_test_type_show, |
3652 | &dev_priv->drm); | |
eb3394fa TP |
3653 | } |
3654 | ||
3655 | static const struct file_operations i915_displayport_test_type_fops = { | |
3656 | .owner = THIS_MODULE, | |
3657 | .open = i915_displayport_test_type_open, | |
3658 | .read = seq_read, | |
3659 | .llseek = seq_lseek, | |
3660 | .release = single_release | |
3661 | }; | |
3662 | ||
97e94b22 | 3663 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3664 | { |
36cdd013 DW |
3665 | struct drm_i915_private *dev_priv = m->private; |
3666 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3667 | int level; |
de38b95c VS |
3668 | int num_levels; |
3669 | ||
36cdd013 | 3670 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3671 | num_levels = 3; |
36cdd013 | 3672 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 3673 | num_levels = 1; |
04548cba VS |
3674 | else if (IS_G4X(dev_priv)) |
3675 | num_levels = 3; | |
de38b95c | 3676 | else |
5db94019 | 3677 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3678 | |
3679 | drm_modeset_lock_all(dev); | |
3680 | ||
3681 | for (level = 0; level < num_levels; level++) { | |
3682 | unsigned int latency = wm[level]; | |
3683 | ||
97e94b22 DL |
3684 | /* |
3685 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3686 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3687 | */ |
04548cba VS |
3688 | if (INTEL_GEN(dev_priv) >= 9 || |
3689 | IS_VALLEYVIEW(dev_priv) || | |
3690 | IS_CHERRYVIEW(dev_priv) || | |
3691 | IS_G4X(dev_priv)) | |
97e94b22 DL |
3692 | latency *= 10; |
3693 | else if (level > 0) | |
369a1342 VS |
3694 | latency *= 5; |
3695 | ||
3696 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3697 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3698 | } |
3699 | ||
3700 | drm_modeset_unlock_all(dev); | |
3701 | } | |
3702 | ||
3703 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3704 | { | |
36cdd013 | 3705 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3706 | const uint16_t *latencies; |
3707 | ||
36cdd013 | 3708 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3709 | latencies = dev_priv->wm.skl_latency; |
3710 | else | |
36cdd013 | 3711 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3712 | |
97e94b22 | 3713 | wm_latency_show(m, latencies); |
369a1342 VS |
3714 | |
3715 | return 0; | |
3716 | } | |
3717 | ||
3718 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3719 | { | |
36cdd013 | 3720 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3721 | const uint16_t *latencies; |
3722 | ||
36cdd013 | 3723 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3724 | latencies = dev_priv->wm.skl_latency; |
3725 | else | |
36cdd013 | 3726 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3727 | |
97e94b22 | 3728 | wm_latency_show(m, latencies); |
369a1342 VS |
3729 | |
3730 | return 0; | |
3731 | } | |
3732 | ||
3733 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3734 | { | |
36cdd013 | 3735 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3736 | const uint16_t *latencies; |
3737 | ||
36cdd013 | 3738 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3739 | latencies = dev_priv->wm.skl_latency; |
3740 | else | |
36cdd013 | 3741 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3742 | |
97e94b22 | 3743 | wm_latency_show(m, latencies); |
369a1342 VS |
3744 | |
3745 | return 0; | |
3746 | } | |
3747 | ||
3748 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3749 | { | |
36cdd013 | 3750 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3751 | |
04548cba | 3752 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
369a1342 VS |
3753 | return -ENODEV; |
3754 | ||
36cdd013 | 3755 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3756 | } |
3757 | ||
3758 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3759 | { | |
36cdd013 | 3760 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3761 | |
36cdd013 | 3762 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3763 | return -ENODEV; |
3764 | ||
36cdd013 | 3765 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3766 | } |
3767 | ||
3768 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3769 | { | |
36cdd013 | 3770 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3771 | |
36cdd013 | 3772 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3773 | return -ENODEV; |
3774 | ||
36cdd013 | 3775 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3776 | } |
3777 | ||
3778 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3779 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3780 | { |
3781 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
3782 | struct drm_i915_private *dev_priv = m->private; |
3783 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 3784 | uint16_t new[8] = { 0 }; |
de38b95c | 3785 | int num_levels; |
369a1342 VS |
3786 | int level; |
3787 | int ret; | |
3788 | char tmp[32]; | |
3789 | ||
36cdd013 | 3790 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3791 | num_levels = 3; |
36cdd013 | 3792 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 3793 | num_levels = 1; |
04548cba VS |
3794 | else if (IS_G4X(dev_priv)) |
3795 | num_levels = 3; | |
de38b95c | 3796 | else |
5db94019 | 3797 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 3798 | |
369a1342 VS |
3799 | if (len >= sizeof(tmp)) |
3800 | return -EINVAL; | |
3801 | ||
3802 | if (copy_from_user(tmp, ubuf, len)) | |
3803 | return -EFAULT; | |
3804 | ||
3805 | tmp[len] = '\0'; | |
3806 | ||
97e94b22 DL |
3807 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
3808 | &new[0], &new[1], &new[2], &new[3], | |
3809 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
3810 | if (ret != num_levels) |
3811 | return -EINVAL; | |
3812 | ||
3813 | drm_modeset_lock_all(dev); | |
3814 | ||
3815 | for (level = 0; level < num_levels; level++) | |
3816 | wm[level] = new[level]; | |
3817 | ||
3818 | drm_modeset_unlock_all(dev); | |
3819 | ||
3820 | return len; | |
3821 | } | |
3822 | ||
3823 | ||
3824 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3825 | size_t len, loff_t *offp) | |
3826 | { | |
3827 | struct seq_file *m = file->private_data; | |
36cdd013 | 3828 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3829 | uint16_t *latencies; |
369a1342 | 3830 | |
36cdd013 | 3831 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3832 | latencies = dev_priv->wm.skl_latency; |
3833 | else | |
36cdd013 | 3834 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
3835 | |
3836 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3837 | } |
3838 | ||
3839 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3840 | size_t len, loff_t *offp) | |
3841 | { | |
3842 | struct seq_file *m = file->private_data; | |
36cdd013 | 3843 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3844 | uint16_t *latencies; |
369a1342 | 3845 | |
36cdd013 | 3846 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3847 | latencies = dev_priv->wm.skl_latency; |
3848 | else | |
36cdd013 | 3849 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
3850 | |
3851 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3852 | } |
3853 | ||
3854 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3855 | size_t len, loff_t *offp) | |
3856 | { | |
3857 | struct seq_file *m = file->private_data; | |
36cdd013 | 3858 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3859 | uint16_t *latencies; |
3860 | ||
36cdd013 | 3861 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3862 | latencies = dev_priv->wm.skl_latency; |
3863 | else | |
36cdd013 | 3864 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3865 | |
97e94b22 | 3866 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
3867 | } |
3868 | ||
3869 | static const struct file_operations i915_pri_wm_latency_fops = { | |
3870 | .owner = THIS_MODULE, | |
3871 | .open = pri_wm_latency_open, | |
3872 | .read = seq_read, | |
3873 | .llseek = seq_lseek, | |
3874 | .release = single_release, | |
3875 | .write = pri_wm_latency_write | |
3876 | }; | |
3877 | ||
3878 | static const struct file_operations i915_spr_wm_latency_fops = { | |
3879 | .owner = THIS_MODULE, | |
3880 | .open = spr_wm_latency_open, | |
3881 | .read = seq_read, | |
3882 | .llseek = seq_lseek, | |
3883 | .release = single_release, | |
3884 | .write = spr_wm_latency_write | |
3885 | }; | |
3886 | ||
3887 | static const struct file_operations i915_cur_wm_latency_fops = { | |
3888 | .owner = THIS_MODULE, | |
3889 | .open = cur_wm_latency_open, | |
3890 | .read = seq_read, | |
3891 | .llseek = seq_lseek, | |
3892 | .release = single_release, | |
3893 | .write = cur_wm_latency_write | |
3894 | }; | |
3895 | ||
647416f9 KC |
3896 | static int |
3897 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 3898 | { |
36cdd013 | 3899 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 3900 | |
d98c52cf | 3901 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 3902 | |
647416f9 | 3903 | return 0; |
f3cd474b CW |
3904 | } |
3905 | ||
647416f9 KC |
3906 | static int |
3907 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3908 | { |
598b6b5a CW |
3909 | struct drm_i915_private *i915 = data; |
3910 | struct intel_engine_cs *engine; | |
3911 | unsigned int tmp; | |
d46c0517 | 3912 | |
b8d24a06 MK |
3913 | /* |
3914 | * There is no safeguard against this debugfs entry colliding | |
3915 | * with the hangcheck calling same i915_handle_error() in | |
3916 | * parallel, causing an explosion. For now we assume that the | |
3917 | * test harness is responsible enough not to inject gpu hangs | |
3918 | * while it is writing to 'i915_wedged' | |
3919 | */ | |
3920 | ||
598b6b5a | 3921 | if (i915_reset_backoff(&i915->gpu_error)) |
b8d24a06 MK |
3922 | return -EAGAIN; |
3923 | ||
598b6b5a CW |
3924 | for_each_engine_masked(engine, i915, val, tmp) { |
3925 | engine->hangcheck.seqno = intel_engine_get_seqno(engine); | |
3926 | engine->hangcheck.stalled = true; | |
3927 | } | |
3928 | ||
3929 | i915_handle_error(i915, val, "Manually setting wedged to %llu", val); | |
d46c0517 | 3930 | |
598b6b5a | 3931 | wait_on_bit(&i915->gpu_error.flags, |
d3df42b7 CW |
3932 | I915_RESET_HANDOFF, |
3933 | TASK_UNINTERRUPTIBLE); | |
3934 | ||
647416f9 | 3935 | return 0; |
f3cd474b CW |
3936 | } |
3937 | ||
647416f9 KC |
3938 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
3939 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 3940 | "%llu\n"); |
f3cd474b | 3941 | |
64486ae7 CW |
3942 | static int |
3943 | fault_irq_set(struct drm_i915_private *i915, | |
3944 | unsigned long *irq, | |
3945 | unsigned long val) | |
3946 | { | |
3947 | int err; | |
3948 | ||
3949 | err = mutex_lock_interruptible(&i915->drm.struct_mutex); | |
3950 | if (err) | |
3951 | return err; | |
3952 | ||
3953 | err = i915_gem_wait_for_idle(i915, | |
3954 | I915_WAIT_LOCKED | | |
3955 | I915_WAIT_INTERRUPTIBLE); | |
3956 | if (err) | |
3957 | goto err_unlock; | |
3958 | ||
64486ae7 CW |
3959 | *irq = val; |
3960 | mutex_unlock(&i915->drm.struct_mutex); | |
3961 | ||
3962 | /* Flush idle worker to disarm irq */ | |
7c26240e | 3963 | drain_delayed_work(&i915->gt.idle_work); |
64486ae7 CW |
3964 | |
3965 | return 0; | |
3966 | ||
3967 | err_unlock: | |
3968 | mutex_unlock(&i915->drm.struct_mutex); | |
3969 | return err; | |
3970 | } | |
3971 | ||
094f9a54 CW |
3972 | static int |
3973 | i915_ring_missed_irq_get(void *data, u64 *val) | |
3974 | { | |
36cdd013 | 3975 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
3976 | |
3977 | *val = dev_priv->gpu_error.missed_irq_rings; | |
3978 | return 0; | |
3979 | } | |
3980 | ||
3981 | static int | |
3982 | i915_ring_missed_irq_set(void *data, u64 val) | |
3983 | { | |
64486ae7 | 3984 | struct drm_i915_private *i915 = data; |
094f9a54 | 3985 | |
64486ae7 | 3986 | return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val); |
094f9a54 CW |
3987 | } |
3988 | ||
3989 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
3990 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
3991 | "0x%08llx\n"); | |
3992 | ||
3993 | static int | |
3994 | i915_ring_test_irq_get(void *data, u64 *val) | |
3995 | { | |
36cdd013 | 3996 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
3997 | |
3998 | *val = dev_priv->gpu_error.test_irq_rings; | |
3999 | ||
4000 | return 0; | |
4001 | } | |
4002 | ||
4003 | static int | |
4004 | i915_ring_test_irq_set(void *data, u64 val) | |
4005 | { | |
64486ae7 | 4006 | struct drm_i915_private *i915 = data; |
094f9a54 | 4007 | |
64486ae7 | 4008 | val &= INTEL_INFO(i915)->ring_mask; |
094f9a54 | 4009 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4010 | |
64486ae7 | 4011 | return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val); |
094f9a54 CW |
4012 | } |
4013 | ||
4014 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4015 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4016 | "0x%08llx\n"); | |
4017 | ||
b4a0b32d CW |
4018 | #define DROP_UNBOUND BIT(0) |
4019 | #define DROP_BOUND BIT(1) | |
4020 | #define DROP_RETIRE BIT(2) | |
4021 | #define DROP_ACTIVE BIT(3) | |
4022 | #define DROP_FREED BIT(4) | |
4023 | #define DROP_SHRINK_ALL BIT(5) | |
4024 | #define DROP_IDLE BIT(6) | |
fbbd37b3 CW |
4025 | #define DROP_ALL (DROP_UNBOUND | \ |
4026 | DROP_BOUND | \ | |
4027 | DROP_RETIRE | \ | |
4028 | DROP_ACTIVE | \ | |
8eadc19b | 4029 | DROP_FREED | \ |
b4a0b32d CW |
4030 | DROP_SHRINK_ALL |\ |
4031 | DROP_IDLE) | |
647416f9 KC |
4032 | static int |
4033 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4034 | { |
647416f9 | 4035 | *val = DROP_ALL; |
dd624afd | 4036 | |
647416f9 | 4037 | return 0; |
dd624afd CW |
4038 | } |
4039 | ||
647416f9 KC |
4040 | static int |
4041 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4042 | { |
36cdd013 DW |
4043 | struct drm_i915_private *dev_priv = data; |
4044 | struct drm_device *dev = &dev_priv->drm; | |
00c26cf9 | 4045 | int ret = 0; |
dd624afd | 4046 | |
b4a0b32d CW |
4047 | DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n", |
4048 | val, val & DROP_ALL); | |
dd624afd CW |
4049 | |
4050 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4051 | * on ioctls on -EAGAIN. */ | |
00c26cf9 CW |
4052 | if (val & (DROP_ACTIVE | DROP_RETIRE)) { |
4053 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
dd624afd | 4054 | if (ret) |
00c26cf9 | 4055 | return ret; |
dd624afd | 4056 | |
00c26cf9 CW |
4057 | if (val & DROP_ACTIVE) |
4058 | ret = i915_gem_wait_for_idle(dev_priv, | |
4059 | I915_WAIT_INTERRUPTIBLE | | |
4060 | I915_WAIT_LOCKED); | |
4061 | ||
4062 | if (val & DROP_RETIRE) | |
4063 | i915_gem_retire_requests(dev_priv); | |
4064 | ||
4065 | mutex_unlock(&dev->struct_mutex); | |
4066 | } | |
dd624afd | 4067 | |
d92a8cfc | 4068 | fs_reclaim_acquire(GFP_KERNEL); |
21ab4e74 | 4069 | if (val & DROP_BOUND) |
912d572d | 4070 | i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND); |
4ad72b7f | 4071 | |
21ab4e74 | 4072 | if (val & DROP_UNBOUND) |
912d572d | 4073 | i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND); |
dd624afd | 4074 | |
8eadc19b CW |
4075 | if (val & DROP_SHRINK_ALL) |
4076 | i915_gem_shrink_all(dev_priv); | |
d92a8cfc | 4077 | fs_reclaim_release(GFP_KERNEL); |
8eadc19b | 4078 | |
b4a0b32d CW |
4079 | if (val & DROP_IDLE) |
4080 | drain_delayed_work(&dev_priv->gt.idle_work); | |
4081 | ||
c9c70471 | 4082 | if (val & DROP_FREED) |
bdeb9785 | 4083 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 | 4084 | |
647416f9 | 4085 | return ret; |
dd624afd CW |
4086 | } |
4087 | ||
647416f9 KC |
4088 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4089 | i915_drop_caches_get, i915_drop_caches_set, | |
4090 | "0x%08llx\n"); | |
dd624afd | 4091 | |
647416f9 KC |
4092 | static int |
4093 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4094 | { |
36cdd013 | 4095 | struct drm_i915_private *dev_priv = data; |
004777cb | 4096 | |
36cdd013 | 4097 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4098 | return -ENODEV; |
4099 | ||
562d9bae | 4100 | *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit); |
647416f9 | 4101 | return 0; |
358733e9 JB |
4102 | } |
4103 | ||
647416f9 KC |
4104 | static int |
4105 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4106 | { |
36cdd013 | 4107 | struct drm_i915_private *dev_priv = data; |
562d9bae | 4108 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
bc4d91f6 | 4109 | u32 hw_max, hw_min; |
647416f9 | 4110 | int ret; |
004777cb | 4111 | |
36cdd013 | 4112 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4113 | return -ENODEV; |
358733e9 | 4114 | |
647416f9 | 4115 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4116 | |
9f817501 | 4117 | ret = mutex_lock_interruptible(&dev_priv->pcu_lock); |
004777cb DV |
4118 | if (ret) |
4119 | return ret; | |
4120 | ||
358733e9 JB |
4121 | /* |
4122 | * Turbo will still be enabled, but won't go above the set value. | |
4123 | */ | |
bc4d91f6 | 4124 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4125 | |
562d9bae SAK |
4126 | hw_max = rps->max_freq; |
4127 | hw_min = rps->min_freq; | |
dd0a1aa1 | 4128 | |
562d9bae | 4129 | if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) { |
9f817501 | 4130 | mutex_unlock(&dev_priv->pcu_lock); |
dd0a1aa1 | 4131 | return -EINVAL; |
0a073b84 JB |
4132 | } |
4133 | ||
562d9bae | 4134 | rps->max_freq_softlimit = val; |
dd0a1aa1 | 4135 | |
9fcee2f7 CW |
4136 | if (intel_set_rps(dev_priv, val)) |
4137 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4138 | |
9f817501 | 4139 | mutex_unlock(&dev_priv->pcu_lock); |
358733e9 | 4140 | |
647416f9 | 4141 | return 0; |
358733e9 JB |
4142 | } |
4143 | ||
647416f9 KC |
4144 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4145 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4146 | "%llu\n"); |
358733e9 | 4147 | |
647416f9 KC |
4148 | static int |
4149 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4150 | { |
36cdd013 | 4151 | struct drm_i915_private *dev_priv = data; |
004777cb | 4152 | |
62e1baa1 | 4153 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4154 | return -ENODEV; |
4155 | ||
562d9bae | 4156 | *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit); |
647416f9 | 4157 | return 0; |
1523c310 JB |
4158 | } |
4159 | ||
647416f9 KC |
4160 | static int |
4161 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4162 | { |
36cdd013 | 4163 | struct drm_i915_private *dev_priv = data; |
562d9bae | 4164 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
bc4d91f6 | 4165 | u32 hw_max, hw_min; |
647416f9 | 4166 | int ret; |
004777cb | 4167 | |
62e1baa1 | 4168 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4169 | return -ENODEV; |
1523c310 | 4170 | |
647416f9 | 4171 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4172 | |
9f817501 | 4173 | ret = mutex_lock_interruptible(&dev_priv->pcu_lock); |
004777cb DV |
4174 | if (ret) |
4175 | return ret; | |
4176 | ||
1523c310 JB |
4177 | /* |
4178 | * Turbo will still be enabled, but won't go below the set value. | |
4179 | */ | |
bc4d91f6 | 4180 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4181 | |
562d9bae SAK |
4182 | hw_max = rps->max_freq; |
4183 | hw_min = rps->min_freq; | |
dd0a1aa1 | 4184 | |
36cdd013 | 4185 | if (val < hw_min || |
562d9bae | 4186 | val > hw_max || val > rps->max_freq_softlimit) { |
9f817501 | 4187 | mutex_unlock(&dev_priv->pcu_lock); |
dd0a1aa1 | 4188 | return -EINVAL; |
0a073b84 | 4189 | } |
dd0a1aa1 | 4190 | |
562d9bae | 4191 | rps->min_freq_softlimit = val; |
dd0a1aa1 | 4192 | |
9fcee2f7 CW |
4193 | if (intel_set_rps(dev_priv, val)) |
4194 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4195 | |
9f817501 | 4196 | mutex_unlock(&dev_priv->pcu_lock); |
1523c310 | 4197 | |
647416f9 | 4198 | return 0; |
1523c310 JB |
4199 | } |
4200 | ||
647416f9 KC |
4201 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4202 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4203 | "%llu\n"); |
1523c310 | 4204 | |
647416f9 KC |
4205 | static int |
4206 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4207 | { |
36cdd013 | 4208 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4209 | u32 snpcr; |
07b7ddd9 | 4210 | |
36cdd013 | 4211 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4212 | return -ENODEV; |
4213 | ||
c8c8fb33 | 4214 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4215 | |
07b7ddd9 | 4216 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4217 | |
4218 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4219 | |
647416f9 | 4220 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4221 | |
647416f9 | 4222 | return 0; |
07b7ddd9 JB |
4223 | } |
4224 | ||
647416f9 KC |
4225 | static int |
4226 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4227 | { |
36cdd013 | 4228 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4229 | u32 snpcr; |
07b7ddd9 | 4230 | |
36cdd013 | 4231 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4232 | return -ENODEV; |
4233 | ||
647416f9 | 4234 | if (val > 3) |
07b7ddd9 JB |
4235 | return -EINVAL; |
4236 | ||
c8c8fb33 | 4237 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4238 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4239 | |
4240 | /* Update the cache sharing policy here as well */ | |
4241 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4242 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4243 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4244 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4245 | ||
c8c8fb33 | 4246 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4247 | return 0; |
07b7ddd9 JB |
4248 | } |
4249 | ||
647416f9 KC |
4250 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4251 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4252 | "%llu\n"); | |
07b7ddd9 | 4253 | |
36cdd013 | 4254 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4255 | struct sseu_dev_info *sseu) |
5d39525a | 4256 | { |
0a0b457f | 4257 | int ss_max = 2; |
5d39525a JM |
4258 | int ss; |
4259 | u32 sig1[ss_max], sig2[ss_max]; | |
4260 | ||
4261 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4262 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4263 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4264 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4265 | ||
4266 | for (ss = 0; ss < ss_max; ss++) { | |
4267 | unsigned int eu_cnt; | |
4268 | ||
4269 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4270 | /* skip disabled subslice */ | |
4271 | continue; | |
4272 | ||
f08a0c92 | 4273 | sseu->slice_mask = BIT(0); |
57ec171e | 4274 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4275 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4276 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4277 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4278 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4279 | sseu->eu_total += eu_cnt; |
4280 | sseu->eu_per_subslice = max_t(unsigned int, | |
4281 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4282 | } |
5d39525a JM |
4283 | } |
4284 | ||
f8c3dcf9 RV |
4285 | static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, |
4286 | struct sseu_dev_info *sseu) | |
4287 | { | |
4288 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
4289 | int s_max = 6, ss_max = 4; | |
4290 | int s, ss; | |
4291 | u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2]; | |
4292 | ||
4293 | for (s = 0; s < s_max; s++) { | |
4294 | /* | |
4295 | * FIXME: Valid SS Mask respects the spec and read | |
4296 | * only valid bits for those registers, excluding reserverd | |
4297 | * although this seems wrong because it would leave many | |
4298 | * subslices without ACK. | |
4299 | */ | |
4300 | s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) & | |
4301 | GEN10_PGCTL_VALID_SS_MASK(s); | |
4302 | eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s)); | |
4303 | eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s)); | |
4304 | } | |
4305 | ||
4306 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | | |
4307 | GEN9_PGCTL_SSA_EU19_ACK | | |
4308 | GEN9_PGCTL_SSA_EU210_ACK | | |
4309 | GEN9_PGCTL_SSA_EU311_ACK; | |
4310 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4311 | GEN9_PGCTL_SSB_EU19_ACK | | |
4312 | GEN9_PGCTL_SSB_EU210_ACK | | |
4313 | GEN9_PGCTL_SSB_EU311_ACK; | |
4314 | ||
4315 | for (s = 0; s < s_max; s++) { | |
4316 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4317 | /* skip disabled slice */ | |
4318 | continue; | |
4319 | ||
4320 | sseu->slice_mask |= BIT(s); | |
4321 | sseu->subslice_mask = info->sseu.subslice_mask; | |
4322 | ||
4323 | for (ss = 0; ss < ss_max; ss++) { | |
4324 | unsigned int eu_cnt; | |
4325 | ||
4326 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
4327 | /* skip disabled subslice */ | |
4328 | continue; | |
4329 | ||
4330 | eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] & | |
4331 | eu_mask[ss % 2]); | |
4332 | sseu->eu_total += eu_cnt; | |
4333 | sseu->eu_per_subslice = max_t(unsigned int, | |
4334 | sseu->eu_per_subslice, | |
4335 | eu_cnt); | |
4336 | } | |
4337 | } | |
4338 | } | |
4339 | ||
36cdd013 | 4340 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4341 | struct sseu_dev_info *sseu) |
5d39525a | 4342 | { |
1c046bc1 | 4343 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4344 | int s, ss; |
4345 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4346 | ||
1c046bc1 | 4347 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4348 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4349 | s_max = 1; |
4350 | ss_max = 3; | |
4351 | } | |
4352 | ||
4353 | for (s = 0; s < s_max; s++) { | |
4354 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4355 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4356 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4357 | } | |
4358 | ||
5d39525a JM |
4359 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4360 | GEN9_PGCTL_SSA_EU19_ACK | | |
4361 | GEN9_PGCTL_SSA_EU210_ACK | | |
4362 | GEN9_PGCTL_SSA_EU311_ACK; | |
4363 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4364 | GEN9_PGCTL_SSB_EU19_ACK | | |
4365 | GEN9_PGCTL_SSB_EU210_ACK | | |
4366 | GEN9_PGCTL_SSB_EU311_ACK; | |
4367 | ||
4368 | for (s = 0; s < s_max; s++) { | |
4369 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4370 | /* skip disabled slice */ | |
4371 | continue; | |
4372 | ||
f08a0c92 | 4373 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4374 | |
f8c3dcf9 | 4375 | if (IS_GEN9_BC(dev_priv)) |
57ec171e ID |
4376 | sseu->subslice_mask = |
4377 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4378 | |
5d39525a JM |
4379 | for (ss = 0; ss < ss_max; ss++) { |
4380 | unsigned int eu_cnt; | |
4381 | ||
cc3f90f0 | 4382 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4383 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4384 | /* skip disabled subslice */ | |
4385 | continue; | |
1c046bc1 | 4386 | |
57ec171e ID |
4387 | sseu->subslice_mask |= BIT(ss); |
4388 | } | |
1c046bc1 | 4389 | |
5d39525a JM |
4390 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4391 | eu_mask[ss%2]); | |
915490d5 ID |
4392 | sseu->eu_total += eu_cnt; |
4393 | sseu->eu_per_subslice = max_t(unsigned int, | |
4394 | sseu->eu_per_subslice, | |
4395 | eu_cnt); | |
5d39525a JM |
4396 | } |
4397 | } | |
4398 | } | |
4399 | ||
36cdd013 | 4400 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4401 | struct sseu_dev_info *sseu) |
91bedd34 | 4402 | { |
91bedd34 | 4403 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4404 | int s; |
91bedd34 | 4405 | |
f08a0c92 | 4406 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4407 | |
f08a0c92 | 4408 | if (sseu->slice_mask) { |
57ec171e | 4409 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4410 | sseu->eu_per_subslice = |
4411 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4412 | sseu->eu_total = sseu->eu_per_subslice * |
4413 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4414 | |
4415 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4416 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4417 | u8 subslice_7eu = |
4418 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4419 | |
915490d5 | 4420 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4421 | } |
4422 | } | |
4423 | } | |
4424 | ||
615d8908 ID |
4425 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4426 | const struct sseu_dev_info *sseu) | |
4427 | { | |
4428 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4429 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4430 | ||
c67ba538 ID |
4431 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4432 | sseu->slice_mask); | |
615d8908 | 4433 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4434 | hweight8(sseu->slice_mask)); |
615d8908 | 4435 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4436 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4437 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4438 | sseu->subslice_mask); | |
615d8908 | 4439 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4440 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4441 | seq_printf(m, " %s EU Total: %u\n", type, |
4442 | sseu->eu_total); | |
4443 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4444 | sseu->eu_per_subslice); | |
4445 | ||
4446 | if (!is_available_info) | |
4447 | return; | |
4448 | ||
4449 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4450 | if (HAS_POOLED_EU(dev_priv)) | |
4451 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4452 | ||
4453 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4454 | yesno(sseu->has_slice_pg)); | |
4455 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4456 | yesno(sseu->has_subslice_pg)); | |
4457 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4458 | yesno(sseu->has_eu_pg)); | |
4459 | } | |
4460 | ||
3873218f JM |
4461 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4462 | { | |
36cdd013 | 4463 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4464 | struct sseu_dev_info sseu; |
3873218f | 4465 | |
36cdd013 | 4466 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4467 | return -ENODEV; |
4468 | ||
4469 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4470 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4471 | |
7f992aba | 4472 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4473 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4474 | |
4475 | intel_runtime_pm_get(dev_priv); | |
4476 | ||
36cdd013 | 4477 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4478 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4479 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4480 | broadwell_sseu_device_status(dev_priv, &sseu); |
f8c3dcf9 | 4481 | } else if (IS_GEN9(dev_priv)) { |
915490d5 | 4482 | gen9_sseu_device_status(dev_priv, &sseu); |
f8c3dcf9 RV |
4483 | } else if (INTEL_GEN(dev_priv) >= 10) { |
4484 | gen10_sseu_device_status(dev_priv, &sseu); | |
7f992aba | 4485 | } |
238010ed DW |
4486 | |
4487 | intel_runtime_pm_put(dev_priv); | |
4488 | ||
615d8908 | 4489 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4490 | |
3873218f JM |
4491 | return 0; |
4492 | } | |
4493 | ||
6d794d42 BW |
4494 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4495 | { | |
d7a133d8 | 4496 | struct drm_i915_private *i915 = inode->i_private; |
6d794d42 | 4497 | |
d7a133d8 | 4498 | if (INTEL_GEN(i915) < 6) |
6d794d42 BW |
4499 | return 0; |
4500 | ||
d7a133d8 CW |
4501 | intel_runtime_pm_get(i915); |
4502 | intel_uncore_forcewake_user_get(i915); | |
6d794d42 BW |
4503 | |
4504 | return 0; | |
4505 | } | |
4506 | ||
c43b5634 | 4507 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4508 | { |
d7a133d8 | 4509 | struct drm_i915_private *i915 = inode->i_private; |
6d794d42 | 4510 | |
d7a133d8 | 4511 | if (INTEL_GEN(i915) < 6) |
6d794d42 BW |
4512 | return 0; |
4513 | ||
d7a133d8 CW |
4514 | intel_uncore_forcewake_user_put(i915); |
4515 | intel_runtime_pm_put(i915); | |
6d794d42 BW |
4516 | |
4517 | return 0; | |
4518 | } | |
4519 | ||
4520 | static const struct file_operations i915_forcewake_fops = { | |
4521 | .owner = THIS_MODULE, | |
4522 | .open = i915_forcewake_open, | |
4523 | .release = i915_forcewake_release, | |
4524 | }; | |
4525 | ||
317eaa95 L |
4526 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4527 | { | |
4528 | struct drm_i915_private *dev_priv = m->private; | |
4529 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4530 | ||
4531 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4532 | seq_printf(m, "Detected: %s\n", | |
4533 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4534 | ||
4535 | return 0; | |
4536 | } | |
4537 | ||
4538 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4539 | const char __user *ubuf, size_t len, | |
4540 | loff_t *offp) | |
4541 | { | |
4542 | struct seq_file *m = file->private_data; | |
4543 | struct drm_i915_private *dev_priv = m->private; | |
4544 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4545 | unsigned int new_threshold; | |
4546 | int i; | |
4547 | char *newline; | |
4548 | char tmp[16]; | |
4549 | ||
4550 | if (len >= sizeof(tmp)) | |
4551 | return -EINVAL; | |
4552 | ||
4553 | if (copy_from_user(tmp, ubuf, len)) | |
4554 | return -EFAULT; | |
4555 | ||
4556 | tmp[len] = '\0'; | |
4557 | ||
4558 | /* Strip newline, if any */ | |
4559 | newline = strchr(tmp, '\n'); | |
4560 | if (newline) | |
4561 | *newline = '\0'; | |
4562 | ||
4563 | if (strcmp(tmp, "reset") == 0) | |
4564 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4565 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4566 | return -EINVAL; | |
4567 | ||
4568 | if (new_threshold > 0) | |
4569 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4570 | new_threshold); | |
4571 | else | |
4572 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4573 | ||
4574 | spin_lock_irq(&dev_priv->irq_lock); | |
4575 | hotplug->hpd_storm_threshold = new_threshold; | |
4576 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4577 | for_each_hpd_pin(i) | |
4578 | hotplug->stats[i].count = 0; | |
4579 | spin_unlock_irq(&dev_priv->irq_lock); | |
4580 | ||
4581 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4582 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4583 | ||
4584 | return len; | |
4585 | } | |
4586 | ||
4587 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4588 | { | |
4589 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4590 | } | |
4591 | ||
4592 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4593 | .owner = THIS_MODULE, | |
4594 | .open = i915_hpd_storm_ctl_open, | |
4595 | .read = seq_read, | |
4596 | .llseek = seq_lseek, | |
4597 | .release = single_release, | |
4598 | .write = i915_hpd_storm_ctl_write | |
4599 | }; | |
4600 | ||
35954e88 R |
4601 | static int i915_drrs_ctl_set(void *data, u64 val) |
4602 | { | |
4603 | struct drm_i915_private *dev_priv = data; | |
4604 | struct drm_device *dev = &dev_priv->drm; | |
4605 | struct intel_crtc *intel_crtc; | |
4606 | struct intel_encoder *encoder; | |
4607 | struct intel_dp *intel_dp; | |
4608 | ||
4609 | if (INTEL_GEN(dev_priv) < 7) | |
4610 | return -ENODEV; | |
4611 | ||
4612 | drm_modeset_lock_all(dev); | |
4613 | for_each_intel_crtc(dev, intel_crtc) { | |
4614 | if (!intel_crtc->base.state->active || | |
4615 | !intel_crtc->config->has_drrs) | |
4616 | continue; | |
4617 | ||
4618 | for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) { | |
4619 | if (encoder->type != INTEL_OUTPUT_EDP) | |
4620 | continue; | |
4621 | ||
4622 | DRM_DEBUG_DRIVER("Manually %sabling DRRS. %llu\n", | |
4623 | val ? "en" : "dis", val); | |
4624 | ||
4625 | intel_dp = enc_to_intel_dp(&encoder->base); | |
4626 | if (val) | |
4627 | intel_edp_drrs_enable(intel_dp, | |
4628 | intel_crtc->config); | |
4629 | else | |
4630 | intel_edp_drrs_disable(intel_dp, | |
4631 | intel_crtc->config); | |
4632 | } | |
4633 | } | |
4634 | drm_modeset_unlock_all(dev); | |
4635 | ||
4636 | return 0; | |
4637 | } | |
4638 | ||
4639 | DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n"); | |
4640 | ||
06c5bf8c | 4641 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4642 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4643 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4644 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6d2b8885 | 4645 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
a6172a80 | 4646 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4647 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4648 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4649 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4650 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4651 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
ac58d2ab | 4652 | {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1}, |
a8b9370f | 4653 | {"i915_guc_stage_pool", i915_guc_stage_pool, 0}, |
0509ead1 | 4654 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4655 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4656 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
061d06a2 | 4657 | {"i915_reset_info", i915_reset_info, 0}, |
f97108d1 | 4658 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4659 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4660 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4661 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4662 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4663 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4664 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4665 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4666 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4667 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4668 | {"i915_context_status", i915_context_status, 0}, |
f65367b5 | 4669 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4670 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4671 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4672 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4673 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4674 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4675 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4676 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4677 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4678 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4679 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4680 | {"i915_engine_info", i915_engine_info, 0}, |
c5418a8b | 4681 | {"i915_shrinker_info", i915_shrinker_info, 0}, |
728e29d7 | 4682 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4683 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4684 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4685 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4686 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4687 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4688 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4689 | }; |
27c202ad | 4690 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4691 | |
06c5bf8c | 4692 | static const struct i915_debugfs_files { |
34b9674c DV |
4693 | const char *name; |
4694 | const struct file_operations *fops; | |
4695 | } i915_debugfs_files[] = { | |
4696 | {"i915_wedged", &i915_wedged_fops}, | |
4697 | {"i915_max_freq", &i915_max_freq_fops}, | |
4698 | {"i915_min_freq", &i915_min_freq_fops}, | |
4699 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4700 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4701 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4702 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4703 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4704 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4705 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4706 | #endif |
34b9674c | 4707 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4708 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4709 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4710 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4711 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
4127dc43 | 4712 | {"i915_fbc_false_color", &i915_fbc_false_color_fops}, |
eb3394fa TP |
4713 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4714 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4715 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
317eaa95 | 4716 | {"i915_guc_log_control", &i915_guc_log_control_fops}, |
d2d4f39b | 4717 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, |
35954e88 R |
4718 | {"i915_ipc_status", &i915_ipc_status_fops}, |
4719 | {"i915_drrs_ctl", &i915_drrs_ctl_fops} | |
34b9674c DV |
4720 | }; |
4721 | ||
1dac891c | 4722 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4723 | { |
91c8a326 | 4724 | struct drm_minor *minor = dev_priv->drm.primary; |
b05eeb0f | 4725 | struct dentry *ent; |
34b9674c | 4726 | int ret, i; |
f3cd474b | 4727 | |
b05eeb0f NT |
4728 | ent = debugfs_create_file("i915_forcewake_user", S_IRUSR, |
4729 | minor->debugfs_root, to_i915(minor->dev), | |
4730 | &i915_forcewake_fops); | |
4731 | if (!ent) | |
4732 | return -ENOMEM; | |
6a9c308d | 4733 | |
731035fe TV |
4734 | ret = intel_pipe_crc_create(minor); |
4735 | if (ret) | |
4736 | return ret; | |
07144428 | 4737 | |
34b9674c | 4738 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
b05eeb0f NT |
4739 | ent = debugfs_create_file(i915_debugfs_files[i].name, |
4740 | S_IRUGO | S_IWUSR, | |
4741 | minor->debugfs_root, | |
4742 | to_i915(minor->dev), | |
34b9674c | 4743 | i915_debugfs_files[i].fops); |
b05eeb0f NT |
4744 | if (!ent) |
4745 | return -ENOMEM; | |
34b9674c | 4746 | } |
40633219 | 4747 | |
27c202ad BG |
4748 | return drm_debugfs_create_files(i915_debugfs_list, |
4749 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4750 | minor->debugfs_root, minor); |
4751 | } | |
4752 | ||
aa7471d2 JN |
4753 | struct dpcd_block { |
4754 | /* DPCD dump start address. */ | |
4755 | unsigned int offset; | |
4756 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4757 | unsigned int end; | |
4758 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4759 | size_t size; | |
4760 | /* Only valid for eDP. */ | |
4761 | bool edp; | |
4762 | }; | |
4763 | ||
4764 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4765 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4766 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4767 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4768 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4769 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4770 | { .offset = DP_SET_POWER }, | |
4771 | { .offset = DP_EDP_DPCD_REV }, | |
4772 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4773 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4774 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4775 | }; | |
4776 | ||
4777 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4778 | { | |
4779 | struct drm_connector *connector = m->private; | |
4780 | struct intel_dp *intel_dp = | |
4781 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4782 | uint8_t buf[16]; | |
4783 | ssize_t err; | |
4784 | int i; | |
4785 | ||
5c1a8875 MK |
4786 | if (connector->status != connector_status_connected) |
4787 | return -ENODEV; | |
4788 | ||
aa7471d2 JN |
4789 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4790 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4791 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4792 | ||
4793 | if (b->edp && | |
4794 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4795 | continue; | |
4796 | ||
4797 | /* low tech for now */ | |
4798 | if (WARN_ON(size > sizeof(buf))) | |
4799 | continue; | |
4800 | ||
4801 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4802 | if (err <= 0) { | |
4803 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4804 | size, b->offset, err); | |
4805 | continue; | |
4806 | } | |
4807 | ||
4808 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4809 | } |
aa7471d2 JN |
4810 | |
4811 | return 0; | |
4812 | } | |
4813 | ||
4814 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4815 | { | |
4816 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4817 | } | |
4818 | ||
4819 | static const struct file_operations i915_dpcd_fops = { | |
4820 | .owner = THIS_MODULE, | |
4821 | .open = i915_dpcd_open, | |
4822 | .read = seq_read, | |
4823 | .llseek = seq_lseek, | |
4824 | .release = single_release, | |
4825 | }; | |
4826 | ||
ecbd6781 DW |
4827 | static int i915_panel_show(struct seq_file *m, void *data) |
4828 | { | |
4829 | struct drm_connector *connector = m->private; | |
4830 | struct intel_dp *intel_dp = | |
4831 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4832 | ||
4833 | if (connector->status != connector_status_connected) | |
4834 | return -ENODEV; | |
4835 | ||
4836 | seq_printf(m, "Panel power up delay: %d\n", | |
4837 | intel_dp->panel_power_up_delay); | |
4838 | seq_printf(m, "Panel power down delay: %d\n", | |
4839 | intel_dp->panel_power_down_delay); | |
4840 | seq_printf(m, "Backlight on delay: %d\n", | |
4841 | intel_dp->backlight_on_delay); | |
4842 | seq_printf(m, "Backlight off delay: %d\n", | |
4843 | intel_dp->backlight_off_delay); | |
4844 | ||
4845 | return 0; | |
4846 | } | |
4847 | ||
4848 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4849 | { | |
4850 | return single_open(file, i915_panel_show, inode->i_private); | |
4851 | } | |
4852 | ||
4853 | static const struct file_operations i915_panel_fops = { | |
4854 | .owner = THIS_MODULE, | |
4855 | .open = i915_panel_open, | |
4856 | .read = seq_read, | |
4857 | .llseek = seq_lseek, | |
4858 | .release = single_release, | |
4859 | }; | |
4860 | ||
aa7471d2 JN |
4861 | /** |
4862 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4863 | * @connector: pointer to a registered drm_connector | |
4864 | * | |
4865 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4866 | * drm_debugfs_connector_remove(). | |
4867 | * | |
4868 | * Returns 0 on success, negative error codes on error. | |
4869 | */ | |
4870 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4871 | { | |
4872 | struct dentry *root = connector->debugfs_entry; | |
4873 | ||
4874 | /* The connector must have been registered beforehands. */ | |
4875 | if (!root) | |
4876 | return -ENODEV; | |
4877 | ||
4878 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
4879 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
4880 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
4881 | connector, &i915_dpcd_fops); | |
4882 | ||
4883 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
4884 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
4885 | connector, &i915_panel_fops); | |
aa7471d2 JN |
4886 | |
4887 | return 0; | |
4888 | } |