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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
79e53945 | 31 | #include "drm_crtc_helper.h" |
785b93ef | 32 | #include "drm_fb_helper.h" |
79e53945 | 33 | #include "intel_drv.h" |
1da177e4 LT |
34 | #include "i915_drm.h" |
35 | #include "i915_drv.h" | |
36 | ||
1da177e4 LT |
37 | /* Really want an OS-independent resettable timer. Would like to have |
38 | * this loop run for (eg) 3 sec, but have the timer reset every time | |
39 | * the head pointer changes, so that EBUSY only happens if the ring | |
40 | * actually stalls for (eg) 3 seconds. | |
41 | */ | |
84b1fd10 | 42 | int i915_wait_ring(struct drm_device * dev, int n, const char *caller) |
1da177e4 LT |
43 | { |
44 | drm_i915_private_t *dev_priv = dev->dev_private; | |
45 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
d3a6d446 KP |
46 | u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; |
47 | u32 last_acthd = I915_READ(acthd_reg); | |
48 | u32 acthd; | |
585fb111 | 49 | u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
1da177e4 LT |
50 | int i; |
51 | ||
d3a6d446 | 52 | for (i = 0; i < 100000; i++) { |
585fb111 | 53 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
d3a6d446 | 54 | acthd = I915_READ(acthd_reg); |
1da177e4 LT |
55 | ring->space = ring->head - (ring->tail + 8); |
56 | if (ring->space < 0) | |
57 | ring->space += ring->Size; | |
58 | if (ring->space >= n) | |
59 | return 0; | |
60 | ||
98787c05 CW |
61 | if (dev->primary->master) { |
62 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
63 | if (master_priv->sarea_priv) | |
64 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
65 | } | |
66 | ||
1da177e4 LT |
67 | |
68 | if (ring->head != last_head) | |
69 | i = 0; | |
d3a6d446 KP |
70 | if (acthd != last_acthd) |
71 | i = 0; | |
1da177e4 LT |
72 | |
73 | last_head = ring->head; | |
d3a6d446 KP |
74 | last_acthd = acthd; |
75 | msleep_interruptible(10); | |
76 | ||
1da177e4 LT |
77 | } |
78 | ||
20caafa6 | 79 | return -EBUSY; |
1da177e4 LT |
80 | } |
81 | ||
0ef82af7 CW |
82 | /* As a ringbuffer is only allowed to wrap between instructions, fill |
83 | * the tail with NOOPs. | |
84 | */ | |
85 | int i915_wrap_ring(struct drm_device *dev) | |
86 | { | |
87 | drm_i915_private_t *dev_priv = dev->dev_private; | |
88 | volatile unsigned int *virt; | |
89 | int rem; | |
90 | ||
91 | rem = dev_priv->ring.Size - dev_priv->ring.tail; | |
92 | if (dev_priv->ring.space < rem) { | |
93 | int ret = i915_wait_ring(dev, rem, __func__); | |
94 | if (ret) | |
95 | return ret; | |
96 | } | |
97 | dev_priv->ring.space -= rem; | |
98 | ||
99 | virt = (unsigned int *) | |
100 | (dev_priv->ring.virtual_start + dev_priv->ring.tail); | |
101 | rem /= 4; | |
102 | while (rem--) | |
103 | *virt++ = MI_NOOP; | |
104 | ||
105 | dev_priv->ring.tail = 0; | |
106 | ||
107 | return 0; | |
108 | } | |
109 | ||
398c9cb2 KP |
110 | /** |
111 | * Sets up the hardware status page for devices that need a physical address | |
112 | * in the register. | |
113 | */ | |
3043c60c | 114 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
115 | { |
116 | drm_i915_private_t *dev_priv = dev->dev_private; | |
117 | /* Program Hardware Status Page */ | |
118 | dev_priv->status_page_dmah = | |
119 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); | |
120 | ||
121 | if (!dev_priv->status_page_dmah) { | |
122 | DRM_ERROR("Can not allocate hardware status page\n"); | |
123 | return -ENOMEM; | |
124 | } | |
125 | dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; | |
126 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | |
127 | ||
128 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
129 | ||
130 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); | |
8a4c47f3 | 131 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
398c9cb2 KP |
132 | return 0; |
133 | } | |
134 | ||
135 | /** | |
136 | * Frees the hardware status page, whether it's a physical address or a virtual | |
137 | * address set up by the X Server. | |
138 | */ | |
3043c60c | 139 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
140 | { |
141 | drm_i915_private_t *dev_priv = dev->dev_private; | |
142 | if (dev_priv->status_page_dmah) { | |
143 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
144 | dev_priv->status_page_dmah = NULL; | |
145 | } | |
146 | ||
147 | if (dev_priv->status_gfx_addr) { | |
148 | dev_priv->status_gfx_addr = 0; | |
149 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | |
150 | } | |
151 | ||
152 | /* Need to rewrite hardware status page */ | |
153 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
154 | } | |
155 | ||
84b1fd10 | 156 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
157 | { |
158 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 159 | struct drm_i915_master_private *master_priv; |
1da177e4 LT |
160 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); |
161 | ||
79e53945 JB |
162 | /* |
163 | * We should never lose context on the ring with modesetting | |
164 | * as we don't expose it to userspace | |
165 | */ | |
166 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
167 | return; | |
168 | ||
585fb111 JB |
169 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
170 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
1da177e4 LT |
171 | ring->space = ring->head - (ring->tail + 8); |
172 | if (ring->space < 0) | |
173 | ring->space += ring->Size; | |
174 | ||
7c1c2871 DA |
175 | if (!dev->primary->master) |
176 | return; | |
177 | ||
178 | master_priv = dev->primary->master->driver_priv; | |
179 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
180 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
181 | } |
182 | ||
84b1fd10 | 183 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 184 | { |
ba8bbcf6 | 185 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
186 | /* Make sure interrupts are disabled here because the uninstall ioctl |
187 | * may not have been called from userspace and after dev_private | |
188 | * is freed, it's too late. | |
189 | */ | |
ed4cb414 | 190 | if (dev->irq_enabled) |
b5e89ed5 | 191 | drm_irq_uninstall(dev); |
1da177e4 | 192 | |
ba8bbcf6 JB |
193 | if (dev_priv->ring.virtual_start) { |
194 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
3043c60c EA |
195 | dev_priv->ring.virtual_start = NULL; |
196 | dev_priv->ring.map.handle = NULL; | |
ba8bbcf6 JB |
197 | dev_priv->ring.map.size = 0; |
198 | } | |
dc7a9319 | 199 | |
398c9cb2 KP |
200 | /* Clear the HWS virtual address at teardown */ |
201 | if (I915_NEED_GFX_HWS(dev)) | |
202 | i915_free_hws(dev); | |
1da177e4 LT |
203 | |
204 | return 0; | |
205 | } | |
206 | ||
ba8bbcf6 | 207 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 208 | { |
ba8bbcf6 | 209 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 210 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 211 | |
3a03ac1a DA |
212 | master_priv->sarea = drm_getsarea(dev); |
213 | if (master_priv->sarea) { | |
214 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
215 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
216 | } else { | |
8a4c47f3 | 217 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
218 | } |
219 | ||
673a394b EA |
220 | if (init->ring_size != 0) { |
221 | if (dev_priv->ring.ring_obj != NULL) { | |
222 | i915_dma_cleanup(dev); | |
223 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
224 | "GEM mode\n"); | |
225 | return -EINVAL; | |
226 | } | |
1da177e4 | 227 | |
673a394b | 228 | dev_priv->ring.Size = init->ring_size; |
1da177e4 | 229 | |
673a394b EA |
230 | dev_priv->ring.map.offset = init->ring_start; |
231 | dev_priv->ring.map.size = init->ring_size; | |
232 | dev_priv->ring.map.type = 0; | |
233 | dev_priv->ring.map.flags = 0; | |
234 | dev_priv->ring.map.mtrr = 0; | |
1da177e4 | 235 | |
6fb88588 | 236 | drm_core_ioremap_wc(&dev_priv->ring.map, dev); |
673a394b EA |
237 | |
238 | if (dev_priv->ring.map.handle == NULL) { | |
239 | i915_dma_cleanup(dev); | |
240 | DRM_ERROR("can not ioremap virtual address for" | |
241 | " ring buffer\n"); | |
242 | return -ENOMEM; | |
243 | } | |
1da177e4 LT |
244 | } |
245 | ||
246 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
247 | ||
a6b54f3f | 248 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
249 | dev_priv->back_offset = init->back_offset; |
250 | dev_priv->front_offset = init->front_offset; | |
251 | dev_priv->current_page = 0; | |
7c1c2871 DA |
252 | if (master_priv->sarea_priv) |
253 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 254 | |
1da177e4 LT |
255 | /* Allow hardware batchbuffers unless told otherwise. |
256 | */ | |
257 | dev_priv->allow_batchbuffer = 1; | |
258 | ||
1da177e4 LT |
259 | return 0; |
260 | } | |
261 | ||
84b1fd10 | 262 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
263 | { |
264 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
265 | ||
8a4c47f3 | 266 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 267 | |
1da177e4 LT |
268 | if (dev_priv->ring.map.handle == NULL) { |
269 | DRM_ERROR("can not ioremap virtual address for" | |
270 | " ring buffer\n"); | |
20caafa6 | 271 | return -ENOMEM; |
1da177e4 LT |
272 | } |
273 | ||
274 | /* Program Hardware Status Page */ | |
275 | if (!dev_priv->hw_status_page) { | |
276 | DRM_ERROR("Can not find hardware status page\n"); | |
20caafa6 | 277 | return -EINVAL; |
1da177e4 | 278 | } |
8a4c47f3 | 279 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
be25ed9c | 280 | dev_priv->hw_status_page); |
1da177e4 | 281 | |
dc7a9319 | 282 | if (dev_priv->status_gfx_addr != 0) |
585fb111 | 283 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
dc7a9319 | 284 | else |
585fb111 | 285 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
8a4c47f3 | 286 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
287 | |
288 | return 0; | |
289 | } | |
290 | ||
c153f45f EA |
291 | static int i915_dma_init(struct drm_device *dev, void *data, |
292 | struct drm_file *file_priv) | |
1da177e4 | 293 | { |
c153f45f | 294 | drm_i915_init_t *init = data; |
1da177e4 LT |
295 | int retcode = 0; |
296 | ||
c153f45f | 297 | switch (init->func) { |
1da177e4 | 298 | case I915_INIT_DMA: |
ba8bbcf6 | 299 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
300 | break; |
301 | case I915_CLEANUP_DMA: | |
302 | retcode = i915_dma_cleanup(dev); | |
303 | break; | |
304 | case I915_RESUME_DMA: | |
0d6aa60b | 305 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
306 | break; |
307 | default: | |
20caafa6 | 308 | retcode = -EINVAL; |
1da177e4 LT |
309 | break; |
310 | } | |
311 | ||
312 | return retcode; | |
313 | } | |
314 | ||
315 | /* Implement basically the same security restrictions as hardware does | |
316 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
317 | * | |
318 | * Most of the calculations below involve calculating the size of a | |
319 | * particular instruction. It's important to get the size right as | |
320 | * that tells us where the next instruction to check is. Any illegal | |
321 | * instruction detected will be given a size of zero, which is a | |
322 | * signal to abort the rest of the buffer. | |
323 | */ | |
324 | static int do_validate_cmd(int cmd) | |
325 | { | |
326 | switch (((cmd >> 29) & 0x7)) { | |
327 | case 0x0: | |
328 | switch ((cmd >> 23) & 0x3f) { | |
329 | case 0x0: | |
330 | return 1; /* MI_NOOP */ | |
331 | case 0x4: | |
332 | return 1; /* MI_FLUSH */ | |
333 | default: | |
334 | return 0; /* disallow everything else */ | |
335 | } | |
336 | break; | |
337 | case 0x1: | |
338 | return 0; /* reserved */ | |
339 | case 0x2: | |
340 | return (cmd & 0xff) + 2; /* 2d commands */ | |
341 | case 0x3: | |
342 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
343 | return 1; | |
344 | ||
345 | switch ((cmd >> 24) & 0x1f) { | |
346 | case 0x1c: | |
347 | return 1; | |
348 | case 0x1d: | |
b5e89ed5 | 349 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
350 | case 0x3: |
351 | return (cmd & 0x1f) + 2; | |
352 | case 0x4: | |
353 | return (cmd & 0xf) + 2; | |
354 | default: | |
355 | return (cmd & 0xffff) + 2; | |
356 | } | |
357 | case 0x1e: | |
358 | if (cmd & (1 << 23)) | |
359 | return (cmd & 0xffff) + 1; | |
360 | else | |
361 | return 1; | |
362 | case 0x1f: | |
363 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
364 | return (cmd & 0x1ffff) + 2; | |
365 | else if (cmd & (1 << 17)) /* indirect random */ | |
366 | if ((cmd & 0xffff) == 0) | |
367 | return 0; /* unknown length, too hard */ | |
368 | else | |
369 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
370 | else | |
371 | return 2; /* indirect sequential */ | |
372 | default: | |
373 | return 0; | |
374 | } | |
375 | default: | |
376 | return 0; | |
377 | } | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static int validate_cmd(int cmd) | |
383 | { | |
384 | int ret = do_validate_cmd(cmd); | |
385 | ||
bc5f4523 | 386 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ |
1da177e4 LT |
387 | |
388 | return ret; | |
389 | } | |
390 | ||
201361a5 | 391 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 LT |
392 | { |
393 | drm_i915_private_t *dev_priv = dev->dev_private; | |
394 | int i; | |
395 | RING_LOCALS; | |
396 | ||
de227f5f | 397 | if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) |
20caafa6 | 398 | return -EINVAL; |
de227f5f | 399 | |
c29b669c | 400 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 401 | |
1da177e4 LT |
402 | for (i = 0; i < dwords;) { |
403 | int cmd, sz; | |
404 | ||
201361a5 | 405 | cmd = buffer[i]; |
1da177e4 | 406 | |
1da177e4 | 407 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
20caafa6 | 408 | return -EINVAL; |
1da177e4 | 409 | |
1da177e4 LT |
410 | OUT_RING(cmd); |
411 | ||
412 | while (++i, --sz) { | |
201361a5 | 413 | OUT_RING(buffer[i]); |
1da177e4 | 414 | } |
1da177e4 LT |
415 | } |
416 | ||
de227f5f DA |
417 | if (dwords & 1) |
418 | OUT_RING(0); | |
419 | ||
420 | ADVANCE_LP_RING(); | |
421 | ||
1da177e4 LT |
422 | return 0; |
423 | } | |
424 | ||
673a394b EA |
425 | int |
426 | i915_emit_box(struct drm_device *dev, | |
201361a5 | 427 | struct drm_clip_rect *boxes, |
673a394b | 428 | int i, int DR1, int DR4) |
1da177e4 LT |
429 | { |
430 | drm_i915_private_t *dev_priv = dev->dev_private; | |
201361a5 | 431 | struct drm_clip_rect box = boxes[i]; |
1da177e4 LT |
432 | RING_LOCALS; |
433 | ||
1da177e4 LT |
434 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { |
435 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
436 | box.x1, box.y1, box.x2, box.y2); | |
20caafa6 | 437 | return -EINVAL; |
1da177e4 LT |
438 | } |
439 | ||
c29b669c AH |
440 | if (IS_I965G(dev)) { |
441 | BEGIN_LP_RING(4); | |
442 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
443 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 444 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
445 | OUT_RING(DR4); |
446 | ADVANCE_LP_RING(); | |
447 | } else { | |
448 | BEGIN_LP_RING(6); | |
449 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
450 | OUT_RING(DR1); | |
451 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
452 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
453 | OUT_RING(DR4); | |
454 | OUT_RING(0); | |
455 | ADVANCE_LP_RING(); | |
456 | } | |
1da177e4 LT |
457 | |
458 | return 0; | |
459 | } | |
460 | ||
c29b669c AH |
461 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
462 | * emit. For now, do it in both places: | |
463 | */ | |
464 | ||
84b1fd10 | 465 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
466 | { |
467 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 468 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f DA |
469 | RING_LOCALS; |
470 | ||
c99b058f | 471 | dev_priv->counter++; |
af6061af | 472 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 473 | dev_priv->counter = 0; |
7c1c2871 DA |
474 | if (master_priv->sarea_priv) |
475 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f DA |
476 | |
477 | BEGIN_LP_RING(4); | |
585fb111 | 478 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 479 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
de227f5f DA |
480 | OUT_RING(dev_priv->counter); |
481 | OUT_RING(0); | |
482 | ADVANCE_LP_RING(); | |
483 | } | |
484 | ||
84b1fd10 | 485 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
486 | drm_i915_cmdbuffer_t *cmd, |
487 | struct drm_clip_rect *cliprects, | |
488 | void *cmdbuf) | |
1da177e4 LT |
489 | { |
490 | int nbox = cmd->num_cliprects; | |
491 | int i = 0, count, ret; | |
492 | ||
493 | if (cmd->sz & 0x3) { | |
494 | DRM_ERROR("alignment"); | |
20caafa6 | 495 | return -EINVAL; |
1da177e4 LT |
496 | } |
497 | ||
498 | i915_kernel_lost_context(dev); | |
499 | ||
500 | count = nbox ? nbox : 1; | |
501 | ||
502 | for (i = 0; i < count; i++) { | |
503 | if (i < nbox) { | |
201361a5 | 504 | ret = i915_emit_box(dev, cliprects, i, |
1da177e4 LT |
505 | cmd->DR1, cmd->DR4); |
506 | if (ret) | |
507 | return ret; | |
508 | } | |
509 | ||
201361a5 | 510 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
511 | if (ret) |
512 | return ret; | |
513 | } | |
514 | ||
de227f5f | 515 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
516 | return 0; |
517 | } | |
518 | ||
84b1fd10 | 519 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
520 | drm_i915_batchbuffer_t * batch, |
521 | struct drm_clip_rect *cliprects) | |
1da177e4 LT |
522 | { |
523 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1da177e4 LT |
524 | int nbox = batch->num_cliprects; |
525 | int i = 0, count; | |
526 | RING_LOCALS; | |
527 | ||
528 | if ((batch->start | batch->used) & 0x7) { | |
529 | DRM_ERROR("alignment"); | |
20caafa6 | 530 | return -EINVAL; |
1da177e4 LT |
531 | } |
532 | ||
533 | i915_kernel_lost_context(dev); | |
534 | ||
535 | count = nbox ? nbox : 1; | |
536 | ||
537 | for (i = 0; i < count; i++) { | |
538 | if (i < nbox) { | |
201361a5 | 539 | int ret = i915_emit_box(dev, cliprects, i, |
1da177e4 LT |
540 | batch->DR1, batch->DR4); |
541 | if (ret) | |
542 | return ret; | |
543 | } | |
544 | ||
0790d5e1 | 545 | if (!IS_I830(dev) && !IS_845G(dev)) { |
1da177e4 | 546 | BEGIN_LP_RING(2); |
21f16289 DA |
547 | if (IS_I965G(dev)) { |
548 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
549 | OUT_RING(batch->start); | |
550 | } else { | |
551 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
552 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
553 | } | |
1da177e4 LT |
554 | ADVANCE_LP_RING(); |
555 | } else { | |
556 | BEGIN_LP_RING(4); | |
557 | OUT_RING(MI_BATCH_BUFFER); | |
558 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
559 | OUT_RING(batch->start + batch->used - 4); | |
560 | OUT_RING(0); | |
561 | ADVANCE_LP_RING(); | |
562 | } | |
563 | } | |
564 | ||
de227f5f | 565 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
566 | |
567 | return 0; | |
568 | } | |
569 | ||
af6061af | 570 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
571 | { |
572 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
573 | struct drm_i915_master_private *master_priv = |
574 | dev->primary->master->driver_priv; | |
1da177e4 LT |
575 | RING_LOCALS; |
576 | ||
7c1c2871 | 577 | if (!master_priv->sarea_priv) |
c99b058f KH |
578 | return -EINVAL; |
579 | ||
8a4c47f3 | 580 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 581 | __func__, |
582 | dev_priv->current_page, | |
583 | master_priv->sarea_priv->pf_current_page); | |
1da177e4 | 584 | |
af6061af DA |
585 | i915_kernel_lost_context(dev); |
586 | ||
587 | BEGIN_LP_RING(2); | |
585fb111 | 588 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af DA |
589 | OUT_RING(0); |
590 | ADVANCE_LP_RING(); | |
1da177e4 | 591 | |
af6061af DA |
592 | BEGIN_LP_RING(6); |
593 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
594 | OUT_RING(0); | |
595 | if (dev_priv->current_page == 0) { | |
596 | OUT_RING(dev_priv->back_offset); | |
597 | dev_priv->current_page = 1; | |
1da177e4 | 598 | } else { |
af6061af DA |
599 | OUT_RING(dev_priv->front_offset); |
600 | dev_priv->current_page = 0; | |
1da177e4 | 601 | } |
af6061af DA |
602 | OUT_RING(0); |
603 | ADVANCE_LP_RING(); | |
1da177e4 | 604 | |
af6061af DA |
605 | BEGIN_LP_RING(2); |
606 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
607 | OUT_RING(0); | |
608 | ADVANCE_LP_RING(); | |
1da177e4 | 609 | |
7c1c2871 | 610 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 LT |
611 | |
612 | BEGIN_LP_RING(4); | |
585fb111 | 613 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 614 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
af6061af DA |
615 | OUT_RING(dev_priv->counter); |
616 | OUT_RING(0); | |
1da177e4 LT |
617 | ADVANCE_LP_RING(); |
618 | ||
7c1c2871 | 619 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
af6061af | 620 | return 0; |
1da177e4 LT |
621 | } |
622 | ||
84b1fd10 | 623 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
624 | { |
625 | drm_i915_private_t *dev_priv = dev->dev_private; | |
626 | ||
627 | i915_kernel_lost_context(dev); | |
bf9d8929 | 628 | return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); |
1da177e4 LT |
629 | } |
630 | ||
c153f45f EA |
631 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
632 | struct drm_file *file_priv) | |
1da177e4 | 633 | { |
546b0974 EA |
634 | int ret; |
635 | ||
636 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1da177e4 | 637 | |
546b0974 EA |
638 | mutex_lock(&dev->struct_mutex); |
639 | ret = i915_quiescent(dev); | |
640 | mutex_unlock(&dev->struct_mutex); | |
641 | ||
642 | return ret; | |
1da177e4 LT |
643 | } |
644 | ||
c153f45f EA |
645 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
646 | struct drm_file *file_priv) | |
1da177e4 | 647 | { |
1da177e4 | 648 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 649 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 650 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 651 | master_priv->sarea_priv; |
c153f45f | 652 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 653 | int ret; |
201361a5 | 654 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 LT |
655 | |
656 | if (!dev_priv->allow_batchbuffer) { | |
657 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 658 | return -EINVAL; |
1da177e4 LT |
659 | } |
660 | ||
8a4c47f3 | 661 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 662 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 663 | |
546b0974 | 664 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 665 | |
201361a5 EA |
666 | if (batch->num_cliprects < 0) |
667 | return -EINVAL; | |
668 | ||
669 | if (batch->num_cliprects) { | |
9a298b2a EA |
670 | cliprects = kcalloc(batch->num_cliprects, |
671 | sizeof(struct drm_clip_rect), | |
672 | GFP_KERNEL); | |
201361a5 EA |
673 | if (cliprects == NULL) |
674 | return -ENOMEM; | |
675 | ||
676 | ret = copy_from_user(cliprects, batch->cliprects, | |
677 | batch->num_cliprects * | |
678 | sizeof(struct drm_clip_rect)); | |
679 | if (ret != 0) | |
680 | goto fail_free; | |
681 | } | |
1da177e4 | 682 | |
546b0974 | 683 | mutex_lock(&dev->struct_mutex); |
201361a5 | 684 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 685 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 686 | |
c99b058f | 687 | if (sarea_priv) |
0baf823a | 688 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
689 | |
690 | fail_free: | |
9a298b2a | 691 | kfree(cliprects); |
201361a5 | 692 | |
1da177e4 LT |
693 | return ret; |
694 | } | |
695 | ||
c153f45f EA |
696 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
697 | struct drm_file *file_priv) | |
1da177e4 | 698 | { |
1da177e4 | 699 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 700 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 701 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 702 | master_priv->sarea_priv; |
c153f45f | 703 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
704 | struct drm_clip_rect *cliprects = NULL; |
705 | void *batch_data; | |
1da177e4 LT |
706 | int ret; |
707 | ||
8a4c47f3 | 708 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 709 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 710 | |
546b0974 | 711 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 712 | |
201361a5 EA |
713 | if (cmdbuf->num_cliprects < 0) |
714 | return -EINVAL; | |
715 | ||
9a298b2a | 716 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
717 | if (batch_data == NULL) |
718 | return -ENOMEM; | |
719 | ||
720 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
721 | if (ret != 0) | |
722 | goto fail_batch_free; | |
723 | ||
724 | if (cmdbuf->num_cliprects) { | |
9a298b2a EA |
725 | cliprects = kcalloc(cmdbuf->num_cliprects, |
726 | sizeof(struct drm_clip_rect), GFP_KERNEL); | |
201361a5 EA |
727 | if (cliprects == NULL) |
728 | goto fail_batch_free; | |
729 | ||
730 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
731 | cmdbuf->num_cliprects * | |
732 | sizeof(struct drm_clip_rect)); | |
733 | if (ret != 0) | |
734 | goto fail_clip_free; | |
1da177e4 LT |
735 | } |
736 | ||
546b0974 | 737 | mutex_lock(&dev->struct_mutex); |
201361a5 | 738 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 739 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
740 | if (ret) { |
741 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 742 | goto fail_clip_free; |
1da177e4 LT |
743 | } |
744 | ||
c99b058f | 745 | if (sarea_priv) |
0baf823a | 746 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 747 | |
201361a5 | 748 | fail_clip_free: |
9a298b2a | 749 | kfree(cliprects); |
355d7f37 | 750 | fail_batch_free: |
9a298b2a | 751 | kfree(batch_data); |
201361a5 EA |
752 | |
753 | return ret; | |
1da177e4 LT |
754 | } |
755 | ||
c153f45f EA |
756 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
757 | struct drm_file *file_priv) | |
1da177e4 | 758 | { |
546b0974 EA |
759 | int ret; |
760 | ||
8a4c47f3 | 761 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 762 | |
546b0974 | 763 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 764 | |
546b0974 EA |
765 | mutex_lock(&dev->struct_mutex); |
766 | ret = i915_dispatch_flip(dev); | |
767 | mutex_unlock(&dev->struct_mutex); | |
768 | ||
769 | return ret; | |
1da177e4 LT |
770 | } |
771 | ||
c153f45f EA |
772 | static int i915_getparam(struct drm_device *dev, void *data, |
773 | struct drm_file *file_priv) | |
1da177e4 | 774 | { |
1da177e4 | 775 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 776 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
777 | int value; |
778 | ||
779 | if (!dev_priv) { | |
3e684eae | 780 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 781 | return -EINVAL; |
1da177e4 LT |
782 | } |
783 | ||
c153f45f | 784 | switch (param->param) { |
1da177e4 | 785 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 786 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
787 | break; |
788 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
789 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
790 | break; | |
0d6aa60b DA |
791 | case I915_PARAM_LAST_DISPATCH: |
792 | value = READ_BREADCRUMB(dev_priv); | |
793 | break; | |
ed4c9c4a KH |
794 | case I915_PARAM_CHIPSET_ID: |
795 | value = dev->pci_device; | |
796 | break; | |
673a394b | 797 | case I915_PARAM_HAS_GEM: |
ac5c4e76 | 798 | value = dev_priv->has_gem; |
673a394b | 799 | break; |
0f973f27 JB |
800 | case I915_PARAM_NUM_FENCES_AVAIL: |
801 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
802 | break; | |
1da177e4 | 803 | default: |
8a4c47f3 | 804 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
be25ed9c | 805 | param->param); |
20caafa6 | 806 | return -EINVAL; |
1da177e4 LT |
807 | } |
808 | ||
c153f45f | 809 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 810 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 811 | return -EFAULT; |
1da177e4 LT |
812 | } |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
c153f45f EA |
817 | static int i915_setparam(struct drm_device *dev, void *data, |
818 | struct drm_file *file_priv) | |
1da177e4 | 819 | { |
1da177e4 | 820 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 821 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
822 | |
823 | if (!dev_priv) { | |
3e684eae | 824 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 825 | return -EINVAL; |
1da177e4 LT |
826 | } |
827 | ||
c153f45f | 828 | switch (param->param) { |
1da177e4 | 829 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
830 | break; |
831 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 832 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
833 | break; |
834 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 835 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 | 836 | break; |
0f973f27 JB |
837 | case I915_SETPARAM_NUM_USED_FENCES: |
838 | if (param->value > dev_priv->num_fence_regs || | |
839 | param->value < 0) | |
840 | return -EINVAL; | |
841 | /* Userspace can use first N regs */ | |
842 | dev_priv->fence_reg_start = param->value; | |
843 | break; | |
1da177e4 | 844 | default: |
8a4c47f3 | 845 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 846 | param->param); |
20caafa6 | 847 | return -EINVAL; |
1da177e4 LT |
848 | } |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
c153f45f EA |
853 | static int i915_set_status_page(struct drm_device *dev, void *data, |
854 | struct drm_file *file_priv) | |
dc7a9319 | 855 | { |
dc7a9319 | 856 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 857 | drm_i915_hws_addr_t *hws = data; |
b39d50e5 ZW |
858 | |
859 | if (!I915_NEED_GFX_HWS(dev)) | |
860 | return -EINVAL; | |
dc7a9319 WZ |
861 | |
862 | if (!dev_priv) { | |
3e684eae | 863 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 864 | return -EINVAL; |
dc7a9319 | 865 | } |
dc7a9319 | 866 | |
79e53945 JB |
867 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
868 | WARN(1, "tried to set status page when mode setting active\n"); | |
869 | return 0; | |
870 | } | |
871 | ||
8a4c47f3 | 872 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f EA |
873 | |
874 | dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); | |
dc7a9319 | 875 | |
8b409580 | 876 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
877 | dev_priv->hws_map.size = 4*1024; |
878 | dev_priv->hws_map.type = 0; | |
879 | dev_priv->hws_map.flags = 0; | |
880 | dev_priv->hws_map.mtrr = 0; | |
881 | ||
dd0910b3 | 882 | drm_core_ioremap_wc(&dev_priv->hws_map, dev); |
dc7a9319 | 883 | if (dev_priv->hws_map.handle == NULL) { |
dc7a9319 WZ |
884 | i915_dma_cleanup(dev); |
885 | dev_priv->status_gfx_addr = 0; | |
886 | DRM_ERROR("can not ioremap virtual address for" | |
887 | " G33 hw status page\n"); | |
20caafa6 | 888 | return -ENOMEM; |
dc7a9319 WZ |
889 | } |
890 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | |
891 | ||
892 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
585fb111 | 893 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
8a4c47f3 | 894 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
be25ed9c | 895 | dev_priv->status_gfx_addr); |
8a4c47f3 | 896 | DRM_DEBUG_DRIVER("load hws at %p\n", |
be25ed9c | 897 | dev_priv->hw_status_page); |
dc7a9319 WZ |
898 | return 0; |
899 | } | |
900 | ||
ec2a4c3f DA |
901 | static int i915_get_bridge_dev(struct drm_device *dev) |
902 | { | |
903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
904 | ||
905 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); | |
906 | if (!dev_priv->bridge_dev) { | |
907 | DRM_ERROR("bridge device not found\n"); | |
908 | return -1; | |
909 | } | |
910 | return 0; | |
911 | } | |
912 | ||
79e53945 JB |
913 | /** |
914 | * i915_probe_agp - get AGP bootup configuration | |
915 | * @pdev: PCI device | |
916 | * @aperture_size: returns AGP aperture configured size | |
917 | * @preallocated_size: returns size of BIOS preallocated AGP space | |
918 | * | |
919 | * Since Intel integrated graphics are UMA, the BIOS has to set aside | |
920 | * some RAM for the framebuffer at early boot. This code figures out | |
921 | * how much was set aside so we can use it for our own purposes. | |
922 | */ | |
2a34f5e6 EA |
923 | static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, |
924 | uint32_t *preallocated_size) | |
79e53945 | 925 | { |
ec2a4c3f | 926 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
927 | u16 tmp = 0; |
928 | unsigned long overhead; | |
241fa85b | 929 | unsigned long stolen; |
79e53945 | 930 | |
79e53945 | 931 | /* Get the fb aperture size and "stolen" memory amount. */ |
ec2a4c3f | 932 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp); |
79e53945 JB |
933 | |
934 | *aperture_size = 1024 * 1024; | |
935 | *preallocated_size = 1024 * 1024; | |
936 | ||
60fd99e3 | 937 | switch (dev->pdev->device) { |
79e53945 JB |
938 | case PCI_DEVICE_ID_INTEL_82830_CGC: |
939 | case PCI_DEVICE_ID_INTEL_82845G_IG: | |
940 | case PCI_DEVICE_ID_INTEL_82855GM_IG: | |
941 | case PCI_DEVICE_ID_INTEL_82865_IG: | |
942 | if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) | |
943 | *aperture_size *= 64; | |
944 | else | |
945 | *aperture_size *= 128; | |
946 | break; | |
947 | default: | |
948 | /* 9xx supports large sizes, just look at the length */ | |
60fd99e3 | 949 | *aperture_size = pci_resource_len(dev->pdev, 2); |
79e53945 JB |
950 | break; |
951 | } | |
952 | ||
953 | /* | |
954 | * Some of the preallocated space is taken by the GTT | |
955 | * and popup. GTT is 1K per MB of aperture size, and popup is 4K. | |
956 | */ | |
2c07245f | 957 | if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev)) |
60fd99e3 EA |
958 | overhead = 4096; |
959 | else | |
960 | overhead = (*aperture_size / 1024) + 4096; | |
961 | ||
241fa85b EA |
962 | switch (tmp & INTEL_GMCH_GMS_MASK) { |
963 | case INTEL_855_GMCH_GMS_DISABLED: | |
964 | DRM_ERROR("video memory is disabled\n"); | |
965 | return -1; | |
79e53945 | 966 | case INTEL_855_GMCH_GMS_STOLEN_1M: |
241fa85b EA |
967 | stolen = 1 * 1024 * 1024; |
968 | break; | |
79e53945 | 969 | case INTEL_855_GMCH_GMS_STOLEN_4M: |
241fa85b | 970 | stolen = 4 * 1024 * 1024; |
79e53945 JB |
971 | break; |
972 | case INTEL_855_GMCH_GMS_STOLEN_8M: | |
241fa85b | 973 | stolen = 8 * 1024 * 1024; |
79e53945 JB |
974 | break; |
975 | case INTEL_855_GMCH_GMS_STOLEN_16M: | |
241fa85b | 976 | stolen = 16 * 1024 * 1024; |
79e53945 JB |
977 | break; |
978 | case INTEL_855_GMCH_GMS_STOLEN_32M: | |
241fa85b | 979 | stolen = 32 * 1024 * 1024; |
79e53945 JB |
980 | break; |
981 | case INTEL_915G_GMCH_GMS_STOLEN_48M: | |
241fa85b | 982 | stolen = 48 * 1024 * 1024; |
79e53945 JB |
983 | break; |
984 | case INTEL_915G_GMCH_GMS_STOLEN_64M: | |
241fa85b EA |
985 | stolen = 64 * 1024 * 1024; |
986 | break; | |
987 | case INTEL_GMCH_GMS_STOLEN_128M: | |
988 | stolen = 128 * 1024 * 1024; | |
989 | break; | |
990 | case INTEL_GMCH_GMS_STOLEN_256M: | |
991 | stolen = 256 * 1024 * 1024; | |
992 | break; | |
993 | case INTEL_GMCH_GMS_STOLEN_96M: | |
994 | stolen = 96 * 1024 * 1024; | |
995 | break; | |
996 | case INTEL_GMCH_GMS_STOLEN_160M: | |
997 | stolen = 160 * 1024 * 1024; | |
998 | break; | |
999 | case INTEL_GMCH_GMS_STOLEN_224M: | |
1000 | stolen = 224 * 1024 * 1024; | |
1001 | break; | |
1002 | case INTEL_GMCH_GMS_STOLEN_352M: | |
1003 | stolen = 352 * 1024 * 1024; | |
79e53945 | 1004 | break; |
79e53945 JB |
1005 | default: |
1006 | DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", | |
241fa85b | 1007 | tmp & INTEL_GMCH_GMS_MASK); |
79e53945 JB |
1008 | return -1; |
1009 | } | |
241fa85b | 1010 | *preallocated_size = stolen - overhead; |
79e53945 JB |
1011 | |
1012 | return 0; | |
1013 | } | |
1014 | ||
2a34f5e6 EA |
1015 | static int i915_load_modeset_init(struct drm_device *dev, |
1016 | unsigned long prealloc_size, | |
1017 | unsigned long agp_size) | |
79e53945 JB |
1018 | { |
1019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
79e53945 JB |
1020 | int fb_bar = IS_I9XX(dev) ? 2 : 0; |
1021 | int ret = 0; | |
1022 | ||
1023 | dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) & | |
1024 | 0xff000000; | |
1025 | ||
2906f025 | 1026 | if (IS_MOBILE(dev) || IS_I9XX(dev)) |
79e53945 JB |
1027 | dev_priv->cursor_needs_physical = true; |
1028 | else | |
1029 | dev_priv->cursor_needs_physical = false; | |
1030 | ||
2906f025 JB |
1031 | if (IS_I965G(dev) || IS_G33(dev)) |
1032 | dev_priv->cursor_needs_physical = false; | |
1033 | ||
79e53945 JB |
1034 | /* Basic memrange allocator for stolen space (aka vram) */ |
1035 | drm_mm_init(&dev_priv->vram, 0, prealloc_size); | |
1036 | ||
13f4c435 EA |
1037 | /* Let GEM Manage from end of prealloc space to end of aperture. |
1038 | * | |
1039 | * However, leave one page at the end still bound to the scratch page. | |
1040 | * There are a number of places where the hardware apparently | |
1041 | * prefetches past the end of the object, and we've seen multiple | |
1042 | * hangs with the GPU head pointer stuck in a batchbuffer bound | |
1043 | * at the last page of the aperture. One page should be enough to | |
1044 | * keep any prefetching inside of the aperture. | |
1045 | */ | |
1046 | i915_gem_do_init(dev, prealloc_size, agp_size - 4096); | |
79e53945 JB |
1047 | |
1048 | ret = i915_gem_init_ringbuffer(dev); | |
1049 | if (ret) | |
b8da7de5 | 1050 | goto out; |
79e53945 | 1051 | |
79e53945 JB |
1052 | /* Allow hardware batchbuffers unless told otherwise. |
1053 | */ | |
1054 | dev_priv->allow_batchbuffer = 1; | |
1055 | ||
1056 | ret = intel_init_bios(dev); | |
1057 | if (ret) | |
1058 | DRM_INFO("failed to find VBIOS tables\n"); | |
1059 | ||
1060 | ret = drm_irq_install(dev); | |
1061 | if (ret) | |
1062 | goto destroy_ringbuffer; | |
1063 | ||
79e53945 JB |
1064 | /* Always safe in the mode setting case. */ |
1065 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
1066 | dev->vblank_disable_allowed = 1; | |
1067 | ||
1068 | /* | |
1069 | * Initialize the hardware status page IRQ location. | |
1070 | */ | |
1071 | ||
1072 | I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); | |
1073 | ||
1074 | intel_modeset_init(dev); | |
1075 | ||
7a1fb5d0 | 1076 | drm_helper_initial_config(dev); |
79e53945 | 1077 | |
79e53945 JB |
1078 | return 0; |
1079 | ||
79e53945 JB |
1080 | destroy_ringbuffer: |
1081 | i915_gem_cleanup_ringbuffer(dev); | |
1082 | out: | |
1083 | return ret; | |
1084 | } | |
1085 | ||
7c1c2871 DA |
1086 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1087 | { | |
1088 | struct drm_i915_master_private *master_priv; | |
1089 | ||
9a298b2a | 1090 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1091 | if (!master_priv) |
1092 | return -ENOMEM; | |
1093 | ||
1094 | master->driver_priv = master_priv; | |
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1099 | { | |
1100 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1101 | ||
1102 | if (!master_priv) | |
1103 | return; | |
1104 | ||
9a298b2a | 1105 | kfree(master_priv); |
7c1c2871 DA |
1106 | |
1107 | master->driver_priv = NULL; | |
1108 | } | |
1109 | ||
7662c8bd SL |
1110 | static void i915_get_mem_freq(struct drm_device *dev) |
1111 | { | |
1112 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1113 | u32 tmp; | |
1114 | ||
1115 | if (!IS_IGD(dev)) | |
1116 | return; | |
1117 | ||
1118 | tmp = I915_READ(CLKCFG); | |
1119 | ||
1120 | switch (tmp & CLKCFG_FSB_MASK) { | |
1121 | case CLKCFG_FSB_533: | |
1122 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
1123 | break; | |
1124 | case CLKCFG_FSB_800: | |
1125 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
1126 | break; | |
1127 | case CLKCFG_FSB_667: | |
1128 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
1129 | break; | |
1130 | case CLKCFG_FSB_400: | |
1131 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
1132 | break; | |
1133 | } | |
1134 | ||
1135 | switch (tmp & CLKCFG_MEM_MASK) { | |
1136 | case CLKCFG_MEM_533: | |
1137 | dev_priv->mem_freq = 533; | |
1138 | break; | |
1139 | case CLKCFG_MEM_667: | |
1140 | dev_priv->mem_freq = 667; | |
1141 | break; | |
1142 | case CLKCFG_MEM_800: | |
1143 | dev_priv->mem_freq = 800; | |
1144 | break; | |
1145 | } | |
1146 | } | |
1147 | ||
79e53945 JB |
1148 | /** |
1149 | * i915_driver_load - setup chip and create an initial config | |
1150 | * @dev: DRM device | |
1151 | * @flags: startup flags | |
1152 | * | |
1153 | * The driver load routine has to do several things: | |
1154 | * - drive output discovery via intel_modeset_init() | |
1155 | * - initialize the memory manager | |
1156 | * - allocate initial config memory | |
1157 | * - setup the DRM framebuffer with the allocated memory | |
1158 | */ | |
84b1fd10 | 1159 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1160 | { |
ba8bbcf6 | 1161 | struct drm_i915_private *dev_priv = dev->dev_private; |
d883f7f1 | 1162 | resource_size_t base, size; |
ba8bbcf6 | 1163 | int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; |
2a34f5e6 | 1164 | uint32_t agp_size, prealloc_size; |
ba8bbcf6 | 1165 | |
22eae947 DA |
1166 | /* i915 has 4 more counters */ |
1167 | dev->counters += 4; | |
1168 | dev->types[6] = _DRM_STAT_IRQ; | |
1169 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1170 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1171 | dev->types[9] = _DRM_STAT_DMA; | |
1172 | ||
9a298b2a | 1173 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
ba8bbcf6 JB |
1174 | if (dev_priv == NULL) |
1175 | return -ENOMEM; | |
1176 | ||
ba8bbcf6 | 1177 | dev->dev_private = (void *)dev_priv; |
673a394b | 1178 | dev_priv->dev = dev; |
ba8bbcf6 JB |
1179 | |
1180 | /* Add register map (needed for suspend/resume) */ | |
1181 | base = drm_get_resource_start(dev, mmio_bar); | |
1182 | size = drm_get_resource_len(dev, mmio_bar); | |
1183 | ||
ec2a4c3f DA |
1184 | if (i915_get_bridge_dev(dev)) { |
1185 | ret = -EIO; | |
1186 | goto free_priv; | |
1187 | } | |
1188 | ||
3043c60c | 1189 | dev_priv->regs = ioremap(base, size); |
79e53945 JB |
1190 | if (!dev_priv->regs) { |
1191 | DRM_ERROR("failed to map registers\n"); | |
1192 | ret = -EIO; | |
ec2a4c3f | 1193 | goto put_bridge; |
79e53945 | 1194 | } |
ed4cb414 | 1195 | |
ab657db1 EA |
1196 | dev_priv->mm.gtt_mapping = |
1197 | io_mapping_create_wc(dev->agp->base, | |
1198 | dev->agp->agp_info.aper_size * 1024*1024); | |
6644107d VP |
1199 | if (dev_priv->mm.gtt_mapping == NULL) { |
1200 | ret = -EIO; | |
1201 | goto out_rmmap; | |
1202 | } | |
1203 | ||
ab657db1 EA |
1204 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
1205 | * one would think, because the kernel disables PAT on first | |
1206 | * generation Core chips because WC PAT gets overridden by a UC | |
1207 | * MTRR if present. Even if a UC MTRR isn't present. | |
1208 | */ | |
1209 | dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, | |
1210 | dev->agp->agp_info.aper_size * | |
1211 | 1024 * 1024, | |
1212 | MTRR_TYPE_WRCOMB, 1); | |
1213 | if (dev_priv->mm.gtt_mtrr < 0) { | |
040aefa2 | 1214 | DRM_INFO("MTRR allocation failed. Graphics " |
ab657db1 EA |
1215 | "performance may suffer.\n"); |
1216 | } | |
1217 | ||
2a34f5e6 EA |
1218 | ret = i915_probe_agp(dev, &agp_size, &prealloc_size); |
1219 | if (ret) | |
1220 | goto out_iomapfree; | |
1221 | ||
9c9fe1f8 EA |
1222 | dev_priv->wq = create_workqueue("i915"); |
1223 | if (dev_priv->wq == NULL) { | |
1224 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1225 | ret = -ENOMEM; | |
1226 | goto out_iomapfree; | |
1227 | } | |
1228 | ||
ac5c4e76 DA |
1229 | /* enable GEM by default */ |
1230 | dev_priv->has_gem = 1; | |
ac5c4e76 | 1231 | |
2a34f5e6 EA |
1232 | if (prealloc_size > agp_size * 3 / 4) { |
1233 | DRM_ERROR("Detected broken video BIOS with %d/%dkB of video " | |
1234 | "memory stolen.\n", | |
1235 | prealloc_size / 1024, agp_size / 1024); | |
1236 | DRM_ERROR("Disabling GEM. (try reducing stolen memory or " | |
1237 | "updating the BIOS to fix).\n"); | |
1238 | dev_priv->has_gem = 0; | |
1239 | } | |
1240 | ||
9880b7a5 | 1241 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
42c2798b | 1242 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
036a4a7d | 1243 | if (IS_G4X(dev) || IS_IGDNG(dev)) { |
42c2798b | 1244 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
9880b7a5 | 1245 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
42c2798b | 1246 | } |
9880b7a5 | 1247 | |
673a394b EA |
1248 | i915_gem_load(dev); |
1249 | ||
398c9cb2 KP |
1250 | /* Init HWS */ |
1251 | if (!I915_NEED_GFX_HWS(dev)) { | |
1252 | ret = i915_init_phys_hws(dev); | |
1253 | if (ret != 0) | |
9c9fe1f8 | 1254 | goto out_workqueue_free; |
398c9cb2 | 1255 | } |
ed4cb414 | 1256 | |
7662c8bd SL |
1257 | i915_get_mem_freq(dev); |
1258 | ||
ed4cb414 EA |
1259 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1260 | * integrated graphics even though the support isn't actually there | |
1261 | * according to the published specs. It doesn't appear to function | |
1262 | * correctly in testing on 945G. | |
1263 | * This may be a side effect of MSI having been made available for PEG | |
1264 | * and the registers being closely associated. | |
d1ed629f KP |
1265 | * |
1266 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1267 | * be lost or delayed, but we use them anyways to avoid |
1268 | * stuck interrupts on some machines. | |
ed4cb414 | 1269 | */ |
b60678a7 | 1270 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1271 | pci_enable_msi(dev->pdev); |
ed4cb414 EA |
1272 | |
1273 | spin_lock_init(&dev_priv->user_irq_lock); | |
63eeaf38 | 1274 | spin_lock_init(&dev_priv->error_lock); |
79e53945 | 1275 | dev_priv->user_irq_refcount = 0; |
ed4cb414 | 1276 | |
52440211 KP |
1277 | ret = drm_vblank_init(dev, I915_NUM_PIPE); |
1278 | ||
1279 | if (ret) { | |
1280 | (void) i915_driver_unload(dev); | |
1281 | return ret; | |
1282 | } | |
1283 | ||
79e53945 | 1284 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
2a34f5e6 | 1285 | ret = i915_load_modeset_init(dev, prealloc_size, agp_size); |
79e53945 JB |
1286 | if (ret < 0) { |
1287 | DRM_ERROR("failed to init modeset\n"); | |
9c9fe1f8 | 1288 | goto out_workqueue_free; |
79e53945 JB |
1289 | } |
1290 | } | |
1291 | ||
74a365b3 | 1292 | /* Must be done after probing outputs */ |
e170b030 ZW |
1293 | /* FIXME: verify on IGDNG */ |
1294 | if (!IS_IGDNG(dev)) | |
1295 | intel_opregion_init(dev, 0); | |
74a365b3 | 1296 | |
79e53945 JB |
1297 | return 0; |
1298 | ||
9c9fe1f8 EA |
1299 | out_workqueue_free: |
1300 | destroy_workqueue(dev_priv->wq); | |
6644107d VP |
1301 | out_iomapfree: |
1302 | io_mapping_free(dev_priv->mm.gtt_mapping); | |
79e53945 JB |
1303 | out_rmmap: |
1304 | iounmap(dev_priv->regs); | |
ec2a4c3f DA |
1305 | put_bridge: |
1306 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1307 | free_priv: |
9a298b2a | 1308 | kfree(dev_priv); |
ba8bbcf6 JB |
1309 | return ret; |
1310 | } | |
1311 | ||
1312 | int i915_driver_unload(struct drm_device *dev) | |
1313 | { | |
1314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1315 | ||
9c9fe1f8 EA |
1316 | destroy_workqueue(dev_priv->wq); |
1317 | ||
ab657db1 EA |
1318 | io_mapping_free(dev_priv->mm.gtt_mapping); |
1319 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
1320 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
1321 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
1322 | dev_priv->mm.gtt_mtrr = -1; | |
1323 | } | |
1324 | ||
79e53945 | 1325 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
79e53945 JB |
1326 | drm_irq_uninstall(dev); |
1327 | } | |
1328 | ||
ed4cb414 EA |
1329 | if (dev->pdev->msi_enabled) |
1330 | pci_disable_msi(dev->pdev); | |
1331 | ||
3043c60c EA |
1332 | if (dev_priv->regs != NULL) |
1333 | iounmap(dev_priv->regs); | |
ba8bbcf6 | 1334 | |
e170b030 ZW |
1335 | if (!IS_IGDNG(dev)) |
1336 | intel_opregion_free(dev, 0); | |
8ee1c3db | 1337 | |
79e53945 JB |
1338 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1339 | intel_modeset_cleanup(dev); | |
1340 | ||
71acb5eb DA |
1341 | i915_gem_free_all_phys_object(dev); |
1342 | ||
79e53945 JB |
1343 | mutex_lock(&dev->struct_mutex); |
1344 | i915_gem_cleanup_ringbuffer(dev); | |
1345 | mutex_unlock(&dev->struct_mutex); | |
1346 | drm_mm_takedown(&dev_priv->vram); | |
1347 | i915_gem_lastclose(dev); | |
1348 | } | |
1349 | ||
ec2a4c3f | 1350 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 1351 | kfree(dev->dev_private); |
ba8bbcf6 | 1352 | |
22eae947 DA |
1353 | return 0; |
1354 | } | |
1355 | ||
673a394b EA |
1356 | int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
1357 | { | |
1358 | struct drm_i915_file_private *i915_file_priv; | |
1359 | ||
8a4c47f3 | 1360 | DRM_DEBUG_DRIVER("\n"); |
673a394b | 1361 | i915_file_priv = (struct drm_i915_file_private *) |
9a298b2a | 1362 | kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); |
673a394b EA |
1363 | |
1364 | if (!i915_file_priv) | |
1365 | return -ENOMEM; | |
1366 | ||
1367 | file_priv->driver_priv = i915_file_priv; | |
1368 | ||
b962442e | 1369 | INIT_LIST_HEAD(&i915_file_priv->mm.request_list); |
673a394b EA |
1370 | |
1371 | return 0; | |
1372 | } | |
1373 | ||
79e53945 JB |
1374 | /** |
1375 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1376 | * @dev: DRM device | |
1377 | * | |
1378 | * Take care of cleaning up after all DRM clients have exited. In the | |
1379 | * mode setting case, we want to restore the kernel's initial mode (just | |
1380 | * in case the last client left us in a bad state). | |
1381 | * | |
1382 | * Additionally, in the non-mode setting case, we'll tear down the AGP | |
1383 | * and DMA structures, since the kernel won't be using them, and clea | |
1384 | * up any GEM state. | |
1385 | */ | |
84b1fd10 | 1386 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1387 | { |
ba8bbcf6 JB |
1388 | drm_i915_private_t *dev_priv = dev->dev_private; |
1389 | ||
79e53945 | 1390 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
785b93ef | 1391 | drm_fb_helper_restore(); |
144a75fa | 1392 | return; |
79e53945 | 1393 | } |
144a75fa | 1394 | |
673a394b EA |
1395 | i915_gem_lastclose(dev); |
1396 | ||
ba8bbcf6 | 1397 | if (dev_priv->agp_heap) |
b5e89ed5 | 1398 | i915_mem_takedown(&(dev_priv->agp_heap)); |
ba8bbcf6 | 1399 | |
b5e89ed5 | 1400 | i915_dma_cleanup(dev); |
1da177e4 LT |
1401 | } |
1402 | ||
6c340eac | 1403 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1404 | { |
ba8bbcf6 | 1405 | drm_i915_private_t *dev_priv = dev->dev_private; |
b962442e | 1406 | i915_gem_release(dev, file_priv); |
79e53945 JB |
1407 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
1408 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); | |
1da177e4 LT |
1409 | } |
1410 | ||
673a394b EA |
1411 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) |
1412 | { | |
1413 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
1414 | ||
9a298b2a | 1415 | kfree(i915_file_priv); |
673a394b EA |
1416 | } |
1417 | ||
c153f45f EA |
1418 | struct drm_ioctl_desc i915_ioctls[] = { |
1419 | DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1420 | DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1421 | DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1422 | DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1423 | DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1424 | DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
1425 | DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), | |
1426 | DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1427 | DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), | |
1428 | DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), | |
1429 | DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1430 | DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), | |
1431 | DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1432 | DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1433 | DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), | |
1434 | DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
4b408939 | 1435 | DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2bdf00b2 | 1436 | DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
673a394b EA |
1437 | DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), |
1438 | DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1439 | DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1440 | DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), | |
1441 | DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), | |
2bdf00b2 DA |
1442 | DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1443 | DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
673a394b EA |
1444 | DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), |
1445 | DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), | |
1446 | DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), | |
1447 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), | |
de151cf6 | 1448 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0), |
673a394b EA |
1449 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), |
1450 | DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), | |
1451 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), | |
1452 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), | |
5a125c3c | 1453 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0), |
08d7b3d1 | 1454 | DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), |
c94f7029 DA |
1455 | }; |
1456 | ||
1457 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
1458 | |
1459 | /** | |
1460 | * Determine if the device really is AGP or not. | |
1461 | * | |
1462 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
1463 | * PCI-e. | |
1464 | * | |
1465 | * \param dev The device to be tested. | |
1466 | * | |
1467 | * \returns | |
1468 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
1469 | */ | |
84b1fd10 | 1470 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1471 | { |
1472 | return 1; | |
1473 | } |