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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | ||
1da177e4 LT |
34 | /* Really want an OS-independent resettable timer. Would like to have |
35 | * this loop run for (eg) 3 sec, but have the timer reset every time | |
36 | * the head pointer changes, so that EBUSY only happens if the ring | |
37 | * actually stalls for (eg) 3 seconds. | |
38 | */ | |
84b1fd10 | 39 | int i915_wait_ring(struct drm_device * dev, int n, const char *caller) |
1da177e4 LT |
40 | { |
41 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
d3a6d446 KP |
43 | u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; |
44 | u32 last_acthd = I915_READ(acthd_reg); | |
45 | u32 acthd; | |
585fb111 | 46 | u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
1da177e4 LT |
47 | int i; |
48 | ||
d3a6d446 | 49 | for (i = 0; i < 100000; i++) { |
585fb111 | 50 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
d3a6d446 | 51 | acthd = I915_READ(acthd_reg); |
1da177e4 LT |
52 | ring->space = ring->head - (ring->tail + 8); |
53 | if (ring->space < 0) | |
54 | ring->space += ring->Size; | |
55 | if (ring->space >= n) | |
56 | return 0; | |
57 | ||
58 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
59 | ||
60 | if (ring->head != last_head) | |
61 | i = 0; | |
d3a6d446 KP |
62 | if (acthd != last_acthd) |
63 | i = 0; | |
1da177e4 LT |
64 | |
65 | last_head = ring->head; | |
d3a6d446 KP |
66 | last_acthd = acthd; |
67 | msleep_interruptible(10); | |
68 | ||
1da177e4 LT |
69 | } |
70 | ||
20caafa6 | 71 | return -EBUSY; |
1da177e4 LT |
72 | } |
73 | ||
398c9cb2 KP |
74 | /** |
75 | * Sets up the hardware status page for devices that need a physical address | |
76 | * in the register. | |
77 | */ | |
78 | int i915_init_phys_hws(struct drm_device *dev) | |
79 | { | |
80 | drm_i915_private_t *dev_priv = dev->dev_private; | |
81 | /* Program Hardware Status Page */ | |
82 | dev_priv->status_page_dmah = | |
83 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); | |
84 | ||
85 | if (!dev_priv->status_page_dmah) { | |
86 | DRM_ERROR("Can not allocate hardware status page\n"); | |
87 | return -ENOMEM; | |
88 | } | |
89 | dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; | |
90 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | |
91 | ||
92 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
93 | ||
94 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); | |
95 | DRM_DEBUG("Enabled hardware status page\n"); | |
96 | return 0; | |
97 | } | |
98 | ||
99 | /** | |
100 | * Frees the hardware status page, whether it's a physical address or a virtual | |
101 | * address set up by the X Server. | |
102 | */ | |
103 | void i915_free_hws(struct drm_device *dev) | |
104 | { | |
105 | drm_i915_private_t *dev_priv = dev->dev_private; | |
106 | if (dev_priv->status_page_dmah) { | |
107 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
108 | dev_priv->status_page_dmah = NULL; | |
109 | } | |
110 | ||
111 | if (dev_priv->status_gfx_addr) { | |
112 | dev_priv->status_gfx_addr = 0; | |
113 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | |
114 | } | |
115 | ||
116 | /* Need to rewrite hardware status page */ | |
117 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
118 | } | |
119 | ||
84b1fd10 | 120 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
121 | { |
122 | drm_i915_private_t *dev_priv = dev->dev_private; | |
123 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
124 | ||
585fb111 JB |
125 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
126 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
1da177e4 LT |
127 | ring->space = ring->head - (ring->tail + 8); |
128 | if (ring->space < 0) | |
129 | ring->space += ring->Size; | |
130 | ||
131 | if (ring->head == ring->tail) | |
132 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
133 | } | |
134 | ||
84b1fd10 | 135 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 136 | { |
ba8bbcf6 | 137 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
138 | /* Make sure interrupts are disabled here because the uninstall ioctl |
139 | * may not have been called from userspace and after dev_private | |
140 | * is freed, it's too late. | |
141 | */ | |
ed4cb414 | 142 | if (dev->irq_enabled) |
b5e89ed5 | 143 | drm_irq_uninstall(dev); |
1da177e4 | 144 | |
ba8bbcf6 JB |
145 | if (dev_priv->ring.virtual_start) { |
146 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
147 | dev_priv->ring.virtual_start = 0; | |
148 | dev_priv->ring.map.handle = 0; | |
149 | dev_priv->ring.map.size = 0; | |
150 | } | |
dc7a9319 | 151 | |
398c9cb2 KP |
152 | /* Clear the HWS virtual address at teardown */ |
153 | if (I915_NEED_GFX_HWS(dev)) | |
154 | i915_free_hws(dev); | |
1da177e4 LT |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
ba8bbcf6 | 159 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 160 | { |
ba8bbcf6 | 161 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 | 162 | |
da509d7a | 163 | dev_priv->sarea = drm_getsarea(dev); |
1da177e4 LT |
164 | if (!dev_priv->sarea) { |
165 | DRM_ERROR("can not find sarea!\n"); | |
1da177e4 | 166 | i915_dma_cleanup(dev); |
20caafa6 | 167 | return -EINVAL; |
1da177e4 LT |
168 | } |
169 | ||
1da177e4 LT |
170 | dev_priv->sarea_priv = (drm_i915_sarea_t *) |
171 | ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); | |
172 | ||
173 | dev_priv->ring.Start = init->ring_start; | |
174 | dev_priv->ring.End = init->ring_end; | |
175 | dev_priv->ring.Size = init->ring_size; | |
176 | dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; | |
177 | ||
178 | dev_priv->ring.map.offset = init->ring_start; | |
179 | dev_priv->ring.map.size = init->ring_size; | |
180 | dev_priv->ring.map.type = 0; | |
181 | dev_priv->ring.map.flags = 0; | |
182 | dev_priv->ring.map.mtrr = 0; | |
183 | ||
b5e89ed5 | 184 | drm_core_ioremap(&dev_priv->ring.map, dev); |
1da177e4 LT |
185 | |
186 | if (dev_priv->ring.map.handle == NULL) { | |
1da177e4 LT |
187 | i915_dma_cleanup(dev); |
188 | DRM_ERROR("can not ioremap virtual address for" | |
189 | " ring buffer\n"); | |
20caafa6 | 190 | return -ENOMEM; |
1da177e4 LT |
191 | } |
192 | ||
193 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
194 | ||
a6b54f3f | 195 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
196 | dev_priv->back_offset = init->back_offset; |
197 | dev_priv->front_offset = init->front_offset; | |
198 | dev_priv->current_page = 0; | |
199 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; | |
200 | ||
1da177e4 LT |
201 | /* Allow hardware batchbuffers unless told otherwise. |
202 | */ | |
203 | dev_priv->allow_batchbuffer = 1; | |
204 | ||
1da177e4 LT |
205 | return 0; |
206 | } | |
207 | ||
84b1fd10 | 208 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
209 | { |
210 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
211 | ||
bf9d8929 | 212 | DRM_DEBUG("%s\n", __func__); |
1da177e4 LT |
213 | |
214 | if (!dev_priv->sarea) { | |
215 | DRM_ERROR("can not find sarea!\n"); | |
20caafa6 | 216 | return -EINVAL; |
1da177e4 LT |
217 | } |
218 | ||
1da177e4 LT |
219 | if (dev_priv->ring.map.handle == NULL) { |
220 | DRM_ERROR("can not ioremap virtual address for" | |
221 | " ring buffer\n"); | |
20caafa6 | 222 | return -ENOMEM; |
1da177e4 LT |
223 | } |
224 | ||
225 | /* Program Hardware Status Page */ | |
226 | if (!dev_priv->hw_status_page) { | |
227 | DRM_ERROR("Can not find hardware status page\n"); | |
20caafa6 | 228 | return -EINVAL; |
1da177e4 LT |
229 | } |
230 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); | |
231 | ||
dc7a9319 | 232 | if (dev_priv->status_gfx_addr != 0) |
585fb111 | 233 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
dc7a9319 | 234 | else |
585fb111 | 235 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
1da177e4 LT |
236 | DRM_DEBUG("Enabled hardware status page\n"); |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
c153f45f EA |
241 | static int i915_dma_init(struct drm_device *dev, void *data, |
242 | struct drm_file *file_priv) | |
1da177e4 | 243 | { |
c153f45f | 244 | drm_i915_init_t *init = data; |
1da177e4 LT |
245 | int retcode = 0; |
246 | ||
c153f45f | 247 | switch (init->func) { |
1da177e4 | 248 | case I915_INIT_DMA: |
ba8bbcf6 | 249 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
250 | break; |
251 | case I915_CLEANUP_DMA: | |
252 | retcode = i915_dma_cleanup(dev); | |
253 | break; | |
254 | case I915_RESUME_DMA: | |
0d6aa60b | 255 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
256 | break; |
257 | default: | |
20caafa6 | 258 | retcode = -EINVAL; |
1da177e4 LT |
259 | break; |
260 | } | |
261 | ||
262 | return retcode; | |
263 | } | |
264 | ||
265 | /* Implement basically the same security restrictions as hardware does | |
266 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
267 | * | |
268 | * Most of the calculations below involve calculating the size of a | |
269 | * particular instruction. It's important to get the size right as | |
270 | * that tells us where the next instruction to check is. Any illegal | |
271 | * instruction detected will be given a size of zero, which is a | |
272 | * signal to abort the rest of the buffer. | |
273 | */ | |
274 | static int do_validate_cmd(int cmd) | |
275 | { | |
276 | switch (((cmd >> 29) & 0x7)) { | |
277 | case 0x0: | |
278 | switch ((cmd >> 23) & 0x3f) { | |
279 | case 0x0: | |
280 | return 1; /* MI_NOOP */ | |
281 | case 0x4: | |
282 | return 1; /* MI_FLUSH */ | |
283 | default: | |
284 | return 0; /* disallow everything else */ | |
285 | } | |
286 | break; | |
287 | case 0x1: | |
288 | return 0; /* reserved */ | |
289 | case 0x2: | |
290 | return (cmd & 0xff) + 2; /* 2d commands */ | |
291 | case 0x3: | |
292 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
293 | return 1; | |
294 | ||
295 | switch ((cmd >> 24) & 0x1f) { | |
296 | case 0x1c: | |
297 | return 1; | |
298 | case 0x1d: | |
b5e89ed5 | 299 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
300 | case 0x3: |
301 | return (cmd & 0x1f) + 2; | |
302 | case 0x4: | |
303 | return (cmd & 0xf) + 2; | |
304 | default: | |
305 | return (cmd & 0xffff) + 2; | |
306 | } | |
307 | case 0x1e: | |
308 | if (cmd & (1 << 23)) | |
309 | return (cmd & 0xffff) + 1; | |
310 | else | |
311 | return 1; | |
312 | case 0x1f: | |
313 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
314 | return (cmd & 0x1ffff) + 2; | |
315 | else if (cmd & (1 << 17)) /* indirect random */ | |
316 | if ((cmd & 0xffff) == 0) | |
317 | return 0; /* unknown length, too hard */ | |
318 | else | |
319 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
320 | else | |
321 | return 2; /* indirect sequential */ | |
322 | default: | |
323 | return 0; | |
324 | } | |
325 | default: | |
326 | return 0; | |
327 | } | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | static int validate_cmd(int cmd) | |
333 | { | |
334 | int ret = do_validate_cmd(cmd); | |
335 | ||
bc5f4523 | 336 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ |
1da177e4 LT |
337 | |
338 | return ret; | |
339 | } | |
340 | ||
84b1fd10 | 341 | static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords) |
1da177e4 LT |
342 | { |
343 | drm_i915_private_t *dev_priv = dev->dev_private; | |
344 | int i; | |
345 | RING_LOCALS; | |
346 | ||
de227f5f | 347 | if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) |
20caafa6 | 348 | return -EINVAL; |
de227f5f | 349 | |
c29b669c | 350 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 351 | |
1da177e4 LT |
352 | for (i = 0; i < dwords;) { |
353 | int cmd, sz; | |
354 | ||
355 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) | |
20caafa6 | 356 | return -EINVAL; |
1da177e4 | 357 | |
1da177e4 | 358 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
20caafa6 | 359 | return -EINVAL; |
1da177e4 | 360 | |
1da177e4 LT |
361 | OUT_RING(cmd); |
362 | ||
363 | while (++i, --sz) { | |
364 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], | |
365 | sizeof(cmd))) { | |
20caafa6 | 366 | return -EINVAL; |
1da177e4 LT |
367 | } |
368 | OUT_RING(cmd); | |
369 | } | |
1da177e4 LT |
370 | } |
371 | ||
de227f5f DA |
372 | if (dwords & 1) |
373 | OUT_RING(0); | |
374 | ||
375 | ADVANCE_LP_RING(); | |
376 | ||
1da177e4 LT |
377 | return 0; |
378 | } | |
379 | ||
84b1fd10 | 380 | static int i915_emit_box(struct drm_device * dev, |
c60ce623 | 381 | struct drm_clip_rect __user * boxes, |
1da177e4 LT |
382 | int i, int DR1, int DR4) |
383 | { | |
384 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 385 | struct drm_clip_rect box; |
1da177e4 LT |
386 | RING_LOCALS; |
387 | ||
388 | if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { | |
20caafa6 | 389 | return -EFAULT; |
1da177e4 LT |
390 | } |
391 | ||
392 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { | |
393 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
394 | box.x1, box.y1, box.x2, box.y2); | |
20caafa6 | 395 | return -EINVAL; |
1da177e4 LT |
396 | } |
397 | ||
c29b669c AH |
398 | if (IS_I965G(dev)) { |
399 | BEGIN_LP_RING(4); | |
400 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
401 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 402 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
403 | OUT_RING(DR4); |
404 | ADVANCE_LP_RING(); | |
405 | } else { | |
406 | BEGIN_LP_RING(6); | |
407 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
408 | OUT_RING(DR1); | |
409 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
410 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
411 | OUT_RING(DR4); | |
412 | OUT_RING(0); | |
413 | ADVANCE_LP_RING(); | |
414 | } | |
1da177e4 LT |
415 | |
416 | return 0; | |
417 | } | |
418 | ||
c29b669c AH |
419 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
420 | * emit. For now, do it in both places: | |
421 | */ | |
422 | ||
84b1fd10 | 423 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
424 | { |
425 | drm_i915_private_t *dev_priv = dev->dev_private; | |
426 | RING_LOCALS; | |
427 | ||
af6061af | 428 | dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter; |
c29b669c | 429 | |
af6061af DA |
430 | if (dev_priv->counter > 0x7FFFFFFFUL) |
431 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; | |
de227f5f DA |
432 | |
433 | BEGIN_LP_RING(4); | |
585fb111 JB |
434 | OUT_RING(MI_STORE_DWORD_INDEX); |
435 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); | |
de227f5f DA |
436 | OUT_RING(dev_priv->counter); |
437 | OUT_RING(0); | |
438 | ADVANCE_LP_RING(); | |
439 | } | |
440 | ||
84b1fd10 | 441 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
1da177e4 LT |
442 | drm_i915_cmdbuffer_t * cmd) |
443 | { | |
444 | int nbox = cmd->num_cliprects; | |
445 | int i = 0, count, ret; | |
446 | ||
447 | if (cmd->sz & 0x3) { | |
448 | DRM_ERROR("alignment"); | |
20caafa6 | 449 | return -EINVAL; |
1da177e4 LT |
450 | } |
451 | ||
452 | i915_kernel_lost_context(dev); | |
453 | ||
454 | count = nbox ? nbox : 1; | |
455 | ||
456 | for (i = 0; i < count; i++) { | |
457 | if (i < nbox) { | |
458 | ret = i915_emit_box(dev, cmd->cliprects, i, | |
459 | cmd->DR1, cmd->DR4); | |
460 | if (ret) | |
461 | return ret; | |
462 | } | |
463 | ||
464 | ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); | |
465 | if (ret) | |
466 | return ret; | |
467 | } | |
468 | ||
de227f5f | 469 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
470 | return 0; |
471 | } | |
472 | ||
84b1fd10 | 473 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
1da177e4 LT |
474 | drm_i915_batchbuffer_t * batch) |
475 | { | |
476 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 477 | struct drm_clip_rect __user *boxes = batch->cliprects; |
1da177e4 LT |
478 | int nbox = batch->num_cliprects; |
479 | int i = 0, count; | |
480 | RING_LOCALS; | |
481 | ||
482 | if ((batch->start | batch->used) & 0x7) { | |
483 | DRM_ERROR("alignment"); | |
20caafa6 | 484 | return -EINVAL; |
1da177e4 LT |
485 | } |
486 | ||
487 | i915_kernel_lost_context(dev); | |
488 | ||
489 | count = nbox ? nbox : 1; | |
490 | ||
491 | for (i = 0; i < count; i++) { | |
492 | if (i < nbox) { | |
493 | int ret = i915_emit_box(dev, boxes, i, | |
494 | batch->DR1, batch->DR4); | |
495 | if (ret) | |
496 | return ret; | |
497 | } | |
498 | ||
0790d5e1 | 499 | if (!IS_I830(dev) && !IS_845G(dev)) { |
1da177e4 | 500 | BEGIN_LP_RING(2); |
21f16289 DA |
501 | if (IS_I965G(dev)) { |
502 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
503 | OUT_RING(batch->start); | |
504 | } else { | |
505 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
506 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
507 | } | |
1da177e4 LT |
508 | ADVANCE_LP_RING(); |
509 | } else { | |
510 | BEGIN_LP_RING(4); | |
511 | OUT_RING(MI_BATCH_BUFFER); | |
512 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
513 | OUT_RING(batch->start + batch->used - 4); | |
514 | OUT_RING(0); | |
515 | ADVANCE_LP_RING(); | |
516 | } | |
517 | } | |
518 | ||
de227f5f | 519 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
520 | |
521 | return 0; | |
522 | } | |
523 | ||
af6061af | 524 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
525 | { |
526 | drm_i915_private_t *dev_priv = dev->dev_private; | |
527 | RING_LOCALS; | |
528 | ||
af6061af | 529 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", |
80a914dc | 530 | __func__, |
af6061af DA |
531 | dev_priv->current_page, |
532 | dev_priv->sarea_priv->pf_current_page); | |
1da177e4 | 533 | |
af6061af DA |
534 | i915_kernel_lost_context(dev); |
535 | ||
536 | BEGIN_LP_RING(2); | |
585fb111 | 537 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af DA |
538 | OUT_RING(0); |
539 | ADVANCE_LP_RING(); | |
1da177e4 | 540 | |
af6061af DA |
541 | BEGIN_LP_RING(6); |
542 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
543 | OUT_RING(0); | |
544 | if (dev_priv->current_page == 0) { | |
545 | OUT_RING(dev_priv->back_offset); | |
546 | dev_priv->current_page = 1; | |
1da177e4 | 547 | } else { |
af6061af DA |
548 | OUT_RING(dev_priv->front_offset); |
549 | dev_priv->current_page = 0; | |
1da177e4 | 550 | } |
af6061af DA |
551 | OUT_RING(0); |
552 | ADVANCE_LP_RING(); | |
1da177e4 | 553 | |
af6061af DA |
554 | BEGIN_LP_RING(2); |
555 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
556 | OUT_RING(0); | |
557 | ADVANCE_LP_RING(); | |
1da177e4 | 558 | |
af6061af | 559 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 LT |
560 | |
561 | BEGIN_LP_RING(4); | |
585fb111 JB |
562 | OUT_RING(MI_STORE_DWORD_INDEX); |
563 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); | |
af6061af DA |
564 | OUT_RING(dev_priv->counter); |
565 | OUT_RING(0); | |
1da177e4 LT |
566 | ADVANCE_LP_RING(); |
567 | ||
af6061af DA |
568 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
569 | return 0; | |
1da177e4 LT |
570 | } |
571 | ||
84b1fd10 | 572 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
573 | { |
574 | drm_i915_private_t *dev_priv = dev->dev_private; | |
575 | ||
576 | i915_kernel_lost_context(dev); | |
bf9d8929 | 577 | return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); |
1da177e4 LT |
578 | } |
579 | ||
c153f45f EA |
580 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
581 | struct drm_file *file_priv) | |
1da177e4 | 582 | { |
6c340eac | 583 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 LT |
584 | |
585 | return i915_quiescent(dev); | |
586 | } | |
587 | ||
c153f45f EA |
588 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
589 | struct drm_file *file_priv) | |
1da177e4 | 590 | { |
1da177e4 | 591 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
af6061af | 592 | u32 *hw_status = dev_priv->hw_status_page; |
1da177e4 LT |
593 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
594 | dev_priv->sarea_priv; | |
c153f45f | 595 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 LT |
596 | int ret; |
597 | ||
598 | if (!dev_priv->allow_batchbuffer) { | |
599 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 600 | return -EINVAL; |
1da177e4 LT |
601 | } |
602 | ||
1da177e4 | 603 | DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", |
c153f45f | 604 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 605 | |
6c340eac | 606 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 607 | |
c153f45f EA |
608 | if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, |
609 | batch->num_cliprects * | |
c60ce623 | 610 | sizeof(struct drm_clip_rect))) |
20caafa6 | 611 | return -EFAULT; |
1da177e4 | 612 | |
c153f45f | 613 | ret = i915_dispatch_batchbuffer(dev, batch); |
1da177e4 | 614 | |
af6061af | 615 | sarea_priv->last_dispatch = (int)hw_status[5]; |
1da177e4 LT |
616 | return ret; |
617 | } | |
618 | ||
c153f45f EA |
619 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
620 | struct drm_file *file_priv) | |
1da177e4 | 621 | { |
1da177e4 | 622 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
af6061af | 623 | u32 *hw_status = dev_priv->hw_status_page; |
1da177e4 LT |
624 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
625 | dev_priv->sarea_priv; | |
c153f45f | 626 | drm_i915_cmdbuffer_t *cmdbuf = data; |
1da177e4 LT |
627 | int ret; |
628 | ||
1da177e4 | 629 | DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
c153f45f | 630 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 631 | |
6c340eac | 632 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 633 | |
c153f45f EA |
634 | if (cmdbuf->num_cliprects && |
635 | DRM_VERIFYAREA_READ(cmdbuf->cliprects, | |
636 | cmdbuf->num_cliprects * | |
c60ce623 | 637 | sizeof(struct drm_clip_rect))) { |
1da177e4 | 638 | DRM_ERROR("Fault accessing cliprects\n"); |
20caafa6 | 639 | return -EFAULT; |
1da177e4 LT |
640 | } |
641 | ||
c153f45f | 642 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf); |
1da177e4 LT |
643 | if (ret) { |
644 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
645 | return ret; | |
646 | } | |
647 | ||
af6061af | 648 | sarea_priv->last_dispatch = (int)hw_status[5]; |
1da177e4 LT |
649 | return 0; |
650 | } | |
651 | ||
c153f45f EA |
652 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
653 | struct drm_file *file_priv) | |
1da177e4 | 654 | { |
80a914dc | 655 | DRM_DEBUG("%s\n", __func__); |
1da177e4 | 656 | |
6c340eac | 657 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 658 | |
af6061af | 659 | return i915_dispatch_flip(dev); |
1da177e4 LT |
660 | } |
661 | ||
c153f45f EA |
662 | static int i915_getparam(struct drm_device *dev, void *data, |
663 | struct drm_file *file_priv) | |
1da177e4 | 664 | { |
1da177e4 | 665 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 666 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
667 | int value; |
668 | ||
669 | if (!dev_priv) { | |
3e684eae | 670 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 671 | return -EINVAL; |
1da177e4 LT |
672 | } |
673 | ||
c153f45f | 674 | switch (param->param) { |
1da177e4 | 675 | case I915_PARAM_IRQ_ACTIVE: |
ed4cb414 | 676 | value = dev->irq_enabled; |
1da177e4 LT |
677 | break; |
678 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
679 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
680 | break; | |
0d6aa60b DA |
681 | case I915_PARAM_LAST_DISPATCH: |
682 | value = READ_BREADCRUMB(dev_priv); | |
683 | break; | |
1da177e4 | 684 | default: |
c153f45f | 685 | DRM_ERROR("Unknown parameter %d\n", param->param); |
20caafa6 | 686 | return -EINVAL; |
1da177e4 LT |
687 | } |
688 | ||
c153f45f | 689 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 690 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 691 | return -EFAULT; |
1da177e4 LT |
692 | } |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
c153f45f EA |
697 | static int i915_setparam(struct drm_device *dev, void *data, |
698 | struct drm_file *file_priv) | |
1da177e4 | 699 | { |
1da177e4 | 700 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 701 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
702 | |
703 | if (!dev_priv) { | |
3e684eae | 704 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 705 | return -EINVAL; |
1da177e4 LT |
706 | } |
707 | ||
c153f45f | 708 | switch (param->param) { |
1da177e4 | 709 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
710 | break; |
711 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 712 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
713 | break; |
714 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 715 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 LT |
716 | break; |
717 | default: | |
c153f45f | 718 | DRM_ERROR("unknown parameter %d\n", param->param); |
20caafa6 | 719 | return -EINVAL; |
1da177e4 LT |
720 | } |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
c153f45f EA |
725 | static int i915_set_status_page(struct drm_device *dev, void *data, |
726 | struct drm_file *file_priv) | |
dc7a9319 | 727 | { |
dc7a9319 | 728 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 729 | drm_i915_hws_addr_t *hws = data; |
b39d50e5 ZW |
730 | |
731 | if (!I915_NEED_GFX_HWS(dev)) | |
732 | return -EINVAL; | |
dc7a9319 WZ |
733 | |
734 | if (!dev_priv) { | |
3e684eae | 735 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 736 | return -EINVAL; |
dc7a9319 | 737 | } |
dc7a9319 | 738 | |
c153f45f EA |
739 | printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr); |
740 | ||
741 | dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); | |
dc7a9319 | 742 | |
8b409580 | 743 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
744 | dev_priv->hws_map.size = 4*1024; |
745 | dev_priv->hws_map.type = 0; | |
746 | dev_priv->hws_map.flags = 0; | |
747 | dev_priv->hws_map.mtrr = 0; | |
748 | ||
749 | drm_core_ioremap(&dev_priv->hws_map, dev); | |
750 | if (dev_priv->hws_map.handle == NULL) { | |
dc7a9319 WZ |
751 | i915_dma_cleanup(dev); |
752 | dev_priv->status_gfx_addr = 0; | |
753 | DRM_ERROR("can not ioremap virtual address for" | |
754 | " G33 hw status page\n"); | |
20caafa6 | 755 | return -ENOMEM; |
dc7a9319 WZ |
756 | } |
757 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | |
758 | ||
759 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
585fb111 JB |
760 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
761 | DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", | |
dc7a9319 WZ |
762 | dev_priv->status_gfx_addr); |
763 | DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); | |
764 | return 0; | |
765 | } | |
766 | ||
84b1fd10 | 767 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 768 | { |
ba8bbcf6 JB |
769 | struct drm_i915_private *dev_priv = dev->dev_private; |
770 | unsigned long base, size; | |
771 | int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; | |
772 | ||
22eae947 DA |
773 | /* i915 has 4 more counters */ |
774 | dev->counters += 4; | |
775 | dev->types[6] = _DRM_STAT_IRQ; | |
776 | dev->types[7] = _DRM_STAT_PRIMARY; | |
777 | dev->types[8] = _DRM_STAT_SECONDARY; | |
778 | dev->types[9] = _DRM_STAT_DMA; | |
779 | ||
ba8bbcf6 JB |
780 | dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); |
781 | if (dev_priv == NULL) | |
782 | return -ENOMEM; | |
783 | ||
784 | memset(dev_priv, 0, sizeof(drm_i915_private_t)); | |
785 | ||
786 | dev->dev_private = (void *)dev_priv; | |
787 | ||
788 | /* Add register map (needed for suspend/resume) */ | |
789 | base = drm_get_resource_start(dev, mmio_bar); | |
790 | size = drm_get_resource_len(dev, mmio_bar); | |
791 | ||
e3236a11 DA |
792 | ret = drm_addmap(dev, base, size, _DRM_REGISTERS, |
793 | _DRM_KERNEL | _DRM_DRIVER, | |
ba8bbcf6 | 794 | &dev_priv->mmio_map); |
ed4cb414 | 795 | |
398c9cb2 KP |
796 | /* Init HWS */ |
797 | if (!I915_NEED_GFX_HWS(dev)) { | |
798 | ret = i915_init_phys_hws(dev); | |
799 | if (ret != 0) | |
800 | return ret; | |
801 | } | |
ed4cb414 EA |
802 | |
803 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
804 | * integrated graphics even though the support isn't actually there | |
805 | * according to the published specs. It doesn't appear to function | |
806 | * correctly in testing on 945G. | |
807 | * This may be a side effect of MSI having been made available for PEG | |
808 | * and the registers being closely associated. | |
809 | */ | |
810 | if (!IS_I945G(dev) && !IS_I945GM(dev)) | |
811 | pci_enable_msi(dev->pdev); | |
812 | ||
813 | spin_lock_init(&dev_priv->user_irq_lock); | |
814 | ||
ba8bbcf6 JB |
815 | return ret; |
816 | } | |
817 | ||
818 | int i915_driver_unload(struct drm_device *dev) | |
819 | { | |
820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821 | ||
ed4cb414 EA |
822 | if (dev->pdev->msi_enabled) |
823 | pci_disable_msi(dev->pdev); | |
824 | ||
398c9cb2 KP |
825 | i915_free_hws(dev); |
826 | ||
ba8bbcf6 JB |
827 | if (dev_priv->mmio_map) |
828 | drm_rmmap(dev, dev_priv->mmio_map); | |
829 | ||
830 | drm_free(dev->dev_private, sizeof(drm_i915_private_t), | |
831 | DRM_MEM_DRIVER); | |
832 | ||
22eae947 DA |
833 | return 0; |
834 | } | |
835 | ||
84b1fd10 | 836 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 837 | { |
ba8bbcf6 JB |
838 | drm_i915_private_t *dev_priv = dev->dev_private; |
839 | ||
144a75fa DA |
840 | if (!dev_priv) |
841 | return; | |
842 | ||
ba8bbcf6 | 843 | if (dev_priv->agp_heap) |
b5e89ed5 | 844 | i915_mem_takedown(&(dev_priv->agp_heap)); |
ba8bbcf6 | 845 | |
b5e89ed5 | 846 | i915_dma_cleanup(dev); |
1da177e4 LT |
847 | } |
848 | ||
6c340eac | 849 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 850 | { |
ba8bbcf6 JB |
851 | drm_i915_private_t *dev_priv = dev->dev_private; |
852 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); | |
1da177e4 LT |
853 | } |
854 | ||
c153f45f EA |
855 | struct drm_ioctl_desc i915_ioctls[] = { |
856 | DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
857 | DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
858 | DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
859 | DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
860 | DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
861 | DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
862 | DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), | |
863 | DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
864 | DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), | |
865 | DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), | |
866 | DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
867 | DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), | |
868 | DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
869 | DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
870 | DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), | |
871 | DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
872 | DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH), | |
c94f7029 DA |
873 | }; |
874 | ||
875 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
876 | |
877 | /** | |
878 | * Determine if the device really is AGP or not. | |
879 | * | |
880 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
881 | * PCI-e. | |
882 | * | |
883 | * \param dev The device to be tested. | |
884 | * | |
885 | * \returns | |
886 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
887 | */ | |
84b1fd10 | 888 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
889 | { |
890 | return 1; | |
891 | } |