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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
79e53945 | 31 | #include "drm_crtc_helper.h" |
785b93ef | 32 | #include "drm_fb_helper.h" |
79e53945 | 33 | #include "intel_drv.h" |
1da177e4 LT |
34 | #include "i915_drm.h" |
35 | #include "i915_drv.h" | |
1c5d22f7 | 36 | #include "i915_trace.h" |
63ee41d7 | 37 | #include "../../../platform/x86/intel_ips.h" |
dcdb1674 | 38 | #include <linux/pci.h> |
28d52043 | 39 | #include <linux/vgaarb.h> |
c4804411 ZW |
40 | #include <linux/acpi.h> |
41 | #include <linux/pnp.h> | |
6a9ee8af | 42 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
e0cd3608 | 44 | #include <linux/module.h> |
44834a67 | 45 | #include <acpi/video.h> |
9e984bc1 | 46 | #include <asm/pat.h> |
1da177e4 | 47 | |
4cbf74cc CW |
48 | static void i915_write_hws_pga(struct drm_device *dev) |
49 | { | |
50 | drm_i915_private_t *dev_priv = dev->dev_private; | |
51 | u32 addr; | |
52 | ||
53 | addr = dev_priv->status_page_dmah->busaddr; | |
54 | if (INTEL_INFO(dev)->gen >= 4) | |
55 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
56 | I915_WRITE(HWS_PGA, addr); | |
57 | } | |
58 | ||
398c9cb2 KP |
59 | /** |
60 | * Sets up the hardware status page for devices that need a physical address | |
61 | * in the register. | |
62 | */ | |
3043c60c | 63 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
64 | { |
65 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 66 | |
398c9cb2 KP |
67 | /* Program Hardware Status Page */ |
68 | dev_priv->status_page_dmah = | |
e6be8d9d | 69 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
398c9cb2 KP |
70 | |
71 | if (!dev_priv->status_page_dmah) { | |
72 | DRM_ERROR("Can not allocate hardware status page\n"); | |
73 | return -ENOMEM; | |
74 | } | |
398c9cb2 | 75 | |
f3234706 KP |
76 | memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr, |
77 | 0, PAGE_SIZE); | |
398c9cb2 | 78 | |
4cbf74cc | 79 | i915_write_hws_pga(dev); |
9b974cc1 | 80 | |
8a4c47f3 | 81 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
398c9cb2 KP |
82 | return 0; |
83 | } | |
84 | ||
85 | /** | |
86 | * Frees the hardware status page, whether it's a physical address or a virtual | |
87 | * address set up by the X Server. | |
88 | */ | |
3043c60c | 89 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
90 | { |
91 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 CW |
92 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
93 | ||
398c9cb2 KP |
94 | if (dev_priv->status_page_dmah) { |
95 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
96 | dev_priv->status_page_dmah = NULL; | |
97 | } | |
98 | ||
1ec14ad3 CW |
99 | if (ring->status_page.gfx_addr) { |
100 | ring->status_page.gfx_addr = 0; | |
398c9cb2 KP |
101 | drm_core_ioremapfree(&dev_priv->hws_map, dev); |
102 | } | |
103 | ||
104 | /* Need to rewrite hardware status page */ | |
105 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
106 | } | |
107 | ||
84b1fd10 | 108 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
109 | { |
110 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 111 | struct drm_i915_master_private *master_priv; |
1ec14ad3 | 112 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 113 | |
79e53945 JB |
114 | /* |
115 | * We should never lose context on the ring with modesetting | |
116 | * as we don't expose it to userspace | |
117 | */ | |
118 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
119 | return; | |
120 | ||
8168bd48 CW |
121 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
122 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
1da177e4 LT |
123 | ring->space = ring->head - (ring->tail + 8); |
124 | if (ring->space < 0) | |
8187a2b7 | 125 | ring->space += ring->size; |
1da177e4 | 126 | |
7c1c2871 DA |
127 | if (!dev->primary->master) |
128 | return; | |
129 | ||
130 | master_priv = dev->primary->master->driver_priv; | |
131 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
132 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
133 | } |
134 | ||
84b1fd10 | 135 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 136 | { |
ba8bbcf6 | 137 | drm_i915_private_t *dev_priv = dev->dev_private; |
1ec14ad3 CW |
138 | int i; |
139 | ||
1da177e4 LT |
140 | /* Make sure interrupts are disabled here because the uninstall ioctl |
141 | * may not have been called from userspace and after dev_private | |
142 | * is freed, it's too late. | |
143 | */ | |
ed4cb414 | 144 | if (dev->irq_enabled) |
b5e89ed5 | 145 | drm_irq_uninstall(dev); |
1da177e4 | 146 | |
ee0c6bfb | 147 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 CW |
148 | for (i = 0; i < I915_NUM_RINGS; i++) |
149 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
ee0c6bfb | 150 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 151 | |
398c9cb2 KP |
152 | /* Clear the HWS virtual address at teardown */ |
153 | if (I915_NEED_GFX_HWS(dev)) | |
154 | i915_free_hws(dev); | |
1da177e4 LT |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
ba8bbcf6 | 159 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 160 | { |
ba8bbcf6 | 161 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 162 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
e8616b6c | 163 | int ret; |
1da177e4 | 164 | |
3a03ac1a DA |
165 | master_priv->sarea = drm_getsarea(dev); |
166 | if (master_priv->sarea) { | |
167 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
168 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
169 | } else { | |
8a4c47f3 | 170 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
171 | } |
172 | ||
673a394b | 173 | if (init->ring_size != 0) { |
e8616b6c | 174 | if (LP_RING(dev_priv)->obj != NULL) { |
673a394b EA |
175 | i915_dma_cleanup(dev); |
176 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
177 | "GEM mode\n"); | |
178 | return -EINVAL; | |
179 | } | |
1da177e4 | 180 | |
e8616b6c CW |
181 | ret = intel_render_ring_init_dri(dev, |
182 | init->ring_start, | |
183 | init->ring_size); | |
184 | if (ret) { | |
673a394b | 185 | i915_dma_cleanup(dev); |
e8616b6c | 186 | return ret; |
673a394b | 187 | } |
1da177e4 LT |
188 | } |
189 | ||
a6b54f3f | 190 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
191 | dev_priv->back_offset = init->back_offset; |
192 | dev_priv->front_offset = init->front_offset; | |
193 | dev_priv->current_page = 0; | |
7c1c2871 DA |
194 | if (master_priv->sarea_priv) |
195 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 196 | |
1da177e4 LT |
197 | /* Allow hardware batchbuffers unless told otherwise. |
198 | */ | |
199 | dev_priv->allow_batchbuffer = 1; | |
200 | ||
1da177e4 LT |
201 | return 0; |
202 | } | |
203 | ||
84b1fd10 | 204 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
205 | { |
206 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1ec14ad3 | 207 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 208 | |
8a4c47f3 | 209 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 210 | |
8187a2b7 | 211 | if (ring->map.handle == NULL) { |
1da177e4 LT |
212 | DRM_ERROR("can not ioremap virtual address for" |
213 | " ring buffer\n"); | |
20caafa6 | 214 | return -ENOMEM; |
1da177e4 LT |
215 | } |
216 | ||
217 | /* Program Hardware Status Page */ | |
8187a2b7 | 218 | if (!ring->status_page.page_addr) { |
1da177e4 | 219 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 220 | return -EINVAL; |
1da177e4 | 221 | } |
8a4c47f3 | 222 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
223 | ring->status_page.page_addr); |
224 | if (ring->status_page.gfx_addr != 0) | |
78501eac | 225 | intel_ring_setup_status_page(ring); |
dc7a9319 | 226 | else |
4cbf74cc | 227 | i915_write_hws_pga(dev); |
8187a2b7 | 228 | |
8a4c47f3 | 229 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
230 | |
231 | return 0; | |
232 | } | |
233 | ||
c153f45f EA |
234 | static int i915_dma_init(struct drm_device *dev, void *data, |
235 | struct drm_file *file_priv) | |
1da177e4 | 236 | { |
c153f45f | 237 | drm_i915_init_t *init = data; |
1da177e4 LT |
238 | int retcode = 0; |
239 | ||
c153f45f | 240 | switch (init->func) { |
1da177e4 | 241 | case I915_INIT_DMA: |
ba8bbcf6 | 242 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
243 | break; |
244 | case I915_CLEANUP_DMA: | |
245 | retcode = i915_dma_cleanup(dev); | |
246 | break; | |
247 | case I915_RESUME_DMA: | |
0d6aa60b | 248 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
249 | break; |
250 | default: | |
20caafa6 | 251 | retcode = -EINVAL; |
1da177e4 LT |
252 | break; |
253 | } | |
254 | ||
255 | return retcode; | |
256 | } | |
257 | ||
258 | /* Implement basically the same security restrictions as hardware does | |
259 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
260 | * | |
261 | * Most of the calculations below involve calculating the size of a | |
262 | * particular instruction. It's important to get the size right as | |
263 | * that tells us where the next instruction to check is. Any illegal | |
264 | * instruction detected will be given a size of zero, which is a | |
265 | * signal to abort the rest of the buffer. | |
266 | */ | |
e1f99ce6 | 267 | static int validate_cmd(int cmd) |
1da177e4 LT |
268 | { |
269 | switch (((cmd >> 29) & 0x7)) { | |
270 | case 0x0: | |
271 | switch ((cmd >> 23) & 0x3f) { | |
272 | case 0x0: | |
273 | return 1; /* MI_NOOP */ | |
274 | case 0x4: | |
275 | return 1; /* MI_FLUSH */ | |
276 | default: | |
277 | return 0; /* disallow everything else */ | |
278 | } | |
279 | break; | |
280 | case 0x1: | |
281 | return 0; /* reserved */ | |
282 | case 0x2: | |
283 | return (cmd & 0xff) + 2; /* 2d commands */ | |
284 | case 0x3: | |
285 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
286 | return 1; | |
287 | ||
288 | switch ((cmd >> 24) & 0x1f) { | |
289 | case 0x1c: | |
290 | return 1; | |
291 | case 0x1d: | |
b5e89ed5 | 292 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
293 | case 0x3: |
294 | return (cmd & 0x1f) + 2; | |
295 | case 0x4: | |
296 | return (cmd & 0xf) + 2; | |
297 | default: | |
298 | return (cmd & 0xffff) + 2; | |
299 | } | |
300 | case 0x1e: | |
301 | if (cmd & (1 << 23)) | |
302 | return (cmd & 0xffff) + 1; | |
303 | else | |
304 | return 1; | |
305 | case 0x1f: | |
306 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
307 | return (cmd & 0x1ffff) + 2; | |
308 | else if (cmd & (1 << 17)) /* indirect random */ | |
309 | if ((cmd & 0xffff) == 0) | |
310 | return 0; /* unknown length, too hard */ | |
311 | else | |
312 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
313 | else | |
314 | return 2; /* indirect sequential */ | |
315 | default: | |
316 | return 0; | |
317 | } | |
318 | default: | |
319 | return 0; | |
320 | } | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
201361a5 | 325 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 LT |
326 | { |
327 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e1f99ce6 | 328 | int i, ret; |
1da177e4 | 329 | |
1ec14ad3 | 330 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) |
20caafa6 | 331 | return -EINVAL; |
de227f5f | 332 | |
1da177e4 | 333 | for (i = 0; i < dwords;) { |
e1f99ce6 CW |
334 | int sz = validate_cmd(buffer[i]); |
335 | if (sz == 0 || i + sz > dwords) | |
20caafa6 | 336 | return -EINVAL; |
e1f99ce6 | 337 | i += sz; |
1da177e4 LT |
338 | } |
339 | ||
e1f99ce6 CW |
340 | ret = BEGIN_LP_RING((dwords+1)&~1); |
341 | if (ret) | |
342 | return ret; | |
343 | ||
344 | for (i = 0; i < dwords; i++) | |
345 | OUT_RING(buffer[i]); | |
de227f5f DA |
346 | if (dwords & 1) |
347 | OUT_RING(0); | |
348 | ||
349 | ADVANCE_LP_RING(); | |
350 | ||
1da177e4 LT |
351 | return 0; |
352 | } | |
353 | ||
673a394b EA |
354 | int |
355 | i915_emit_box(struct drm_device *dev, | |
c4e7a414 CW |
356 | struct drm_clip_rect *box, |
357 | int DR1, int DR4) | |
1da177e4 | 358 | { |
e1f99ce6 | 359 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 360 | int ret; |
1da177e4 | 361 | |
c4e7a414 CW |
362 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
363 | box->y2 <= 0 || box->x2 <= 0) { | |
1da177e4 | 364 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
c4e7a414 | 365 | box->x1, box->y1, box->x2, box->y2); |
20caafa6 | 366 | return -EINVAL; |
1da177e4 LT |
367 | } |
368 | ||
a6c45cf0 | 369 | if (INTEL_INFO(dev)->gen >= 4) { |
e1f99ce6 CW |
370 | ret = BEGIN_LP_RING(4); |
371 | if (ret) | |
372 | return ret; | |
373 | ||
c29b669c | 374 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
c4e7a414 CW |
375 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
376 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c | 377 | OUT_RING(DR4); |
c29b669c | 378 | } else { |
e1f99ce6 CW |
379 | ret = BEGIN_LP_RING(6); |
380 | if (ret) | |
381 | return ret; | |
382 | ||
c29b669c AH |
383 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
384 | OUT_RING(DR1); | |
c4e7a414 CW |
385 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
386 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c AH |
387 | OUT_RING(DR4); |
388 | OUT_RING(0); | |
c29b669c | 389 | } |
e1f99ce6 | 390 | ADVANCE_LP_RING(); |
1da177e4 LT |
391 | |
392 | return 0; | |
393 | } | |
394 | ||
c29b669c AH |
395 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
396 | * emit. For now, do it in both places: | |
397 | */ | |
398 | ||
84b1fd10 | 399 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
400 | { |
401 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 402 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 403 | |
c99b058f | 404 | dev_priv->counter++; |
af6061af | 405 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 406 | dev_priv->counter = 0; |
7c1c2871 DA |
407 | if (master_priv->sarea_priv) |
408 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f | 409 | |
e1f99ce6 CW |
410 | if (BEGIN_LP_RING(4) == 0) { |
411 | OUT_RING(MI_STORE_DWORD_INDEX); | |
412 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
413 | OUT_RING(dev_priv->counter); | |
414 | OUT_RING(0); | |
415 | ADVANCE_LP_RING(); | |
416 | } | |
de227f5f DA |
417 | } |
418 | ||
84b1fd10 | 419 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
420 | drm_i915_cmdbuffer_t *cmd, |
421 | struct drm_clip_rect *cliprects, | |
422 | void *cmdbuf) | |
1da177e4 LT |
423 | { |
424 | int nbox = cmd->num_cliprects; | |
425 | int i = 0, count, ret; | |
426 | ||
427 | if (cmd->sz & 0x3) { | |
428 | DRM_ERROR("alignment"); | |
20caafa6 | 429 | return -EINVAL; |
1da177e4 LT |
430 | } |
431 | ||
432 | i915_kernel_lost_context(dev); | |
433 | ||
434 | count = nbox ? nbox : 1; | |
435 | ||
436 | for (i = 0; i < count; i++) { | |
437 | if (i < nbox) { | |
c4e7a414 | 438 | ret = i915_emit_box(dev, &cliprects[i], |
1da177e4 LT |
439 | cmd->DR1, cmd->DR4); |
440 | if (ret) | |
441 | return ret; | |
442 | } | |
443 | ||
201361a5 | 444 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
445 | if (ret) |
446 | return ret; | |
447 | } | |
448 | ||
de227f5f | 449 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
450 | return 0; |
451 | } | |
452 | ||
84b1fd10 | 453 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
454 | drm_i915_batchbuffer_t * batch, |
455 | struct drm_clip_rect *cliprects) | |
1da177e4 | 456 | { |
e1f99ce6 | 457 | struct drm_i915_private *dev_priv = dev->dev_private; |
1da177e4 | 458 | int nbox = batch->num_cliprects; |
e1f99ce6 | 459 | int i, count, ret; |
1da177e4 LT |
460 | |
461 | if ((batch->start | batch->used) & 0x7) { | |
462 | DRM_ERROR("alignment"); | |
20caafa6 | 463 | return -EINVAL; |
1da177e4 LT |
464 | } |
465 | ||
466 | i915_kernel_lost_context(dev); | |
467 | ||
468 | count = nbox ? nbox : 1; | |
1da177e4 LT |
469 | for (i = 0; i < count; i++) { |
470 | if (i < nbox) { | |
c4e7a414 | 471 | ret = i915_emit_box(dev, &cliprects[i], |
e1f99ce6 | 472 | batch->DR1, batch->DR4); |
1da177e4 LT |
473 | if (ret) |
474 | return ret; | |
475 | } | |
476 | ||
0790d5e1 | 477 | if (!IS_I830(dev) && !IS_845G(dev)) { |
e1f99ce6 CW |
478 | ret = BEGIN_LP_RING(2); |
479 | if (ret) | |
480 | return ret; | |
481 | ||
a6c45cf0 | 482 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
483 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
484 | OUT_RING(batch->start); | |
485 | } else { | |
486 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
487 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
488 | } | |
1da177e4 | 489 | } else { |
e1f99ce6 CW |
490 | ret = BEGIN_LP_RING(4); |
491 | if (ret) | |
492 | return ret; | |
493 | ||
1da177e4 LT |
494 | OUT_RING(MI_BATCH_BUFFER); |
495 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
496 | OUT_RING(batch->start + batch->used - 4); | |
497 | OUT_RING(0); | |
1da177e4 | 498 | } |
e1f99ce6 | 499 | ADVANCE_LP_RING(); |
1da177e4 LT |
500 | } |
501 | ||
1cafd347 | 502 | |
f00a3ddf | 503 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
504 | if (BEGIN_LP_RING(2) == 0) { |
505 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
506 | OUT_RING(MI_NOOP); | |
507 | ADVANCE_LP_RING(); | |
508 | } | |
1cafd347 | 509 | } |
1da177e4 | 510 | |
e1f99ce6 | 511 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
512 | return 0; |
513 | } | |
514 | ||
af6061af | 515 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
516 | { |
517 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
518 | struct drm_i915_master_private *master_priv = |
519 | dev->primary->master->driver_priv; | |
e1f99ce6 | 520 | int ret; |
1da177e4 | 521 | |
7c1c2871 | 522 | if (!master_priv->sarea_priv) |
c99b058f KH |
523 | return -EINVAL; |
524 | ||
8a4c47f3 | 525 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 526 | __func__, |
527 | dev_priv->current_page, | |
528 | master_priv->sarea_priv->pf_current_page); | |
1da177e4 | 529 | |
af6061af DA |
530 | i915_kernel_lost_context(dev); |
531 | ||
e1f99ce6 CW |
532 | ret = BEGIN_LP_RING(10); |
533 | if (ret) | |
534 | return ret; | |
535 | ||
585fb111 | 536 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af | 537 | OUT_RING(0); |
1da177e4 | 538 | |
af6061af DA |
539 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
540 | OUT_RING(0); | |
541 | if (dev_priv->current_page == 0) { | |
542 | OUT_RING(dev_priv->back_offset); | |
543 | dev_priv->current_page = 1; | |
1da177e4 | 544 | } else { |
af6061af DA |
545 | OUT_RING(dev_priv->front_offset); |
546 | dev_priv->current_page = 0; | |
1da177e4 | 547 | } |
af6061af | 548 | OUT_RING(0); |
1da177e4 | 549 | |
af6061af DA |
550 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
551 | OUT_RING(0); | |
e1f99ce6 | 552 | |
af6061af | 553 | ADVANCE_LP_RING(); |
1da177e4 | 554 | |
7c1c2871 | 555 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 | 556 | |
e1f99ce6 CW |
557 | if (BEGIN_LP_RING(4) == 0) { |
558 | OUT_RING(MI_STORE_DWORD_INDEX); | |
559 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
560 | OUT_RING(dev_priv->counter); | |
561 | OUT_RING(0); | |
562 | ADVANCE_LP_RING(); | |
563 | } | |
1da177e4 | 564 | |
7c1c2871 | 565 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
af6061af | 566 | return 0; |
1da177e4 LT |
567 | } |
568 | ||
1ec14ad3 | 569 | static int i915_quiescent(struct drm_device *dev) |
1da177e4 | 570 | { |
1ec14ad3 | 571 | struct intel_ring_buffer *ring = LP_RING(dev->dev_private); |
1da177e4 LT |
572 | |
573 | i915_kernel_lost_context(dev); | |
96f298aa | 574 | return intel_wait_ring_idle(ring); |
1da177e4 LT |
575 | } |
576 | ||
c153f45f EA |
577 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
578 | struct drm_file *file_priv) | |
1da177e4 | 579 | { |
546b0974 EA |
580 | int ret; |
581 | ||
582 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1da177e4 | 583 | |
546b0974 EA |
584 | mutex_lock(&dev->struct_mutex); |
585 | ret = i915_quiescent(dev); | |
586 | mutex_unlock(&dev->struct_mutex); | |
587 | ||
588 | return ret; | |
1da177e4 LT |
589 | } |
590 | ||
c153f45f EA |
591 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
592 | struct drm_file *file_priv) | |
1da177e4 | 593 | { |
1da177e4 | 594 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 595 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 596 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 597 | master_priv->sarea_priv; |
c153f45f | 598 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 599 | int ret; |
201361a5 | 600 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 LT |
601 | |
602 | if (!dev_priv->allow_batchbuffer) { | |
603 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 604 | return -EINVAL; |
1da177e4 LT |
605 | } |
606 | ||
8a4c47f3 | 607 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 608 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 609 | |
546b0974 | 610 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 611 | |
201361a5 EA |
612 | if (batch->num_cliprects < 0) |
613 | return -EINVAL; | |
614 | ||
615 | if (batch->num_cliprects) { | |
9a298b2a EA |
616 | cliprects = kcalloc(batch->num_cliprects, |
617 | sizeof(struct drm_clip_rect), | |
618 | GFP_KERNEL); | |
201361a5 EA |
619 | if (cliprects == NULL) |
620 | return -ENOMEM; | |
621 | ||
622 | ret = copy_from_user(cliprects, batch->cliprects, | |
623 | batch->num_cliprects * | |
624 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
625 | if (ret != 0) { |
626 | ret = -EFAULT; | |
201361a5 | 627 | goto fail_free; |
9927a403 | 628 | } |
201361a5 | 629 | } |
1da177e4 | 630 | |
546b0974 | 631 | mutex_lock(&dev->struct_mutex); |
201361a5 | 632 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 633 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 634 | |
c99b058f | 635 | if (sarea_priv) |
0baf823a | 636 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
637 | |
638 | fail_free: | |
9a298b2a | 639 | kfree(cliprects); |
201361a5 | 640 | |
1da177e4 LT |
641 | return ret; |
642 | } | |
643 | ||
c153f45f EA |
644 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
645 | struct drm_file *file_priv) | |
1da177e4 | 646 | { |
1da177e4 | 647 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 648 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 649 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 650 | master_priv->sarea_priv; |
c153f45f | 651 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
652 | struct drm_clip_rect *cliprects = NULL; |
653 | void *batch_data; | |
1da177e4 LT |
654 | int ret; |
655 | ||
8a4c47f3 | 656 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 657 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 658 | |
546b0974 | 659 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 660 | |
201361a5 EA |
661 | if (cmdbuf->num_cliprects < 0) |
662 | return -EINVAL; | |
663 | ||
9a298b2a | 664 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
665 | if (batch_data == NULL) |
666 | return -ENOMEM; | |
667 | ||
668 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
669 | if (ret != 0) { |
670 | ret = -EFAULT; | |
201361a5 | 671 | goto fail_batch_free; |
9927a403 | 672 | } |
201361a5 EA |
673 | |
674 | if (cmdbuf->num_cliprects) { | |
9a298b2a EA |
675 | cliprects = kcalloc(cmdbuf->num_cliprects, |
676 | sizeof(struct drm_clip_rect), GFP_KERNEL); | |
a40e8d31 OA |
677 | if (cliprects == NULL) { |
678 | ret = -ENOMEM; | |
201361a5 | 679 | goto fail_batch_free; |
a40e8d31 | 680 | } |
201361a5 EA |
681 | |
682 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
683 | cmdbuf->num_cliprects * | |
684 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
685 | if (ret != 0) { |
686 | ret = -EFAULT; | |
201361a5 | 687 | goto fail_clip_free; |
9927a403 | 688 | } |
1da177e4 LT |
689 | } |
690 | ||
546b0974 | 691 | mutex_lock(&dev->struct_mutex); |
201361a5 | 692 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 693 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
694 | if (ret) { |
695 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 696 | goto fail_clip_free; |
1da177e4 LT |
697 | } |
698 | ||
c99b058f | 699 | if (sarea_priv) |
0baf823a | 700 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 701 | |
201361a5 | 702 | fail_clip_free: |
9a298b2a | 703 | kfree(cliprects); |
355d7f37 | 704 | fail_batch_free: |
9a298b2a | 705 | kfree(batch_data); |
201361a5 EA |
706 | |
707 | return ret; | |
1da177e4 LT |
708 | } |
709 | ||
c153f45f EA |
710 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
711 | struct drm_file *file_priv) | |
1da177e4 | 712 | { |
546b0974 EA |
713 | int ret; |
714 | ||
8a4c47f3 | 715 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 716 | |
546b0974 | 717 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 718 | |
546b0974 EA |
719 | mutex_lock(&dev->struct_mutex); |
720 | ret = i915_dispatch_flip(dev); | |
721 | mutex_unlock(&dev->struct_mutex); | |
722 | ||
723 | return ret; | |
1da177e4 LT |
724 | } |
725 | ||
c153f45f EA |
726 | static int i915_getparam(struct drm_device *dev, void *data, |
727 | struct drm_file *file_priv) | |
1da177e4 | 728 | { |
1da177e4 | 729 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 730 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
731 | int value; |
732 | ||
733 | if (!dev_priv) { | |
3e684eae | 734 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 735 | return -EINVAL; |
1da177e4 LT |
736 | } |
737 | ||
c153f45f | 738 | switch (param->param) { |
1da177e4 | 739 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 740 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
741 | break; |
742 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
743 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
744 | break; | |
0d6aa60b DA |
745 | case I915_PARAM_LAST_DISPATCH: |
746 | value = READ_BREADCRUMB(dev_priv); | |
747 | break; | |
ed4c9c4a KH |
748 | case I915_PARAM_CHIPSET_ID: |
749 | value = dev->pci_device; | |
750 | break; | |
673a394b | 751 | case I915_PARAM_HAS_GEM: |
ac5c4e76 | 752 | value = dev_priv->has_gem; |
673a394b | 753 | break; |
0f973f27 JB |
754 | case I915_PARAM_NUM_FENCES_AVAIL: |
755 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
756 | break; | |
02e792fb DV |
757 | case I915_PARAM_HAS_OVERLAY: |
758 | value = dev_priv->overlay ? 1 : 0; | |
759 | break; | |
e9560f7c JB |
760 | case I915_PARAM_HAS_PAGEFLIPPING: |
761 | value = 1; | |
762 | break; | |
76446cac JB |
763 | case I915_PARAM_HAS_EXECBUF2: |
764 | /* depends on GEM */ | |
765 | value = dev_priv->has_gem; | |
766 | break; | |
e3a815fc ZN |
767 | case I915_PARAM_HAS_BSD: |
768 | value = HAS_BSD(dev); | |
769 | break; | |
549f7365 CW |
770 | case I915_PARAM_HAS_BLT: |
771 | value = HAS_BLT(dev); | |
772 | break; | |
a00b10c3 CW |
773 | case I915_PARAM_HAS_RELAXED_FENCING: |
774 | value = 1; | |
775 | break; | |
bbf0c6b3 DV |
776 | case I915_PARAM_HAS_COHERENT_RINGS: |
777 | value = 1; | |
778 | break; | |
72bfa19c CW |
779 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
780 | value = INTEL_INFO(dev)->gen >= 4; | |
781 | break; | |
271d81b8 CW |
782 | case I915_PARAM_HAS_RELAXED_DELTA: |
783 | value = 1; | |
784 | break; | |
ae662d31 EA |
785 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
786 | value = 1; | |
787 | break; | |
3d29b842 ED |
788 | case I915_PARAM_HAS_LLC: |
789 | value = HAS_LLC(dev); | |
790 | break; | |
1da177e4 | 791 | default: |
8a4c47f3 | 792 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
76446cac | 793 | param->param); |
20caafa6 | 794 | return -EINVAL; |
1da177e4 LT |
795 | } |
796 | ||
c153f45f | 797 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 798 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 799 | return -EFAULT; |
1da177e4 LT |
800 | } |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
c153f45f EA |
805 | static int i915_setparam(struct drm_device *dev, void *data, |
806 | struct drm_file *file_priv) | |
1da177e4 | 807 | { |
1da177e4 | 808 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 809 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
810 | |
811 | if (!dev_priv) { | |
3e684eae | 812 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 813 | return -EINVAL; |
1da177e4 LT |
814 | } |
815 | ||
c153f45f | 816 | switch (param->param) { |
1da177e4 | 817 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
818 | break; |
819 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 820 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
821 | break; |
822 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 823 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 | 824 | break; |
0f973f27 JB |
825 | case I915_SETPARAM_NUM_USED_FENCES: |
826 | if (param->value > dev_priv->num_fence_regs || | |
827 | param->value < 0) | |
828 | return -EINVAL; | |
829 | /* Userspace can use first N regs */ | |
830 | dev_priv->fence_reg_start = param->value; | |
831 | break; | |
1da177e4 | 832 | default: |
8a4c47f3 | 833 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 834 | param->param); |
20caafa6 | 835 | return -EINVAL; |
1da177e4 LT |
836 | } |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
c153f45f EA |
841 | static int i915_set_status_page(struct drm_device *dev, void *data, |
842 | struct drm_file *file_priv) | |
dc7a9319 | 843 | { |
dc7a9319 | 844 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 845 | drm_i915_hws_addr_t *hws = data; |
1ec14ad3 | 846 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
b39d50e5 ZW |
847 | |
848 | if (!I915_NEED_GFX_HWS(dev)) | |
849 | return -EINVAL; | |
dc7a9319 WZ |
850 | |
851 | if (!dev_priv) { | |
3e684eae | 852 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 853 | return -EINVAL; |
dc7a9319 | 854 | } |
dc7a9319 | 855 | |
79e53945 JB |
856 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
857 | WARN(1, "tried to set status page when mode setting active\n"); | |
858 | return 0; | |
859 | } | |
860 | ||
8a4c47f3 | 861 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 862 | |
8187a2b7 | 863 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 864 | |
8b409580 | 865 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
866 | dev_priv->hws_map.size = 4*1024; |
867 | dev_priv->hws_map.type = 0; | |
868 | dev_priv->hws_map.flags = 0; | |
869 | dev_priv->hws_map.mtrr = 0; | |
870 | ||
dd0910b3 | 871 | drm_core_ioremap_wc(&dev_priv->hws_map, dev); |
dc7a9319 | 872 | if (dev_priv->hws_map.handle == NULL) { |
dc7a9319 | 873 | i915_dma_cleanup(dev); |
e20f9c64 | 874 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
875 | DRM_ERROR("can not ioremap virtual address for" |
876 | " G33 hw status page\n"); | |
20caafa6 | 877 | return -ENOMEM; |
dc7a9319 | 878 | } |
311bd68e CW |
879 | ring->status_page.page_addr = |
880 | (void __force __iomem *)dev_priv->hws_map.handle; | |
881 | memset_io(ring->status_page.page_addr, 0, PAGE_SIZE); | |
8187a2b7 | 882 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
dc7a9319 | 883 | |
8a4c47f3 | 884 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 885 | ring->status_page.gfx_addr); |
8a4c47f3 | 886 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 887 | ring->status_page.page_addr); |
dc7a9319 WZ |
888 | return 0; |
889 | } | |
890 | ||
ec2a4c3f DA |
891 | static int i915_get_bridge_dev(struct drm_device *dev) |
892 | { | |
893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
894 | ||
0206e353 | 895 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
896 | if (!dev_priv->bridge_dev) { |
897 | DRM_ERROR("bridge device not found\n"); | |
898 | return -1; | |
899 | } | |
900 | return 0; | |
901 | } | |
902 | ||
c4804411 ZW |
903 | #define MCHBAR_I915 0x44 |
904 | #define MCHBAR_I965 0x48 | |
905 | #define MCHBAR_SIZE (4*4096) | |
906 | ||
907 | #define DEVEN_REG 0x54 | |
908 | #define DEVEN_MCHBAR_EN (1 << 28) | |
909 | ||
910 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
911 | static int | |
912 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
913 | { | |
914 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 915 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
916 | u32 temp_lo, temp_hi = 0; |
917 | u64 mchbar_addr; | |
a25c25c2 | 918 | int ret; |
c4804411 | 919 | |
a6c45cf0 | 920 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
921 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
922 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
923 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
924 | ||
925 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
926 | #ifdef CONFIG_PNP | |
927 | if (mchbar_addr && | |
a25c25c2 CW |
928 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
929 | return 0; | |
c4804411 ZW |
930 | #endif |
931 | ||
932 | /* Get some space for it */ | |
a25c25c2 CW |
933 | dev_priv->mch_res.name = "i915 MCHBAR"; |
934 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
935 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
936 | &dev_priv->mch_res, | |
c4804411 ZW |
937 | MCHBAR_SIZE, MCHBAR_SIZE, |
938 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 939 | 0, pcibios_align_resource, |
c4804411 ZW |
940 | dev_priv->bridge_dev); |
941 | if (ret) { | |
942 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
943 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 944 | return ret; |
c4804411 ZW |
945 | } |
946 | ||
a6c45cf0 | 947 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
948 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
949 | upper_32_bits(dev_priv->mch_res.start)); | |
950 | ||
951 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
952 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 953 | return 0; |
c4804411 ZW |
954 | } |
955 | ||
956 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
957 | static void | |
958 | intel_setup_mchbar(struct drm_device *dev) | |
959 | { | |
960 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 961 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
962 | u32 temp; |
963 | bool enabled; | |
964 | ||
965 | dev_priv->mchbar_need_disable = false; | |
966 | ||
967 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
968 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
969 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
970 | } else { | |
971 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
972 | enabled = temp & 1; | |
973 | } | |
974 | ||
975 | /* If it's already enabled, don't have to do anything */ | |
976 | if (enabled) | |
977 | return; | |
978 | ||
979 | if (intel_alloc_mchbar_resource(dev)) | |
980 | return; | |
981 | ||
982 | dev_priv->mchbar_need_disable = true; | |
983 | ||
984 | /* Space is allocated or reserved, so enable it. */ | |
985 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
986 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
987 | temp | DEVEN_MCHBAR_EN); | |
988 | } else { | |
989 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
990 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
991 | } | |
992 | } | |
993 | ||
994 | static void | |
995 | intel_teardown_mchbar(struct drm_device *dev) | |
996 | { | |
997 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 998 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
999 | u32 temp; |
1000 | ||
1001 | if (dev_priv->mchbar_need_disable) { | |
1002 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1003 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1004 | temp &= ~DEVEN_MCHBAR_EN; | |
1005 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1006 | } else { | |
1007 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1008 | temp &= ~1; | |
1009 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1010 | } | |
1011 | } | |
1012 | ||
1013 | if (dev_priv->mch_res.start) | |
1014 | release_resource(&dev_priv->mch_res); | |
1015 | } | |
1016 | ||
80824003 JB |
1017 | #define PTE_ADDRESS_MASK 0xfffff000 |
1018 | #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ | |
1019 | #define PTE_MAPPING_TYPE_UNCACHED (0 << 1) | |
1020 | #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ | |
1021 | #define PTE_MAPPING_TYPE_CACHED (3 << 1) | |
1022 | #define PTE_MAPPING_TYPE_MASK (3 << 1) | |
1023 | #define PTE_VALID (1 << 0) | |
1024 | ||
1025 | /** | |
fe669bf8 CW |
1026 | * i915_stolen_to_phys - take an offset into stolen memory and turn it into |
1027 | * a physical one | |
80824003 | 1028 | * @dev: drm device |
fe669bf8 | 1029 | * @offset: address to translate |
80824003 | 1030 | * |
fe669bf8 CW |
1031 | * Some chip functions require allocations from stolen space and need the |
1032 | * physical address of the memory in question. | |
80824003 | 1033 | */ |
fe669bf8 | 1034 | static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset) |
80824003 | 1035 | { |
fe669bf8 CW |
1036 | struct drm_i915_private *dev_priv = dev->dev_private; |
1037 | struct pci_dev *pdev = dev_priv->bridge_dev; | |
1038 | u32 base; | |
1039 | ||
1040 | #if 0 | |
1041 | /* On the machines I have tested the Graphics Base of Stolen Memory | |
1042 | * is unreliable, so compute the base by subtracting the stolen memory | |
1043 | * from the Top of Low Usable DRAM which is where the BIOS places | |
1044 | * the graphics stolen memory. | |
1045 | */ | |
1046 | if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) { | |
1047 | /* top 32bits are reserved = 0 */ | |
1048 | pci_read_config_dword(pdev, 0xA4, &base); | |
80824003 | 1049 | } else { |
fe669bf8 CW |
1050 | /* XXX presume 8xx is the same as i915 */ |
1051 | pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base); | |
1052 | } | |
1053 | #else | |
1054 | if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) { | |
1055 | u16 val; | |
1056 | pci_read_config_word(pdev, 0xb0, &val); | |
1057 | base = val >> 4 << 20; | |
1058 | } else { | |
1059 | u8 val; | |
1060 | pci_read_config_byte(pdev, 0x9c, &val); | |
1061 | base = val >> 3 << 27; | |
80824003 | 1062 | } |
c64f7ba5 | 1063 | base -= dev_priv->mm.gtt->stolen_size; |
fe669bf8 | 1064 | #endif |
80824003 | 1065 | |
fe669bf8 | 1066 | return base + offset; |
80824003 JB |
1067 | } |
1068 | ||
1069 | static void i915_warn_stolen(struct drm_device *dev) | |
1070 | { | |
1071 | DRM_ERROR("not enough stolen space for compressed buffer, disabling\n"); | |
1072 | DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); | |
1073 | } | |
1074 | ||
1075 | static void i915_setup_compression(struct drm_device *dev, int size) | |
1076 | { | |
1077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
132b6aab | 1078 | struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb); |
29bd0ae2 AM |
1079 | unsigned long cfb_base; |
1080 | unsigned long ll_base = 0; | |
80824003 | 1081 | |
43a9539f CW |
1082 | /* Just in case the BIOS is doing something questionable. */ |
1083 | intel_disable_fbc(dev); | |
1084 | ||
fe669bf8 CW |
1085 | compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0); |
1086 | if (compressed_fb) | |
1087 | compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); | |
1088 | if (!compressed_fb) | |
1089 | goto err; | |
80824003 | 1090 | |
fe669bf8 CW |
1091 | cfb_base = i915_stolen_to_phys(dev, compressed_fb->start); |
1092 | if (!cfb_base) | |
1093 | goto err_fb; | |
80824003 | 1094 | |
9c04f015 | 1095 | if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) { |
fe669bf8 CW |
1096 | compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen, |
1097 | 4096, 4096, 0); | |
1098 | if (compressed_llb) | |
1099 | compressed_llb = drm_mm_get_block(compressed_llb, | |
1100 | 4096, 4096); | |
1101 | if (!compressed_llb) | |
1102 | goto err_fb; | |
74dff282 | 1103 | |
fe669bf8 CW |
1104 | ll_base = i915_stolen_to_phys(dev, compressed_llb->start); |
1105 | if (!ll_base) | |
1106 | goto err_llb; | |
80824003 JB |
1107 | } |
1108 | ||
1109 | dev_priv->cfb_size = size; | |
1110 | ||
20bf377e | 1111 | dev_priv->compressed_fb = compressed_fb; |
9c04f015 | 1112 | if (HAS_PCH_SPLIT(dev)) |
b52eb4dc ZY |
1113 | I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start); |
1114 | else if (IS_GM45(dev)) { | |
74dff282 JB |
1115 | I915_WRITE(DPFC_CB_BASE, compressed_fb->start); |
1116 | } else { | |
74dff282 JB |
1117 | I915_WRITE(FBC_CFB_BASE, cfb_base); |
1118 | I915_WRITE(FBC_LL_BASE, ll_base); | |
20bf377e | 1119 | dev_priv->compressed_llb = compressed_llb; |
80824003 JB |
1120 | } |
1121 | ||
fe669bf8 CW |
1122 | DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", |
1123 | cfb_base, ll_base, size >> 20); | |
1124 | return; | |
1125 | ||
1126 | err_llb: | |
1127 | drm_mm_put_block(compressed_llb); | |
1128 | err_fb: | |
1129 | drm_mm_put_block(compressed_fb); | |
1130 | err: | |
1131 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; | |
1132 | i915_warn_stolen(dev); | |
80824003 JB |
1133 | } |
1134 | ||
20bf377e JB |
1135 | static void i915_cleanup_compression(struct drm_device *dev) |
1136 | { | |
1137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1138 | ||
1139 | drm_mm_put_block(dev_priv->compressed_fb); | |
aebf0daf | 1140 | if (dev_priv->compressed_llb) |
20bf377e JB |
1141 | drm_mm_put_block(dev_priv->compressed_llb); |
1142 | } | |
1143 | ||
28d52043 DA |
1144 | /* true = enable decode, false = disable decoder */ |
1145 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1146 | { | |
1147 | struct drm_device *dev = cookie; | |
1148 | ||
1149 | intel_modeset_vga_set_state(dev, state); | |
1150 | if (state) | |
1151 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1152 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1153 | else | |
1154 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1155 | } | |
1156 | ||
6a9ee8af DA |
1157 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1158 | { | |
1159 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1160 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1161 | if (state == VGA_SWITCHEROO_ON) { | |
fbf81762 | 1162 | printk(KERN_INFO "i915: switched on\n"); |
5bcf719b | 1163 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
1164 | /* i915 resume handler doesn't set to D0 */ |
1165 | pci_set_power_state(dev->pdev, PCI_D0); | |
1166 | i915_resume(dev); | |
5bcf719b | 1167 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af DA |
1168 | } else { |
1169 | printk(KERN_ERR "i915: switched off\n"); | |
5bcf719b | 1170 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 1171 | i915_suspend(dev, pmm); |
5bcf719b | 1172 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1173 | } |
1174 | } | |
1175 | ||
1176 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1177 | { | |
1178 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1179 | bool can_switch; | |
1180 | ||
1181 | spin_lock(&dev->count_lock); | |
1182 | can_switch = (dev->open_count == 0); | |
1183 | spin_unlock(&dev->count_lock); | |
1184 | return can_switch; | |
1185 | } | |
1186 | ||
2c7111db | 1187 | static int i915_load_gem_init(struct drm_device *dev) |
79e53945 JB |
1188 | { |
1189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
53984635 | 1190 | unsigned long prealloc_size, gtt_size, mappable_size; |
2c7111db | 1191 | int ret; |
79e53945 | 1192 | |
c64f7ba5 | 1193 | prealloc_size = dev_priv->mm.gtt->stolen_size; |
53984635 DV |
1194 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; |
1195 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
53984635 | 1196 | |
fe669bf8 CW |
1197 | /* Basic memrange allocator for stolen space */ |
1198 | drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size); | |
79e53945 | 1199 | |
d3ae0810 | 1200 | mutex_lock(&dev->struct_mutex); |
e21af88d | 1201 | if (i915_enable_ppgtt && HAS_ALIASING_PPGTT(dev)) { |
1d2a314c DV |
1202 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the |
1203 | * aperture accordingly when using aliasing ppgtt. */ | |
1204 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
1205 | /* For paranoia keep the guard page in between. */ | |
1206 | gtt_size -= PAGE_SIZE; | |
1207 | ||
1208 | i915_gem_do_init(dev, 0, mappable_size, gtt_size); | |
1209 | ||
1210 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
1211 | if (ret) | |
1212 | return ret; | |
1213 | } else { | |
1214 | /* Let GEM Manage all of the aperture. | |
1215 | * | |
1216 | * However, leave one page at the end still bound to the scratch | |
1217 | * page. There are a number of places where the hardware | |
1218 | * apparently prefetches past the end of the object, and we've | |
1219 | * seen multiple hangs with the GPU head pointer stuck in a | |
1220 | * batchbuffer bound at the last page of the aperture. One page | |
1221 | * should be enough to keep any prefetching inside of the | |
1222 | * aperture. | |
1223 | */ | |
1224 | i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE); | |
1225 | } | |
79e53945 | 1226 | |
f691e2f4 | 1227 | ret = i915_gem_init_hw(dev); |
11ed50ec | 1228 | mutex_unlock(&dev->struct_mutex); |
1d2a314c DV |
1229 | if (ret) { |
1230 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
2c7111db | 1231 | return ret; |
1d2a314c | 1232 | } |
79e53945 | 1233 | |
80824003 | 1234 | /* Try to set up FBC with a reasonable compressed buffer size */ |
9216d44d | 1235 | if (I915_HAS_FBC(dev) && i915_powersave) { |
80824003 JB |
1236 | int cfb_size; |
1237 | ||
fe669bf8 CW |
1238 | /* Leave 1M for line length buffer & misc. */ |
1239 | ||
1240 | /* Try to get a 32M buffer... */ | |
1241 | if (prealloc_size > (36*1024*1024)) | |
1242 | cfb_size = 32*1024*1024; | |
80824003 JB |
1243 | else /* fall back to 7/8 of the stolen space */ |
1244 | cfb_size = prealloc_size * 7 / 8; | |
1245 | i915_setup_compression(dev, cfb_size); | |
1246 | } | |
1247 | ||
fe669bf8 | 1248 | /* Allow hardware batchbuffers unless told otherwise. */ |
79e53945 | 1249 | dev_priv->allow_batchbuffer = 1; |
2c7111db CW |
1250 | return 0; |
1251 | } | |
1252 | ||
1253 | static int i915_load_modeset_init(struct drm_device *dev) | |
1254 | { | |
1255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1256 | int ret; | |
79e53945 | 1257 | |
6d139a87 | 1258 | ret = intel_parse_bios(dev); |
79e53945 JB |
1259 | if (ret) |
1260 | DRM_INFO("failed to find VBIOS tables\n"); | |
1261 | ||
934f992c CW |
1262 | /* If we have > 1 VGA cards, then we need to arbitrate access |
1263 | * to the common VGA resources. | |
1264 | * | |
1265 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
1266 | * then we do not take part in VGA arbitration and the | |
1267 | * vga_client_register() fails with -ENODEV. | |
1268 | */ | |
28d52043 | 1269 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
934f992c | 1270 | if (ret && ret != -ENODEV) |
2c7111db | 1271 | goto out; |
28d52043 | 1272 | |
723bfd70 JB |
1273 | intel_register_dsm_handler(); |
1274 | ||
6a9ee8af DA |
1275 | ret = vga_switcheroo_register_client(dev->pdev, |
1276 | i915_switcheroo_set_state, | |
8d608aa6 | 1277 | NULL, |
6a9ee8af DA |
1278 | i915_switcheroo_can_switch); |
1279 | if (ret) | |
5a79395b | 1280 | goto cleanup_vga_client; |
6a9ee8af | 1281 | |
1afe3e9d JB |
1282 | /* IIR "flip pending" bit means done if this bit is set */ |
1283 | if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE)) | |
1284 | dev_priv->flip_pending_is_done = true; | |
1285 | ||
b01f2c3a JB |
1286 | intel_modeset_init(dev); |
1287 | ||
2c7111db | 1288 | ret = i915_load_gem_init(dev); |
79e53945 | 1289 | if (ret) |
5a79395b | 1290 | goto cleanup_vga_switcheroo; |
79e53945 | 1291 | |
2c7111db CW |
1292 | intel_modeset_gem_init(dev); |
1293 | ||
1294 | ret = drm_irq_install(dev); | |
1295 | if (ret) | |
1296 | goto cleanup_gem; | |
1297 | ||
79e53945 JB |
1298 | /* Always safe in the mode setting case. */ |
1299 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
1300 | dev->vblank_disable_allowed = 1; | |
1301 | ||
5a79395b CW |
1302 | ret = intel_fbdev_init(dev); |
1303 | if (ret) | |
1304 | goto cleanup_irq; | |
1305 | ||
eb1f8e4f | 1306 | drm_kms_helper_poll_init(dev); |
87acb0a5 CW |
1307 | |
1308 | /* We're off and running w/KMS */ | |
1309 | dev_priv->mm.suspended = 0; | |
1310 | ||
79e53945 JB |
1311 | return 0; |
1312 | ||
5a79395b CW |
1313 | cleanup_irq: |
1314 | drm_irq_uninstall(dev); | |
2c7111db CW |
1315 | cleanup_gem: |
1316 | mutex_lock(&dev->struct_mutex); | |
1317 | i915_gem_cleanup_ringbuffer(dev); | |
1318 | mutex_unlock(&dev->struct_mutex); | |
1d2a314c | 1319 | i915_gem_cleanup_aliasing_ppgtt(dev); |
5a79395b CW |
1320 | cleanup_vga_switcheroo: |
1321 | vga_switcheroo_unregister_client(dev->pdev); | |
1322 | cleanup_vga_client: | |
1323 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
1324 | out: |
1325 | return ret; | |
1326 | } | |
1327 | ||
7c1c2871 DA |
1328 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1329 | { | |
1330 | struct drm_i915_master_private *master_priv; | |
1331 | ||
9a298b2a | 1332 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1333 | if (!master_priv) |
1334 | return -ENOMEM; | |
1335 | ||
1336 | master->driver_priv = master_priv; | |
1337 | return 0; | |
1338 | } | |
1339 | ||
1340 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1341 | { | |
1342 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1343 | ||
1344 | if (!master_priv) | |
1345 | return; | |
1346 | ||
9a298b2a | 1347 | kfree(master_priv); |
7c1c2871 DA |
1348 | |
1349 | master->driver_priv = NULL; | |
1350 | } | |
1351 | ||
7648fa99 | 1352 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
7662c8bd SL |
1353 | { |
1354 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1355 | u32 tmp; | |
1356 | ||
7662c8bd SL |
1357 | tmp = I915_READ(CLKCFG); |
1358 | ||
1359 | switch (tmp & CLKCFG_FSB_MASK) { | |
1360 | case CLKCFG_FSB_533: | |
1361 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
1362 | break; | |
1363 | case CLKCFG_FSB_800: | |
1364 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
1365 | break; | |
1366 | case CLKCFG_FSB_667: | |
1367 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
1368 | break; | |
1369 | case CLKCFG_FSB_400: | |
1370 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
1371 | break; | |
1372 | } | |
1373 | ||
1374 | switch (tmp & CLKCFG_MEM_MASK) { | |
1375 | case CLKCFG_MEM_533: | |
1376 | dev_priv->mem_freq = 533; | |
1377 | break; | |
1378 | case CLKCFG_MEM_667: | |
1379 | dev_priv->mem_freq = 667; | |
1380 | break; | |
1381 | case CLKCFG_MEM_800: | |
1382 | dev_priv->mem_freq = 800; | |
1383 | break; | |
1384 | } | |
95534263 LP |
1385 | |
1386 | /* detect pineview DDR3 setting */ | |
1387 | tmp = I915_READ(CSHRDDR3CTL); | |
1388 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
7662c8bd SL |
1389 | } |
1390 | ||
7648fa99 JB |
1391 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
1392 | { | |
1393 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1394 | u16 ddrpll, csipll; | |
1395 | ||
1396 | ddrpll = I915_READ16(DDRMPLL1); | |
1397 | csipll = I915_READ16(CSIPLL0); | |
1398 | ||
1399 | switch (ddrpll & 0xff) { | |
1400 | case 0xc: | |
1401 | dev_priv->mem_freq = 800; | |
1402 | break; | |
1403 | case 0x10: | |
1404 | dev_priv->mem_freq = 1066; | |
1405 | break; | |
1406 | case 0x14: | |
1407 | dev_priv->mem_freq = 1333; | |
1408 | break; | |
1409 | case 0x18: | |
1410 | dev_priv->mem_freq = 1600; | |
1411 | break; | |
1412 | default: | |
1413 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
1414 | ddrpll & 0xff); | |
1415 | dev_priv->mem_freq = 0; | |
1416 | break; | |
1417 | } | |
1418 | ||
1419 | dev_priv->r_t = dev_priv->mem_freq; | |
1420 | ||
1421 | switch (csipll & 0x3ff) { | |
1422 | case 0x00c: | |
1423 | dev_priv->fsb_freq = 3200; | |
1424 | break; | |
1425 | case 0x00e: | |
1426 | dev_priv->fsb_freq = 3733; | |
1427 | break; | |
1428 | case 0x010: | |
1429 | dev_priv->fsb_freq = 4266; | |
1430 | break; | |
1431 | case 0x012: | |
1432 | dev_priv->fsb_freq = 4800; | |
1433 | break; | |
1434 | case 0x014: | |
1435 | dev_priv->fsb_freq = 5333; | |
1436 | break; | |
1437 | case 0x016: | |
1438 | dev_priv->fsb_freq = 5866; | |
1439 | break; | |
1440 | case 0x018: | |
1441 | dev_priv->fsb_freq = 6400; | |
1442 | break; | |
1443 | default: | |
1444 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
1445 | csipll & 0x3ff); | |
1446 | dev_priv->fsb_freq = 0; | |
1447 | break; | |
1448 | } | |
1449 | ||
1450 | if (dev_priv->fsb_freq == 3200) { | |
1451 | dev_priv->c_m = 0; | |
1452 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { | |
1453 | dev_priv->c_m = 1; | |
1454 | } else { | |
1455 | dev_priv->c_m = 2; | |
1456 | } | |
1457 | } | |
1458 | ||
faa60c41 CW |
1459 | static const struct cparams { |
1460 | u16 i; | |
1461 | u16 t; | |
1462 | u16 m; | |
1463 | u16 c; | |
1464 | } cparams[] = { | |
7648fa99 JB |
1465 | { 1, 1333, 301, 28664 }, |
1466 | { 1, 1066, 294, 24460 }, | |
1467 | { 1, 800, 294, 25192 }, | |
1468 | { 0, 1333, 276, 27605 }, | |
1469 | { 0, 1066, 276, 27605 }, | |
1470 | { 0, 800, 231, 23784 }, | |
1471 | }; | |
1472 | ||
1473 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) | |
1474 | { | |
1475 | u64 total_count, diff, ret; | |
1476 | u32 count1, count2, count3, m = 0, c = 0; | |
1477 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
1478 | int i; | |
1479 | ||
1480 | diff1 = now - dev_priv->last_time1; | |
1481 | ||
4ed0b577 ED |
1482 | /* Prevent division-by-zero if we are asking too fast. |
1483 | * Also, we don't get interesting results if we are polling | |
1484 | * faster than once in 10ms, so just return the saved value | |
1485 | * in such cases. | |
1486 | */ | |
1487 | if (diff1 <= 10) | |
1488 | return dev_priv->chipset_power; | |
1489 | ||
7648fa99 JB |
1490 | count1 = I915_READ(DMIEC); |
1491 | count2 = I915_READ(DDREC); | |
1492 | count3 = I915_READ(CSIEC); | |
1493 | ||
1494 | total_count = count1 + count2 + count3; | |
1495 | ||
1496 | /* FIXME: handle per-counter overflow */ | |
1497 | if (total_count < dev_priv->last_count1) { | |
1498 | diff = ~0UL - dev_priv->last_count1; | |
1499 | diff += total_count; | |
1500 | } else { | |
1501 | diff = total_count - dev_priv->last_count1; | |
1502 | } | |
1503 | ||
1504 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
1505 | if (cparams[i].i == dev_priv->c_m && | |
1506 | cparams[i].t == dev_priv->r_t) { | |
1507 | m = cparams[i].m; | |
1508 | c = cparams[i].c; | |
1509 | break; | |
1510 | } | |
1511 | } | |
1512 | ||
d270ae34 | 1513 | diff = div_u64(diff, diff1); |
7648fa99 | 1514 | ret = ((m * diff) + c); |
d270ae34 | 1515 | ret = div_u64(ret, 10); |
7648fa99 JB |
1516 | |
1517 | dev_priv->last_count1 = total_count; | |
1518 | dev_priv->last_time1 = now; | |
1519 | ||
4ed0b577 ED |
1520 | dev_priv->chipset_power = ret; |
1521 | ||
7648fa99 JB |
1522 | return ret; |
1523 | } | |
1524 | ||
1525 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) | |
1526 | { | |
1527 | unsigned long m, x, b; | |
1528 | u32 tsfs; | |
1529 | ||
1530 | tsfs = I915_READ(TSFS); | |
1531 | ||
1532 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
1533 | x = I915_READ8(TR1); | |
1534 | ||
1535 | b = tsfs & TSFS_INTR_MASK; | |
1536 | ||
1537 | return ((m * x) / 127) - b; | |
1538 | } | |
1539 | ||
faa60c41 | 1540 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
7648fa99 | 1541 | { |
faa60c41 CW |
1542 | static const struct v_table { |
1543 | u16 vd; /* in .1 mil */ | |
1544 | u16 vm; /* in .1 mil */ | |
1545 | } v_table[] = { | |
1546 | { 0, 0, }, | |
1547 | { 375, 0, }, | |
1548 | { 500, 0, }, | |
1549 | { 625, 0, }, | |
1550 | { 750, 0, }, | |
1551 | { 875, 0, }, | |
1552 | { 1000, 0, }, | |
1553 | { 1125, 0, }, | |
1554 | { 4125, 3000, }, | |
1555 | { 4125, 3000, }, | |
1556 | { 4125, 3000, }, | |
1557 | { 4125, 3000, }, | |
1558 | { 4125, 3000, }, | |
1559 | { 4125, 3000, }, | |
1560 | { 4125, 3000, }, | |
1561 | { 4125, 3000, }, | |
1562 | { 4125, 3000, }, | |
1563 | { 4125, 3000, }, | |
1564 | { 4125, 3000, }, | |
1565 | { 4125, 3000, }, | |
1566 | { 4125, 3000, }, | |
1567 | { 4125, 3000, }, | |
1568 | { 4125, 3000, }, | |
1569 | { 4125, 3000, }, | |
1570 | { 4125, 3000, }, | |
1571 | { 4125, 3000, }, | |
1572 | { 4125, 3000, }, | |
1573 | { 4125, 3000, }, | |
1574 | { 4125, 3000, }, | |
1575 | { 4125, 3000, }, | |
1576 | { 4125, 3000, }, | |
1577 | { 4125, 3000, }, | |
1578 | { 4250, 3125, }, | |
1579 | { 4375, 3250, }, | |
1580 | { 4500, 3375, }, | |
1581 | { 4625, 3500, }, | |
1582 | { 4750, 3625, }, | |
1583 | { 4875, 3750, }, | |
1584 | { 5000, 3875, }, | |
1585 | { 5125, 4000, }, | |
1586 | { 5250, 4125, }, | |
1587 | { 5375, 4250, }, | |
1588 | { 5500, 4375, }, | |
1589 | { 5625, 4500, }, | |
1590 | { 5750, 4625, }, | |
1591 | { 5875, 4750, }, | |
1592 | { 6000, 4875, }, | |
1593 | { 6125, 5000, }, | |
1594 | { 6250, 5125, }, | |
1595 | { 6375, 5250, }, | |
1596 | { 6500, 5375, }, | |
1597 | { 6625, 5500, }, | |
1598 | { 6750, 5625, }, | |
1599 | { 6875, 5750, }, | |
1600 | { 7000, 5875, }, | |
1601 | { 7125, 6000, }, | |
1602 | { 7250, 6125, }, | |
1603 | { 7375, 6250, }, | |
1604 | { 7500, 6375, }, | |
1605 | { 7625, 6500, }, | |
1606 | { 7750, 6625, }, | |
1607 | { 7875, 6750, }, | |
1608 | { 8000, 6875, }, | |
1609 | { 8125, 7000, }, | |
1610 | { 8250, 7125, }, | |
1611 | { 8375, 7250, }, | |
1612 | { 8500, 7375, }, | |
1613 | { 8625, 7500, }, | |
1614 | { 8750, 7625, }, | |
1615 | { 8875, 7750, }, | |
1616 | { 9000, 7875, }, | |
1617 | { 9125, 8000, }, | |
1618 | { 9250, 8125, }, | |
1619 | { 9375, 8250, }, | |
1620 | { 9500, 8375, }, | |
1621 | { 9625, 8500, }, | |
1622 | { 9750, 8625, }, | |
1623 | { 9875, 8750, }, | |
1624 | { 10000, 8875, }, | |
1625 | { 10125, 9000, }, | |
1626 | { 10250, 9125, }, | |
1627 | { 10375, 9250, }, | |
1628 | { 10500, 9375, }, | |
1629 | { 10625, 9500, }, | |
1630 | { 10750, 9625, }, | |
1631 | { 10875, 9750, }, | |
1632 | { 11000, 9875, }, | |
1633 | { 11125, 10000, }, | |
1634 | { 11250, 10125, }, | |
1635 | { 11375, 10250, }, | |
1636 | { 11500, 10375, }, | |
1637 | { 11625, 10500, }, | |
1638 | { 11750, 10625, }, | |
1639 | { 11875, 10750, }, | |
1640 | { 12000, 10875, }, | |
1641 | { 12125, 11000, }, | |
1642 | { 12250, 11125, }, | |
1643 | { 12375, 11250, }, | |
1644 | { 12500, 11375, }, | |
1645 | { 12625, 11500, }, | |
1646 | { 12750, 11625, }, | |
1647 | { 12875, 11750, }, | |
1648 | { 13000, 11875, }, | |
1649 | { 13125, 12000, }, | |
1650 | { 13250, 12125, }, | |
1651 | { 13375, 12250, }, | |
1652 | { 13500, 12375, }, | |
1653 | { 13625, 12500, }, | |
1654 | { 13750, 12625, }, | |
1655 | { 13875, 12750, }, | |
1656 | { 14000, 12875, }, | |
1657 | { 14125, 13000, }, | |
1658 | { 14250, 13125, }, | |
1659 | { 14375, 13250, }, | |
1660 | { 14500, 13375, }, | |
1661 | { 14625, 13500, }, | |
1662 | { 14750, 13625, }, | |
1663 | { 14875, 13750, }, | |
1664 | { 15000, 13875, }, | |
1665 | { 15125, 14000, }, | |
1666 | { 15250, 14125, }, | |
1667 | { 15375, 14250, }, | |
1668 | { 15500, 14375, }, | |
1669 | { 15625, 14500, }, | |
1670 | { 15750, 14625, }, | |
1671 | { 15875, 14750, }, | |
1672 | { 16000, 14875, }, | |
1673 | { 16125, 15000, }, | |
1674 | }; | |
1675 | if (dev_priv->info->is_mobile) | |
1676 | return v_table[pxvid].vm; | |
1677 | else | |
1678 | return v_table[pxvid].vd; | |
7648fa99 JB |
1679 | } |
1680 | ||
1681 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) | |
1682 | { | |
1683 | struct timespec now, diff1; | |
1684 | u64 diff; | |
1685 | unsigned long diffms; | |
1686 | u32 count; | |
1687 | ||
1688 | getrawmonotonic(&now); | |
1689 | diff1 = timespec_sub(now, dev_priv->last_time2); | |
1690 | ||
1691 | /* Don't divide by 0 */ | |
1692 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; | |
1693 | if (!diffms) | |
1694 | return; | |
1695 | ||
1696 | count = I915_READ(GFXEC); | |
1697 | ||
1698 | if (count < dev_priv->last_count2) { | |
1699 | diff = ~0UL - dev_priv->last_count2; | |
1700 | diff += count; | |
1701 | } else { | |
1702 | diff = count - dev_priv->last_count2; | |
1703 | } | |
1704 | ||
1705 | dev_priv->last_count2 = count; | |
1706 | dev_priv->last_time2 = now; | |
1707 | ||
1708 | /* More magic constants... */ | |
1709 | diff = diff * 1181; | |
d270ae34 | 1710 | diff = div_u64(diff, diffms * 10); |
7648fa99 JB |
1711 | dev_priv->gfx_power = diff; |
1712 | } | |
1713 | ||
1714 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) | |
1715 | { | |
1716 | unsigned long t, corr, state1, corr2, state2; | |
1717 | u32 pxvid, ext_v; | |
1718 | ||
1719 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4)); | |
1720 | pxvid = (pxvid >> 24) & 0x7f; | |
1721 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
1722 | ||
1723 | state1 = ext_v; | |
1724 | ||
1725 | t = i915_mch_val(dev_priv); | |
1726 | ||
1727 | /* Revel in the empirically derived constants */ | |
1728 | ||
1729 | /* Correction factor in 1/100000 units */ | |
1730 | if (t > 80) | |
1731 | corr = ((t * 2349) + 135940); | |
1732 | else if (t >= 50) | |
1733 | corr = ((t * 964) + 29317); | |
1734 | else /* < 50 */ | |
1735 | corr = ((t * 301) + 1004); | |
1736 | ||
1737 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
1738 | corr /= 100000; | |
1739 | corr2 = (corr * dev_priv->corr); | |
1740 | ||
1741 | state2 = (corr2 * state1) / 10000; | |
1742 | state2 /= 100; /* convert to mW */ | |
1743 | ||
1744 | i915_update_gfx_val(dev_priv); | |
1745 | ||
1746 | return dev_priv->gfx_power + state2; | |
1747 | } | |
1748 | ||
1749 | /* Global for IPS driver to get at the current i915 device */ | |
1750 | static struct drm_i915_private *i915_mch_dev; | |
1751 | /* | |
1752 | * Lock protecting IPS related data structures | |
1753 | * - i915_mch_dev | |
1754 | * - dev_priv->max_delay | |
1755 | * - dev_priv->min_delay | |
1756 | * - dev_priv->fmax | |
1757 | * - dev_priv->gpu_busy | |
1758 | */ | |
995b6762 | 1759 | static DEFINE_SPINLOCK(mchdev_lock); |
7648fa99 JB |
1760 | |
1761 | /** | |
1762 | * i915_read_mch_val - return value for IPS use | |
1763 | * | |
1764 | * Calculate and return a value for the IPS driver to use when deciding whether | |
1765 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
1766 | */ | |
1767 | unsigned long i915_read_mch_val(void) | |
1768 | { | |
0206e353 | 1769 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1770 | unsigned long chipset_val, graphics_val, ret = 0; |
1771 | ||
0206e353 | 1772 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1773 | if (!i915_mch_dev) |
1774 | goto out_unlock; | |
1775 | dev_priv = i915_mch_dev; | |
1776 | ||
1777 | chipset_val = i915_chipset_val(dev_priv); | |
1778 | graphics_val = i915_gfx_val(dev_priv); | |
1779 | ||
1780 | ret = chipset_val + graphics_val; | |
1781 | ||
1782 | out_unlock: | |
0206e353 | 1783 | spin_unlock(&mchdev_lock); |
7648fa99 | 1784 | |
0206e353 | 1785 | return ret; |
7648fa99 JB |
1786 | } |
1787 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
1788 | ||
1789 | /** | |
1790 | * i915_gpu_raise - raise GPU frequency limit | |
1791 | * | |
1792 | * Raise the limit; IPS indicates we have thermal headroom. | |
1793 | */ | |
1794 | bool i915_gpu_raise(void) | |
1795 | { | |
0206e353 | 1796 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1797 | bool ret = true; |
1798 | ||
0206e353 | 1799 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1800 | if (!i915_mch_dev) { |
1801 | ret = false; | |
1802 | goto out_unlock; | |
1803 | } | |
1804 | dev_priv = i915_mch_dev; | |
1805 | ||
1806 | if (dev_priv->max_delay > dev_priv->fmax) | |
1807 | dev_priv->max_delay--; | |
1808 | ||
1809 | out_unlock: | |
0206e353 | 1810 | spin_unlock(&mchdev_lock); |
7648fa99 | 1811 | |
0206e353 | 1812 | return ret; |
7648fa99 JB |
1813 | } |
1814 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
1815 | ||
1816 | /** | |
1817 | * i915_gpu_lower - lower GPU frequency limit | |
1818 | * | |
1819 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
1820 | * frequency maximum. | |
1821 | */ | |
1822 | bool i915_gpu_lower(void) | |
1823 | { | |
0206e353 | 1824 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1825 | bool ret = true; |
1826 | ||
0206e353 | 1827 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1828 | if (!i915_mch_dev) { |
1829 | ret = false; | |
1830 | goto out_unlock; | |
1831 | } | |
1832 | dev_priv = i915_mch_dev; | |
1833 | ||
1834 | if (dev_priv->max_delay < dev_priv->min_delay) | |
1835 | dev_priv->max_delay++; | |
1836 | ||
1837 | out_unlock: | |
0206e353 | 1838 | spin_unlock(&mchdev_lock); |
7648fa99 | 1839 | |
0206e353 | 1840 | return ret; |
7648fa99 JB |
1841 | } |
1842 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
1843 | ||
1844 | /** | |
1845 | * i915_gpu_busy - indicate GPU business to IPS | |
1846 | * | |
1847 | * Tell the IPS driver whether or not the GPU is busy. | |
1848 | */ | |
1849 | bool i915_gpu_busy(void) | |
1850 | { | |
0206e353 | 1851 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1852 | bool ret = false; |
1853 | ||
0206e353 | 1854 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1855 | if (!i915_mch_dev) |
1856 | goto out_unlock; | |
1857 | dev_priv = i915_mch_dev; | |
1858 | ||
1859 | ret = dev_priv->busy; | |
1860 | ||
1861 | out_unlock: | |
0206e353 | 1862 | spin_unlock(&mchdev_lock); |
7648fa99 | 1863 | |
0206e353 | 1864 | return ret; |
7648fa99 JB |
1865 | } |
1866 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
1867 | ||
1868 | /** | |
1869 | * i915_gpu_turbo_disable - disable graphics turbo | |
1870 | * | |
1871 | * Disable graphics turbo by resetting the max frequency and setting the | |
1872 | * current frequency to the default. | |
1873 | */ | |
1874 | bool i915_gpu_turbo_disable(void) | |
1875 | { | |
0206e353 | 1876 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1877 | bool ret = true; |
1878 | ||
0206e353 | 1879 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1880 | if (!i915_mch_dev) { |
1881 | ret = false; | |
1882 | goto out_unlock; | |
1883 | } | |
1884 | dev_priv = i915_mch_dev; | |
1885 | ||
1886 | dev_priv->max_delay = dev_priv->fstart; | |
1887 | ||
1888 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart)) | |
1889 | ret = false; | |
1890 | ||
1891 | out_unlock: | |
0206e353 | 1892 | spin_unlock(&mchdev_lock); |
7648fa99 | 1893 | |
0206e353 | 1894 | return ret; |
7648fa99 JB |
1895 | } |
1896 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
1897 | ||
63ee41d7 EA |
1898 | /** |
1899 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
1900 | * IPS got loaded first. | |
1901 | * | |
1902 | * This awkward dance is so that neither module has to depend on the | |
1903 | * other in order for IPS to do the appropriate communication of | |
1904 | * GPU turbo limits to i915. | |
1905 | */ | |
1906 | static void | |
1907 | ips_ping_for_i915_load(void) | |
1908 | { | |
1909 | void (*link)(void); | |
1910 | ||
1911 | link = symbol_get(ips_link_to_i915_driver); | |
1912 | if (link) { | |
1913 | link(); | |
1914 | symbol_put(ips_link_to_i915_driver); | |
1915 | } | |
1916 | } | |
1917 | ||
e2b665c4 AJ |
1918 | static void |
1919 | i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, | |
1920 | unsigned long size) | |
1921 | { | |
9e984bc1 AJ |
1922 | #if defined(CONFIG_X86_PAT) |
1923 | if (cpu_has_pat) | |
1924 | return; | |
1925 | #endif | |
1926 | ||
e2b665c4 AJ |
1927 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
1928 | * one would think, because the kernel disables PAT on first | |
1929 | * generation Core chips because WC PAT gets overridden by a UC | |
1930 | * MTRR if present. Even if a UC MTRR isn't present. | |
1931 | */ | |
1932 | dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1); | |
1933 | if (dev_priv->mm.gtt_mtrr < 0) { | |
1934 | DRM_INFO("MTRR allocation failed. Graphics " | |
1935 | "performance may suffer.\n"); | |
1936 | } | |
1937 | } | |
1938 | ||
79e53945 JB |
1939 | /** |
1940 | * i915_driver_load - setup chip and create an initial config | |
1941 | * @dev: DRM device | |
1942 | * @flags: startup flags | |
1943 | * | |
1944 | * The driver load routine has to do several things: | |
1945 | * - drive output discovery via intel_modeset_init() | |
1946 | * - initialize the memory manager | |
1947 | * - allocate initial config memory | |
1948 | * - setup the DRM framebuffer with the allocated memory | |
1949 | */ | |
84b1fd10 | 1950 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1951 | { |
ea059a1e | 1952 | struct drm_i915_private *dev_priv; |
cfdf1fa2 | 1953 | int ret = 0, mmio_bar; |
fe669bf8 CW |
1954 | uint32_t agp_size; |
1955 | ||
22eae947 DA |
1956 | /* i915 has 4 more counters */ |
1957 | dev->counters += 4; | |
1958 | dev->types[6] = _DRM_STAT_IRQ; | |
1959 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1960 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1961 | dev->types[9] = _DRM_STAT_DMA; | |
1962 | ||
9a298b2a | 1963 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
ba8bbcf6 JB |
1964 | if (dev_priv == NULL) |
1965 | return -ENOMEM; | |
1966 | ||
ba8bbcf6 | 1967 | dev->dev_private = (void *)dev_priv; |
673a394b | 1968 | dev_priv->dev = dev; |
cfdf1fa2 | 1969 | dev_priv->info = (struct intel_device_info *) flags; |
ba8bbcf6 | 1970 | |
ec2a4c3f DA |
1971 | if (i915_get_bridge_dev(dev)) { |
1972 | ret = -EIO; | |
1973 | goto free_priv; | |
1974 | } | |
1975 | ||
466e69b8 DA |
1976 | pci_set_master(dev->pdev); |
1977 | ||
9f82d238 DV |
1978 | /* overlay on gen2 is broken and can't address above 1G */ |
1979 | if (IS_GEN2(dev)) | |
1980 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1981 | ||
6927faf3 JN |
1982 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1983 | * using 32bit addressing, overwriting memory if HWS is located | |
1984 | * above 4GB. | |
1985 | * | |
1986 | * The documentation also mentions an issue with undefined | |
1987 | * behaviour if any general state is accessed within a page above 4GB, | |
1988 | * which also needs to be handled carefully. | |
1989 | */ | |
1990 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1991 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1992 | ||
b4ce0f85 CW |
1993 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
1994 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0); | |
1995 | if (!dev_priv->regs) { | |
1996 | DRM_ERROR("failed to map registers\n"); | |
1997 | ret = -EIO; | |
1998 | goto put_bridge; | |
1999 | } | |
2000 | ||
71e9339c CW |
2001 | dev_priv->mm.gtt = intel_gtt_get(); |
2002 | if (!dev_priv->mm.gtt) { | |
2003 | DRM_ERROR("Failed to initialize GTT\n"); | |
2004 | ret = -ENODEV; | |
a7b85d2a | 2005 | goto out_rmmap; |
71e9339c CW |
2006 | } |
2007 | ||
71e9339c CW |
2008 | agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
2009 | ||
0206e353 | 2010 | dev_priv->mm.gtt_mapping = |
71e9339c | 2011 | io_mapping_create_wc(dev->agp->base, agp_size); |
6644107d VP |
2012 | if (dev_priv->mm.gtt_mapping == NULL) { |
2013 | ret = -EIO; | |
2014 | goto out_rmmap; | |
2015 | } | |
2016 | ||
e2b665c4 | 2017 | i915_mtrr_setup(dev_priv, dev->agp->base, agp_size); |
19966754 | 2018 | |
e642abbf CW |
2019 | /* The i915 workqueue is primarily used for batched retirement of |
2020 | * requests (and thus managing bo) once the task has been completed | |
2021 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
2022 | * need high-priority retirement, such as waiting for an explicit | |
2023 | * bo. | |
2024 | * | |
2025 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 2026 | * idle-timers and recording error state. |
e642abbf CW |
2027 | * |
2028 | * All tasks on the workqueue are expected to acquire the dev mutex | |
2029 | * so there is no point in running more than one instance of the | |
2030 | * workqueue at any time: max_active = 1 and NON_REENTRANT. | |
2031 | */ | |
2032 | dev_priv->wq = alloc_workqueue("i915", | |
2033 | WQ_UNBOUND | WQ_NON_REENTRANT, | |
2034 | 1); | |
9c9fe1f8 EA |
2035 | if (dev_priv->wq == NULL) { |
2036 | DRM_ERROR("Failed to create our workqueue.\n"); | |
2037 | ret = -ENOMEM; | |
a7b85d2a | 2038 | goto out_mtrrfree; |
9c9fe1f8 EA |
2039 | } |
2040 | ||
ac5c4e76 DA |
2041 | /* enable GEM by default */ |
2042 | dev_priv->has_gem = 1; | |
ac5c4e76 | 2043 | |
f71d4af4 | 2044 | intel_irq_init(dev); |
9880b7a5 | 2045 | |
c4804411 ZW |
2046 | /* Try to make sure MCHBAR is enabled before poking at it */ |
2047 | intel_setup_mchbar(dev); | |
f899fc64 | 2048 | intel_setup_gmbus(dev); |
44834a67 | 2049 | intel_opregion_setup(dev); |
c4804411 | 2050 | |
6d139a87 BF |
2051 | /* Make sure the bios did its job and set up vital registers */ |
2052 | intel_setup_bios(dev); | |
2053 | ||
673a394b EA |
2054 | i915_gem_load(dev); |
2055 | ||
398c9cb2 KP |
2056 | /* Init HWS */ |
2057 | if (!I915_NEED_GFX_HWS(dev)) { | |
2058 | ret = i915_init_phys_hws(dev); | |
56e2ea34 CW |
2059 | if (ret) |
2060 | goto out_gem_unload; | |
398c9cb2 | 2061 | } |
ed4cb414 | 2062 | |
7648fa99 JB |
2063 | if (IS_PINEVIEW(dev)) |
2064 | i915_pineview_get_mem_freq(dev); | |
f00a3ddf | 2065 | else if (IS_GEN5(dev)) |
7648fa99 | 2066 | i915_ironlake_get_mem_freq(dev); |
7662c8bd | 2067 | |
ed4cb414 EA |
2068 | /* On the 945G/GM, the chipset reports the MSI capability on the |
2069 | * integrated graphics even though the support isn't actually there | |
2070 | * according to the published specs. It doesn't appear to function | |
2071 | * correctly in testing on 945G. | |
2072 | * This may be a side effect of MSI having been made available for PEG | |
2073 | * and the registers being closely associated. | |
d1ed629f KP |
2074 | * |
2075 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
2076 | * be lost or delayed, but we use them anyways to avoid |
2077 | * stuck interrupts on some machines. | |
ed4cb414 | 2078 | */ |
b60678a7 | 2079 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 2080 | pci_enable_msi(dev->pdev); |
ed4cb414 | 2081 | |
9f1f46a4 | 2082 | spin_lock_init(&dev_priv->gt_lock); |
1ec14ad3 | 2083 | spin_lock_init(&dev_priv->irq_lock); |
63eeaf38 | 2084 | spin_lock_init(&dev_priv->error_lock); |
4912d041 | 2085 | spin_lock_init(&dev_priv->rps_lock); |
ed4cb414 | 2086 | |
27f8227b JB |
2087 | if (IS_IVYBRIDGE(dev)) |
2088 | dev_priv->num_pipe = 3; | |
2089 | else if (IS_MOBILE(dev) || !IS_GEN2(dev)) | |
9db4a9c7 JB |
2090 | dev_priv->num_pipe = 2; |
2091 | else | |
2092 | dev_priv->num_pipe = 1; | |
2093 | ||
2094 | ret = drm_vblank_init(dev, dev_priv->num_pipe); | |
56e2ea34 CW |
2095 | if (ret) |
2096 | goto out_gem_unload; | |
52440211 | 2097 | |
11ed50ec BG |
2098 | /* Start out suspended */ |
2099 | dev_priv->mm.suspended = 1; | |
2100 | ||
3bad0781 ZW |
2101 | intel_detect_pch(dev); |
2102 | ||
79e53945 | 2103 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 2104 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
2105 | if (ret < 0) { |
2106 | DRM_ERROR("failed to init modeset\n"); | |
56e2ea34 | 2107 | goto out_gem_unload; |
79e53945 JB |
2108 | } |
2109 | } | |
2110 | ||
74a365b3 | 2111 | /* Must be done after probing outputs */ |
44834a67 CW |
2112 | intel_opregion_init(dev); |
2113 | acpi_video_register(); | |
74a365b3 | 2114 | |
f65d9421 BG |
2115 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
2116 | (unsigned long) dev); | |
7648fa99 JB |
2117 | |
2118 | spin_lock(&mchdev_lock); | |
2119 | i915_mch_dev = dev_priv; | |
2120 | dev_priv->mchdev_lock = &mchdev_lock; | |
2121 | spin_unlock(&mchdev_lock); | |
2122 | ||
63ee41d7 EA |
2123 | ips_ping_for_i915_load(); |
2124 | ||
79e53945 JB |
2125 | return 0; |
2126 | ||
56e2ea34 | 2127 | out_gem_unload: |
a7b85d2a KP |
2128 | if (dev_priv->mm.inactive_shrinker.shrink) |
2129 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
2130 | ||
56e2ea34 CW |
2131 | if (dev->pdev->msi_enabled) |
2132 | pci_disable_msi(dev->pdev); | |
2133 | ||
2134 | intel_teardown_gmbus(dev); | |
2135 | intel_teardown_mchbar(dev); | |
9c9fe1f8 | 2136 | destroy_workqueue(dev_priv->wq); |
a7b85d2a KP |
2137 | out_mtrrfree: |
2138 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
2139 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
2140 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
2141 | dev_priv->mm.gtt_mtrr = -1; | |
2142 | } | |
6644107d | 2143 | io_mapping_free(dev_priv->mm.gtt_mapping); |
79e53945 | 2144 | out_rmmap: |
6dda569f | 2145 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
2146 | put_bridge: |
2147 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 2148 | free_priv: |
9a298b2a | 2149 | kfree(dev_priv); |
ba8bbcf6 JB |
2150 | return ret; |
2151 | } | |
2152 | ||
2153 | int i915_driver_unload(struct drm_device *dev) | |
2154 | { | |
2155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 2156 | int ret; |
ba8bbcf6 | 2157 | |
7648fa99 JB |
2158 | spin_lock(&mchdev_lock); |
2159 | i915_mch_dev = NULL; | |
2160 | spin_unlock(&mchdev_lock); | |
2161 | ||
17250b71 CW |
2162 | if (dev_priv->mm.inactive_shrinker.shrink) |
2163 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
2164 | ||
c911fc1c | 2165 | mutex_lock(&dev->struct_mutex); |
b93f9cf1 | 2166 | ret = i915_gpu_idle(dev, true); |
c911fc1c DV |
2167 | if (ret) |
2168 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
2169 | mutex_unlock(&dev->struct_mutex); | |
2170 | ||
75ef9da2 DV |
2171 | /* Cancel the retire work handler, which should be idle now. */ |
2172 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
2173 | ||
ab657db1 EA |
2174 | io_mapping_free(dev_priv->mm.gtt_mapping); |
2175 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
2176 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
2177 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
2178 | dev_priv->mm.gtt_mtrr = -1; | |
2179 | } | |
2180 | ||
44834a67 CW |
2181 | acpi_video_unregister(); |
2182 | ||
79e53945 | 2183 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
7b4f3990 | 2184 | intel_fbdev_fini(dev); |
3d8620cc JB |
2185 | intel_modeset_cleanup(dev); |
2186 | ||
6363ee6f ZY |
2187 | /* |
2188 | * free the memory space allocated for the child device | |
2189 | * config parsed from VBT | |
2190 | */ | |
2191 | if (dev_priv->child_dev && dev_priv->child_dev_num) { | |
2192 | kfree(dev_priv->child_dev); | |
2193 | dev_priv->child_dev = NULL; | |
2194 | dev_priv->child_dev_num = 0; | |
2195 | } | |
6c0d9350 | 2196 | |
6a9ee8af | 2197 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 2198 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
2199 | } |
2200 | ||
a8b4899e | 2201 | /* Free error state after interrupts are fully disabled. */ |
bc0c7f14 DV |
2202 | del_timer_sync(&dev_priv->hangcheck_timer); |
2203 | cancel_work_sync(&dev_priv->error_work); | |
a8b4899e | 2204 | i915_destroy_error_state(dev); |
bc0c7f14 | 2205 | |
ed4cb414 EA |
2206 | if (dev->pdev->msi_enabled) |
2207 | pci_disable_msi(dev->pdev); | |
2208 | ||
44834a67 | 2209 | intel_opregion_fini(dev); |
8ee1c3db | 2210 | |
79e53945 | 2211 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
2212 | /* Flush any outstanding unpin_work. */ |
2213 | flush_workqueue(dev_priv->wq); | |
2214 | ||
79e53945 | 2215 | mutex_lock(&dev->struct_mutex); |
ecbec53b | 2216 | i915_gem_free_all_phys_object(dev); |
79e53945 JB |
2217 | i915_gem_cleanup_ringbuffer(dev); |
2218 | mutex_unlock(&dev->struct_mutex); | |
1d2a314c | 2219 | i915_gem_cleanup_aliasing_ppgtt(dev); |
20bf377e JB |
2220 | if (I915_HAS_FBC(dev) && i915_powersave) |
2221 | i915_cleanup_compression(dev); | |
fe669bf8 | 2222 | drm_mm_takedown(&dev_priv->mm.stolen); |
02e792fb DV |
2223 | |
2224 | intel_cleanup_overlay(dev); | |
c2873e96 KP |
2225 | |
2226 | if (!I915_NEED_GFX_HWS(dev)) | |
2227 | i915_free_hws(dev); | |
79e53945 JB |
2228 | } |
2229 | ||
701394cc | 2230 | if (dev_priv->regs != NULL) |
6dda569f | 2231 | pci_iounmap(dev->pdev, dev_priv->regs); |
701394cc | 2232 | |
f899fc64 | 2233 | intel_teardown_gmbus(dev); |
c4804411 ZW |
2234 | intel_teardown_mchbar(dev); |
2235 | ||
bc0c7f14 DV |
2236 | destroy_workqueue(dev_priv->wq); |
2237 | ||
ec2a4c3f | 2238 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 2239 | kfree(dev->dev_private); |
ba8bbcf6 | 2240 | |
22eae947 DA |
2241 | return 0; |
2242 | } | |
2243 | ||
f787a5f5 | 2244 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 2245 | { |
f787a5f5 | 2246 | struct drm_i915_file_private *file_priv; |
673a394b | 2247 | |
8a4c47f3 | 2248 | DRM_DEBUG_DRIVER("\n"); |
f787a5f5 CW |
2249 | file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL); |
2250 | if (!file_priv) | |
673a394b EA |
2251 | return -ENOMEM; |
2252 | ||
f787a5f5 | 2253 | file->driver_priv = file_priv; |
673a394b | 2254 | |
1c25595f | 2255 | spin_lock_init(&file_priv->mm.lock); |
f787a5f5 | 2256 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
673a394b EA |
2257 | |
2258 | return 0; | |
2259 | } | |
2260 | ||
79e53945 JB |
2261 | /** |
2262 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
2263 | * @dev: DRM device | |
2264 | * | |
2265 | * Take care of cleaning up after all DRM clients have exited. In the | |
2266 | * mode setting case, we want to restore the kernel's initial mode (just | |
2267 | * in case the last client left us in a bad state). | |
2268 | * | |
2269 | * Additionally, in the non-mode setting case, we'll tear down the AGP | |
2270 | * and DMA structures, since the kernel won't be using them, and clea | |
2271 | * up any GEM state. | |
2272 | */ | |
84b1fd10 | 2273 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 2274 | { |
ba8bbcf6 JB |
2275 | drm_i915_private_t *dev_priv = dev->dev_private; |
2276 | ||
79e53945 | 2277 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
e8e7a2b8 | 2278 | intel_fb_restore_mode(dev); |
6a9ee8af | 2279 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 2280 | return; |
79e53945 | 2281 | } |
144a75fa | 2282 | |
673a394b EA |
2283 | i915_gem_lastclose(dev); |
2284 | ||
b5e89ed5 | 2285 | i915_dma_cleanup(dev); |
1da177e4 LT |
2286 | } |
2287 | ||
6c340eac | 2288 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 2289 | { |
b962442e | 2290 | i915_gem_release(dev, file_priv); |
1da177e4 LT |
2291 | } |
2292 | ||
f787a5f5 | 2293 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 2294 | { |
f787a5f5 | 2295 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 2296 | |
f787a5f5 | 2297 | kfree(file_priv); |
673a394b EA |
2298 | } |
2299 | ||
c153f45f | 2300 | struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
2301 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2302 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
2303 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
2304 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
2305 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
2306 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
2307 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), | |
2308 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
b2c606fe DV |
2309 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
2310 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
2311 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1b2f1489 | 2312 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
b2c606fe | 2313 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1b2f1489 DA |
2314 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2315 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), | |
2316 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
2317 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2318 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2319 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
2320 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), | |
2321 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2322 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2323 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
2324 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
2325 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2326 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2327 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), | |
2328 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), | |
2329 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), | |
2330 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), | |
2331 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), | |
2332 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), | |
2333 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), | |
2334 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), | |
2335 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), | |
2336 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), | |
2337 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), | |
2338 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), | |
2339 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
2340 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
2341 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
2342 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
c94f7029 DA |
2343 | }; |
2344 | ||
2345 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
2346 | |
2347 | /** | |
2348 | * Determine if the device really is AGP or not. | |
2349 | * | |
2350 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
2351 | * PCI-e. | |
2352 | * | |
2353 | * \param dev The device to be tested. | |
2354 | * | |
2355 | * \returns | |
2356 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
2357 | */ | |
84b1fd10 | 2358 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
2359 | { |
2360 | return 1; | |
2361 | } |