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Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
79e53945 JB |
31 | #include "drm_crtc_helper.h" |
32 | #include "intel_drv.h" | |
1da177e4 LT |
33 | #include "i915_drm.h" |
34 | #include "i915_drv.h" | |
35 | ||
1da177e4 LT |
36 | /* Really want an OS-independent resettable timer. Would like to have |
37 | * this loop run for (eg) 3 sec, but have the timer reset every time | |
38 | * the head pointer changes, so that EBUSY only happens if the ring | |
39 | * actually stalls for (eg) 3 seconds. | |
40 | */ | |
84b1fd10 | 41 | int i915_wait_ring(struct drm_device * dev, int n, const char *caller) |
1da177e4 LT |
42 | { |
43 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 44 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 45 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); |
d3a6d446 KP |
46 | u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; |
47 | u32 last_acthd = I915_READ(acthd_reg); | |
48 | u32 acthd; | |
585fb111 | 49 | u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
1da177e4 LT |
50 | int i; |
51 | ||
d3a6d446 | 52 | for (i = 0; i < 100000; i++) { |
585fb111 | 53 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
d3a6d446 | 54 | acthd = I915_READ(acthd_reg); |
1da177e4 LT |
55 | ring->space = ring->head - (ring->tail + 8); |
56 | if (ring->space < 0) | |
57 | ring->space += ring->Size; | |
58 | if (ring->space >= n) | |
59 | return 0; | |
60 | ||
7c1c2871 DA |
61 | if (master_priv->sarea_priv) |
62 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 LT |
63 | |
64 | if (ring->head != last_head) | |
65 | i = 0; | |
d3a6d446 KP |
66 | if (acthd != last_acthd) |
67 | i = 0; | |
1da177e4 LT |
68 | |
69 | last_head = ring->head; | |
d3a6d446 KP |
70 | last_acthd = acthd; |
71 | msleep_interruptible(10); | |
72 | ||
1da177e4 LT |
73 | } |
74 | ||
20caafa6 | 75 | return -EBUSY; |
1da177e4 LT |
76 | } |
77 | ||
398c9cb2 KP |
78 | /** |
79 | * Sets up the hardware status page for devices that need a physical address | |
80 | * in the register. | |
81 | */ | |
3043c60c | 82 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
83 | { |
84 | drm_i915_private_t *dev_priv = dev->dev_private; | |
85 | /* Program Hardware Status Page */ | |
86 | dev_priv->status_page_dmah = | |
87 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); | |
88 | ||
89 | if (!dev_priv->status_page_dmah) { | |
90 | DRM_ERROR("Can not allocate hardware status page\n"); | |
91 | return -ENOMEM; | |
92 | } | |
93 | dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; | |
94 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | |
95 | ||
96 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
97 | ||
98 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); | |
99 | DRM_DEBUG("Enabled hardware status page\n"); | |
100 | return 0; | |
101 | } | |
102 | ||
103 | /** | |
104 | * Frees the hardware status page, whether it's a physical address or a virtual | |
105 | * address set up by the X Server. | |
106 | */ | |
3043c60c | 107 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
108 | { |
109 | drm_i915_private_t *dev_priv = dev->dev_private; | |
110 | if (dev_priv->status_page_dmah) { | |
111 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
112 | dev_priv->status_page_dmah = NULL; | |
113 | } | |
114 | ||
115 | if (dev_priv->status_gfx_addr) { | |
116 | dev_priv->status_gfx_addr = 0; | |
117 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | |
118 | } | |
119 | ||
120 | /* Need to rewrite hardware status page */ | |
121 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
122 | } | |
123 | ||
84b1fd10 | 124 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
125 | { |
126 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 127 | struct drm_i915_master_private *master_priv; |
1da177e4 LT |
128 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); |
129 | ||
79e53945 JB |
130 | /* |
131 | * We should never lose context on the ring with modesetting | |
132 | * as we don't expose it to userspace | |
133 | */ | |
134 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
135 | return; | |
136 | ||
585fb111 JB |
137 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
138 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
1da177e4 LT |
139 | ring->space = ring->head - (ring->tail + 8); |
140 | if (ring->space < 0) | |
141 | ring->space += ring->Size; | |
142 | ||
7c1c2871 DA |
143 | if (!dev->primary->master) |
144 | return; | |
145 | ||
146 | master_priv = dev->primary->master->driver_priv; | |
147 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
148 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
149 | } |
150 | ||
84b1fd10 | 151 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 152 | { |
ba8bbcf6 | 153 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
154 | /* Make sure interrupts are disabled here because the uninstall ioctl |
155 | * may not have been called from userspace and after dev_private | |
156 | * is freed, it's too late. | |
157 | */ | |
ed4cb414 | 158 | if (dev->irq_enabled) |
b5e89ed5 | 159 | drm_irq_uninstall(dev); |
1da177e4 | 160 | |
ba8bbcf6 JB |
161 | if (dev_priv->ring.virtual_start) { |
162 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
3043c60c EA |
163 | dev_priv->ring.virtual_start = NULL; |
164 | dev_priv->ring.map.handle = NULL; | |
ba8bbcf6 JB |
165 | dev_priv->ring.map.size = 0; |
166 | } | |
dc7a9319 | 167 | |
398c9cb2 KP |
168 | /* Clear the HWS virtual address at teardown */ |
169 | if (I915_NEED_GFX_HWS(dev)) | |
170 | i915_free_hws(dev); | |
1da177e4 LT |
171 | |
172 | return 0; | |
173 | } | |
174 | ||
ba8bbcf6 | 175 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 176 | { |
ba8bbcf6 | 177 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 178 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 179 | |
673a394b EA |
180 | if (init->ring_size != 0) { |
181 | if (dev_priv->ring.ring_obj != NULL) { | |
182 | i915_dma_cleanup(dev); | |
183 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
184 | "GEM mode\n"); | |
185 | return -EINVAL; | |
186 | } | |
1da177e4 | 187 | |
673a394b EA |
188 | dev_priv->ring.Size = init->ring_size; |
189 | dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; | |
1da177e4 | 190 | |
673a394b EA |
191 | dev_priv->ring.map.offset = init->ring_start; |
192 | dev_priv->ring.map.size = init->ring_size; | |
193 | dev_priv->ring.map.type = 0; | |
194 | dev_priv->ring.map.flags = 0; | |
195 | dev_priv->ring.map.mtrr = 0; | |
1da177e4 | 196 | |
673a394b EA |
197 | drm_core_ioremap(&dev_priv->ring.map, dev); |
198 | ||
199 | if (dev_priv->ring.map.handle == NULL) { | |
200 | i915_dma_cleanup(dev); | |
201 | DRM_ERROR("can not ioremap virtual address for" | |
202 | " ring buffer\n"); | |
203 | return -ENOMEM; | |
204 | } | |
1da177e4 LT |
205 | } |
206 | ||
207 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
208 | ||
a6b54f3f | 209 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
210 | dev_priv->back_offset = init->back_offset; |
211 | dev_priv->front_offset = init->front_offset; | |
212 | dev_priv->current_page = 0; | |
7c1c2871 DA |
213 | if (master_priv->sarea_priv) |
214 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 215 | |
1da177e4 LT |
216 | /* Allow hardware batchbuffers unless told otherwise. |
217 | */ | |
218 | dev_priv->allow_batchbuffer = 1; | |
219 | ||
1da177e4 LT |
220 | return 0; |
221 | } | |
222 | ||
84b1fd10 | 223 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
224 | { |
225 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
226 | ||
bf9d8929 | 227 | DRM_DEBUG("%s\n", __func__); |
1da177e4 | 228 | |
1da177e4 LT |
229 | if (dev_priv->ring.map.handle == NULL) { |
230 | DRM_ERROR("can not ioremap virtual address for" | |
231 | " ring buffer\n"); | |
20caafa6 | 232 | return -ENOMEM; |
1da177e4 LT |
233 | } |
234 | ||
235 | /* Program Hardware Status Page */ | |
236 | if (!dev_priv->hw_status_page) { | |
237 | DRM_ERROR("Can not find hardware status page\n"); | |
20caafa6 | 238 | return -EINVAL; |
1da177e4 LT |
239 | } |
240 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); | |
241 | ||
dc7a9319 | 242 | if (dev_priv->status_gfx_addr != 0) |
585fb111 | 243 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
dc7a9319 | 244 | else |
585fb111 | 245 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
1da177e4 LT |
246 | DRM_DEBUG("Enabled hardware status page\n"); |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
c153f45f EA |
251 | static int i915_dma_init(struct drm_device *dev, void *data, |
252 | struct drm_file *file_priv) | |
1da177e4 | 253 | { |
c153f45f | 254 | drm_i915_init_t *init = data; |
1da177e4 LT |
255 | int retcode = 0; |
256 | ||
c153f45f | 257 | switch (init->func) { |
1da177e4 | 258 | case I915_INIT_DMA: |
ba8bbcf6 | 259 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
260 | break; |
261 | case I915_CLEANUP_DMA: | |
262 | retcode = i915_dma_cleanup(dev); | |
263 | break; | |
264 | case I915_RESUME_DMA: | |
0d6aa60b | 265 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
266 | break; |
267 | default: | |
20caafa6 | 268 | retcode = -EINVAL; |
1da177e4 LT |
269 | break; |
270 | } | |
271 | ||
272 | return retcode; | |
273 | } | |
274 | ||
275 | /* Implement basically the same security restrictions as hardware does | |
276 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
277 | * | |
278 | * Most of the calculations below involve calculating the size of a | |
279 | * particular instruction. It's important to get the size right as | |
280 | * that tells us where the next instruction to check is. Any illegal | |
281 | * instruction detected will be given a size of zero, which is a | |
282 | * signal to abort the rest of the buffer. | |
283 | */ | |
284 | static int do_validate_cmd(int cmd) | |
285 | { | |
286 | switch (((cmd >> 29) & 0x7)) { | |
287 | case 0x0: | |
288 | switch ((cmd >> 23) & 0x3f) { | |
289 | case 0x0: | |
290 | return 1; /* MI_NOOP */ | |
291 | case 0x4: | |
292 | return 1; /* MI_FLUSH */ | |
293 | default: | |
294 | return 0; /* disallow everything else */ | |
295 | } | |
296 | break; | |
297 | case 0x1: | |
298 | return 0; /* reserved */ | |
299 | case 0x2: | |
300 | return (cmd & 0xff) + 2; /* 2d commands */ | |
301 | case 0x3: | |
302 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
303 | return 1; | |
304 | ||
305 | switch ((cmd >> 24) & 0x1f) { | |
306 | case 0x1c: | |
307 | return 1; | |
308 | case 0x1d: | |
b5e89ed5 | 309 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
310 | case 0x3: |
311 | return (cmd & 0x1f) + 2; | |
312 | case 0x4: | |
313 | return (cmd & 0xf) + 2; | |
314 | default: | |
315 | return (cmd & 0xffff) + 2; | |
316 | } | |
317 | case 0x1e: | |
318 | if (cmd & (1 << 23)) | |
319 | return (cmd & 0xffff) + 1; | |
320 | else | |
321 | return 1; | |
322 | case 0x1f: | |
323 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
324 | return (cmd & 0x1ffff) + 2; | |
325 | else if (cmd & (1 << 17)) /* indirect random */ | |
326 | if ((cmd & 0xffff) == 0) | |
327 | return 0; /* unknown length, too hard */ | |
328 | else | |
329 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
330 | else | |
331 | return 2; /* indirect sequential */ | |
332 | default: | |
333 | return 0; | |
334 | } | |
335 | default: | |
336 | return 0; | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static int validate_cmd(int cmd) | |
343 | { | |
344 | int ret = do_validate_cmd(cmd); | |
345 | ||
bc5f4523 | 346 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ |
1da177e4 LT |
347 | |
348 | return ret; | |
349 | } | |
350 | ||
84b1fd10 | 351 | static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords) |
1da177e4 LT |
352 | { |
353 | drm_i915_private_t *dev_priv = dev->dev_private; | |
354 | int i; | |
355 | RING_LOCALS; | |
356 | ||
de227f5f | 357 | if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) |
20caafa6 | 358 | return -EINVAL; |
de227f5f | 359 | |
c29b669c | 360 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 361 | |
1da177e4 LT |
362 | for (i = 0; i < dwords;) { |
363 | int cmd, sz; | |
364 | ||
365 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) | |
20caafa6 | 366 | return -EINVAL; |
1da177e4 | 367 | |
1da177e4 | 368 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
20caafa6 | 369 | return -EINVAL; |
1da177e4 | 370 | |
1da177e4 LT |
371 | OUT_RING(cmd); |
372 | ||
373 | while (++i, --sz) { | |
374 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], | |
375 | sizeof(cmd))) { | |
20caafa6 | 376 | return -EINVAL; |
1da177e4 LT |
377 | } |
378 | OUT_RING(cmd); | |
379 | } | |
1da177e4 LT |
380 | } |
381 | ||
de227f5f DA |
382 | if (dwords & 1) |
383 | OUT_RING(0); | |
384 | ||
385 | ADVANCE_LP_RING(); | |
386 | ||
1da177e4 LT |
387 | return 0; |
388 | } | |
389 | ||
673a394b EA |
390 | int |
391 | i915_emit_box(struct drm_device *dev, | |
392 | struct drm_clip_rect __user *boxes, | |
393 | int i, int DR1, int DR4) | |
1da177e4 LT |
394 | { |
395 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 396 | struct drm_clip_rect box; |
1da177e4 LT |
397 | RING_LOCALS; |
398 | ||
399 | if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { | |
20caafa6 | 400 | return -EFAULT; |
1da177e4 LT |
401 | } |
402 | ||
403 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { | |
404 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
405 | box.x1, box.y1, box.x2, box.y2); | |
20caafa6 | 406 | return -EINVAL; |
1da177e4 LT |
407 | } |
408 | ||
c29b669c AH |
409 | if (IS_I965G(dev)) { |
410 | BEGIN_LP_RING(4); | |
411 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
412 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 413 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
414 | OUT_RING(DR4); |
415 | ADVANCE_LP_RING(); | |
416 | } else { | |
417 | BEGIN_LP_RING(6); | |
418 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
419 | OUT_RING(DR1); | |
420 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
421 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
422 | OUT_RING(DR4); | |
423 | OUT_RING(0); | |
424 | ADVANCE_LP_RING(); | |
425 | } | |
1da177e4 LT |
426 | |
427 | return 0; | |
428 | } | |
429 | ||
c29b669c AH |
430 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
431 | * emit. For now, do it in both places: | |
432 | */ | |
433 | ||
84b1fd10 | 434 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
435 | { |
436 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 437 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f DA |
438 | RING_LOCALS; |
439 | ||
c99b058f | 440 | dev_priv->counter++; |
af6061af | 441 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 442 | dev_priv->counter = 0; |
7c1c2871 DA |
443 | if (master_priv->sarea_priv) |
444 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f DA |
445 | |
446 | BEGIN_LP_RING(4); | |
585fb111 | 447 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 448 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
de227f5f DA |
449 | OUT_RING(dev_priv->counter); |
450 | OUT_RING(0); | |
451 | ADVANCE_LP_RING(); | |
452 | } | |
453 | ||
84b1fd10 | 454 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
1da177e4 LT |
455 | drm_i915_cmdbuffer_t * cmd) |
456 | { | |
457 | int nbox = cmd->num_cliprects; | |
458 | int i = 0, count, ret; | |
459 | ||
460 | if (cmd->sz & 0x3) { | |
461 | DRM_ERROR("alignment"); | |
20caafa6 | 462 | return -EINVAL; |
1da177e4 LT |
463 | } |
464 | ||
465 | i915_kernel_lost_context(dev); | |
466 | ||
467 | count = nbox ? nbox : 1; | |
468 | ||
469 | for (i = 0; i < count; i++) { | |
470 | if (i < nbox) { | |
471 | ret = i915_emit_box(dev, cmd->cliprects, i, | |
472 | cmd->DR1, cmd->DR4); | |
473 | if (ret) | |
474 | return ret; | |
475 | } | |
476 | ||
477 | ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); | |
478 | if (ret) | |
479 | return ret; | |
480 | } | |
481 | ||
de227f5f | 482 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
483 | return 0; |
484 | } | |
485 | ||
84b1fd10 | 486 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
1da177e4 LT |
487 | drm_i915_batchbuffer_t * batch) |
488 | { | |
489 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 490 | struct drm_clip_rect __user *boxes = batch->cliprects; |
1da177e4 LT |
491 | int nbox = batch->num_cliprects; |
492 | int i = 0, count; | |
493 | RING_LOCALS; | |
494 | ||
495 | if ((batch->start | batch->used) & 0x7) { | |
496 | DRM_ERROR("alignment"); | |
20caafa6 | 497 | return -EINVAL; |
1da177e4 LT |
498 | } |
499 | ||
500 | i915_kernel_lost_context(dev); | |
501 | ||
502 | count = nbox ? nbox : 1; | |
503 | ||
504 | for (i = 0; i < count; i++) { | |
505 | if (i < nbox) { | |
506 | int ret = i915_emit_box(dev, boxes, i, | |
507 | batch->DR1, batch->DR4); | |
508 | if (ret) | |
509 | return ret; | |
510 | } | |
511 | ||
0790d5e1 | 512 | if (!IS_I830(dev) && !IS_845G(dev)) { |
1da177e4 | 513 | BEGIN_LP_RING(2); |
21f16289 DA |
514 | if (IS_I965G(dev)) { |
515 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
516 | OUT_RING(batch->start); | |
517 | } else { | |
518 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
519 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
520 | } | |
1da177e4 LT |
521 | ADVANCE_LP_RING(); |
522 | } else { | |
523 | BEGIN_LP_RING(4); | |
524 | OUT_RING(MI_BATCH_BUFFER); | |
525 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
526 | OUT_RING(batch->start + batch->used - 4); | |
527 | OUT_RING(0); | |
528 | ADVANCE_LP_RING(); | |
529 | } | |
530 | } | |
531 | ||
de227f5f | 532 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
533 | |
534 | return 0; | |
535 | } | |
536 | ||
af6061af | 537 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
538 | { |
539 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
540 | struct drm_i915_master_private *master_priv = |
541 | dev->primary->master->driver_priv; | |
1da177e4 LT |
542 | RING_LOCALS; |
543 | ||
7c1c2871 | 544 | if (!master_priv->sarea_priv) |
c99b058f KH |
545 | return -EINVAL; |
546 | ||
af6061af | 547 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", |
80a914dc | 548 | __func__, |
af6061af | 549 | dev_priv->current_page, |
7c1c2871 | 550 | master_priv->sarea_priv->pf_current_page); |
1da177e4 | 551 | |
af6061af DA |
552 | i915_kernel_lost_context(dev); |
553 | ||
554 | BEGIN_LP_RING(2); | |
585fb111 | 555 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af DA |
556 | OUT_RING(0); |
557 | ADVANCE_LP_RING(); | |
1da177e4 | 558 | |
af6061af DA |
559 | BEGIN_LP_RING(6); |
560 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
561 | OUT_RING(0); | |
562 | if (dev_priv->current_page == 0) { | |
563 | OUT_RING(dev_priv->back_offset); | |
564 | dev_priv->current_page = 1; | |
1da177e4 | 565 | } else { |
af6061af DA |
566 | OUT_RING(dev_priv->front_offset); |
567 | dev_priv->current_page = 0; | |
1da177e4 | 568 | } |
af6061af DA |
569 | OUT_RING(0); |
570 | ADVANCE_LP_RING(); | |
1da177e4 | 571 | |
af6061af DA |
572 | BEGIN_LP_RING(2); |
573 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
574 | OUT_RING(0); | |
575 | ADVANCE_LP_RING(); | |
1da177e4 | 576 | |
7c1c2871 | 577 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 LT |
578 | |
579 | BEGIN_LP_RING(4); | |
585fb111 | 580 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 581 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
af6061af DA |
582 | OUT_RING(dev_priv->counter); |
583 | OUT_RING(0); | |
1da177e4 LT |
584 | ADVANCE_LP_RING(); |
585 | ||
7c1c2871 | 586 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
af6061af | 587 | return 0; |
1da177e4 LT |
588 | } |
589 | ||
84b1fd10 | 590 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
591 | { |
592 | drm_i915_private_t *dev_priv = dev->dev_private; | |
593 | ||
594 | i915_kernel_lost_context(dev); | |
bf9d8929 | 595 | return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); |
1da177e4 LT |
596 | } |
597 | ||
c153f45f EA |
598 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
599 | struct drm_file *file_priv) | |
1da177e4 | 600 | { |
546b0974 EA |
601 | int ret; |
602 | ||
603 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1da177e4 | 604 | |
546b0974 EA |
605 | mutex_lock(&dev->struct_mutex); |
606 | ret = i915_quiescent(dev); | |
607 | mutex_unlock(&dev->struct_mutex); | |
608 | ||
609 | return ret; | |
1da177e4 LT |
610 | } |
611 | ||
c153f45f EA |
612 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
613 | struct drm_file *file_priv) | |
1da177e4 | 614 | { |
1da177e4 | 615 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 616 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 617 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 618 | master_priv->sarea_priv; |
c153f45f | 619 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 LT |
620 | int ret; |
621 | ||
622 | if (!dev_priv->allow_batchbuffer) { | |
623 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 624 | return -EINVAL; |
1da177e4 LT |
625 | } |
626 | ||
1da177e4 | 627 | DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", |
c153f45f | 628 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 629 | |
546b0974 | 630 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 631 | |
c153f45f EA |
632 | if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, |
633 | batch->num_cliprects * | |
c60ce623 | 634 | sizeof(struct drm_clip_rect))) |
20caafa6 | 635 | return -EFAULT; |
1da177e4 | 636 | |
546b0974 | 637 | mutex_lock(&dev->struct_mutex); |
c153f45f | 638 | ret = i915_dispatch_batchbuffer(dev, batch); |
546b0974 | 639 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 640 | |
c99b058f | 641 | if (sarea_priv) |
0baf823a | 642 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
1da177e4 LT |
643 | return ret; |
644 | } | |
645 | ||
c153f45f EA |
646 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
647 | struct drm_file *file_priv) | |
1da177e4 | 648 | { |
1da177e4 | 649 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 650 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 651 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 652 | master_priv->sarea_priv; |
c153f45f | 653 | drm_i915_cmdbuffer_t *cmdbuf = data; |
1da177e4 LT |
654 | int ret; |
655 | ||
1da177e4 | 656 | DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
c153f45f | 657 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 658 | |
546b0974 | 659 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 660 | |
c153f45f EA |
661 | if (cmdbuf->num_cliprects && |
662 | DRM_VERIFYAREA_READ(cmdbuf->cliprects, | |
663 | cmdbuf->num_cliprects * | |
c60ce623 | 664 | sizeof(struct drm_clip_rect))) { |
1da177e4 | 665 | DRM_ERROR("Fault accessing cliprects\n"); |
20caafa6 | 666 | return -EFAULT; |
1da177e4 LT |
667 | } |
668 | ||
546b0974 | 669 | mutex_lock(&dev->struct_mutex); |
c153f45f | 670 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf); |
546b0974 | 671 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
672 | if (ret) { |
673 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
674 | return ret; | |
675 | } | |
676 | ||
c99b058f | 677 | if (sarea_priv) |
0baf823a | 678 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
1da177e4 LT |
679 | return 0; |
680 | } | |
681 | ||
c153f45f EA |
682 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
683 | struct drm_file *file_priv) | |
1da177e4 | 684 | { |
546b0974 EA |
685 | int ret; |
686 | ||
80a914dc | 687 | DRM_DEBUG("%s\n", __func__); |
1da177e4 | 688 | |
546b0974 | 689 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 690 | |
546b0974 EA |
691 | mutex_lock(&dev->struct_mutex); |
692 | ret = i915_dispatch_flip(dev); | |
693 | mutex_unlock(&dev->struct_mutex); | |
694 | ||
695 | return ret; | |
1da177e4 LT |
696 | } |
697 | ||
c153f45f EA |
698 | static int i915_getparam(struct drm_device *dev, void *data, |
699 | struct drm_file *file_priv) | |
1da177e4 | 700 | { |
1da177e4 | 701 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 702 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
703 | int value; |
704 | ||
705 | if (!dev_priv) { | |
3e684eae | 706 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 707 | return -EINVAL; |
1da177e4 LT |
708 | } |
709 | ||
c153f45f | 710 | switch (param->param) { |
1da177e4 | 711 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 712 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
713 | break; |
714 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
715 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
716 | break; | |
0d6aa60b DA |
717 | case I915_PARAM_LAST_DISPATCH: |
718 | value = READ_BREADCRUMB(dev_priv); | |
719 | break; | |
ed4c9c4a KH |
720 | case I915_PARAM_CHIPSET_ID: |
721 | value = dev->pci_device; | |
722 | break; | |
673a394b | 723 | case I915_PARAM_HAS_GEM: |
ac5c4e76 | 724 | value = dev_priv->has_gem; |
673a394b | 725 | break; |
1da177e4 | 726 | default: |
c153f45f | 727 | DRM_ERROR("Unknown parameter %d\n", param->param); |
20caafa6 | 728 | return -EINVAL; |
1da177e4 LT |
729 | } |
730 | ||
c153f45f | 731 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 732 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 733 | return -EFAULT; |
1da177e4 LT |
734 | } |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
c153f45f EA |
739 | static int i915_setparam(struct drm_device *dev, void *data, |
740 | struct drm_file *file_priv) | |
1da177e4 | 741 | { |
1da177e4 | 742 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 743 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
744 | |
745 | if (!dev_priv) { | |
3e684eae | 746 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 747 | return -EINVAL; |
1da177e4 LT |
748 | } |
749 | ||
c153f45f | 750 | switch (param->param) { |
1da177e4 | 751 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
752 | break; |
753 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 754 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
755 | break; |
756 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 757 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 LT |
758 | break; |
759 | default: | |
c153f45f | 760 | DRM_ERROR("unknown parameter %d\n", param->param); |
20caafa6 | 761 | return -EINVAL; |
1da177e4 LT |
762 | } |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
c153f45f EA |
767 | static int i915_set_status_page(struct drm_device *dev, void *data, |
768 | struct drm_file *file_priv) | |
dc7a9319 | 769 | { |
dc7a9319 | 770 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 771 | drm_i915_hws_addr_t *hws = data; |
b39d50e5 ZW |
772 | |
773 | if (!I915_NEED_GFX_HWS(dev)) | |
774 | return -EINVAL; | |
dc7a9319 WZ |
775 | |
776 | if (!dev_priv) { | |
3e684eae | 777 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 778 | return -EINVAL; |
dc7a9319 | 779 | } |
dc7a9319 | 780 | |
79e53945 JB |
781 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
782 | WARN(1, "tried to set status page when mode setting active\n"); | |
783 | return 0; | |
784 | } | |
785 | ||
c153f45f EA |
786 | printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr); |
787 | ||
788 | dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); | |
dc7a9319 | 789 | |
8b409580 | 790 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
791 | dev_priv->hws_map.size = 4*1024; |
792 | dev_priv->hws_map.type = 0; | |
793 | dev_priv->hws_map.flags = 0; | |
794 | dev_priv->hws_map.mtrr = 0; | |
795 | ||
796 | drm_core_ioremap(&dev_priv->hws_map, dev); | |
797 | if (dev_priv->hws_map.handle == NULL) { | |
dc7a9319 WZ |
798 | i915_dma_cleanup(dev); |
799 | dev_priv->status_gfx_addr = 0; | |
800 | DRM_ERROR("can not ioremap virtual address for" | |
801 | " G33 hw status page\n"); | |
20caafa6 | 802 | return -ENOMEM; |
dc7a9319 WZ |
803 | } |
804 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | |
805 | ||
806 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
585fb111 JB |
807 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
808 | DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", | |
dc7a9319 WZ |
809 | dev_priv->status_gfx_addr); |
810 | DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); | |
811 | return 0; | |
812 | } | |
813 | ||
79e53945 JB |
814 | /** |
815 | * i915_probe_agp - get AGP bootup configuration | |
816 | * @pdev: PCI device | |
817 | * @aperture_size: returns AGP aperture configured size | |
818 | * @preallocated_size: returns size of BIOS preallocated AGP space | |
819 | * | |
820 | * Since Intel integrated graphics are UMA, the BIOS has to set aside | |
821 | * some RAM for the framebuffer at early boot. This code figures out | |
822 | * how much was set aside so we can use it for our own purposes. | |
823 | */ | |
b358d0a6 HE |
824 | static int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size, |
825 | unsigned long *preallocated_size) | |
79e53945 JB |
826 | { |
827 | struct pci_dev *bridge_dev; | |
828 | u16 tmp = 0; | |
829 | unsigned long overhead; | |
830 | ||
831 | bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); | |
832 | if (!bridge_dev) { | |
833 | DRM_ERROR("bridge device not found\n"); | |
834 | return -1; | |
835 | } | |
836 | ||
837 | /* Get the fb aperture size and "stolen" memory amount. */ | |
838 | pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); | |
839 | pci_dev_put(bridge_dev); | |
840 | ||
841 | *aperture_size = 1024 * 1024; | |
842 | *preallocated_size = 1024 * 1024; | |
843 | ||
60fd99e3 | 844 | switch (dev->pdev->device) { |
79e53945 JB |
845 | case PCI_DEVICE_ID_INTEL_82830_CGC: |
846 | case PCI_DEVICE_ID_INTEL_82845G_IG: | |
847 | case PCI_DEVICE_ID_INTEL_82855GM_IG: | |
848 | case PCI_DEVICE_ID_INTEL_82865_IG: | |
849 | if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) | |
850 | *aperture_size *= 64; | |
851 | else | |
852 | *aperture_size *= 128; | |
853 | break; | |
854 | default: | |
855 | /* 9xx supports large sizes, just look at the length */ | |
60fd99e3 | 856 | *aperture_size = pci_resource_len(dev->pdev, 2); |
79e53945 JB |
857 | break; |
858 | } | |
859 | ||
860 | /* | |
861 | * Some of the preallocated space is taken by the GTT | |
862 | * and popup. GTT is 1K per MB of aperture size, and popup is 4K. | |
863 | */ | |
60fd99e3 EA |
864 | if (IS_G4X(dev)) |
865 | overhead = 4096; | |
866 | else | |
867 | overhead = (*aperture_size / 1024) + 4096; | |
868 | ||
79e53945 JB |
869 | switch (tmp & INTEL_855_GMCH_GMS_MASK) { |
870 | case INTEL_855_GMCH_GMS_STOLEN_1M: | |
871 | break; /* 1M already */ | |
872 | case INTEL_855_GMCH_GMS_STOLEN_4M: | |
873 | *preallocated_size *= 4; | |
874 | break; | |
875 | case INTEL_855_GMCH_GMS_STOLEN_8M: | |
876 | *preallocated_size *= 8; | |
877 | break; | |
878 | case INTEL_855_GMCH_GMS_STOLEN_16M: | |
879 | *preallocated_size *= 16; | |
880 | break; | |
881 | case INTEL_855_GMCH_GMS_STOLEN_32M: | |
882 | *preallocated_size *= 32; | |
883 | break; | |
884 | case INTEL_915G_GMCH_GMS_STOLEN_48M: | |
885 | *preallocated_size *= 48; | |
886 | break; | |
887 | case INTEL_915G_GMCH_GMS_STOLEN_64M: | |
888 | *preallocated_size *= 64; | |
889 | break; | |
890 | case INTEL_855_GMCH_GMS_DISABLED: | |
891 | DRM_ERROR("video memory is disabled\n"); | |
892 | return -1; | |
893 | default: | |
894 | DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", | |
895 | tmp & INTEL_855_GMCH_GMS_MASK); | |
896 | return -1; | |
897 | } | |
898 | *preallocated_size -= overhead; | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
903 | static int i915_load_modeset_init(struct drm_device *dev) | |
904 | { | |
905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
906 | unsigned long agp_size, prealloc_size; | |
907 | int fb_bar = IS_I9XX(dev) ? 2 : 0; | |
908 | int ret = 0; | |
909 | ||
aa596629 DA |
910 | dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL); |
911 | if (!dev->devname) { | |
912 | ret = -ENOMEM; | |
913 | goto out; | |
914 | } | |
915 | ||
79e53945 JB |
916 | dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) & |
917 | 0xff000000; | |
918 | ||
919 | DRM_DEBUG("*** fb base 0x%08lx\n", dev->mode_config.fb_base); | |
920 | ||
921 | if (IS_MOBILE(dev) || (IS_I9XX(dev) && !IS_I965G(dev) && !IS_G33(dev))) | |
922 | dev_priv->cursor_needs_physical = true; | |
923 | else | |
924 | dev_priv->cursor_needs_physical = false; | |
925 | ||
aa596629 DA |
926 | ret = i915_probe_agp(dev, &agp_size, &prealloc_size); |
927 | if (ret) | |
928 | goto kfree_devname; | |
79e53945 JB |
929 | |
930 | /* Basic memrange allocator for stolen space (aka vram) */ | |
931 | drm_mm_init(&dev_priv->vram, 0, prealloc_size); | |
932 | ||
933 | /* Let GEM Manage from end of prealloc space to end of aperture */ | |
934 | i915_gem_do_init(dev, prealloc_size, agp_size); | |
935 | ||
936 | ret = i915_gem_init_ringbuffer(dev); | |
937 | if (ret) | |
aa596629 | 938 | goto kfree_devname; |
79e53945 JB |
939 | |
940 | dev_priv->mm.gtt_mapping = | |
941 | io_mapping_create_wc(dev->agp->base, | |
942 | dev->agp->agp_info.aper_size * 1024*1024); | |
943 | ||
944 | /* Allow hardware batchbuffers unless told otherwise. | |
945 | */ | |
946 | dev_priv->allow_batchbuffer = 1; | |
947 | ||
948 | ret = intel_init_bios(dev); | |
949 | if (ret) | |
950 | DRM_INFO("failed to find VBIOS tables\n"); | |
951 | ||
952 | ret = drm_irq_install(dev); | |
953 | if (ret) | |
954 | goto destroy_ringbuffer; | |
955 | ||
956 | /* FIXME: re-add hotplug support */ | |
957 | #if 0 | |
958 | ret = drm_hotplug_init(dev); | |
959 | if (ret) | |
960 | goto destroy_ringbuffer; | |
961 | #endif | |
962 | ||
963 | /* Always safe in the mode setting case. */ | |
964 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
965 | dev->vblank_disable_allowed = 1; | |
966 | ||
967 | /* | |
968 | * Initialize the hardware status page IRQ location. | |
969 | */ | |
970 | ||
971 | I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); | |
972 | ||
973 | intel_modeset_init(dev); | |
974 | ||
975 | drm_helper_initial_config(dev, false); | |
976 | ||
79e53945 JB |
977 | return 0; |
978 | ||
79e53945 JB |
979 | destroy_ringbuffer: |
980 | i915_gem_cleanup_ringbuffer(dev); | |
aa596629 DA |
981 | kfree_devname: |
982 | kfree(dev->devname); | |
79e53945 JB |
983 | out: |
984 | return ret; | |
985 | } | |
986 | ||
7c1c2871 DA |
987 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
988 | { | |
989 | struct drm_i915_master_private *master_priv; | |
990 | ||
991 | master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER); | |
992 | if (!master_priv) | |
993 | return -ENOMEM; | |
994 | ||
995 | master->driver_priv = master_priv; | |
996 | return 0; | |
997 | } | |
998 | ||
999 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1000 | { | |
1001 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1002 | ||
1003 | if (!master_priv) | |
1004 | return; | |
1005 | ||
1006 | drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER); | |
1007 | ||
1008 | master->driver_priv = NULL; | |
1009 | } | |
1010 | ||
79e53945 JB |
1011 | /** |
1012 | * i915_driver_load - setup chip and create an initial config | |
1013 | * @dev: DRM device | |
1014 | * @flags: startup flags | |
1015 | * | |
1016 | * The driver load routine has to do several things: | |
1017 | * - drive output discovery via intel_modeset_init() | |
1018 | * - initialize the memory manager | |
1019 | * - allocate initial config memory | |
1020 | * - setup the DRM framebuffer with the allocated memory | |
1021 | */ | |
84b1fd10 | 1022 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1023 | { |
ba8bbcf6 JB |
1024 | struct drm_i915_private *dev_priv = dev->dev_private; |
1025 | unsigned long base, size; | |
1026 | int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; | |
1027 | ||
22eae947 DA |
1028 | /* i915 has 4 more counters */ |
1029 | dev->counters += 4; | |
1030 | dev->types[6] = _DRM_STAT_IRQ; | |
1031 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1032 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1033 | dev->types[9] = _DRM_STAT_DMA; | |
1034 | ||
ba8bbcf6 JB |
1035 | dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); |
1036 | if (dev_priv == NULL) | |
1037 | return -ENOMEM; | |
1038 | ||
1039 | memset(dev_priv, 0, sizeof(drm_i915_private_t)); | |
1040 | ||
1041 | dev->dev_private = (void *)dev_priv; | |
673a394b | 1042 | dev_priv->dev = dev; |
ba8bbcf6 JB |
1043 | |
1044 | /* Add register map (needed for suspend/resume) */ | |
1045 | base = drm_get_resource_start(dev, mmio_bar); | |
1046 | size = drm_get_resource_len(dev, mmio_bar); | |
1047 | ||
3043c60c | 1048 | dev_priv->regs = ioremap(base, size); |
79e53945 JB |
1049 | if (!dev_priv->regs) { |
1050 | DRM_ERROR("failed to map registers\n"); | |
1051 | ret = -EIO; | |
1052 | goto free_priv; | |
1053 | } | |
ed4cb414 | 1054 | |
ac5c4e76 DA |
1055 | #ifdef CONFIG_HIGHMEM64G |
1056 | /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */ | |
1057 | dev_priv->has_gem = 0; | |
1058 | #else | |
1059 | /* enable GEM by default */ | |
1060 | dev_priv->has_gem = 1; | |
1061 | #endif | |
1062 | ||
673a394b EA |
1063 | i915_gem_load(dev); |
1064 | ||
398c9cb2 KP |
1065 | /* Init HWS */ |
1066 | if (!I915_NEED_GFX_HWS(dev)) { | |
1067 | ret = i915_init_phys_hws(dev); | |
1068 | if (ret != 0) | |
79e53945 | 1069 | goto out_rmmap; |
398c9cb2 | 1070 | } |
ed4cb414 EA |
1071 | |
1072 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
1073 | * integrated graphics even though the support isn't actually there | |
1074 | * according to the published specs. It doesn't appear to function | |
1075 | * correctly in testing on 945G. | |
1076 | * This may be a side effect of MSI having been made available for PEG | |
1077 | * and the registers being closely associated. | |
d1ed629f KP |
1078 | * |
1079 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1080 | * be lost or delayed, but we use them anyways to avoid |
1081 | * stuck interrupts on some machines. | |
ed4cb414 | 1082 | */ |
b60678a7 | 1083 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1084 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1085 | |
8ee1c3db MG |
1086 | intel_opregion_init(dev); |
1087 | ||
ed4cb414 | 1088 | spin_lock_init(&dev_priv->user_irq_lock); |
79e53945 | 1089 | dev_priv->user_irq_refcount = 0; |
ed4cb414 | 1090 | |
52440211 KP |
1091 | ret = drm_vblank_init(dev, I915_NUM_PIPE); |
1092 | ||
1093 | if (ret) { | |
1094 | (void) i915_driver_unload(dev); | |
1095 | return ret; | |
1096 | } | |
1097 | ||
79e53945 JB |
1098 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1099 | ret = i915_load_modeset_init(dev); | |
1100 | if (ret < 0) { | |
1101 | DRM_ERROR("failed to init modeset\n"); | |
1102 | goto out_rmmap; | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | return 0; | |
1107 | ||
1108 | out_rmmap: | |
1109 | iounmap(dev_priv->regs); | |
1110 | free_priv: | |
1111 | drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER); | |
ba8bbcf6 JB |
1112 | return ret; |
1113 | } | |
1114 | ||
1115 | int i915_driver_unload(struct drm_device *dev) | |
1116 | { | |
1117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1118 | ||
79e53945 JB |
1119 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1120 | io_mapping_free(dev_priv->mm.gtt_mapping); | |
1121 | drm_irq_uninstall(dev); | |
1122 | } | |
1123 | ||
ed4cb414 EA |
1124 | if (dev->pdev->msi_enabled) |
1125 | pci_disable_msi(dev->pdev); | |
1126 | ||
3043c60c EA |
1127 | if (dev_priv->regs != NULL) |
1128 | iounmap(dev_priv->regs); | |
ba8bbcf6 | 1129 | |
8ee1c3db MG |
1130 | intel_opregion_free(dev); |
1131 | ||
79e53945 JB |
1132 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1133 | intel_modeset_cleanup(dev); | |
1134 | ||
1135 | mutex_lock(&dev->struct_mutex); | |
1136 | i915_gem_cleanup_ringbuffer(dev); | |
1137 | mutex_unlock(&dev->struct_mutex); | |
1138 | drm_mm_takedown(&dev_priv->vram); | |
1139 | i915_gem_lastclose(dev); | |
1140 | } | |
1141 | ||
ba8bbcf6 JB |
1142 | drm_free(dev->dev_private, sizeof(drm_i915_private_t), |
1143 | DRM_MEM_DRIVER); | |
1144 | ||
22eae947 DA |
1145 | return 0; |
1146 | } | |
1147 | ||
673a394b EA |
1148 | int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
1149 | { | |
1150 | struct drm_i915_file_private *i915_file_priv; | |
1151 | ||
1152 | DRM_DEBUG("\n"); | |
1153 | i915_file_priv = (struct drm_i915_file_private *) | |
1154 | drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES); | |
1155 | ||
1156 | if (!i915_file_priv) | |
1157 | return -ENOMEM; | |
1158 | ||
1159 | file_priv->driver_priv = i915_file_priv; | |
1160 | ||
1161 | i915_file_priv->mm.last_gem_seqno = 0; | |
1162 | i915_file_priv->mm.last_gem_throttle_seqno = 0; | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
79e53945 JB |
1167 | /** |
1168 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1169 | * @dev: DRM device | |
1170 | * | |
1171 | * Take care of cleaning up after all DRM clients have exited. In the | |
1172 | * mode setting case, we want to restore the kernel's initial mode (just | |
1173 | * in case the last client left us in a bad state). | |
1174 | * | |
1175 | * Additionally, in the non-mode setting case, we'll tear down the AGP | |
1176 | * and DMA structures, since the kernel won't be using them, and clea | |
1177 | * up any GEM state. | |
1178 | */ | |
84b1fd10 | 1179 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1180 | { |
ba8bbcf6 JB |
1181 | drm_i915_private_t *dev_priv = dev->dev_private; |
1182 | ||
79e53945 JB |
1183 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
1184 | intelfb_restore(); | |
144a75fa | 1185 | return; |
79e53945 | 1186 | } |
144a75fa | 1187 | |
673a394b EA |
1188 | i915_gem_lastclose(dev); |
1189 | ||
ba8bbcf6 | 1190 | if (dev_priv->agp_heap) |
b5e89ed5 | 1191 | i915_mem_takedown(&(dev_priv->agp_heap)); |
ba8bbcf6 | 1192 | |
b5e89ed5 | 1193 | i915_dma_cleanup(dev); |
1da177e4 LT |
1194 | } |
1195 | ||
6c340eac | 1196 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1197 | { |
ba8bbcf6 | 1198 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
1199 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
1200 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); | |
1da177e4 LT |
1201 | } |
1202 | ||
673a394b EA |
1203 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) |
1204 | { | |
1205 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
1206 | ||
1207 | drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES); | |
1208 | } | |
1209 | ||
c153f45f EA |
1210 | struct drm_ioctl_desc i915_ioctls[] = { |
1211 | DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1212 | DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1213 | DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1214 | DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1215 | DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1216 | DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
1217 | DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), | |
1218 | DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1219 | DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), | |
1220 | DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), | |
1221 | DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1222 | DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), | |
1223 | DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1224 | DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1225 | DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), | |
1226 | DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
4b408939 | 1227 | DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2bdf00b2 | 1228 | DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
673a394b EA |
1229 | DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), |
1230 | DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1231 | DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1232 | DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), | |
1233 | DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), | |
2bdf00b2 DA |
1234 | DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1235 | DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
673a394b EA |
1236 | DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), |
1237 | DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), | |
1238 | DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), | |
1239 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), | |
de151cf6 | 1240 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0), |
673a394b EA |
1241 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), |
1242 | DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), | |
1243 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), | |
1244 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), | |
5a125c3c | 1245 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0), |
c94f7029 DA |
1246 | }; |
1247 | ||
1248 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
1249 | |
1250 | /** | |
1251 | * Determine if the device really is AGP or not. | |
1252 | * | |
1253 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
1254 | * PCI-e. | |
1255 | * | |
1256 | * \param dev The device to be tested. | |
1257 | * | |
1258 | * \returns | |
1259 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
1260 | */ | |
84b1fd10 | 1261 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1262 | { |
1263 | return 1; | |
1264 | } |