]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
d1d70677 | 31 | #include <linux/async.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_fb_helper.h> | |
4f03b1fc | 35 | #include <drm/drm_legacy.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
1da177e4 | 38 | #include "i915_drv.h" |
1c5d22f7 | 39 | #include "i915_trace.h" |
dcdb1674 | 40 | #include <linux/pci.h> |
a4de0526 DV |
41 | #include <linux/console.h> |
42 | #include <linux/vt.h> | |
28d52043 | 43 | #include <linux/vgaarb.h> |
c4804411 ZW |
44 | #include <linux/acpi.h> |
45 | #include <linux/pnp.h> | |
6a9ee8af | 46 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
44834a67 | 48 | #include <acpi/video.h> |
8a187455 PZ |
49 | #include <linux/pm.h> |
50 | #include <linux/pm_runtime.h> | |
4bdc7293 | 51 | #include <linux/oom.h> |
1da177e4 | 52 | |
09422b2e DV |
53 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
54 | ||
55 | #define BEGIN_LP_RING(n) \ | |
56 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
57 | ||
58 | #define OUT_RING(x) \ | |
59 | intel_ring_emit(LP_RING(dev_priv), x) | |
60 | ||
61 | #define ADVANCE_LP_RING() \ | |
09246732 | 62 | __intel_ring_advance(LP_RING(dev_priv)) |
09422b2e DV |
63 | |
64 | /** | |
65 | * Lock test for when it's just for synchronization of ring access. | |
66 | * | |
67 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
68 | * has access to the ring. | |
69 | */ | |
70 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ | |
ee1b1e5e | 71 | if (LP_RING(dev->dev_private)->buffer->obj == NULL) \ |
09422b2e DV |
72 | LOCK_TEST_WITH_RETURN(dev, file); \ |
73 | } while (0) | |
74 | ||
316d3884 DV |
75 | static inline u32 |
76 | intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) | |
77 | { | |
78 | if (I915_NEED_GFX_HWS(dev_priv->dev)) | |
79 | return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); | |
80 | else | |
81 | return intel_read_status_page(LP_RING(dev_priv), reg); | |
82 | } | |
83 | ||
84 | #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) | |
09422b2e DV |
85 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
86 | #define I915_BREADCRUMB_INDEX 0x21 | |
87 | ||
d05c617e DV |
88 | void i915_update_dri1_breadcrumb(struct drm_device *dev) |
89 | { | |
4c8a4be9 | 90 | struct drm_i915_private *dev_priv = dev->dev_private; |
d05c617e DV |
91 | struct drm_i915_master_private *master_priv; |
92 | ||
6c719fac DV |
93 | /* |
94 | * The dri breadcrumb update races against the drm master disappearing. | |
95 | * Instead of trying to fix this (this is by far not the only ums issue) | |
96 | * just don't do the update in kms mode. | |
97 | */ | |
98 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
99 | return; | |
100 | ||
d05c617e DV |
101 | if (dev->primary->master) { |
102 | master_priv = dev->primary->master->driver_priv; | |
103 | if (master_priv->sarea_priv) | |
104 | master_priv->sarea_priv->last_dispatch = | |
105 | READ_BREADCRUMB(dev_priv); | |
106 | } | |
107 | } | |
108 | ||
4cbf74cc CW |
109 | static void i915_write_hws_pga(struct drm_device *dev) |
110 | { | |
4c8a4be9 | 111 | struct drm_i915_private *dev_priv = dev->dev_private; |
4cbf74cc CW |
112 | u32 addr; |
113 | ||
114 | addr = dev_priv->status_page_dmah->busaddr; | |
115 | if (INTEL_INFO(dev)->gen >= 4) | |
116 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
117 | I915_WRITE(HWS_PGA, addr); | |
118 | } | |
119 | ||
398c9cb2 KP |
120 | /** |
121 | * Frees the hardware status page, whether it's a physical address or a virtual | |
122 | * address set up by the X Server. | |
123 | */ | |
3043c60c | 124 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 | 125 | { |
4c8a4be9 | 126 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 127 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
1ec14ad3 | 128 | |
398c9cb2 KP |
129 | if (dev_priv->status_page_dmah) { |
130 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
131 | dev_priv->status_page_dmah = NULL; | |
132 | } | |
133 | ||
1ec14ad3 CW |
134 | if (ring->status_page.gfx_addr) { |
135 | ring->status_page.gfx_addr = 0; | |
316d3884 | 136 | iounmap(dev_priv->dri1.gfx_hws_cpu_addr); |
398c9cb2 KP |
137 | } |
138 | ||
139 | /* Need to rewrite hardware status page */ | |
140 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
141 | } | |
142 | ||
1a5036bf | 143 | void i915_kernel_lost_context(struct drm_device *dev) |
1da177e4 | 144 | { |
4c8a4be9 | 145 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 146 | struct drm_i915_master_private *master_priv; |
a4872ba6 | 147 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
93b0a4e0 | 148 | struct intel_ringbuffer *ringbuf = ring->buffer; |
1da177e4 | 149 | |
79e53945 JB |
150 | /* |
151 | * We should never lose context on the ring with modesetting | |
152 | * as we don't expose it to userspace | |
153 | */ | |
154 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
155 | return; | |
156 | ||
93b0a4e0 OM |
157 | ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
158 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
159 | ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE); | |
160 | if (ringbuf->space < 0) | |
161 | ringbuf->space += ringbuf->size; | |
1da177e4 | 162 | |
7c1c2871 DA |
163 | if (!dev->primary->master) |
164 | return; | |
165 | ||
166 | master_priv = dev->primary->master->driver_priv; | |
93b0a4e0 | 167 | if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv) |
7c1c2871 | 168 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; |
1da177e4 LT |
169 | } |
170 | ||
1a5036bf | 171 | static int i915_dma_cleanup(struct drm_device *dev) |
1da177e4 | 172 | { |
4c8a4be9 | 173 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
174 | int i; |
175 | ||
1da177e4 LT |
176 | /* Make sure interrupts are disabled here because the uninstall ioctl |
177 | * may not have been called from userspace and after dev_private | |
178 | * is freed, it's too late. | |
179 | */ | |
ed4cb414 | 180 | if (dev->irq_enabled) |
b5e89ed5 | 181 | drm_irq_uninstall(dev); |
1da177e4 | 182 | |
ee0c6bfb | 183 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 CW |
184 | for (i = 0; i < I915_NUM_RINGS; i++) |
185 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
ee0c6bfb | 186 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 187 | |
398c9cb2 KP |
188 | /* Clear the HWS virtual address at teardown */ |
189 | if (I915_NEED_GFX_HWS(dev)) | |
190 | i915_free_hws(dev); | |
1da177e4 LT |
191 | |
192 | return 0; | |
193 | } | |
194 | ||
1a5036bf | 195 | static int i915_initialize(struct drm_device *dev, drm_i915_init_t *init) |
1da177e4 | 196 | { |
4c8a4be9 | 197 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 198 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
e8616b6c | 199 | int ret; |
1da177e4 | 200 | |
9fc5cde7 | 201 | master_priv->sarea = drm_legacy_getsarea(dev); |
3a03ac1a DA |
202 | if (master_priv->sarea) { |
203 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
204 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
205 | } else { | |
8a4c47f3 | 206 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
207 | } |
208 | ||
673a394b | 209 | if (init->ring_size != 0) { |
ee1b1e5e | 210 | if (LP_RING(dev_priv)->buffer->obj != NULL) { |
673a394b EA |
211 | i915_dma_cleanup(dev); |
212 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
213 | "GEM mode\n"); | |
214 | return -EINVAL; | |
215 | } | |
1da177e4 | 216 | |
e8616b6c CW |
217 | ret = intel_render_ring_init_dri(dev, |
218 | init->ring_start, | |
219 | init->ring_size); | |
220 | if (ret) { | |
673a394b | 221 | i915_dma_cleanup(dev); |
e8616b6c | 222 | return ret; |
673a394b | 223 | } |
1da177e4 LT |
224 | } |
225 | ||
5d985ac8 DV |
226 | dev_priv->dri1.cpp = init->cpp; |
227 | dev_priv->dri1.back_offset = init->back_offset; | |
228 | dev_priv->dri1.front_offset = init->front_offset; | |
229 | dev_priv->dri1.current_page = 0; | |
7c1c2871 DA |
230 | if (master_priv->sarea_priv) |
231 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 232 | |
1da177e4 LT |
233 | /* Allow hardware batchbuffers unless told otherwise. |
234 | */ | |
8781342d | 235 | dev_priv->dri1.allow_batchbuffer = 1; |
1da177e4 | 236 | |
1da177e4 LT |
237 | return 0; |
238 | } | |
239 | ||
1a5036bf | 240 | static int i915_dma_resume(struct drm_device *dev) |
1da177e4 | 241 | { |
4c8a4be9 | 242 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 243 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
1da177e4 | 244 | |
8a4c47f3 | 245 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 246 | |
ee1b1e5e | 247 | if (ring->buffer->virtual_start == NULL) { |
1da177e4 LT |
248 | DRM_ERROR("can not ioremap virtual address for" |
249 | " ring buffer\n"); | |
20caafa6 | 250 | return -ENOMEM; |
1da177e4 LT |
251 | } |
252 | ||
253 | /* Program Hardware Status Page */ | |
8187a2b7 | 254 | if (!ring->status_page.page_addr) { |
1da177e4 | 255 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 256 | return -EINVAL; |
1da177e4 | 257 | } |
8a4c47f3 | 258 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
259 | ring->status_page.page_addr); |
260 | if (ring->status_page.gfx_addr != 0) | |
78501eac | 261 | intel_ring_setup_status_page(ring); |
dc7a9319 | 262 | else |
4cbf74cc | 263 | i915_write_hws_pga(dev); |
8187a2b7 | 264 | |
8a4c47f3 | 265 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
266 | |
267 | return 0; | |
268 | } | |
269 | ||
c153f45f EA |
270 | static int i915_dma_init(struct drm_device *dev, void *data, |
271 | struct drm_file *file_priv) | |
1da177e4 | 272 | { |
c153f45f | 273 | drm_i915_init_t *init = data; |
1da177e4 LT |
274 | int retcode = 0; |
275 | ||
cd9d4e9f DV |
276 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
277 | return -ENODEV; | |
278 | ||
c153f45f | 279 | switch (init->func) { |
1da177e4 | 280 | case I915_INIT_DMA: |
ba8bbcf6 | 281 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
282 | break; |
283 | case I915_CLEANUP_DMA: | |
284 | retcode = i915_dma_cleanup(dev); | |
285 | break; | |
286 | case I915_RESUME_DMA: | |
0d6aa60b | 287 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
288 | break; |
289 | default: | |
20caafa6 | 290 | retcode = -EINVAL; |
1da177e4 LT |
291 | break; |
292 | } | |
293 | ||
294 | return retcode; | |
295 | } | |
296 | ||
297 | /* Implement basically the same security restrictions as hardware does | |
298 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
299 | * | |
300 | * Most of the calculations below involve calculating the size of a | |
301 | * particular instruction. It's important to get the size right as | |
302 | * that tells us where the next instruction to check is. Any illegal | |
303 | * instruction detected will be given a size of zero, which is a | |
304 | * signal to abort the rest of the buffer. | |
305 | */ | |
e1f99ce6 | 306 | static int validate_cmd(int cmd) |
1da177e4 LT |
307 | { |
308 | switch (((cmd >> 29) & 0x7)) { | |
309 | case 0x0: | |
310 | switch ((cmd >> 23) & 0x3f) { | |
311 | case 0x0: | |
312 | return 1; /* MI_NOOP */ | |
313 | case 0x4: | |
314 | return 1; /* MI_FLUSH */ | |
315 | default: | |
316 | return 0; /* disallow everything else */ | |
317 | } | |
318 | break; | |
319 | case 0x1: | |
320 | return 0; /* reserved */ | |
321 | case 0x2: | |
322 | return (cmd & 0xff) + 2; /* 2d commands */ | |
323 | case 0x3: | |
324 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
325 | return 1; | |
326 | ||
327 | switch ((cmd >> 24) & 0x1f) { | |
328 | case 0x1c: | |
329 | return 1; | |
330 | case 0x1d: | |
b5e89ed5 | 331 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
332 | case 0x3: |
333 | return (cmd & 0x1f) + 2; | |
334 | case 0x4: | |
335 | return (cmd & 0xf) + 2; | |
336 | default: | |
337 | return (cmd & 0xffff) + 2; | |
338 | } | |
339 | case 0x1e: | |
340 | if (cmd & (1 << 23)) | |
341 | return (cmd & 0xffff) + 1; | |
342 | else | |
343 | return 1; | |
344 | case 0x1f: | |
345 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
346 | return (cmd & 0x1ffff) + 2; | |
347 | else if (cmd & (1 << 17)) /* indirect random */ | |
348 | if ((cmd & 0xffff) == 0) | |
349 | return 0; /* unknown length, too hard */ | |
350 | else | |
351 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
352 | else | |
353 | return 2; /* indirect sequential */ | |
354 | default: | |
355 | return 0; | |
356 | } | |
357 | default: | |
358 | return 0; | |
359 | } | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
1a5036bf | 364 | static int i915_emit_cmds(struct drm_device *dev, int *buffer, int dwords) |
1da177e4 | 365 | { |
4c8a4be9 | 366 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 367 | int i, ret; |
1da177e4 | 368 | |
ee1b1e5e | 369 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8) |
20caafa6 | 370 | return -EINVAL; |
de227f5f | 371 | |
1da177e4 | 372 | for (i = 0; i < dwords;) { |
e1f99ce6 | 373 | int sz = validate_cmd(buffer[i]); |
1a5036bf | 374 | |
e1f99ce6 | 375 | if (sz == 0 || i + sz > dwords) |
20caafa6 | 376 | return -EINVAL; |
e1f99ce6 | 377 | i += sz; |
1da177e4 LT |
378 | } |
379 | ||
e1f99ce6 CW |
380 | ret = BEGIN_LP_RING((dwords+1)&~1); |
381 | if (ret) | |
382 | return ret; | |
383 | ||
384 | for (i = 0; i < dwords; i++) | |
385 | OUT_RING(buffer[i]); | |
de227f5f DA |
386 | if (dwords & 1) |
387 | OUT_RING(0); | |
388 | ||
389 | ADVANCE_LP_RING(); | |
390 | ||
1da177e4 LT |
391 | return 0; |
392 | } | |
393 | ||
673a394b EA |
394 | int |
395 | i915_emit_box(struct drm_device *dev, | |
c4e7a414 CW |
396 | struct drm_clip_rect *box, |
397 | int DR1, int DR4) | |
1da177e4 | 398 | { |
e1f99ce6 | 399 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 400 | int ret; |
1da177e4 | 401 | |
c4e7a414 CW |
402 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
403 | box->y2 <= 0 || box->x2 <= 0) { | |
1da177e4 | 404 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
c4e7a414 | 405 | box->x1, box->y1, box->x2, box->y2); |
20caafa6 | 406 | return -EINVAL; |
1da177e4 LT |
407 | } |
408 | ||
a6c45cf0 | 409 | if (INTEL_INFO(dev)->gen >= 4) { |
e1f99ce6 CW |
410 | ret = BEGIN_LP_RING(4); |
411 | if (ret) | |
412 | return ret; | |
413 | ||
c29b669c | 414 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
c4e7a414 CW |
415 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
416 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c | 417 | OUT_RING(DR4); |
c29b669c | 418 | } else { |
e1f99ce6 CW |
419 | ret = BEGIN_LP_RING(6); |
420 | if (ret) | |
421 | return ret; | |
422 | ||
c29b669c AH |
423 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
424 | OUT_RING(DR1); | |
c4e7a414 CW |
425 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
426 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c AH |
427 | OUT_RING(DR4); |
428 | OUT_RING(0); | |
c29b669c | 429 | } |
e1f99ce6 | 430 | ADVANCE_LP_RING(); |
1da177e4 LT |
431 | |
432 | return 0; | |
433 | } | |
434 | ||
c29b669c AH |
435 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
436 | * emit. For now, do it in both places: | |
437 | */ | |
438 | ||
84b1fd10 | 439 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f | 440 | { |
4c8a4be9 | 441 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 442 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 443 | |
231f42a4 DV |
444 | dev_priv->dri1.counter++; |
445 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
446 | dev_priv->dri1.counter = 0; | |
7c1c2871 | 447 | if (master_priv->sarea_priv) |
231f42a4 | 448 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
de227f5f | 449 | |
e1f99ce6 CW |
450 | if (BEGIN_LP_RING(4) == 0) { |
451 | OUT_RING(MI_STORE_DWORD_INDEX); | |
452 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 453 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
454 | OUT_RING(0); |
455 | ADVANCE_LP_RING(); | |
456 | } | |
de227f5f DA |
457 | } |
458 | ||
1a5036bf | 459 | static int i915_dispatch_cmdbuffer(struct drm_device *dev, |
201361a5 EA |
460 | drm_i915_cmdbuffer_t *cmd, |
461 | struct drm_clip_rect *cliprects, | |
462 | void *cmdbuf) | |
1da177e4 LT |
463 | { |
464 | int nbox = cmd->num_cliprects; | |
465 | int i = 0, count, ret; | |
466 | ||
467 | if (cmd->sz & 0x3) { | |
468 | DRM_ERROR("alignment"); | |
20caafa6 | 469 | return -EINVAL; |
1da177e4 LT |
470 | } |
471 | ||
472 | i915_kernel_lost_context(dev); | |
473 | ||
474 | count = nbox ? nbox : 1; | |
475 | ||
476 | for (i = 0; i < count; i++) { | |
477 | if (i < nbox) { | |
c4e7a414 | 478 | ret = i915_emit_box(dev, &cliprects[i], |
1da177e4 LT |
479 | cmd->DR1, cmd->DR4); |
480 | if (ret) | |
481 | return ret; | |
482 | } | |
483 | ||
201361a5 | 484 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
485 | if (ret) |
486 | return ret; | |
487 | } | |
488 | ||
de227f5f | 489 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
490 | return 0; |
491 | } | |
492 | ||
1a5036bf RS |
493 | static int i915_dispatch_batchbuffer(struct drm_device *dev, |
494 | drm_i915_batchbuffer_t *batch, | |
201361a5 | 495 | struct drm_clip_rect *cliprects) |
1da177e4 | 496 | { |
e1f99ce6 | 497 | struct drm_i915_private *dev_priv = dev->dev_private; |
1da177e4 | 498 | int nbox = batch->num_cliprects; |
e1f99ce6 | 499 | int i, count, ret; |
1da177e4 LT |
500 | |
501 | if ((batch->start | batch->used) & 0x7) { | |
502 | DRM_ERROR("alignment"); | |
20caafa6 | 503 | return -EINVAL; |
1da177e4 LT |
504 | } |
505 | ||
506 | i915_kernel_lost_context(dev); | |
507 | ||
508 | count = nbox ? nbox : 1; | |
1da177e4 LT |
509 | for (i = 0; i < count; i++) { |
510 | if (i < nbox) { | |
c4e7a414 | 511 | ret = i915_emit_box(dev, &cliprects[i], |
e1f99ce6 | 512 | batch->DR1, batch->DR4); |
1da177e4 LT |
513 | if (ret) |
514 | return ret; | |
515 | } | |
516 | ||
0790d5e1 | 517 | if (!IS_I830(dev) && !IS_845G(dev)) { |
e1f99ce6 CW |
518 | ret = BEGIN_LP_RING(2); |
519 | if (ret) | |
520 | return ret; | |
521 | ||
a6c45cf0 | 522 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
523 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
524 | OUT_RING(batch->start); | |
525 | } else { | |
526 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
527 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
528 | } | |
1da177e4 | 529 | } else { |
e1f99ce6 CW |
530 | ret = BEGIN_LP_RING(4); |
531 | if (ret) | |
532 | return ret; | |
533 | ||
1da177e4 LT |
534 | OUT_RING(MI_BATCH_BUFFER); |
535 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
536 | OUT_RING(batch->start + batch->used - 4); | |
537 | OUT_RING(0); | |
1da177e4 | 538 | } |
e1f99ce6 | 539 | ADVANCE_LP_RING(); |
1da177e4 LT |
540 | } |
541 | ||
1cafd347 | 542 | |
f00a3ddf | 543 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
544 | if (BEGIN_LP_RING(2) == 0) { |
545 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
546 | OUT_RING(MI_NOOP); | |
547 | ADVANCE_LP_RING(); | |
548 | } | |
1cafd347 | 549 | } |
1da177e4 | 550 | |
e1f99ce6 | 551 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
552 | return 0; |
553 | } | |
554 | ||
1a5036bf | 555 | static int i915_dispatch_flip(struct drm_device *dev) |
1da177e4 | 556 | { |
4c8a4be9 | 557 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 DA |
558 | struct drm_i915_master_private *master_priv = |
559 | dev->primary->master->driver_priv; | |
e1f99ce6 | 560 | int ret; |
1da177e4 | 561 | |
7c1c2871 | 562 | if (!master_priv->sarea_priv) |
c99b058f KH |
563 | return -EINVAL; |
564 | ||
8a4c47f3 | 565 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 566 | __func__, |
5d985ac8 | 567 | dev_priv->dri1.current_page, |
be25ed9c | 568 | master_priv->sarea_priv->pf_current_page); |
1da177e4 | 569 | |
af6061af DA |
570 | i915_kernel_lost_context(dev); |
571 | ||
e1f99ce6 CW |
572 | ret = BEGIN_LP_RING(10); |
573 | if (ret) | |
574 | return ret; | |
575 | ||
585fb111 | 576 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af | 577 | OUT_RING(0); |
1da177e4 | 578 | |
af6061af DA |
579 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
580 | OUT_RING(0); | |
5d985ac8 DV |
581 | if (dev_priv->dri1.current_page == 0) { |
582 | OUT_RING(dev_priv->dri1.back_offset); | |
583 | dev_priv->dri1.current_page = 1; | |
1da177e4 | 584 | } else { |
5d985ac8 DV |
585 | OUT_RING(dev_priv->dri1.front_offset); |
586 | dev_priv->dri1.current_page = 0; | |
1da177e4 | 587 | } |
af6061af | 588 | OUT_RING(0); |
1da177e4 | 589 | |
af6061af DA |
590 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
591 | OUT_RING(0); | |
e1f99ce6 | 592 | |
af6061af | 593 | ADVANCE_LP_RING(); |
1da177e4 | 594 | |
231f42a4 | 595 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++; |
1da177e4 | 596 | |
e1f99ce6 CW |
597 | if (BEGIN_LP_RING(4) == 0) { |
598 | OUT_RING(MI_STORE_DWORD_INDEX); | |
599 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 600 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
601 | OUT_RING(0); |
602 | ADVANCE_LP_RING(); | |
603 | } | |
1da177e4 | 604 | |
5d985ac8 | 605 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
af6061af | 606 | return 0; |
1da177e4 LT |
607 | } |
608 | ||
1ec14ad3 | 609 | static int i915_quiescent(struct drm_device *dev) |
1da177e4 | 610 | { |
1da177e4 | 611 | i915_kernel_lost_context(dev); |
3e960501 | 612 | return intel_ring_idle(LP_RING(dev->dev_private)); |
1da177e4 LT |
613 | } |
614 | ||
c153f45f EA |
615 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
616 | struct drm_file *file_priv) | |
1da177e4 | 617 | { |
546b0974 EA |
618 | int ret; |
619 | ||
cd9d4e9f DV |
620 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
621 | return -ENODEV; | |
622 | ||
546b0974 | 623 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 624 | |
546b0974 EA |
625 | mutex_lock(&dev->struct_mutex); |
626 | ret = i915_quiescent(dev); | |
627 | mutex_unlock(&dev->struct_mutex); | |
628 | ||
629 | return ret; | |
1da177e4 LT |
630 | } |
631 | ||
c153f45f EA |
632 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
633 | struct drm_file *file_priv) | |
1da177e4 | 634 | { |
4c8a4be9 | 635 | struct drm_i915_private *dev_priv = dev->dev_private; |
4d10cc0f DV |
636 | struct drm_i915_master_private *master_priv; |
637 | drm_i915_sarea_t *sarea_priv; | |
c153f45f | 638 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 639 | int ret; |
201361a5 | 640 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 | 641 | |
cd9d4e9f DV |
642 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
643 | return -ENODEV; | |
644 | ||
4d10cc0f DV |
645 | master_priv = dev->primary->master->driver_priv; |
646 | sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv; | |
647 | ||
8781342d | 648 | if (!dev_priv->dri1.allow_batchbuffer) { |
1da177e4 | 649 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
20caafa6 | 650 | return -EINVAL; |
1da177e4 LT |
651 | } |
652 | ||
8a4c47f3 | 653 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 654 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 655 | |
546b0974 | 656 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 657 | |
201361a5 EA |
658 | if (batch->num_cliprects < 0) |
659 | return -EINVAL; | |
660 | ||
661 | if (batch->num_cliprects) { | |
9a298b2a | 662 | cliprects = kcalloc(batch->num_cliprects, |
b14c5679 | 663 | sizeof(*cliprects), |
9a298b2a | 664 | GFP_KERNEL); |
201361a5 EA |
665 | if (cliprects == NULL) |
666 | return -ENOMEM; | |
667 | ||
668 | ret = copy_from_user(cliprects, batch->cliprects, | |
669 | batch->num_cliprects * | |
670 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
671 | if (ret != 0) { |
672 | ret = -EFAULT; | |
201361a5 | 673 | goto fail_free; |
9927a403 | 674 | } |
201361a5 | 675 | } |
1da177e4 | 676 | |
546b0974 | 677 | mutex_lock(&dev->struct_mutex); |
201361a5 | 678 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 679 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 680 | |
c99b058f | 681 | if (sarea_priv) |
0baf823a | 682 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
683 | |
684 | fail_free: | |
9a298b2a | 685 | kfree(cliprects); |
201361a5 | 686 | |
1da177e4 LT |
687 | return ret; |
688 | } | |
689 | ||
c153f45f EA |
690 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
691 | struct drm_file *file_priv) | |
1da177e4 | 692 | { |
4c8a4be9 | 693 | struct drm_i915_private *dev_priv = dev->dev_private; |
4d10cc0f DV |
694 | struct drm_i915_master_private *master_priv; |
695 | drm_i915_sarea_t *sarea_priv; | |
c153f45f | 696 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
697 | struct drm_clip_rect *cliprects = NULL; |
698 | void *batch_data; | |
1da177e4 LT |
699 | int ret; |
700 | ||
8a4c47f3 | 701 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 702 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 703 | |
cd9d4e9f DV |
704 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
705 | return -ENODEV; | |
706 | ||
4d10cc0f DV |
707 | master_priv = dev->primary->master->driver_priv; |
708 | sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv; | |
709 | ||
546b0974 | 710 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 711 | |
201361a5 EA |
712 | if (cmdbuf->num_cliprects < 0) |
713 | return -EINVAL; | |
714 | ||
9a298b2a | 715 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
716 | if (batch_data == NULL) |
717 | return -ENOMEM; | |
718 | ||
719 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
720 | if (ret != 0) { |
721 | ret = -EFAULT; | |
201361a5 | 722 | goto fail_batch_free; |
9927a403 | 723 | } |
201361a5 EA |
724 | |
725 | if (cmdbuf->num_cliprects) { | |
9a298b2a | 726 | cliprects = kcalloc(cmdbuf->num_cliprects, |
b14c5679 | 727 | sizeof(*cliprects), GFP_KERNEL); |
a40e8d31 OA |
728 | if (cliprects == NULL) { |
729 | ret = -ENOMEM; | |
201361a5 | 730 | goto fail_batch_free; |
a40e8d31 | 731 | } |
201361a5 EA |
732 | |
733 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
734 | cmdbuf->num_cliprects * | |
735 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
736 | if (ret != 0) { |
737 | ret = -EFAULT; | |
201361a5 | 738 | goto fail_clip_free; |
9927a403 | 739 | } |
1da177e4 LT |
740 | } |
741 | ||
546b0974 | 742 | mutex_lock(&dev->struct_mutex); |
201361a5 | 743 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 744 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
745 | if (ret) { |
746 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 747 | goto fail_clip_free; |
1da177e4 LT |
748 | } |
749 | ||
c99b058f | 750 | if (sarea_priv) |
0baf823a | 751 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 752 | |
201361a5 | 753 | fail_clip_free: |
9a298b2a | 754 | kfree(cliprects); |
355d7f37 | 755 | fail_batch_free: |
9a298b2a | 756 | kfree(batch_data); |
201361a5 EA |
757 | |
758 | return ret; | |
1da177e4 LT |
759 | } |
760 | ||
1a5036bf | 761 | static int i915_emit_irq(struct drm_device *dev) |
9488867a | 762 | { |
4c8a4be9 | 763 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
764 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
765 | ||
766 | i915_kernel_lost_context(dev); | |
767 | ||
768 | DRM_DEBUG_DRIVER("\n"); | |
769 | ||
231f42a4 DV |
770 | dev_priv->dri1.counter++; |
771 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
772 | dev_priv->dri1.counter = 1; | |
9488867a | 773 | if (master_priv->sarea_priv) |
231f42a4 | 774 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
9488867a DV |
775 | |
776 | if (BEGIN_LP_RING(4) == 0) { | |
777 | OUT_RING(MI_STORE_DWORD_INDEX); | |
778 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 779 | OUT_RING(dev_priv->dri1.counter); |
9488867a DV |
780 | OUT_RING(MI_USER_INTERRUPT); |
781 | ADVANCE_LP_RING(); | |
782 | } | |
783 | ||
231f42a4 | 784 | return dev_priv->dri1.counter; |
9488867a DV |
785 | } |
786 | ||
1a5036bf | 787 | static int i915_wait_irq(struct drm_device *dev, int irq_nr) |
9488867a | 788 | { |
4c8a4be9 | 789 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
790 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
791 | int ret = 0; | |
a4872ba6 | 792 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
9488867a DV |
793 | |
794 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, | |
795 | READ_BREADCRUMB(dev_priv)); | |
796 | ||
797 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { | |
798 | if (master_priv->sarea_priv) | |
799 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
800 | return 0; | |
801 | } | |
802 | ||
803 | if (master_priv->sarea_priv) | |
804 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
805 | ||
806 | if (ring->irq_get(ring)) { | |
bfd8303a | 807 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ, |
9488867a DV |
808 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
809 | ring->irq_put(ring); | |
810 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) | |
811 | ret = -EBUSY; | |
812 | ||
813 | if (ret == -EBUSY) { | |
814 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", | |
231f42a4 | 815 | READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter); |
9488867a DV |
816 | } |
817 | ||
818 | return ret; | |
819 | } | |
820 | ||
821 | /* Needs the lock as it touches the ring. | |
822 | */ | |
823 | static int i915_irq_emit(struct drm_device *dev, void *data, | |
824 | struct drm_file *file_priv) | |
825 | { | |
4c8a4be9 | 826 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
827 | drm_i915_irq_emit_t *emit = data; |
828 | int result; | |
829 | ||
830 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
831 | return -ENODEV; | |
832 | ||
ee1b1e5e | 833 | if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) { |
9488867a DV |
834 | DRM_ERROR("called with no initialization\n"); |
835 | return -EINVAL; | |
836 | } | |
837 | ||
838 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
839 | ||
840 | mutex_lock(&dev->struct_mutex); | |
841 | result = i915_emit_irq(dev); | |
842 | mutex_unlock(&dev->struct_mutex); | |
843 | ||
1d6ac185 | 844 | if (copy_to_user(emit->irq_seq, &result, sizeof(int))) { |
9488867a DV |
845 | DRM_ERROR("copy_to_user\n"); |
846 | return -EFAULT; | |
847 | } | |
848 | ||
849 | return 0; | |
850 | } | |
851 | ||
852 | /* Doesn't need the hardware lock. | |
853 | */ | |
854 | static int i915_irq_wait(struct drm_device *dev, void *data, | |
855 | struct drm_file *file_priv) | |
856 | { | |
4c8a4be9 | 857 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
858 | drm_i915_irq_wait_t *irqwait = data; |
859 | ||
860 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
861 | return -ENODEV; | |
862 | ||
863 | if (!dev_priv) { | |
864 | DRM_ERROR("called with no initialization\n"); | |
865 | return -EINVAL; | |
866 | } | |
867 | ||
868 | return i915_wait_irq(dev, irqwait->irq_seq); | |
869 | } | |
870 | ||
d1c1edbc DV |
871 | static int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
872 | struct drm_file *file_priv) | |
873 | { | |
4c8a4be9 | 874 | struct drm_i915_private *dev_priv = dev->dev_private; |
d1c1edbc DV |
875 | drm_i915_vblank_pipe_t *pipe = data; |
876 | ||
877 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
878 | return -ENODEV; | |
879 | ||
880 | if (!dev_priv) { | |
881 | DRM_ERROR("called with no initialization\n"); | |
882 | return -EINVAL; | |
883 | } | |
884 | ||
885 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
890 | /** | |
891 | * Schedule buffer swap at given vertical blank. | |
892 | */ | |
893 | static int i915_vblank_swap(struct drm_device *dev, void *data, | |
894 | struct drm_file *file_priv) | |
895 | { | |
896 | /* The delayed swap mechanism was fundamentally racy, and has been | |
897 | * removed. The model was that the client requested a delayed flip/swap | |
898 | * from the kernel, then waited for vblank before continuing to perform | |
899 | * rendering. The problem was that the kernel might wake the client | |
900 | * up before it dispatched the vblank swap (since the lock has to be | |
901 | * held while touching the ringbuffer), in which case the client would | |
902 | * clear and start the next frame before the swap occurred, and | |
903 | * flicker would occur in addition to likely missing the vblank. | |
904 | * | |
905 | * In the absence of this ioctl, userland falls back to a correct path | |
906 | * of waiting for a vblank, then dispatching the swap on its own. | |
907 | * Context switching to userland and back is plenty fast enough for | |
908 | * meeting the requirements of vblank swapping. | |
909 | */ | |
910 | return -EINVAL; | |
911 | } | |
912 | ||
c153f45f EA |
913 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
914 | struct drm_file *file_priv) | |
1da177e4 | 915 | { |
546b0974 EA |
916 | int ret; |
917 | ||
cd9d4e9f DV |
918 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
919 | return -ENODEV; | |
920 | ||
8a4c47f3 | 921 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 922 | |
546b0974 | 923 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 924 | |
546b0974 EA |
925 | mutex_lock(&dev->struct_mutex); |
926 | ret = i915_dispatch_flip(dev); | |
927 | mutex_unlock(&dev->struct_mutex); | |
928 | ||
929 | return ret; | |
1da177e4 LT |
930 | } |
931 | ||
c153f45f EA |
932 | static int i915_getparam(struct drm_device *dev, void *data, |
933 | struct drm_file *file_priv) | |
1da177e4 | 934 | { |
4c8a4be9 | 935 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 936 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
937 | int value; |
938 | ||
939 | if (!dev_priv) { | |
3e684eae | 940 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 941 | return -EINVAL; |
1da177e4 LT |
942 | } |
943 | ||
c153f45f | 944 | switch (param->param) { |
1da177e4 | 945 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 946 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
947 | break; |
948 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
8781342d | 949 | value = dev_priv->dri1.allow_batchbuffer ? 1 : 0; |
1da177e4 | 950 | break; |
0d6aa60b DA |
951 | case I915_PARAM_LAST_DISPATCH: |
952 | value = READ_BREADCRUMB(dev_priv); | |
953 | break; | |
ed4c9c4a | 954 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 955 | value = dev->pdev->device; |
ed4c9c4a | 956 | break; |
673a394b | 957 | case I915_PARAM_HAS_GEM: |
2e895b17 | 958 | value = 1; |
673a394b | 959 | break; |
0f973f27 JB |
960 | case I915_PARAM_NUM_FENCES_AVAIL: |
961 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
962 | break; | |
02e792fb DV |
963 | case I915_PARAM_HAS_OVERLAY: |
964 | value = dev_priv->overlay ? 1 : 0; | |
965 | break; | |
e9560f7c JB |
966 | case I915_PARAM_HAS_PAGEFLIPPING: |
967 | value = 1; | |
968 | break; | |
76446cac JB |
969 | case I915_PARAM_HAS_EXECBUF2: |
970 | /* depends on GEM */ | |
2e895b17 | 971 | value = 1; |
76446cac | 972 | break; |
e3a815fc | 973 | case I915_PARAM_HAS_BSD: |
edc912f5 | 974 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 975 | break; |
549f7365 | 976 | case I915_PARAM_HAS_BLT: |
edc912f5 | 977 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 978 | break; |
a1f2cc73 XH |
979 | case I915_PARAM_HAS_VEBOX: |
980 | value = intel_ring_initialized(&dev_priv->ring[VECS]); | |
981 | break; | |
a00b10c3 CW |
982 | case I915_PARAM_HAS_RELAXED_FENCING: |
983 | value = 1; | |
984 | break; | |
bbf0c6b3 DV |
985 | case I915_PARAM_HAS_COHERENT_RINGS: |
986 | value = 1; | |
987 | break; | |
72bfa19c CW |
988 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
989 | value = INTEL_INFO(dev)->gen >= 4; | |
990 | break; | |
271d81b8 CW |
991 | case I915_PARAM_HAS_RELAXED_DELTA: |
992 | value = 1; | |
993 | break; | |
ae662d31 EA |
994 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
995 | value = 1; | |
996 | break; | |
3d29b842 ED |
997 | case I915_PARAM_HAS_LLC: |
998 | value = HAS_LLC(dev); | |
999 | break; | |
651d794f CW |
1000 | case I915_PARAM_HAS_WT: |
1001 | value = HAS_WT(dev); | |
1002 | break; | |
777ee96f | 1003 | case I915_PARAM_HAS_ALIASING_PPGTT: |
896ab1a5 | 1004 | value = USES_PPGTT(dev); |
777ee96f | 1005 | break; |
172cf15d BW |
1006 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
1007 | value = 1; | |
1008 | break; | |
2fedbff9 CW |
1009 | case I915_PARAM_HAS_SEMAPHORES: |
1010 | value = i915_semaphore_is_enabled(dev); | |
1011 | break; | |
ec6f1bb9 DA |
1012 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
1013 | value = 1; | |
1014 | break; | |
d7d4eedd CW |
1015 | case I915_PARAM_HAS_SECURE_BATCHES: |
1016 | value = capable(CAP_SYS_ADMIN); | |
1017 | break; | |
b45305fc DV |
1018 | case I915_PARAM_HAS_PINNED_BATCHES: |
1019 | value = 1; | |
1020 | break; | |
ed5982e6 DV |
1021 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
1022 | value = 1; | |
1023 | break; | |
eef90ccb CW |
1024 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
1025 | value = 1; | |
1026 | break; | |
d728c8ef BV |
1027 | case I915_PARAM_CMD_PARSER_VERSION: |
1028 | value = i915_cmd_parser_get_version(); | |
1029 | break; | |
1da177e4 | 1030 | default: |
e29c32da | 1031 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 1032 | return -EINVAL; |
1da177e4 LT |
1033 | } |
1034 | ||
1d6ac185 DV |
1035 | if (copy_to_user(param->value, &value, sizeof(int))) { |
1036 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 1037 | return -EFAULT; |
1da177e4 LT |
1038 | } |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
c153f45f EA |
1043 | static int i915_setparam(struct drm_device *dev, void *data, |
1044 | struct drm_file *file_priv) | |
1da177e4 | 1045 | { |
4c8a4be9 | 1046 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 1047 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
1048 | |
1049 | if (!dev_priv) { | |
3e684eae | 1050 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1051 | return -EINVAL; |
1da177e4 LT |
1052 | } |
1053 | ||
c153f45f | 1054 | switch (param->param) { |
1da177e4 | 1055 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
1056 | break; |
1057 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
1da177e4 LT |
1058 | break; |
1059 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
8781342d | 1060 | dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0; |
1da177e4 | 1061 | break; |
0f973f27 JB |
1062 | case I915_SETPARAM_NUM_USED_FENCES: |
1063 | if (param->value > dev_priv->num_fence_regs || | |
1064 | param->value < 0) | |
1065 | return -EINVAL; | |
1066 | /* Userspace can use first N regs */ | |
1067 | dev_priv->fence_reg_start = param->value; | |
1068 | break; | |
1da177e4 | 1069 | default: |
8a4c47f3 | 1070 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 1071 | param->param); |
20caafa6 | 1072 | return -EINVAL; |
1da177e4 LT |
1073 | } |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
c153f45f EA |
1078 | static int i915_set_status_page(struct drm_device *dev, void *data, |
1079 | struct drm_file *file_priv) | |
dc7a9319 | 1080 | { |
4c8a4be9 | 1081 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 1082 | drm_i915_hws_addr_t *hws = data; |
a4872ba6 | 1083 | struct intel_engine_cs *ring; |
b39d50e5 | 1084 | |
cd9d4e9f DV |
1085 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1086 | return -ENODEV; | |
1087 | ||
b39d50e5 ZW |
1088 | if (!I915_NEED_GFX_HWS(dev)) |
1089 | return -EINVAL; | |
dc7a9319 WZ |
1090 | |
1091 | if (!dev_priv) { | |
3e684eae | 1092 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1093 | return -EINVAL; |
dc7a9319 | 1094 | } |
dc7a9319 | 1095 | |
79e53945 JB |
1096 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1097 | WARN(1, "tried to set status page when mode setting active\n"); | |
1098 | return 0; | |
1099 | } | |
1100 | ||
8a4c47f3 | 1101 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 1102 | |
4f1ba0f8 | 1103 | ring = LP_RING(dev_priv); |
8187a2b7 | 1104 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 1105 | |
dd2757f8 | 1106 | dev_priv->dri1.gfx_hws_cpu_addr = |
5d4545ae | 1107 | ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096); |
316d3884 | 1108 | if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) { |
dc7a9319 | 1109 | i915_dma_cleanup(dev); |
e20f9c64 | 1110 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
1111 | DRM_ERROR("can not ioremap virtual address for" |
1112 | " G33 hw status page\n"); | |
20caafa6 | 1113 | return -ENOMEM; |
dc7a9319 | 1114 | } |
316d3884 DV |
1115 | |
1116 | memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE); | |
8187a2b7 | 1117 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
dc7a9319 | 1118 | |
8a4c47f3 | 1119 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 1120 | ring->status_page.gfx_addr); |
8a4c47f3 | 1121 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 1122 | ring->status_page.page_addr); |
dc7a9319 WZ |
1123 | return 0; |
1124 | } | |
1125 | ||
ec2a4c3f DA |
1126 | static int i915_get_bridge_dev(struct drm_device *dev) |
1127 | { | |
1128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1129 | ||
0206e353 | 1130 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
1131 | if (!dev_priv->bridge_dev) { |
1132 | DRM_ERROR("bridge device not found\n"); | |
1133 | return -1; | |
1134 | } | |
1135 | return 0; | |
1136 | } | |
1137 | ||
c4804411 ZW |
1138 | #define MCHBAR_I915 0x44 |
1139 | #define MCHBAR_I965 0x48 | |
1140 | #define MCHBAR_SIZE (4*4096) | |
1141 | ||
1142 | #define DEVEN_REG 0x54 | |
1143 | #define DEVEN_MCHBAR_EN (1 << 28) | |
1144 | ||
1145 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
1146 | static int | |
1147 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
1148 | { | |
4c8a4be9 | 1149 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1150 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1151 | u32 temp_lo, temp_hi = 0; |
1152 | u64 mchbar_addr; | |
a25c25c2 | 1153 | int ret; |
c4804411 | 1154 | |
a6c45cf0 | 1155 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1156 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
1157 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
1158 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
1159 | ||
1160 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
1161 | #ifdef CONFIG_PNP | |
1162 | if (mchbar_addr && | |
a25c25c2 CW |
1163 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
1164 | return 0; | |
c4804411 ZW |
1165 | #endif |
1166 | ||
1167 | /* Get some space for it */ | |
a25c25c2 CW |
1168 | dev_priv->mch_res.name = "i915 MCHBAR"; |
1169 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
1170 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
1171 | &dev_priv->mch_res, | |
c4804411 ZW |
1172 | MCHBAR_SIZE, MCHBAR_SIZE, |
1173 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 1174 | 0, pcibios_align_resource, |
c4804411 ZW |
1175 | dev_priv->bridge_dev); |
1176 | if (ret) { | |
1177 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
1178 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 1179 | return ret; |
c4804411 ZW |
1180 | } |
1181 | ||
a6c45cf0 | 1182 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1183 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
1184 | upper_32_bits(dev_priv->mch_res.start)); | |
1185 | ||
1186 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
1187 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 1188 | return 0; |
c4804411 ZW |
1189 | } |
1190 | ||
1191 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
1192 | static void | |
1193 | intel_setup_mchbar(struct drm_device *dev) | |
1194 | { | |
4c8a4be9 | 1195 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1196 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1197 | u32 temp; |
1198 | bool enabled; | |
1199 | ||
11ea8b7d JB |
1200 | if (IS_VALLEYVIEW(dev)) |
1201 | return; | |
1202 | ||
c4804411 ZW |
1203 | dev_priv->mchbar_need_disable = false; |
1204 | ||
1205 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1206 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1207 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
1208 | } else { | |
1209 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1210 | enabled = temp & 1; | |
1211 | } | |
1212 | ||
1213 | /* If it's already enabled, don't have to do anything */ | |
1214 | if (enabled) | |
1215 | return; | |
1216 | ||
1217 | if (intel_alloc_mchbar_resource(dev)) | |
1218 | return; | |
1219 | ||
1220 | dev_priv->mchbar_need_disable = true; | |
1221 | ||
1222 | /* Space is allocated or reserved, so enable it. */ | |
1223 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1224 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
1225 | temp | DEVEN_MCHBAR_EN); | |
1226 | } else { | |
1227 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1228 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
1229 | } | |
1230 | } | |
1231 | ||
1232 | static void | |
1233 | intel_teardown_mchbar(struct drm_device *dev) | |
1234 | { | |
4c8a4be9 | 1235 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1236 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1237 | u32 temp; |
1238 | ||
1239 | if (dev_priv->mchbar_need_disable) { | |
1240 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1241 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1242 | temp &= ~DEVEN_MCHBAR_EN; | |
1243 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1244 | } else { | |
1245 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1246 | temp &= ~1; | |
1247 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1248 | } | |
1249 | } | |
1250 | ||
1251 | if (dev_priv->mch_res.start) | |
1252 | release_resource(&dev_priv->mch_res); | |
1253 | } | |
1254 | ||
28d52043 DA |
1255 | /* true = enable decode, false = disable decoder */ |
1256 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1257 | { | |
1258 | struct drm_device *dev = cookie; | |
1259 | ||
1260 | intel_modeset_vga_set_state(dev, state); | |
1261 | if (state) | |
1262 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1263 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1264 | else | |
1265 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1266 | } | |
1267 | ||
6a9ee8af DA |
1268 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1269 | { | |
1270 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1271 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1a5036bf | 1272 | |
6a9ee8af | 1273 | if (state == VGA_SWITCHEROO_ON) { |
a70491cc | 1274 | pr_info("switched on\n"); |
5bcf719b | 1275 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
1276 | /* i915 resume handler doesn't set to D0 */ |
1277 | pci_set_power_state(dev->pdev, PCI_D0); | |
1278 | i915_resume(dev); | |
5bcf719b | 1279 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 1280 | } else { |
a70491cc | 1281 | pr_err("switched off\n"); |
5bcf719b | 1282 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 1283 | i915_suspend(dev, pmm); |
5bcf719b | 1284 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1285 | } |
1286 | } | |
1287 | ||
1288 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1289 | { | |
1290 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 1291 | |
fc8fd40e DV |
1292 | /* |
1293 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1294 | * locking inversion with the driver load path. And the access here is | |
1295 | * completely racy anyway. So don't bother with locking for now. | |
1296 | */ | |
1297 | return dev->open_count == 0; | |
6a9ee8af DA |
1298 | } |
1299 | ||
26ec685f TI |
1300 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
1301 | .set_gpu_state = i915_switcheroo_set_state, | |
1302 | .reprobe = NULL, | |
1303 | .can_switch = i915_switcheroo_can_switch, | |
1304 | }; | |
1305 | ||
2c7111db CW |
1306 | static int i915_load_modeset_init(struct drm_device *dev) |
1307 | { | |
1308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1309 | int ret; | |
79e53945 | 1310 | |
6d139a87 | 1311 | ret = intel_parse_bios(dev); |
79e53945 JB |
1312 | if (ret) |
1313 | DRM_INFO("failed to find VBIOS tables\n"); | |
1314 | ||
934f992c CW |
1315 | /* If we have > 1 VGA cards, then we need to arbitrate access |
1316 | * to the common VGA resources. | |
1317 | * | |
1318 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
1319 | * then we do not take part in VGA arbitration and the | |
1320 | * vga_client_register() fails with -ENODEV. | |
1321 | */ | |
ebff5fa9 DA |
1322 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
1323 | if (ret && ret != -ENODEV) | |
1324 | goto out; | |
28d52043 | 1325 | |
723bfd70 JB |
1326 | intel_register_dsm_handler(); |
1327 | ||
0d69704a | 1328 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 1329 | if (ret) |
5a79395b | 1330 | goto cleanup_vga_client; |
6a9ee8af | 1331 | |
9797fbfb CW |
1332 | /* Initialise stolen first so that we may reserve preallocated |
1333 | * objects for the BIOS to KMS transition. | |
1334 | */ | |
1335 | ret = i915_gem_init_stolen(dev); | |
1336 | if (ret) | |
1337 | goto cleanup_vga_switcheroo; | |
1338 | ||
e13192f6 ID |
1339 | intel_power_domains_init_hw(dev_priv); |
1340 | ||
2aeb7d3a | 1341 | ret = intel_irq_install(dev_priv); |
52d7eced DV |
1342 | if (ret) |
1343 | goto cleanup_gem_stolen; | |
1344 | ||
1345 | /* Important: The output setup functions called by modeset_init need | |
1346 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
1347 | intel_modeset_init(dev); |
1348 | ||
1070a42b | 1349 | ret = i915_gem_init(dev); |
79e53945 | 1350 | if (ret) |
713028b3 | 1351 | goto cleanup_irq; |
2c7111db | 1352 | |
52d7eced | 1353 | intel_modeset_gem_init(dev); |
2c7111db | 1354 | |
79e53945 JB |
1355 | /* Always safe in the mode setting case. */ |
1356 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
ba0bf120 | 1357 | dev->vblank_disable_allowed = true; |
713028b3 | 1358 | if (INTEL_INFO(dev)->num_pipes == 0) |
e3c74757 | 1359 | return 0; |
79e53945 | 1360 | |
5a79395b CW |
1361 | ret = intel_fbdev_init(dev); |
1362 | if (ret) | |
52d7eced DV |
1363 | goto cleanup_gem; |
1364 | ||
20afbda2 | 1365 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
b963291c | 1366 | intel_hpd_init(dev_priv); |
20afbda2 DV |
1367 | |
1368 | /* | |
1369 | * Some ports require correctly set-up hpd registers for detection to | |
1370 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1371 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1372 | * irqs are fully enabled. Now we should scan for the initial config | |
1373 | * only once hotplug handling is enabled, but due to screwed-up locking | |
1374 | * around kms/fbdev init we can't protect the fdbev initial config | |
1375 | * scanning against hotplug events. Hence do this first and ignore the | |
1376 | * tiny window where we will loose hotplug notifactions. | |
1377 | */ | |
d1d70677 | 1378 | async_schedule(intel_fbdev_initial_config, dev_priv); |
20afbda2 | 1379 | |
eb1f8e4f | 1380 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 1381 | |
79e53945 JB |
1382 | return 0; |
1383 | ||
2c7111db CW |
1384 | cleanup_gem: |
1385 | mutex_lock(&dev->struct_mutex); | |
1386 | i915_gem_cleanup_ringbuffer(dev); | |
55d23285 | 1387 | i915_gem_context_fini(dev); |
2c7111db | 1388 | mutex_unlock(&dev->struct_mutex); |
713028b3 | 1389 | cleanup_irq: |
52d7eced | 1390 | drm_irq_uninstall(dev); |
9797fbfb CW |
1391 | cleanup_gem_stolen: |
1392 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
1393 | cleanup_vga_switcheroo: |
1394 | vga_switcheroo_unregister_client(dev->pdev); | |
1395 | cleanup_vga_client: | |
1396 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
1397 | out: |
1398 | return ret; | |
1399 | } | |
1400 | ||
7c1c2871 DA |
1401 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1402 | { | |
1403 | struct drm_i915_master_private *master_priv; | |
1404 | ||
9a298b2a | 1405 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1406 | if (!master_priv) |
1407 | return -ENOMEM; | |
1408 | ||
1409 | master->driver_priv = master_priv; | |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1414 | { | |
1415 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1416 | ||
1417 | if (!master_priv) | |
1418 | return; | |
1419 | ||
9a298b2a | 1420 | kfree(master_priv); |
7c1c2871 DA |
1421 | |
1422 | master->driver_priv = NULL; | |
1423 | } | |
1424 | ||
243eaf38 | 1425 | #if IS_ENABLED(CONFIG_FB) |
f96de58f | 1426 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
e188719a DV |
1427 | { |
1428 | struct apertures_struct *ap; | |
1429 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
1430 | bool primary; | |
f96de58f | 1431 | int ret; |
e188719a DV |
1432 | |
1433 | ap = alloc_apertures(1); | |
1434 | if (!ap) | |
f96de58f | 1435 | return -ENOMEM; |
e188719a | 1436 | |
dabb7a91 | 1437 | ap->ranges[0].base = dev_priv->gtt.mappable_base; |
f64e2922 | 1438 | ap->ranges[0].size = dev_priv->gtt.mappable_end; |
93d18799 | 1439 | |
e188719a DV |
1440 | primary = |
1441 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
1442 | ||
f96de58f | 1443 | ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
e188719a DV |
1444 | |
1445 | kfree(ap); | |
f96de58f CW |
1446 | |
1447 | return ret; | |
e188719a | 1448 | } |
4520f53a | 1449 | #else |
f96de58f | 1450 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
4520f53a | 1451 | { |
f96de58f | 1452 | return 0; |
4520f53a DV |
1453 | } |
1454 | #endif | |
e188719a | 1455 | |
a4de0526 DV |
1456 | #if !defined(CONFIG_VGA_CONSOLE) |
1457 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
1458 | { | |
1459 | return 0; | |
1460 | } | |
1461 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
1462 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
1463 | { | |
1464 | return -ENODEV; | |
1465 | } | |
1466 | #else | |
1467 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
1468 | { | |
1bb9e632 | 1469 | int ret = 0; |
a4de0526 DV |
1470 | |
1471 | DRM_INFO("Replacing VGA console driver\n"); | |
1472 | ||
1473 | console_lock(); | |
1bb9e632 DV |
1474 | if (con_is_bound(&vga_con)) |
1475 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
a4de0526 DV |
1476 | if (ret == 0) { |
1477 | ret = do_unregister_con_driver(&vga_con); | |
1478 | ||
1479 | /* Ignore "already unregistered". */ | |
1480 | if (ret == -ENODEV) | |
1481 | ret = 0; | |
1482 | } | |
1483 | console_unlock(); | |
1484 | ||
1485 | return ret; | |
1486 | } | |
1487 | #endif | |
1488 | ||
c96ea64e DV |
1489 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
1490 | { | |
5c969aa7 | 1491 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 1492 | |
e2a5800a DL |
1493 | #define PRINT_S(name) "%s" |
1494 | #define SEP_EMPTY | |
79fc46df DL |
1495 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
1496 | #define SEP_COMMA , | |
19c656a1 | 1497 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" |
e2a5800a | 1498 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
1499 | info->gen, |
1500 | dev_priv->dev->pdev->device, | |
19c656a1 | 1501 | dev_priv->dev->pdev->revision, |
79fc46df | 1502 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
1503 | #undef PRINT_S |
1504 | #undef SEP_EMPTY | |
79fc46df DL |
1505 | #undef PRINT_FLAG |
1506 | #undef SEP_COMMA | |
c96ea64e DV |
1507 | } |
1508 | ||
22d3fd46 DL |
1509 | /* |
1510 | * Determine various intel_device_info fields at runtime. | |
1511 | * | |
1512 | * Use it when either: | |
1513 | * - it's judged too laborious to fill n static structures with the limit | |
1514 | * when a simple if statement does the job, | |
1515 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
1516 | * |
1517 | * This function needs to be called: | |
1518 | * - after the MMIO has been setup as we are reading registers, | |
1519 | * - after the PCH has been detected, | |
1520 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
1521 | */ |
1522 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
1523 | { | |
658ac4c6 | 1524 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 1525 | struct intel_device_info *info; |
d615a166 | 1526 | enum pipe pipe; |
22d3fd46 | 1527 | |
658ac4c6 | 1528 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 1529 | |
1fc8ac3e | 1530 | if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9) |
055e393f | 1531 | for_each_pipe(dev_priv, pipe) |
d615a166 DL |
1532 | info->num_sprites[pipe] = 2; |
1533 | else | |
055e393f | 1534 | for_each_pipe(dev_priv, pipe) |
d615a166 | 1535 | info->num_sprites[pipe] = 1; |
658ac4c6 | 1536 | |
a0bae57f DL |
1537 | if (i915.disable_display) { |
1538 | DRM_INFO("Display disabled (module parameter)\n"); | |
1539 | info->num_pipes = 0; | |
1540 | } else if (info->num_pipes > 0 && | |
1541 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && | |
1542 | !IS_VALLEYVIEW(dev)) { | |
658ac4c6 DL |
1543 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
1544 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
1545 | ||
1546 | /* | |
1547 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
1548 | * is fused off. Unfortunately it seems that, at least in | |
1549 | * certain cases, fused off display means that PCH display | |
1550 | * reads don't land anywhere. In that case, we read 0s. | |
1551 | * | |
1552 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
1553 | * should be set when taking over after the firmware. | |
1554 | */ | |
1555 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
1556 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
1557 | (dev_priv->pch_type == PCH_CPT && | |
1558 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
1559 | DRM_INFO("Display fused off, disabling\n"); | |
1560 | info->num_pipes = 0; | |
1561 | } | |
1562 | } | |
22d3fd46 DL |
1563 | } |
1564 | ||
79e53945 JB |
1565 | /** |
1566 | * i915_driver_load - setup chip and create an initial config | |
1567 | * @dev: DRM device | |
1568 | * @flags: startup flags | |
1569 | * | |
1570 | * The driver load routine has to do several things: | |
1571 | * - drive output discovery via intel_modeset_init() | |
1572 | * - initialize the memory manager | |
1573 | * - allocate initial config memory | |
1574 | * - setup the DRM framebuffer with the allocated memory | |
1575 | */ | |
84b1fd10 | 1576 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1577 | { |
ea059a1e | 1578 | struct drm_i915_private *dev_priv; |
5c969aa7 | 1579 | struct intel_device_info *info, *device_info; |
934d6086 | 1580 | int ret = 0, mmio_bar, mmio_size; |
9021f284 | 1581 | uint32_t aperture_size; |
fe669bf8 | 1582 | |
26394d92 DV |
1583 | info = (struct intel_device_info *) flags; |
1584 | ||
1585 | /* Refuse to load on gen6+ without kms enabled. */ | |
e147accb JN |
1586 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) { |
1587 | DRM_INFO("Your hardware requires kernel modesetting (KMS)\n"); | |
1588 | DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n"); | |
26394d92 | 1589 | return -ENODEV; |
e147accb | 1590 | } |
26394d92 | 1591 | |
24986ee0 DV |
1592 | /* UMS needs agp support. */ |
1593 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp) | |
1594 | return -EINVAL; | |
1595 | ||
b14c5679 | 1596 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
ba8bbcf6 JB |
1597 | if (dev_priv == NULL) |
1598 | return -ENOMEM; | |
1599 | ||
755f68f4 | 1600 | dev->dev_private = dev_priv; |
673a394b | 1601 | dev_priv->dev = dev; |
5c969aa7 | 1602 | |
87f1f465 | 1603 | /* Setup the write-once "constant" device info */ |
5c969aa7 | 1604 | device_info = (struct intel_device_info *)&dev_priv->info; |
87f1f465 CW |
1605 | memcpy(device_info, info, sizeof(dev_priv->info)); |
1606 | device_info->device_id = dev->pdev->device; | |
ba8bbcf6 | 1607 | |
7dcd2677 KK |
1608 | spin_lock_init(&dev_priv->irq_lock); |
1609 | spin_lock_init(&dev_priv->gpu_error.lock); | |
07f11d49 | 1610 | mutex_init(&dev_priv->backlight_lock); |
907b28c5 | 1611 | spin_lock_init(&dev_priv->uncore.lock); |
c20e8355 | 1612 | spin_lock_init(&dev_priv->mm.object_stat_lock); |
84c33a64 | 1613 | spin_lock_init(&dev_priv->mmio_flip_lock); |
7dcd2677 | 1614 | mutex_init(&dev_priv->dpio_lock); |
7dcd2677 KK |
1615 | mutex_init(&dev_priv->modeset_restore_lock); |
1616 | ||
f742a552 | 1617 | intel_pm_setup(dev); |
c67a470b | 1618 | |
07144428 DL |
1619 | intel_display_crc_init(dev); |
1620 | ||
c96ea64e DV |
1621 | i915_dump_device_info(dev_priv); |
1622 | ||
ed1c9e2c PZ |
1623 | /* Not all pre-production machines fall into this category, only the |
1624 | * very first ones. Almost everything should work, except for maybe | |
1625 | * suspend/resume. And we don't implement workarounds that affect only | |
1626 | * pre-production machines. */ | |
1627 | if (IS_HSW_EARLY_SDV(dev)) | |
1628 | DRM_INFO("This is an early pre-production Haswell machine. " | |
1629 | "It may not be fully functional.\n"); | |
1630 | ||
ec2a4c3f DA |
1631 | if (i915_get_bridge_dev(dev)) { |
1632 | ret = -EIO; | |
1633 | goto free_priv; | |
1634 | } | |
1635 | ||
1e1bd0fd BW |
1636 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
1637 | /* Before gen4, the registers and the GTT are behind different BARs. | |
1638 | * However, from gen4 onwards, the registers and the GTT are shared | |
1639 | * in the same BAR, so we want to restrict this ioremap from | |
1640 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1641 | * the register BAR remains the same size for all the earlier | |
1642 | * generations up to Ironlake. | |
1643 | */ | |
1644 | if (info->gen < 5) | |
1645 | mmio_size = 512*1024; | |
1646 | else | |
1647 | mmio_size = 2*1024*1024; | |
1648 | ||
1649 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
1650 | if (!dev_priv->regs) { | |
1651 | DRM_ERROR("failed to map registers\n"); | |
1652 | ret = -EIO; | |
1653 | goto put_bridge; | |
1654 | } | |
1655 | ||
c3d685a7 BW |
1656 | /* This must be called before any calls to HAS_PCH_* */ |
1657 | intel_detect_pch(dev); | |
1658 | ||
1659 | intel_uncore_init(dev); | |
1660 | ||
e76e9aeb BW |
1661 | ret = i915_gem_gtt_init(dev); |
1662 | if (ret) | |
cbb47d17 | 1663 | goto out_regs; |
e188719a | 1664 | |
a4de0526 DV |
1665 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1666 | ret = i915_kick_out_vgacon(dev_priv); | |
1667 | if (ret) { | |
1668 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
1669 | goto out_gtt; | |
1670 | } | |
1671 | ||
f96de58f CW |
1672 | ret = i915_kick_out_firmware_fb(dev_priv); |
1673 | if (ret) { | |
1674 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
1675 | goto out_gtt; | |
1676 | } | |
a4de0526 | 1677 | } |
e188719a | 1678 | |
466e69b8 DA |
1679 | pci_set_master(dev->pdev); |
1680 | ||
9f82d238 DV |
1681 | /* overlay on gen2 is broken and can't address above 1G */ |
1682 | if (IS_GEN2(dev)) | |
1683 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1684 | ||
6927faf3 JN |
1685 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1686 | * using 32bit addressing, overwriting memory if HWS is located | |
1687 | * above 4GB. | |
1688 | * | |
1689 | * The documentation also mentions an issue with undefined | |
1690 | * behaviour if any general state is accessed within a page above 4GB, | |
1691 | * which also needs to be handled carefully. | |
1692 | */ | |
1693 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1694 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1695 | ||
93d18799 | 1696 | aperture_size = dev_priv->gtt.mappable_end; |
71e9339c | 1697 | |
5d4545ae BW |
1698 | dev_priv->gtt.mappable = |
1699 | io_mapping_create_wc(dev_priv->gtt.mappable_base, | |
dd2757f8 | 1700 | aperture_size); |
5d4545ae | 1701 | if (dev_priv->gtt.mappable == NULL) { |
6644107d | 1702 | ret = -EIO; |
cbb47d17 | 1703 | goto out_gtt; |
6644107d VP |
1704 | } |
1705 | ||
911bdf0a BW |
1706 | dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base, |
1707 | aperture_size); | |
19966754 | 1708 | |
e642abbf CW |
1709 | /* The i915 workqueue is primarily used for batched retirement of |
1710 | * requests (and thus managing bo) once the task has been completed | |
1711 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
1712 | * need high-priority retirement, such as waiting for an explicit | |
1713 | * bo. | |
1714 | * | |
1715 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 1716 | * idle-timers and recording error state. |
e642abbf CW |
1717 | * |
1718 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1719 | * so there is no point in running more than one instance of the | |
53621860 | 1720 | * workqueue at any time. Use an ordered one. |
e642abbf | 1721 | */ |
53621860 | 1722 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
9c9fe1f8 EA |
1723 | if (dev_priv->wq == NULL) { |
1724 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1725 | ret = -ENOMEM; | |
a7b85d2a | 1726 | goto out_mtrrfree; |
9c9fe1f8 EA |
1727 | } |
1728 | ||
0e32b39c DA |
1729 | dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0); |
1730 | if (dev_priv->dp_wq == NULL) { | |
1731 | DRM_ERROR("Failed to create our dp workqueue.\n"); | |
1732 | ret = -ENOMEM; | |
1733 | goto out_freewq; | |
1734 | } | |
1735 | ||
b963291c | 1736 | intel_irq_init(dev_priv); |
78511f2a | 1737 | intel_uncore_sanitize(dev); |
9880b7a5 | 1738 | |
c4804411 ZW |
1739 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1740 | intel_setup_mchbar(dev); | |
f899fc64 | 1741 | intel_setup_gmbus(dev); |
44834a67 | 1742 | intel_opregion_setup(dev); |
c4804411 | 1743 | |
6d139a87 BF |
1744 | intel_setup_bios(dev); |
1745 | ||
673a394b EA |
1746 | i915_gem_load(dev); |
1747 | ||
ed4cb414 EA |
1748 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1749 | * integrated graphics even though the support isn't actually there | |
1750 | * according to the published specs. It doesn't appear to function | |
1751 | * correctly in testing on 945G. | |
1752 | * This may be a side effect of MSI having been made available for PEG | |
1753 | * and the registers being closely associated. | |
d1ed629f KP |
1754 | * |
1755 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1756 | * be lost or delayed, but we use them anyways to avoid |
1757 | * stuck interrupts on some machines. | |
ed4cb414 | 1758 | */ |
b60678a7 | 1759 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1760 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1761 | |
22d3fd46 | 1762 | intel_device_info_runtime_init(dev); |
7f1f3851 | 1763 | |
e3c74757 BW |
1764 | if (INTEL_INFO(dev)->num_pipes) { |
1765 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); | |
1766 | if (ret) | |
1767 | goto out_gem_unload; | |
1768 | } | |
52440211 | 1769 | |
da7e29bd | 1770 | intel_power_domains_init(dev_priv); |
a38911a3 | 1771 | |
79e53945 | 1772 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 1773 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
1774 | if (ret < 0) { |
1775 | DRM_ERROR("failed to init modeset\n"); | |
cbb47d17 | 1776 | goto out_power_well; |
79e53945 | 1777 | } |
db1b76ca DV |
1778 | } else { |
1779 | /* Start out suspended in ums mode. */ | |
1780 | dev_priv->ums.mm_suspended = 1; | |
79e53945 JB |
1781 | } |
1782 | ||
0136db58 BW |
1783 | i915_setup_sysfs(dev); |
1784 | ||
e3c74757 BW |
1785 | if (INTEL_INFO(dev)->num_pipes) { |
1786 | /* Must be done after probing outputs */ | |
1787 | intel_opregion_init(dev); | |
8e5c2b77 | 1788 | acpi_video_register(); |
e3c74757 | 1789 | } |
74a365b3 | 1790 | |
eb48eb00 DV |
1791 | if (IS_GEN5(dev)) |
1792 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 1793 | |
f458ebbc | 1794 | intel_runtime_pm_enable(dev_priv); |
8a187455 | 1795 | |
79e53945 JB |
1796 | return 0; |
1797 | ||
cbb47d17 | 1798 | out_power_well: |
f458ebbc | 1799 | intel_power_domains_fini(dev_priv); |
cbb47d17 | 1800 | drm_vblank_cleanup(dev); |
56e2ea34 | 1801 | out_gem_unload: |
4bdc7293 ID |
1802 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1803 | unregister_shrinker(&dev_priv->mm.shrinker); | |
a7b85d2a | 1804 | |
56e2ea34 CW |
1805 | if (dev->pdev->msi_enabled) |
1806 | pci_disable_msi(dev->pdev); | |
1807 | ||
1808 | intel_teardown_gmbus(dev); | |
1809 | intel_teardown_mchbar(dev); | |
22accca0 | 1810 | pm_qos_remove_request(&dev_priv->pm_qos); |
0e32b39c DA |
1811 | destroy_workqueue(dev_priv->dp_wq); |
1812 | out_freewq: | |
9c9fe1f8 | 1813 | destroy_workqueue(dev_priv->wq); |
a7b85d2a | 1814 | out_mtrrfree: |
911bdf0a | 1815 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
5d4545ae | 1816 | io_mapping_free(dev_priv->gtt.mappable); |
cbb47d17 | 1817 | out_gtt: |
90d0a0e8 | 1818 | i915_global_gtt_cleanup(dev); |
cbb47d17 | 1819 | out_regs: |
c3d685a7 | 1820 | intel_uncore_fini(dev); |
6dda569f | 1821 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
1822 | put_bridge: |
1823 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1824 | free_priv: |
cbb47d17 CW |
1825 | if (dev_priv->slab) |
1826 | kmem_cache_destroy(dev_priv->slab); | |
9a298b2a | 1827 | kfree(dev_priv); |
ba8bbcf6 JB |
1828 | return ret; |
1829 | } | |
1830 | ||
1831 | int i915_driver_unload(struct drm_device *dev) | |
1832 | { | |
1833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1834 | int ret; |
ba8bbcf6 | 1835 | |
ce58c32b CW |
1836 | ret = i915_gem_suspend(dev); |
1837 | if (ret) { | |
1838 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
1839 | return ret; | |
1840 | } | |
1841 | ||
41373cd5 | 1842 | intel_power_domains_fini(dev_priv); |
8a187455 | 1843 | |
eb48eb00 | 1844 | intel_gpu_ips_teardown(); |
7648fa99 | 1845 | |
0136db58 BW |
1846 | i915_teardown_sysfs(dev); |
1847 | ||
4bdc7293 ID |
1848 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1849 | unregister_shrinker(&dev_priv->mm.shrinker); | |
17250b71 | 1850 | |
5d4545ae | 1851 | io_mapping_free(dev_priv->gtt.mappable); |
911bdf0a | 1852 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
ab657db1 | 1853 | |
44834a67 CW |
1854 | acpi_video_unregister(); |
1855 | ||
79e53945 | 1856 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
7b4f3990 | 1857 | intel_fbdev_fini(dev); |
3d8620cc JB |
1858 | intel_modeset_cleanup(dev); |
1859 | ||
6363ee6f ZY |
1860 | /* |
1861 | * free the memory space allocated for the child device | |
1862 | * config parsed from VBT | |
1863 | */ | |
41aa3448 RV |
1864 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
1865 | kfree(dev_priv->vbt.child_dev); | |
1866 | dev_priv->vbt.child_dev = NULL; | |
1867 | dev_priv->vbt.child_dev_num = 0; | |
6363ee6f | 1868 | } |
6c0d9350 | 1869 | |
6a9ee8af | 1870 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 1871 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
1872 | } |
1873 | ||
a8b4899e | 1874 | /* Free error state after interrupts are fully disabled. */ |
99584db3 DV |
1875 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
1876 | cancel_work_sync(&dev_priv->gpu_error.work); | |
a8b4899e | 1877 | i915_destroy_error_state(dev); |
bc0c7f14 | 1878 | |
ed4cb414 EA |
1879 | if (dev->pdev->msi_enabled) |
1880 | pci_disable_msi(dev->pdev); | |
1881 | ||
44834a67 | 1882 | intel_opregion_fini(dev); |
8ee1c3db | 1883 | |
79e53945 | 1884 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
1885 | /* Flush any outstanding unpin_work. */ |
1886 | flush_workqueue(dev_priv->wq); | |
1887 | ||
79e53945 JB |
1888 | mutex_lock(&dev->struct_mutex); |
1889 | i915_gem_cleanup_ringbuffer(dev); | |
55a66628 | 1890 | i915_gem_context_fini(dev); |
79e53945 | 1891 | mutex_unlock(&dev->struct_mutex); |
9797fbfb | 1892 | i915_gem_cleanup_stolen(dev); |
c2873e96 KP |
1893 | |
1894 | if (!I915_NEED_GFX_HWS(dev)) | |
1895 | i915_free_hws(dev); | |
79e53945 JB |
1896 | } |
1897 | ||
cbb47d17 CW |
1898 | drm_vblank_cleanup(dev); |
1899 | ||
f899fc64 | 1900 | intel_teardown_gmbus(dev); |
c4804411 ZW |
1901 | intel_teardown_mchbar(dev); |
1902 | ||
0e32b39c | 1903 | destroy_workqueue(dev_priv->dp_wq); |
bc0c7f14 | 1904 | destroy_workqueue(dev_priv->wq); |
9ee32fea | 1905 | pm_qos_remove_request(&dev_priv->pm_qos); |
bc0c7f14 | 1906 | |
90d0a0e8 | 1907 | i915_global_gtt_cleanup(dev); |
6640aab6 | 1908 | |
aec347ab CW |
1909 | intel_uncore_fini(dev); |
1910 | if (dev_priv->regs != NULL) | |
1911 | pci_iounmap(dev->pdev, dev_priv->regs); | |
1912 | ||
42dcedd4 CW |
1913 | if (dev_priv->slab) |
1914 | kmem_cache_destroy(dev_priv->slab); | |
bc0c7f14 | 1915 | |
ec2a4c3f | 1916 | pci_dev_put(dev_priv->bridge_dev); |
2206e6a1 | 1917 | kfree(dev_priv); |
ba8bbcf6 | 1918 | |
22eae947 DA |
1919 | return 0; |
1920 | } | |
1921 | ||
f787a5f5 | 1922 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1923 | { |
b29c19b6 | 1924 | int ret; |
673a394b | 1925 | |
b29c19b6 CW |
1926 | ret = i915_gem_open(dev, file); |
1927 | if (ret) | |
1928 | return ret; | |
254f965c | 1929 | |
673a394b EA |
1930 | return 0; |
1931 | } | |
1932 | ||
79e53945 JB |
1933 | /** |
1934 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1935 | * @dev: DRM device | |
1936 | * | |
1937 | * Take care of cleaning up after all DRM clients have exited. In the | |
1938 | * mode setting case, we want to restore the kernel's initial mode (just | |
1939 | * in case the last client left us in a bad state). | |
1940 | * | |
9021f284 | 1941 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1942 | * and DMA structures, since the kernel won't be using them, and clea |
1943 | * up any GEM state. | |
1944 | */ | |
1a5036bf | 1945 | void i915_driver_lastclose(struct drm_device *dev) |
1da177e4 | 1946 | { |
4c8a4be9 | 1947 | struct drm_i915_private *dev_priv = dev->dev_private; |
ba8bbcf6 | 1948 | |
e8aeaee7 DV |
1949 | /* On gen6+ we refuse to init without kms enabled, but then the drm core |
1950 | * goes right around and calls lastclose. Check for this and don't clean | |
1951 | * up anything. */ | |
1952 | if (!dev_priv) | |
1953 | return; | |
1954 | ||
1955 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
0632fef6 | 1956 | intel_fbdev_restore_mode(dev); |
6a9ee8af | 1957 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 1958 | return; |
79e53945 | 1959 | } |
144a75fa | 1960 | |
673a394b EA |
1961 | i915_gem_lastclose(dev); |
1962 | ||
b5e89ed5 | 1963 | i915_dma_cleanup(dev); |
1da177e4 LT |
1964 | } |
1965 | ||
2885f6ac | 1966 | void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
1da177e4 | 1967 | { |
0d1430a3 | 1968 | mutex_lock(&dev->struct_mutex); |
2885f6ac JH |
1969 | i915_gem_context_close(dev, file); |
1970 | i915_gem_release(dev, file); | |
0d1430a3 | 1971 | mutex_unlock(&dev->struct_mutex); |
e2fcdaa9 VS |
1972 | |
1973 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
1974 | intel_modeset_preclose(dev, file); | |
1da177e4 LT |
1975 | } |
1976 | ||
f787a5f5 | 1977 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1978 | { |
f787a5f5 | 1979 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1980 | |
a8ebba75 ZY |
1981 | if (file_priv && file_priv->bsd_ring) |
1982 | file_priv->bsd_ring = NULL; | |
f787a5f5 | 1983 | kfree(file_priv); |
673a394b EA |
1984 | } |
1985 | ||
baa70943 | 1986 | const struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
1987 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1988 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1989 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1990 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1991 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1992 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
10ba5012 | 1993 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
1b2f1489 | 1994 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1995 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1996 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1997 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1b2f1489 | 1998 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
b2c606fe | 1999 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 2000 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1b2f1489 DA |
2001 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
2002 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
2003 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2004 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2005 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
10ba5012 | 2006 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
2007 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
2008 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
2009 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
2010 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2011 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2012 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 DA |
2013 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
2014 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
2015 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
2016 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2017 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2018 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2019 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2020 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2021 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2022 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2023 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2024 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 | 2025 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
10ba5012 | 2026 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
2027 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
2028 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
2029 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
2030 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
10ba5012 KH |
2031 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
2032 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2033 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2034 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
b6359918 | 2035 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
5cc9ed4b | 2036 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
c94f7029 DA |
2037 | }; |
2038 | ||
f95aeb17 | 2039 | int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); |
cda17380 | 2040 | |
9021f284 DV |
2041 | /* |
2042 | * This is really ugly: Because old userspace abused the linux agp interface to | |
2043 | * manage the gtt, we need to claim that all intel devices are agp. For | |
2044 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 2045 | */ |
1a5036bf | 2046 | int i915_driver_device_is_agp(struct drm_device *dev) |
cda17380 DA |
2047 | { |
2048 | return 1; | |
2049 | } |