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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
dcdb1674 | 38 | #include <linux/pci.h> |
a4de0526 DV |
39 | #include <linux/console.h> |
40 | #include <linux/vt.h> | |
28d52043 | 41 | #include <linux/vgaarb.h> |
c4804411 ZW |
42 | #include <linux/acpi.h> |
43 | #include <linux/pnp.h> | |
6a9ee8af | 44 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
44834a67 | 46 | #include <acpi/video.h> |
8a187455 PZ |
47 | #include <linux/pm.h> |
48 | #include <linux/pm_runtime.h> | |
4bdc7293 | 49 | #include <linux/oom.h> |
1da177e4 | 50 | |
09422b2e DV |
51 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
52 | ||
53 | #define BEGIN_LP_RING(n) \ | |
54 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
55 | ||
56 | #define OUT_RING(x) \ | |
57 | intel_ring_emit(LP_RING(dev_priv), x) | |
58 | ||
59 | #define ADVANCE_LP_RING() \ | |
09246732 | 60 | __intel_ring_advance(LP_RING(dev_priv)) |
09422b2e DV |
61 | |
62 | /** | |
63 | * Lock test for when it's just for synchronization of ring access. | |
64 | * | |
65 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
66 | * has access to the ring. | |
67 | */ | |
68 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ | |
ee1b1e5e | 69 | if (LP_RING(dev->dev_private)->buffer->obj == NULL) \ |
09422b2e DV |
70 | LOCK_TEST_WITH_RETURN(dev, file); \ |
71 | } while (0) | |
72 | ||
316d3884 DV |
73 | static inline u32 |
74 | intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) | |
75 | { | |
76 | if (I915_NEED_GFX_HWS(dev_priv->dev)) | |
77 | return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); | |
78 | else | |
79 | return intel_read_status_page(LP_RING(dev_priv), reg); | |
80 | } | |
81 | ||
82 | #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) | |
09422b2e DV |
83 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
84 | #define I915_BREADCRUMB_INDEX 0x21 | |
85 | ||
d05c617e DV |
86 | void i915_update_dri1_breadcrumb(struct drm_device *dev) |
87 | { | |
4c8a4be9 | 88 | struct drm_i915_private *dev_priv = dev->dev_private; |
d05c617e DV |
89 | struct drm_i915_master_private *master_priv; |
90 | ||
6c719fac DV |
91 | /* |
92 | * The dri breadcrumb update races against the drm master disappearing. | |
93 | * Instead of trying to fix this (this is by far not the only ums issue) | |
94 | * just don't do the update in kms mode. | |
95 | */ | |
96 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
97 | return; | |
98 | ||
d05c617e DV |
99 | if (dev->primary->master) { |
100 | master_priv = dev->primary->master->driver_priv; | |
101 | if (master_priv->sarea_priv) | |
102 | master_priv->sarea_priv->last_dispatch = | |
103 | READ_BREADCRUMB(dev_priv); | |
104 | } | |
105 | } | |
106 | ||
4cbf74cc CW |
107 | static void i915_write_hws_pga(struct drm_device *dev) |
108 | { | |
4c8a4be9 | 109 | struct drm_i915_private *dev_priv = dev->dev_private; |
4cbf74cc CW |
110 | u32 addr; |
111 | ||
112 | addr = dev_priv->status_page_dmah->busaddr; | |
113 | if (INTEL_INFO(dev)->gen >= 4) | |
114 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
115 | I915_WRITE(HWS_PGA, addr); | |
116 | } | |
117 | ||
398c9cb2 KP |
118 | /** |
119 | * Frees the hardware status page, whether it's a physical address or a virtual | |
120 | * address set up by the X Server. | |
121 | */ | |
3043c60c | 122 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 | 123 | { |
4c8a4be9 | 124 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 125 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
1ec14ad3 | 126 | |
398c9cb2 KP |
127 | if (dev_priv->status_page_dmah) { |
128 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
129 | dev_priv->status_page_dmah = NULL; | |
130 | } | |
131 | ||
1ec14ad3 CW |
132 | if (ring->status_page.gfx_addr) { |
133 | ring->status_page.gfx_addr = 0; | |
316d3884 | 134 | iounmap(dev_priv->dri1.gfx_hws_cpu_addr); |
398c9cb2 KP |
135 | } |
136 | ||
137 | /* Need to rewrite hardware status page */ | |
138 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
139 | } | |
140 | ||
1a5036bf | 141 | void i915_kernel_lost_context(struct drm_device *dev) |
1da177e4 | 142 | { |
4c8a4be9 | 143 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 144 | struct drm_i915_master_private *master_priv; |
a4872ba6 | 145 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
93b0a4e0 | 146 | struct intel_ringbuffer *ringbuf = ring->buffer; |
1da177e4 | 147 | |
79e53945 JB |
148 | /* |
149 | * We should never lose context on the ring with modesetting | |
150 | * as we don't expose it to userspace | |
151 | */ | |
152 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
153 | return; | |
154 | ||
93b0a4e0 OM |
155 | ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
156 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
157 | ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE); | |
158 | if (ringbuf->space < 0) | |
159 | ringbuf->space += ringbuf->size; | |
1da177e4 | 160 | |
7c1c2871 DA |
161 | if (!dev->primary->master) |
162 | return; | |
163 | ||
164 | master_priv = dev->primary->master->driver_priv; | |
93b0a4e0 | 165 | if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv) |
7c1c2871 | 166 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; |
1da177e4 LT |
167 | } |
168 | ||
1a5036bf | 169 | static int i915_dma_cleanup(struct drm_device *dev) |
1da177e4 | 170 | { |
4c8a4be9 | 171 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
172 | int i; |
173 | ||
1da177e4 LT |
174 | /* Make sure interrupts are disabled here because the uninstall ioctl |
175 | * may not have been called from userspace and after dev_private | |
176 | * is freed, it's too late. | |
177 | */ | |
ed4cb414 | 178 | if (dev->irq_enabled) |
b5e89ed5 | 179 | drm_irq_uninstall(dev); |
1da177e4 | 180 | |
ee0c6bfb | 181 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 CW |
182 | for (i = 0; i < I915_NUM_RINGS; i++) |
183 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
ee0c6bfb | 184 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 185 | |
398c9cb2 KP |
186 | /* Clear the HWS virtual address at teardown */ |
187 | if (I915_NEED_GFX_HWS(dev)) | |
188 | i915_free_hws(dev); | |
1da177e4 LT |
189 | |
190 | return 0; | |
191 | } | |
192 | ||
1a5036bf | 193 | static int i915_initialize(struct drm_device *dev, drm_i915_init_t *init) |
1da177e4 | 194 | { |
4c8a4be9 | 195 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 196 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
e8616b6c | 197 | int ret; |
1da177e4 | 198 | |
3a03ac1a DA |
199 | master_priv->sarea = drm_getsarea(dev); |
200 | if (master_priv->sarea) { | |
201 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
202 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
203 | } else { | |
8a4c47f3 | 204 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
205 | } |
206 | ||
673a394b | 207 | if (init->ring_size != 0) { |
ee1b1e5e | 208 | if (LP_RING(dev_priv)->buffer->obj != NULL) { |
673a394b EA |
209 | i915_dma_cleanup(dev); |
210 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
211 | "GEM mode\n"); | |
212 | return -EINVAL; | |
213 | } | |
1da177e4 | 214 | |
e8616b6c CW |
215 | ret = intel_render_ring_init_dri(dev, |
216 | init->ring_start, | |
217 | init->ring_size); | |
218 | if (ret) { | |
673a394b | 219 | i915_dma_cleanup(dev); |
e8616b6c | 220 | return ret; |
673a394b | 221 | } |
1da177e4 LT |
222 | } |
223 | ||
5d985ac8 DV |
224 | dev_priv->dri1.cpp = init->cpp; |
225 | dev_priv->dri1.back_offset = init->back_offset; | |
226 | dev_priv->dri1.front_offset = init->front_offset; | |
227 | dev_priv->dri1.current_page = 0; | |
7c1c2871 DA |
228 | if (master_priv->sarea_priv) |
229 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 230 | |
1da177e4 LT |
231 | /* Allow hardware batchbuffers unless told otherwise. |
232 | */ | |
8781342d | 233 | dev_priv->dri1.allow_batchbuffer = 1; |
1da177e4 | 234 | |
1da177e4 LT |
235 | return 0; |
236 | } | |
237 | ||
1a5036bf | 238 | static int i915_dma_resume(struct drm_device *dev) |
1da177e4 | 239 | { |
4c8a4be9 | 240 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 241 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
1da177e4 | 242 | |
8a4c47f3 | 243 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 244 | |
ee1b1e5e | 245 | if (ring->buffer->virtual_start == NULL) { |
1da177e4 LT |
246 | DRM_ERROR("can not ioremap virtual address for" |
247 | " ring buffer\n"); | |
20caafa6 | 248 | return -ENOMEM; |
1da177e4 LT |
249 | } |
250 | ||
251 | /* Program Hardware Status Page */ | |
8187a2b7 | 252 | if (!ring->status_page.page_addr) { |
1da177e4 | 253 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 254 | return -EINVAL; |
1da177e4 | 255 | } |
8a4c47f3 | 256 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
257 | ring->status_page.page_addr); |
258 | if (ring->status_page.gfx_addr != 0) | |
78501eac | 259 | intel_ring_setup_status_page(ring); |
dc7a9319 | 260 | else |
4cbf74cc | 261 | i915_write_hws_pga(dev); |
8187a2b7 | 262 | |
8a4c47f3 | 263 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
264 | |
265 | return 0; | |
266 | } | |
267 | ||
c153f45f EA |
268 | static int i915_dma_init(struct drm_device *dev, void *data, |
269 | struct drm_file *file_priv) | |
1da177e4 | 270 | { |
c153f45f | 271 | drm_i915_init_t *init = data; |
1da177e4 LT |
272 | int retcode = 0; |
273 | ||
cd9d4e9f DV |
274 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
275 | return -ENODEV; | |
276 | ||
c153f45f | 277 | switch (init->func) { |
1da177e4 | 278 | case I915_INIT_DMA: |
ba8bbcf6 | 279 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
280 | break; |
281 | case I915_CLEANUP_DMA: | |
282 | retcode = i915_dma_cleanup(dev); | |
283 | break; | |
284 | case I915_RESUME_DMA: | |
0d6aa60b | 285 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
286 | break; |
287 | default: | |
20caafa6 | 288 | retcode = -EINVAL; |
1da177e4 LT |
289 | break; |
290 | } | |
291 | ||
292 | return retcode; | |
293 | } | |
294 | ||
295 | /* Implement basically the same security restrictions as hardware does | |
296 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
297 | * | |
298 | * Most of the calculations below involve calculating the size of a | |
299 | * particular instruction. It's important to get the size right as | |
300 | * that tells us where the next instruction to check is. Any illegal | |
301 | * instruction detected will be given a size of zero, which is a | |
302 | * signal to abort the rest of the buffer. | |
303 | */ | |
e1f99ce6 | 304 | static int validate_cmd(int cmd) |
1da177e4 LT |
305 | { |
306 | switch (((cmd >> 29) & 0x7)) { | |
307 | case 0x0: | |
308 | switch ((cmd >> 23) & 0x3f) { | |
309 | case 0x0: | |
310 | return 1; /* MI_NOOP */ | |
311 | case 0x4: | |
312 | return 1; /* MI_FLUSH */ | |
313 | default: | |
314 | return 0; /* disallow everything else */ | |
315 | } | |
316 | break; | |
317 | case 0x1: | |
318 | return 0; /* reserved */ | |
319 | case 0x2: | |
320 | return (cmd & 0xff) + 2; /* 2d commands */ | |
321 | case 0x3: | |
322 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
323 | return 1; | |
324 | ||
325 | switch ((cmd >> 24) & 0x1f) { | |
326 | case 0x1c: | |
327 | return 1; | |
328 | case 0x1d: | |
b5e89ed5 | 329 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
330 | case 0x3: |
331 | return (cmd & 0x1f) + 2; | |
332 | case 0x4: | |
333 | return (cmd & 0xf) + 2; | |
334 | default: | |
335 | return (cmd & 0xffff) + 2; | |
336 | } | |
337 | case 0x1e: | |
338 | if (cmd & (1 << 23)) | |
339 | return (cmd & 0xffff) + 1; | |
340 | else | |
341 | return 1; | |
342 | case 0x1f: | |
343 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
344 | return (cmd & 0x1ffff) + 2; | |
345 | else if (cmd & (1 << 17)) /* indirect random */ | |
346 | if ((cmd & 0xffff) == 0) | |
347 | return 0; /* unknown length, too hard */ | |
348 | else | |
349 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
350 | else | |
351 | return 2; /* indirect sequential */ | |
352 | default: | |
353 | return 0; | |
354 | } | |
355 | default: | |
356 | return 0; | |
357 | } | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
1a5036bf | 362 | static int i915_emit_cmds(struct drm_device *dev, int *buffer, int dwords) |
1da177e4 | 363 | { |
4c8a4be9 | 364 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 365 | int i, ret; |
1da177e4 | 366 | |
ee1b1e5e | 367 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8) |
20caafa6 | 368 | return -EINVAL; |
de227f5f | 369 | |
1da177e4 | 370 | for (i = 0; i < dwords;) { |
e1f99ce6 | 371 | int sz = validate_cmd(buffer[i]); |
1a5036bf | 372 | |
e1f99ce6 | 373 | if (sz == 0 || i + sz > dwords) |
20caafa6 | 374 | return -EINVAL; |
e1f99ce6 | 375 | i += sz; |
1da177e4 LT |
376 | } |
377 | ||
e1f99ce6 CW |
378 | ret = BEGIN_LP_RING((dwords+1)&~1); |
379 | if (ret) | |
380 | return ret; | |
381 | ||
382 | for (i = 0; i < dwords; i++) | |
383 | OUT_RING(buffer[i]); | |
de227f5f DA |
384 | if (dwords & 1) |
385 | OUT_RING(0); | |
386 | ||
387 | ADVANCE_LP_RING(); | |
388 | ||
1da177e4 LT |
389 | return 0; |
390 | } | |
391 | ||
673a394b EA |
392 | int |
393 | i915_emit_box(struct drm_device *dev, | |
c4e7a414 CW |
394 | struct drm_clip_rect *box, |
395 | int DR1, int DR4) | |
1da177e4 | 396 | { |
e1f99ce6 | 397 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 398 | int ret; |
1da177e4 | 399 | |
c4e7a414 CW |
400 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
401 | box->y2 <= 0 || box->x2 <= 0) { | |
1da177e4 | 402 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
c4e7a414 | 403 | box->x1, box->y1, box->x2, box->y2); |
20caafa6 | 404 | return -EINVAL; |
1da177e4 LT |
405 | } |
406 | ||
a6c45cf0 | 407 | if (INTEL_INFO(dev)->gen >= 4) { |
e1f99ce6 CW |
408 | ret = BEGIN_LP_RING(4); |
409 | if (ret) | |
410 | return ret; | |
411 | ||
c29b669c | 412 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
c4e7a414 CW |
413 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
414 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c | 415 | OUT_RING(DR4); |
c29b669c | 416 | } else { |
e1f99ce6 CW |
417 | ret = BEGIN_LP_RING(6); |
418 | if (ret) | |
419 | return ret; | |
420 | ||
c29b669c AH |
421 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
422 | OUT_RING(DR1); | |
c4e7a414 CW |
423 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
424 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c AH |
425 | OUT_RING(DR4); |
426 | OUT_RING(0); | |
c29b669c | 427 | } |
e1f99ce6 | 428 | ADVANCE_LP_RING(); |
1da177e4 LT |
429 | |
430 | return 0; | |
431 | } | |
432 | ||
c29b669c AH |
433 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
434 | * emit. For now, do it in both places: | |
435 | */ | |
436 | ||
84b1fd10 | 437 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f | 438 | { |
4c8a4be9 | 439 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 440 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 441 | |
231f42a4 DV |
442 | dev_priv->dri1.counter++; |
443 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
444 | dev_priv->dri1.counter = 0; | |
7c1c2871 | 445 | if (master_priv->sarea_priv) |
231f42a4 | 446 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
de227f5f | 447 | |
e1f99ce6 CW |
448 | if (BEGIN_LP_RING(4) == 0) { |
449 | OUT_RING(MI_STORE_DWORD_INDEX); | |
450 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 451 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
452 | OUT_RING(0); |
453 | ADVANCE_LP_RING(); | |
454 | } | |
de227f5f DA |
455 | } |
456 | ||
1a5036bf | 457 | static int i915_dispatch_cmdbuffer(struct drm_device *dev, |
201361a5 EA |
458 | drm_i915_cmdbuffer_t *cmd, |
459 | struct drm_clip_rect *cliprects, | |
460 | void *cmdbuf) | |
1da177e4 LT |
461 | { |
462 | int nbox = cmd->num_cliprects; | |
463 | int i = 0, count, ret; | |
464 | ||
465 | if (cmd->sz & 0x3) { | |
466 | DRM_ERROR("alignment"); | |
20caafa6 | 467 | return -EINVAL; |
1da177e4 LT |
468 | } |
469 | ||
470 | i915_kernel_lost_context(dev); | |
471 | ||
472 | count = nbox ? nbox : 1; | |
473 | ||
474 | for (i = 0; i < count; i++) { | |
475 | if (i < nbox) { | |
c4e7a414 | 476 | ret = i915_emit_box(dev, &cliprects[i], |
1da177e4 LT |
477 | cmd->DR1, cmd->DR4); |
478 | if (ret) | |
479 | return ret; | |
480 | } | |
481 | ||
201361a5 | 482 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
483 | if (ret) |
484 | return ret; | |
485 | } | |
486 | ||
de227f5f | 487 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
488 | return 0; |
489 | } | |
490 | ||
1a5036bf RS |
491 | static int i915_dispatch_batchbuffer(struct drm_device *dev, |
492 | drm_i915_batchbuffer_t *batch, | |
201361a5 | 493 | struct drm_clip_rect *cliprects) |
1da177e4 | 494 | { |
e1f99ce6 | 495 | struct drm_i915_private *dev_priv = dev->dev_private; |
1da177e4 | 496 | int nbox = batch->num_cliprects; |
e1f99ce6 | 497 | int i, count, ret; |
1da177e4 LT |
498 | |
499 | if ((batch->start | batch->used) & 0x7) { | |
500 | DRM_ERROR("alignment"); | |
20caafa6 | 501 | return -EINVAL; |
1da177e4 LT |
502 | } |
503 | ||
504 | i915_kernel_lost_context(dev); | |
505 | ||
506 | count = nbox ? nbox : 1; | |
1da177e4 LT |
507 | for (i = 0; i < count; i++) { |
508 | if (i < nbox) { | |
c4e7a414 | 509 | ret = i915_emit_box(dev, &cliprects[i], |
e1f99ce6 | 510 | batch->DR1, batch->DR4); |
1da177e4 LT |
511 | if (ret) |
512 | return ret; | |
513 | } | |
514 | ||
0790d5e1 | 515 | if (!IS_I830(dev) && !IS_845G(dev)) { |
e1f99ce6 CW |
516 | ret = BEGIN_LP_RING(2); |
517 | if (ret) | |
518 | return ret; | |
519 | ||
a6c45cf0 | 520 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
521 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
522 | OUT_RING(batch->start); | |
523 | } else { | |
524 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
525 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
526 | } | |
1da177e4 | 527 | } else { |
e1f99ce6 CW |
528 | ret = BEGIN_LP_RING(4); |
529 | if (ret) | |
530 | return ret; | |
531 | ||
1da177e4 LT |
532 | OUT_RING(MI_BATCH_BUFFER); |
533 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
534 | OUT_RING(batch->start + batch->used - 4); | |
535 | OUT_RING(0); | |
1da177e4 | 536 | } |
e1f99ce6 | 537 | ADVANCE_LP_RING(); |
1da177e4 LT |
538 | } |
539 | ||
1cafd347 | 540 | |
f00a3ddf | 541 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
542 | if (BEGIN_LP_RING(2) == 0) { |
543 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
544 | OUT_RING(MI_NOOP); | |
545 | ADVANCE_LP_RING(); | |
546 | } | |
1cafd347 | 547 | } |
1da177e4 | 548 | |
e1f99ce6 | 549 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
550 | return 0; |
551 | } | |
552 | ||
1a5036bf | 553 | static int i915_dispatch_flip(struct drm_device *dev) |
1da177e4 | 554 | { |
4c8a4be9 | 555 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 DA |
556 | struct drm_i915_master_private *master_priv = |
557 | dev->primary->master->driver_priv; | |
e1f99ce6 | 558 | int ret; |
1da177e4 | 559 | |
7c1c2871 | 560 | if (!master_priv->sarea_priv) |
c99b058f KH |
561 | return -EINVAL; |
562 | ||
8a4c47f3 | 563 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 564 | __func__, |
5d985ac8 | 565 | dev_priv->dri1.current_page, |
be25ed9c | 566 | master_priv->sarea_priv->pf_current_page); |
1da177e4 | 567 | |
af6061af DA |
568 | i915_kernel_lost_context(dev); |
569 | ||
e1f99ce6 CW |
570 | ret = BEGIN_LP_RING(10); |
571 | if (ret) | |
572 | return ret; | |
573 | ||
585fb111 | 574 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af | 575 | OUT_RING(0); |
1da177e4 | 576 | |
af6061af DA |
577 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
578 | OUT_RING(0); | |
5d985ac8 DV |
579 | if (dev_priv->dri1.current_page == 0) { |
580 | OUT_RING(dev_priv->dri1.back_offset); | |
581 | dev_priv->dri1.current_page = 1; | |
1da177e4 | 582 | } else { |
5d985ac8 DV |
583 | OUT_RING(dev_priv->dri1.front_offset); |
584 | dev_priv->dri1.current_page = 0; | |
1da177e4 | 585 | } |
af6061af | 586 | OUT_RING(0); |
1da177e4 | 587 | |
af6061af DA |
588 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
589 | OUT_RING(0); | |
e1f99ce6 | 590 | |
af6061af | 591 | ADVANCE_LP_RING(); |
1da177e4 | 592 | |
231f42a4 | 593 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++; |
1da177e4 | 594 | |
e1f99ce6 CW |
595 | if (BEGIN_LP_RING(4) == 0) { |
596 | OUT_RING(MI_STORE_DWORD_INDEX); | |
597 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 598 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
599 | OUT_RING(0); |
600 | ADVANCE_LP_RING(); | |
601 | } | |
1da177e4 | 602 | |
5d985ac8 | 603 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
af6061af | 604 | return 0; |
1da177e4 LT |
605 | } |
606 | ||
1ec14ad3 | 607 | static int i915_quiescent(struct drm_device *dev) |
1da177e4 | 608 | { |
1da177e4 | 609 | i915_kernel_lost_context(dev); |
3e960501 | 610 | return intel_ring_idle(LP_RING(dev->dev_private)); |
1da177e4 LT |
611 | } |
612 | ||
c153f45f EA |
613 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
614 | struct drm_file *file_priv) | |
1da177e4 | 615 | { |
546b0974 EA |
616 | int ret; |
617 | ||
cd9d4e9f DV |
618 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
619 | return -ENODEV; | |
620 | ||
546b0974 | 621 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 622 | |
546b0974 EA |
623 | mutex_lock(&dev->struct_mutex); |
624 | ret = i915_quiescent(dev); | |
625 | mutex_unlock(&dev->struct_mutex); | |
626 | ||
627 | return ret; | |
1da177e4 LT |
628 | } |
629 | ||
c153f45f EA |
630 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
631 | struct drm_file *file_priv) | |
1da177e4 | 632 | { |
4c8a4be9 | 633 | struct drm_i915_private *dev_priv = dev->dev_private; |
4d10cc0f DV |
634 | struct drm_i915_master_private *master_priv; |
635 | drm_i915_sarea_t *sarea_priv; | |
c153f45f | 636 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 637 | int ret; |
201361a5 | 638 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 | 639 | |
cd9d4e9f DV |
640 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
641 | return -ENODEV; | |
642 | ||
4d10cc0f DV |
643 | master_priv = dev->primary->master->driver_priv; |
644 | sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv; | |
645 | ||
8781342d | 646 | if (!dev_priv->dri1.allow_batchbuffer) { |
1da177e4 | 647 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
20caafa6 | 648 | return -EINVAL; |
1da177e4 LT |
649 | } |
650 | ||
8a4c47f3 | 651 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 652 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 653 | |
546b0974 | 654 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 655 | |
201361a5 EA |
656 | if (batch->num_cliprects < 0) |
657 | return -EINVAL; | |
658 | ||
659 | if (batch->num_cliprects) { | |
9a298b2a | 660 | cliprects = kcalloc(batch->num_cliprects, |
b14c5679 | 661 | sizeof(*cliprects), |
9a298b2a | 662 | GFP_KERNEL); |
201361a5 EA |
663 | if (cliprects == NULL) |
664 | return -ENOMEM; | |
665 | ||
666 | ret = copy_from_user(cliprects, batch->cliprects, | |
667 | batch->num_cliprects * | |
668 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
669 | if (ret != 0) { |
670 | ret = -EFAULT; | |
201361a5 | 671 | goto fail_free; |
9927a403 | 672 | } |
201361a5 | 673 | } |
1da177e4 | 674 | |
546b0974 | 675 | mutex_lock(&dev->struct_mutex); |
201361a5 | 676 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 677 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 678 | |
c99b058f | 679 | if (sarea_priv) |
0baf823a | 680 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
681 | |
682 | fail_free: | |
9a298b2a | 683 | kfree(cliprects); |
201361a5 | 684 | |
1da177e4 LT |
685 | return ret; |
686 | } | |
687 | ||
c153f45f EA |
688 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
689 | struct drm_file *file_priv) | |
1da177e4 | 690 | { |
4c8a4be9 | 691 | struct drm_i915_private *dev_priv = dev->dev_private; |
4d10cc0f DV |
692 | struct drm_i915_master_private *master_priv; |
693 | drm_i915_sarea_t *sarea_priv; | |
c153f45f | 694 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
695 | struct drm_clip_rect *cliprects = NULL; |
696 | void *batch_data; | |
1da177e4 LT |
697 | int ret; |
698 | ||
8a4c47f3 | 699 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 700 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 701 | |
cd9d4e9f DV |
702 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
703 | return -ENODEV; | |
704 | ||
4d10cc0f DV |
705 | master_priv = dev->primary->master->driver_priv; |
706 | sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv; | |
707 | ||
546b0974 | 708 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 709 | |
201361a5 EA |
710 | if (cmdbuf->num_cliprects < 0) |
711 | return -EINVAL; | |
712 | ||
9a298b2a | 713 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
714 | if (batch_data == NULL) |
715 | return -ENOMEM; | |
716 | ||
717 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
718 | if (ret != 0) { |
719 | ret = -EFAULT; | |
201361a5 | 720 | goto fail_batch_free; |
9927a403 | 721 | } |
201361a5 EA |
722 | |
723 | if (cmdbuf->num_cliprects) { | |
9a298b2a | 724 | cliprects = kcalloc(cmdbuf->num_cliprects, |
b14c5679 | 725 | sizeof(*cliprects), GFP_KERNEL); |
a40e8d31 OA |
726 | if (cliprects == NULL) { |
727 | ret = -ENOMEM; | |
201361a5 | 728 | goto fail_batch_free; |
a40e8d31 | 729 | } |
201361a5 EA |
730 | |
731 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
732 | cmdbuf->num_cliprects * | |
733 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
734 | if (ret != 0) { |
735 | ret = -EFAULT; | |
201361a5 | 736 | goto fail_clip_free; |
9927a403 | 737 | } |
1da177e4 LT |
738 | } |
739 | ||
546b0974 | 740 | mutex_lock(&dev->struct_mutex); |
201361a5 | 741 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 742 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
743 | if (ret) { |
744 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 745 | goto fail_clip_free; |
1da177e4 LT |
746 | } |
747 | ||
c99b058f | 748 | if (sarea_priv) |
0baf823a | 749 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 750 | |
201361a5 | 751 | fail_clip_free: |
9a298b2a | 752 | kfree(cliprects); |
355d7f37 | 753 | fail_batch_free: |
9a298b2a | 754 | kfree(batch_data); |
201361a5 EA |
755 | |
756 | return ret; | |
1da177e4 LT |
757 | } |
758 | ||
1a5036bf | 759 | static int i915_emit_irq(struct drm_device *dev) |
9488867a | 760 | { |
4c8a4be9 | 761 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
762 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
763 | ||
764 | i915_kernel_lost_context(dev); | |
765 | ||
766 | DRM_DEBUG_DRIVER("\n"); | |
767 | ||
231f42a4 DV |
768 | dev_priv->dri1.counter++; |
769 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
770 | dev_priv->dri1.counter = 1; | |
9488867a | 771 | if (master_priv->sarea_priv) |
231f42a4 | 772 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
9488867a DV |
773 | |
774 | if (BEGIN_LP_RING(4) == 0) { | |
775 | OUT_RING(MI_STORE_DWORD_INDEX); | |
776 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 777 | OUT_RING(dev_priv->dri1.counter); |
9488867a DV |
778 | OUT_RING(MI_USER_INTERRUPT); |
779 | ADVANCE_LP_RING(); | |
780 | } | |
781 | ||
231f42a4 | 782 | return dev_priv->dri1.counter; |
9488867a DV |
783 | } |
784 | ||
1a5036bf | 785 | static int i915_wait_irq(struct drm_device *dev, int irq_nr) |
9488867a | 786 | { |
4c8a4be9 | 787 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
788 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
789 | int ret = 0; | |
a4872ba6 | 790 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
9488867a DV |
791 | |
792 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, | |
793 | READ_BREADCRUMB(dev_priv)); | |
794 | ||
795 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { | |
796 | if (master_priv->sarea_priv) | |
797 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
798 | return 0; | |
799 | } | |
800 | ||
801 | if (master_priv->sarea_priv) | |
802 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
803 | ||
804 | if (ring->irq_get(ring)) { | |
bfd8303a | 805 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ, |
9488867a DV |
806 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
807 | ring->irq_put(ring); | |
808 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) | |
809 | ret = -EBUSY; | |
810 | ||
811 | if (ret == -EBUSY) { | |
812 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", | |
231f42a4 | 813 | READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter); |
9488867a DV |
814 | } |
815 | ||
816 | return ret; | |
817 | } | |
818 | ||
819 | /* Needs the lock as it touches the ring. | |
820 | */ | |
821 | static int i915_irq_emit(struct drm_device *dev, void *data, | |
822 | struct drm_file *file_priv) | |
823 | { | |
4c8a4be9 | 824 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
825 | drm_i915_irq_emit_t *emit = data; |
826 | int result; | |
827 | ||
828 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
829 | return -ENODEV; | |
830 | ||
ee1b1e5e | 831 | if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) { |
9488867a DV |
832 | DRM_ERROR("called with no initialization\n"); |
833 | return -EINVAL; | |
834 | } | |
835 | ||
836 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
837 | ||
838 | mutex_lock(&dev->struct_mutex); | |
839 | result = i915_emit_irq(dev); | |
840 | mutex_unlock(&dev->struct_mutex); | |
841 | ||
1d6ac185 | 842 | if (copy_to_user(emit->irq_seq, &result, sizeof(int))) { |
9488867a DV |
843 | DRM_ERROR("copy_to_user\n"); |
844 | return -EFAULT; | |
845 | } | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
850 | /* Doesn't need the hardware lock. | |
851 | */ | |
852 | static int i915_irq_wait(struct drm_device *dev, void *data, | |
853 | struct drm_file *file_priv) | |
854 | { | |
4c8a4be9 | 855 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
856 | drm_i915_irq_wait_t *irqwait = data; |
857 | ||
858 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
859 | return -ENODEV; | |
860 | ||
861 | if (!dev_priv) { | |
862 | DRM_ERROR("called with no initialization\n"); | |
863 | return -EINVAL; | |
864 | } | |
865 | ||
866 | return i915_wait_irq(dev, irqwait->irq_seq); | |
867 | } | |
868 | ||
d1c1edbc DV |
869 | static int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
870 | struct drm_file *file_priv) | |
871 | { | |
4c8a4be9 | 872 | struct drm_i915_private *dev_priv = dev->dev_private; |
d1c1edbc DV |
873 | drm_i915_vblank_pipe_t *pipe = data; |
874 | ||
875 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
876 | return -ENODEV; | |
877 | ||
878 | if (!dev_priv) { | |
879 | DRM_ERROR("called with no initialization\n"); | |
880 | return -EINVAL; | |
881 | } | |
882 | ||
883 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
888 | /** | |
889 | * Schedule buffer swap at given vertical blank. | |
890 | */ | |
891 | static int i915_vblank_swap(struct drm_device *dev, void *data, | |
892 | struct drm_file *file_priv) | |
893 | { | |
894 | /* The delayed swap mechanism was fundamentally racy, and has been | |
895 | * removed. The model was that the client requested a delayed flip/swap | |
896 | * from the kernel, then waited for vblank before continuing to perform | |
897 | * rendering. The problem was that the kernel might wake the client | |
898 | * up before it dispatched the vblank swap (since the lock has to be | |
899 | * held while touching the ringbuffer), in which case the client would | |
900 | * clear and start the next frame before the swap occurred, and | |
901 | * flicker would occur in addition to likely missing the vblank. | |
902 | * | |
903 | * In the absence of this ioctl, userland falls back to a correct path | |
904 | * of waiting for a vblank, then dispatching the swap on its own. | |
905 | * Context switching to userland and back is plenty fast enough for | |
906 | * meeting the requirements of vblank swapping. | |
907 | */ | |
908 | return -EINVAL; | |
909 | } | |
910 | ||
c153f45f EA |
911 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
912 | struct drm_file *file_priv) | |
1da177e4 | 913 | { |
546b0974 EA |
914 | int ret; |
915 | ||
cd9d4e9f DV |
916 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
917 | return -ENODEV; | |
918 | ||
8a4c47f3 | 919 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 920 | |
546b0974 | 921 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 922 | |
546b0974 EA |
923 | mutex_lock(&dev->struct_mutex); |
924 | ret = i915_dispatch_flip(dev); | |
925 | mutex_unlock(&dev->struct_mutex); | |
926 | ||
927 | return ret; | |
1da177e4 LT |
928 | } |
929 | ||
c153f45f EA |
930 | static int i915_getparam(struct drm_device *dev, void *data, |
931 | struct drm_file *file_priv) | |
1da177e4 | 932 | { |
4c8a4be9 | 933 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 934 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
935 | int value; |
936 | ||
937 | if (!dev_priv) { | |
3e684eae | 938 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 939 | return -EINVAL; |
1da177e4 LT |
940 | } |
941 | ||
c153f45f | 942 | switch (param->param) { |
1da177e4 | 943 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 944 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
945 | break; |
946 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
8781342d | 947 | value = dev_priv->dri1.allow_batchbuffer ? 1 : 0; |
1da177e4 | 948 | break; |
0d6aa60b DA |
949 | case I915_PARAM_LAST_DISPATCH: |
950 | value = READ_BREADCRUMB(dev_priv); | |
951 | break; | |
ed4c9c4a | 952 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 953 | value = dev->pdev->device; |
ed4c9c4a | 954 | break; |
673a394b | 955 | case I915_PARAM_HAS_GEM: |
2e895b17 | 956 | value = 1; |
673a394b | 957 | break; |
0f973f27 JB |
958 | case I915_PARAM_NUM_FENCES_AVAIL: |
959 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
960 | break; | |
02e792fb DV |
961 | case I915_PARAM_HAS_OVERLAY: |
962 | value = dev_priv->overlay ? 1 : 0; | |
963 | break; | |
e9560f7c JB |
964 | case I915_PARAM_HAS_PAGEFLIPPING: |
965 | value = 1; | |
966 | break; | |
76446cac JB |
967 | case I915_PARAM_HAS_EXECBUF2: |
968 | /* depends on GEM */ | |
2e895b17 | 969 | value = 1; |
76446cac | 970 | break; |
e3a815fc | 971 | case I915_PARAM_HAS_BSD: |
edc912f5 | 972 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 973 | break; |
549f7365 | 974 | case I915_PARAM_HAS_BLT: |
edc912f5 | 975 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 976 | break; |
a1f2cc73 XH |
977 | case I915_PARAM_HAS_VEBOX: |
978 | value = intel_ring_initialized(&dev_priv->ring[VECS]); | |
979 | break; | |
a00b10c3 CW |
980 | case I915_PARAM_HAS_RELAXED_FENCING: |
981 | value = 1; | |
982 | break; | |
bbf0c6b3 DV |
983 | case I915_PARAM_HAS_COHERENT_RINGS: |
984 | value = 1; | |
985 | break; | |
72bfa19c CW |
986 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
987 | value = INTEL_INFO(dev)->gen >= 4; | |
988 | break; | |
271d81b8 CW |
989 | case I915_PARAM_HAS_RELAXED_DELTA: |
990 | value = 1; | |
991 | break; | |
ae662d31 EA |
992 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
993 | value = 1; | |
994 | break; | |
3d29b842 ED |
995 | case I915_PARAM_HAS_LLC: |
996 | value = HAS_LLC(dev); | |
997 | break; | |
651d794f CW |
998 | case I915_PARAM_HAS_WT: |
999 | value = HAS_WT(dev); | |
1000 | break; | |
777ee96f | 1001 | case I915_PARAM_HAS_ALIASING_PPGTT: |
7d9c4779 | 1002 | value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev); |
777ee96f | 1003 | break; |
172cf15d BW |
1004 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
1005 | value = 1; | |
1006 | break; | |
2fedbff9 CW |
1007 | case I915_PARAM_HAS_SEMAPHORES: |
1008 | value = i915_semaphore_is_enabled(dev); | |
1009 | break; | |
ec6f1bb9 DA |
1010 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
1011 | value = 1; | |
1012 | break; | |
d7d4eedd CW |
1013 | case I915_PARAM_HAS_SECURE_BATCHES: |
1014 | value = capable(CAP_SYS_ADMIN); | |
1015 | break; | |
b45305fc DV |
1016 | case I915_PARAM_HAS_PINNED_BATCHES: |
1017 | value = 1; | |
1018 | break; | |
ed5982e6 DV |
1019 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
1020 | value = 1; | |
1021 | break; | |
eef90ccb CW |
1022 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
1023 | value = 1; | |
1024 | break; | |
d728c8ef BV |
1025 | case I915_PARAM_CMD_PARSER_VERSION: |
1026 | value = i915_cmd_parser_get_version(); | |
1027 | break; | |
1da177e4 | 1028 | default: |
e29c32da | 1029 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 1030 | return -EINVAL; |
1da177e4 LT |
1031 | } |
1032 | ||
1d6ac185 DV |
1033 | if (copy_to_user(param->value, &value, sizeof(int))) { |
1034 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 1035 | return -EFAULT; |
1da177e4 LT |
1036 | } |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | ||
c153f45f EA |
1041 | static int i915_setparam(struct drm_device *dev, void *data, |
1042 | struct drm_file *file_priv) | |
1da177e4 | 1043 | { |
4c8a4be9 | 1044 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 1045 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
1046 | |
1047 | if (!dev_priv) { | |
3e684eae | 1048 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1049 | return -EINVAL; |
1da177e4 LT |
1050 | } |
1051 | ||
c153f45f | 1052 | switch (param->param) { |
1da177e4 | 1053 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
1054 | break; |
1055 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
1da177e4 LT |
1056 | break; |
1057 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
8781342d | 1058 | dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0; |
1da177e4 | 1059 | break; |
0f973f27 JB |
1060 | case I915_SETPARAM_NUM_USED_FENCES: |
1061 | if (param->value > dev_priv->num_fence_regs || | |
1062 | param->value < 0) | |
1063 | return -EINVAL; | |
1064 | /* Userspace can use first N regs */ | |
1065 | dev_priv->fence_reg_start = param->value; | |
1066 | break; | |
1da177e4 | 1067 | default: |
8a4c47f3 | 1068 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 1069 | param->param); |
20caafa6 | 1070 | return -EINVAL; |
1da177e4 LT |
1071 | } |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
c153f45f EA |
1076 | static int i915_set_status_page(struct drm_device *dev, void *data, |
1077 | struct drm_file *file_priv) | |
dc7a9319 | 1078 | { |
4c8a4be9 | 1079 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 1080 | drm_i915_hws_addr_t *hws = data; |
a4872ba6 | 1081 | struct intel_engine_cs *ring; |
b39d50e5 | 1082 | |
cd9d4e9f DV |
1083 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1084 | return -ENODEV; | |
1085 | ||
b39d50e5 ZW |
1086 | if (!I915_NEED_GFX_HWS(dev)) |
1087 | return -EINVAL; | |
dc7a9319 WZ |
1088 | |
1089 | if (!dev_priv) { | |
3e684eae | 1090 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1091 | return -EINVAL; |
dc7a9319 | 1092 | } |
dc7a9319 | 1093 | |
79e53945 JB |
1094 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1095 | WARN(1, "tried to set status page when mode setting active\n"); | |
1096 | return 0; | |
1097 | } | |
1098 | ||
8a4c47f3 | 1099 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 1100 | |
4f1ba0f8 | 1101 | ring = LP_RING(dev_priv); |
8187a2b7 | 1102 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 1103 | |
dd2757f8 | 1104 | dev_priv->dri1.gfx_hws_cpu_addr = |
5d4545ae | 1105 | ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096); |
316d3884 | 1106 | if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) { |
dc7a9319 | 1107 | i915_dma_cleanup(dev); |
e20f9c64 | 1108 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
1109 | DRM_ERROR("can not ioremap virtual address for" |
1110 | " G33 hw status page\n"); | |
20caafa6 | 1111 | return -ENOMEM; |
dc7a9319 | 1112 | } |
316d3884 DV |
1113 | |
1114 | memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE); | |
8187a2b7 | 1115 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
dc7a9319 | 1116 | |
8a4c47f3 | 1117 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 1118 | ring->status_page.gfx_addr); |
8a4c47f3 | 1119 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 1120 | ring->status_page.page_addr); |
dc7a9319 WZ |
1121 | return 0; |
1122 | } | |
1123 | ||
ec2a4c3f DA |
1124 | static int i915_get_bridge_dev(struct drm_device *dev) |
1125 | { | |
1126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1127 | ||
0206e353 | 1128 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
1129 | if (!dev_priv->bridge_dev) { |
1130 | DRM_ERROR("bridge device not found\n"); | |
1131 | return -1; | |
1132 | } | |
1133 | return 0; | |
1134 | } | |
1135 | ||
c4804411 ZW |
1136 | #define MCHBAR_I915 0x44 |
1137 | #define MCHBAR_I965 0x48 | |
1138 | #define MCHBAR_SIZE (4*4096) | |
1139 | ||
1140 | #define DEVEN_REG 0x54 | |
1141 | #define DEVEN_MCHBAR_EN (1 << 28) | |
1142 | ||
1143 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
1144 | static int | |
1145 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
1146 | { | |
4c8a4be9 | 1147 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1148 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1149 | u32 temp_lo, temp_hi = 0; |
1150 | u64 mchbar_addr; | |
a25c25c2 | 1151 | int ret; |
c4804411 | 1152 | |
a6c45cf0 | 1153 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1154 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
1155 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
1156 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
1157 | ||
1158 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
1159 | #ifdef CONFIG_PNP | |
1160 | if (mchbar_addr && | |
a25c25c2 CW |
1161 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
1162 | return 0; | |
c4804411 ZW |
1163 | #endif |
1164 | ||
1165 | /* Get some space for it */ | |
a25c25c2 CW |
1166 | dev_priv->mch_res.name = "i915 MCHBAR"; |
1167 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
1168 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
1169 | &dev_priv->mch_res, | |
c4804411 ZW |
1170 | MCHBAR_SIZE, MCHBAR_SIZE, |
1171 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 1172 | 0, pcibios_align_resource, |
c4804411 ZW |
1173 | dev_priv->bridge_dev); |
1174 | if (ret) { | |
1175 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
1176 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 1177 | return ret; |
c4804411 ZW |
1178 | } |
1179 | ||
a6c45cf0 | 1180 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1181 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
1182 | upper_32_bits(dev_priv->mch_res.start)); | |
1183 | ||
1184 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
1185 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 1186 | return 0; |
c4804411 ZW |
1187 | } |
1188 | ||
1189 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
1190 | static void | |
1191 | intel_setup_mchbar(struct drm_device *dev) | |
1192 | { | |
4c8a4be9 | 1193 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1194 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1195 | u32 temp; |
1196 | bool enabled; | |
1197 | ||
11ea8b7d JB |
1198 | if (IS_VALLEYVIEW(dev)) |
1199 | return; | |
1200 | ||
c4804411 ZW |
1201 | dev_priv->mchbar_need_disable = false; |
1202 | ||
1203 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1204 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1205 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
1206 | } else { | |
1207 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1208 | enabled = temp & 1; | |
1209 | } | |
1210 | ||
1211 | /* If it's already enabled, don't have to do anything */ | |
1212 | if (enabled) | |
1213 | return; | |
1214 | ||
1215 | if (intel_alloc_mchbar_resource(dev)) | |
1216 | return; | |
1217 | ||
1218 | dev_priv->mchbar_need_disable = true; | |
1219 | ||
1220 | /* Space is allocated or reserved, so enable it. */ | |
1221 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1222 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
1223 | temp | DEVEN_MCHBAR_EN); | |
1224 | } else { | |
1225 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1226 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
1227 | } | |
1228 | } | |
1229 | ||
1230 | static void | |
1231 | intel_teardown_mchbar(struct drm_device *dev) | |
1232 | { | |
4c8a4be9 | 1233 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1234 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1235 | u32 temp; |
1236 | ||
1237 | if (dev_priv->mchbar_need_disable) { | |
1238 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1239 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1240 | temp &= ~DEVEN_MCHBAR_EN; | |
1241 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1242 | } else { | |
1243 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1244 | temp &= ~1; | |
1245 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1246 | } | |
1247 | } | |
1248 | ||
1249 | if (dev_priv->mch_res.start) | |
1250 | release_resource(&dev_priv->mch_res); | |
1251 | } | |
1252 | ||
28d52043 DA |
1253 | /* true = enable decode, false = disable decoder */ |
1254 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1255 | { | |
1256 | struct drm_device *dev = cookie; | |
1257 | ||
1258 | intel_modeset_vga_set_state(dev, state); | |
1259 | if (state) | |
1260 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1261 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1262 | else | |
1263 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1264 | } | |
1265 | ||
6a9ee8af DA |
1266 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1267 | { | |
1268 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1269 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1a5036bf | 1270 | |
6a9ee8af | 1271 | if (state == VGA_SWITCHEROO_ON) { |
a70491cc | 1272 | pr_info("switched on\n"); |
5bcf719b | 1273 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
1274 | /* i915 resume handler doesn't set to D0 */ |
1275 | pci_set_power_state(dev->pdev, PCI_D0); | |
1276 | i915_resume(dev); | |
5bcf719b | 1277 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 1278 | } else { |
a70491cc | 1279 | pr_err("switched off\n"); |
5bcf719b | 1280 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 1281 | i915_suspend(dev, pmm); |
5bcf719b | 1282 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1283 | } |
1284 | } | |
1285 | ||
1286 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1287 | { | |
1288 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 1289 | |
fc8fd40e DV |
1290 | /* |
1291 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1292 | * locking inversion with the driver load path. And the access here is | |
1293 | * completely racy anyway. So don't bother with locking for now. | |
1294 | */ | |
1295 | return dev->open_count == 0; | |
6a9ee8af DA |
1296 | } |
1297 | ||
26ec685f TI |
1298 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
1299 | .set_gpu_state = i915_switcheroo_set_state, | |
1300 | .reprobe = NULL, | |
1301 | .can_switch = i915_switcheroo_can_switch, | |
1302 | }; | |
1303 | ||
2c7111db CW |
1304 | static int i915_load_modeset_init(struct drm_device *dev) |
1305 | { | |
1306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1307 | int ret; | |
79e53945 | 1308 | |
6d139a87 | 1309 | ret = intel_parse_bios(dev); |
79e53945 JB |
1310 | if (ret) |
1311 | DRM_INFO("failed to find VBIOS tables\n"); | |
1312 | ||
934f992c CW |
1313 | /* If we have > 1 VGA cards, then we need to arbitrate access |
1314 | * to the common VGA resources. | |
1315 | * | |
1316 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
1317 | * then we do not take part in VGA arbitration and the | |
1318 | * vga_client_register() fails with -ENODEV. | |
1319 | */ | |
ebff5fa9 DA |
1320 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
1321 | if (ret && ret != -ENODEV) | |
1322 | goto out; | |
28d52043 | 1323 | |
723bfd70 JB |
1324 | intel_register_dsm_handler(); |
1325 | ||
0d69704a | 1326 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 1327 | if (ret) |
5a79395b | 1328 | goto cleanup_vga_client; |
6a9ee8af | 1329 | |
9797fbfb CW |
1330 | /* Initialise stolen first so that we may reserve preallocated |
1331 | * objects for the BIOS to KMS transition. | |
1332 | */ | |
1333 | ret = i915_gem_init_stolen(dev); | |
1334 | if (ret) | |
1335 | goto cleanup_vga_switcheroo; | |
1336 | ||
e13192f6 ID |
1337 | intel_power_domains_init_hw(dev_priv); |
1338 | ||
bb0f1b5c | 1339 | ret = drm_irq_install(dev, dev->pdev->irq); |
52d7eced DV |
1340 | if (ret) |
1341 | goto cleanup_gem_stolen; | |
1342 | ||
1343 | /* Important: The output setup functions called by modeset_init need | |
1344 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
1345 | intel_modeset_init(dev); |
1346 | ||
1070a42b | 1347 | ret = i915_gem_init(dev); |
79e53945 | 1348 | if (ret) |
713028b3 | 1349 | goto cleanup_irq; |
2c7111db | 1350 | |
073f34d9 JB |
1351 | INIT_WORK(&dev_priv->console_resume_work, intel_console_resume); |
1352 | ||
52d7eced | 1353 | intel_modeset_gem_init(dev); |
2c7111db | 1354 | |
79e53945 JB |
1355 | /* Always safe in the mode setting case. */ |
1356 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
ba0bf120 | 1357 | dev->vblank_disable_allowed = true; |
713028b3 | 1358 | if (INTEL_INFO(dev)->num_pipes == 0) |
e3c74757 | 1359 | return 0; |
79e53945 | 1360 | |
5a79395b CW |
1361 | ret = intel_fbdev_init(dev); |
1362 | if (ret) | |
52d7eced DV |
1363 | goto cleanup_gem; |
1364 | ||
20afbda2 DV |
1365 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
1366 | intel_hpd_init(dev); | |
1367 | ||
1368 | /* | |
1369 | * Some ports require correctly set-up hpd registers for detection to | |
1370 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1371 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1372 | * irqs are fully enabled. Now we should scan for the initial config | |
1373 | * only once hotplug handling is enabled, but due to screwed-up locking | |
1374 | * around kms/fbdev init we can't protect the fdbev initial config | |
1375 | * scanning against hotplug events. Hence do this first and ignore the | |
1376 | * tiny window where we will loose hotplug notifactions. | |
1377 | */ | |
1378 | intel_fbdev_initial_config(dev); | |
1379 | ||
eb1f8e4f | 1380 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 1381 | |
79e53945 JB |
1382 | return 0; |
1383 | ||
2c7111db CW |
1384 | cleanup_gem: |
1385 | mutex_lock(&dev->struct_mutex); | |
1386 | i915_gem_cleanup_ringbuffer(dev); | |
55d23285 | 1387 | i915_gem_context_fini(dev); |
2c7111db | 1388 | mutex_unlock(&dev->struct_mutex); |
bdf4fd7e | 1389 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
713028b3 | 1390 | cleanup_irq: |
52d7eced | 1391 | drm_irq_uninstall(dev); |
9797fbfb CW |
1392 | cleanup_gem_stolen: |
1393 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
1394 | cleanup_vga_switcheroo: |
1395 | vga_switcheroo_unregister_client(dev->pdev); | |
1396 | cleanup_vga_client: | |
1397 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
1398 | out: |
1399 | return ret; | |
1400 | } | |
1401 | ||
7c1c2871 DA |
1402 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1403 | { | |
1404 | struct drm_i915_master_private *master_priv; | |
1405 | ||
9a298b2a | 1406 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1407 | if (!master_priv) |
1408 | return -ENOMEM; | |
1409 | ||
1410 | master->driver_priv = master_priv; | |
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1415 | { | |
1416 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1417 | ||
1418 | if (!master_priv) | |
1419 | return; | |
1420 | ||
9a298b2a | 1421 | kfree(master_priv); |
7c1c2871 DA |
1422 | |
1423 | master->driver_priv = NULL; | |
1424 | } | |
1425 | ||
243eaf38 | 1426 | #if IS_ENABLED(CONFIG_FB) |
e188719a DV |
1427 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
1428 | { | |
1429 | struct apertures_struct *ap; | |
1430 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
1431 | bool primary; | |
1432 | ||
1433 | ap = alloc_apertures(1); | |
1434 | if (!ap) | |
1435 | return; | |
1436 | ||
dabb7a91 | 1437 | ap->ranges[0].base = dev_priv->gtt.mappable_base; |
f64e2922 | 1438 | ap->ranges[0].size = dev_priv->gtt.mappable_end; |
93d18799 | 1439 | |
e188719a DV |
1440 | primary = |
1441 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
1442 | ||
1443 | remove_conflicting_framebuffers(ap, "inteldrmfb", primary); | |
1444 | ||
1445 | kfree(ap); | |
1446 | } | |
4520f53a DV |
1447 | #else |
1448 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) | |
1449 | { | |
1450 | } | |
1451 | #endif | |
e188719a | 1452 | |
a4de0526 DV |
1453 | #if !defined(CONFIG_VGA_CONSOLE) |
1454 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
1455 | { | |
1456 | return 0; | |
1457 | } | |
1458 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
1459 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
1460 | { | |
1461 | return -ENODEV; | |
1462 | } | |
1463 | #else | |
1464 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
1465 | { | |
1466 | int ret; | |
1467 | ||
1468 | DRM_INFO("Replacing VGA console driver\n"); | |
1469 | ||
1470 | console_lock(); | |
1471 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
1472 | if (ret == 0) { | |
1473 | ret = do_unregister_con_driver(&vga_con); | |
1474 | ||
1475 | /* Ignore "already unregistered". */ | |
1476 | if (ret == -ENODEV) | |
1477 | ret = 0; | |
1478 | } | |
1479 | console_unlock(); | |
1480 | ||
1481 | return ret; | |
1482 | } | |
1483 | #endif | |
1484 | ||
c96ea64e DV |
1485 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
1486 | { | |
5c969aa7 | 1487 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 1488 | |
e2a5800a DL |
1489 | #define PRINT_S(name) "%s" |
1490 | #define SEP_EMPTY | |
79fc46df DL |
1491 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
1492 | #define SEP_COMMA , | |
19c656a1 | 1493 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" |
e2a5800a | 1494 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
1495 | info->gen, |
1496 | dev_priv->dev->pdev->device, | |
19c656a1 | 1497 | dev_priv->dev->pdev->revision, |
79fc46df | 1498 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
1499 | #undef PRINT_S |
1500 | #undef SEP_EMPTY | |
79fc46df DL |
1501 | #undef PRINT_FLAG |
1502 | #undef SEP_COMMA | |
c96ea64e DV |
1503 | } |
1504 | ||
22d3fd46 DL |
1505 | /* |
1506 | * Determine various intel_device_info fields at runtime. | |
1507 | * | |
1508 | * Use it when either: | |
1509 | * - it's judged too laborious to fill n static structures with the limit | |
1510 | * when a simple if statement does the job, | |
1511 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
1512 | * |
1513 | * This function needs to be called: | |
1514 | * - after the MMIO has been setup as we are reading registers, | |
1515 | * - after the PCH has been detected, | |
1516 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
1517 | */ |
1518 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
1519 | { | |
658ac4c6 | 1520 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 1521 | struct intel_device_info *info; |
d615a166 | 1522 | enum pipe pipe; |
22d3fd46 | 1523 | |
658ac4c6 | 1524 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 1525 | |
22d3fd46 | 1526 | if (IS_VALLEYVIEW(dev)) |
d615a166 DL |
1527 | for_each_pipe(pipe) |
1528 | info->num_sprites[pipe] = 2; | |
1529 | else | |
1530 | for_each_pipe(pipe) | |
1531 | info->num_sprites[pipe] = 1; | |
658ac4c6 | 1532 | |
a0bae57f DL |
1533 | if (i915.disable_display) { |
1534 | DRM_INFO("Display disabled (module parameter)\n"); | |
1535 | info->num_pipes = 0; | |
1536 | } else if (info->num_pipes > 0 && | |
1537 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && | |
1538 | !IS_VALLEYVIEW(dev)) { | |
658ac4c6 DL |
1539 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
1540 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
1541 | ||
1542 | /* | |
1543 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
1544 | * is fused off. Unfortunately it seems that, at least in | |
1545 | * certain cases, fused off display means that PCH display | |
1546 | * reads don't land anywhere. In that case, we read 0s. | |
1547 | * | |
1548 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
1549 | * should be set when taking over after the firmware. | |
1550 | */ | |
1551 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
1552 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
1553 | (dev_priv->pch_type == PCH_CPT && | |
1554 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
1555 | DRM_INFO("Display fused off, disabling\n"); | |
1556 | info->num_pipes = 0; | |
1557 | } | |
1558 | } | |
22d3fd46 DL |
1559 | } |
1560 | ||
79e53945 JB |
1561 | /** |
1562 | * i915_driver_load - setup chip and create an initial config | |
1563 | * @dev: DRM device | |
1564 | * @flags: startup flags | |
1565 | * | |
1566 | * The driver load routine has to do several things: | |
1567 | * - drive output discovery via intel_modeset_init() | |
1568 | * - initialize the memory manager | |
1569 | * - allocate initial config memory | |
1570 | * - setup the DRM framebuffer with the allocated memory | |
1571 | */ | |
84b1fd10 | 1572 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1573 | { |
ea059a1e | 1574 | struct drm_i915_private *dev_priv; |
5c969aa7 | 1575 | struct intel_device_info *info, *device_info; |
934d6086 | 1576 | int ret = 0, mmio_bar, mmio_size; |
9021f284 | 1577 | uint32_t aperture_size; |
fe669bf8 | 1578 | |
26394d92 DV |
1579 | info = (struct intel_device_info *) flags; |
1580 | ||
1581 | /* Refuse to load on gen6+ without kms enabled. */ | |
e147accb JN |
1582 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) { |
1583 | DRM_INFO("Your hardware requires kernel modesetting (KMS)\n"); | |
1584 | DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n"); | |
26394d92 | 1585 | return -ENODEV; |
e147accb | 1586 | } |
26394d92 | 1587 | |
24986ee0 DV |
1588 | /* UMS needs agp support. */ |
1589 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp) | |
1590 | return -EINVAL; | |
1591 | ||
b14c5679 | 1592 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
ba8bbcf6 JB |
1593 | if (dev_priv == NULL) |
1594 | return -ENOMEM; | |
1595 | ||
755f68f4 | 1596 | dev->dev_private = dev_priv; |
673a394b | 1597 | dev_priv->dev = dev; |
5c969aa7 DL |
1598 | |
1599 | /* copy initial configuration to dev_priv->info */ | |
1600 | device_info = (struct intel_device_info *)&dev_priv->info; | |
1601 | *device_info = *info; | |
ba8bbcf6 | 1602 | |
7dcd2677 KK |
1603 | spin_lock_init(&dev_priv->irq_lock); |
1604 | spin_lock_init(&dev_priv->gpu_error.lock); | |
58c68779 | 1605 | spin_lock_init(&dev_priv->backlight_lock); |
907b28c5 | 1606 | spin_lock_init(&dev_priv->uncore.lock); |
c20e8355 | 1607 | spin_lock_init(&dev_priv->mm.object_stat_lock); |
84c33a64 | 1608 | spin_lock_init(&dev_priv->mmio_flip_lock); |
7dcd2677 | 1609 | mutex_init(&dev_priv->dpio_lock); |
7dcd2677 KK |
1610 | mutex_init(&dev_priv->modeset_restore_lock); |
1611 | ||
f742a552 | 1612 | intel_pm_setup(dev); |
c67a470b | 1613 | |
07144428 DL |
1614 | intel_display_crc_init(dev); |
1615 | ||
c96ea64e DV |
1616 | i915_dump_device_info(dev_priv); |
1617 | ||
ed1c9e2c PZ |
1618 | /* Not all pre-production machines fall into this category, only the |
1619 | * very first ones. Almost everything should work, except for maybe | |
1620 | * suspend/resume. And we don't implement workarounds that affect only | |
1621 | * pre-production machines. */ | |
1622 | if (IS_HSW_EARLY_SDV(dev)) | |
1623 | DRM_INFO("This is an early pre-production Haswell machine. " | |
1624 | "It may not be fully functional.\n"); | |
1625 | ||
ec2a4c3f DA |
1626 | if (i915_get_bridge_dev(dev)) { |
1627 | ret = -EIO; | |
1628 | goto free_priv; | |
1629 | } | |
1630 | ||
1e1bd0fd BW |
1631 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
1632 | /* Before gen4, the registers and the GTT are behind different BARs. | |
1633 | * However, from gen4 onwards, the registers and the GTT are shared | |
1634 | * in the same BAR, so we want to restrict this ioremap from | |
1635 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1636 | * the register BAR remains the same size for all the earlier | |
1637 | * generations up to Ironlake. | |
1638 | */ | |
1639 | if (info->gen < 5) | |
1640 | mmio_size = 512*1024; | |
1641 | else | |
1642 | mmio_size = 2*1024*1024; | |
1643 | ||
1644 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
1645 | if (!dev_priv->regs) { | |
1646 | DRM_ERROR("failed to map registers\n"); | |
1647 | ret = -EIO; | |
1648 | goto put_bridge; | |
1649 | } | |
1650 | ||
c3d685a7 BW |
1651 | /* This must be called before any calls to HAS_PCH_* */ |
1652 | intel_detect_pch(dev); | |
1653 | ||
1654 | intel_uncore_init(dev); | |
1655 | ||
e76e9aeb BW |
1656 | ret = i915_gem_gtt_init(dev); |
1657 | if (ret) | |
cbb47d17 | 1658 | goto out_regs; |
e188719a | 1659 | |
a4de0526 DV |
1660 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1661 | ret = i915_kick_out_vgacon(dev_priv); | |
1662 | if (ret) { | |
1663 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
1664 | goto out_gtt; | |
1665 | } | |
1666 | ||
1623392a | 1667 | i915_kick_out_firmware_fb(dev_priv); |
a4de0526 | 1668 | } |
e188719a | 1669 | |
466e69b8 DA |
1670 | pci_set_master(dev->pdev); |
1671 | ||
9f82d238 DV |
1672 | /* overlay on gen2 is broken and can't address above 1G */ |
1673 | if (IS_GEN2(dev)) | |
1674 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1675 | ||
6927faf3 JN |
1676 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1677 | * using 32bit addressing, overwriting memory if HWS is located | |
1678 | * above 4GB. | |
1679 | * | |
1680 | * The documentation also mentions an issue with undefined | |
1681 | * behaviour if any general state is accessed within a page above 4GB, | |
1682 | * which also needs to be handled carefully. | |
1683 | */ | |
1684 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1685 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1686 | ||
93d18799 | 1687 | aperture_size = dev_priv->gtt.mappable_end; |
71e9339c | 1688 | |
5d4545ae BW |
1689 | dev_priv->gtt.mappable = |
1690 | io_mapping_create_wc(dev_priv->gtt.mappable_base, | |
dd2757f8 | 1691 | aperture_size); |
5d4545ae | 1692 | if (dev_priv->gtt.mappable == NULL) { |
6644107d | 1693 | ret = -EIO; |
cbb47d17 | 1694 | goto out_gtt; |
6644107d VP |
1695 | } |
1696 | ||
911bdf0a BW |
1697 | dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base, |
1698 | aperture_size); | |
19966754 | 1699 | |
e642abbf CW |
1700 | /* The i915 workqueue is primarily used for batched retirement of |
1701 | * requests (and thus managing bo) once the task has been completed | |
1702 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
1703 | * need high-priority retirement, such as waiting for an explicit | |
1704 | * bo. | |
1705 | * | |
1706 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 1707 | * idle-timers and recording error state. |
e642abbf CW |
1708 | * |
1709 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1710 | * so there is no point in running more than one instance of the | |
53621860 | 1711 | * workqueue at any time. Use an ordered one. |
e642abbf | 1712 | */ |
53621860 | 1713 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
9c9fe1f8 EA |
1714 | if (dev_priv->wq == NULL) { |
1715 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1716 | ret = -ENOMEM; | |
a7b85d2a | 1717 | goto out_mtrrfree; |
9c9fe1f8 EA |
1718 | } |
1719 | ||
f71d4af4 | 1720 | intel_irq_init(dev); |
78511f2a | 1721 | intel_uncore_sanitize(dev); |
9880b7a5 | 1722 | |
c4804411 ZW |
1723 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1724 | intel_setup_mchbar(dev); | |
f899fc64 | 1725 | intel_setup_gmbus(dev); |
44834a67 | 1726 | intel_opregion_setup(dev); |
c4804411 | 1727 | |
6d139a87 BF |
1728 | intel_setup_bios(dev); |
1729 | ||
673a394b EA |
1730 | i915_gem_load(dev); |
1731 | ||
ed4cb414 EA |
1732 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1733 | * integrated graphics even though the support isn't actually there | |
1734 | * according to the published specs. It doesn't appear to function | |
1735 | * correctly in testing on 945G. | |
1736 | * This may be a side effect of MSI having been made available for PEG | |
1737 | * and the registers being closely associated. | |
d1ed629f KP |
1738 | * |
1739 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1740 | * be lost or delayed, but we use them anyways to avoid |
1741 | * stuck interrupts on some machines. | |
ed4cb414 | 1742 | */ |
b60678a7 | 1743 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1744 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1745 | |
22d3fd46 | 1746 | intel_device_info_runtime_init(dev); |
7f1f3851 | 1747 | |
e3c74757 BW |
1748 | if (INTEL_INFO(dev)->num_pipes) { |
1749 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); | |
1750 | if (ret) | |
1751 | goto out_gem_unload; | |
1752 | } | |
52440211 | 1753 | |
da7e29bd | 1754 | intel_power_domains_init(dev_priv); |
a38911a3 | 1755 | |
79e53945 | 1756 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 1757 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
1758 | if (ret < 0) { |
1759 | DRM_ERROR("failed to init modeset\n"); | |
cbb47d17 | 1760 | goto out_power_well; |
79e53945 | 1761 | } |
db1b76ca DV |
1762 | } else { |
1763 | /* Start out suspended in ums mode. */ | |
1764 | dev_priv->ums.mm_suspended = 1; | |
79e53945 JB |
1765 | } |
1766 | ||
0136db58 BW |
1767 | i915_setup_sysfs(dev); |
1768 | ||
e3c74757 BW |
1769 | if (INTEL_INFO(dev)->num_pipes) { |
1770 | /* Must be done after probing outputs */ | |
1771 | intel_opregion_init(dev); | |
8e5c2b77 | 1772 | acpi_video_register(); |
e3c74757 | 1773 | } |
74a365b3 | 1774 | |
eb48eb00 DV |
1775 | if (IS_GEN5(dev)) |
1776 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 1777 | |
8a187455 PZ |
1778 | intel_init_runtime_pm(dev_priv); |
1779 | ||
79e53945 JB |
1780 | return 0; |
1781 | ||
cbb47d17 | 1782 | out_power_well: |
da7e29bd | 1783 | intel_power_domains_remove(dev_priv); |
cbb47d17 | 1784 | drm_vblank_cleanup(dev); |
56e2ea34 | 1785 | out_gem_unload: |
4bdc7293 ID |
1786 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1787 | unregister_shrinker(&dev_priv->mm.shrinker); | |
a7b85d2a | 1788 | |
56e2ea34 CW |
1789 | if (dev->pdev->msi_enabled) |
1790 | pci_disable_msi(dev->pdev); | |
1791 | ||
1792 | intel_teardown_gmbus(dev); | |
1793 | intel_teardown_mchbar(dev); | |
22accca0 | 1794 | pm_qos_remove_request(&dev_priv->pm_qos); |
9c9fe1f8 | 1795 | destroy_workqueue(dev_priv->wq); |
a7b85d2a | 1796 | out_mtrrfree: |
911bdf0a | 1797 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
5d4545ae | 1798 | io_mapping_free(dev_priv->gtt.mappable); |
cbb47d17 | 1799 | out_gtt: |
853ba5d2 | 1800 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
cbb47d17 | 1801 | out_regs: |
c3d685a7 | 1802 | intel_uncore_fini(dev); |
6dda569f | 1803 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
1804 | put_bridge: |
1805 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1806 | free_priv: |
cbb47d17 CW |
1807 | if (dev_priv->slab) |
1808 | kmem_cache_destroy(dev_priv->slab); | |
9a298b2a | 1809 | kfree(dev_priv); |
ba8bbcf6 JB |
1810 | return ret; |
1811 | } | |
1812 | ||
1813 | int i915_driver_unload(struct drm_device *dev) | |
1814 | { | |
1815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1816 | int ret; |
ba8bbcf6 | 1817 | |
ce58c32b CW |
1818 | ret = i915_gem_suspend(dev); |
1819 | if (ret) { | |
1820 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
1821 | return ret; | |
1822 | } | |
1823 | ||
8a187455 PZ |
1824 | intel_fini_runtime_pm(dev_priv); |
1825 | ||
eb48eb00 | 1826 | intel_gpu_ips_teardown(); |
7648fa99 | 1827 | |
1c2256df ID |
1828 | /* The i915.ko module is still not prepared to be loaded when |
1829 | * the power well is not enabled, so just enable it in case | |
1830 | * we're going to unload/reload. */ | |
da7e29bd ID |
1831 | intel_display_set_init_power(dev_priv, true); |
1832 | intel_power_domains_remove(dev_priv); | |
a38911a3 | 1833 | |
0136db58 BW |
1834 | i915_teardown_sysfs(dev); |
1835 | ||
4bdc7293 ID |
1836 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1837 | unregister_shrinker(&dev_priv->mm.shrinker); | |
17250b71 | 1838 | |
5d4545ae | 1839 | io_mapping_free(dev_priv->gtt.mappable); |
911bdf0a | 1840 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
ab657db1 | 1841 | |
44834a67 CW |
1842 | acpi_video_unregister(); |
1843 | ||
79e53945 | 1844 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
7b4f3990 | 1845 | intel_fbdev_fini(dev); |
3d8620cc | 1846 | intel_modeset_cleanup(dev); |
073f34d9 | 1847 | cancel_work_sync(&dev_priv->console_resume_work); |
3d8620cc | 1848 | |
6363ee6f ZY |
1849 | /* |
1850 | * free the memory space allocated for the child device | |
1851 | * config parsed from VBT | |
1852 | */ | |
41aa3448 RV |
1853 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
1854 | kfree(dev_priv->vbt.child_dev); | |
1855 | dev_priv->vbt.child_dev = NULL; | |
1856 | dev_priv->vbt.child_dev_num = 0; | |
6363ee6f | 1857 | } |
6c0d9350 | 1858 | |
6a9ee8af | 1859 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 1860 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
1861 | } |
1862 | ||
a8b4899e | 1863 | /* Free error state after interrupts are fully disabled. */ |
99584db3 DV |
1864 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
1865 | cancel_work_sync(&dev_priv->gpu_error.work); | |
a8b4899e | 1866 | i915_destroy_error_state(dev); |
bc0c7f14 | 1867 | |
ed4cb414 EA |
1868 | if (dev->pdev->msi_enabled) |
1869 | pci_disable_msi(dev->pdev); | |
1870 | ||
44834a67 | 1871 | intel_opregion_fini(dev); |
8ee1c3db | 1872 | |
79e53945 | 1873 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
1874 | /* Flush any outstanding unpin_work. */ |
1875 | flush_workqueue(dev_priv->wq); | |
1876 | ||
79e53945 JB |
1877 | mutex_lock(&dev->struct_mutex); |
1878 | i915_gem_cleanup_ringbuffer(dev); | |
55a66628 | 1879 | i915_gem_context_fini(dev); |
bdf4fd7e | 1880 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
79e53945 | 1881 | mutex_unlock(&dev->struct_mutex); |
9797fbfb | 1882 | i915_gem_cleanup_stolen(dev); |
c2873e96 KP |
1883 | |
1884 | if (!I915_NEED_GFX_HWS(dev)) | |
1885 | i915_free_hws(dev); | |
79e53945 JB |
1886 | } |
1887 | ||
a7bbbd63 | 1888 | WARN_ON(!list_empty(&dev_priv->vm_list)); |
701394cc | 1889 | |
cbb47d17 CW |
1890 | drm_vblank_cleanup(dev); |
1891 | ||
f899fc64 | 1892 | intel_teardown_gmbus(dev); |
c4804411 ZW |
1893 | intel_teardown_mchbar(dev); |
1894 | ||
bc0c7f14 | 1895 | destroy_workqueue(dev_priv->wq); |
9ee32fea | 1896 | pm_qos_remove_request(&dev_priv->pm_qos); |
bc0c7f14 | 1897 | |
853ba5d2 | 1898 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
6640aab6 | 1899 | |
aec347ab CW |
1900 | intel_uncore_fini(dev); |
1901 | if (dev_priv->regs != NULL) | |
1902 | pci_iounmap(dev->pdev, dev_priv->regs); | |
1903 | ||
42dcedd4 CW |
1904 | if (dev_priv->slab) |
1905 | kmem_cache_destroy(dev_priv->slab); | |
bc0c7f14 | 1906 | |
ec2a4c3f | 1907 | pci_dev_put(dev_priv->bridge_dev); |
2206e6a1 | 1908 | kfree(dev_priv); |
ba8bbcf6 | 1909 | |
22eae947 DA |
1910 | return 0; |
1911 | } | |
1912 | ||
f787a5f5 | 1913 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1914 | { |
b29c19b6 | 1915 | int ret; |
673a394b | 1916 | |
b29c19b6 CW |
1917 | ret = i915_gem_open(dev, file); |
1918 | if (ret) | |
1919 | return ret; | |
254f965c | 1920 | |
673a394b EA |
1921 | return 0; |
1922 | } | |
1923 | ||
79e53945 JB |
1924 | /** |
1925 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1926 | * @dev: DRM device | |
1927 | * | |
1928 | * Take care of cleaning up after all DRM clients have exited. In the | |
1929 | * mode setting case, we want to restore the kernel's initial mode (just | |
1930 | * in case the last client left us in a bad state). | |
1931 | * | |
9021f284 | 1932 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1933 | * and DMA structures, since the kernel won't be using them, and clea |
1934 | * up any GEM state. | |
1935 | */ | |
1a5036bf | 1936 | void i915_driver_lastclose(struct drm_device *dev) |
1da177e4 | 1937 | { |
4c8a4be9 | 1938 | struct drm_i915_private *dev_priv = dev->dev_private; |
ba8bbcf6 | 1939 | |
e8aeaee7 DV |
1940 | /* On gen6+ we refuse to init without kms enabled, but then the drm core |
1941 | * goes right around and calls lastclose. Check for this and don't clean | |
1942 | * up anything. */ | |
1943 | if (!dev_priv) | |
1944 | return; | |
1945 | ||
1946 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
0632fef6 | 1947 | intel_fbdev_restore_mode(dev); |
6a9ee8af | 1948 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 1949 | return; |
79e53945 | 1950 | } |
144a75fa | 1951 | |
673a394b EA |
1952 | i915_gem_lastclose(dev); |
1953 | ||
b5e89ed5 | 1954 | i915_dma_cleanup(dev); |
1da177e4 LT |
1955 | } |
1956 | ||
2885f6ac | 1957 | void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
1da177e4 | 1958 | { |
0d1430a3 | 1959 | mutex_lock(&dev->struct_mutex); |
2885f6ac JH |
1960 | i915_gem_context_close(dev, file); |
1961 | i915_gem_release(dev, file); | |
0d1430a3 | 1962 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
1963 | } |
1964 | ||
f787a5f5 | 1965 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1966 | { |
f787a5f5 | 1967 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1968 | |
a8ebba75 ZY |
1969 | if (file_priv && file_priv->bsd_ring) |
1970 | file_priv->bsd_ring = NULL; | |
f787a5f5 | 1971 | kfree(file_priv); |
673a394b EA |
1972 | } |
1973 | ||
baa70943 | 1974 | const struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
1975 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1976 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1977 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1978 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1979 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1980 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
10ba5012 | 1981 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
1b2f1489 | 1982 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1983 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1984 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1985 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1b2f1489 | 1986 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
b2c606fe | 1987 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1988 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1b2f1489 DA |
1989 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
1990 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
1991 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1992 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1993 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
10ba5012 | 1994 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
1995 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1996 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
1997 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1998 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1999 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2000 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 DA |
2001 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
2002 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
2003 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
2004 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2005 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2006 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2007 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2008 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2009 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2010 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2011 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2012 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 | 2013 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
10ba5012 | 2014 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
2015 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
2016 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
2017 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
2018 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
10ba5012 KH |
2019 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
2020 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2021 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
2022 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
b6359918 | 2023 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
5cc9ed4b | 2024 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
c94f7029 DA |
2025 | }; |
2026 | ||
f95aeb17 | 2027 | int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); |
cda17380 | 2028 | |
9021f284 DV |
2029 | /* |
2030 | * This is really ugly: Because old userspace abused the linux agp interface to | |
2031 | * manage the gtt, we need to claim that all intel devices are agp. For | |
2032 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 2033 | */ |
1a5036bf | 2034 | int i915_driver_device_is_agp(struct drm_device *dev) |
cda17380 DA |
2035 | { |
2036 | return 1; | |
2037 | } |