]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
79e53945 | 33 | #include "drm_crtc_helper.h" |
785b93ef | 34 | #include "drm_fb_helper.h" |
79e53945 | 35 | #include "intel_drv.h" |
1da177e4 LT |
36 | #include "i915_drm.h" |
37 | #include "i915_drv.h" | |
1c5d22f7 | 38 | #include "i915_trace.h" |
63ee41d7 | 39 | #include "../../../platform/x86/intel_ips.h" |
dcdb1674 | 40 | #include <linux/pci.h> |
28d52043 | 41 | #include <linux/vgaarb.h> |
c4804411 ZW |
42 | #include <linux/acpi.h> |
43 | #include <linux/pnp.h> | |
6a9ee8af | 44 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
e0cd3608 | 46 | #include <linux/module.h> |
44834a67 | 47 | #include <acpi/video.h> |
9e984bc1 | 48 | #include <asm/pat.h> |
1da177e4 | 49 | |
4cbf74cc CW |
50 | static void i915_write_hws_pga(struct drm_device *dev) |
51 | { | |
52 | drm_i915_private_t *dev_priv = dev->dev_private; | |
53 | u32 addr; | |
54 | ||
55 | addr = dev_priv->status_page_dmah->busaddr; | |
56 | if (INTEL_INFO(dev)->gen >= 4) | |
57 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
58 | I915_WRITE(HWS_PGA, addr); | |
59 | } | |
60 | ||
398c9cb2 KP |
61 | /** |
62 | * Sets up the hardware status page for devices that need a physical address | |
63 | * in the register. | |
64 | */ | |
3043c60c | 65 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
66 | { |
67 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 68 | |
398c9cb2 KP |
69 | /* Program Hardware Status Page */ |
70 | dev_priv->status_page_dmah = | |
e6be8d9d | 71 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
398c9cb2 KP |
72 | |
73 | if (!dev_priv->status_page_dmah) { | |
74 | DRM_ERROR("Can not allocate hardware status page\n"); | |
75 | return -ENOMEM; | |
76 | } | |
398c9cb2 | 77 | |
f3234706 KP |
78 | memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr, |
79 | 0, PAGE_SIZE); | |
398c9cb2 | 80 | |
4cbf74cc | 81 | i915_write_hws_pga(dev); |
9b974cc1 | 82 | |
8a4c47f3 | 83 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
398c9cb2 KP |
84 | return 0; |
85 | } | |
86 | ||
87 | /** | |
88 | * Frees the hardware status page, whether it's a physical address or a virtual | |
89 | * address set up by the X Server. | |
90 | */ | |
3043c60c | 91 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
92 | { |
93 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 CW |
94 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
95 | ||
398c9cb2 KP |
96 | if (dev_priv->status_page_dmah) { |
97 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
98 | dev_priv->status_page_dmah = NULL; | |
99 | } | |
100 | ||
1ec14ad3 CW |
101 | if (ring->status_page.gfx_addr) { |
102 | ring->status_page.gfx_addr = 0; | |
398c9cb2 KP |
103 | drm_core_ioremapfree(&dev_priv->hws_map, dev); |
104 | } | |
105 | ||
106 | /* Need to rewrite hardware status page */ | |
107 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
108 | } | |
109 | ||
84b1fd10 | 110 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
111 | { |
112 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 113 | struct drm_i915_master_private *master_priv; |
1ec14ad3 | 114 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 115 | |
79e53945 JB |
116 | /* |
117 | * We should never lose context on the ring with modesetting | |
118 | * as we don't expose it to userspace | |
119 | */ | |
120 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
121 | return; | |
122 | ||
8168bd48 CW |
123 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
124 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
1da177e4 LT |
125 | ring->space = ring->head - (ring->tail + 8); |
126 | if (ring->space < 0) | |
8187a2b7 | 127 | ring->space += ring->size; |
1da177e4 | 128 | |
7c1c2871 DA |
129 | if (!dev->primary->master) |
130 | return; | |
131 | ||
132 | master_priv = dev->primary->master->driver_priv; | |
133 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
134 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
135 | } |
136 | ||
84b1fd10 | 137 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 138 | { |
ba8bbcf6 | 139 | drm_i915_private_t *dev_priv = dev->dev_private; |
1ec14ad3 CW |
140 | int i; |
141 | ||
1da177e4 LT |
142 | /* Make sure interrupts are disabled here because the uninstall ioctl |
143 | * may not have been called from userspace and after dev_private | |
144 | * is freed, it's too late. | |
145 | */ | |
ed4cb414 | 146 | if (dev->irq_enabled) |
b5e89ed5 | 147 | drm_irq_uninstall(dev); |
1da177e4 | 148 | |
ee0c6bfb | 149 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 CW |
150 | for (i = 0; i < I915_NUM_RINGS; i++) |
151 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
ee0c6bfb | 152 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 153 | |
398c9cb2 KP |
154 | /* Clear the HWS virtual address at teardown */ |
155 | if (I915_NEED_GFX_HWS(dev)) | |
156 | i915_free_hws(dev); | |
1da177e4 LT |
157 | |
158 | return 0; | |
159 | } | |
160 | ||
ba8bbcf6 | 161 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 162 | { |
ba8bbcf6 | 163 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 164 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
e8616b6c | 165 | int ret; |
1da177e4 | 166 | |
3a03ac1a DA |
167 | master_priv->sarea = drm_getsarea(dev); |
168 | if (master_priv->sarea) { | |
169 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
170 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
171 | } else { | |
8a4c47f3 | 172 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
173 | } |
174 | ||
673a394b | 175 | if (init->ring_size != 0) { |
e8616b6c | 176 | if (LP_RING(dev_priv)->obj != NULL) { |
673a394b EA |
177 | i915_dma_cleanup(dev); |
178 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
179 | "GEM mode\n"); | |
180 | return -EINVAL; | |
181 | } | |
1da177e4 | 182 | |
e8616b6c CW |
183 | ret = intel_render_ring_init_dri(dev, |
184 | init->ring_start, | |
185 | init->ring_size); | |
186 | if (ret) { | |
673a394b | 187 | i915_dma_cleanup(dev); |
e8616b6c | 188 | return ret; |
673a394b | 189 | } |
1da177e4 LT |
190 | } |
191 | ||
a6b54f3f | 192 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
193 | dev_priv->back_offset = init->back_offset; |
194 | dev_priv->front_offset = init->front_offset; | |
195 | dev_priv->current_page = 0; | |
7c1c2871 DA |
196 | if (master_priv->sarea_priv) |
197 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 198 | |
1da177e4 LT |
199 | /* Allow hardware batchbuffers unless told otherwise. |
200 | */ | |
201 | dev_priv->allow_batchbuffer = 1; | |
202 | ||
1da177e4 LT |
203 | return 0; |
204 | } | |
205 | ||
84b1fd10 | 206 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
207 | { |
208 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1ec14ad3 | 209 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 210 | |
8a4c47f3 | 211 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 212 | |
8187a2b7 | 213 | if (ring->map.handle == NULL) { |
1da177e4 LT |
214 | DRM_ERROR("can not ioremap virtual address for" |
215 | " ring buffer\n"); | |
20caafa6 | 216 | return -ENOMEM; |
1da177e4 LT |
217 | } |
218 | ||
219 | /* Program Hardware Status Page */ | |
8187a2b7 | 220 | if (!ring->status_page.page_addr) { |
1da177e4 | 221 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 222 | return -EINVAL; |
1da177e4 | 223 | } |
8a4c47f3 | 224 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
225 | ring->status_page.page_addr); |
226 | if (ring->status_page.gfx_addr != 0) | |
78501eac | 227 | intel_ring_setup_status_page(ring); |
dc7a9319 | 228 | else |
4cbf74cc | 229 | i915_write_hws_pga(dev); |
8187a2b7 | 230 | |
8a4c47f3 | 231 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
232 | |
233 | return 0; | |
234 | } | |
235 | ||
c153f45f EA |
236 | static int i915_dma_init(struct drm_device *dev, void *data, |
237 | struct drm_file *file_priv) | |
1da177e4 | 238 | { |
c153f45f | 239 | drm_i915_init_t *init = data; |
1da177e4 LT |
240 | int retcode = 0; |
241 | ||
c153f45f | 242 | switch (init->func) { |
1da177e4 | 243 | case I915_INIT_DMA: |
ba8bbcf6 | 244 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
245 | break; |
246 | case I915_CLEANUP_DMA: | |
247 | retcode = i915_dma_cleanup(dev); | |
248 | break; | |
249 | case I915_RESUME_DMA: | |
0d6aa60b | 250 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
251 | break; |
252 | default: | |
20caafa6 | 253 | retcode = -EINVAL; |
1da177e4 LT |
254 | break; |
255 | } | |
256 | ||
257 | return retcode; | |
258 | } | |
259 | ||
260 | /* Implement basically the same security restrictions as hardware does | |
261 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
262 | * | |
263 | * Most of the calculations below involve calculating the size of a | |
264 | * particular instruction. It's important to get the size right as | |
265 | * that tells us where the next instruction to check is. Any illegal | |
266 | * instruction detected will be given a size of zero, which is a | |
267 | * signal to abort the rest of the buffer. | |
268 | */ | |
e1f99ce6 | 269 | static int validate_cmd(int cmd) |
1da177e4 LT |
270 | { |
271 | switch (((cmd >> 29) & 0x7)) { | |
272 | case 0x0: | |
273 | switch ((cmd >> 23) & 0x3f) { | |
274 | case 0x0: | |
275 | return 1; /* MI_NOOP */ | |
276 | case 0x4: | |
277 | return 1; /* MI_FLUSH */ | |
278 | default: | |
279 | return 0; /* disallow everything else */ | |
280 | } | |
281 | break; | |
282 | case 0x1: | |
283 | return 0; /* reserved */ | |
284 | case 0x2: | |
285 | return (cmd & 0xff) + 2; /* 2d commands */ | |
286 | case 0x3: | |
287 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
288 | return 1; | |
289 | ||
290 | switch ((cmd >> 24) & 0x1f) { | |
291 | case 0x1c: | |
292 | return 1; | |
293 | case 0x1d: | |
b5e89ed5 | 294 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
295 | case 0x3: |
296 | return (cmd & 0x1f) + 2; | |
297 | case 0x4: | |
298 | return (cmd & 0xf) + 2; | |
299 | default: | |
300 | return (cmd & 0xffff) + 2; | |
301 | } | |
302 | case 0x1e: | |
303 | if (cmd & (1 << 23)) | |
304 | return (cmd & 0xffff) + 1; | |
305 | else | |
306 | return 1; | |
307 | case 0x1f: | |
308 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
309 | return (cmd & 0x1ffff) + 2; | |
310 | else if (cmd & (1 << 17)) /* indirect random */ | |
311 | if ((cmd & 0xffff) == 0) | |
312 | return 0; /* unknown length, too hard */ | |
313 | else | |
314 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
315 | else | |
316 | return 2; /* indirect sequential */ | |
317 | default: | |
318 | return 0; | |
319 | } | |
320 | default: | |
321 | return 0; | |
322 | } | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
201361a5 | 327 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 LT |
328 | { |
329 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e1f99ce6 | 330 | int i, ret; |
1da177e4 | 331 | |
1ec14ad3 | 332 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) |
20caafa6 | 333 | return -EINVAL; |
de227f5f | 334 | |
1da177e4 | 335 | for (i = 0; i < dwords;) { |
e1f99ce6 CW |
336 | int sz = validate_cmd(buffer[i]); |
337 | if (sz == 0 || i + sz > dwords) | |
20caafa6 | 338 | return -EINVAL; |
e1f99ce6 | 339 | i += sz; |
1da177e4 LT |
340 | } |
341 | ||
e1f99ce6 CW |
342 | ret = BEGIN_LP_RING((dwords+1)&~1); |
343 | if (ret) | |
344 | return ret; | |
345 | ||
346 | for (i = 0; i < dwords; i++) | |
347 | OUT_RING(buffer[i]); | |
de227f5f DA |
348 | if (dwords & 1) |
349 | OUT_RING(0); | |
350 | ||
351 | ADVANCE_LP_RING(); | |
352 | ||
1da177e4 LT |
353 | return 0; |
354 | } | |
355 | ||
673a394b EA |
356 | int |
357 | i915_emit_box(struct drm_device *dev, | |
c4e7a414 CW |
358 | struct drm_clip_rect *box, |
359 | int DR1, int DR4) | |
1da177e4 | 360 | { |
e1f99ce6 | 361 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 362 | int ret; |
1da177e4 | 363 | |
c4e7a414 CW |
364 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
365 | box->y2 <= 0 || box->x2 <= 0) { | |
1da177e4 | 366 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
c4e7a414 | 367 | box->x1, box->y1, box->x2, box->y2); |
20caafa6 | 368 | return -EINVAL; |
1da177e4 LT |
369 | } |
370 | ||
a6c45cf0 | 371 | if (INTEL_INFO(dev)->gen >= 4) { |
e1f99ce6 CW |
372 | ret = BEGIN_LP_RING(4); |
373 | if (ret) | |
374 | return ret; | |
375 | ||
c29b669c | 376 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
c4e7a414 CW |
377 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
378 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c | 379 | OUT_RING(DR4); |
c29b669c | 380 | } else { |
e1f99ce6 CW |
381 | ret = BEGIN_LP_RING(6); |
382 | if (ret) | |
383 | return ret; | |
384 | ||
c29b669c AH |
385 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
386 | OUT_RING(DR1); | |
c4e7a414 CW |
387 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
388 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c AH |
389 | OUT_RING(DR4); |
390 | OUT_RING(0); | |
c29b669c | 391 | } |
e1f99ce6 | 392 | ADVANCE_LP_RING(); |
1da177e4 LT |
393 | |
394 | return 0; | |
395 | } | |
396 | ||
c29b669c AH |
397 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
398 | * emit. For now, do it in both places: | |
399 | */ | |
400 | ||
84b1fd10 | 401 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
402 | { |
403 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 404 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 405 | |
c99b058f | 406 | dev_priv->counter++; |
af6061af | 407 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 408 | dev_priv->counter = 0; |
7c1c2871 DA |
409 | if (master_priv->sarea_priv) |
410 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f | 411 | |
e1f99ce6 CW |
412 | if (BEGIN_LP_RING(4) == 0) { |
413 | OUT_RING(MI_STORE_DWORD_INDEX); | |
414 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
415 | OUT_RING(dev_priv->counter); | |
416 | OUT_RING(0); | |
417 | ADVANCE_LP_RING(); | |
418 | } | |
de227f5f DA |
419 | } |
420 | ||
84b1fd10 | 421 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
422 | drm_i915_cmdbuffer_t *cmd, |
423 | struct drm_clip_rect *cliprects, | |
424 | void *cmdbuf) | |
1da177e4 LT |
425 | { |
426 | int nbox = cmd->num_cliprects; | |
427 | int i = 0, count, ret; | |
428 | ||
429 | if (cmd->sz & 0x3) { | |
430 | DRM_ERROR("alignment"); | |
20caafa6 | 431 | return -EINVAL; |
1da177e4 LT |
432 | } |
433 | ||
434 | i915_kernel_lost_context(dev); | |
435 | ||
436 | count = nbox ? nbox : 1; | |
437 | ||
438 | for (i = 0; i < count; i++) { | |
439 | if (i < nbox) { | |
c4e7a414 | 440 | ret = i915_emit_box(dev, &cliprects[i], |
1da177e4 LT |
441 | cmd->DR1, cmd->DR4); |
442 | if (ret) | |
443 | return ret; | |
444 | } | |
445 | ||
201361a5 | 446 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
447 | if (ret) |
448 | return ret; | |
449 | } | |
450 | ||
de227f5f | 451 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
452 | return 0; |
453 | } | |
454 | ||
84b1fd10 | 455 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
456 | drm_i915_batchbuffer_t * batch, |
457 | struct drm_clip_rect *cliprects) | |
1da177e4 | 458 | { |
e1f99ce6 | 459 | struct drm_i915_private *dev_priv = dev->dev_private; |
1da177e4 | 460 | int nbox = batch->num_cliprects; |
e1f99ce6 | 461 | int i, count, ret; |
1da177e4 LT |
462 | |
463 | if ((batch->start | batch->used) & 0x7) { | |
464 | DRM_ERROR("alignment"); | |
20caafa6 | 465 | return -EINVAL; |
1da177e4 LT |
466 | } |
467 | ||
468 | i915_kernel_lost_context(dev); | |
469 | ||
470 | count = nbox ? nbox : 1; | |
1da177e4 LT |
471 | for (i = 0; i < count; i++) { |
472 | if (i < nbox) { | |
c4e7a414 | 473 | ret = i915_emit_box(dev, &cliprects[i], |
e1f99ce6 | 474 | batch->DR1, batch->DR4); |
1da177e4 LT |
475 | if (ret) |
476 | return ret; | |
477 | } | |
478 | ||
0790d5e1 | 479 | if (!IS_I830(dev) && !IS_845G(dev)) { |
e1f99ce6 CW |
480 | ret = BEGIN_LP_RING(2); |
481 | if (ret) | |
482 | return ret; | |
483 | ||
a6c45cf0 | 484 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
485 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
486 | OUT_RING(batch->start); | |
487 | } else { | |
488 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
489 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
490 | } | |
1da177e4 | 491 | } else { |
e1f99ce6 CW |
492 | ret = BEGIN_LP_RING(4); |
493 | if (ret) | |
494 | return ret; | |
495 | ||
1da177e4 LT |
496 | OUT_RING(MI_BATCH_BUFFER); |
497 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
498 | OUT_RING(batch->start + batch->used - 4); | |
499 | OUT_RING(0); | |
1da177e4 | 500 | } |
e1f99ce6 | 501 | ADVANCE_LP_RING(); |
1da177e4 LT |
502 | } |
503 | ||
1cafd347 | 504 | |
f00a3ddf | 505 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
506 | if (BEGIN_LP_RING(2) == 0) { |
507 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
508 | OUT_RING(MI_NOOP); | |
509 | ADVANCE_LP_RING(); | |
510 | } | |
1cafd347 | 511 | } |
1da177e4 | 512 | |
e1f99ce6 | 513 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
514 | return 0; |
515 | } | |
516 | ||
af6061af | 517 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
518 | { |
519 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
520 | struct drm_i915_master_private *master_priv = |
521 | dev->primary->master->driver_priv; | |
e1f99ce6 | 522 | int ret; |
1da177e4 | 523 | |
7c1c2871 | 524 | if (!master_priv->sarea_priv) |
c99b058f KH |
525 | return -EINVAL; |
526 | ||
8a4c47f3 | 527 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 528 | __func__, |
529 | dev_priv->current_page, | |
530 | master_priv->sarea_priv->pf_current_page); | |
1da177e4 | 531 | |
af6061af DA |
532 | i915_kernel_lost_context(dev); |
533 | ||
e1f99ce6 CW |
534 | ret = BEGIN_LP_RING(10); |
535 | if (ret) | |
536 | return ret; | |
537 | ||
585fb111 | 538 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af | 539 | OUT_RING(0); |
1da177e4 | 540 | |
af6061af DA |
541 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
542 | OUT_RING(0); | |
543 | if (dev_priv->current_page == 0) { | |
544 | OUT_RING(dev_priv->back_offset); | |
545 | dev_priv->current_page = 1; | |
1da177e4 | 546 | } else { |
af6061af DA |
547 | OUT_RING(dev_priv->front_offset); |
548 | dev_priv->current_page = 0; | |
1da177e4 | 549 | } |
af6061af | 550 | OUT_RING(0); |
1da177e4 | 551 | |
af6061af DA |
552 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
553 | OUT_RING(0); | |
e1f99ce6 | 554 | |
af6061af | 555 | ADVANCE_LP_RING(); |
1da177e4 | 556 | |
7c1c2871 | 557 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 | 558 | |
e1f99ce6 CW |
559 | if (BEGIN_LP_RING(4) == 0) { |
560 | OUT_RING(MI_STORE_DWORD_INDEX); | |
561 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
562 | OUT_RING(dev_priv->counter); | |
563 | OUT_RING(0); | |
564 | ADVANCE_LP_RING(); | |
565 | } | |
1da177e4 | 566 | |
7c1c2871 | 567 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
af6061af | 568 | return 0; |
1da177e4 LT |
569 | } |
570 | ||
1ec14ad3 | 571 | static int i915_quiescent(struct drm_device *dev) |
1da177e4 | 572 | { |
1ec14ad3 | 573 | struct intel_ring_buffer *ring = LP_RING(dev->dev_private); |
1da177e4 LT |
574 | |
575 | i915_kernel_lost_context(dev); | |
96f298aa | 576 | return intel_wait_ring_idle(ring); |
1da177e4 LT |
577 | } |
578 | ||
c153f45f EA |
579 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
580 | struct drm_file *file_priv) | |
1da177e4 | 581 | { |
546b0974 EA |
582 | int ret; |
583 | ||
584 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1da177e4 | 585 | |
546b0974 EA |
586 | mutex_lock(&dev->struct_mutex); |
587 | ret = i915_quiescent(dev); | |
588 | mutex_unlock(&dev->struct_mutex); | |
589 | ||
590 | return ret; | |
1da177e4 LT |
591 | } |
592 | ||
c153f45f EA |
593 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
594 | struct drm_file *file_priv) | |
1da177e4 | 595 | { |
1da177e4 | 596 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 597 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 598 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 599 | master_priv->sarea_priv; |
c153f45f | 600 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 601 | int ret; |
201361a5 | 602 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 LT |
603 | |
604 | if (!dev_priv->allow_batchbuffer) { | |
605 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 606 | return -EINVAL; |
1da177e4 LT |
607 | } |
608 | ||
8a4c47f3 | 609 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 610 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 611 | |
546b0974 | 612 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 613 | |
201361a5 EA |
614 | if (batch->num_cliprects < 0) |
615 | return -EINVAL; | |
616 | ||
617 | if (batch->num_cliprects) { | |
9a298b2a EA |
618 | cliprects = kcalloc(batch->num_cliprects, |
619 | sizeof(struct drm_clip_rect), | |
620 | GFP_KERNEL); | |
201361a5 EA |
621 | if (cliprects == NULL) |
622 | return -ENOMEM; | |
623 | ||
624 | ret = copy_from_user(cliprects, batch->cliprects, | |
625 | batch->num_cliprects * | |
626 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
627 | if (ret != 0) { |
628 | ret = -EFAULT; | |
201361a5 | 629 | goto fail_free; |
9927a403 | 630 | } |
201361a5 | 631 | } |
1da177e4 | 632 | |
546b0974 | 633 | mutex_lock(&dev->struct_mutex); |
201361a5 | 634 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 635 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 636 | |
c99b058f | 637 | if (sarea_priv) |
0baf823a | 638 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
639 | |
640 | fail_free: | |
9a298b2a | 641 | kfree(cliprects); |
201361a5 | 642 | |
1da177e4 LT |
643 | return ret; |
644 | } | |
645 | ||
c153f45f EA |
646 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
647 | struct drm_file *file_priv) | |
1da177e4 | 648 | { |
1da177e4 | 649 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 650 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 651 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 652 | master_priv->sarea_priv; |
c153f45f | 653 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
654 | struct drm_clip_rect *cliprects = NULL; |
655 | void *batch_data; | |
1da177e4 LT |
656 | int ret; |
657 | ||
8a4c47f3 | 658 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 659 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 660 | |
546b0974 | 661 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 662 | |
201361a5 EA |
663 | if (cmdbuf->num_cliprects < 0) |
664 | return -EINVAL; | |
665 | ||
9a298b2a | 666 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
667 | if (batch_data == NULL) |
668 | return -ENOMEM; | |
669 | ||
670 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
671 | if (ret != 0) { |
672 | ret = -EFAULT; | |
201361a5 | 673 | goto fail_batch_free; |
9927a403 | 674 | } |
201361a5 EA |
675 | |
676 | if (cmdbuf->num_cliprects) { | |
9a298b2a EA |
677 | cliprects = kcalloc(cmdbuf->num_cliprects, |
678 | sizeof(struct drm_clip_rect), GFP_KERNEL); | |
a40e8d31 OA |
679 | if (cliprects == NULL) { |
680 | ret = -ENOMEM; | |
201361a5 | 681 | goto fail_batch_free; |
a40e8d31 | 682 | } |
201361a5 EA |
683 | |
684 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
685 | cmdbuf->num_cliprects * | |
686 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
687 | if (ret != 0) { |
688 | ret = -EFAULT; | |
201361a5 | 689 | goto fail_clip_free; |
9927a403 | 690 | } |
1da177e4 LT |
691 | } |
692 | ||
546b0974 | 693 | mutex_lock(&dev->struct_mutex); |
201361a5 | 694 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 695 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
696 | if (ret) { |
697 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 698 | goto fail_clip_free; |
1da177e4 LT |
699 | } |
700 | ||
c99b058f | 701 | if (sarea_priv) |
0baf823a | 702 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 703 | |
201361a5 | 704 | fail_clip_free: |
9a298b2a | 705 | kfree(cliprects); |
355d7f37 | 706 | fail_batch_free: |
9a298b2a | 707 | kfree(batch_data); |
201361a5 EA |
708 | |
709 | return ret; | |
1da177e4 LT |
710 | } |
711 | ||
c153f45f EA |
712 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
713 | struct drm_file *file_priv) | |
1da177e4 | 714 | { |
546b0974 EA |
715 | int ret; |
716 | ||
8a4c47f3 | 717 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 718 | |
546b0974 | 719 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 720 | |
546b0974 EA |
721 | mutex_lock(&dev->struct_mutex); |
722 | ret = i915_dispatch_flip(dev); | |
723 | mutex_unlock(&dev->struct_mutex); | |
724 | ||
725 | return ret; | |
1da177e4 LT |
726 | } |
727 | ||
c153f45f EA |
728 | static int i915_getparam(struct drm_device *dev, void *data, |
729 | struct drm_file *file_priv) | |
1da177e4 | 730 | { |
1da177e4 | 731 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 732 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
733 | int value; |
734 | ||
735 | if (!dev_priv) { | |
3e684eae | 736 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 737 | return -EINVAL; |
1da177e4 LT |
738 | } |
739 | ||
c153f45f | 740 | switch (param->param) { |
1da177e4 | 741 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 742 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
743 | break; |
744 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
745 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
746 | break; | |
0d6aa60b DA |
747 | case I915_PARAM_LAST_DISPATCH: |
748 | value = READ_BREADCRUMB(dev_priv); | |
749 | break; | |
ed4c9c4a KH |
750 | case I915_PARAM_CHIPSET_ID: |
751 | value = dev->pci_device; | |
752 | break; | |
673a394b | 753 | case I915_PARAM_HAS_GEM: |
ac5c4e76 | 754 | value = dev_priv->has_gem; |
673a394b | 755 | break; |
0f973f27 JB |
756 | case I915_PARAM_NUM_FENCES_AVAIL: |
757 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
758 | break; | |
02e792fb DV |
759 | case I915_PARAM_HAS_OVERLAY: |
760 | value = dev_priv->overlay ? 1 : 0; | |
761 | break; | |
e9560f7c JB |
762 | case I915_PARAM_HAS_PAGEFLIPPING: |
763 | value = 1; | |
764 | break; | |
76446cac JB |
765 | case I915_PARAM_HAS_EXECBUF2: |
766 | /* depends on GEM */ | |
767 | value = dev_priv->has_gem; | |
768 | break; | |
e3a815fc ZN |
769 | case I915_PARAM_HAS_BSD: |
770 | value = HAS_BSD(dev); | |
771 | break; | |
549f7365 CW |
772 | case I915_PARAM_HAS_BLT: |
773 | value = HAS_BLT(dev); | |
774 | break; | |
a00b10c3 CW |
775 | case I915_PARAM_HAS_RELAXED_FENCING: |
776 | value = 1; | |
777 | break; | |
bbf0c6b3 DV |
778 | case I915_PARAM_HAS_COHERENT_RINGS: |
779 | value = 1; | |
780 | break; | |
72bfa19c CW |
781 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
782 | value = INTEL_INFO(dev)->gen >= 4; | |
783 | break; | |
271d81b8 CW |
784 | case I915_PARAM_HAS_RELAXED_DELTA: |
785 | value = 1; | |
786 | break; | |
ae662d31 EA |
787 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
788 | value = 1; | |
789 | break; | |
3d29b842 ED |
790 | case I915_PARAM_HAS_LLC: |
791 | value = HAS_LLC(dev); | |
792 | break; | |
777ee96f DV |
793 | case I915_PARAM_HAS_ALIASING_PPGTT: |
794 | value = dev_priv->mm.aliasing_ppgtt ? 1 : 0; | |
795 | break; | |
1da177e4 | 796 | default: |
8a4c47f3 | 797 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
76446cac | 798 | param->param); |
20caafa6 | 799 | return -EINVAL; |
1da177e4 LT |
800 | } |
801 | ||
c153f45f | 802 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 803 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 804 | return -EFAULT; |
1da177e4 LT |
805 | } |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
c153f45f EA |
810 | static int i915_setparam(struct drm_device *dev, void *data, |
811 | struct drm_file *file_priv) | |
1da177e4 | 812 | { |
1da177e4 | 813 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 814 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
815 | |
816 | if (!dev_priv) { | |
3e684eae | 817 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 818 | return -EINVAL; |
1da177e4 LT |
819 | } |
820 | ||
c153f45f | 821 | switch (param->param) { |
1da177e4 | 822 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
823 | break; |
824 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 825 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
826 | break; |
827 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 828 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 | 829 | break; |
0f973f27 JB |
830 | case I915_SETPARAM_NUM_USED_FENCES: |
831 | if (param->value > dev_priv->num_fence_regs || | |
832 | param->value < 0) | |
833 | return -EINVAL; | |
834 | /* Userspace can use first N regs */ | |
835 | dev_priv->fence_reg_start = param->value; | |
836 | break; | |
1da177e4 | 837 | default: |
8a4c47f3 | 838 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 839 | param->param); |
20caafa6 | 840 | return -EINVAL; |
1da177e4 LT |
841 | } |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
c153f45f EA |
846 | static int i915_set_status_page(struct drm_device *dev, void *data, |
847 | struct drm_file *file_priv) | |
dc7a9319 | 848 | { |
dc7a9319 | 849 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 850 | drm_i915_hws_addr_t *hws = data; |
1ec14ad3 | 851 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
b39d50e5 ZW |
852 | |
853 | if (!I915_NEED_GFX_HWS(dev)) | |
854 | return -EINVAL; | |
dc7a9319 WZ |
855 | |
856 | if (!dev_priv) { | |
3e684eae | 857 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 858 | return -EINVAL; |
dc7a9319 | 859 | } |
dc7a9319 | 860 | |
79e53945 JB |
861 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
862 | WARN(1, "tried to set status page when mode setting active\n"); | |
863 | return 0; | |
864 | } | |
865 | ||
8a4c47f3 | 866 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 867 | |
8187a2b7 | 868 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 869 | |
8b409580 | 870 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
871 | dev_priv->hws_map.size = 4*1024; |
872 | dev_priv->hws_map.type = 0; | |
873 | dev_priv->hws_map.flags = 0; | |
874 | dev_priv->hws_map.mtrr = 0; | |
875 | ||
dd0910b3 | 876 | drm_core_ioremap_wc(&dev_priv->hws_map, dev); |
dc7a9319 | 877 | if (dev_priv->hws_map.handle == NULL) { |
dc7a9319 | 878 | i915_dma_cleanup(dev); |
e20f9c64 | 879 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
880 | DRM_ERROR("can not ioremap virtual address for" |
881 | " G33 hw status page\n"); | |
20caafa6 | 882 | return -ENOMEM; |
dc7a9319 | 883 | } |
311bd68e CW |
884 | ring->status_page.page_addr = |
885 | (void __force __iomem *)dev_priv->hws_map.handle; | |
886 | memset_io(ring->status_page.page_addr, 0, PAGE_SIZE); | |
8187a2b7 | 887 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
dc7a9319 | 888 | |
8a4c47f3 | 889 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 890 | ring->status_page.gfx_addr); |
8a4c47f3 | 891 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 892 | ring->status_page.page_addr); |
dc7a9319 WZ |
893 | return 0; |
894 | } | |
895 | ||
ec2a4c3f DA |
896 | static int i915_get_bridge_dev(struct drm_device *dev) |
897 | { | |
898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
899 | ||
0206e353 | 900 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
901 | if (!dev_priv->bridge_dev) { |
902 | DRM_ERROR("bridge device not found\n"); | |
903 | return -1; | |
904 | } | |
905 | return 0; | |
906 | } | |
907 | ||
c4804411 ZW |
908 | #define MCHBAR_I915 0x44 |
909 | #define MCHBAR_I965 0x48 | |
910 | #define MCHBAR_SIZE (4*4096) | |
911 | ||
912 | #define DEVEN_REG 0x54 | |
913 | #define DEVEN_MCHBAR_EN (1 << 28) | |
914 | ||
915 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
916 | static int | |
917 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
918 | { | |
919 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 920 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
921 | u32 temp_lo, temp_hi = 0; |
922 | u64 mchbar_addr; | |
a25c25c2 | 923 | int ret; |
c4804411 | 924 | |
a6c45cf0 | 925 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
926 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
927 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
928 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
929 | ||
930 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
931 | #ifdef CONFIG_PNP | |
932 | if (mchbar_addr && | |
a25c25c2 CW |
933 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
934 | return 0; | |
c4804411 ZW |
935 | #endif |
936 | ||
937 | /* Get some space for it */ | |
a25c25c2 CW |
938 | dev_priv->mch_res.name = "i915 MCHBAR"; |
939 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
940 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
941 | &dev_priv->mch_res, | |
c4804411 ZW |
942 | MCHBAR_SIZE, MCHBAR_SIZE, |
943 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 944 | 0, pcibios_align_resource, |
c4804411 ZW |
945 | dev_priv->bridge_dev); |
946 | if (ret) { | |
947 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
948 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 949 | return ret; |
c4804411 ZW |
950 | } |
951 | ||
a6c45cf0 | 952 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
953 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
954 | upper_32_bits(dev_priv->mch_res.start)); | |
955 | ||
956 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
957 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 958 | return 0; |
c4804411 ZW |
959 | } |
960 | ||
961 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
962 | static void | |
963 | intel_setup_mchbar(struct drm_device *dev) | |
964 | { | |
965 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 966 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
967 | u32 temp; |
968 | bool enabled; | |
969 | ||
970 | dev_priv->mchbar_need_disable = false; | |
971 | ||
972 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
973 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
974 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
975 | } else { | |
976 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
977 | enabled = temp & 1; | |
978 | } | |
979 | ||
980 | /* If it's already enabled, don't have to do anything */ | |
981 | if (enabled) | |
982 | return; | |
983 | ||
984 | if (intel_alloc_mchbar_resource(dev)) | |
985 | return; | |
986 | ||
987 | dev_priv->mchbar_need_disable = true; | |
988 | ||
989 | /* Space is allocated or reserved, so enable it. */ | |
990 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
991 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
992 | temp | DEVEN_MCHBAR_EN); | |
993 | } else { | |
994 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
995 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
996 | } | |
997 | } | |
998 | ||
999 | static void | |
1000 | intel_teardown_mchbar(struct drm_device *dev) | |
1001 | { | |
1002 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1003 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1004 | u32 temp; |
1005 | ||
1006 | if (dev_priv->mchbar_need_disable) { | |
1007 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1008 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1009 | temp &= ~DEVEN_MCHBAR_EN; | |
1010 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1011 | } else { | |
1012 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1013 | temp &= ~1; | |
1014 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | if (dev_priv->mch_res.start) | |
1019 | release_resource(&dev_priv->mch_res); | |
1020 | } | |
1021 | ||
80824003 JB |
1022 | #define PTE_ADDRESS_MASK 0xfffff000 |
1023 | #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ | |
1024 | #define PTE_MAPPING_TYPE_UNCACHED (0 << 1) | |
1025 | #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ | |
1026 | #define PTE_MAPPING_TYPE_CACHED (3 << 1) | |
1027 | #define PTE_MAPPING_TYPE_MASK (3 << 1) | |
1028 | #define PTE_VALID (1 << 0) | |
1029 | ||
1030 | /** | |
fe669bf8 CW |
1031 | * i915_stolen_to_phys - take an offset into stolen memory and turn it into |
1032 | * a physical one | |
80824003 | 1033 | * @dev: drm device |
fe669bf8 | 1034 | * @offset: address to translate |
80824003 | 1035 | * |
fe669bf8 CW |
1036 | * Some chip functions require allocations from stolen space and need the |
1037 | * physical address of the memory in question. | |
80824003 | 1038 | */ |
fe669bf8 | 1039 | static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset) |
80824003 | 1040 | { |
fe669bf8 CW |
1041 | struct drm_i915_private *dev_priv = dev->dev_private; |
1042 | struct pci_dev *pdev = dev_priv->bridge_dev; | |
1043 | u32 base; | |
1044 | ||
1045 | #if 0 | |
1046 | /* On the machines I have tested the Graphics Base of Stolen Memory | |
1047 | * is unreliable, so compute the base by subtracting the stolen memory | |
1048 | * from the Top of Low Usable DRAM which is where the BIOS places | |
1049 | * the graphics stolen memory. | |
1050 | */ | |
1051 | if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) { | |
1052 | /* top 32bits are reserved = 0 */ | |
1053 | pci_read_config_dword(pdev, 0xA4, &base); | |
80824003 | 1054 | } else { |
fe669bf8 CW |
1055 | /* XXX presume 8xx is the same as i915 */ |
1056 | pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base); | |
1057 | } | |
1058 | #else | |
1059 | if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) { | |
1060 | u16 val; | |
1061 | pci_read_config_word(pdev, 0xb0, &val); | |
1062 | base = val >> 4 << 20; | |
1063 | } else { | |
1064 | u8 val; | |
1065 | pci_read_config_byte(pdev, 0x9c, &val); | |
1066 | base = val >> 3 << 27; | |
80824003 | 1067 | } |
c64f7ba5 | 1068 | base -= dev_priv->mm.gtt->stolen_size; |
fe669bf8 | 1069 | #endif |
80824003 | 1070 | |
fe669bf8 | 1071 | return base + offset; |
80824003 JB |
1072 | } |
1073 | ||
1074 | static void i915_warn_stolen(struct drm_device *dev) | |
1075 | { | |
1076 | DRM_ERROR("not enough stolen space for compressed buffer, disabling\n"); | |
1077 | DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); | |
1078 | } | |
1079 | ||
1080 | static void i915_setup_compression(struct drm_device *dev, int size) | |
1081 | { | |
1082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
132b6aab | 1083 | struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb); |
29bd0ae2 AM |
1084 | unsigned long cfb_base; |
1085 | unsigned long ll_base = 0; | |
80824003 | 1086 | |
43a9539f CW |
1087 | /* Just in case the BIOS is doing something questionable. */ |
1088 | intel_disable_fbc(dev); | |
1089 | ||
fe669bf8 CW |
1090 | compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0); |
1091 | if (compressed_fb) | |
1092 | compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); | |
1093 | if (!compressed_fb) | |
1094 | goto err; | |
80824003 | 1095 | |
fe669bf8 CW |
1096 | cfb_base = i915_stolen_to_phys(dev, compressed_fb->start); |
1097 | if (!cfb_base) | |
1098 | goto err_fb; | |
80824003 | 1099 | |
9c04f015 | 1100 | if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) { |
fe669bf8 CW |
1101 | compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen, |
1102 | 4096, 4096, 0); | |
1103 | if (compressed_llb) | |
1104 | compressed_llb = drm_mm_get_block(compressed_llb, | |
1105 | 4096, 4096); | |
1106 | if (!compressed_llb) | |
1107 | goto err_fb; | |
74dff282 | 1108 | |
fe669bf8 CW |
1109 | ll_base = i915_stolen_to_phys(dev, compressed_llb->start); |
1110 | if (!ll_base) | |
1111 | goto err_llb; | |
80824003 JB |
1112 | } |
1113 | ||
1114 | dev_priv->cfb_size = size; | |
1115 | ||
20bf377e | 1116 | dev_priv->compressed_fb = compressed_fb; |
9c04f015 | 1117 | if (HAS_PCH_SPLIT(dev)) |
b52eb4dc ZY |
1118 | I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start); |
1119 | else if (IS_GM45(dev)) { | |
74dff282 JB |
1120 | I915_WRITE(DPFC_CB_BASE, compressed_fb->start); |
1121 | } else { | |
74dff282 JB |
1122 | I915_WRITE(FBC_CFB_BASE, cfb_base); |
1123 | I915_WRITE(FBC_LL_BASE, ll_base); | |
20bf377e | 1124 | dev_priv->compressed_llb = compressed_llb; |
80824003 JB |
1125 | } |
1126 | ||
fe669bf8 CW |
1127 | DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", |
1128 | cfb_base, ll_base, size >> 20); | |
1129 | return; | |
1130 | ||
1131 | err_llb: | |
1132 | drm_mm_put_block(compressed_llb); | |
1133 | err_fb: | |
1134 | drm_mm_put_block(compressed_fb); | |
1135 | err: | |
1136 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; | |
1137 | i915_warn_stolen(dev); | |
80824003 JB |
1138 | } |
1139 | ||
20bf377e JB |
1140 | static void i915_cleanup_compression(struct drm_device *dev) |
1141 | { | |
1142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1143 | ||
1144 | drm_mm_put_block(dev_priv->compressed_fb); | |
aebf0daf | 1145 | if (dev_priv->compressed_llb) |
20bf377e JB |
1146 | drm_mm_put_block(dev_priv->compressed_llb); |
1147 | } | |
1148 | ||
28d52043 DA |
1149 | /* true = enable decode, false = disable decoder */ |
1150 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1151 | { | |
1152 | struct drm_device *dev = cookie; | |
1153 | ||
1154 | intel_modeset_vga_set_state(dev, state); | |
1155 | if (state) | |
1156 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1157 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1158 | else | |
1159 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1160 | } | |
1161 | ||
6a9ee8af DA |
1162 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1163 | { | |
1164 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1165 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1166 | if (state == VGA_SWITCHEROO_ON) { | |
a70491cc | 1167 | pr_info("switched on\n"); |
5bcf719b | 1168 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
1169 | /* i915 resume handler doesn't set to D0 */ |
1170 | pci_set_power_state(dev->pdev, PCI_D0); | |
1171 | i915_resume(dev); | |
5bcf719b | 1172 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 1173 | } else { |
a70491cc | 1174 | pr_err("switched off\n"); |
5bcf719b | 1175 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 1176 | i915_suspend(dev, pmm); |
5bcf719b | 1177 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1178 | } |
1179 | } | |
1180 | ||
1181 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1182 | { | |
1183 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1184 | bool can_switch; | |
1185 | ||
1186 | spin_lock(&dev->count_lock); | |
1187 | can_switch = (dev->open_count == 0); | |
1188 | spin_unlock(&dev->count_lock); | |
1189 | return can_switch; | |
1190 | } | |
1191 | ||
650dc07e DV |
1192 | static bool |
1193 | intel_enable_ppgtt(struct drm_device *dev) | |
1194 | { | |
1195 | if (i915_enable_ppgtt >= 0) | |
1196 | return i915_enable_ppgtt; | |
1197 | ||
1198 | #ifdef CONFIG_INTEL_IOMMU | |
1199 | /* Disable ppgtt on SNB if VT-d is on. */ | |
1200 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
1201 | return false; | |
1202 | #endif | |
1203 | ||
1204 | return true; | |
1205 | } | |
1206 | ||
2c7111db | 1207 | static int i915_load_gem_init(struct drm_device *dev) |
79e53945 JB |
1208 | { |
1209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
53984635 | 1210 | unsigned long prealloc_size, gtt_size, mappable_size; |
2c7111db | 1211 | int ret; |
79e53945 | 1212 | |
c64f7ba5 | 1213 | prealloc_size = dev_priv->mm.gtt->stolen_size; |
53984635 DV |
1214 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; |
1215 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
53984635 | 1216 | |
fe669bf8 CW |
1217 | /* Basic memrange allocator for stolen space */ |
1218 | drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size); | |
79e53945 | 1219 | |
d3ae0810 | 1220 | mutex_lock(&dev->struct_mutex); |
650dc07e | 1221 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { |
1d2a314c DV |
1222 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the |
1223 | * aperture accordingly when using aliasing ppgtt. */ | |
1224 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
1d2a314c | 1225 | |
644ec02b | 1226 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); |
1d2a314c DV |
1227 | |
1228 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e02f14cd DV |
1229 | if (ret) { |
1230 | mutex_unlock(&dev->struct_mutex); | |
1d2a314c | 1231 | return ret; |
e02f14cd | 1232 | } |
1d2a314c DV |
1233 | } else { |
1234 | /* Let GEM Manage all of the aperture. | |
1235 | * | |
1236 | * However, leave one page at the end still bound to the scratch | |
1237 | * page. There are a number of places where the hardware | |
1238 | * apparently prefetches past the end of the object, and we've | |
1239 | * seen multiple hangs with the GPU head pointer stuck in a | |
1240 | * batchbuffer bound at the last page of the aperture. One page | |
1241 | * should be enough to keep any prefetching inside of the | |
1242 | * aperture. | |
1243 | */ | |
644ec02b | 1244 | i915_gem_init_global_gtt(dev, 0, mappable_size, |
d1dd20a9 | 1245 | gtt_size); |
1d2a314c | 1246 | } |
79e53945 | 1247 | |
f691e2f4 | 1248 | ret = i915_gem_init_hw(dev); |
11ed50ec | 1249 | mutex_unlock(&dev->struct_mutex); |
1d2a314c DV |
1250 | if (ret) { |
1251 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
2c7111db | 1252 | return ret; |
1d2a314c | 1253 | } |
79e53945 | 1254 | |
80824003 | 1255 | /* Try to set up FBC with a reasonable compressed buffer size */ |
9216d44d | 1256 | if (I915_HAS_FBC(dev) && i915_powersave) { |
80824003 JB |
1257 | int cfb_size; |
1258 | ||
fe669bf8 CW |
1259 | /* Leave 1M for line length buffer & misc. */ |
1260 | ||
1261 | /* Try to get a 32M buffer... */ | |
1262 | if (prealloc_size > (36*1024*1024)) | |
1263 | cfb_size = 32*1024*1024; | |
80824003 JB |
1264 | else /* fall back to 7/8 of the stolen space */ |
1265 | cfb_size = prealloc_size * 7 / 8; | |
1266 | i915_setup_compression(dev, cfb_size); | |
1267 | } | |
1268 | ||
fe669bf8 | 1269 | /* Allow hardware batchbuffers unless told otherwise. */ |
79e53945 | 1270 | dev_priv->allow_batchbuffer = 1; |
2c7111db CW |
1271 | return 0; |
1272 | } | |
1273 | ||
1274 | static int i915_load_modeset_init(struct drm_device *dev) | |
1275 | { | |
1276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1277 | int ret; | |
79e53945 | 1278 | |
6d139a87 | 1279 | ret = intel_parse_bios(dev); |
79e53945 JB |
1280 | if (ret) |
1281 | DRM_INFO("failed to find VBIOS tables\n"); | |
1282 | ||
934f992c CW |
1283 | /* If we have > 1 VGA cards, then we need to arbitrate access |
1284 | * to the common VGA resources. | |
1285 | * | |
1286 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
1287 | * then we do not take part in VGA arbitration and the | |
1288 | * vga_client_register() fails with -ENODEV. | |
1289 | */ | |
28d52043 | 1290 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
934f992c | 1291 | if (ret && ret != -ENODEV) |
2c7111db | 1292 | goto out; |
28d52043 | 1293 | |
723bfd70 JB |
1294 | intel_register_dsm_handler(); |
1295 | ||
6a9ee8af DA |
1296 | ret = vga_switcheroo_register_client(dev->pdev, |
1297 | i915_switcheroo_set_state, | |
8d608aa6 | 1298 | NULL, |
6a9ee8af DA |
1299 | i915_switcheroo_can_switch); |
1300 | if (ret) | |
5a79395b | 1301 | goto cleanup_vga_client; |
6a9ee8af | 1302 | |
1afe3e9d JB |
1303 | /* IIR "flip pending" bit means done if this bit is set */ |
1304 | if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE)) | |
1305 | dev_priv->flip_pending_is_done = true; | |
1306 | ||
b01f2c3a JB |
1307 | intel_modeset_init(dev); |
1308 | ||
2c7111db | 1309 | ret = i915_load_gem_init(dev); |
79e53945 | 1310 | if (ret) |
5a79395b | 1311 | goto cleanup_vga_switcheroo; |
79e53945 | 1312 | |
2c7111db CW |
1313 | intel_modeset_gem_init(dev); |
1314 | ||
1315 | ret = drm_irq_install(dev); | |
1316 | if (ret) | |
1317 | goto cleanup_gem; | |
1318 | ||
79e53945 JB |
1319 | /* Always safe in the mode setting case. */ |
1320 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
1321 | dev->vblank_disable_allowed = 1; | |
1322 | ||
5a79395b CW |
1323 | ret = intel_fbdev_init(dev); |
1324 | if (ret) | |
1325 | goto cleanup_irq; | |
1326 | ||
eb1f8e4f | 1327 | drm_kms_helper_poll_init(dev); |
87acb0a5 CW |
1328 | |
1329 | /* We're off and running w/KMS */ | |
1330 | dev_priv->mm.suspended = 0; | |
1331 | ||
79e53945 JB |
1332 | return 0; |
1333 | ||
5a79395b CW |
1334 | cleanup_irq: |
1335 | drm_irq_uninstall(dev); | |
2c7111db CW |
1336 | cleanup_gem: |
1337 | mutex_lock(&dev->struct_mutex); | |
1338 | i915_gem_cleanup_ringbuffer(dev); | |
1339 | mutex_unlock(&dev->struct_mutex); | |
1d2a314c | 1340 | i915_gem_cleanup_aliasing_ppgtt(dev); |
5a79395b CW |
1341 | cleanup_vga_switcheroo: |
1342 | vga_switcheroo_unregister_client(dev->pdev); | |
1343 | cleanup_vga_client: | |
1344 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
1345 | out: |
1346 | return ret; | |
1347 | } | |
1348 | ||
7c1c2871 DA |
1349 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1350 | { | |
1351 | struct drm_i915_master_private *master_priv; | |
1352 | ||
9a298b2a | 1353 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1354 | if (!master_priv) |
1355 | return -ENOMEM; | |
1356 | ||
1357 | master->driver_priv = master_priv; | |
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1362 | { | |
1363 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1364 | ||
1365 | if (!master_priv) | |
1366 | return; | |
1367 | ||
9a298b2a | 1368 | kfree(master_priv); |
7c1c2871 DA |
1369 | |
1370 | master->driver_priv = NULL; | |
1371 | } | |
1372 | ||
7648fa99 | 1373 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
7662c8bd SL |
1374 | { |
1375 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1376 | u32 tmp; | |
1377 | ||
7662c8bd SL |
1378 | tmp = I915_READ(CLKCFG); |
1379 | ||
1380 | switch (tmp & CLKCFG_FSB_MASK) { | |
1381 | case CLKCFG_FSB_533: | |
1382 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
1383 | break; | |
1384 | case CLKCFG_FSB_800: | |
1385 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
1386 | break; | |
1387 | case CLKCFG_FSB_667: | |
1388 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
1389 | break; | |
1390 | case CLKCFG_FSB_400: | |
1391 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
1392 | break; | |
1393 | } | |
1394 | ||
1395 | switch (tmp & CLKCFG_MEM_MASK) { | |
1396 | case CLKCFG_MEM_533: | |
1397 | dev_priv->mem_freq = 533; | |
1398 | break; | |
1399 | case CLKCFG_MEM_667: | |
1400 | dev_priv->mem_freq = 667; | |
1401 | break; | |
1402 | case CLKCFG_MEM_800: | |
1403 | dev_priv->mem_freq = 800; | |
1404 | break; | |
1405 | } | |
95534263 LP |
1406 | |
1407 | /* detect pineview DDR3 setting */ | |
1408 | tmp = I915_READ(CSHRDDR3CTL); | |
1409 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
7662c8bd SL |
1410 | } |
1411 | ||
7648fa99 JB |
1412 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
1413 | { | |
1414 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1415 | u16 ddrpll, csipll; | |
1416 | ||
1417 | ddrpll = I915_READ16(DDRMPLL1); | |
1418 | csipll = I915_READ16(CSIPLL0); | |
1419 | ||
1420 | switch (ddrpll & 0xff) { | |
1421 | case 0xc: | |
1422 | dev_priv->mem_freq = 800; | |
1423 | break; | |
1424 | case 0x10: | |
1425 | dev_priv->mem_freq = 1066; | |
1426 | break; | |
1427 | case 0x14: | |
1428 | dev_priv->mem_freq = 1333; | |
1429 | break; | |
1430 | case 0x18: | |
1431 | dev_priv->mem_freq = 1600; | |
1432 | break; | |
1433 | default: | |
1434 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
1435 | ddrpll & 0xff); | |
1436 | dev_priv->mem_freq = 0; | |
1437 | break; | |
1438 | } | |
1439 | ||
1440 | dev_priv->r_t = dev_priv->mem_freq; | |
1441 | ||
1442 | switch (csipll & 0x3ff) { | |
1443 | case 0x00c: | |
1444 | dev_priv->fsb_freq = 3200; | |
1445 | break; | |
1446 | case 0x00e: | |
1447 | dev_priv->fsb_freq = 3733; | |
1448 | break; | |
1449 | case 0x010: | |
1450 | dev_priv->fsb_freq = 4266; | |
1451 | break; | |
1452 | case 0x012: | |
1453 | dev_priv->fsb_freq = 4800; | |
1454 | break; | |
1455 | case 0x014: | |
1456 | dev_priv->fsb_freq = 5333; | |
1457 | break; | |
1458 | case 0x016: | |
1459 | dev_priv->fsb_freq = 5866; | |
1460 | break; | |
1461 | case 0x018: | |
1462 | dev_priv->fsb_freq = 6400; | |
1463 | break; | |
1464 | default: | |
1465 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
1466 | csipll & 0x3ff); | |
1467 | dev_priv->fsb_freq = 0; | |
1468 | break; | |
1469 | } | |
1470 | ||
1471 | if (dev_priv->fsb_freq == 3200) { | |
1472 | dev_priv->c_m = 0; | |
1473 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { | |
1474 | dev_priv->c_m = 1; | |
1475 | } else { | |
1476 | dev_priv->c_m = 2; | |
1477 | } | |
1478 | } | |
1479 | ||
faa60c41 CW |
1480 | static const struct cparams { |
1481 | u16 i; | |
1482 | u16 t; | |
1483 | u16 m; | |
1484 | u16 c; | |
1485 | } cparams[] = { | |
7648fa99 JB |
1486 | { 1, 1333, 301, 28664 }, |
1487 | { 1, 1066, 294, 24460 }, | |
1488 | { 1, 800, 294, 25192 }, | |
1489 | { 0, 1333, 276, 27605 }, | |
1490 | { 0, 1066, 276, 27605 }, | |
1491 | { 0, 800, 231, 23784 }, | |
1492 | }; | |
1493 | ||
1494 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) | |
1495 | { | |
1496 | u64 total_count, diff, ret; | |
1497 | u32 count1, count2, count3, m = 0, c = 0; | |
1498 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
1499 | int i; | |
1500 | ||
1501 | diff1 = now - dev_priv->last_time1; | |
1502 | ||
4ed0b577 ED |
1503 | /* Prevent division-by-zero if we are asking too fast. |
1504 | * Also, we don't get interesting results if we are polling | |
1505 | * faster than once in 10ms, so just return the saved value | |
1506 | * in such cases. | |
1507 | */ | |
1508 | if (diff1 <= 10) | |
1509 | return dev_priv->chipset_power; | |
1510 | ||
7648fa99 JB |
1511 | count1 = I915_READ(DMIEC); |
1512 | count2 = I915_READ(DDREC); | |
1513 | count3 = I915_READ(CSIEC); | |
1514 | ||
1515 | total_count = count1 + count2 + count3; | |
1516 | ||
1517 | /* FIXME: handle per-counter overflow */ | |
1518 | if (total_count < dev_priv->last_count1) { | |
1519 | diff = ~0UL - dev_priv->last_count1; | |
1520 | diff += total_count; | |
1521 | } else { | |
1522 | diff = total_count - dev_priv->last_count1; | |
1523 | } | |
1524 | ||
1525 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
1526 | if (cparams[i].i == dev_priv->c_m && | |
1527 | cparams[i].t == dev_priv->r_t) { | |
1528 | m = cparams[i].m; | |
1529 | c = cparams[i].c; | |
1530 | break; | |
1531 | } | |
1532 | } | |
1533 | ||
d270ae34 | 1534 | diff = div_u64(diff, diff1); |
7648fa99 | 1535 | ret = ((m * diff) + c); |
d270ae34 | 1536 | ret = div_u64(ret, 10); |
7648fa99 JB |
1537 | |
1538 | dev_priv->last_count1 = total_count; | |
1539 | dev_priv->last_time1 = now; | |
1540 | ||
4ed0b577 ED |
1541 | dev_priv->chipset_power = ret; |
1542 | ||
7648fa99 JB |
1543 | return ret; |
1544 | } | |
1545 | ||
1546 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) | |
1547 | { | |
1548 | unsigned long m, x, b; | |
1549 | u32 tsfs; | |
1550 | ||
1551 | tsfs = I915_READ(TSFS); | |
1552 | ||
1553 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
1554 | x = I915_READ8(TR1); | |
1555 | ||
1556 | b = tsfs & TSFS_INTR_MASK; | |
1557 | ||
1558 | return ((m * x) / 127) - b; | |
1559 | } | |
1560 | ||
faa60c41 | 1561 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
7648fa99 | 1562 | { |
faa60c41 CW |
1563 | static const struct v_table { |
1564 | u16 vd; /* in .1 mil */ | |
1565 | u16 vm; /* in .1 mil */ | |
1566 | } v_table[] = { | |
1567 | { 0, 0, }, | |
1568 | { 375, 0, }, | |
1569 | { 500, 0, }, | |
1570 | { 625, 0, }, | |
1571 | { 750, 0, }, | |
1572 | { 875, 0, }, | |
1573 | { 1000, 0, }, | |
1574 | { 1125, 0, }, | |
1575 | { 4125, 3000, }, | |
1576 | { 4125, 3000, }, | |
1577 | { 4125, 3000, }, | |
1578 | { 4125, 3000, }, | |
1579 | { 4125, 3000, }, | |
1580 | { 4125, 3000, }, | |
1581 | { 4125, 3000, }, | |
1582 | { 4125, 3000, }, | |
1583 | { 4125, 3000, }, | |
1584 | { 4125, 3000, }, | |
1585 | { 4125, 3000, }, | |
1586 | { 4125, 3000, }, | |
1587 | { 4125, 3000, }, | |
1588 | { 4125, 3000, }, | |
1589 | { 4125, 3000, }, | |
1590 | { 4125, 3000, }, | |
1591 | { 4125, 3000, }, | |
1592 | { 4125, 3000, }, | |
1593 | { 4125, 3000, }, | |
1594 | { 4125, 3000, }, | |
1595 | { 4125, 3000, }, | |
1596 | { 4125, 3000, }, | |
1597 | { 4125, 3000, }, | |
1598 | { 4125, 3000, }, | |
1599 | { 4250, 3125, }, | |
1600 | { 4375, 3250, }, | |
1601 | { 4500, 3375, }, | |
1602 | { 4625, 3500, }, | |
1603 | { 4750, 3625, }, | |
1604 | { 4875, 3750, }, | |
1605 | { 5000, 3875, }, | |
1606 | { 5125, 4000, }, | |
1607 | { 5250, 4125, }, | |
1608 | { 5375, 4250, }, | |
1609 | { 5500, 4375, }, | |
1610 | { 5625, 4500, }, | |
1611 | { 5750, 4625, }, | |
1612 | { 5875, 4750, }, | |
1613 | { 6000, 4875, }, | |
1614 | { 6125, 5000, }, | |
1615 | { 6250, 5125, }, | |
1616 | { 6375, 5250, }, | |
1617 | { 6500, 5375, }, | |
1618 | { 6625, 5500, }, | |
1619 | { 6750, 5625, }, | |
1620 | { 6875, 5750, }, | |
1621 | { 7000, 5875, }, | |
1622 | { 7125, 6000, }, | |
1623 | { 7250, 6125, }, | |
1624 | { 7375, 6250, }, | |
1625 | { 7500, 6375, }, | |
1626 | { 7625, 6500, }, | |
1627 | { 7750, 6625, }, | |
1628 | { 7875, 6750, }, | |
1629 | { 8000, 6875, }, | |
1630 | { 8125, 7000, }, | |
1631 | { 8250, 7125, }, | |
1632 | { 8375, 7250, }, | |
1633 | { 8500, 7375, }, | |
1634 | { 8625, 7500, }, | |
1635 | { 8750, 7625, }, | |
1636 | { 8875, 7750, }, | |
1637 | { 9000, 7875, }, | |
1638 | { 9125, 8000, }, | |
1639 | { 9250, 8125, }, | |
1640 | { 9375, 8250, }, | |
1641 | { 9500, 8375, }, | |
1642 | { 9625, 8500, }, | |
1643 | { 9750, 8625, }, | |
1644 | { 9875, 8750, }, | |
1645 | { 10000, 8875, }, | |
1646 | { 10125, 9000, }, | |
1647 | { 10250, 9125, }, | |
1648 | { 10375, 9250, }, | |
1649 | { 10500, 9375, }, | |
1650 | { 10625, 9500, }, | |
1651 | { 10750, 9625, }, | |
1652 | { 10875, 9750, }, | |
1653 | { 11000, 9875, }, | |
1654 | { 11125, 10000, }, | |
1655 | { 11250, 10125, }, | |
1656 | { 11375, 10250, }, | |
1657 | { 11500, 10375, }, | |
1658 | { 11625, 10500, }, | |
1659 | { 11750, 10625, }, | |
1660 | { 11875, 10750, }, | |
1661 | { 12000, 10875, }, | |
1662 | { 12125, 11000, }, | |
1663 | { 12250, 11125, }, | |
1664 | { 12375, 11250, }, | |
1665 | { 12500, 11375, }, | |
1666 | { 12625, 11500, }, | |
1667 | { 12750, 11625, }, | |
1668 | { 12875, 11750, }, | |
1669 | { 13000, 11875, }, | |
1670 | { 13125, 12000, }, | |
1671 | { 13250, 12125, }, | |
1672 | { 13375, 12250, }, | |
1673 | { 13500, 12375, }, | |
1674 | { 13625, 12500, }, | |
1675 | { 13750, 12625, }, | |
1676 | { 13875, 12750, }, | |
1677 | { 14000, 12875, }, | |
1678 | { 14125, 13000, }, | |
1679 | { 14250, 13125, }, | |
1680 | { 14375, 13250, }, | |
1681 | { 14500, 13375, }, | |
1682 | { 14625, 13500, }, | |
1683 | { 14750, 13625, }, | |
1684 | { 14875, 13750, }, | |
1685 | { 15000, 13875, }, | |
1686 | { 15125, 14000, }, | |
1687 | { 15250, 14125, }, | |
1688 | { 15375, 14250, }, | |
1689 | { 15500, 14375, }, | |
1690 | { 15625, 14500, }, | |
1691 | { 15750, 14625, }, | |
1692 | { 15875, 14750, }, | |
1693 | { 16000, 14875, }, | |
1694 | { 16125, 15000, }, | |
1695 | }; | |
1696 | if (dev_priv->info->is_mobile) | |
1697 | return v_table[pxvid].vm; | |
1698 | else | |
1699 | return v_table[pxvid].vd; | |
7648fa99 JB |
1700 | } |
1701 | ||
1702 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) | |
1703 | { | |
1704 | struct timespec now, diff1; | |
1705 | u64 diff; | |
1706 | unsigned long diffms; | |
1707 | u32 count; | |
1708 | ||
1709 | getrawmonotonic(&now); | |
1710 | diff1 = timespec_sub(now, dev_priv->last_time2); | |
1711 | ||
1712 | /* Don't divide by 0 */ | |
1713 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; | |
1714 | if (!diffms) | |
1715 | return; | |
1716 | ||
1717 | count = I915_READ(GFXEC); | |
1718 | ||
1719 | if (count < dev_priv->last_count2) { | |
1720 | diff = ~0UL - dev_priv->last_count2; | |
1721 | diff += count; | |
1722 | } else { | |
1723 | diff = count - dev_priv->last_count2; | |
1724 | } | |
1725 | ||
1726 | dev_priv->last_count2 = count; | |
1727 | dev_priv->last_time2 = now; | |
1728 | ||
1729 | /* More magic constants... */ | |
1730 | diff = diff * 1181; | |
d270ae34 | 1731 | diff = div_u64(diff, diffms * 10); |
7648fa99 JB |
1732 | dev_priv->gfx_power = diff; |
1733 | } | |
1734 | ||
1735 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) | |
1736 | { | |
1737 | unsigned long t, corr, state1, corr2, state2; | |
1738 | u32 pxvid, ext_v; | |
1739 | ||
1740 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4)); | |
1741 | pxvid = (pxvid >> 24) & 0x7f; | |
1742 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
1743 | ||
1744 | state1 = ext_v; | |
1745 | ||
1746 | t = i915_mch_val(dev_priv); | |
1747 | ||
1748 | /* Revel in the empirically derived constants */ | |
1749 | ||
1750 | /* Correction factor in 1/100000 units */ | |
1751 | if (t > 80) | |
1752 | corr = ((t * 2349) + 135940); | |
1753 | else if (t >= 50) | |
1754 | corr = ((t * 964) + 29317); | |
1755 | else /* < 50 */ | |
1756 | corr = ((t * 301) + 1004); | |
1757 | ||
1758 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
1759 | corr /= 100000; | |
1760 | corr2 = (corr * dev_priv->corr); | |
1761 | ||
1762 | state2 = (corr2 * state1) / 10000; | |
1763 | state2 /= 100; /* convert to mW */ | |
1764 | ||
1765 | i915_update_gfx_val(dev_priv); | |
1766 | ||
1767 | return dev_priv->gfx_power + state2; | |
1768 | } | |
1769 | ||
1770 | /* Global for IPS driver to get at the current i915 device */ | |
1771 | static struct drm_i915_private *i915_mch_dev; | |
1772 | /* | |
1773 | * Lock protecting IPS related data structures | |
1774 | * - i915_mch_dev | |
1775 | * - dev_priv->max_delay | |
1776 | * - dev_priv->min_delay | |
1777 | * - dev_priv->fmax | |
1778 | * - dev_priv->gpu_busy | |
1779 | */ | |
995b6762 | 1780 | static DEFINE_SPINLOCK(mchdev_lock); |
7648fa99 JB |
1781 | |
1782 | /** | |
1783 | * i915_read_mch_val - return value for IPS use | |
1784 | * | |
1785 | * Calculate and return a value for the IPS driver to use when deciding whether | |
1786 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
1787 | */ | |
1788 | unsigned long i915_read_mch_val(void) | |
1789 | { | |
0206e353 | 1790 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1791 | unsigned long chipset_val, graphics_val, ret = 0; |
1792 | ||
0206e353 | 1793 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1794 | if (!i915_mch_dev) |
1795 | goto out_unlock; | |
1796 | dev_priv = i915_mch_dev; | |
1797 | ||
1798 | chipset_val = i915_chipset_val(dev_priv); | |
1799 | graphics_val = i915_gfx_val(dev_priv); | |
1800 | ||
1801 | ret = chipset_val + graphics_val; | |
1802 | ||
1803 | out_unlock: | |
0206e353 | 1804 | spin_unlock(&mchdev_lock); |
7648fa99 | 1805 | |
0206e353 | 1806 | return ret; |
7648fa99 JB |
1807 | } |
1808 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
1809 | ||
1810 | /** | |
1811 | * i915_gpu_raise - raise GPU frequency limit | |
1812 | * | |
1813 | * Raise the limit; IPS indicates we have thermal headroom. | |
1814 | */ | |
1815 | bool i915_gpu_raise(void) | |
1816 | { | |
0206e353 | 1817 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1818 | bool ret = true; |
1819 | ||
0206e353 | 1820 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1821 | if (!i915_mch_dev) { |
1822 | ret = false; | |
1823 | goto out_unlock; | |
1824 | } | |
1825 | dev_priv = i915_mch_dev; | |
1826 | ||
1827 | if (dev_priv->max_delay > dev_priv->fmax) | |
1828 | dev_priv->max_delay--; | |
1829 | ||
1830 | out_unlock: | |
0206e353 | 1831 | spin_unlock(&mchdev_lock); |
7648fa99 | 1832 | |
0206e353 | 1833 | return ret; |
7648fa99 JB |
1834 | } |
1835 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
1836 | ||
1837 | /** | |
1838 | * i915_gpu_lower - lower GPU frequency limit | |
1839 | * | |
1840 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
1841 | * frequency maximum. | |
1842 | */ | |
1843 | bool i915_gpu_lower(void) | |
1844 | { | |
0206e353 | 1845 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1846 | bool ret = true; |
1847 | ||
0206e353 | 1848 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1849 | if (!i915_mch_dev) { |
1850 | ret = false; | |
1851 | goto out_unlock; | |
1852 | } | |
1853 | dev_priv = i915_mch_dev; | |
1854 | ||
1855 | if (dev_priv->max_delay < dev_priv->min_delay) | |
1856 | dev_priv->max_delay++; | |
1857 | ||
1858 | out_unlock: | |
0206e353 | 1859 | spin_unlock(&mchdev_lock); |
7648fa99 | 1860 | |
0206e353 | 1861 | return ret; |
7648fa99 JB |
1862 | } |
1863 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
1864 | ||
1865 | /** | |
1866 | * i915_gpu_busy - indicate GPU business to IPS | |
1867 | * | |
1868 | * Tell the IPS driver whether or not the GPU is busy. | |
1869 | */ | |
1870 | bool i915_gpu_busy(void) | |
1871 | { | |
0206e353 | 1872 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1873 | bool ret = false; |
1874 | ||
0206e353 | 1875 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1876 | if (!i915_mch_dev) |
1877 | goto out_unlock; | |
1878 | dev_priv = i915_mch_dev; | |
1879 | ||
1880 | ret = dev_priv->busy; | |
1881 | ||
1882 | out_unlock: | |
0206e353 | 1883 | spin_unlock(&mchdev_lock); |
7648fa99 | 1884 | |
0206e353 | 1885 | return ret; |
7648fa99 JB |
1886 | } |
1887 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
1888 | ||
1889 | /** | |
1890 | * i915_gpu_turbo_disable - disable graphics turbo | |
1891 | * | |
1892 | * Disable graphics turbo by resetting the max frequency and setting the | |
1893 | * current frequency to the default. | |
1894 | */ | |
1895 | bool i915_gpu_turbo_disable(void) | |
1896 | { | |
0206e353 | 1897 | struct drm_i915_private *dev_priv; |
7648fa99 JB |
1898 | bool ret = true; |
1899 | ||
0206e353 | 1900 | spin_lock(&mchdev_lock); |
7648fa99 JB |
1901 | if (!i915_mch_dev) { |
1902 | ret = false; | |
1903 | goto out_unlock; | |
1904 | } | |
1905 | dev_priv = i915_mch_dev; | |
1906 | ||
1907 | dev_priv->max_delay = dev_priv->fstart; | |
1908 | ||
1909 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart)) | |
1910 | ret = false; | |
1911 | ||
1912 | out_unlock: | |
0206e353 | 1913 | spin_unlock(&mchdev_lock); |
7648fa99 | 1914 | |
0206e353 | 1915 | return ret; |
7648fa99 JB |
1916 | } |
1917 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
1918 | ||
63ee41d7 EA |
1919 | /** |
1920 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
1921 | * IPS got loaded first. | |
1922 | * | |
1923 | * This awkward dance is so that neither module has to depend on the | |
1924 | * other in order for IPS to do the appropriate communication of | |
1925 | * GPU turbo limits to i915. | |
1926 | */ | |
1927 | static void | |
1928 | ips_ping_for_i915_load(void) | |
1929 | { | |
1930 | void (*link)(void); | |
1931 | ||
1932 | link = symbol_get(ips_link_to_i915_driver); | |
1933 | if (link) { | |
1934 | link(); | |
1935 | symbol_put(ips_link_to_i915_driver); | |
1936 | } | |
1937 | } | |
1938 | ||
e2b665c4 AJ |
1939 | static void |
1940 | i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, | |
1941 | unsigned long size) | |
1942 | { | |
23f54bea CW |
1943 | dev_priv->mm.gtt_mtrr = -1; |
1944 | ||
9e984bc1 AJ |
1945 | #if defined(CONFIG_X86_PAT) |
1946 | if (cpu_has_pat) | |
1947 | return; | |
1948 | #endif | |
1949 | ||
e2b665c4 AJ |
1950 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
1951 | * one would think, because the kernel disables PAT on first | |
1952 | * generation Core chips because WC PAT gets overridden by a UC | |
1953 | * MTRR if present. Even if a UC MTRR isn't present. | |
1954 | */ | |
1955 | dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1); | |
1956 | if (dev_priv->mm.gtt_mtrr < 0) { | |
1957 | DRM_INFO("MTRR allocation failed. Graphics " | |
1958 | "performance may suffer.\n"); | |
1959 | } | |
1960 | } | |
1961 | ||
79e53945 JB |
1962 | /** |
1963 | * i915_driver_load - setup chip and create an initial config | |
1964 | * @dev: DRM device | |
1965 | * @flags: startup flags | |
1966 | * | |
1967 | * The driver load routine has to do several things: | |
1968 | * - drive output discovery via intel_modeset_init() | |
1969 | * - initialize the memory manager | |
1970 | * - allocate initial config memory | |
1971 | * - setup the DRM framebuffer with the allocated memory | |
1972 | */ | |
84b1fd10 | 1973 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1974 | { |
ea059a1e | 1975 | struct drm_i915_private *dev_priv; |
26394d92 | 1976 | struct intel_device_info *info; |
cfdf1fa2 | 1977 | int ret = 0, mmio_bar; |
9021f284 | 1978 | uint32_t aperture_size; |
fe669bf8 | 1979 | |
26394d92 DV |
1980 | info = (struct intel_device_info *) flags; |
1981 | ||
1982 | /* Refuse to load on gen6+ without kms enabled. */ | |
1983 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) | |
1984 | return -ENODEV; | |
1985 | ||
fe669bf8 | 1986 | |
22eae947 DA |
1987 | /* i915 has 4 more counters */ |
1988 | dev->counters += 4; | |
1989 | dev->types[6] = _DRM_STAT_IRQ; | |
1990 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1991 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1992 | dev->types[9] = _DRM_STAT_DMA; | |
1993 | ||
9a298b2a | 1994 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
ba8bbcf6 JB |
1995 | if (dev_priv == NULL) |
1996 | return -ENOMEM; | |
1997 | ||
ba8bbcf6 | 1998 | dev->dev_private = (void *)dev_priv; |
673a394b | 1999 | dev_priv->dev = dev; |
26394d92 | 2000 | dev_priv->info = info; |
ba8bbcf6 | 2001 | |
ec2a4c3f DA |
2002 | if (i915_get_bridge_dev(dev)) { |
2003 | ret = -EIO; | |
2004 | goto free_priv; | |
2005 | } | |
2006 | ||
466e69b8 DA |
2007 | pci_set_master(dev->pdev); |
2008 | ||
9f82d238 DV |
2009 | /* overlay on gen2 is broken and can't address above 1G */ |
2010 | if (IS_GEN2(dev)) | |
2011 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
2012 | ||
6927faf3 JN |
2013 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
2014 | * using 32bit addressing, overwriting memory if HWS is located | |
2015 | * above 4GB. | |
2016 | * | |
2017 | * The documentation also mentions an issue with undefined | |
2018 | * behaviour if any general state is accessed within a page above 4GB, | |
2019 | * which also needs to be handled carefully. | |
2020 | */ | |
2021 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
2022 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
2023 | ||
b4ce0f85 CW |
2024 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
2025 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0); | |
2026 | if (!dev_priv->regs) { | |
2027 | DRM_ERROR("failed to map registers\n"); | |
2028 | ret = -EIO; | |
2029 | goto put_bridge; | |
2030 | } | |
2031 | ||
71e9339c CW |
2032 | dev_priv->mm.gtt = intel_gtt_get(); |
2033 | if (!dev_priv->mm.gtt) { | |
2034 | DRM_ERROR("Failed to initialize GTT\n"); | |
2035 | ret = -ENODEV; | |
a7b85d2a | 2036 | goto out_rmmap; |
71e9339c CW |
2037 | } |
2038 | ||
9021f284 | 2039 | aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
71e9339c | 2040 | |
0206e353 | 2041 | dev_priv->mm.gtt_mapping = |
9021f284 | 2042 | io_mapping_create_wc(dev->agp->base, aperture_size); |
6644107d VP |
2043 | if (dev_priv->mm.gtt_mapping == NULL) { |
2044 | ret = -EIO; | |
2045 | goto out_rmmap; | |
2046 | } | |
2047 | ||
9021f284 | 2048 | i915_mtrr_setup(dev_priv, dev->agp->base, aperture_size); |
19966754 | 2049 | |
e642abbf CW |
2050 | /* The i915 workqueue is primarily used for batched retirement of |
2051 | * requests (and thus managing bo) once the task has been completed | |
2052 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
2053 | * need high-priority retirement, such as waiting for an explicit | |
2054 | * bo. | |
2055 | * | |
2056 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 2057 | * idle-timers and recording error state. |
e642abbf CW |
2058 | * |
2059 | * All tasks on the workqueue are expected to acquire the dev mutex | |
2060 | * so there is no point in running more than one instance of the | |
2061 | * workqueue at any time: max_active = 1 and NON_REENTRANT. | |
2062 | */ | |
2063 | dev_priv->wq = alloc_workqueue("i915", | |
2064 | WQ_UNBOUND | WQ_NON_REENTRANT, | |
2065 | 1); | |
9c9fe1f8 EA |
2066 | if (dev_priv->wq == NULL) { |
2067 | DRM_ERROR("Failed to create our workqueue.\n"); | |
2068 | ret = -ENOMEM; | |
a7b85d2a | 2069 | goto out_mtrrfree; |
9c9fe1f8 EA |
2070 | } |
2071 | ||
ac5c4e76 DA |
2072 | /* enable GEM by default */ |
2073 | dev_priv->has_gem = 1; | |
ac5c4e76 | 2074 | |
f71d4af4 | 2075 | intel_irq_init(dev); |
9880b7a5 | 2076 | |
c4804411 ZW |
2077 | /* Try to make sure MCHBAR is enabled before poking at it */ |
2078 | intel_setup_mchbar(dev); | |
f899fc64 | 2079 | intel_setup_gmbus(dev); |
44834a67 | 2080 | intel_opregion_setup(dev); |
c4804411 | 2081 | |
6d139a87 BF |
2082 | /* Make sure the bios did its job and set up vital registers */ |
2083 | intel_setup_bios(dev); | |
2084 | ||
673a394b EA |
2085 | i915_gem_load(dev); |
2086 | ||
398c9cb2 KP |
2087 | /* Init HWS */ |
2088 | if (!I915_NEED_GFX_HWS(dev)) { | |
2089 | ret = i915_init_phys_hws(dev); | |
56e2ea34 CW |
2090 | if (ret) |
2091 | goto out_gem_unload; | |
398c9cb2 | 2092 | } |
ed4cb414 | 2093 | |
7648fa99 JB |
2094 | if (IS_PINEVIEW(dev)) |
2095 | i915_pineview_get_mem_freq(dev); | |
f00a3ddf | 2096 | else if (IS_GEN5(dev)) |
7648fa99 | 2097 | i915_ironlake_get_mem_freq(dev); |
7662c8bd | 2098 | |
ed4cb414 EA |
2099 | /* On the 945G/GM, the chipset reports the MSI capability on the |
2100 | * integrated graphics even though the support isn't actually there | |
2101 | * according to the published specs. It doesn't appear to function | |
2102 | * correctly in testing on 945G. | |
2103 | * This may be a side effect of MSI having been made available for PEG | |
2104 | * and the registers being closely associated. | |
d1ed629f KP |
2105 | * |
2106 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
2107 | * be lost or delayed, but we use them anyways to avoid |
2108 | * stuck interrupts on some machines. | |
ed4cb414 | 2109 | */ |
b60678a7 | 2110 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 2111 | pci_enable_msi(dev->pdev); |
ed4cb414 | 2112 | |
9f1f46a4 | 2113 | spin_lock_init(&dev_priv->gt_lock); |
1ec14ad3 | 2114 | spin_lock_init(&dev_priv->irq_lock); |
63eeaf38 | 2115 | spin_lock_init(&dev_priv->error_lock); |
4912d041 | 2116 | spin_lock_init(&dev_priv->rps_lock); |
ed4cb414 | 2117 | |
27f8227b JB |
2118 | if (IS_IVYBRIDGE(dev)) |
2119 | dev_priv->num_pipe = 3; | |
2120 | else if (IS_MOBILE(dev) || !IS_GEN2(dev)) | |
9db4a9c7 JB |
2121 | dev_priv->num_pipe = 2; |
2122 | else | |
2123 | dev_priv->num_pipe = 1; | |
2124 | ||
2125 | ret = drm_vblank_init(dev, dev_priv->num_pipe); | |
56e2ea34 CW |
2126 | if (ret) |
2127 | goto out_gem_unload; | |
52440211 | 2128 | |
11ed50ec BG |
2129 | /* Start out suspended */ |
2130 | dev_priv->mm.suspended = 1; | |
2131 | ||
3bad0781 ZW |
2132 | intel_detect_pch(dev); |
2133 | ||
79e53945 | 2134 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 2135 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
2136 | if (ret < 0) { |
2137 | DRM_ERROR("failed to init modeset\n"); | |
56e2ea34 | 2138 | goto out_gem_unload; |
79e53945 JB |
2139 | } |
2140 | } | |
2141 | ||
74a365b3 | 2142 | /* Must be done after probing outputs */ |
44834a67 CW |
2143 | intel_opregion_init(dev); |
2144 | acpi_video_register(); | |
74a365b3 | 2145 | |
f65d9421 BG |
2146 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
2147 | (unsigned long) dev); | |
7648fa99 JB |
2148 | |
2149 | spin_lock(&mchdev_lock); | |
2150 | i915_mch_dev = dev_priv; | |
2151 | dev_priv->mchdev_lock = &mchdev_lock; | |
2152 | spin_unlock(&mchdev_lock); | |
2153 | ||
63ee41d7 EA |
2154 | ips_ping_for_i915_load(); |
2155 | ||
79e53945 JB |
2156 | return 0; |
2157 | ||
56e2ea34 | 2158 | out_gem_unload: |
a7b85d2a KP |
2159 | if (dev_priv->mm.inactive_shrinker.shrink) |
2160 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
2161 | ||
56e2ea34 CW |
2162 | if (dev->pdev->msi_enabled) |
2163 | pci_disable_msi(dev->pdev); | |
2164 | ||
2165 | intel_teardown_gmbus(dev); | |
2166 | intel_teardown_mchbar(dev); | |
9c9fe1f8 | 2167 | destroy_workqueue(dev_priv->wq); |
a7b85d2a KP |
2168 | out_mtrrfree: |
2169 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
2170 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
2171 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
2172 | dev_priv->mm.gtt_mtrr = -1; | |
2173 | } | |
6644107d | 2174 | io_mapping_free(dev_priv->mm.gtt_mapping); |
79e53945 | 2175 | out_rmmap: |
6dda569f | 2176 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
2177 | put_bridge: |
2178 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 2179 | free_priv: |
9a298b2a | 2180 | kfree(dev_priv); |
ba8bbcf6 JB |
2181 | return ret; |
2182 | } | |
2183 | ||
2184 | int i915_driver_unload(struct drm_device *dev) | |
2185 | { | |
2186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 2187 | int ret; |
ba8bbcf6 | 2188 | |
7648fa99 JB |
2189 | spin_lock(&mchdev_lock); |
2190 | i915_mch_dev = NULL; | |
2191 | spin_unlock(&mchdev_lock); | |
2192 | ||
17250b71 CW |
2193 | if (dev_priv->mm.inactive_shrinker.shrink) |
2194 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
2195 | ||
c911fc1c | 2196 | mutex_lock(&dev->struct_mutex); |
b93f9cf1 | 2197 | ret = i915_gpu_idle(dev, true); |
c911fc1c DV |
2198 | if (ret) |
2199 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
2200 | mutex_unlock(&dev->struct_mutex); | |
2201 | ||
75ef9da2 DV |
2202 | /* Cancel the retire work handler, which should be idle now. */ |
2203 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
2204 | ||
ab657db1 EA |
2205 | io_mapping_free(dev_priv->mm.gtt_mapping); |
2206 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
2207 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
2208 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
2209 | dev_priv->mm.gtt_mtrr = -1; | |
2210 | } | |
2211 | ||
44834a67 CW |
2212 | acpi_video_unregister(); |
2213 | ||
79e53945 | 2214 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
7b4f3990 | 2215 | intel_fbdev_fini(dev); |
3d8620cc JB |
2216 | intel_modeset_cleanup(dev); |
2217 | ||
6363ee6f ZY |
2218 | /* |
2219 | * free the memory space allocated for the child device | |
2220 | * config parsed from VBT | |
2221 | */ | |
2222 | if (dev_priv->child_dev && dev_priv->child_dev_num) { | |
2223 | kfree(dev_priv->child_dev); | |
2224 | dev_priv->child_dev = NULL; | |
2225 | dev_priv->child_dev_num = 0; | |
2226 | } | |
6c0d9350 | 2227 | |
6a9ee8af | 2228 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 2229 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
2230 | } |
2231 | ||
a8b4899e | 2232 | /* Free error state after interrupts are fully disabled. */ |
bc0c7f14 DV |
2233 | del_timer_sync(&dev_priv->hangcheck_timer); |
2234 | cancel_work_sync(&dev_priv->error_work); | |
a8b4899e | 2235 | i915_destroy_error_state(dev); |
bc0c7f14 | 2236 | |
ed4cb414 EA |
2237 | if (dev->pdev->msi_enabled) |
2238 | pci_disable_msi(dev->pdev); | |
2239 | ||
44834a67 | 2240 | intel_opregion_fini(dev); |
8ee1c3db | 2241 | |
79e53945 | 2242 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
2243 | /* Flush any outstanding unpin_work. */ |
2244 | flush_workqueue(dev_priv->wq); | |
2245 | ||
79e53945 | 2246 | mutex_lock(&dev->struct_mutex); |
ecbec53b | 2247 | i915_gem_free_all_phys_object(dev); |
79e53945 JB |
2248 | i915_gem_cleanup_ringbuffer(dev); |
2249 | mutex_unlock(&dev->struct_mutex); | |
1d2a314c | 2250 | i915_gem_cleanup_aliasing_ppgtt(dev); |
20bf377e JB |
2251 | if (I915_HAS_FBC(dev) && i915_powersave) |
2252 | i915_cleanup_compression(dev); | |
fe669bf8 | 2253 | drm_mm_takedown(&dev_priv->mm.stolen); |
02e792fb DV |
2254 | |
2255 | intel_cleanup_overlay(dev); | |
c2873e96 KP |
2256 | |
2257 | if (!I915_NEED_GFX_HWS(dev)) | |
2258 | i915_free_hws(dev); | |
79e53945 JB |
2259 | } |
2260 | ||
701394cc | 2261 | if (dev_priv->regs != NULL) |
6dda569f | 2262 | pci_iounmap(dev->pdev, dev_priv->regs); |
701394cc | 2263 | |
f899fc64 | 2264 | intel_teardown_gmbus(dev); |
c4804411 ZW |
2265 | intel_teardown_mchbar(dev); |
2266 | ||
bc0c7f14 DV |
2267 | destroy_workqueue(dev_priv->wq); |
2268 | ||
ec2a4c3f | 2269 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 2270 | kfree(dev->dev_private); |
ba8bbcf6 | 2271 | |
22eae947 DA |
2272 | return 0; |
2273 | } | |
2274 | ||
f787a5f5 | 2275 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 2276 | { |
f787a5f5 | 2277 | struct drm_i915_file_private *file_priv; |
673a394b | 2278 | |
8a4c47f3 | 2279 | DRM_DEBUG_DRIVER("\n"); |
f787a5f5 CW |
2280 | file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL); |
2281 | if (!file_priv) | |
673a394b EA |
2282 | return -ENOMEM; |
2283 | ||
f787a5f5 | 2284 | file->driver_priv = file_priv; |
673a394b | 2285 | |
1c25595f | 2286 | spin_lock_init(&file_priv->mm.lock); |
f787a5f5 | 2287 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
673a394b EA |
2288 | |
2289 | return 0; | |
2290 | } | |
2291 | ||
79e53945 JB |
2292 | /** |
2293 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
2294 | * @dev: DRM device | |
2295 | * | |
2296 | * Take care of cleaning up after all DRM clients have exited. In the | |
2297 | * mode setting case, we want to restore the kernel's initial mode (just | |
2298 | * in case the last client left us in a bad state). | |
2299 | * | |
9021f284 | 2300 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
2301 | * and DMA structures, since the kernel won't be using them, and clea |
2302 | * up any GEM state. | |
2303 | */ | |
84b1fd10 | 2304 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 2305 | { |
ba8bbcf6 JB |
2306 | drm_i915_private_t *dev_priv = dev->dev_private; |
2307 | ||
79e53945 | 2308 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
e8e7a2b8 | 2309 | intel_fb_restore_mode(dev); |
6a9ee8af | 2310 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 2311 | return; |
79e53945 | 2312 | } |
144a75fa | 2313 | |
673a394b EA |
2314 | i915_gem_lastclose(dev); |
2315 | ||
b5e89ed5 | 2316 | i915_dma_cleanup(dev); |
1da177e4 LT |
2317 | } |
2318 | ||
6c340eac | 2319 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 2320 | { |
b962442e | 2321 | i915_gem_release(dev, file_priv); |
1da177e4 LT |
2322 | } |
2323 | ||
f787a5f5 | 2324 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 2325 | { |
f787a5f5 | 2326 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 2327 | |
f787a5f5 | 2328 | kfree(file_priv); |
673a394b EA |
2329 | } |
2330 | ||
c153f45f | 2331 | struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
2332 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2333 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
2334 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
2335 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
2336 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
2337 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
2338 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), | |
2339 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
b2c606fe DV |
2340 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
2341 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
2342 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1b2f1489 | 2343 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
b2c606fe | 2344 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1b2f1489 DA |
2345 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2346 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), | |
2347 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
2348 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2349 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2350 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
2351 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), | |
2352 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2353 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2354 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
2355 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
2356 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2357 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2358 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), | |
2359 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), | |
2360 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), | |
2361 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), | |
2362 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), | |
2363 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), | |
2364 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), | |
2365 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), | |
2366 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), | |
2367 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), | |
2368 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), | |
2369 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), | |
2370 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
2371 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
2372 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
2373 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
c94f7029 DA |
2374 | }; |
2375 | ||
2376 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 | 2377 | |
9021f284 DV |
2378 | /* |
2379 | * This is really ugly: Because old userspace abused the linux agp interface to | |
2380 | * manage the gtt, we need to claim that all intel devices are agp. For | |
2381 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 2382 | */ |
84b1fd10 | 2383 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
2384 | { |
2385 | return 1; | |
2386 | } |