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Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | ||
1da177e4 LT |
34 | /* Really want an OS-independent resettable timer. Would like to have |
35 | * this loop run for (eg) 3 sec, but have the timer reset every time | |
36 | * the head pointer changes, so that EBUSY only happens if the ring | |
37 | * actually stalls for (eg) 3 seconds. | |
38 | */ | |
84b1fd10 | 39 | int i915_wait_ring(struct drm_device * dev, int n, const char *caller) |
1da177e4 LT |
40 | { |
41 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
d3a6d446 KP |
43 | u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; |
44 | u32 last_acthd = I915_READ(acthd_reg); | |
45 | u32 acthd; | |
585fb111 | 46 | u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
1da177e4 LT |
47 | int i; |
48 | ||
d3a6d446 | 49 | for (i = 0; i < 100000; i++) { |
585fb111 | 50 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
d3a6d446 | 51 | acthd = I915_READ(acthd_reg); |
1da177e4 LT |
52 | ring->space = ring->head - (ring->tail + 8); |
53 | if (ring->space < 0) | |
54 | ring->space += ring->Size; | |
55 | if (ring->space >= n) | |
56 | return 0; | |
57 | ||
58 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
59 | ||
60 | if (ring->head != last_head) | |
61 | i = 0; | |
d3a6d446 KP |
62 | if (acthd != last_acthd) |
63 | i = 0; | |
1da177e4 LT |
64 | |
65 | last_head = ring->head; | |
d3a6d446 KP |
66 | last_acthd = acthd; |
67 | msleep_interruptible(10); | |
68 | ||
1da177e4 LT |
69 | } |
70 | ||
20caafa6 | 71 | return -EBUSY; |
1da177e4 LT |
72 | } |
73 | ||
84b1fd10 | 74 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
75 | { |
76 | drm_i915_private_t *dev_priv = dev->dev_private; | |
77 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
78 | ||
585fb111 JB |
79 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
80 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
1da177e4 LT |
81 | ring->space = ring->head - (ring->tail + 8); |
82 | if (ring->space < 0) | |
83 | ring->space += ring->Size; | |
84 | ||
85 | if (ring->head == ring->tail) | |
86 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
87 | } | |
88 | ||
84b1fd10 | 89 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 90 | { |
ba8bbcf6 | 91 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
92 | /* Make sure interrupts are disabled here because the uninstall ioctl |
93 | * may not have been called from userspace and after dev_private | |
94 | * is freed, it's too late. | |
95 | */ | |
ed4cb414 | 96 | if (dev->irq_enabled) |
b5e89ed5 | 97 | drm_irq_uninstall(dev); |
1da177e4 | 98 | |
ba8bbcf6 JB |
99 | if (dev_priv->ring.virtual_start) { |
100 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
101 | dev_priv->ring.virtual_start = 0; | |
102 | dev_priv->ring.map.handle = 0; | |
103 | dev_priv->ring.map.size = 0; | |
104 | } | |
dc7a9319 | 105 | |
ba8bbcf6 JB |
106 | if (dev_priv->status_page_dmah) { |
107 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
108 | dev_priv->status_page_dmah = NULL; | |
109 | /* Need to rewrite hardware status page */ | |
585fb111 | 110 | I915_WRITE(HWS_PGA, 0x1ffff000); |
ba8bbcf6 | 111 | } |
1da177e4 | 112 | |
ba8bbcf6 JB |
113 | if (dev_priv->status_gfx_addr) { |
114 | dev_priv->status_gfx_addr = 0; | |
115 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | |
585fb111 | 116 | I915_WRITE(HWS_PGA, 0x1ffff000); |
1da177e4 LT |
117 | } |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
ba8bbcf6 | 122 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 123 | { |
ba8bbcf6 | 124 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 | 125 | |
da509d7a | 126 | dev_priv->sarea = drm_getsarea(dev); |
1da177e4 LT |
127 | if (!dev_priv->sarea) { |
128 | DRM_ERROR("can not find sarea!\n"); | |
1da177e4 | 129 | i915_dma_cleanup(dev); |
20caafa6 | 130 | return -EINVAL; |
1da177e4 LT |
131 | } |
132 | ||
1da177e4 LT |
133 | dev_priv->sarea_priv = (drm_i915_sarea_t *) |
134 | ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); | |
135 | ||
136 | dev_priv->ring.Start = init->ring_start; | |
137 | dev_priv->ring.End = init->ring_end; | |
138 | dev_priv->ring.Size = init->ring_size; | |
139 | dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; | |
140 | ||
141 | dev_priv->ring.map.offset = init->ring_start; | |
142 | dev_priv->ring.map.size = init->ring_size; | |
143 | dev_priv->ring.map.type = 0; | |
144 | dev_priv->ring.map.flags = 0; | |
145 | dev_priv->ring.map.mtrr = 0; | |
146 | ||
b5e89ed5 | 147 | drm_core_ioremap(&dev_priv->ring.map, dev); |
1da177e4 LT |
148 | |
149 | if (dev_priv->ring.map.handle == NULL) { | |
1da177e4 LT |
150 | i915_dma_cleanup(dev); |
151 | DRM_ERROR("can not ioremap virtual address for" | |
152 | " ring buffer\n"); | |
20caafa6 | 153 | return -ENOMEM; |
1da177e4 LT |
154 | } |
155 | ||
156 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
157 | ||
a6b54f3f | 158 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
159 | dev_priv->back_offset = init->back_offset; |
160 | dev_priv->front_offset = init->front_offset; | |
161 | dev_priv->current_page = 0; | |
162 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; | |
163 | ||
1da177e4 LT |
164 | /* Allow hardware batchbuffers unless told otherwise. |
165 | */ | |
166 | dev_priv->allow_batchbuffer = 1; | |
167 | ||
168 | /* Program Hardware Status Page */ | |
b39d50e5 | 169 | if (!I915_NEED_GFX_HWS(dev)) { |
dc7a9319 WZ |
170 | dev_priv->status_page_dmah = |
171 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); | |
172 | ||
173 | if (!dev_priv->status_page_dmah) { | |
dc7a9319 WZ |
174 | i915_dma_cleanup(dev); |
175 | DRM_ERROR("Can not allocate hardware status page\n"); | |
20caafa6 | 176 | return -ENOMEM; |
dc7a9319 WZ |
177 | } |
178 | dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; | |
179 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | |
1da177e4 | 180 | |
dc7a9319 | 181 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
585fb111 | 182 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
1da177e4 | 183 | } |
1da177e4 | 184 | DRM_DEBUG("Enabled hardware status page\n"); |
1da177e4 LT |
185 | return 0; |
186 | } | |
187 | ||
84b1fd10 | 188 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
189 | { |
190 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
191 | ||
bf9d8929 | 192 | DRM_DEBUG("%s\n", __func__); |
1da177e4 LT |
193 | |
194 | if (!dev_priv->sarea) { | |
195 | DRM_ERROR("can not find sarea!\n"); | |
20caafa6 | 196 | return -EINVAL; |
1da177e4 LT |
197 | } |
198 | ||
1da177e4 LT |
199 | if (dev_priv->ring.map.handle == NULL) { |
200 | DRM_ERROR("can not ioremap virtual address for" | |
201 | " ring buffer\n"); | |
20caafa6 | 202 | return -ENOMEM; |
1da177e4 LT |
203 | } |
204 | ||
205 | /* Program Hardware Status Page */ | |
206 | if (!dev_priv->hw_status_page) { | |
207 | DRM_ERROR("Can not find hardware status page\n"); | |
20caafa6 | 208 | return -EINVAL; |
1da177e4 LT |
209 | } |
210 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); | |
211 | ||
dc7a9319 | 212 | if (dev_priv->status_gfx_addr != 0) |
585fb111 | 213 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
dc7a9319 | 214 | else |
585fb111 | 215 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
1da177e4 LT |
216 | DRM_DEBUG("Enabled hardware status page\n"); |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
c153f45f EA |
221 | static int i915_dma_init(struct drm_device *dev, void *data, |
222 | struct drm_file *file_priv) | |
1da177e4 | 223 | { |
c153f45f | 224 | drm_i915_init_t *init = data; |
1da177e4 LT |
225 | int retcode = 0; |
226 | ||
c153f45f | 227 | switch (init->func) { |
1da177e4 | 228 | case I915_INIT_DMA: |
ba8bbcf6 | 229 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
230 | break; |
231 | case I915_CLEANUP_DMA: | |
232 | retcode = i915_dma_cleanup(dev); | |
233 | break; | |
234 | case I915_RESUME_DMA: | |
0d6aa60b | 235 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
236 | break; |
237 | default: | |
20caafa6 | 238 | retcode = -EINVAL; |
1da177e4 LT |
239 | break; |
240 | } | |
241 | ||
242 | return retcode; | |
243 | } | |
244 | ||
245 | /* Implement basically the same security restrictions as hardware does | |
246 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
247 | * | |
248 | * Most of the calculations below involve calculating the size of a | |
249 | * particular instruction. It's important to get the size right as | |
250 | * that tells us where the next instruction to check is. Any illegal | |
251 | * instruction detected will be given a size of zero, which is a | |
252 | * signal to abort the rest of the buffer. | |
253 | */ | |
254 | static int do_validate_cmd(int cmd) | |
255 | { | |
256 | switch (((cmd >> 29) & 0x7)) { | |
257 | case 0x0: | |
258 | switch ((cmd >> 23) & 0x3f) { | |
259 | case 0x0: | |
260 | return 1; /* MI_NOOP */ | |
261 | case 0x4: | |
262 | return 1; /* MI_FLUSH */ | |
263 | default: | |
264 | return 0; /* disallow everything else */ | |
265 | } | |
266 | break; | |
267 | case 0x1: | |
268 | return 0; /* reserved */ | |
269 | case 0x2: | |
270 | return (cmd & 0xff) + 2; /* 2d commands */ | |
271 | case 0x3: | |
272 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
273 | return 1; | |
274 | ||
275 | switch ((cmd >> 24) & 0x1f) { | |
276 | case 0x1c: | |
277 | return 1; | |
278 | case 0x1d: | |
b5e89ed5 | 279 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
280 | case 0x3: |
281 | return (cmd & 0x1f) + 2; | |
282 | case 0x4: | |
283 | return (cmd & 0xf) + 2; | |
284 | default: | |
285 | return (cmd & 0xffff) + 2; | |
286 | } | |
287 | case 0x1e: | |
288 | if (cmd & (1 << 23)) | |
289 | return (cmd & 0xffff) + 1; | |
290 | else | |
291 | return 1; | |
292 | case 0x1f: | |
293 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
294 | return (cmd & 0x1ffff) + 2; | |
295 | else if (cmd & (1 << 17)) /* indirect random */ | |
296 | if ((cmd & 0xffff) == 0) | |
297 | return 0; /* unknown length, too hard */ | |
298 | else | |
299 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
300 | else | |
301 | return 2; /* indirect sequential */ | |
302 | default: | |
303 | return 0; | |
304 | } | |
305 | default: | |
306 | return 0; | |
307 | } | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static int validate_cmd(int cmd) | |
313 | { | |
314 | int ret = do_validate_cmd(cmd); | |
315 | ||
bc5f4523 | 316 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ |
1da177e4 LT |
317 | |
318 | return ret; | |
319 | } | |
320 | ||
84b1fd10 | 321 | static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords) |
1da177e4 LT |
322 | { |
323 | drm_i915_private_t *dev_priv = dev->dev_private; | |
324 | int i; | |
325 | RING_LOCALS; | |
326 | ||
de227f5f | 327 | if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) |
20caafa6 | 328 | return -EINVAL; |
de227f5f | 329 | |
c29b669c | 330 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 331 | |
1da177e4 LT |
332 | for (i = 0; i < dwords;) { |
333 | int cmd, sz; | |
334 | ||
335 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) | |
20caafa6 | 336 | return -EINVAL; |
1da177e4 | 337 | |
1da177e4 | 338 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
20caafa6 | 339 | return -EINVAL; |
1da177e4 | 340 | |
1da177e4 LT |
341 | OUT_RING(cmd); |
342 | ||
343 | while (++i, --sz) { | |
344 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], | |
345 | sizeof(cmd))) { | |
20caafa6 | 346 | return -EINVAL; |
1da177e4 LT |
347 | } |
348 | OUT_RING(cmd); | |
349 | } | |
1da177e4 LT |
350 | } |
351 | ||
de227f5f DA |
352 | if (dwords & 1) |
353 | OUT_RING(0); | |
354 | ||
355 | ADVANCE_LP_RING(); | |
356 | ||
1da177e4 LT |
357 | return 0; |
358 | } | |
359 | ||
84b1fd10 | 360 | static int i915_emit_box(struct drm_device * dev, |
c60ce623 | 361 | struct drm_clip_rect __user * boxes, |
1da177e4 LT |
362 | int i, int DR1, int DR4) |
363 | { | |
364 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 365 | struct drm_clip_rect box; |
1da177e4 LT |
366 | RING_LOCALS; |
367 | ||
368 | if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { | |
20caafa6 | 369 | return -EFAULT; |
1da177e4 LT |
370 | } |
371 | ||
372 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { | |
373 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
374 | box.x1, box.y1, box.x2, box.y2); | |
20caafa6 | 375 | return -EINVAL; |
1da177e4 LT |
376 | } |
377 | ||
c29b669c AH |
378 | if (IS_I965G(dev)) { |
379 | BEGIN_LP_RING(4); | |
380 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
381 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 382 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
383 | OUT_RING(DR4); |
384 | ADVANCE_LP_RING(); | |
385 | } else { | |
386 | BEGIN_LP_RING(6); | |
387 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
388 | OUT_RING(DR1); | |
389 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
390 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
391 | OUT_RING(DR4); | |
392 | OUT_RING(0); | |
393 | ADVANCE_LP_RING(); | |
394 | } | |
1da177e4 LT |
395 | |
396 | return 0; | |
397 | } | |
398 | ||
c29b669c AH |
399 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
400 | * emit. For now, do it in both places: | |
401 | */ | |
402 | ||
84b1fd10 | 403 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
404 | { |
405 | drm_i915_private_t *dev_priv = dev->dev_private; | |
406 | RING_LOCALS; | |
407 | ||
af6061af | 408 | dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter; |
c29b669c | 409 | |
af6061af DA |
410 | if (dev_priv->counter > 0x7FFFFFFFUL) |
411 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; | |
de227f5f DA |
412 | |
413 | BEGIN_LP_RING(4); | |
585fb111 JB |
414 | OUT_RING(MI_STORE_DWORD_INDEX); |
415 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); | |
de227f5f DA |
416 | OUT_RING(dev_priv->counter); |
417 | OUT_RING(0); | |
418 | ADVANCE_LP_RING(); | |
419 | } | |
420 | ||
84b1fd10 | 421 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
1da177e4 LT |
422 | drm_i915_cmdbuffer_t * cmd) |
423 | { | |
424 | int nbox = cmd->num_cliprects; | |
425 | int i = 0, count, ret; | |
426 | ||
427 | if (cmd->sz & 0x3) { | |
428 | DRM_ERROR("alignment"); | |
20caafa6 | 429 | return -EINVAL; |
1da177e4 LT |
430 | } |
431 | ||
432 | i915_kernel_lost_context(dev); | |
433 | ||
434 | count = nbox ? nbox : 1; | |
435 | ||
436 | for (i = 0; i < count; i++) { | |
437 | if (i < nbox) { | |
438 | ret = i915_emit_box(dev, cmd->cliprects, i, | |
439 | cmd->DR1, cmd->DR4); | |
440 | if (ret) | |
441 | return ret; | |
442 | } | |
443 | ||
444 | ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); | |
445 | if (ret) | |
446 | return ret; | |
447 | } | |
448 | ||
de227f5f | 449 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
450 | return 0; |
451 | } | |
452 | ||
84b1fd10 | 453 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
1da177e4 LT |
454 | drm_i915_batchbuffer_t * batch) |
455 | { | |
456 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 457 | struct drm_clip_rect __user *boxes = batch->cliprects; |
1da177e4 LT |
458 | int nbox = batch->num_cliprects; |
459 | int i = 0, count; | |
460 | RING_LOCALS; | |
461 | ||
462 | if ((batch->start | batch->used) & 0x7) { | |
463 | DRM_ERROR("alignment"); | |
20caafa6 | 464 | return -EINVAL; |
1da177e4 LT |
465 | } |
466 | ||
467 | i915_kernel_lost_context(dev); | |
468 | ||
469 | count = nbox ? nbox : 1; | |
470 | ||
471 | for (i = 0; i < count; i++) { | |
472 | if (i < nbox) { | |
473 | int ret = i915_emit_box(dev, boxes, i, | |
474 | batch->DR1, batch->DR4); | |
475 | if (ret) | |
476 | return ret; | |
477 | } | |
478 | ||
0790d5e1 | 479 | if (!IS_I830(dev) && !IS_845G(dev)) { |
1da177e4 | 480 | BEGIN_LP_RING(2); |
21f16289 DA |
481 | if (IS_I965G(dev)) { |
482 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
483 | OUT_RING(batch->start); | |
484 | } else { | |
485 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
486 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
487 | } | |
1da177e4 LT |
488 | ADVANCE_LP_RING(); |
489 | } else { | |
490 | BEGIN_LP_RING(4); | |
491 | OUT_RING(MI_BATCH_BUFFER); | |
492 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
493 | OUT_RING(batch->start + batch->used - 4); | |
494 | OUT_RING(0); | |
495 | ADVANCE_LP_RING(); | |
496 | } | |
497 | } | |
498 | ||
de227f5f | 499 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
500 | |
501 | return 0; | |
502 | } | |
503 | ||
af6061af | 504 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
505 | { |
506 | drm_i915_private_t *dev_priv = dev->dev_private; | |
507 | RING_LOCALS; | |
508 | ||
af6061af | 509 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", |
80a914dc | 510 | __func__, |
af6061af DA |
511 | dev_priv->current_page, |
512 | dev_priv->sarea_priv->pf_current_page); | |
1da177e4 | 513 | |
af6061af DA |
514 | i915_kernel_lost_context(dev); |
515 | ||
516 | BEGIN_LP_RING(2); | |
585fb111 | 517 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af DA |
518 | OUT_RING(0); |
519 | ADVANCE_LP_RING(); | |
1da177e4 | 520 | |
af6061af DA |
521 | BEGIN_LP_RING(6); |
522 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
523 | OUT_RING(0); | |
524 | if (dev_priv->current_page == 0) { | |
525 | OUT_RING(dev_priv->back_offset); | |
526 | dev_priv->current_page = 1; | |
1da177e4 | 527 | } else { |
af6061af DA |
528 | OUT_RING(dev_priv->front_offset); |
529 | dev_priv->current_page = 0; | |
1da177e4 | 530 | } |
af6061af DA |
531 | OUT_RING(0); |
532 | ADVANCE_LP_RING(); | |
1da177e4 | 533 | |
af6061af DA |
534 | BEGIN_LP_RING(2); |
535 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
536 | OUT_RING(0); | |
537 | ADVANCE_LP_RING(); | |
1da177e4 | 538 | |
af6061af | 539 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 LT |
540 | |
541 | BEGIN_LP_RING(4); | |
585fb111 JB |
542 | OUT_RING(MI_STORE_DWORD_INDEX); |
543 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); | |
af6061af DA |
544 | OUT_RING(dev_priv->counter); |
545 | OUT_RING(0); | |
1da177e4 LT |
546 | ADVANCE_LP_RING(); |
547 | ||
af6061af DA |
548 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
549 | return 0; | |
1da177e4 LT |
550 | } |
551 | ||
84b1fd10 | 552 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
553 | { |
554 | drm_i915_private_t *dev_priv = dev->dev_private; | |
555 | ||
556 | i915_kernel_lost_context(dev); | |
bf9d8929 | 557 | return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); |
1da177e4 LT |
558 | } |
559 | ||
c153f45f EA |
560 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
561 | struct drm_file *file_priv) | |
1da177e4 | 562 | { |
6c340eac | 563 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 LT |
564 | |
565 | return i915_quiescent(dev); | |
566 | } | |
567 | ||
c153f45f EA |
568 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
569 | struct drm_file *file_priv) | |
1da177e4 | 570 | { |
1da177e4 | 571 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
af6061af | 572 | u32 *hw_status = dev_priv->hw_status_page; |
1da177e4 LT |
573 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
574 | dev_priv->sarea_priv; | |
c153f45f | 575 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 LT |
576 | int ret; |
577 | ||
578 | if (!dev_priv->allow_batchbuffer) { | |
579 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 580 | return -EINVAL; |
1da177e4 LT |
581 | } |
582 | ||
1da177e4 | 583 | DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", |
c153f45f | 584 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 585 | |
6c340eac | 586 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 587 | |
c153f45f EA |
588 | if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, |
589 | batch->num_cliprects * | |
c60ce623 | 590 | sizeof(struct drm_clip_rect))) |
20caafa6 | 591 | return -EFAULT; |
1da177e4 | 592 | |
c153f45f | 593 | ret = i915_dispatch_batchbuffer(dev, batch); |
1da177e4 | 594 | |
af6061af | 595 | sarea_priv->last_dispatch = (int)hw_status[5]; |
1da177e4 LT |
596 | return ret; |
597 | } | |
598 | ||
c153f45f EA |
599 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
600 | struct drm_file *file_priv) | |
1da177e4 | 601 | { |
1da177e4 | 602 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
af6061af | 603 | u32 *hw_status = dev_priv->hw_status_page; |
1da177e4 LT |
604 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
605 | dev_priv->sarea_priv; | |
c153f45f | 606 | drm_i915_cmdbuffer_t *cmdbuf = data; |
1da177e4 LT |
607 | int ret; |
608 | ||
1da177e4 | 609 | DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
c153f45f | 610 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 611 | |
6c340eac | 612 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 613 | |
c153f45f EA |
614 | if (cmdbuf->num_cliprects && |
615 | DRM_VERIFYAREA_READ(cmdbuf->cliprects, | |
616 | cmdbuf->num_cliprects * | |
c60ce623 | 617 | sizeof(struct drm_clip_rect))) { |
1da177e4 | 618 | DRM_ERROR("Fault accessing cliprects\n"); |
20caafa6 | 619 | return -EFAULT; |
1da177e4 LT |
620 | } |
621 | ||
c153f45f | 622 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf); |
1da177e4 LT |
623 | if (ret) { |
624 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
625 | return ret; | |
626 | } | |
627 | ||
af6061af | 628 | sarea_priv->last_dispatch = (int)hw_status[5]; |
1da177e4 LT |
629 | return 0; |
630 | } | |
631 | ||
c153f45f EA |
632 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
633 | struct drm_file *file_priv) | |
1da177e4 | 634 | { |
80a914dc | 635 | DRM_DEBUG("%s\n", __func__); |
1da177e4 | 636 | |
6c340eac | 637 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 638 | |
af6061af | 639 | return i915_dispatch_flip(dev); |
1da177e4 LT |
640 | } |
641 | ||
c153f45f EA |
642 | static int i915_getparam(struct drm_device *dev, void *data, |
643 | struct drm_file *file_priv) | |
1da177e4 | 644 | { |
1da177e4 | 645 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 646 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
647 | int value; |
648 | ||
649 | if (!dev_priv) { | |
3e684eae | 650 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 651 | return -EINVAL; |
1da177e4 LT |
652 | } |
653 | ||
c153f45f | 654 | switch (param->param) { |
1da177e4 | 655 | case I915_PARAM_IRQ_ACTIVE: |
ed4cb414 | 656 | value = dev->irq_enabled; |
1da177e4 LT |
657 | break; |
658 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
659 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
660 | break; | |
0d6aa60b DA |
661 | case I915_PARAM_LAST_DISPATCH: |
662 | value = READ_BREADCRUMB(dev_priv); | |
663 | break; | |
1da177e4 | 664 | default: |
c153f45f | 665 | DRM_ERROR("Unknown parameter %d\n", param->param); |
20caafa6 | 666 | return -EINVAL; |
1da177e4 LT |
667 | } |
668 | ||
c153f45f | 669 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 670 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 671 | return -EFAULT; |
1da177e4 LT |
672 | } |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
c153f45f EA |
677 | static int i915_setparam(struct drm_device *dev, void *data, |
678 | struct drm_file *file_priv) | |
1da177e4 | 679 | { |
1da177e4 | 680 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 681 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
682 | |
683 | if (!dev_priv) { | |
3e684eae | 684 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 685 | return -EINVAL; |
1da177e4 LT |
686 | } |
687 | ||
c153f45f | 688 | switch (param->param) { |
1da177e4 | 689 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
690 | break; |
691 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 692 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
693 | break; |
694 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 695 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 LT |
696 | break; |
697 | default: | |
c153f45f | 698 | DRM_ERROR("unknown parameter %d\n", param->param); |
20caafa6 | 699 | return -EINVAL; |
1da177e4 LT |
700 | } |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
c153f45f EA |
705 | static int i915_set_status_page(struct drm_device *dev, void *data, |
706 | struct drm_file *file_priv) | |
dc7a9319 | 707 | { |
dc7a9319 | 708 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 709 | drm_i915_hws_addr_t *hws = data; |
b39d50e5 ZW |
710 | |
711 | if (!I915_NEED_GFX_HWS(dev)) | |
712 | return -EINVAL; | |
dc7a9319 WZ |
713 | |
714 | if (!dev_priv) { | |
3e684eae | 715 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 716 | return -EINVAL; |
dc7a9319 | 717 | } |
dc7a9319 | 718 | |
c153f45f EA |
719 | printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr); |
720 | ||
721 | dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); | |
dc7a9319 | 722 | |
8b409580 | 723 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
724 | dev_priv->hws_map.size = 4*1024; |
725 | dev_priv->hws_map.type = 0; | |
726 | dev_priv->hws_map.flags = 0; | |
727 | dev_priv->hws_map.mtrr = 0; | |
728 | ||
729 | drm_core_ioremap(&dev_priv->hws_map, dev); | |
730 | if (dev_priv->hws_map.handle == NULL) { | |
dc7a9319 WZ |
731 | i915_dma_cleanup(dev); |
732 | dev_priv->status_gfx_addr = 0; | |
733 | DRM_ERROR("can not ioremap virtual address for" | |
734 | " G33 hw status page\n"); | |
20caafa6 | 735 | return -ENOMEM; |
dc7a9319 WZ |
736 | } |
737 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | |
738 | ||
739 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
585fb111 JB |
740 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
741 | DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", | |
dc7a9319 WZ |
742 | dev_priv->status_gfx_addr); |
743 | DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); | |
744 | return 0; | |
745 | } | |
746 | ||
84b1fd10 | 747 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 748 | { |
ba8bbcf6 JB |
749 | struct drm_i915_private *dev_priv = dev->dev_private; |
750 | unsigned long base, size; | |
751 | int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; | |
752 | ||
22eae947 DA |
753 | /* i915 has 4 more counters */ |
754 | dev->counters += 4; | |
755 | dev->types[6] = _DRM_STAT_IRQ; | |
756 | dev->types[7] = _DRM_STAT_PRIMARY; | |
757 | dev->types[8] = _DRM_STAT_SECONDARY; | |
758 | dev->types[9] = _DRM_STAT_DMA; | |
759 | ||
ba8bbcf6 JB |
760 | dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); |
761 | if (dev_priv == NULL) | |
762 | return -ENOMEM; | |
763 | ||
764 | memset(dev_priv, 0, sizeof(drm_i915_private_t)); | |
765 | ||
766 | dev->dev_private = (void *)dev_priv; | |
767 | ||
768 | /* Add register map (needed for suspend/resume) */ | |
769 | base = drm_get_resource_start(dev, mmio_bar); | |
770 | size = drm_get_resource_len(dev, mmio_bar); | |
771 | ||
e3236a11 DA |
772 | ret = drm_addmap(dev, base, size, _DRM_REGISTERS, |
773 | _DRM_KERNEL | _DRM_DRIVER, | |
ba8bbcf6 | 774 | &dev_priv->mmio_map); |
ed4cb414 EA |
775 | |
776 | ||
777 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
778 | * integrated graphics even though the support isn't actually there | |
779 | * according to the published specs. It doesn't appear to function | |
780 | * correctly in testing on 945G. | |
781 | * This may be a side effect of MSI having been made available for PEG | |
782 | * and the registers being closely associated. | |
783 | */ | |
784 | if (!IS_I945G(dev) && !IS_I945GM(dev)) | |
785 | pci_enable_msi(dev->pdev); | |
786 | ||
787 | spin_lock_init(&dev_priv->user_irq_lock); | |
788 | ||
ba8bbcf6 JB |
789 | return ret; |
790 | } | |
791 | ||
792 | int i915_driver_unload(struct drm_device *dev) | |
793 | { | |
794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
795 | ||
ed4cb414 EA |
796 | if (dev->pdev->msi_enabled) |
797 | pci_disable_msi(dev->pdev); | |
798 | ||
ba8bbcf6 JB |
799 | if (dev_priv->mmio_map) |
800 | drm_rmmap(dev, dev_priv->mmio_map); | |
801 | ||
802 | drm_free(dev->dev_private, sizeof(drm_i915_private_t), | |
803 | DRM_MEM_DRIVER); | |
804 | ||
22eae947 DA |
805 | return 0; |
806 | } | |
807 | ||
84b1fd10 | 808 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 809 | { |
ba8bbcf6 JB |
810 | drm_i915_private_t *dev_priv = dev->dev_private; |
811 | ||
144a75fa DA |
812 | if (!dev_priv) |
813 | return; | |
814 | ||
ba8bbcf6 | 815 | if (dev_priv->agp_heap) |
b5e89ed5 | 816 | i915_mem_takedown(&(dev_priv->agp_heap)); |
ba8bbcf6 | 817 | |
b5e89ed5 | 818 | i915_dma_cleanup(dev); |
1da177e4 LT |
819 | } |
820 | ||
6c340eac | 821 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 822 | { |
ba8bbcf6 JB |
823 | drm_i915_private_t *dev_priv = dev->dev_private; |
824 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); | |
1da177e4 LT |
825 | } |
826 | ||
c153f45f EA |
827 | struct drm_ioctl_desc i915_ioctls[] = { |
828 | DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
829 | DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
830 | DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
831 | DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
832 | DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
833 | DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
834 | DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), | |
835 | DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
836 | DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), | |
837 | DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), | |
838 | DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
839 | DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), | |
840 | DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
841 | DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
842 | DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), | |
843 | DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
844 | DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH), | |
c94f7029 DA |
845 | }; |
846 | ||
847 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
848 | |
849 | /** | |
850 | * Determine if the device really is AGP or not. | |
851 | * | |
852 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
853 | * PCI-e. | |
854 | * | |
855 | * \param dev The device to be tested. | |
856 | * | |
857 | * \returns | |
858 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
859 | */ | |
84b1fd10 | 860 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
861 | { |
862 | return 1; | |
863 | } |