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drm/i915: Refine tracepoints
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_dma.c
CommitLineData
1da177e4
LT		 1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4
LT		 28
29#include "drmP.h"
30#include "drm.h"
79e53945 31#include "drm_crtc_helper.h"
785b93ef 32#include "drm_fb_helper.h"
79e53945 33#include "intel_drv.h"
1da177e4
LT		 34#include "i915_drm.h"
35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
63ee41d7 37#include "../../../platform/x86/intel_ips.h"
dcdb1674 38#include <linux/pci.h>
28d52043 39#include <linux/vgaarb.h>
c4804411
ZW		 40#include <linux/acpi.h>
41#include <linux/pnp.h>
6a9ee8af 42#include <linux/vga_switcheroo.h>
5a0e3ad6 43#include <linux/slab.h>
44834a67 44#include <acpi/video.h>
1da177e4 45
398c9cb2
KP		 46/**
47 * Sets up the hardware status page for devices that need a physical address
48 * in the register.
49 */
3043c60c 50static int i915_init_phys_hws(struct drm_device *dev)
398c9cb2
KP		 51{
52 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3
CW		 53 struct intel_ring_buffer *ring = LP_RING(dev_priv);
54
398c9cb2
KP		 55 /* Program Hardware Status Page */
56 dev_priv->status_page_dmah =
e6be8d9d 57 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
398c9cb2
KP		 58
59 if (!dev_priv->status_page_dmah) {
60 DRM_ERROR("Can not allocate hardware status page\n");
61 return -ENOMEM;
62 }
311bd68e
CW		 63 ring->status_page.page_addr =
64 (void __force __iomem *)dev_priv->status_page_dmah->vaddr;
398c9cb2
KP		 65 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
66
311bd68e 67 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
398c9cb2 68
a6c45cf0 69 if (INTEL_INFO(dev)->gen >= 4)
9b974cc1
ZW		 70 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
71 0xf0;
72
398c9cb2 73 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
8a4c47f3 74 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
398c9cb2
KP		 75 return 0;
76}
77
78/**
79 * Frees the hardware status page, whether it's a physical address or a virtual
80 * address set up by the X Server.
81 */
3043c60c 82static void i915_free_hws(struct drm_device *dev)
398c9cb2
KP		 83{
84 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3
CW		 85 struct intel_ring_buffer *ring = LP_RING(dev_priv);
86
398c9cb2
KP		 87 if (dev_priv->status_page_dmah) {
88 drm_pci_free(dev, dev_priv->status_page_dmah);
89 dev_priv->status_page_dmah = NULL;
90 }
91
1ec14ad3
CW		 92 if (ring->status_page.gfx_addr) {
93 ring->status_page.gfx_addr = 0;
398c9cb2
KP		 94 drm_core_ioremapfree(&dev_priv->hws_map, dev);
95 }
96
97 /* Need to rewrite hardware status page */
98 I915_WRITE(HWS_PGA, 0x1ffff000);
99}
100
84b1fd10 101void i915_kernel_lost_context(struct drm_device * dev)
1da177e4
LT		 102{
103 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 104 struct drm_i915_master_private *master_priv;
1ec14ad3 105 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 106
79e53945
JB		 107 /*
108 * We should never lose context on the ring with modesetting
109 * as we don't expose it to userspace
110 */
111 if (drm_core_check_feature(dev, DRIVER_MODESET))
112 return;
113
8168bd48
CW		 114 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
115 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
1da177e4
LT		 116 ring->space = ring->head - (ring->tail + 8);
117 if (ring->space < 0)
8187a2b7 118 ring->space += ring->size;
1da177e4 119
7c1c2871
DA		 120 if (!dev->primary->master)
121 return;
122
123 master_priv = dev->primary->master->driver_priv;
124 if (ring->head == ring->tail && master_priv->sarea_priv)
125 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
1da177e4
LT		 126}
127
84b1fd10 128static int i915_dma_cleanup(struct drm_device * dev)
1da177e4 129{
ba8bbcf6 130 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3
CW		 131 int i;
132
1da177e4
LT		 133 /* Make sure interrupts are disabled here because the uninstall ioctl
134 * may not have been called from userspace and after dev_private
135 * is freed, it's too late.
136 */
ed4cb414 137 if (dev->irq_enabled)
b5e89ed5 138 drm_irq_uninstall(dev);
1da177e4 139
ee0c6bfb 140 mutex_lock(&dev->struct_mutex);
1ec14ad3
CW		 141 for (i = 0; i < I915_NUM_RINGS; i++)
142 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
ee0c6bfb 143 mutex_unlock(&dev->struct_mutex);
dc7a9319 144
398c9cb2
KP		 145 /* Clear the HWS virtual address at teardown */
146 if (I915_NEED_GFX_HWS(dev))
147 i915_free_hws(dev);
1da177e4
LT		 148
149 return 0;
150}
151
ba8bbcf6 152static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
1da177e4 153{
ba8bbcf6 154 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 155 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
e8616b6c 156 int ret;
1da177e4 157
3a03ac1a
DA		 158 master_priv->sarea = drm_getsarea(dev);
159 if (master_priv->sarea) {
160 master_priv->sarea_priv = (drm_i915_sarea_t *)
161 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
162 } else {
8a4c47f3 163 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
3a03ac1a
DA		 164 }
165
673a394b 166 if (init->ring_size != 0) {
e8616b6c 167 if (LP_RING(dev_priv)->obj != NULL) {
673a394b
EA		 168 i915_dma_cleanup(dev);
169 DRM_ERROR("Client tried to initialize ringbuffer in "
170 "GEM mode\n");
171 return -EINVAL;
172 }
1da177e4 173
e8616b6c
CW		 174 ret = intel_render_ring_init_dri(dev,
175 init->ring_start,
176 init->ring_size);
177 if (ret) {
673a394b 178 i915_dma_cleanup(dev);
e8616b6c 179 return ret;
673a394b 180 }
1da177e4
LT		 181 }
182
a6b54f3f 183 dev_priv->cpp = init->cpp;
1da177e4
LT		 184 dev_priv->back_offset = init->back_offset;
185 dev_priv->front_offset = init->front_offset;
186 dev_priv->current_page = 0;
7c1c2871
DA		 187 if (master_priv->sarea_priv)
188 master_priv->sarea_priv->pf_current_page = 0;
1da177e4 189
1da177e4
LT		 190 /* Allow hardware batchbuffers unless told otherwise.
191 */
192 dev_priv->allow_batchbuffer = 1;
193
1da177e4
LT		 194 return 0;
195}
196
84b1fd10 197static int i915_dma_resume(struct drm_device * dev)
1da177e4
LT		 198{
199 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1ec14ad3 200 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 201
8a4c47f3 202 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 203
8187a2b7 204 if (ring->map.handle == NULL) {
1da177e4
LT		 205 DRM_ERROR("can not ioremap virtual address for"
206 " ring buffer\n");
20caafa6 207 return -ENOMEM;
1da177e4
LT		 208 }
209
210 /* Program Hardware Status Page */
8187a2b7 211 if (!ring->status_page.page_addr) {
1da177e4 212 DRM_ERROR("Can not find hardware status page\n");
20caafa6 213 return -EINVAL;
1da177e4 214 }
8a4c47f3 215 DRM_DEBUG_DRIVER("hw status page @ %p\n",
8187a2b7
ZN		 216 ring->status_page.page_addr);
217 if (ring->status_page.gfx_addr != 0)
78501eac 218 intel_ring_setup_status_page(ring);
dc7a9319 219 else
585fb111 220 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
8187a2b7 221
8a4c47f3 222 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
1da177e4
LT		 223
224 return 0;
225}
226
c153f45f
EA		 227static int i915_dma_init(struct drm_device *dev, void *data,
228 struct drm_file *file_priv)
1da177e4 229{
c153f45f 230 drm_i915_init_t *init = data;
1da177e4
LT		 231 int retcode = 0;
232
c153f45f 233 switch (init->func) {
1da177e4 234 case I915_INIT_DMA:
ba8bbcf6 235 retcode = i915_initialize(dev, init);
1da177e4
LT		 236 break;
237 case I915_CLEANUP_DMA:
238 retcode = i915_dma_cleanup(dev);
239 break;
240 case I915_RESUME_DMA:
0d6aa60b 241 retcode = i915_dma_resume(dev);
1da177e4
LT		 242 break;
243 default:
20caafa6 244 retcode = -EINVAL;
1da177e4
LT		 245 break;
246 }
247
248 return retcode;
249}
250
251/* Implement basically the same security restrictions as hardware does
252 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
253 *
254 * Most of the calculations below involve calculating the size of a
255 * particular instruction. It's important to get the size right as
256 * that tells us where the next instruction to check is. Any illegal
257 * instruction detected will be given a size of zero, which is a
258 * signal to abort the rest of the buffer.
259 */
e1f99ce6 260static int validate_cmd(int cmd)
1da177e4
LT		 261{
262 switch (((cmd >> 29) & 0x7)) {
263 case 0x0:
264 switch ((cmd >> 23) & 0x3f) {
265 case 0x0:
266 return 1; /* MI_NOOP */
267 case 0x4:
268 return 1; /* MI_FLUSH */
269 default:
270 return 0; /* disallow everything else */
271 }
272 break;
273 case 0x1:
274 return 0; /* reserved */
275 case 0x2:
276 return (cmd & 0xff) + 2; /* 2d commands */
277 case 0x3:
278 if (((cmd >> 24) & 0x1f) <= 0x18)
279 return 1;
280
281 switch ((cmd >> 24) & 0x1f) {
282 case 0x1c:
283 return 1;
284 case 0x1d:
b5e89ed5 285 switch ((cmd >> 16) & 0xff) {
1da177e4
LT		 286 case 0x3:
287 return (cmd & 0x1f) + 2;
288 case 0x4:
289 return (cmd & 0xf) + 2;
290 default:
291 return (cmd & 0xffff) + 2;
292 }
293 case 0x1e:
294 if (cmd & (1 << 23))
295 return (cmd & 0xffff) + 1;
296 else
297 return 1;
298 case 0x1f:
299 if ((cmd & (1 << 23)) == 0) /* inline vertices */
300 return (cmd & 0x1ffff) + 2;
301 else if (cmd & (1 << 17)) /* indirect random */
302 if ((cmd & 0xffff) == 0)
303 return 0; /* unknown length, too hard */
304 else
305 return (((cmd & 0xffff) + 1) / 2) + 1;
306 else
307 return 2; /* indirect sequential */
308 default:
309 return 0;
310 }
311 default:
312 return 0;
313 }
314
315 return 0;
316}
317
201361a5 318static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
1da177e4
LT		 319{
320 drm_i915_private_t *dev_priv = dev->dev_private;
e1f99ce6 321 int i, ret;
1da177e4 322
1ec14ad3 323 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
20caafa6 324 return -EINVAL;
de227f5f 325
1da177e4 326 for (i = 0; i < dwords;) {
e1f99ce6
CW		 327 int sz = validate_cmd(buffer[i]);
328 if (sz == 0 || i + sz > dwords)
20caafa6 329 return -EINVAL;
e1f99ce6 330 i += sz;
1da177e4
LT		 331 }
332
e1f99ce6
CW		 333 ret = BEGIN_LP_RING((dwords+1)&~1);
334 if (ret)
335 return ret;
336
337 for (i = 0; i < dwords; i++)
338 OUT_RING(buffer[i]);
de227f5f
DA		 339 if (dwords & 1)
340 OUT_RING(0);
341
342 ADVANCE_LP_RING();
343
1da177e4
LT		 344 return 0;
345}
346
673a394b
EA		 347int
348i915_emit_box(struct drm_device *dev,
c4e7a414
CW		 349 struct drm_clip_rect *box,
350 int DR1, int DR4)
1da177e4 351{
e1f99ce6 352 struct drm_i915_private *dev_priv = dev->dev_private;
e1f99ce6 353 int ret;
1da177e4 354
c4e7a414
CW		 355 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
356 box->y2 <= 0 || box->x2 <= 0) {
1da177e4 357 DRM_ERROR("Bad box %d,%d..%d,%d\n",
c4e7a414 358 box->x1, box->y1, box->x2, box->y2);
20caafa6 359 return -EINVAL;
1da177e4
LT		 360 }
361
a6c45cf0 362 if (INTEL_INFO(dev)->gen >= 4) {
e1f99ce6
CW		 363 ret = BEGIN_LP_RING(4);
364 if (ret)
365 return ret;
366
c29b669c 367 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
c4e7a414
CW		 368 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
369 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
c29b669c 370 OUT_RING(DR4);
c29b669c 371 } else {
e1f99ce6
CW		 372 ret = BEGIN_LP_RING(6);
373 if (ret)
374 return ret;
375
c29b669c
AH		 376 OUT_RING(GFX_OP_DRAWRECT_INFO);
377 OUT_RING(DR1);
c4e7a414
CW		 378 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
379 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
c29b669c
AH		 380 OUT_RING(DR4);
381 OUT_RING(0);
c29b669c 382 }
e1f99ce6 383 ADVANCE_LP_RING();
1da177e4
LT		 384
385 return 0;
386}
387
c29b669c
AH		 388/* XXX: Emitting the counter should really be moved to part of the IRQ
389 * emit. For now, do it in both places:
390 */
391
84b1fd10 392static void i915_emit_breadcrumb(struct drm_device *dev)
de227f5f
DA		 393{
394 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 395 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
de227f5f 396
c99b058f 397 dev_priv->counter++;
af6061af 398 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 399 dev_priv->counter = 0;
7c1c2871
DA		 400 if (master_priv->sarea_priv)
401 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
de227f5f 402
e1f99ce6
CW		 403 if (BEGIN_LP_RING(4) == 0) {
404 OUT_RING(MI_STORE_DWORD_INDEX);
405 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
406 OUT_RING(dev_priv->counter);
407 OUT_RING(0);
408 ADVANCE_LP_RING();
409 }
de227f5f
DA		 410}
411
84b1fd10 412static int i915_dispatch_cmdbuffer(struct drm_device * dev,
201361a5
EA		 413 drm_i915_cmdbuffer_t *cmd,
414 struct drm_clip_rect *cliprects,
415 void *cmdbuf)
1da177e4
LT		 416{
417 int nbox = cmd->num_cliprects;
418 int i = 0, count, ret;
419
420 if (cmd->sz & 0x3) {
421 DRM_ERROR("alignment");
20caafa6 422 return -EINVAL;
1da177e4
LT		 423 }
424
425 i915_kernel_lost_context(dev);
426
427 count = nbox ? nbox : 1;
428
429 for (i = 0; i < count; i++) {
430 if (i < nbox) {
c4e7a414 431 ret = i915_emit_box(dev, &cliprects[i],
1da177e4
LT		 432 cmd->DR1, cmd->DR4);
433 if (ret)
434 return ret;
435 }
436
201361a5 437 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
1da177e4
LT		 438 if (ret)
439 return ret;
440 }
441
de227f5f 442 i915_emit_breadcrumb(dev);
1da177e4
LT		 443 return 0;
444}
445
84b1fd10 446static int i915_dispatch_batchbuffer(struct drm_device * dev,
201361a5
EA		 447 drm_i915_batchbuffer_t * batch,
448 struct drm_clip_rect *cliprects)
1da177e4 449{
e1f99ce6 450 struct drm_i915_private *dev_priv = dev->dev_private;
1da177e4 451 int nbox = batch->num_cliprects;
e1f99ce6 452 int i, count, ret;
1da177e4
LT		 453
454 if ((batch->start | batch->used) & 0x7) {
455 DRM_ERROR("alignment");
20caafa6 456 return -EINVAL;
1da177e4
LT		 457 }
458
459 i915_kernel_lost_context(dev);
460
461 count = nbox ? nbox : 1;
1da177e4
LT		 462 for (i = 0; i < count; i++) {
463 if (i < nbox) {
c4e7a414 464 ret = i915_emit_box(dev, &cliprects[i],
e1f99ce6 465 batch->DR1, batch->DR4);
1da177e4
LT		 466 if (ret)
467 return ret;
468 }
469
0790d5e1 470 if (!IS_I830(dev) && !IS_845G(dev)) {
e1f99ce6
CW		 471 ret = BEGIN_LP_RING(2);
472 if (ret)
473 return ret;
474
a6c45cf0 475 if (INTEL_INFO(dev)->gen >= 4) {
21f16289
DA		 476 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
477 OUT_RING(batch->start);
478 } else {
479 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
480 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
481 }
1da177e4 482 } else {
e1f99ce6
CW		 483 ret = BEGIN_LP_RING(4);
484 if (ret)
485 return ret;
486
1da177e4
LT		 487 OUT_RING(MI_BATCH_BUFFER);
488 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
489 OUT_RING(batch->start + batch->used - 4);
490 OUT_RING(0);
1da177e4 491 }
e1f99ce6 492 ADVANCE_LP_RING();
1da177e4
LT		 493 }
494
1cafd347 495
f00a3ddf 496 if (IS_G4X(dev) || IS_GEN5(dev)) {
e1f99ce6
CW		 497 if (BEGIN_LP_RING(2) == 0) {
498 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
499 OUT_RING(MI_NOOP);
500 ADVANCE_LP_RING();
501 }
1cafd347 502 }
1da177e4 503
e1f99ce6 504 i915_emit_breadcrumb(dev);
1da177e4
LT		 505 return 0;
506}
507
af6061af 508static int i915_dispatch_flip(struct drm_device * dev)
1da177e4
LT		 509{
510 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871
DA		 511 struct drm_i915_master_private *master_priv =
512 dev->primary->master->driver_priv;
e1f99ce6 513 int ret;
1da177e4 514
7c1c2871 515 if (!master_priv->sarea_priv)
c99b058f
KH		 516 return -EINVAL;
517
8a4c47f3 518 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
be25ed9c 519 __func__,
520 dev_priv->current_page,
521 master_priv->sarea_priv->pf_current_page);
1da177e4 522
af6061af
DA		 523 i915_kernel_lost_context(dev);
524
e1f99ce6
CW		 525 ret = BEGIN_LP_RING(10);
526 if (ret)
527 return ret;
528
585fb111 529 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
af6061af 530 OUT_RING(0);
1da177e4 531
af6061af
DA		 532 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
533 OUT_RING(0);
534 if (dev_priv->current_page == 0) {
535 OUT_RING(dev_priv->back_offset);
536 dev_priv->current_page = 1;
1da177e4 537 } else {
af6061af
DA		 538 OUT_RING(dev_priv->front_offset);
539 dev_priv->current_page = 0;
1da177e4 540 }
af6061af 541 OUT_RING(0);
1da177e4 542
af6061af
DA		 543 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
544 OUT_RING(0);
e1f99ce6 545
af6061af 546 ADVANCE_LP_RING();
1da177e4 547
7c1c2871 548 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
1da177e4 549
e1f99ce6
CW		 550 if (BEGIN_LP_RING(4) == 0) {
551 OUT_RING(MI_STORE_DWORD_INDEX);
552 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
553 OUT_RING(dev_priv->counter);
554 OUT_RING(0);
555 ADVANCE_LP_RING();
556 }
1da177e4 557
7c1c2871 558 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
af6061af 559 return 0;
1da177e4
LT		 560}
561
1ec14ad3 562static int i915_quiescent(struct drm_device *dev)
1da177e4 563{
1ec14ad3 564 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
1da177e4
LT		 565
566 i915_kernel_lost_context(dev);
1ec14ad3 567 return intel_wait_ring_buffer(ring, ring->size - 8);
1da177e4
LT		 568}
569
c153f45f
EA		 570static int i915_flush_ioctl(struct drm_device *dev, void *data,
571 struct drm_file *file_priv)
1da177e4 572{
546b0974
EA		 573 int ret;
574
575 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 576
546b0974
EA		 577 mutex_lock(&dev->struct_mutex);
578 ret = i915_quiescent(dev);
579 mutex_unlock(&dev->struct_mutex);
580
581 return ret;
1da177e4
LT		 582}
583
c153f45f
EA		 584static int i915_batchbuffer(struct drm_device *dev, void *data,
585 struct drm_file *file_priv)
1da177e4 586{
1da177e4 587 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 588 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 589 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 590 master_priv->sarea_priv;
c153f45f 591 drm_i915_batchbuffer_t *batch = data;
1da177e4 592 int ret;
201361a5 593 struct drm_clip_rect *cliprects = NULL;
1da177e4
LT		 594
595 if (!dev_priv->allow_batchbuffer) {
596 DRM_ERROR("Batchbuffer ioctl disabled\n");
20caafa6 597 return -EINVAL;
1da177e4
LT		 598 }
599
8a4c47f3 600 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
be25ed9c 601 batch->start, batch->used, batch->num_cliprects);
1da177e4 602
546b0974 603 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 604
201361a5
EA		 605 if (batch->num_cliprects < 0)
606 return -EINVAL;
607
608 if (batch->num_cliprects) {
9a298b2a
EA		 609 cliprects = kcalloc(batch->num_cliprects,
610 sizeof(struct drm_clip_rect),
611 GFP_KERNEL);
201361a5
EA		 612 if (cliprects == NULL)
613 return -ENOMEM;
614
615 ret = copy_from_user(cliprects, batch->cliprects,
616 batch->num_cliprects *
617 sizeof(struct drm_clip_rect));
9927a403
DC		 618 if (ret != 0) {
619 ret = -EFAULT;
201361a5 620 goto fail_free;
9927a403 621 }
201361a5 622 }
1da177e4 623
546b0974 624 mutex_lock(&dev->struct_mutex);
201361a5 625 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
546b0974 626 mutex_unlock(&dev->struct_mutex);
1da177e4 627
c99b058f 628 if (sarea_priv)
0baf823a 629 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5
EA		 630
631fail_free:
9a298b2a 632 kfree(cliprects);
201361a5 633
1da177e4
LT		 634 return ret;
635}
636
c153f45f
EA		 637static int i915_cmdbuffer(struct drm_device *dev, void *data,
638 struct drm_file *file_priv)
1da177e4 639{
1da177e4 640 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 641 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 642 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 643 master_priv->sarea_priv;
c153f45f 644 drm_i915_cmdbuffer_t *cmdbuf = data;
201361a5
EA		 645 struct drm_clip_rect *cliprects = NULL;
646 void *batch_data;
1da177e4
LT		 647 int ret;
648
8a4c47f3 649 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
be25ed9c 650 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
1da177e4 651
546b0974 652 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 653
201361a5
EA		 654 if (cmdbuf->num_cliprects < 0)
655 return -EINVAL;
656
9a298b2a 657 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
201361a5
EA		 658 if (batch_data == NULL)
659 return -ENOMEM;
660
661 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
9927a403
DC		 662 if (ret != 0) {
663 ret = -EFAULT;
201361a5 664 goto fail_batch_free;
9927a403 665 }
201361a5
EA		 666
667 if (cmdbuf->num_cliprects) {
9a298b2a
EA		 668 cliprects = kcalloc(cmdbuf->num_cliprects,
669 sizeof(struct drm_clip_rect), GFP_KERNEL);
a40e8d31
OA		 670 if (cliprects == NULL) {
671 ret = -ENOMEM;
201361a5 672 goto fail_batch_free;
a40e8d31 673 }
201361a5
EA		 674
675 ret = copy_from_user(cliprects, cmdbuf->cliprects,
676 cmdbuf->num_cliprects *
677 sizeof(struct drm_clip_rect));
9927a403
DC		 678 if (ret != 0) {
679 ret = -EFAULT;
201361a5 680 goto fail_clip_free;
9927a403 681 }
1da177e4
LT		 682 }
683
546b0974 684 mutex_lock(&dev->struct_mutex);
201361a5 685 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
546b0974 686 mutex_unlock(&dev->struct_mutex);
1da177e4
LT		 687 if (ret) {
688 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
355d7f37 689 goto fail_clip_free;
1da177e4
LT		 690 }
691
c99b058f 692 if (sarea_priv)
0baf823a 693 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5 694
201361a5 695fail_clip_free:
9a298b2a 696 kfree(cliprects);
355d7f37 697fail_batch_free:
9a298b2a 698 kfree(batch_data);
201361a5
EA		 699
700 return ret;
1da177e4
LT		 701}
702
c153f45f
EA		 703static int i915_flip_bufs(struct drm_device *dev, void *data,
704 struct drm_file *file_priv)
1da177e4 705{
546b0974
EA		 706 int ret;
707
8a4c47f3 708 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 709
546b0974 710 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 711
546b0974
EA		 712 mutex_lock(&dev->struct_mutex);
713 ret = i915_dispatch_flip(dev);
714 mutex_unlock(&dev->struct_mutex);
715
716 return ret;
1da177e4
LT		 717}
718
c153f45f
EA		 719static int i915_getparam(struct drm_device *dev, void *data,
720 struct drm_file *file_priv)
1da177e4 721{
1da177e4 722 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 723 drm_i915_getparam_t *param = data;
1da177e4
LT		 724 int value;
725
726 if (!dev_priv) {
3e684eae 727 DRM_ERROR("called with no initialization\n");
20caafa6 728 return -EINVAL;
1da177e4
LT		 729 }
730
c153f45f 731 switch (param->param) {
1da177e4 732 case I915_PARAM_IRQ_ACTIVE:
0a3e67a4 733 value = dev->pdev->irq ? 1 : 0;
1da177e4
LT		 734 break;
735 case I915_PARAM_ALLOW_BATCHBUFFER:
736 value = dev_priv->allow_batchbuffer ? 1 : 0;
737 break;
0d6aa60b
DA		 738 case I915_PARAM_LAST_DISPATCH:
739 value = READ_BREADCRUMB(dev_priv);
740 break;
ed4c9c4a
KH		 741 case I915_PARAM_CHIPSET_ID:
742 value = dev->pci_device;
743 break;
673a394b 744 case I915_PARAM_HAS_GEM:
ac5c4e76 745 value = dev_priv->has_gem;
673a394b 746 break;
0f973f27
JB		 747 case I915_PARAM_NUM_FENCES_AVAIL:
748 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
749 break;
02e792fb
DV		 750 case I915_PARAM_HAS_OVERLAY:
751 value = dev_priv->overlay ? 1 : 0;
752 break;
e9560f7c
JB		 753 case I915_PARAM_HAS_PAGEFLIPPING:
754 value = 1;
755 break;
76446cac
JB		 756 case I915_PARAM_HAS_EXECBUF2:
757 /* depends on GEM */
758 value = dev_priv->has_gem;
759 break;
e3a815fc
ZN		 760 case I915_PARAM_HAS_BSD:
761 value = HAS_BSD(dev);
762 break;
549f7365
CW		 763 case I915_PARAM_HAS_BLT:
764 value = HAS_BLT(dev);
765 break;
a00b10c3
CW		 766 case I915_PARAM_HAS_RELAXED_FENCING:
767 value = 1;
768 break;
bbf0c6b3
DV		 769 case I915_PARAM_HAS_COHERENT_RINGS:
770 value = 1;
771 break;
72bfa19c
CW		 772 case I915_PARAM_HAS_EXEC_CONSTANTS:
773 value = INTEL_INFO(dev)->gen >= 4;
774 break;
1da177e4 775 default:
8a4c47f3 776 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
76446cac 777 param->param);
20caafa6 778 return -EINVAL;
1da177e4
LT		 779 }
780
c153f45f 781 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1da177e4 782 DRM_ERROR("DRM_COPY_TO_USER failed\n");
20caafa6 783 return -EFAULT;
1da177e4
LT		 784 }
785
786 return 0;
787}
788
c153f45f
EA		 789static int i915_setparam(struct drm_device *dev, void *data,
790 struct drm_file *file_priv)
1da177e4 791{
1da177e4 792 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 793 drm_i915_setparam_t *param = data;
1da177e4
LT		 794
795 if (!dev_priv) {
3e684eae 796 DRM_ERROR("called with no initialization\n");
20caafa6 797 return -EINVAL;
1da177e4
LT		 798 }
799
c153f45f 800 switch (param->param) {
1da177e4 801 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1da177e4
LT		 802 break;
803 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
c153f45f 804 dev_priv->tex_lru_log_granularity = param->value;
1da177e4
LT		 805 break;
806 case I915_SETPARAM_ALLOW_BATCHBUFFER:
c153f45f 807 dev_priv->allow_batchbuffer = param->value;
1da177e4 808 break;
0f973f27
JB		 809 case I915_SETPARAM_NUM_USED_FENCES:
810 if (param->value > dev_priv->num_fence_regs ||
811 param->value < 0)
812 return -EINVAL;
813 /* Userspace can use first N regs */
814 dev_priv->fence_reg_start = param->value;
815 break;
1da177e4 816 default:
8a4c47f3 817 DRM_DEBUG_DRIVER("unknown parameter %d\n",
be25ed9c 818 param->param);
20caafa6 819 return -EINVAL;
1da177e4
LT		 820 }
821
822 return 0;
823}
824
c153f45f
EA		 825static int i915_set_status_page(struct drm_device *dev, void *data,
826 struct drm_file *file_priv)
dc7a9319 827{
dc7a9319 828 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 829 drm_i915_hws_addr_t *hws = data;
1ec14ad3 830 struct intel_ring_buffer *ring = LP_RING(dev_priv);
b39d50e5
ZW		 831
832 if (!I915_NEED_GFX_HWS(dev))
833 return -EINVAL;
dc7a9319
WZ		 834
835 if (!dev_priv) {
3e684eae 836 DRM_ERROR("called with no initialization\n");
20caafa6 837 return -EINVAL;
dc7a9319 838 }
dc7a9319 839
79e53945
JB		 840 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
841 WARN(1, "tried to set status page when mode setting active\n");
842 return 0;
843 }
844
8a4c47f3 845 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
c153f45f 846
8187a2b7 847 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
dc7a9319 848
8b409580 849 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
dc7a9319
WZ		 850 dev_priv->hws_map.size = 4*1024;
851 dev_priv->hws_map.type = 0;
852 dev_priv->hws_map.flags = 0;
853 dev_priv->hws_map.mtrr = 0;
854
dd0910b3 855 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
dc7a9319 856 if (dev_priv->hws_map.handle == NULL) {
dc7a9319 857 i915_dma_cleanup(dev);
e20f9c64 858 ring->status_page.gfx_addr = 0;
dc7a9319
WZ		 859 DRM_ERROR("can not ioremap virtual address for"
860 " G33 hw status page\n");
20caafa6 861 return -ENOMEM;
dc7a9319 862 }
311bd68e
CW		 863 ring->status_page.page_addr =
864 (void __force __iomem *)dev_priv->hws_map.handle;
865 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
8187a2b7 866 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
dc7a9319 867
8a4c47f3 868 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
e20f9c64 869 ring->status_page.gfx_addr);
8a4c47f3 870 DRM_DEBUG_DRIVER("load hws at %p\n",
e20f9c64 871 ring->status_page.page_addr);
dc7a9319
WZ		 872 return 0;
873}
874
ec2a4c3f
DA		 875static int i915_get_bridge_dev(struct drm_device *dev)
876{
877 struct drm_i915_private *dev_priv = dev->dev_private;
878
879 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
880 if (!dev_priv->bridge_dev) {
881 DRM_ERROR("bridge device not found\n");
882 return -1;
883 }
884 return 0;
885}
886
c4804411
ZW		 887#define MCHBAR_I915 0x44
888#define MCHBAR_I965 0x48
889#define MCHBAR_SIZE (4*4096)
890
891#define DEVEN_REG 0x54
892#define DEVEN_MCHBAR_EN (1 << 28)
893
894/* Allocate space for the MCH regs if needed, return nonzero on error */
895static int
896intel_alloc_mchbar_resource(struct drm_device *dev)
897{
898 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 899 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
c4804411
ZW		 900 u32 temp_lo, temp_hi = 0;
901 u64 mchbar_addr;
a25c25c2 902 int ret;
c4804411 903
a6c45cf0 904 if (INTEL_INFO(dev)->gen >= 4)
c4804411
ZW		 905 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
906 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
907 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
908
909 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
910#ifdef CONFIG_PNP
911 if (mchbar_addr &&
a25c25c2
CW		 912 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
913 return 0;
c4804411
ZW		 914#endif
915
916 /* Get some space for it */
a25c25c2
CW		 917 dev_priv->mch_res.name = "i915 MCHBAR";
918 dev_priv->mch_res.flags = IORESOURCE_MEM;
919 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
920 &dev_priv->mch_res,
c4804411
ZW		 921 MCHBAR_SIZE, MCHBAR_SIZE,
922 PCIBIOS_MIN_MEM,
a25c25c2 923 0, pcibios_align_resource,
c4804411
ZW		 924 dev_priv->bridge_dev);
925 if (ret) {
926 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
927 dev_priv->mch_res.start = 0;
a25c25c2 928 return ret;
c4804411
ZW		 929 }
930
a6c45cf0 931 if (INTEL_INFO(dev)->gen >= 4)
c4804411
ZW		 932 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
933 upper_32_bits(dev_priv->mch_res.start));
934
935 pci_write_config_dword(dev_priv->bridge_dev, reg,
936 lower_32_bits(dev_priv->mch_res.start));
a25c25c2 937 return 0;
c4804411
ZW		 938}
939
940/* Setup MCHBAR if possible, return true if we should disable it again */
941static void
942intel_setup_mchbar(struct drm_device *dev)
943{
944 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 945 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
c4804411
ZW		 946 u32 temp;
947 bool enabled;
948
949 dev_priv->mchbar_need_disable = false;
950
951 if (IS_I915G(dev) || IS_I915GM(dev)) {
952 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
953 enabled = !!(temp & DEVEN_MCHBAR_EN);
954 } else {
955 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
956 enabled = temp & 1;
957 }
958
959 /* If it's already enabled, don't have to do anything */
960 if (enabled)
961 return;
962
963 if (intel_alloc_mchbar_resource(dev))
964 return;
965
966 dev_priv->mchbar_need_disable = true;
967
968 /* Space is allocated or reserved, so enable it. */
969 if (IS_I915G(dev) || IS_I915GM(dev)) {
970 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
971 temp | DEVEN_MCHBAR_EN);
972 } else {
973 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
974 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
975 }
976}
977
978static void
979intel_teardown_mchbar(struct drm_device *dev)
980{
981 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 982 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
c4804411
ZW		 983 u32 temp;
984
985 if (dev_priv->mchbar_need_disable) {
986 if (IS_I915G(dev) || IS_I915GM(dev)) {
987 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
988 temp &= ~DEVEN_MCHBAR_EN;
989 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
990 } else {
991 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
992 temp &= ~1;
993 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
994 }
995 }
996
997 if (dev_priv->mch_res.start)
998 release_resource(&dev_priv->mch_res);
999}
1000
80824003
JB		 1001#define PTE_ADDRESS_MASK 0xfffff000
1002#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1003#define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1004#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1005#define PTE_MAPPING_TYPE_CACHED (3 << 1)
1006#define PTE_MAPPING_TYPE_MASK (3 << 1)
1007#define PTE_VALID (1 << 0)
1008
1009/**
fe669bf8
CW		 1010 * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1011 * a physical one
80824003 1012 * @dev: drm device
fe669bf8 1013 * @offset: address to translate
80824003 1014 *
fe669bf8
CW		 1015 * Some chip functions require allocations from stolen space and need the
1016 * physical address of the memory in question.
80824003 1017 */
fe669bf8 1018static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
80824003 1019{
fe669bf8
CW		 1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 struct pci_dev *pdev = dev_priv->bridge_dev;
1022 u32 base;
1023
1024#if 0
1025 /* On the machines I have tested the Graphics Base of Stolen Memory
1026 * is unreliable, so compute the base by subtracting the stolen memory
1027 * from the Top of Low Usable DRAM which is where the BIOS places
1028 * the graphics stolen memory.
1029 */
1030 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1031 /* top 32bits are reserved = 0 */
1032 pci_read_config_dword(pdev, 0xA4, &base);
80824003 1033 } else {
fe669bf8
CW		 1034 /* XXX presume 8xx is the same as i915 */
1035 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1036 }
1037#else
1038 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1039 u16 val;
1040 pci_read_config_word(pdev, 0xb0, &val);
1041 base = val >> 4 << 20;
1042 } else {
1043 u8 val;
1044 pci_read_config_byte(pdev, 0x9c, &val);
1045 base = val >> 3 << 27;
80824003 1046 }
c64f7ba5 1047 base -= dev_priv->mm.gtt->stolen_size;
fe669bf8 1048#endif
80824003 1049
fe669bf8 1050 return base + offset;
80824003
JB		 1051}
1052
1053static void i915_warn_stolen(struct drm_device *dev)
1054{
1055 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1056 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1057}
1058
1059static void i915_setup_compression(struct drm_device *dev, int size)
1060{
1061 struct drm_i915_private *dev_priv = dev->dev_private;
132b6aab 1062 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
29bd0ae2
AM		 1063 unsigned long cfb_base;
1064 unsigned long ll_base = 0;
80824003 1065
fe669bf8
CW		 1066 compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1067 if (compressed_fb)
1068 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1069 if (!compressed_fb)
1070 goto err;
80824003 1071
fe669bf8
CW		 1072 cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1073 if (!cfb_base)
1074 goto err_fb;
80824003 1075
9c04f015 1076 if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
fe669bf8
CW		 1077 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1078 4096, 4096, 0);
1079 if (compressed_llb)
1080 compressed_llb = drm_mm_get_block(compressed_llb,
1081 4096, 4096);
1082 if (!compressed_llb)
1083 goto err_fb;
74dff282 1084
fe669bf8
CW		 1085 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1086 if (!ll_base)
1087 goto err_llb;
80824003
JB		 1088 }
1089
1090 dev_priv->cfb_size = size;
1091
ee5382ae 1092 intel_disable_fbc(dev);
20bf377e 1093 dev_priv->compressed_fb = compressed_fb;
9c04f015 1094 if (HAS_PCH_SPLIT(dev))
b52eb4dc
ZY		 1095 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1096 else if (IS_GM45(dev)) {
74dff282
JB		 1097 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1098 } else {
74dff282
JB		 1099 I915_WRITE(FBC_CFB_BASE, cfb_base);
1100 I915_WRITE(FBC_LL_BASE, ll_base);
20bf377e 1101 dev_priv->compressed_llb = compressed_llb;
80824003
JB		 1102 }
1103
fe669bf8
CW		 1104 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1105 cfb_base, ll_base, size >> 20);
1106 return;
1107
1108err_llb:
1109 drm_mm_put_block(compressed_llb);
1110err_fb:
1111 drm_mm_put_block(compressed_fb);
1112err:
1113 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1114 i915_warn_stolen(dev);
80824003
JB		 1115}
1116
20bf377e
JB		 1117static void i915_cleanup_compression(struct drm_device *dev)
1118{
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120
1121 drm_mm_put_block(dev_priv->compressed_fb);
aebf0daf 1122 if (dev_priv->compressed_llb)
20bf377e
JB		 1123 drm_mm_put_block(dev_priv->compressed_llb);
1124}
1125
28d52043
DA		 1126/* true = enable decode, false = disable decoder */
1127static unsigned int i915_vga_set_decode(void *cookie, bool state)
1128{
1129 struct drm_device *dev = cookie;
1130
1131 intel_modeset_vga_set_state(dev, state);
1132 if (state)
1133 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1134 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1135 else
1136 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1137}
1138
6a9ee8af
DA		 1139static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1140{
1141 struct drm_device *dev = pci_get_drvdata(pdev);
1142 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1143 if (state == VGA_SWITCHEROO_ON) {
fbf81762 1144 printk(KERN_INFO "i915: switched on\n");
5bcf719b 1145 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
6a9ee8af
DA		 1146 /* i915 resume handler doesn't set to D0 */
1147 pci_set_power_state(dev->pdev, PCI_D0);
1148 i915_resume(dev);
5bcf719b 1149 dev->switch_power_state = DRM_SWITCH_POWER_ON;
6a9ee8af
DA		 1150 } else {
1151 printk(KERN_ERR "i915: switched off\n");
5bcf719b 1152 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
6a9ee8af 1153 i915_suspend(dev, pmm);
5bcf719b 1154 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
6a9ee8af
DA		 1155 }
1156}
1157
1158static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1159{
1160 struct drm_device *dev = pci_get_drvdata(pdev);
1161 bool can_switch;
1162
1163 spin_lock(&dev->count_lock);
1164 can_switch = (dev->open_count == 0);
1165 spin_unlock(&dev->count_lock);
1166 return can_switch;
1167}
1168
53984635 1169static int i915_load_modeset_init(struct drm_device *dev)
79e53945
JB		 1170{
1171 struct drm_i915_private *dev_priv = dev->dev_private;
53984635 1172 unsigned long prealloc_size, gtt_size, mappable_size;
79e53945
JB		 1173 int ret = 0;
1174
c64f7ba5 1175 prealloc_size = dev_priv->mm.gtt->stolen_size;
53984635
DV		 1176 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1177 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
53984635 1178
fe669bf8
CW		 1179 /* Basic memrange allocator for stolen space */
1180 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
79e53945 1181
fe669bf8 1182 /* Let GEM Manage all of the aperture.
13f4c435
EA		 1183 *
1184 * However, leave one page at the end still bound to the scratch page.
1185 * There are a number of places where the hardware apparently
1186 * prefetches past the end of the object, and we've seen multiple
1187 * hangs with the GPU head pointer stuck in a batchbuffer bound
1188 * at the last page of the aperture. One page should be enough to
1189 * keep any prefetching inside of the aperture.
1190 */
fe669bf8 1191 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
79e53945 1192
11ed50ec 1193 mutex_lock(&dev->struct_mutex);
79e53945 1194 ret = i915_gem_init_ringbuffer(dev);
11ed50ec 1195 mutex_unlock(&dev->struct_mutex);
79e53945 1196 if (ret)
b8da7de5 1197 goto out;
79e53945 1198
80824003 1199 /* Try to set up FBC with a reasonable compressed buffer size */
9216d44d 1200 if (I915_HAS_FBC(dev) && i915_powersave) {
80824003
JB		 1201 int cfb_size;
1202
fe669bf8
CW		 1203 /* Leave 1M for line length buffer & misc. */
1204
1205 /* Try to get a 32M buffer... */
1206 if (prealloc_size > (36*1024*1024))
1207 cfb_size = 32*1024*1024;
80824003
JB		 1208 else /* fall back to 7/8 of the stolen space */
1209 cfb_size = prealloc_size * 7 / 8;
1210 i915_setup_compression(dev, cfb_size);
1211 }
1212
fe669bf8 1213 /* Allow hardware batchbuffers unless told otherwise. */
79e53945
JB		 1214 dev_priv->allow_batchbuffer = 1;
1215
6d139a87 1216 ret = intel_parse_bios(dev);
79e53945
JB		 1217 if (ret)
1218 DRM_INFO("failed to find VBIOS tables\n");
1219
934f992c
CW		 1220 /* If we have > 1 VGA cards, then we need to arbitrate access
1221 * to the common VGA resources.
1222 *
1223 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1224 * then we do not take part in VGA arbitration and the
1225 * vga_client_register() fails with -ENODEV.
1226 */
28d52043 1227 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
934f992c 1228 if (ret && ret != -ENODEV)
5a79395b 1229 goto cleanup_ringbuffer;
28d52043 1230
723bfd70
JB		 1231 intel_register_dsm_handler();
1232
6a9ee8af
DA		 1233 ret = vga_switcheroo_register_client(dev->pdev,
1234 i915_switcheroo_set_state,
8d608aa6 1235 NULL,
6a9ee8af
DA		 1236 i915_switcheroo_can_switch);
1237 if (ret)
5a79395b 1238 goto cleanup_vga_client;
6a9ee8af 1239
1afe3e9d
JB		 1240 /* IIR "flip pending" bit means done if this bit is set */
1241 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1242 dev_priv->flip_pending_is_done = true;
1243
b01f2c3a
JB		 1244 intel_modeset_init(dev);
1245
79e53945
JB		 1246 ret = drm_irq_install(dev);
1247 if (ret)
5a79395b 1248 goto cleanup_vga_switcheroo;
79e53945 1249
79e53945
JB		 1250 /* Always safe in the mode setting case. */
1251 /* FIXME: do pre/post-mode set stuff in core KMS code */
1252 dev->vblank_disable_allowed = 1;
1253
5a79395b
CW		 1254 ret = intel_fbdev_init(dev);
1255 if (ret)
1256 goto cleanup_irq;
1257
eb1f8e4f 1258 drm_kms_helper_poll_init(dev);
87acb0a5
CW		 1259
1260 /* We're off and running w/KMS */
1261 dev_priv->mm.suspended = 0;
1262
79e53945
JB		 1263 return 0;
1264
5a79395b
CW		 1265cleanup_irq:
1266 drm_irq_uninstall(dev);
1267cleanup_vga_switcheroo:
1268 vga_switcheroo_unregister_client(dev->pdev);
1269cleanup_vga_client:
1270 vga_client_register(dev->pdev, NULL, NULL, NULL);
1271cleanup_ringbuffer:
21099537 1272 mutex_lock(&dev->struct_mutex);
79e53945 1273 i915_gem_cleanup_ringbuffer(dev);
21099537 1274 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1275out:
1276 return ret;
1277}
1278
7c1c2871
DA		 1279int i915_master_create(struct drm_device *dev, struct drm_master *master)
1280{
1281 struct drm_i915_master_private *master_priv;
1282
9a298b2a 1283 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
7c1c2871
DA		 1284 if (!master_priv)
1285 return -ENOMEM;
1286
1287 master->driver_priv = master_priv;
1288 return 0;
1289}
1290
1291void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1292{
1293 struct drm_i915_master_private *master_priv = master->driver_priv;
1294
1295 if (!master_priv)
1296 return;
1297
9a298b2a 1298 kfree(master_priv);
7c1c2871
DA		 1299
1300 master->driver_priv = NULL;
1301}
1302
7648fa99 1303static void i915_pineview_get_mem_freq(struct drm_device *dev)
7662c8bd
SL		 1304{
1305 drm_i915_private_t *dev_priv = dev->dev_private;
1306 u32 tmp;
1307
7662c8bd
SL		 1308 tmp = I915_READ(CLKCFG);
1309
1310 switch (tmp & CLKCFG_FSB_MASK) {
1311 case CLKCFG_FSB_533:
1312 dev_priv->fsb_freq = 533; /* 133*4 */
1313 break;
1314 case CLKCFG_FSB_800:
1315 dev_priv->fsb_freq = 800; /* 200*4 */
1316 break;
1317 case CLKCFG_FSB_667:
1318 dev_priv->fsb_freq = 667; /* 167*4 */
1319 break;
1320 case CLKCFG_FSB_400:
1321 dev_priv->fsb_freq = 400; /* 100*4 */
1322 break;
1323 }
1324
1325 switch (tmp & CLKCFG_MEM_MASK) {
1326 case CLKCFG_MEM_533:
1327 dev_priv->mem_freq = 533;
1328 break;
1329 case CLKCFG_MEM_667:
1330 dev_priv->mem_freq = 667;
1331 break;
1332 case CLKCFG_MEM_800:
1333 dev_priv->mem_freq = 800;
1334 break;
1335 }
95534263
LP		 1336
1337 /* detect pineview DDR3 setting */
1338 tmp = I915_READ(CSHRDDR3CTL);
1339 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
7662c8bd
SL		 1340}
1341
7648fa99
JB		 1342static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1343{
1344 drm_i915_private_t *dev_priv = dev->dev_private;
1345 u16 ddrpll, csipll;
1346
1347 ddrpll = I915_READ16(DDRMPLL1);
1348 csipll = I915_READ16(CSIPLL0);
1349
1350 switch (ddrpll & 0xff) {
1351 case 0xc:
1352 dev_priv->mem_freq = 800;
1353 break;
1354 case 0x10:
1355 dev_priv->mem_freq = 1066;
1356 break;
1357 case 0x14:
1358 dev_priv->mem_freq = 1333;
1359 break;
1360 case 0x18:
1361 dev_priv->mem_freq = 1600;
1362 break;
1363 default:
1364 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1365 ddrpll & 0xff);
1366 dev_priv->mem_freq = 0;
1367 break;
1368 }
1369
1370 dev_priv->r_t = dev_priv->mem_freq;
1371
1372 switch (csipll & 0x3ff) {
1373 case 0x00c:
1374 dev_priv->fsb_freq = 3200;
1375 break;
1376 case 0x00e:
1377 dev_priv->fsb_freq = 3733;
1378 break;
1379 case 0x010:
1380 dev_priv->fsb_freq = 4266;
1381 break;
1382 case 0x012:
1383 dev_priv->fsb_freq = 4800;
1384 break;
1385 case 0x014:
1386 dev_priv->fsb_freq = 5333;
1387 break;
1388 case 0x016:
1389 dev_priv->fsb_freq = 5866;
1390 break;
1391 case 0x018:
1392 dev_priv->fsb_freq = 6400;
1393 break;
1394 default:
1395 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1396 csipll & 0x3ff);
1397 dev_priv->fsb_freq = 0;
1398 break;
1399 }
1400
1401 if (dev_priv->fsb_freq == 3200) {
1402 dev_priv->c_m = 0;
1403 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1404 dev_priv->c_m = 1;
1405 } else {
1406 dev_priv->c_m = 2;
1407 }
1408}
1409
faa60c41
CW		 1410static const struct cparams {
1411 u16 i;
1412 u16 t;
1413 u16 m;
1414 u16 c;
1415} cparams[] = {
7648fa99
JB		 1416 { 1, 1333, 301, 28664 },
1417 { 1, 1066, 294, 24460 },
1418 { 1, 800, 294, 25192 },
1419 { 0, 1333, 276, 27605 },
1420 { 0, 1066, 276, 27605 },
1421 { 0, 800, 231, 23784 },
1422};
1423
1424unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1425{
1426 u64 total_count, diff, ret;
1427 u32 count1, count2, count3, m = 0, c = 0;
1428 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1429 int i;
1430
1431 diff1 = now - dev_priv->last_time1;
1432
1433 count1 = I915_READ(DMIEC);
1434 count2 = I915_READ(DDREC);
1435 count3 = I915_READ(CSIEC);
1436
1437 total_count = count1 + count2 + count3;
1438
1439 /* FIXME: handle per-counter overflow */
1440 if (total_count < dev_priv->last_count1) {
1441 diff = ~0UL - dev_priv->last_count1;
1442 diff += total_count;
1443 } else {
1444 diff = total_count - dev_priv->last_count1;
1445 }
1446
1447 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1448 if (cparams[i].i == dev_priv->c_m &&
1449 cparams[i].t == dev_priv->r_t) {
1450 m = cparams[i].m;
1451 c = cparams[i].c;
1452 break;
1453 }
1454 }
1455
d270ae34 1456 diff = div_u64(diff, diff1);
7648fa99 1457 ret = ((m * diff) + c);
d270ae34 1458 ret = div_u64(ret, 10);
7648fa99
JB		 1459
1460 dev_priv->last_count1 = total_count;
1461 dev_priv->last_time1 = now;
1462
1463 return ret;
1464}
1465
1466unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1467{
1468 unsigned long m, x, b;
1469 u32 tsfs;
1470
1471 tsfs = I915_READ(TSFS);
1472
1473 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1474 x = I915_READ8(TR1);
1475
1476 b = tsfs & TSFS_INTR_MASK;
1477
1478 return ((m * x) / 127) - b;
1479}
1480
faa60c41 1481static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
7648fa99 1482{
faa60c41
CW		 1483 static const struct v_table {
1484 u16 vd; /* in .1 mil */
1485 u16 vm; /* in .1 mil */
1486 } v_table[] = {
1487 { 0, 0, },
1488 { 375, 0, },
1489 { 500, 0, },
1490 { 625, 0, },
1491 { 750, 0, },
1492 { 875, 0, },
1493 { 1000, 0, },
1494 { 1125, 0, },
1495 { 4125, 3000, },
1496 { 4125, 3000, },
1497 { 4125, 3000, },
1498 { 4125, 3000, },
1499 { 4125, 3000, },
1500 { 4125, 3000, },
1501 { 4125, 3000, },
1502 { 4125, 3000, },
1503 { 4125, 3000, },
1504 { 4125, 3000, },
1505 { 4125, 3000, },
1506 { 4125, 3000, },
1507 { 4125, 3000, },
1508 { 4125, 3000, },
1509 { 4125, 3000, },
1510 { 4125, 3000, },
1511 { 4125, 3000, },
1512 { 4125, 3000, },
1513 { 4125, 3000, },
1514 { 4125, 3000, },
1515 { 4125, 3000, },
1516 { 4125, 3000, },
1517 { 4125, 3000, },
1518 { 4125, 3000, },
1519 { 4250, 3125, },
1520 { 4375, 3250, },
1521 { 4500, 3375, },
1522 { 4625, 3500, },
1523 { 4750, 3625, },
1524 { 4875, 3750, },
1525 { 5000, 3875, },
1526 { 5125, 4000, },
1527 { 5250, 4125, },
1528 { 5375, 4250, },
1529 { 5500, 4375, },
1530 { 5625, 4500, },
1531 { 5750, 4625, },
1532 { 5875, 4750, },
1533 { 6000, 4875, },
1534 { 6125, 5000, },
1535 { 6250, 5125, },
1536 { 6375, 5250, },
1537 { 6500, 5375, },
1538 { 6625, 5500, },
1539 { 6750, 5625, },
1540 { 6875, 5750, },
1541 { 7000, 5875, },
1542 { 7125, 6000, },
1543 { 7250, 6125, },
1544 { 7375, 6250, },
1545 { 7500, 6375, },
1546 { 7625, 6500, },
1547 { 7750, 6625, },
1548 { 7875, 6750, },
1549 { 8000, 6875, },
1550 { 8125, 7000, },
1551 { 8250, 7125, },
1552 { 8375, 7250, },
1553 { 8500, 7375, },
1554 { 8625, 7500, },
1555 { 8750, 7625, },
1556 { 8875, 7750, },
1557 { 9000, 7875, },
1558 { 9125, 8000, },
1559 { 9250, 8125, },
1560 { 9375, 8250, },
1561 { 9500, 8375, },
1562 { 9625, 8500, },
1563 { 9750, 8625, },
1564 { 9875, 8750, },
1565 { 10000, 8875, },
1566 { 10125, 9000, },
1567 { 10250, 9125, },
1568 { 10375, 9250, },
1569 { 10500, 9375, },
1570 { 10625, 9500, },
1571 { 10750, 9625, },
1572 { 10875, 9750, },
1573 { 11000, 9875, },
1574 { 11125, 10000, },
1575 { 11250, 10125, },
1576 { 11375, 10250, },
1577 { 11500, 10375, },
1578 { 11625, 10500, },
1579 { 11750, 10625, },
1580 { 11875, 10750, },
1581 { 12000, 10875, },
1582 { 12125, 11000, },
1583 { 12250, 11125, },
1584 { 12375, 11250, },
1585 { 12500, 11375, },
1586 { 12625, 11500, },
1587 { 12750, 11625, },
1588 { 12875, 11750, },
1589 { 13000, 11875, },
1590 { 13125, 12000, },
1591 { 13250, 12125, },
1592 { 13375, 12250, },
1593 { 13500, 12375, },
1594 { 13625, 12500, },
1595 { 13750, 12625, },
1596 { 13875, 12750, },
1597 { 14000, 12875, },
1598 { 14125, 13000, },
1599 { 14250, 13125, },
1600 { 14375, 13250, },
1601 { 14500, 13375, },
1602 { 14625, 13500, },
1603 { 14750, 13625, },
1604 { 14875, 13750, },
1605 { 15000, 13875, },
1606 { 15125, 14000, },
1607 { 15250, 14125, },
1608 { 15375, 14250, },
1609 { 15500, 14375, },
1610 { 15625, 14500, },
1611 { 15750, 14625, },
1612 { 15875, 14750, },
1613 { 16000, 14875, },
1614 { 16125, 15000, },
1615 };
1616 if (dev_priv->info->is_mobile)
1617 return v_table[pxvid].vm;
1618 else
1619 return v_table[pxvid].vd;
7648fa99
JB		 1620}
1621
1622void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1623{
1624 struct timespec now, diff1;
1625 u64 diff;
1626 unsigned long diffms;
1627 u32 count;
1628
1629 getrawmonotonic(&now);
1630 diff1 = timespec_sub(now, dev_priv->last_time2);
1631
1632 /* Don't divide by 0 */
1633 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1634 if (!diffms)
1635 return;
1636
1637 count = I915_READ(GFXEC);
1638
1639 if (count < dev_priv->last_count2) {
1640 diff = ~0UL - dev_priv->last_count2;
1641 diff += count;
1642 } else {
1643 diff = count - dev_priv->last_count2;
1644 }
1645
1646 dev_priv->last_count2 = count;
1647 dev_priv->last_time2 = now;
1648
1649 /* More magic constants... */
1650 diff = diff * 1181;
d270ae34 1651 diff = div_u64(diff, diffms * 10);
7648fa99
JB		 1652 dev_priv->gfx_power = diff;
1653}
1654
1655unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1656{
1657 unsigned long t, corr, state1, corr2, state2;
1658 u32 pxvid, ext_v;
1659
1660 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1661 pxvid = (pxvid >> 24) & 0x7f;
1662 ext_v = pvid_to_extvid(dev_priv, pxvid);
1663
1664 state1 = ext_v;
1665
1666 t = i915_mch_val(dev_priv);
1667
1668 /* Revel in the empirically derived constants */
1669
1670 /* Correction factor in 1/100000 units */
1671 if (t > 80)
1672 corr = ((t * 2349) + 135940);
1673 else if (t >= 50)
1674 corr = ((t * 964) + 29317);
1675 else /* < 50 */
1676 corr = ((t * 301) + 1004);
1677
1678 corr = corr * ((150142 * state1) / 10000 - 78642);
1679 corr /= 100000;
1680 corr2 = (corr * dev_priv->corr);
1681
1682 state2 = (corr2 * state1) / 10000;
1683 state2 /= 100; /* convert to mW */
1684
1685 i915_update_gfx_val(dev_priv);
1686
1687 return dev_priv->gfx_power + state2;
1688}
1689
1690/* Global for IPS driver to get at the current i915 device */
1691static struct drm_i915_private *i915_mch_dev;
1692/*
1693 * Lock protecting IPS related data structures
1694 * - i915_mch_dev
1695 * - dev_priv->max_delay
1696 * - dev_priv->min_delay
1697 * - dev_priv->fmax
1698 * - dev_priv->gpu_busy
1699 */
995b6762 1700static DEFINE_SPINLOCK(mchdev_lock);
7648fa99
JB		 1701
1702/**
1703 * i915_read_mch_val - return value for IPS use
1704 *
1705 * Calculate and return a value for the IPS driver to use when deciding whether
1706 * we have thermal and power headroom to increase CPU or GPU power budget.
1707 */
1708unsigned long i915_read_mch_val(void)
1709{
1710 struct drm_i915_private *dev_priv;
1711 unsigned long chipset_val, graphics_val, ret = 0;
1712
1713 spin_lock(&mchdev_lock);
1714 if (!i915_mch_dev)
1715 goto out_unlock;
1716 dev_priv = i915_mch_dev;
1717
1718 chipset_val = i915_chipset_val(dev_priv);
1719 graphics_val = i915_gfx_val(dev_priv);
1720
1721 ret = chipset_val + graphics_val;
1722
1723out_unlock:
1724 spin_unlock(&mchdev_lock);
1725
1726 return ret;
1727}
1728EXPORT_SYMBOL_GPL(i915_read_mch_val);
1729
1730/**
1731 * i915_gpu_raise - raise GPU frequency limit
1732 *
1733 * Raise the limit; IPS indicates we have thermal headroom.
1734 */
1735bool i915_gpu_raise(void)
1736{
1737 struct drm_i915_private *dev_priv;
1738 bool ret = true;
1739
1740 spin_lock(&mchdev_lock);
1741 if (!i915_mch_dev) {
1742 ret = false;
1743 goto out_unlock;
1744 }
1745 dev_priv = i915_mch_dev;
1746
1747 if (dev_priv->max_delay > dev_priv->fmax)
1748 dev_priv->max_delay--;
1749
1750out_unlock:
1751 spin_unlock(&mchdev_lock);
1752
1753 return ret;
1754}
1755EXPORT_SYMBOL_GPL(i915_gpu_raise);
1756
1757/**
1758 * i915_gpu_lower - lower GPU frequency limit
1759 *
1760 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1761 * frequency maximum.
1762 */
1763bool i915_gpu_lower(void)
1764{
1765 struct drm_i915_private *dev_priv;
1766 bool ret = true;
1767
1768 spin_lock(&mchdev_lock);
1769 if (!i915_mch_dev) {
1770 ret = false;
1771 goto out_unlock;
1772 }
1773 dev_priv = i915_mch_dev;
1774
1775 if (dev_priv->max_delay < dev_priv->min_delay)
1776 dev_priv->max_delay++;
1777
1778out_unlock:
1779 spin_unlock(&mchdev_lock);
1780
1781 return ret;
1782}
1783EXPORT_SYMBOL_GPL(i915_gpu_lower);
1784
1785/**
1786 * i915_gpu_busy - indicate GPU business to IPS
1787 *
1788 * Tell the IPS driver whether or not the GPU is busy.
1789 */
1790bool i915_gpu_busy(void)
1791{
1792 struct drm_i915_private *dev_priv;
1793 bool ret = false;
1794
1795 spin_lock(&mchdev_lock);
1796 if (!i915_mch_dev)
1797 goto out_unlock;
1798 dev_priv = i915_mch_dev;
1799
1800 ret = dev_priv->busy;
1801
1802out_unlock:
1803 spin_unlock(&mchdev_lock);
1804
1805 return ret;
1806}
1807EXPORT_SYMBOL_GPL(i915_gpu_busy);
1808
1809/**
1810 * i915_gpu_turbo_disable - disable graphics turbo
1811 *
1812 * Disable graphics turbo by resetting the max frequency and setting the
1813 * current frequency to the default.
1814 */
1815bool i915_gpu_turbo_disable(void)
1816{
1817 struct drm_i915_private *dev_priv;
1818 bool ret = true;
1819
1820 spin_lock(&mchdev_lock);
1821 if (!i915_mch_dev) {
1822 ret = false;
1823 goto out_unlock;
1824 }
1825 dev_priv = i915_mch_dev;
1826
1827 dev_priv->max_delay = dev_priv->fstart;
1828
1829 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1830 ret = false;
1831
1832out_unlock:
1833 spin_unlock(&mchdev_lock);
1834
1835 return ret;
1836}
1837EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1838
63ee41d7
EA		 1839/**
1840 * Tells the intel_ips driver that the i915 driver is now loaded, if
1841 * IPS got loaded first.
1842 *
1843 * This awkward dance is so that neither module has to depend on the
1844 * other in order for IPS to do the appropriate communication of
1845 * GPU turbo limits to i915.
1846 */
1847static void
1848ips_ping_for_i915_load(void)
1849{
1850 void (*link)(void);
1851
1852 link = symbol_get(ips_link_to_i915_driver);
1853 if (link) {
1854 link();
1855 symbol_put(ips_link_to_i915_driver);
1856 }
1857}
1858
79e53945
JB		 1859/**
1860 * i915_driver_load - setup chip and create an initial config
1861 * @dev: DRM device
1862 * @flags: startup flags
1863 *
1864 * The driver load routine has to do several things:
1865 * - drive output discovery via intel_modeset_init()
1866 * - initialize the memory manager
1867 * - allocate initial config memory
1868 * - setup the DRM framebuffer with the allocated memory
1869 */
84b1fd10 1870int i915_driver_load(struct drm_device *dev, unsigned long flags)
22eae947 1871{
ea059a1e 1872 struct drm_i915_private *dev_priv;
cfdf1fa2 1873 int ret = 0, mmio_bar;
fe669bf8
CW		 1874 uint32_t agp_size;
1875
22eae947
DA		 1876 /* i915 has 4 more counters */
1877 dev->counters += 4;
1878 dev->types[6] = _DRM_STAT_IRQ;
1879 dev->types[7] = _DRM_STAT_PRIMARY;
1880 dev->types[8] = _DRM_STAT_SECONDARY;
1881 dev->types[9] = _DRM_STAT_DMA;
1882
9a298b2a 1883 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
ba8bbcf6
JB		 1884 if (dev_priv == NULL)
1885 return -ENOMEM;
1886
ba8bbcf6 1887 dev->dev_private = (void *)dev_priv;
673a394b 1888 dev_priv->dev = dev;
cfdf1fa2 1889 dev_priv->info = (struct intel_device_info *) flags;
ba8bbcf6 1890
ec2a4c3f
DA		 1891 if (i915_get_bridge_dev(dev)) {
1892 ret = -EIO;
1893 goto free_priv;
1894 }
1895
9f82d238
DV		 1896 /* overlay on gen2 is broken and can't address above 1G */
1897 if (IS_GEN2(dev))
1898 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1899
b4ce0f85
CW		 1900 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1901 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1902 if (!dev_priv->regs) {
1903 DRM_ERROR("failed to map registers\n");
1904 ret = -EIO;
1905 goto put_bridge;
1906 }
1907
71e9339c
CW		 1908 dev_priv->mm.gtt = intel_gtt_get();
1909 if (!dev_priv->mm.gtt) {
1910 DRM_ERROR("Failed to initialize GTT\n");
1911 ret = -ENODEV;
1912 goto out_iomapfree;
1913 }
1914
71e9339c
CW		 1915 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1916
ab657db1 1917 dev_priv->mm.gtt_mapping =
71e9339c 1918 io_mapping_create_wc(dev->agp->base, agp_size);
6644107d
VP		 1919 if (dev_priv->mm.gtt_mapping == NULL) {
1920 ret = -EIO;
1921 goto out_rmmap;
1922 }
1923
ab657db1
EA		 1924 /* Set up a WC MTRR for non-PAT systems. This is more common than
1925 * one would think, because the kernel disables PAT on first
1926 * generation Core chips because WC PAT gets overridden by a UC
1927 * MTRR if present. Even if a UC MTRR isn't present.
1928 */
1929 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
71e9339c 1930 agp_size,
ab657db1
EA		 1931 MTRR_TYPE_WRCOMB, 1);
1932 if (dev_priv->mm.gtt_mtrr < 0) {
040aefa2 1933 DRM_INFO("MTRR allocation failed. Graphics "
ab657db1
EA		 1934 "performance may suffer.\n");
1935 }
19966754 1936
e642abbf
CW		 1937 /* The i915 workqueue is primarily used for batched retirement of
1938 * requests (and thus managing bo) once the task has been completed
1939 * by the GPU. i915_gem_retire_requests() is called directly when we
1940 * need high-priority retirement, such as waiting for an explicit
1941 * bo.
1942 *
1943 * It is also used for periodic low-priority events, such as
df9c2042 1944 * idle-timers and recording error state.
e642abbf
CW		 1945 *
1946 * All tasks on the workqueue are expected to acquire the dev mutex
1947 * so there is no point in running more than one instance of the
1948 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1949 */
1950 dev_priv->wq = alloc_workqueue("i915",
1951 WQ_UNBOUND | WQ_NON_REENTRANT,
1952 1);
9c9fe1f8
EA		 1953 if (dev_priv->wq == NULL) {
1954 DRM_ERROR("Failed to create our workqueue.\n");
1955 ret = -ENOMEM;
1956 goto out_iomapfree;
1957 }
1958
ac5c4e76
DA		 1959 /* enable GEM by default */
1960 dev_priv->has_gem = 1;
ac5c4e76 1961
9880b7a5 1962 dev->driver->get_vblank_counter = i915_get_vblank_counter;
42c2798b 1963 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f00a3ddf 1964 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
42c2798b 1965 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
9880b7a5 1966 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
42c2798b 1967 }
9880b7a5 1968
c4804411
ZW		 1969 /* Try to make sure MCHBAR is enabled before poking at it */
1970 intel_setup_mchbar(dev);
f899fc64 1971 intel_setup_gmbus(dev);
44834a67 1972 intel_opregion_setup(dev);
c4804411 1973
6d139a87
BF		 1974 /* Make sure the bios did its job and set up vital registers */
1975 intel_setup_bios(dev);
1976
673a394b
EA		 1977 i915_gem_load(dev);
1978
398c9cb2
KP		 1979 /* Init HWS */
1980 if (!I915_NEED_GFX_HWS(dev)) {
1981 ret = i915_init_phys_hws(dev);
56e2ea34
CW		 1982 if (ret)
1983 goto out_gem_unload;
398c9cb2 1984 }
ed4cb414 1985
7648fa99
JB		 1986 if (IS_PINEVIEW(dev))
1987 i915_pineview_get_mem_freq(dev);
f00a3ddf 1988 else if (IS_GEN5(dev))
7648fa99 1989 i915_ironlake_get_mem_freq(dev);
7662c8bd 1990
ed4cb414
EA		 1991 /* On the 945G/GM, the chipset reports the MSI capability on the
1992 * integrated graphics even though the support isn't actually there
1993 * according to the published specs. It doesn't appear to function
1994 * correctly in testing on 945G.
1995 * This may be a side effect of MSI having been made available for PEG
1996 * and the registers being closely associated.
d1ed629f
KP		 1997 *
1998 * According to chipset errata, on the 965GM, MSI interrupts may
b60678a7
KP		 1999 * be lost or delayed, but we use them anyways to avoid
2000 * stuck interrupts on some machines.
ed4cb414 2001 */
b60678a7 2002 if (!IS_I945G(dev) && !IS_I945GM(dev))
d3e74d02 2003 pci_enable_msi(dev->pdev);
ed4cb414 2004
1ec14ad3 2005 spin_lock_init(&dev_priv->irq_lock);
63eeaf38 2006 spin_lock_init(&dev_priv->error_lock);
ed4cb414 2007
52440211 2008 ret = drm_vblank_init(dev, I915_NUM_PIPE);
56e2ea34
CW		 2009 if (ret)
2010 goto out_gem_unload;
52440211 2011
11ed50ec
BG		 2012 /* Start out suspended */
2013 dev_priv->mm.suspended = 1;
2014
3bad0781
ZW		 2015 intel_detect_pch(dev);
2016
79e53945 2017 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
53984635 2018 ret = i915_load_modeset_init(dev);
79e53945
JB		 2019 if (ret < 0) {
2020 DRM_ERROR("failed to init modeset\n");
56e2ea34 2021 goto out_gem_unload;
79e53945
JB		 2022 }
2023 }
2024
74a365b3 2025 /* Must be done after probing outputs */
44834a67
CW		 2026 intel_opregion_init(dev);
2027 acpi_video_register();
74a365b3 2028
f65d9421
BG		 2029 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2030 (unsigned long) dev);
7648fa99
JB		 2031
2032 spin_lock(&mchdev_lock);
2033 i915_mch_dev = dev_priv;
2034 dev_priv->mchdev_lock = &mchdev_lock;
2035 spin_unlock(&mchdev_lock);
2036
63ee41d7
EA		 2037 ips_ping_for_i915_load();
2038
79e53945
JB		 2039 return 0;
2040
56e2ea34
CW		 2041out_gem_unload:
2042 if (dev->pdev->msi_enabled)
2043 pci_disable_msi(dev->pdev);
2044
2045 intel_teardown_gmbus(dev);
2046 intel_teardown_mchbar(dev);
9c9fe1f8 2047 destroy_workqueue(dev_priv->wq);
6644107d
VP		 2048out_iomapfree:
2049 io_mapping_free(dev_priv->mm.gtt_mapping);
79e53945 2050out_rmmap:
6dda569f 2051 pci_iounmap(dev->pdev, dev_priv->regs);
ec2a4c3f
DA		 2052put_bridge:
2053 pci_dev_put(dev_priv->bridge_dev);
79e53945 2054free_priv:
9a298b2a 2055 kfree(dev_priv);
ba8bbcf6
JB		 2056 return ret;
2057}
2058
2059int i915_driver_unload(struct drm_device *dev)
2060{
2061 struct drm_i915_private *dev_priv = dev->dev_private;
c911fc1c 2062 int ret;
ba8bbcf6 2063
7648fa99
JB		 2064 spin_lock(&mchdev_lock);
2065 i915_mch_dev = NULL;
2066 spin_unlock(&mchdev_lock);
2067
17250b71
CW		 2068 if (dev_priv->mm.inactive_shrinker.shrink)
2069 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2070
c911fc1c
DV		 2071 mutex_lock(&dev->struct_mutex);
2072 ret = i915_gpu_idle(dev);
2073 if (ret)
2074 DRM_ERROR("failed to idle hardware: %d\n", ret);
2075 mutex_unlock(&dev->struct_mutex);
2076
75ef9da2
DV		 2077 /* Cancel the retire work handler, which should be idle now. */
2078 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2079
ab657db1
EA		 2080 io_mapping_free(dev_priv->mm.gtt_mapping);
2081 if (dev_priv->mm.gtt_mtrr >= 0) {
2082 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2083 dev->agp->agp_info.aper_size * 1024 * 1024);
2084 dev_priv->mm.gtt_mtrr = -1;
2085 }
2086
44834a67
CW		 2087 acpi_video_unregister();
2088
79e53945 2089 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
7b4f3990 2090 intel_fbdev_fini(dev);
3d8620cc
JB		 2091 intel_modeset_cleanup(dev);
2092
6363ee6f
ZY		 2093 /*
2094 * free the memory space allocated for the child device
2095 * config parsed from VBT
2096 */
2097 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2098 kfree(dev_priv->child_dev);
2099 dev_priv->child_dev = NULL;
2100 dev_priv->child_dev_num = 0;
2101 }
6c0d9350 2102
6a9ee8af 2103 vga_switcheroo_unregister_client(dev->pdev);
28d52043 2104 vga_client_register(dev->pdev, NULL, NULL, NULL);
79e53945
JB		 2105 }
2106
a8b4899e 2107 /* Free error state after interrupts are fully disabled. */
bc0c7f14
DV		 2108 del_timer_sync(&dev_priv->hangcheck_timer);
2109 cancel_work_sync(&dev_priv->error_work);
a8b4899e 2110 i915_destroy_error_state(dev);
bc0c7f14 2111
ed4cb414
EA		 2112 if (dev->pdev->msi_enabled)
2113 pci_disable_msi(dev->pdev);
2114
44834a67 2115 intel_opregion_fini(dev);
8ee1c3db 2116
79e53945 2117 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
67e77c5a
DV		 2118 /* Flush any outstanding unpin_work. */
2119 flush_workqueue(dev_priv->wq);
2120
71acb5eb
DA		 2121 i915_gem_free_all_phys_object(dev);
2122
79e53945
JB		 2123 mutex_lock(&dev->struct_mutex);
2124 i915_gem_cleanup_ringbuffer(dev);
2125 mutex_unlock(&dev->struct_mutex);
20bf377e
JB		 2126 if (I915_HAS_FBC(dev) && i915_powersave)
2127 i915_cleanup_compression(dev);
fe669bf8 2128 drm_mm_takedown(&dev_priv->mm.stolen);
02e792fb
DV		 2129
2130 intel_cleanup_overlay(dev);
c2873e96
KP		 2131
2132 if (!I915_NEED_GFX_HWS(dev))
2133 i915_free_hws(dev);
79e53945
JB		 2134 }
2135
701394cc 2136 if (dev_priv->regs != NULL)
6dda569f 2137 pci_iounmap(dev->pdev, dev_priv->regs);
701394cc 2138
f899fc64 2139 intel_teardown_gmbus(dev);
c4804411
ZW		 2140 intel_teardown_mchbar(dev);
2141
bc0c7f14
DV		 2142 destroy_workqueue(dev_priv->wq);
2143
ec2a4c3f 2144 pci_dev_put(dev_priv->bridge_dev);
9a298b2a 2145 kfree(dev->dev_private);
ba8bbcf6 2146
22eae947
DA		 2147 return 0;
2148}
2149
f787a5f5 2150int i915_driver_open(struct drm_device *dev, struct drm_file *file)
673a394b 2151{
f787a5f5 2152 struct drm_i915_file_private *file_priv;
673a394b 2153
8a4c47f3 2154 DRM_DEBUG_DRIVER("\n");
f787a5f5
CW		 2155 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2156 if (!file_priv)
673a394b
EA		 2157 return -ENOMEM;
2158
f787a5f5 2159 file->driver_priv = file_priv;
673a394b 2160
1c25595f 2161 spin_lock_init(&file_priv->mm.lock);
f787a5f5 2162 INIT_LIST_HEAD(&file_priv->mm.request_list);
673a394b
EA		 2163
2164 return 0;
2165}
2166
79e53945
JB		 2167/**
2168 * i915_driver_lastclose - clean up after all DRM clients have exited
2169 * @dev: DRM device
2170 *
2171 * Take care of cleaning up after all DRM clients have exited. In the
2172 * mode setting case, we want to restore the kernel's initial mode (just
2173 * in case the last client left us in a bad state).
2174 *
2175 * Additionally, in the non-mode setting case, we'll tear down the AGP
2176 * and DMA structures, since the kernel won't be using them, and clea
2177 * up any GEM state.
2178 */
84b1fd10 2179void i915_driver_lastclose(struct drm_device * dev)
1da177e4 2180{
ba8bbcf6
JB		 2181 drm_i915_private_t *dev_priv = dev->dev_private;
2182
79e53945 2183 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
785b93ef 2184 drm_fb_helper_restore();
6a9ee8af 2185 vga_switcheroo_process_delayed_switch();
144a75fa 2186 return;
79e53945 2187 }
144a75fa 2188
673a394b
EA		 2189 i915_gem_lastclose(dev);
2190
ba8bbcf6 2191 if (dev_priv->agp_heap)
b5e89ed5 2192 i915_mem_takedown(&(dev_priv->agp_heap));
ba8bbcf6 2193
b5e89ed5 2194 i915_dma_cleanup(dev);
1da177e4
LT		 2195}
2196
6c340eac 2197void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1da177e4 2198{
ba8bbcf6 2199 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 2200 i915_gem_release(dev, file_priv);
79e53945
JB		 2201 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2202 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1da177e4
LT		 2203}
2204
f787a5f5 2205void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
673a394b 2206{
f787a5f5 2207 struct drm_i915_file_private *file_priv = file->driver_priv;
673a394b 2208
f787a5f5 2209 kfree(file_priv);
673a394b
EA		 2210}
2211
c153f45f 2212struct drm_ioctl_desc i915_ioctls[] = {
1b2f1489
DA		 2213 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2214 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2215 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2216 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2217 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2218 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2219 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2220 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2221 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2222 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2223 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2224 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2225 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2226 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2227 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2228 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2229 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2230 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2231 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2232 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2233 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2234 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2235 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2236 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2237 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2238 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2239 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2240 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2241 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2242 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2243 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2244 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2245 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2246 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2247 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2248 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2249 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2250 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2251 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2252 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
c94f7029
DA		 2253};
2254
2255int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
cda17380
DA		 2256
2257/**
2258 * Determine if the device really is AGP or not.
2259 *
2260 * All Intel graphics chipsets are treated as AGP, even if they are really
2261 * PCI-e.
2262 *
2263 * \param dev The device to be tested.
2264 *
2265 * \returns
2266 * A value of 1 is always retured to indictate every i9x5 is AGP.
2267 */
84b1fd10 2268int i915_driver_device_is_agp(struct drm_device * dev)
cda17380
DA		 2269{
2270 return 1;
2271}
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