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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
e5747e3a | 31 | #include <linux/acpi.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/i915_drm.h> | |
1da177e4 | 34 | #include "i915_drv.h" |
990bbdad | 35 | #include "i915_trace.h" |
f49f0586 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
79e53945 | 38 | #include <linux/console.h> |
e0cd3608 | 39 | #include <linux/module.h> |
d6102977 | 40 | #include <linux/pm_runtime.h> |
760285e7 | 41 | #include <drm/drm_crtc_helper.h> |
79e53945 | 42 | |
112b715e KH |
43 | static struct drm_driver driver; |
44 | ||
a57c774a AK |
45 | #define GEN_DEFAULT_PIPEOFFSETS \ |
46 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
47 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
48 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
49 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
a57c774a AK |
50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
51 | ||
84fd4f4e RB |
52 | #define GEN_CHV_PIPEOFFSETS \ |
53 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
54 | CHV_PIPE_C_OFFSET }, \ | |
55 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
56 | CHV_TRANSCODER_C_OFFSET, }, \ | |
84fd4f4e RB |
57 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
58 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 59 | |
5efb3e28 VS |
60 | #define CURSOR_OFFSETS \ |
61 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
62 | ||
63 | #define IVB_CURSOR_OFFSETS \ | |
64 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
65 | ||
9a7e8492 | 66 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 67 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 68 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 69 | .ring_mask = RENDER_RING, |
a57c774a | 70 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 71 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
72 | }; |
73 | ||
9a7e8492 | 74 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 75 | .gen = 2, .num_pipes = 1, |
31578148 | 76 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 77 | .ring_mask = RENDER_RING, |
a57c774a | 78 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 79 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
80 | }; |
81 | ||
9a7e8492 | 82 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 83 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 84 | .cursor_needs_physical = 1, |
31578148 | 85 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 86 | .has_fbc = 1, |
73ae478c | 87 | .ring_mask = RENDER_RING, |
a57c774a | 88 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 89 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
90 | }; |
91 | ||
9a7e8492 | 92 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 93 | .gen = 2, .num_pipes = 1, |
31578148 | 94 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 95 | .ring_mask = RENDER_RING, |
a57c774a | 96 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 97 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
98 | }; |
99 | ||
9a7e8492 | 100 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 101 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 102 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 103 | .ring_mask = RENDER_RING, |
a57c774a | 104 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 105 | CURSOR_OFFSETS, |
cfdf1fa2 | 106 | }; |
9a7e8492 | 107 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 108 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 109 | .cursor_needs_physical = 1, |
31578148 | 110 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 111 | .supports_tv = 1, |
fd70d52a | 112 | .has_fbc = 1, |
73ae478c | 113 | .ring_mask = RENDER_RING, |
a57c774a | 114 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 115 | CURSOR_OFFSETS, |
cfdf1fa2 | 116 | }; |
9a7e8492 | 117 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 118 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 119 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 120 | .ring_mask = RENDER_RING, |
a57c774a | 121 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 122 | CURSOR_OFFSETS, |
cfdf1fa2 | 123 | }; |
9a7e8492 | 124 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 125 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 126 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 127 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 128 | .supports_tv = 1, |
fd70d52a | 129 | .has_fbc = 1, |
73ae478c | 130 | .ring_mask = RENDER_RING, |
a57c774a | 131 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 132 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
133 | }; |
134 | ||
9a7e8492 | 135 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 136 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 137 | .has_hotplug = 1, |
31578148 | 138 | .has_overlay = 1, |
73ae478c | 139 | .ring_mask = RENDER_RING, |
a57c774a | 140 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 141 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
142 | }; |
143 | ||
9a7e8492 | 144 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 145 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 146 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 147 | .has_overlay = 1, |
a6c45cf0 | 148 | .supports_tv = 1, |
73ae478c | 149 | .ring_mask = RENDER_RING, |
a57c774a | 150 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 151 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
152 | }; |
153 | ||
9a7e8492 | 154 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 155 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 156 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 157 | .has_overlay = 1, |
73ae478c | 158 | .ring_mask = RENDER_RING, |
a57c774a | 159 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 160 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
161 | }; |
162 | ||
9a7e8492 | 163 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 164 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 165 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 166 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 167 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 168 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
169 | }; |
170 | ||
9a7e8492 | 171 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 172 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 173 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 174 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 175 | .supports_tv = 1, |
73ae478c | 176 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 177 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 178 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
179 | }; |
180 | ||
9a7e8492 | 181 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 182 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 183 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 184 | .has_overlay = 1, |
a57c774a | 185 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 186 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
187 | }; |
188 | ||
9a7e8492 | 189 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 190 | .gen = 5, .num_pipes = 2, |
5a117db7 | 191 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 192 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 193 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 194 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
195 | }; |
196 | ||
9a7e8492 | 197 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 198 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 199 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 200 | .has_fbc = 1, |
73ae478c | 201 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 202 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 203 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
204 | }; |
205 | ||
9a7e8492 | 206 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 207 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 208 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 209 | .has_fbc = 1, |
73ae478c | 210 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 211 | .has_llc = 1, |
a57c774a | 212 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 213 | CURSOR_OFFSETS, |
f6e450a6 EA |
214 | }; |
215 | ||
9a7e8492 | 216 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 217 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 218 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 219 | .has_fbc = 1, |
73ae478c | 220 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 221 | .has_llc = 1, |
a57c774a | 222 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 223 | CURSOR_OFFSETS, |
a13e4093 EA |
224 | }; |
225 | ||
219f4fdb BW |
226 | #define GEN7_FEATURES \ |
227 | .gen = 7, .num_pipes = 3, \ | |
228 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 229 | .has_fbc = 1, \ |
73ae478c | 230 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 231 | .has_llc = 1 |
219f4fdb | 232 | |
c76b615c | 233 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
234 | GEN7_FEATURES, |
235 | .is_ivybridge = 1, | |
a57c774a | 236 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 237 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
238 | }; |
239 | ||
240 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
241 | GEN7_FEATURES, |
242 | .is_ivybridge = 1, | |
243 | .is_mobile = 1, | |
a57c774a | 244 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 245 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
246 | }; |
247 | ||
999bcdea BW |
248 | static const struct intel_device_info intel_ivybridge_q_info = { |
249 | GEN7_FEATURES, | |
250 | .is_ivybridge = 1, | |
251 | .num_pipes = 0, /* legal, last one wins */ | |
a57c774a | 252 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 253 | IVB_CURSOR_OFFSETS, |
999bcdea BW |
254 | }; |
255 | ||
70a3eb7a | 256 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
257 | GEN7_FEATURES, |
258 | .is_mobile = 1, | |
259 | .num_pipes = 2, | |
70a3eb7a | 260 | .is_valleyview = 1, |
fba5d532 | 261 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 262 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 263 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 264 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 265 | CURSOR_OFFSETS, |
70a3eb7a JB |
266 | }; |
267 | ||
268 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
269 | GEN7_FEATURES, |
270 | .num_pipes = 2, | |
70a3eb7a | 271 | .is_valleyview = 1, |
fba5d532 | 272 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 273 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 274 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 275 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 276 | CURSOR_OFFSETS, |
70a3eb7a JB |
277 | }; |
278 | ||
4cae9ae0 | 279 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
280 | GEN7_FEATURES, |
281 | .is_haswell = 1, | |
dd93be58 | 282 | .has_ddi = 1, |
30568c45 | 283 | .has_fpga_dbg = 1, |
73ae478c | 284 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 285 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 286 | IVB_CURSOR_OFFSETS, |
4cae9ae0 ED |
287 | }; |
288 | ||
289 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
290 | GEN7_FEATURES, |
291 | .is_haswell = 1, | |
292 | .is_mobile = 1, | |
dd93be58 | 293 | .has_ddi = 1, |
30568c45 | 294 | .has_fpga_dbg = 1, |
73ae478c | 295 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 296 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 297 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
298 | }; |
299 | ||
4d4dead6 | 300 | static const struct intel_device_info intel_broadwell_d_info = { |
4b30553d | 301 | .gen = 8, .num_pipes = 3, |
4d4dead6 BW |
302 | .need_gfx_hws = 1, .has_hotplug = 1, |
303 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
304 | .has_llc = 1, | |
305 | .has_ddi = 1, | |
66bc2cab | 306 | .has_fpga_dbg = 1, |
8f94d24b | 307 | .has_fbc = 1, |
a57c774a | 308 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 309 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
310 | }; |
311 | ||
312 | static const struct intel_device_info intel_broadwell_m_info = { | |
4b30553d | 313 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
4d4dead6 BW |
314 | .need_gfx_hws = 1, .has_hotplug = 1, |
315 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
316 | .has_llc = 1, | |
317 | .has_ddi = 1, | |
66bc2cab | 318 | .has_fpga_dbg = 1, |
8f94d24b | 319 | .has_fbc = 1, |
a57c774a | 320 | GEN_DEFAULT_PIPEOFFSETS, |
15d24aa5 | 321 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
322 | }; |
323 | ||
fd3c269f ZY |
324 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
325 | .gen = 8, .num_pipes = 3, | |
326 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 327 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
328 | .has_llc = 1, |
329 | .has_ddi = 1, | |
66bc2cab | 330 | .has_fpga_dbg = 1, |
fd3c269f ZY |
331 | .has_fbc = 1, |
332 | GEN_DEFAULT_PIPEOFFSETS, | |
15d24aa5 | 333 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
334 | }; |
335 | ||
336 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
337 | .gen = 8, .is_mobile = 1, .num_pipes = 3, | |
338 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 339 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
340 | .has_llc = 1, |
341 | .has_ddi = 1, | |
66bc2cab | 342 | .has_fpga_dbg = 1, |
fd3c269f ZY |
343 | .has_fbc = 1, |
344 | GEN_DEFAULT_PIPEOFFSETS, | |
5efb3e28 | 345 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
346 | }; |
347 | ||
7d87a7f7 | 348 | static const struct intel_device_info intel_cherryview_info = { |
07fddb14 | 349 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
350 | .need_gfx_hws = 1, .has_hotplug = 1, |
351 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
352 | .is_valleyview = 1, | |
353 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
84fd4f4e | 354 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 355 | CURSOR_OFFSETS, |
7d87a7f7 VS |
356 | }; |
357 | ||
72bbf0af | 358 | static const struct intel_device_info intel_skylake_info = { |
7201c0b3 | 359 | .is_skylake = 1, |
72bbf0af DL |
360 | .gen = 9, .num_pipes = 3, |
361 | .need_gfx_hws = 1, .has_hotplug = 1, | |
362 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
363 | .has_llc = 1, | |
364 | .has_ddi = 1, | |
6c908bf4 | 365 | .has_fpga_dbg = 1, |
043efb11 | 366 | .has_fbc = 1, |
72bbf0af DL |
367 | GEN_DEFAULT_PIPEOFFSETS, |
368 | IVB_CURSOR_OFFSETS, | |
369 | }; | |
370 | ||
719388e1 | 371 | static const struct intel_device_info intel_skylake_gt3_info = { |
719388e1 DL |
372 | .is_skylake = 1, |
373 | .gen = 9, .num_pipes = 3, | |
374 | .need_gfx_hws = 1, .has_hotplug = 1, | |
375 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, | |
376 | .has_llc = 1, | |
377 | .has_ddi = 1, | |
6c908bf4 | 378 | .has_fpga_dbg = 1, |
719388e1 DL |
379 | .has_fbc = 1, |
380 | GEN_DEFAULT_PIPEOFFSETS, | |
381 | IVB_CURSOR_OFFSETS, | |
382 | }; | |
383 | ||
1347f5b4 DL |
384 | static const struct intel_device_info intel_broxton_info = { |
385 | .is_preliminary = 1, | |
386 | .gen = 9, | |
387 | .need_gfx_hws = 1, .has_hotplug = 1, | |
388 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
389 | .num_pipes = 3, | |
390 | .has_ddi = 1, | |
6c908bf4 | 391 | .has_fpga_dbg = 1, |
ce89db2e | 392 | .has_fbc = 1, |
1347f5b4 DL |
393 | GEN_DEFAULT_PIPEOFFSETS, |
394 | IVB_CURSOR_OFFSETS, | |
395 | }; | |
396 | ||
a0a18075 JB |
397 | /* |
398 | * Make sure any device matches here are from most specific to most | |
399 | * general. For example, since the Quanta match is based on the subsystem | |
400 | * and subvendor IDs, we need it to come before the more general IVB | |
401 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
402 | */ | |
403 | #define INTEL_PCI_IDS \ | |
404 | INTEL_I830_IDS(&intel_i830_info), \ | |
405 | INTEL_I845G_IDS(&intel_845g_info), \ | |
406 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
407 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
408 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
409 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
410 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
411 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
412 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
413 | INTEL_G33_IDS(&intel_g33_info), \ | |
414 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
415 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
416 | INTEL_G45_IDS(&intel_g45_info), \ | |
417 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
418 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
419 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
420 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
421 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
422 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
423 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
424 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
425 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
426 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
427 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
4d4dead6 | 428 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ |
fd3c269f ZY |
429 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ |
430 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ | |
431 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ | |
7d87a7f7 | 432 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \ |
72bbf0af | 433 | INTEL_CHV_IDS(&intel_cherryview_info), \ |
719388e1 DL |
434 | INTEL_SKL_GT1_IDS(&intel_skylake_info), \ |
435 | INTEL_SKL_GT2_IDS(&intel_skylake_info), \ | |
1347f5b4 DL |
436 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \ |
437 | INTEL_BXT_IDS(&intel_broxton_info) | |
a0a18075 | 438 | |
6103da0d | 439 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 440 | INTEL_PCI_IDS, |
49ae35f2 | 441 | {0, 0, 0} |
1da177e4 LT |
442 | }; |
443 | ||
79e53945 | 444 | MODULE_DEVICE_TABLE(pci, pciidlist); |
79e53945 | 445 | |
0206e353 | 446 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
447 | { |
448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 449 | struct pci_dev *pch = NULL; |
3bad0781 | 450 | |
ce1bb329 BW |
451 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
452 | * (which really amounts to a PCH but no South Display). | |
453 | */ | |
454 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
455 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
456 | return; |
457 | } | |
458 | ||
3bad0781 ZW |
459 | /* |
460 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
461 | * make graphics device passthrough work easy for VMM, that only | |
462 | * need to expose ISA bridge to let driver know the real hardware | |
463 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
464 | * |
465 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
466 | * ISA bridge in the system. To work reliably, we should scan trhough | |
467 | * all the ISA bridge devices and check for the first match, instead | |
468 | * of only checking the first one. | |
3bad0781 | 469 | */ |
bcdb72ac | 470 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 471 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 472 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 473 | dev_priv->pch_id = id; |
3bad0781 | 474 | |
90711d50 JB |
475 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
476 | dev_priv->pch_type = PCH_IBX; | |
477 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 478 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 479 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
480 | dev_priv->pch_type = PCH_CPT; |
481 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 482 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
483 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
484 | /* PantherPoint is CPT compatible */ | |
485 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 486 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 487 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
488 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
489 | dev_priv->pch_type = PCH_LPT; | |
490 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
a35cc9d0 RV |
491 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
492 | WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); | |
e76e0634 BW |
493 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
494 | dev_priv->pch_type = PCH_LPT; | |
495 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
a35cc9d0 RV |
496 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
497 | WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); | |
e7e7ea20 S |
498 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
499 | dev_priv->pch_type = PCH_SPT; | |
500 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
501 | WARN_ON(!IS_SKYLAKE(dev)); | |
e7e7ea20 S |
502 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
503 | dev_priv->pch_type = PCH_SPT; | |
504 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
505 | WARN_ON(!IS_SKYLAKE(dev)); | |
bcdb72ac ID |
506 | } else |
507 | continue; | |
508 | ||
6a9c4b35 | 509 | break; |
3bad0781 | 510 | } |
3bad0781 | 511 | } |
6a9c4b35 | 512 | if (!pch) |
bcdb72ac ID |
513 | DRM_DEBUG_KMS("No PCH found.\n"); |
514 | ||
515 | pci_dev_put(pch); | |
3bad0781 ZW |
516 | } |
517 | ||
2911a35b BW |
518 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
519 | { | |
520 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 521 | return false; |
2911a35b | 522 | |
d330a953 JN |
523 | if (i915.semaphores >= 0) |
524 | return i915.semaphores; | |
2911a35b | 525 | |
71386ef9 OM |
526 | /* TODO: make semaphores and Execlists play nicely together */ |
527 | if (i915.enable_execlists) | |
528 | return false; | |
529 | ||
be71eabe RV |
530 | /* Until we get further testing... */ |
531 | if (IS_GEN8(dev)) | |
532 | return false; | |
533 | ||
59de3295 | 534 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 535 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
536 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
537 | return false; | |
538 | #endif | |
2911a35b | 539 | |
a08acaf2 | 540 | return true; |
2911a35b BW |
541 | } |
542 | ||
eb805623 DV |
543 | void i915_firmware_load_error_print(const char *fw_path, int err) |
544 | { | |
545 | DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err); | |
546 | ||
547 | /* | |
548 | * If the reason is not known assume -ENOENT since that's the most | |
549 | * usual failure mode. | |
550 | */ | |
551 | if (!err) | |
552 | err = -ENOENT; | |
553 | ||
554 | if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT)) | |
555 | return; | |
556 | ||
557 | DRM_ERROR( | |
558 | "The driver is built-in, so to load the firmware you need to\n" | |
559 | "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n" | |
560 | "in your initrd/initramfs image.\n"); | |
561 | } | |
562 | ||
07f9cd0b ID |
563 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
564 | { | |
565 | struct drm_device *dev = dev_priv->dev; | |
566 | struct drm_encoder *encoder; | |
567 | ||
568 | drm_modeset_lock_all(dev); | |
569 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
570 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
571 | ||
572 | if (intel_encoder->suspend) | |
573 | intel_encoder->suspend(intel_encoder); | |
574 | } | |
575 | drm_modeset_unlock_all(dev); | |
576 | } | |
577 | ||
ebc32824 | 578 | static int intel_suspend_complete(struct drm_i915_private *dev_priv); |
1a5df187 PZ |
579 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
580 | bool rpm_resume); | |
f75a1985 | 581 | static int skl_resume_prepare(struct drm_i915_private *dev_priv); |
a9a6b73a | 582 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv); |
f75a1985 | 583 | |
ebc32824 | 584 | |
5e365c39 | 585 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 586 | { |
61caf87c | 587 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5747e3a | 588 | pci_power_t opregion_target_state; |
d5818938 | 589 | int error; |
61caf87c | 590 | |
b8efb17b ZR |
591 | /* ignore lid events during suspend */ |
592 | mutex_lock(&dev_priv->modeset_restore_lock); | |
593 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
594 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
595 | ||
c67a470b PZ |
596 | /* We do a lot of poking in a lot of registers, make sure they work |
597 | * properly. */ | |
da7e29bd | 598 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 599 | |
5bcf719b DA |
600 | drm_kms_helper_poll_disable(dev); |
601 | ||
ba8bbcf6 | 602 | pci_save_state(dev->pdev); |
ba8bbcf6 | 603 | |
d5818938 DV |
604 | error = i915_gem_suspend(dev); |
605 | if (error) { | |
606 | dev_err(&dev->pdev->dev, | |
607 | "GEM idle failed, resume might fail\n"); | |
608 | return error; | |
609 | } | |
db1b76ca | 610 | |
d5818938 | 611 | intel_suspend_gt_powersave(dev); |
a261b246 | 612 | |
d5818938 DV |
613 | /* |
614 | * Disable CRTCs directly since we want to preserve sw state | |
615 | * for _thaw. Also, power gate the CRTC power wells. | |
616 | */ | |
617 | drm_modeset_lock_all(dev); | |
6b72d486 | 618 | intel_display_suspend(dev); |
d5818938 | 619 | drm_modeset_unlock_all(dev); |
2eb5252e | 620 | |
d5818938 | 621 | intel_dp_mst_suspend(dev); |
7d708ee4 | 622 | |
d5818938 DV |
623 | intel_runtime_pm_disable_interrupts(dev_priv); |
624 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 625 | |
d5818938 | 626 | intel_suspend_encoders(dev_priv); |
0e32b39c | 627 | |
d5818938 | 628 | intel_suspend_hw(dev); |
5669fcac | 629 | |
828c7908 BW |
630 | i915_gem_suspend_gtt_mappings(dev); |
631 | ||
9e06dd39 JB |
632 | i915_save_state(dev); |
633 | ||
95fa2eee ID |
634 | opregion_target_state = PCI_D3cold; |
635 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
636 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
e5747e3a | 637 | opregion_target_state = PCI_D1; |
95fa2eee | 638 | #endif |
e5747e3a JB |
639 | intel_opregion_notify_adapter(dev, opregion_target_state); |
640 | ||
156c7ca0 | 641 | intel_uncore_forcewake_reset(dev, false); |
44834a67 | 642 | intel_opregion_fini(dev); |
8ee1c3db | 643 | |
82e3b8c1 | 644 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 645 | |
62d5d69b MK |
646 | dev_priv->suspend_count++; |
647 | ||
85e90679 KCA |
648 | intel_display_set_init_power(dev_priv, false); |
649 | ||
61caf87c | 650 | return 0; |
84b79f8d RW |
651 | } |
652 | ||
ab3be73f | 653 | static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) |
c3c09c95 ID |
654 | { |
655 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
656 | int ret; | |
657 | ||
658 | ret = intel_suspend_complete(dev_priv); | |
659 | ||
660 | if (ret) { | |
661 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
662 | ||
663 | return ret; | |
664 | } | |
665 | ||
666 | pci_disable_device(drm_dev->pdev); | |
ab3be73f ID |
667 | /* |
668 | * During hibernation on some GEN4 platforms the BIOS may try to access | |
669 | * the device even though it's already in D3 and hang the machine. So | |
670 | * leave the device in D0 on those platforms and hope the BIOS will | |
671 | * power down the device properly. Platforms where this was seen: | |
672 | * Lenovo Thinkpad X301, X61s | |
673 | */ | |
674 | if (!(hibernation && | |
675 | drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO && | |
676 | INTEL_INFO(dev_priv)->gen == 4)) | |
677 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); | |
c3c09c95 ID |
678 | |
679 | return 0; | |
680 | } | |
681 | ||
fc49b3da | 682 | int i915_suspend_legacy(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
683 | { |
684 | int error; | |
685 | ||
686 | if (!dev || !dev->dev_private) { | |
687 | DRM_ERROR("dev: %p\n", dev); | |
688 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
689 | return -ENODEV; | |
690 | } | |
691 | ||
0b14cbd2 ID |
692 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
693 | state.event != PM_EVENT_FREEZE)) | |
694 | return -EINVAL; | |
5bcf719b DA |
695 | |
696 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
697 | return 0; | |
6eecba33 | 698 | |
5e365c39 | 699 | error = i915_drm_suspend(dev); |
84b79f8d RW |
700 | if (error) |
701 | return error; | |
702 | ||
ab3be73f | 703 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
704 | } |
705 | ||
5e365c39 | 706 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 ID |
707 | { |
708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9d49c0ef | 709 | |
d5818938 DV |
710 | mutex_lock(&dev->struct_mutex); |
711 | i915_gem_restore_gtt_mappings(dev); | |
712 | mutex_unlock(&dev->struct_mutex); | |
9d49c0ef | 713 | |
61caf87c | 714 | i915_restore_state(dev); |
44834a67 | 715 | intel_opregion_setup(dev); |
61caf87c | 716 | |
d5818938 DV |
717 | intel_init_pch_refclk(dev); |
718 | drm_mode_config_reset(dev); | |
1833b134 | 719 | |
364aece0 PA |
720 | /* |
721 | * Interrupts have to be enabled before any batches are run. If not the | |
722 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
723 | * update/restore the context. | |
724 | * | |
725 | * Modeset enabling in intel_modeset_init_hw() also needs working | |
726 | * interrupts. | |
727 | */ | |
728 | intel_runtime_pm_enable_interrupts(dev_priv); | |
729 | ||
d5818938 DV |
730 | mutex_lock(&dev->struct_mutex); |
731 | if (i915_gem_init_hw(dev)) { | |
732 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
733 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
734 | } | |
735 | mutex_unlock(&dev->struct_mutex); | |
226485e9 | 736 | |
d5818938 | 737 | intel_modeset_init_hw(dev); |
24576d23 | 738 | |
d5818938 DV |
739 | spin_lock_irq(&dev_priv->irq_lock); |
740 | if (dev_priv->display.hpd_irq_setup) | |
741 | dev_priv->display.hpd_irq_setup(dev); | |
742 | spin_unlock_irq(&dev_priv->irq_lock); | |
0e32b39c | 743 | |
d5818938 | 744 | drm_modeset_lock_all(dev); |
043e9bda | 745 | intel_display_resume(dev); |
d5818938 | 746 | drm_modeset_unlock_all(dev); |
15239099 | 747 | |
d5818938 | 748 | intel_dp_mst_resume(dev); |
e7d6f7d7 | 749 | |
d5818938 DV |
750 | /* |
751 | * ... but also need to make sure that hotplug processing | |
752 | * doesn't cause havoc. Like in the driver load code we don't | |
753 | * bother with the tiny race here where we might loose hotplug | |
754 | * notifications. | |
755 | * */ | |
756 | intel_hpd_init(dev_priv); | |
757 | /* Config may have changed between suspend and resume */ | |
758 | drm_helper_hpd_irq_event(dev); | |
1daed3fb | 759 | |
44834a67 CW |
760 | intel_opregion_init(dev); |
761 | ||
82e3b8c1 | 762 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 763 | |
b8efb17b ZR |
764 | mutex_lock(&dev_priv->modeset_restore_lock); |
765 | dev_priv->modeset_restore = MODESET_DONE; | |
766 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 767 | |
e5747e3a JB |
768 | intel_opregion_notify_adapter(dev, PCI_D0); |
769 | ||
ee6f280e ID |
770 | drm_kms_helper_poll_enable(dev); |
771 | ||
074c6ada | 772 | return 0; |
84b79f8d RW |
773 | } |
774 | ||
5e365c39 | 775 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 776 | { |
36d61e67 | 777 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a5df187 | 778 | int ret = 0; |
36d61e67 | 779 | |
76c4b250 ID |
780 | /* |
781 | * We have a resume ordering issue with the snd-hda driver also | |
782 | * requiring our device to be power up. Due to the lack of a | |
783 | * parent/child relationship we currently solve this with an early | |
784 | * resume hook. | |
785 | * | |
786 | * FIXME: This should be solved with a special hdmi sink device or | |
787 | * similar so that power domains can be employed. | |
788 | */ | |
84b79f8d RW |
789 | if (pci_enable_device(dev->pdev)) |
790 | return -EIO; | |
791 | ||
792 | pci_set_master(dev->pdev); | |
793 | ||
efee833a | 794 | if (IS_VALLEYVIEW(dev_priv)) |
1a5df187 | 795 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 796 | if (ret) |
ff0b187f DL |
797 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
798 | ret); | |
36d61e67 ID |
799 | |
800 | intel_uncore_early_sanitize(dev, true); | |
efee833a | 801 | |
a9a6b73a DL |
802 | if (IS_BROXTON(dev)) |
803 | ret = bxt_resume_prepare(dev_priv); | |
f75a1985 SS |
804 | else if (IS_SKYLAKE(dev_priv)) |
805 | ret = skl_resume_prepare(dev_priv); | |
a9a6b73a DL |
806 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
807 | hsw_disable_pc8(dev_priv); | |
efee833a | 808 | |
36d61e67 ID |
809 | intel_uncore_sanitize(dev); |
810 | intel_power_domains_init_hw(dev_priv); | |
811 | ||
812 | return ret; | |
76c4b250 ID |
813 | } |
814 | ||
fc49b3da | 815 | int i915_resume_legacy(struct drm_device *dev) |
76c4b250 | 816 | { |
50a0072f | 817 | int ret; |
76c4b250 | 818 | |
097dd837 ID |
819 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
820 | return 0; | |
821 | ||
5e365c39 | 822 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
823 | if (ret) |
824 | return ret; | |
825 | ||
5a17514e ID |
826 | return i915_drm_resume(dev); |
827 | } | |
828 | ||
11ed50ec | 829 | /** |
f3953dcb | 830 | * i915_reset - reset chip after a hang |
11ed50ec | 831 | * @dev: drm device to reset |
11ed50ec BG |
832 | * |
833 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
834 | * reset or otherwise an error code. | |
835 | * | |
836 | * Procedure is fairly simple: | |
837 | * - reset the chip using the reset reg | |
838 | * - re-init context state | |
839 | * - re-init hardware status page | |
840 | * - re-init ring buffer | |
841 | * - re-init interrupt state | |
842 | * - re-init display | |
843 | */ | |
d4b8bb2a | 844 | int i915_reset(struct drm_device *dev) |
11ed50ec | 845 | { |
50227e1c | 846 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 847 | bool simulated; |
0573ed4a | 848 | int ret; |
11ed50ec | 849 | |
dbea3cea ID |
850 | intel_reset_gt_powersave(dev); |
851 | ||
d54a02c0 | 852 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 853 | |
069efc1d | 854 | i915_gem_reset(dev); |
77f01230 | 855 | |
2e7c8ee7 CW |
856 | simulated = dev_priv->gpu_error.stop_rings != 0; |
857 | ||
be62acb4 MK |
858 | ret = intel_gpu_reset(dev); |
859 | ||
860 | /* Also reset the gpu hangman. */ | |
861 | if (simulated) { | |
862 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
863 | dev_priv->gpu_error.stop_rings = 0; | |
864 | if (ret == -ENODEV) { | |
f2d91a2c DV |
865 | DRM_INFO("Reset not implemented, but ignoring " |
866 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
867 | ret = 0; |
868 | } | |
2e7c8ee7 | 869 | } |
be62acb4 | 870 | |
d8f2716a DV |
871 | if (i915_stop_ring_allow_warn(dev_priv)) |
872 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); | |
873 | ||
0573ed4a | 874 | if (ret) { |
f2d91a2c | 875 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 876 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 877 | return ret; |
11ed50ec BG |
878 | } |
879 | ||
1362b776 VS |
880 | intel_overlay_reset(dev_priv); |
881 | ||
11ed50ec BG |
882 | /* Ok, now get things going again... */ |
883 | ||
884 | /* | |
885 | * Everything depends on having the GTT running, so we need to start | |
886 | * there. Fortunately we don't need to do this unless we reset the | |
887 | * chip at a PCI level. | |
888 | * | |
889 | * Next we need to restore the context, but we don't use those | |
890 | * yet either... | |
891 | * | |
892 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
893 | * was running at the time of the reset (i.e. we weren't VT | |
894 | * switched away). | |
895 | */ | |
6689c167 | 896 | |
33d30a9c DV |
897 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
898 | dev_priv->gpu_error.reload_in_reset = true; | |
6689c167 | 899 | |
33d30a9c | 900 | ret = i915_gem_init_hw(dev); |
6689c167 | 901 | |
33d30a9c | 902 | dev_priv->gpu_error.reload_in_reset = false; |
f817586c | 903 | |
33d30a9c DV |
904 | mutex_unlock(&dev->struct_mutex); |
905 | if (ret) { | |
906 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
907 | return ret; | |
11ed50ec BG |
908 | } |
909 | ||
33d30a9c DV |
910 | /* |
911 | * rps/rc6 re-init is necessary to restore state lost after the | |
912 | * reset and the re-install of gt irqs. Skip for ironlake per | |
913 | * previous concerns that it doesn't respond well to some forms | |
914 | * of re-init after reset. | |
915 | */ | |
916 | if (INTEL_INFO(dev)->gen > 5) | |
917 | intel_enable_gt_powersave(dev); | |
918 | ||
11ed50ec BG |
919 | return 0; |
920 | } | |
921 | ||
56550d94 | 922 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 923 | { |
01a06850 DV |
924 | struct intel_device_info *intel_info = |
925 | (struct intel_device_info *) ent->driver_data; | |
926 | ||
d330a953 | 927 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
928 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
929 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
930 | return -ENODEV; | |
931 | } | |
932 | ||
5fe49d86 CW |
933 | /* Only bind to function 0 of the device. Early generations |
934 | * used function 1 as a placeholder for multi-head. This causes | |
935 | * us confusion instead, especially on the systems where both | |
936 | * functions have the same PCI-ID! | |
937 | */ | |
938 | if (PCI_FUNC(pdev->devfn)) | |
939 | return -ENODEV; | |
940 | ||
dcdb1674 | 941 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
942 | } |
943 | ||
944 | static void | |
945 | i915_pci_remove(struct pci_dev *pdev) | |
946 | { | |
947 | struct drm_device *dev = pci_get_drvdata(pdev); | |
948 | ||
949 | drm_put_dev(dev); | |
950 | } | |
951 | ||
84b79f8d | 952 | static int i915_pm_suspend(struct device *dev) |
112b715e | 953 | { |
84b79f8d RW |
954 | struct pci_dev *pdev = to_pci_dev(dev); |
955 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 956 | |
84b79f8d RW |
957 | if (!drm_dev || !drm_dev->dev_private) { |
958 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
959 | return -ENODEV; | |
960 | } | |
112b715e | 961 | |
5bcf719b DA |
962 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
963 | return 0; | |
964 | ||
5e365c39 | 965 | return i915_drm_suspend(drm_dev); |
76c4b250 ID |
966 | } |
967 | ||
968 | static int i915_pm_suspend_late(struct device *dev) | |
969 | { | |
888d0d42 | 970 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 ID |
971 | |
972 | /* | |
c965d995 | 973 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
974 | * requiring our device to be power up. Due to the lack of a |
975 | * parent/child relationship we currently solve this with an late | |
976 | * suspend hook. | |
977 | * | |
978 | * FIXME: This should be solved with a special hdmi sink device or | |
979 | * similar so that power domains can be employed. | |
980 | */ | |
981 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
982 | return 0; | |
112b715e | 983 | |
ab3be73f ID |
984 | return i915_drm_suspend_late(drm_dev, false); |
985 | } | |
986 | ||
987 | static int i915_pm_poweroff_late(struct device *dev) | |
988 | { | |
989 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; | |
990 | ||
991 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
992 | return 0; | |
993 | ||
994 | return i915_drm_suspend_late(drm_dev, true); | |
cbda12d7 ZW |
995 | } |
996 | ||
76c4b250 ID |
997 | static int i915_pm_resume_early(struct device *dev) |
998 | { | |
888d0d42 | 999 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 | 1000 | |
097dd837 ID |
1001 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1002 | return 0; | |
1003 | ||
5e365c39 | 1004 | return i915_drm_resume_early(drm_dev); |
76c4b250 ID |
1005 | } |
1006 | ||
84b79f8d | 1007 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 1008 | { |
888d0d42 | 1009 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
84b79f8d | 1010 | |
097dd837 ID |
1011 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1012 | return 0; | |
1013 | ||
5a17514e | 1014 | return i915_drm_resume(drm_dev); |
cbda12d7 ZW |
1015 | } |
1016 | ||
f75a1985 SS |
1017 | static int skl_suspend_complete(struct drm_i915_private *dev_priv) |
1018 | { | |
1019 | /* Enabling DC6 is not a hard requirement to enter runtime D3 */ | |
1020 | ||
1021 | /* | |
1022 | * This is to ensure that CSR isn't identified as loaded before | |
1023 | * CSR-loading program is called during runtime-resume. | |
1024 | */ | |
1025 | intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED); | |
1026 | ||
5d96d8af DL |
1027 | skl_uninit_cdclk(dev_priv); |
1028 | ||
f75a1985 SS |
1029 | return 0; |
1030 | } | |
1031 | ||
ebc32824 | 1032 | static int hsw_suspend_complete(struct drm_i915_private *dev_priv) |
97bea207 | 1033 | { |
414de7a0 | 1034 | hsw_enable_pc8(dev_priv); |
0ab9cfeb ID |
1035 | |
1036 | return 0; | |
97bea207 PZ |
1037 | } |
1038 | ||
31335cec SS |
1039 | static int bxt_suspend_complete(struct drm_i915_private *dev_priv) |
1040 | { | |
1041 | struct drm_device *dev = dev_priv->dev; | |
1042 | ||
1043 | /* TODO: when DC5 support is added disable DC5 here. */ | |
1044 | ||
1045 | broxton_ddi_phy_uninit(dev); | |
1046 | broxton_uninit_cdclk(dev); | |
1047 | bxt_enable_dc9(dev_priv); | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv) | |
1053 | { | |
1054 | struct drm_device *dev = dev_priv->dev; | |
1055 | ||
1056 | /* TODO: when CSR FW support is added make sure the FW is loaded */ | |
1057 | ||
1058 | bxt_disable_dc9(dev_priv); | |
1059 | ||
1060 | /* | |
1061 | * TODO: when DC5 support is added enable DC5 here if the CSR FW | |
1062 | * is available. | |
1063 | */ | |
1064 | broxton_init_cdclk(dev); | |
1065 | broxton_ddi_phy_init(dev); | |
1066 | intel_prepare_ddi(dev); | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
f75a1985 SS |
1071 | static int skl_resume_prepare(struct drm_i915_private *dev_priv) |
1072 | { | |
1073 | struct drm_device *dev = dev_priv->dev; | |
1074 | ||
5d96d8af | 1075 | skl_init_cdclk(dev_priv); |
f75a1985 SS |
1076 | intel_csr_load_program(dev); |
1077 | ||
1078 | return 0; | |
1079 | } | |
1080 | ||
ddeea5b0 ID |
1081 | /* |
1082 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
1083 | * S0i[R123] transition. The list of registers needing a save/restore is | |
1084 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
1085 | * registers in the following way: | |
1086 | * - Driver: saved/restored by the driver | |
1087 | * - Punit : saved/restored by the Punit firmware | |
1088 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
1089 | * used internally by the HW in a way that doesn't depend | |
1090 | * keeping the content across a suspend/resume. | |
1091 | * - Debug : used for debugging | |
1092 | * | |
1093 | * We save/restore all registers marked with 'Driver', with the following | |
1094 | * exceptions: | |
1095 | * - Registers out of use, including also registers marked with 'Debug'. | |
1096 | * These have no effect on the driver's operation, so we don't save/restore | |
1097 | * them to reduce the overhead. | |
1098 | * - Registers that are fully setup by an initialization function called from | |
1099 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1100 | * - Registers that provide the right functionality with their reset defaults. | |
1101 | * | |
1102 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1103 | * ignored, we save/restore all others, practically treating the HW context as | |
1104 | * a black-box for the driver. Further investigation is needed to reduce the | |
1105 | * saved/restored registers even further, by following the same 3 criteria. | |
1106 | */ | |
1107 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1108 | { | |
1109 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1110 | int i; | |
1111 | ||
1112 | /* GAM 0x4000-0x4770 */ | |
1113 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1114 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1115 | s->arb_mode = I915_READ(ARB_MODE); | |
1116 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1117 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1118 | ||
1119 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1120 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); | |
1121 | ||
1122 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 1123 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
1124 | |
1125 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1126 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1127 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1128 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1129 | ||
1130 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1131 | ||
1132 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1133 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1134 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1135 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1136 | ||
1137 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1138 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1139 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1140 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1141 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1142 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1143 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1144 | ||
1145 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1146 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1147 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1148 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1149 | s->ecobus = I915_READ(ECOBUS); | |
1150 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1151 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1152 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1153 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1154 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1155 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1156 | ||
1157 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1158 | s->gt_imr = I915_READ(GTIMR); | |
1159 | s->gt_ier = I915_READ(GTIER); | |
1160 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1161 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1162 | ||
1163 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1164 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); | |
1165 | ||
1166 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1167 | s->tilectl = I915_READ(TILECTL); | |
1168 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1169 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1170 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1171 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1172 | ||
1173 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1174 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1175 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 1176 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
1177 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
1178 | ||
1179 | /* | |
1180 | * Not saving any of: | |
1181 | * DFT, 0x9800-0x9EC0 | |
1182 | * SARB, 0xB000-0xB1FC | |
1183 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1184 | * PCI CFG | |
1185 | */ | |
1186 | } | |
1187 | ||
1188 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1189 | { | |
1190 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1191 | u32 val; | |
1192 | int i; | |
1193 | ||
1194 | /* GAM 0x4000-0x4770 */ | |
1195 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1196 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1197 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1198 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1199 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1200 | ||
1201 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1202 | I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); | |
1203 | ||
1204 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 1205 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
1206 | |
1207 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1208 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1209 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1210 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1211 | ||
1212 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1213 | ||
1214 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1215 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1216 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1217 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1218 | ||
1219 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1220 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1221 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1222 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1223 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1224 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1225 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1226 | ||
1227 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1228 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1229 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1230 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1231 | I915_WRITE(ECOBUS, s->ecobus); | |
1232 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1233 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1234 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1235 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1236 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1237 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1238 | ||
1239 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1240 | I915_WRITE(GTIMR, s->gt_imr); | |
1241 | I915_WRITE(GTIER, s->gt_ier); | |
1242 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1243 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1244 | ||
1245 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1246 | I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); | |
1247 | ||
1248 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1249 | I915_WRITE(TILECTL, s->tilectl); | |
1250 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1251 | /* | |
1252 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1253 | * be restored, as they are used to control the s0ix suspend/resume | |
1254 | * sequence by the caller. | |
1255 | */ | |
1256 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1257 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1258 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1259 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1260 | ||
1261 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1262 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1263 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1264 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1265 | ||
1266 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1267 | ||
1268 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1269 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1270 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 1271 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
1272 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
1273 | } | |
1274 | ||
650ad970 ID |
1275 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1276 | { | |
1277 | u32 val; | |
1278 | int err; | |
1279 | ||
650ad970 | 1280 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) |
650ad970 ID |
1281 | |
1282 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1283 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1284 | if (force_on) | |
1285 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1286 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1287 | ||
1288 | if (!force_on) | |
1289 | return 0; | |
1290 | ||
8d4eee9c | 1291 | err = wait_for(COND, 20); |
650ad970 ID |
1292 | if (err) |
1293 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1294 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1295 | ||
1296 | return err; | |
1297 | #undef COND | |
1298 | } | |
1299 | ||
ddeea5b0 ID |
1300 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1301 | { | |
1302 | u32 val; | |
1303 | int err = 0; | |
1304 | ||
1305 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1306 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1307 | if (allow) | |
1308 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1309 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1310 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1311 | ||
1312 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1313 | allow) | |
1314 | err = wait_for(COND, 1); | |
1315 | if (err) | |
1316 | DRM_ERROR("timeout disabling GT waking\n"); | |
1317 | return err; | |
1318 | #undef COND | |
1319 | } | |
1320 | ||
1321 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1322 | bool wait_for_on) | |
1323 | { | |
1324 | u32 mask; | |
1325 | u32 val; | |
1326 | int err; | |
1327 | ||
1328 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1329 | val = wait_for_on ? mask : 0; | |
1330 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1331 | if (COND) | |
1332 | return 0; | |
1333 | ||
1334 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
1335 | wait_for_on ? "on" : "off", | |
1336 | I915_READ(VLV_GTLC_PW_STATUS)); | |
1337 | ||
1338 | /* | |
1339 | * RC6 transitioning can be delayed up to 2 msec (see | |
1340 | * valleyview_enable_rps), use 3 msec for safety. | |
1341 | */ | |
1342 | err = wait_for(COND, 3); | |
1343 | if (err) | |
1344 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
1345 | wait_for_on ? "on" : "off"); | |
1346 | ||
1347 | return err; | |
1348 | #undef COND | |
1349 | } | |
1350 | ||
1351 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1352 | { | |
1353 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1354 | return; | |
1355 | ||
1356 | DRM_ERROR("GT register access while GT waking disabled\n"); | |
1357 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); | |
1358 | } | |
1359 | ||
ebc32824 | 1360 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
1361 | { |
1362 | u32 mask; | |
1363 | int err; | |
1364 | ||
1365 | /* | |
1366 | * Bspec defines the following GT well on flags as debug only, so | |
1367 | * don't treat them as hard failures. | |
1368 | */ | |
1369 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1370 | ||
1371 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1372 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1373 | ||
1374 | vlv_check_no_gt_access(dev_priv); | |
1375 | ||
1376 | err = vlv_force_gfx_clock(dev_priv, true); | |
1377 | if (err) | |
1378 | goto err1; | |
1379 | ||
1380 | err = vlv_allow_gt_wake(dev_priv, false); | |
1381 | if (err) | |
1382 | goto err2; | |
98711167 D |
1383 | |
1384 | if (!IS_CHERRYVIEW(dev_priv->dev)) | |
1385 | vlv_save_gunit_s0ix_state(dev_priv); | |
ddeea5b0 ID |
1386 | |
1387 | err = vlv_force_gfx_clock(dev_priv, false); | |
1388 | if (err) | |
1389 | goto err2; | |
1390 | ||
1391 | return 0; | |
1392 | ||
1393 | err2: | |
1394 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1395 | vlv_allow_gt_wake(dev_priv, true); | |
1396 | err1: | |
1397 | vlv_force_gfx_clock(dev_priv, false); | |
1398 | ||
1399 | return err; | |
1400 | } | |
1401 | ||
016970be SK |
1402 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1403 | bool rpm_resume) | |
ddeea5b0 ID |
1404 | { |
1405 | struct drm_device *dev = dev_priv->dev; | |
1406 | int err; | |
1407 | int ret; | |
1408 | ||
1409 | /* | |
1410 | * If any of the steps fail just try to continue, that's the best we | |
1411 | * can do at this point. Return the first error code (which will also | |
1412 | * leave RPM permanently disabled). | |
1413 | */ | |
1414 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1415 | ||
98711167 D |
1416 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
1417 | vlv_restore_gunit_s0ix_state(dev_priv); | |
ddeea5b0 ID |
1418 | |
1419 | err = vlv_allow_gt_wake(dev_priv, true); | |
1420 | if (!ret) | |
1421 | ret = err; | |
1422 | ||
1423 | err = vlv_force_gfx_clock(dev_priv, false); | |
1424 | if (!ret) | |
1425 | ret = err; | |
1426 | ||
1427 | vlv_check_no_gt_access(dev_priv); | |
1428 | ||
016970be SK |
1429 | if (rpm_resume) { |
1430 | intel_init_clock_gating(dev); | |
1431 | i915_gem_restore_fences(dev); | |
1432 | } | |
ddeea5b0 ID |
1433 | |
1434 | return ret; | |
1435 | } | |
1436 | ||
97bea207 | 1437 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1438 | { |
1439 | struct pci_dev *pdev = to_pci_dev(device); | |
1440 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1442 | int ret; |
8a187455 | 1443 | |
aeab0b5a | 1444 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1445 | return -ENODEV; |
1446 | ||
604effb7 ID |
1447 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1448 | return -ENODEV; | |
1449 | ||
8a187455 PZ |
1450 | DRM_DEBUG_KMS("Suspending device\n"); |
1451 | ||
d6102977 ID |
1452 | /* |
1453 | * We could deadlock here in case another thread holding struct_mutex | |
1454 | * calls RPM suspend concurrently, since the RPM suspend will wait | |
1455 | * first for this RPM suspend to finish. In this case the concurrent | |
1456 | * RPM resume will be followed by its RPM suspend counterpart. Still | |
1457 | * for consistency return -EAGAIN, which will reschedule this suspend. | |
1458 | */ | |
1459 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1460 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); | |
1461 | /* | |
1462 | * Bump the expiration timestamp, otherwise the suspend won't | |
1463 | * be rescheduled. | |
1464 | */ | |
1465 | pm_runtime_mark_last_busy(device); | |
1466 | ||
1467 | return -EAGAIN; | |
1468 | } | |
1469 | /* | |
1470 | * We are safe here against re-faults, since the fault handler takes | |
1471 | * an RPM reference. | |
1472 | */ | |
1473 | i915_gem_release_all_mmaps(dev_priv); | |
1474 | mutex_unlock(&dev->struct_mutex); | |
1475 | ||
fac6adb0 | 1476 | intel_suspend_gt_powersave(dev); |
2eb5252e | 1477 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 1478 | |
ebc32824 | 1479 | ret = intel_suspend_complete(dev_priv); |
0ab9cfeb ID |
1480 | if (ret) { |
1481 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
b963291c | 1482 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb ID |
1483 | |
1484 | return ret; | |
1485 | } | |
a8a8bd54 | 1486 | |
737b1506 | 1487 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
dc9fb09c | 1488 | intel_uncore_forcewake_reset(dev, false); |
8a187455 | 1489 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1490 | |
1491 | /* | |
c8a0bd42 PZ |
1492 | * FIXME: We really should find a document that references the arguments |
1493 | * used below! | |
1fb2362b | 1494 | */ |
d37ae19a PZ |
1495 | if (IS_BROADWELL(dev)) { |
1496 | /* | |
1497 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
1498 | * being detected, and the call we do at intel_runtime_resume() | |
1499 | * won't be able to restore them. Since PCI_D3hot matches the | |
1500 | * actual specification and appears to be working, use it. | |
1501 | */ | |
1502 | intel_opregion_notify_adapter(dev, PCI_D3hot); | |
1503 | } else { | |
c8a0bd42 PZ |
1504 | /* |
1505 | * current versions of firmware which depend on this opregion | |
1506 | * notification have repurposed the D1 definition to mean | |
1507 | * "runtime suspended" vs. what you would normally expect (D3) | |
1508 | * to distinguish it from notifications that might be sent via | |
1509 | * the suspend path. | |
1510 | */ | |
1511 | intel_opregion_notify_adapter(dev, PCI_D1); | |
c8a0bd42 | 1512 | } |
8a187455 | 1513 | |
59bad947 | 1514 | assert_forcewakes_inactive(dev_priv); |
dc9fb09c | 1515 | |
a8a8bd54 | 1516 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1517 | return 0; |
1518 | } | |
1519 | ||
97bea207 | 1520 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1521 | { |
1522 | struct pci_dev *pdev = to_pci_dev(device); | |
1523 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1a5df187 | 1525 | int ret = 0; |
8a187455 | 1526 | |
604effb7 ID |
1527 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1528 | return -ENODEV; | |
8a187455 PZ |
1529 | |
1530 | DRM_DEBUG_KMS("Resuming device\n"); | |
1531 | ||
cd2e9e90 | 1532 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 PZ |
1533 | dev_priv->pm.suspended = false; |
1534 | ||
1a5df187 PZ |
1535 | if (IS_GEN6(dev_priv)) |
1536 | intel_init_pch_refclk(dev); | |
31335cec SS |
1537 | |
1538 | if (IS_BROXTON(dev)) | |
1539 | ret = bxt_resume_prepare(dev_priv); | |
f75a1985 SS |
1540 | else if (IS_SKYLAKE(dev)) |
1541 | ret = skl_resume_prepare(dev_priv); | |
1a5df187 PZ |
1542 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
1543 | hsw_disable_pc8(dev_priv); | |
1544 | else if (IS_VALLEYVIEW(dev_priv)) | |
1545 | ret = vlv_resume_prepare(dev_priv, true); | |
1546 | ||
0ab9cfeb ID |
1547 | /* |
1548 | * No point of rolling back things in case of an error, as the best | |
1549 | * we can do is to hope that things will still work (and disable RPM). | |
1550 | */ | |
92b806d3 ID |
1551 | i915_gem_init_swizzling(dev); |
1552 | gen6_update_ring_freq(dev); | |
1553 | ||
b963291c | 1554 | intel_runtime_pm_enable_interrupts(dev_priv); |
fac6adb0 | 1555 | intel_enable_gt_powersave(dev); |
b5478bcd | 1556 | |
0ab9cfeb ID |
1557 | if (ret) |
1558 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1559 | else | |
1560 | DRM_DEBUG_KMS("Device resumed\n"); | |
1561 | ||
1562 | return ret; | |
8a187455 PZ |
1563 | } |
1564 | ||
016970be SK |
1565 | /* |
1566 | * This function implements common functionality of runtime and system | |
1567 | * suspend sequence. | |
1568 | */ | |
ebc32824 SK |
1569 | static int intel_suspend_complete(struct drm_i915_private *dev_priv) |
1570 | { | |
ebc32824 SK |
1571 | int ret; |
1572 | ||
16e44e3e | 1573 | if (IS_BROXTON(dev_priv)) |
31335cec | 1574 | ret = bxt_suspend_complete(dev_priv); |
16e44e3e | 1575 | else if (IS_SKYLAKE(dev_priv)) |
f75a1985 | 1576 | ret = skl_suspend_complete(dev_priv); |
16e44e3e | 1577 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ebc32824 | 1578 | ret = hsw_suspend_complete(dev_priv); |
16e44e3e | 1579 | else if (IS_VALLEYVIEW(dev_priv)) |
ebc32824 | 1580 | ret = vlv_suspend_complete(dev_priv); |
604effb7 ID |
1581 | else |
1582 | ret = 0; | |
ebc32824 SK |
1583 | |
1584 | return ret; | |
1585 | } | |
1586 | ||
b4b78d12 | 1587 | static const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
1588 | /* |
1589 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
1590 | * PMSG_RESUME] | |
1591 | */ | |
0206e353 | 1592 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1593 | .suspend_late = i915_pm_suspend_late, |
1594 | .resume_early = i915_pm_resume_early, | |
0206e353 | 1595 | .resume = i915_pm_resume, |
5545dbbf ID |
1596 | |
1597 | /* | |
1598 | * S4 event handlers | |
1599 | * @freeze, @freeze_late : called (1) before creating the | |
1600 | * hibernation image [PMSG_FREEZE] and | |
1601 | * (2) after rebooting, before restoring | |
1602 | * the image [PMSG_QUIESCE] | |
1603 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
1604 | * image, before writing it [PMSG_THAW] | |
1605 | * and (2) after failing to create or | |
1606 | * restore the image [PMSG_RECOVER] | |
1607 | * @poweroff, @poweroff_late: called after writing the hibernation | |
1608 | * image, before rebooting [PMSG_HIBERNATE] | |
1609 | * @restore, @restore_early : called after rebooting and restoring the | |
1610 | * hibernation image [PMSG_RESTORE] | |
1611 | */ | |
36d61e67 ID |
1612 | .freeze = i915_pm_suspend, |
1613 | .freeze_late = i915_pm_suspend_late, | |
1614 | .thaw_early = i915_pm_resume_early, | |
1615 | .thaw = i915_pm_resume, | |
1616 | .poweroff = i915_pm_suspend, | |
ab3be73f | 1617 | .poweroff_late = i915_pm_poweroff_late, |
76c4b250 | 1618 | .restore_early = i915_pm_resume_early, |
0206e353 | 1619 | .restore = i915_pm_resume, |
5545dbbf ID |
1620 | |
1621 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
1622 | .runtime_suspend = intel_runtime_suspend, |
1623 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1624 | }; |
1625 | ||
78b68556 | 1626 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1627 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1628 | .open = drm_gem_vm_open, |
1629 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1630 | }; |
1631 | ||
e08e96de AV |
1632 | static const struct file_operations i915_driver_fops = { |
1633 | .owner = THIS_MODULE, | |
1634 | .open = drm_open, | |
1635 | .release = drm_release, | |
1636 | .unlocked_ioctl = drm_ioctl, | |
1637 | .mmap = drm_gem_mmap, | |
1638 | .poll = drm_poll, | |
e08e96de AV |
1639 | .read = drm_read, |
1640 | #ifdef CONFIG_COMPAT | |
1641 | .compat_ioctl = i915_compat_ioctl, | |
1642 | #endif | |
1643 | .llseek = noop_llseek, | |
1644 | }; | |
1645 | ||
1da177e4 | 1646 | static struct drm_driver driver = { |
0c54781b MW |
1647 | /* Don't use MTRRs here; the Xserver or userspace app should |
1648 | * deal with them for Intel hardware. | |
792d2b9a | 1649 | */ |
673a394b | 1650 | .driver_features = |
10ba5012 KH |
1651 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1652 | DRIVER_RENDER, | |
22eae947 | 1653 | .load = i915_driver_load, |
ba8bbcf6 | 1654 | .unload = i915_driver_unload, |
673a394b | 1655 | .open = i915_driver_open, |
22eae947 DA |
1656 | .lastclose = i915_driver_lastclose, |
1657 | .preclose = i915_driver_preclose, | |
673a394b | 1658 | .postclose = i915_driver_postclose, |
915b4d11 | 1659 | .set_busid = drm_pci_set_busid, |
d8e29209 RW |
1660 | |
1661 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
fc49b3da | 1662 | .suspend = i915_suspend_legacy, |
76c4b250 | 1663 | .resume = i915_resume_legacy, |
d8e29209 | 1664 | |
955b12de | 1665 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1666 | .debugfs_init = i915_debugfs_init, |
1667 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1668 | #endif |
673a394b | 1669 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1670 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1671 | |
1672 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1673 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1674 | .gem_prime_export = i915_gem_prime_export, | |
1675 | .gem_prime_import = i915_gem_prime_import, | |
1676 | ||
ff72145b | 1677 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 1678 | .dumb_map_offset = i915_gem_mmap_gtt, |
43387b37 | 1679 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1680 | .ioctls = i915_ioctls, |
e08e96de | 1681 | .fops = &i915_driver_fops, |
22eae947 DA |
1682 | .name = DRIVER_NAME, |
1683 | .desc = DRIVER_DESC, | |
1684 | .date = DRIVER_DATE, | |
1685 | .major = DRIVER_MAJOR, | |
1686 | .minor = DRIVER_MINOR, | |
1687 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1688 | }; |
1689 | ||
8410ea3b DA |
1690 | static struct pci_driver i915_pci_driver = { |
1691 | .name = DRIVER_NAME, | |
1692 | .id_table = pciidlist, | |
1693 | .probe = i915_pci_probe, | |
1694 | .remove = i915_pci_remove, | |
1695 | .driver.pm = &i915_pm_ops, | |
1696 | }; | |
1697 | ||
1da177e4 LT |
1698 | static int __init i915_init(void) |
1699 | { | |
1700 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1701 | |
1702 | /* | |
fd930478 CW |
1703 | * Enable KMS by default, unless explicitly overriden by |
1704 | * either the i915.modeset prarameter or by the | |
1705 | * vga_text_mode_force boot option. | |
79e53945 | 1706 | */ |
fd930478 CW |
1707 | driver.driver_features |= DRIVER_MODESET; |
1708 | ||
1709 | if (i915.modeset == 0) | |
1710 | driver.driver_features &= ~DRIVER_MODESET; | |
79e53945 JB |
1711 | |
1712 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 1713 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
1714 | driver.driver_features &= ~DRIVER_MODESET; |
1715 | #endif | |
1716 | ||
b30324ad | 1717 | if (!(driver.driver_features & DRIVER_MODESET)) { |
3885c6bb | 1718 | driver.get_vblank_timestamp = NULL; |
b30324ad | 1719 | /* Silently fail loading to not upset userspace. */ |
c9cd7b65 | 1720 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
b30324ad | 1721 | return 0; |
b30324ad | 1722 | } |
3885c6bb | 1723 | |
b2e7723b MR |
1724 | /* |
1725 | * FIXME: Note that we're lying to the DRM core here so that we can get access | |
1726 | * to the atomic ioctl and the atomic properties. Only plane operations on | |
1727 | * a single CRTC will actually work. | |
1728 | */ | |
c5b852f3 | 1729 | if (i915.nuclear_pageflip) |
b2e7723b MR |
1730 | driver.driver_features |= DRIVER_ATOMIC; |
1731 | ||
8410ea3b | 1732 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1733 | } |
1734 | ||
1735 | static void __exit i915_exit(void) | |
1736 | { | |
b33ecdd1 DV |
1737 | if (!(driver.driver_features & DRIVER_MODESET)) |
1738 | return; /* Never loaded a driver. */ | |
b33ecdd1 | 1739 | |
8410ea3b | 1740 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1741 | } |
1742 | ||
1743 | module_init(i915_init); | |
1744 | module_exit(i915_exit); | |
1745 | ||
0a6d1631 | 1746 | MODULE_AUTHOR("Tungsten Graphics, Inc."); |
1eab9234 | 1747 | MODULE_AUTHOR("Intel Corporation"); |
0a6d1631 | 1748 | |
b5e89ed5 | 1749 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 | 1750 | MODULE_LICENSE("GPL and additional rights"); |