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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
e5747e3a | 30 | #include <linux/acpi.h> |
0673ad47 CW |
31 | #include <linux/device.h> |
32 | #include <linux/oom.h> | |
e0cd3608 | 33 | #include <linux/module.h> |
0673ad47 CW |
34 | #include <linux/pci.h> |
35 | #include <linux/pm.h> | |
d6102977 | 36 | #include <linux/pm_runtime.h> |
0673ad47 CW |
37 | #include <linux/pnp.h> |
38 | #include <linux/slab.h> | |
39 | #include <linux/vgaarb.h> | |
704ab614 | 40 | #include <linux/vga_switcheroo.h> |
0673ad47 CW |
41 | #include <linux/vt.h> |
42 | #include <acpi/video.h> | |
43 | ||
44 | #include <drm/drmP.h> | |
760285e7 | 45 | #include <drm/drm_crtc_helper.h> |
a667fb40 | 46 | #include <drm/drm_atomic_helper.h> |
0673ad47 CW |
47 | #include <drm/i915_drm.h> |
48 | ||
49 | #include "i915_drv.h" | |
50 | #include "i915_trace.h" | |
b46a33e2 | 51 | #include "i915_pmu.h" |
a446ae2c | 52 | #include "i915_query.h" |
0673ad47 CW |
53 | #include "i915_vgpu.h" |
54 | #include "intel_drv.h" | |
5464cd65 | 55 | #include "intel_uc.h" |
79e53945 | 56 | |
112b715e KH |
57 | static struct drm_driver driver; |
58 | ||
fae919f0 | 59 | #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) |
0673ad47 CW |
60 | static unsigned int i915_load_fail_count; |
61 | ||
62 | bool __i915_inject_load_failure(const char *func, int line) | |
63 | { | |
4f044a88 | 64 | if (i915_load_fail_count >= i915_modparams.inject_load_failure) |
0673ad47 CW |
65 | return false; |
66 | ||
4f044a88 | 67 | if (++i915_load_fail_count == i915_modparams.inject_load_failure) { |
0673ad47 | 68 | DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n", |
4f044a88 | 69 | i915_modparams.inject_load_failure, func, line); |
cf68f0c3 | 70 | i915_modparams.inject_load_failure = 0; |
0673ad47 CW |
71 | return true; |
72 | } | |
73 | ||
74 | return false; | |
75 | } | |
51c18bf7 CW |
76 | |
77 | bool i915_error_injected(void) | |
78 | { | |
79 | return i915_load_fail_count && !i915_modparams.inject_load_failure; | |
80 | } | |
81 | ||
fae919f0 | 82 | #endif |
0673ad47 CW |
83 | |
84 | #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI" | |
85 | #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \ | |
86 | "providing the dmesg log by booting with drm.debug=0xf" | |
87 | ||
88 | void | |
89 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
90 | const char *fmt, ...) | |
91 | { | |
92 | static bool shown_bug_once; | |
c49d13ee | 93 | struct device *kdev = dev_priv->drm.dev; |
0673ad47 CW |
94 | bool is_error = level[1] <= KERN_ERR[1]; |
95 | bool is_debug = level[1] == KERN_DEBUG[1]; | |
96 | struct va_format vaf; | |
97 | va_list args; | |
98 | ||
99 | if (is_debug && !(drm_debug & DRM_UT_DRIVER)) | |
100 | return; | |
101 | ||
102 | va_start(args, fmt); | |
103 | ||
104 | vaf.fmt = fmt; | |
105 | vaf.va = &args; | |
106 | ||
8cff1f4a CW |
107 | if (is_error) |
108 | dev_printk(level, kdev, "%pV", &vaf); | |
109 | else | |
110 | dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV", | |
111 | __builtin_return_address(0), &vaf); | |
112 | ||
113 | va_end(args); | |
0673ad47 CW |
114 | |
115 | if (is_error && !shown_bug_once) { | |
4e8507ba CW |
116 | /* |
117 | * Ask the user to file a bug report for the error, except | |
118 | * if they may have caused the bug by fiddling with unsafe | |
119 | * module parameters. | |
120 | */ | |
121 | if (!test_taint(TAINT_USER)) | |
122 | dev_notice(kdev, "%s", FDO_BUG_MSG); | |
0673ad47 CW |
123 | shown_bug_once = true; |
124 | } | |
0673ad47 CW |
125 | } |
126 | ||
da6c10c2 JN |
127 | /* Map PCH device id to PCH type, or PCH_NONE if unknown. */ |
128 | static enum intel_pch | |
129 | intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) | |
130 | { | |
131 | switch (id) { | |
132 | case INTEL_PCH_IBX_DEVICE_ID_TYPE: | |
133 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
134 | WARN_ON(!IS_GEN5(dev_priv)); | |
135 | return PCH_IBX; | |
136 | case INTEL_PCH_CPT_DEVICE_ID_TYPE: | |
137 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
138 | WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); | |
139 | return PCH_CPT; | |
140 | case INTEL_PCH_PPT_DEVICE_ID_TYPE: | |
141 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); | |
142 | WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); | |
143 | /* PantherPoint is CPT compatible */ | |
144 | return PCH_CPT; | |
145 | case INTEL_PCH_LPT_DEVICE_ID_TYPE: | |
146 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
147 | WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); | |
148 | WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); | |
149 | return PCH_LPT; | |
150 | case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE: | |
151 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
152 | WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); | |
153 | WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); | |
154 | return PCH_LPT; | |
155 | case INTEL_PCH_WPT_DEVICE_ID_TYPE: | |
156 | DRM_DEBUG_KMS("Found WildcatPoint PCH\n"); | |
157 | WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); | |
158 | WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); | |
159 | /* WildcatPoint is LPT compatible */ | |
160 | return PCH_LPT; | |
161 | case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE: | |
162 | DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n"); | |
163 | WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); | |
164 | WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); | |
165 | /* WildcatPoint is LPT compatible */ | |
166 | return PCH_LPT; | |
167 | case INTEL_PCH_SPT_DEVICE_ID_TYPE: | |
168 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
169 | WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); | |
170 | return PCH_SPT; | |
171 | case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: | |
172 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
173 | WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); | |
174 | return PCH_SPT; | |
175 | case INTEL_PCH_KBP_DEVICE_ID_TYPE: | |
176 | DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n"); | |
177 | WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && | |
178 | !IS_COFFEELAKE(dev_priv)); | |
179 | return PCH_KBP; | |
180 | case INTEL_PCH_CNP_DEVICE_ID_TYPE: | |
181 | DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n"); | |
182 | WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); | |
183 | return PCH_CNP; | |
184 | case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: | |
185 | DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n"); | |
186 | WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); | |
187 | return PCH_CNP; | |
188 | case INTEL_PCH_ICP_DEVICE_ID_TYPE: | |
189 | DRM_DEBUG_KMS("Found Ice Lake PCH\n"); | |
190 | WARN_ON(!IS_ICELAKE(dev_priv)); | |
191 | return PCH_ICP; | |
192 | default: | |
193 | return PCH_NONE; | |
194 | } | |
195 | } | |
0673ad47 | 196 | |
435ad2c0 JN |
197 | static bool intel_is_virt_pch(unsigned short id, |
198 | unsigned short svendor, unsigned short sdevice) | |
199 | { | |
200 | return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE || | |
201 | id == INTEL_PCH_P3X_DEVICE_ID_TYPE || | |
202 | (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE && | |
203 | svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET && | |
204 | sdevice == PCI_SUBDEVICE_ID_QEMU)); | |
205 | } | |
206 | ||
40ace64b JN |
207 | static unsigned short |
208 | intel_virt_detect_pch(const struct drm_i915_private *dev_priv) | |
0673ad47 | 209 | { |
40ace64b | 210 | unsigned short id = 0; |
0673ad47 CW |
211 | |
212 | /* | |
213 | * In a virtualized passthrough environment we can be in a | |
214 | * setup where the ISA bridge is not able to be passed through. | |
215 | * In this case, a south bridge can be emulated and we have to | |
216 | * make an educated guess as to which PCH is really there. | |
217 | */ | |
218 | ||
40ace64b JN |
219 | if (IS_GEN5(dev_priv)) |
220 | id = INTEL_PCH_IBX_DEVICE_ID_TYPE; | |
221 | else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
222 | id = INTEL_PCH_CPT_DEVICE_ID_TYPE; | |
223 | else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) | |
224 | id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
225 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
226 | id = INTEL_PCH_LPT_DEVICE_ID_TYPE; | |
227 | else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
228 | id = INTEL_PCH_SPT_DEVICE_ID_TYPE; | |
229 | else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) | |
230 | id = INTEL_PCH_CNP_DEVICE_ID_TYPE; | |
f17ca501 AS |
231 | else if (IS_ICELAKE(dev_priv)) |
232 | id = INTEL_PCH_ICP_DEVICE_ID_TYPE; | |
40ace64b JN |
233 | |
234 | if (id) | |
235 | DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id); | |
236 | else | |
237 | DRM_DEBUG_KMS("Assuming no PCH\n"); | |
238 | ||
239 | return id; | |
0673ad47 CW |
240 | } |
241 | ||
da5f53bf | 242 | static void intel_detect_pch(struct drm_i915_private *dev_priv) |
0673ad47 | 243 | { |
0673ad47 CW |
244 | struct pci_dev *pch = NULL; |
245 | ||
0673ad47 CW |
246 | /* |
247 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
248 | * make graphics device passthrough work easy for VMM, that only | |
249 | * need to expose ISA bridge to let driver know the real hardware | |
250 | * underneath. This is a requirement from virtualization team. | |
251 | * | |
252 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
253 | * ISA bridge in the system. To work reliably, we should scan trhough | |
254 | * all the ISA bridge devices and check for the first match, instead | |
255 | * of only checking the first one. | |
256 | */ | |
257 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { | |
d67c0ac1 | 258 | unsigned short id; |
da6c10c2 | 259 | enum intel_pch pch_type; |
d67c0ac1 JN |
260 | |
261 | if (pch->vendor != PCI_VENDOR_ID_INTEL) | |
262 | continue; | |
263 | ||
264 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
265 | ||
da6c10c2 JN |
266 | pch_type = intel_pch_type(dev_priv, id); |
267 | if (pch_type != PCH_NONE) { | |
268 | dev_priv->pch_type = pch_type; | |
40ace64b JN |
269 | dev_priv->pch_id = id; |
270 | break; | |
435ad2c0 | 271 | } else if (intel_is_virt_pch(id, pch->subsystem_vendor, |
40ace64b JN |
272 | pch->subsystem_device)) { |
273 | id = intel_virt_detect_pch(dev_priv); | |
85b17e6e JN |
274 | pch_type = intel_pch_type(dev_priv, id); |
275 | ||
276 | /* Sanity check virtual PCH id */ | |
277 | if (WARN_ON(id && pch_type == PCH_NONE)) | |
278 | id = 0; | |
279 | ||
40ace64b JN |
280 | dev_priv->pch_type = pch_type; |
281 | dev_priv->pch_id = id; | |
282 | break; | |
0673ad47 CW |
283 | } |
284 | } | |
07ba0a82 JN |
285 | |
286 | /* | |
287 | * Use PCH_NOP (PCH but no South Display) for PCH platforms without | |
288 | * display. | |
289 | */ | |
290 | if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) { | |
291 | DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n"); | |
292 | dev_priv->pch_type = PCH_NOP; | |
293 | dev_priv->pch_id = 0; | |
294 | } | |
295 | ||
0673ad47 CW |
296 | if (!pch) |
297 | DRM_DEBUG_KMS("No PCH found.\n"); | |
298 | ||
299 | pci_dev_put(pch); | |
300 | } | |
301 | ||
6a20fe7b VS |
302 | static int i915_getparam_ioctl(struct drm_device *dev, void *data, |
303 | struct drm_file *file_priv) | |
0673ad47 | 304 | { |
fac5e23e | 305 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 306 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
307 | drm_i915_getparam_t *param = data; |
308 | int value; | |
309 | ||
310 | switch (param->param) { | |
311 | case I915_PARAM_IRQ_ACTIVE: | |
312 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
313 | case I915_PARAM_LAST_DISPATCH: | |
ef0f411f | 314 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
0673ad47 CW |
315 | /* Reject all old ums/dri params. */ |
316 | return -ENODEV; | |
317 | case I915_PARAM_CHIPSET_ID: | |
52a05c30 | 318 | value = pdev->device; |
0673ad47 CW |
319 | break; |
320 | case I915_PARAM_REVISION: | |
52a05c30 | 321 | value = pdev->revision; |
0673ad47 | 322 | break; |
0673ad47 CW |
323 | case I915_PARAM_NUM_FENCES_AVAIL: |
324 | value = dev_priv->num_fence_regs; | |
325 | break; | |
326 | case I915_PARAM_HAS_OVERLAY: | |
327 | value = dev_priv->overlay ? 1 : 0; | |
328 | break; | |
0673ad47 | 329 | case I915_PARAM_HAS_BSD: |
3b3f1650 | 330 | value = !!dev_priv->engine[VCS]; |
0673ad47 CW |
331 | break; |
332 | case I915_PARAM_HAS_BLT: | |
3b3f1650 | 333 | value = !!dev_priv->engine[BCS]; |
0673ad47 CW |
334 | break; |
335 | case I915_PARAM_HAS_VEBOX: | |
3b3f1650 | 336 | value = !!dev_priv->engine[VECS]; |
0673ad47 CW |
337 | break; |
338 | case I915_PARAM_HAS_BSD2: | |
3b3f1650 | 339 | value = !!dev_priv->engine[VCS2]; |
0673ad47 | 340 | break; |
0673ad47 | 341 | case I915_PARAM_HAS_LLC: |
16162470 | 342 | value = HAS_LLC(dev_priv); |
0673ad47 CW |
343 | break; |
344 | case I915_PARAM_HAS_WT: | |
16162470 | 345 | value = HAS_WT(dev_priv); |
0673ad47 CW |
346 | break; |
347 | case I915_PARAM_HAS_ALIASING_PPGTT: | |
16162470 | 348 | value = USES_PPGTT(dev_priv); |
0673ad47 CW |
349 | break; |
350 | case I915_PARAM_HAS_SEMAPHORES: | |
93c6e966 | 351 | value = HAS_LEGACY_SEMAPHORES(dev_priv); |
0673ad47 | 352 | break; |
0673ad47 CW |
353 | case I915_PARAM_HAS_SECURE_BATCHES: |
354 | value = capable(CAP_SYS_ADMIN); | |
355 | break; | |
0673ad47 CW |
356 | case I915_PARAM_CMD_PARSER_VERSION: |
357 | value = i915_cmd_parser_get_version(dev_priv); | |
358 | break; | |
0673ad47 | 359 | case I915_PARAM_SUBSLICE_TOTAL: |
57ec171e | 360 | value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu); |
0673ad47 CW |
361 | if (!value) |
362 | return -ENODEV; | |
363 | break; | |
364 | case I915_PARAM_EU_TOTAL: | |
43b67998 | 365 | value = INTEL_INFO(dev_priv)->sseu.eu_total; |
0673ad47 CW |
366 | if (!value) |
367 | return -ENODEV; | |
368 | break; | |
369 | case I915_PARAM_HAS_GPU_RESET: | |
4f044a88 MW |
370 | value = i915_modparams.enable_hangcheck && |
371 | intel_has_gpu_reset(dev_priv); | |
142bc7d9 MT |
372 | if (value && intel_has_reset_engine(dev_priv)) |
373 | value = 2; | |
0673ad47 CW |
374 | break; |
375 | case I915_PARAM_HAS_RESOURCE_STREAMER: | |
16162470 | 376 | value = HAS_RESOURCE_STREAMER(dev_priv); |
0673ad47 | 377 | break; |
37f501af | 378 | case I915_PARAM_HAS_POOLED_EU: |
16162470 | 379 | value = HAS_POOLED_EU(dev_priv); |
37f501af | 380 | break; |
381 | case I915_PARAM_MIN_EU_IN_POOL: | |
43b67998 | 382 | value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool; |
37f501af | 383 | break; |
5464cd65 | 384 | case I915_PARAM_HUC_STATUS: |
fa265275 MW |
385 | value = intel_huc_check_status(&dev_priv->huc); |
386 | if (value < 0) | |
387 | return value; | |
5464cd65 | 388 | break; |
4cc69075 CW |
389 | case I915_PARAM_MMAP_GTT_VERSION: |
390 | /* Though we've started our numbering from 1, and so class all | |
391 | * earlier versions as 0, in effect their value is undefined as | |
392 | * the ioctl will report EINVAL for the unknown param! | |
393 | */ | |
394 | value = i915_gem_mmap_gtt_version(); | |
395 | break; | |
0de9136d | 396 | case I915_PARAM_HAS_SCHEDULER: |
3fed1808 | 397 | value = dev_priv->caps.scheduler; |
0de9136d | 398 | break; |
beecec90 | 399 | |
16162470 DW |
400 | case I915_PARAM_MMAP_VERSION: |
401 | /* Remember to bump this if the version changes! */ | |
402 | case I915_PARAM_HAS_GEM: | |
403 | case I915_PARAM_HAS_PAGEFLIPPING: | |
404 | case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */ | |
405 | case I915_PARAM_HAS_RELAXED_FENCING: | |
406 | case I915_PARAM_HAS_COHERENT_RINGS: | |
407 | case I915_PARAM_HAS_RELAXED_DELTA: | |
408 | case I915_PARAM_HAS_GEN7_SOL_RESET: | |
409 | case I915_PARAM_HAS_WAIT_TIMEOUT: | |
410 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: | |
411 | case I915_PARAM_HAS_PINNED_BATCHES: | |
412 | case I915_PARAM_HAS_EXEC_NO_RELOC: | |
413 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: | |
414 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: | |
415 | case I915_PARAM_HAS_EXEC_SOFTPIN: | |
77ae9957 | 416 | case I915_PARAM_HAS_EXEC_ASYNC: |
fec0445c | 417 | case I915_PARAM_HAS_EXEC_FENCE: |
b0fd47ad | 418 | case I915_PARAM_HAS_EXEC_CAPTURE: |
1a71cf2f | 419 | case I915_PARAM_HAS_EXEC_BATCH_FIRST: |
cf6e7bac | 420 | case I915_PARAM_HAS_EXEC_FENCE_ARRAY: |
16162470 DW |
421 | /* For the time being all of these are always true; |
422 | * if some supported hardware does not have one of these | |
423 | * features this value needs to be provided from | |
424 | * INTEL_INFO(), a feature macro, or similar. | |
425 | */ | |
426 | value = 1; | |
427 | break; | |
d2b4b979 CW |
428 | case I915_PARAM_HAS_CONTEXT_ISOLATION: |
429 | value = intel_engines_has_context_isolation(dev_priv); | |
430 | break; | |
7fed555c RB |
431 | case I915_PARAM_SLICE_MASK: |
432 | value = INTEL_INFO(dev_priv)->sseu.slice_mask; | |
433 | if (!value) | |
434 | return -ENODEV; | |
435 | break; | |
f5320233 | 436 | case I915_PARAM_SUBSLICE_MASK: |
8cc76693 | 437 | value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0]; |
f5320233 RB |
438 | if (!value) |
439 | return -ENODEV; | |
440 | break; | |
dab91783 | 441 | case I915_PARAM_CS_TIMESTAMP_FREQUENCY: |
f577a03b | 442 | value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz; |
dab91783 | 443 | break; |
0673ad47 CW |
444 | default: |
445 | DRM_DEBUG("Unknown parameter %d\n", param->param); | |
446 | return -EINVAL; | |
447 | } | |
448 | ||
dda33009 | 449 | if (put_user(value, param->value)) |
0673ad47 | 450 | return -EFAULT; |
0673ad47 CW |
451 | |
452 | return 0; | |
453 | } | |
454 | ||
da5f53bf | 455 | static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) |
0673ad47 | 456 | { |
57b29646 SK |
457 | int domain = pci_domain_nr(dev_priv->drm.pdev->bus); |
458 | ||
459 | dev_priv->bridge_dev = | |
460 | pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); | |
0673ad47 CW |
461 | if (!dev_priv->bridge_dev) { |
462 | DRM_ERROR("bridge device not found\n"); | |
463 | return -1; | |
464 | } | |
465 | return 0; | |
466 | } | |
467 | ||
468 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
469 | static int | |
da5f53bf | 470 | intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) |
0673ad47 | 471 | { |
514e1d64 | 472 | int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
473 | u32 temp_lo, temp_hi = 0; |
474 | u64 mchbar_addr; | |
475 | int ret; | |
476 | ||
514e1d64 | 477 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
478 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
479 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
480 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
481 | ||
482 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
483 | #ifdef CONFIG_PNP | |
484 | if (mchbar_addr && | |
485 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) | |
486 | return 0; | |
487 | #endif | |
488 | ||
489 | /* Get some space for it */ | |
490 | dev_priv->mch_res.name = "i915 MCHBAR"; | |
491 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
492 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
493 | &dev_priv->mch_res, | |
494 | MCHBAR_SIZE, MCHBAR_SIZE, | |
495 | PCIBIOS_MIN_MEM, | |
496 | 0, pcibios_align_resource, | |
497 | dev_priv->bridge_dev); | |
498 | if (ret) { | |
499 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
500 | dev_priv->mch_res.start = 0; | |
501 | return ret; | |
502 | } | |
503 | ||
514e1d64 | 504 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
505 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
506 | upper_32_bits(dev_priv->mch_res.start)); | |
507 | ||
508 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
509 | lower_32_bits(dev_priv->mch_res.start)); | |
510 | return 0; | |
511 | } | |
512 | ||
513 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
514 | static void | |
da5f53bf | 515 | intel_setup_mchbar(struct drm_i915_private *dev_priv) |
0673ad47 | 516 | { |
514e1d64 | 517 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
518 | u32 temp; |
519 | bool enabled; | |
520 | ||
920a14b2 | 521 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
0673ad47 CW |
522 | return; |
523 | ||
524 | dev_priv->mchbar_need_disable = false; | |
525 | ||
50a0bc90 | 526 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
527 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); |
528 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
529 | } else { | |
530 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
531 | enabled = temp & 1; | |
532 | } | |
533 | ||
534 | /* If it's already enabled, don't have to do anything */ | |
535 | if (enabled) | |
536 | return; | |
537 | ||
da5f53bf | 538 | if (intel_alloc_mchbar_resource(dev_priv)) |
0673ad47 CW |
539 | return; |
540 | ||
541 | dev_priv->mchbar_need_disable = true; | |
542 | ||
543 | /* Space is allocated or reserved, so enable it. */ | |
50a0bc90 | 544 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
545 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, |
546 | temp | DEVEN_MCHBAR_EN); | |
547 | } else { | |
548 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
549 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
550 | } | |
551 | } | |
552 | ||
553 | static void | |
da5f53bf | 554 | intel_teardown_mchbar(struct drm_i915_private *dev_priv) |
0673ad47 | 555 | { |
514e1d64 | 556 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
557 | |
558 | if (dev_priv->mchbar_need_disable) { | |
50a0bc90 | 559 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
560 | u32 deven_val; |
561 | ||
562 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, | |
563 | &deven_val); | |
564 | deven_val &= ~DEVEN_MCHBAR_EN; | |
565 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, | |
566 | deven_val); | |
567 | } else { | |
568 | u32 mchbar_val; | |
569 | ||
570 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
571 | &mchbar_val); | |
572 | mchbar_val &= ~1; | |
573 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
574 | mchbar_val); | |
575 | } | |
576 | } | |
577 | ||
578 | if (dev_priv->mch_res.start) | |
579 | release_resource(&dev_priv->mch_res); | |
580 | } | |
581 | ||
582 | /* true = enable decode, false = disable decoder */ | |
583 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
584 | { | |
da5f53bf | 585 | struct drm_i915_private *dev_priv = cookie; |
0673ad47 | 586 | |
da5f53bf | 587 | intel_modeset_vga_set_state(dev_priv, state); |
0673ad47 CW |
588 | if (state) |
589 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
590 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
591 | else | |
592 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
593 | } | |
594 | ||
7f26cb88 TU |
595 | static int i915_resume_switcheroo(struct drm_device *dev); |
596 | static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); | |
597 | ||
0673ad47 CW |
598 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
599 | { | |
600 | struct drm_device *dev = pci_get_drvdata(pdev); | |
601 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
602 | ||
603 | if (state == VGA_SWITCHEROO_ON) { | |
604 | pr_info("switched on\n"); | |
605 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
606 | /* i915 resume handler doesn't set to D0 */ | |
52a05c30 | 607 | pci_set_power_state(pdev, PCI_D0); |
0673ad47 CW |
608 | i915_resume_switcheroo(dev); |
609 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
610 | } else { | |
611 | pr_info("switched off\n"); | |
612 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
613 | i915_suspend_switcheroo(dev, pmm); | |
614 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; | |
615 | } | |
616 | } | |
617 | ||
618 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
619 | { | |
620 | struct drm_device *dev = pci_get_drvdata(pdev); | |
621 | ||
622 | /* | |
623 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
624 | * locking inversion with the driver load path. And the access here is | |
625 | * completely racy anyway. So don't bother with locking for now. | |
626 | */ | |
627 | return dev->open_count == 0; | |
628 | } | |
629 | ||
630 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { | |
631 | .set_gpu_state = i915_switcheroo_set_state, | |
632 | .reprobe = NULL, | |
633 | .can_switch = i915_switcheroo_can_switch, | |
634 | }; | |
635 | ||
0673ad47 CW |
636 | static int i915_load_modeset_init(struct drm_device *dev) |
637 | { | |
fac5e23e | 638 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 639 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
640 | int ret; |
641 | ||
642 | if (i915_inject_load_failure()) | |
643 | return -ENODEV; | |
644 | ||
66578857 | 645 | intel_bios_init(dev_priv); |
0673ad47 CW |
646 | |
647 | /* If we have > 1 VGA cards, then we need to arbitrate access | |
648 | * to the common VGA resources. | |
649 | * | |
650 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
651 | * then we do not take part in VGA arbitration and the | |
652 | * vga_client_register() fails with -ENODEV. | |
653 | */ | |
da5f53bf | 654 | ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode); |
0673ad47 CW |
655 | if (ret && ret != -ENODEV) |
656 | goto out; | |
657 | ||
658 | intel_register_dsm_handler(); | |
659 | ||
52a05c30 | 660 | ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false); |
0673ad47 CW |
661 | if (ret) |
662 | goto cleanup_vga_client; | |
663 | ||
664 | /* must happen before intel_power_domains_init_hw() on VLV/CHV */ | |
665 | intel_update_rawclk(dev_priv); | |
666 | ||
667 | intel_power_domains_init_hw(dev_priv, false); | |
668 | ||
669 | intel_csr_ucode_init(dev_priv); | |
670 | ||
671 | ret = intel_irq_install(dev_priv); | |
672 | if (ret) | |
673 | goto cleanup_csr; | |
674 | ||
40196446 | 675 | intel_setup_gmbus(dev_priv); |
0673ad47 CW |
676 | |
677 | /* Important: The output setup functions called by modeset_init need | |
678 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b079bd17 VS |
679 | ret = intel_modeset_init(dev); |
680 | if (ret) | |
681 | goto cleanup_irq; | |
0673ad47 | 682 | |
bf9e8429 | 683 | ret = i915_gem_init(dev_priv); |
0673ad47 | 684 | if (ret) |
73bad7ca | 685 | goto cleanup_modeset; |
0673ad47 | 686 | |
d378a3ef | 687 | intel_setup_overlay(dev_priv); |
0673ad47 | 688 | |
b7f05d4a | 689 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
0673ad47 CW |
690 | return 0; |
691 | ||
692 | ret = intel_fbdev_init(dev); | |
693 | if (ret) | |
694 | goto cleanup_gem; | |
695 | ||
696 | /* Only enable hotplug handling once the fbdev is fully set up. */ | |
697 | intel_hpd_init(dev_priv); | |
698 | ||
0673ad47 CW |
699 | return 0; |
700 | ||
701 | cleanup_gem: | |
bf9e8429 | 702 | if (i915_gem_suspend(dev_priv)) |
1c777c5d | 703 | DRM_ERROR("failed to idle hardware; continuing to unload!\n"); |
fbbd37b3 | 704 | i915_gem_fini(dev_priv); |
73bad7ca CW |
705 | cleanup_modeset: |
706 | intel_modeset_cleanup(dev); | |
0673ad47 | 707 | cleanup_irq: |
0673ad47 | 708 | drm_irq_uninstall(dev); |
40196446 | 709 | intel_teardown_gmbus(dev_priv); |
0673ad47 CW |
710 | cleanup_csr: |
711 | intel_csr_ucode_fini(dev_priv); | |
712 | intel_power_domains_fini(dev_priv); | |
52a05c30 | 713 | vga_switcheroo_unregister_client(pdev); |
0673ad47 | 714 | cleanup_vga_client: |
52a05c30 | 715 | vga_client_register(pdev, NULL, NULL, NULL); |
0673ad47 CW |
716 | out: |
717 | return ret; | |
718 | } | |
719 | ||
0673ad47 CW |
720 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
721 | { | |
722 | struct apertures_struct *ap; | |
91c8a326 | 723 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
724 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
725 | bool primary; | |
726 | int ret; | |
727 | ||
728 | ap = alloc_apertures(1); | |
729 | if (!ap) | |
730 | return -ENOMEM; | |
731 | ||
73ebd503 | 732 | ap->ranges[0].base = ggtt->gmadr.start; |
0673ad47 CW |
733 | ap->ranges[0].size = ggtt->mappable_end; |
734 | ||
735 | primary = | |
736 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
737 | ||
44adece5 | 738 | ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
0673ad47 CW |
739 | |
740 | kfree(ap); | |
741 | ||
742 | return ret; | |
743 | } | |
0673ad47 CW |
744 | |
745 | #if !defined(CONFIG_VGA_CONSOLE) | |
746 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
747 | { | |
748 | return 0; | |
749 | } | |
750 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
751 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
752 | { | |
753 | return -ENODEV; | |
754 | } | |
755 | #else | |
756 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
757 | { | |
758 | int ret = 0; | |
759 | ||
760 | DRM_INFO("Replacing VGA console driver\n"); | |
761 | ||
762 | console_lock(); | |
763 | if (con_is_bound(&vga_con)) | |
764 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
765 | if (ret == 0) { | |
766 | ret = do_unregister_con_driver(&vga_con); | |
767 | ||
768 | /* Ignore "already unregistered". */ | |
769 | if (ret == -ENODEV) | |
770 | ret = 0; | |
771 | } | |
772 | console_unlock(); | |
773 | ||
774 | return ret; | |
775 | } | |
776 | #endif | |
777 | ||
0673ad47 CW |
778 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
779 | { | |
780 | /* | |
781 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
782 | * CHV x1 PHY (DP/HDMI D) | |
783 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
784 | */ | |
785 | if (IS_CHERRYVIEW(dev_priv)) { | |
786 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
787 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
788 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
789 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
790 | } | |
791 | } | |
792 | ||
793 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) | |
794 | { | |
795 | /* | |
796 | * The i915 workqueue is primarily used for batched retirement of | |
797 | * requests (and thus managing bo) once the task has been completed | |
e61e0f51 | 798 | * by the GPU. i915_retire_requests() is called directly when we |
0673ad47 CW |
799 | * need high-priority retirement, such as waiting for an explicit |
800 | * bo. | |
801 | * | |
802 | * It is also used for periodic low-priority events, such as | |
803 | * idle-timers and recording error state. | |
804 | * | |
805 | * All tasks on the workqueue are expected to acquire the dev mutex | |
806 | * so there is no point in running more than one instance of the | |
807 | * workqueue at any time. Use an ordered one. | |
808 | */ | |
809 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); | |
810 | if (dev_priv->wq == NULL) | |
811 | goto out_err; | |
812 | ||
813 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); | |
814 | if (dev_priv->hotplug.dp_wq == NULL) | |
815 | goto out_free_wq; | |
816 | ||
0673ad47 CW |
817 | return 0; |
818 | ||
0673ad47 CW |
819 | out_free_wq: |
820 | destroy_workqueue(dev_priv->wq); | |
821 | out_err: | |
822 | DRM_ERROR("Failed to allocate workqueues.\n"); | |
823 | ||
824 | return -ENOMEM; | |
825 | } | |
826 | ||
bb8f0f5a CW |
827 | static void i915_engines_cleanup(struct drm_i915_private *i915) |
828 | { | |
829 | struct intel_engine_cs *engine; | |
830 | enum intel_engine_id id; | |
831 | ||
832 | for_each_engine(engine, i915, id) | |
833 | kfree(engine); | |
834 | } | |
835 | ||
0673ad47 CW |
836 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) |
837 | { | |
0673ad47 CW |
838 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
839 | destroy_workqueue(dev_priv->wq); | |
840 | } | |
841 | ||
4fc7e845 PZ |
842 | /* |
843 | * We don't keep the workarounds for pre-production hardware, so we expect our | |
844 | * driver to fail on these machines in one way or another. A little warning on | |
845 | * dmesg may help both the user and the bug triagers. | |
6a7a6a98 CW |
846 | * |
847 | * Our policy for removing pre-production workarounds is to keep the | |
848 | * current gen workarounds as a guide to the bring-up of the next gen | |
849 | * (workarounds have a habit of persisting!). Anything older than that | |
850 | * should be removed along with the complications they introduce. | |
4fc7e845 PZ |
851 | */ |
852 | static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) | |
853 | { | |
248a124d CW |
854 | bool pre = false; |
855 | ||
856 | pre |= IS_HSW_EARLY_SDV(dev_priv); | |
857 | pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0); | |
0102ba1f | 858 | pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST); |
248a124d | 859 | |
7c5ff4a2 | 860 | if (pre) { |
4fc7e845 PZ |
861 | DRM_ERROR("This is a pre-production stepping. " |
862 | "It may not be fully functional.\n"); | |
7c5ff4a2 CW |
863 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); |
864 | } | |
4fc7e845 PZ |
865 | } |
866 | ||
0673ad47 CW |
867 | /** |
868 | * i915_driver_init_early - setup state not requiring device access | |
869 | * @dev_priv: device private | |
34e07e42 | 870 | * @ent: the matching pci_device_id |
0673ad47 CW |
871 | * |
872 | * Initialize everything that is a "SW-only" state, that is state not | |
873 | * requiring accessing the device or exposing the driver via kernel internal | |
874 | * or userspace interfaces. Example steps belonging here: lock initialization, | |
875 | * system memory allocation, setting up device specific attributes and | |
876 | * function hooks not requiring accessing the device. | |
877 | */ | |
878 | static int i915_driver_init_early(struct drm_i915_private *dev_priv, | |
879 | const struct pci_device_id *ent) | |
880 | { | |
881 | const struct intel_device_info *match_info = | |
882 | (struct intel_device_info *)ent->driver_data; | |
883 | struct intel_device_info *device_info; | |
884 | int ret = 0; | |
885 | ||
886 | if (i915_inject_load_failure()) | |
887 | return -ENODEV; | |
888 | ||
889 | /* Setup the write-once "constant" device info */ | |
94b4f3ba | 890 | device_info = mkwrite_device_info(dev_priv); |
0673ad47 CW |
891 | memcpy(device_info, match_info, sizeof(*device_info)); |
892 | device_info->device_id = dev_priv->drm.pdev->device; | |
893 | ||
ae7617f0 TU |
894 | BUILD_BUG_ON(INTEL_MAX_PLATFORMS > |
895 | sizeof(device_info->platform_mask) * BITS_PER_BYTE); | |
0673ad47 | 896 | BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE); |
0673ad47 CW |
897 | spin_lock_init(&dev_priv->irq_lock); |
898 | spin_lock_init(&dev_priv->gpu_error.lock); | |
899 | mutex_init(&dev_priv->backlight_lock); | |
900 | spin_lock_init(&dev_priv->uncore.lock); | |
317eaa95 | 901 | |
0673ad47 | 902 | mutex_init(&dev_priv->sb_lock); |
0673ad47 CW |
903 | mutex_init(&dev_priv->av_mutex); |
904 | mutex_init(&dev_priv->wm.wm_mutex); | |
905 | mutex_init(&dev_priv->pps_mutex); | |
906 | ||
0b1de5d5 CW |
907 | i915_memcpy_init_early(dev_priv); |
908 | ||
0673ad47 CW |
909 | ret = i915_workqueues_init(dev_priv); |
910 | if (ret < 0) | |
bb8f0f5a | 911 | goto err_engines; |
0673ad47 | 912 | |
a0de908d MW |
913 | ret = i915_gem_init_early(dev_priv); |
914 | if (ret < 0) | |
915 | goto err_workqueues; | |
916 | ||
0673ad47 | 917 | /* This must be called before any calls to HAS_PCH_* */ |
da5f53bf | 918 | intel_detect_pch(dev_priv); |
0673ad47 | 919 | |
a0de908d MW |
920 | intel_wopcm_init_early(&dev_priv->wopcm); |
921 | intel_uc_init_early(dev_priv); | |
192aa181 | 922 | intel_pm_setup(dev_priv); |
0673ad47 CW |
923 | intel_init_dpio(dev_priv); |
924 | intel_power_domains_init(dev_priv); | |
925 | intel_irq_init(dev_priv); | |
3ac168a7 | 926 | intel_hangcheck_init(dev_priv); |
0673ad47 CW |
927 | intel_init_display_hooks(dev_priv); |
928 | intel_init_clock_gating_hooks(dev_priv); | |
929 | intel_init_audio_hooks(dev_priv); | |
36cdd013 | 930 | intel_display_crc_init(dev_priv); |
0673ad47 | 931 | |
4fc7e845 | 932 | intel_detect_preproduction_hw(dev_priv); |
0673ad47 CW |
933 | |
934 | return 0; | |
935 | ||
a0de908d | 936 | err_workqueues: |
0673ad47 | 937 | i915_workqueues_cleanup(dev_priv); |
bb8f0f5a CW |
938 | err_engines: |
939 | i915_engines_cleanup(dev_priv); | |
0673ad47 CW |
940 | return ret; |
941 | } | |
942 | ||
943 | /** | |
944 | * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early() | |
945 | * @dev_priv: device private | |
946 | */ | |
947 | static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv) | |
948 | { | |
cefcff8f | 949 | intel_irq_fini(dev_priv); |
8c650aef | 950 | intel_uc_cleanup_early(dev_priv); |
a0de908d | 951 | i915_gem_cleanup_early(dev_priv); |
0673ad47 | 952 | i915_workqueues_cleanup(dev_priv); |
bb8f0f5a | 953 | i915_engines_cleanup(dev_priv); |
0673ad47 CW |
954 | } |
955 | ||
da5f53bf | 956 | static int i915_mmio_setup(struct drm_i915_private *dev_priv) |
0673ad47 | 957 | { |
52a05c30 | 958 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
959 | int mmio_bar; |
960 | int mmio_size; | |
961 | ||
5db94019 | 962 | mmio_bar = IS_GEN2(dev_priv) ? 1 : 0; |
0673ad47 CW |
963 | /* |
964 | * Before gen4, the registers and the GTT are behind different BARs. | |
965 | * However, from gen4 onwards, the registers and the GTT are shared | |
966 | * in the same BAR, so we want to restrict this ioremap from | |
967 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
968 | * the register BAR remains the same size for all the earlier | |
969 | * generations up to Ironlake. | |
970 | */ | |
514e1d64 | 971 | if (INTEL_GEN(dev_priv) < 5) |
0673ad47 CW |
972 | mmio_size = 512 * 1024; |
973 | else | |
974 | mmio_size = 2 * 1024 * 1024; | |
52a05c30 | 975 | dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size); |
0673ad47 CW |
976 | if (dev_priv->regs == NULL) { |
977 | DRM_ERROR("failed to map registers\n"); | |
978 | ||
979 | return -EIO; | |
980 | } | |
981 | ||
982 | /* Try to make sure MCHBAR is enabled before poking at it */ | |
da5f53bf | 983 | intel_setup_mchbar(dev_priv); |
0673ad47 CW |
984 | |
985 | return 0; | |
986 | } | |
987 | ||
da5f53bf | 988 | static void i915_mmio_cleanup(struct drm_i915_private *dev_priv) |
0673ad47 | 989 | { |
52a05c30 | 990 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 | 991 | |
da5f53bf | 992 | intel_teardown_mchbar(dev_priv); |
52a05c30 | 993 | pci_iounmap(pdev, dev_priv->regs); |
0673ad47 CW |
994 | } |
995 | ||
996 | /** | |
997 | * i915_driver_init_mmio - setup device MMIO | |
998 | * @dev_priv: device private | |
999 | * | |
1000 | * Setup minimal device state necessary for MMIO accesses later in the | |
1001 | * initialization sequence. The setup here should avoid any other device-wide | |
1002 | * side effects or exposing the driver via kernel internal or user space | |
1003 | * interfaces. | |
1004 | */ | |
1005 | static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) | |
1006 | { | |
0673ad47 CW |
1007 | int ret; |
1008 | ||
1009 | if (i915_inject_load_failure()) | |
1010 | return -ENODEV; | |
1011 | ||
da5f53bf | 1012 | if (i915_get_bridge_dev(dev_priv)) |
0673ad47 CW |
1013 | return -EIO; |
1014 | ||
da5f53bf | 1015 | ret = i915_mmio_setup(dev_priv); |
0673ad47 | 1016 | if (ret < 0) |
63ffbcda | 1017 | goto err_bridge; |
0673ad47 CW |
1018 | |
1019 | intel_uncore_init(dev_priv); | |
63ffbcda | 1020 | |
26376a7e OM |
1021 | intel_device_info_init_mmio(dev_priv); |
1022 | ||
1023 | intel_uncore_prune(dev_priv); | |
1024 | ||
1fc556fa SAK |
1025 | intel_uc_init_mmio(dev_priv); |
1026 | ||
63ffbcda JL |
1027 | ret = intel_engines_init_mmio(dev_priv); |
1028 | if (ret) | |
1029 | goto err_uncore; | |
1030 | ||
24145517 | 1031 | i915_gem_init_mmio(dev_priv); |
0673ad47 CW |
1032 | |
1033 | return 0; | |
1034 | ||
63ffbcda JL |
1035 | err_uncore: |
1036 | intel_uncore_fini(dev_priv); | |
1037 | err_bridge: | |
0673ad47 CW |
1038 | pci_dev_put(dev_priv->bridge_dev); |
1039 | ||
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | /** | |
1044 | * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio() | |
1045 | * @dev_priv: device private | |
1046 | */ | |
1047 | static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) | |
1048 | { | |
0673ad47 | 1049 | intel_uncore_fini(dev_priv); |
da5f53bf | 1050 | i915_mmio_cleanup(dev_priv); |
0673ad47 CW |
1051 | pci_dev_put(dev_priv->bridge_dev); |
1052 | } | |
1053 | ||
94b4f3ba CW |
1054 | static void intel_sanitize_options(struct drm_i915_private *dev_priv) |
1055 | { | |
94b4f3ba CW |
1056 | /* |
1057 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
1058 | * user's requested state against the hardware/driver capabilities. We | |
1059 | * do this now so that we can print out any log messages once rather | |
1060 | * than every time we check intel_enable_ppgtt(). | |
1061 | */ | |
4f044a88 MW |
1062 | i915_modparams.enable_ppgtt = |
1063 | intel_sanitize_enable_ppgtt(dev_priv, | |
1064 | i915_modparams.enable_ppgtt); | |
1065 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt); | |
39df9190 | 1066 | |
67b7f33e | 1067 | intel_gvt_sanitize_options(dev_priv); |
94b4f3ba CW |
1068 | } |
1069 | ||
0673ad47 CW |
1070 | /** |
1071 | * i915_driver_init_hw - setup state requiring device access | |
1072 | * @dev_priv: device private | |
1073 | * | |
1074 | * Setup state that requires accessing the device, but doesn't require | |
1075 | * exposing the driver via kernel internal or userspace interfaces. | |
1076 | */ | |
1077 | static int i915_driver_init_hw(struct drm_i915_private *dev_priv) | |
1078 | { | |
52a05c30 | 1079 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
1080 | int ret; |
1081 | ||
1082 | if (i915_inject_load_failure()) | |
1083 | return -ENODEV; | |
1084 | ||
6a7e51f3 | 1085 | intel_device_info_runtime_init(mkwrite_device_info(dev_priv)); |
94b4f3ba CW |
1086 | |
1087 | intel_sanitize_options(dev_priv); | |
0673ad47 | 1088 | |
9f9b2792 LL |
1089 | i915_perf_init(dev_priv); |
1090 | ||
97d6d7ab | 1091 | ret = i915_ggtt_probe_hw(dev_priv); |
0673ad47 | 1092 | if (ret) |
4a0559ed | 1093 | goto err_perf; |
0673ad47 | 1094 | |
4a0559ed CW |
1095 | /* |
1096 | * WARNING: Apparently we must kick fbdev drivers before vgacon, | |
1097 | * otherwise the vga fbdev driver falls over. | |
1098 | */ | |
0673ad47 CW |
1099 | ret = i915_kick_out_firmware_fb(dev_priv); |
1100 | if (ret) { | |
1101 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
4a0559ed | 1102 | goto err_ggtt; |
0673ad47 CW |
1103 | } |
1104 | ||
1105 | ret = i915_kick_out_vgacon(dev_priv); | |
1106 | if (ret) { | |
1107 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
4a0559ed | 1108 | goto err_ggtt; |
0673ad47 CW |
1109 | } |
1110 | ||
97d6d7ab | 1111 | ret = i915_ggtt_init_hw(dev_priv); |
0088e522 | 1112 | if (ret) |
4a0559ed | 1113 | goto err_ggtt; |
0088e522 | 1114 | |
97d6d7ab | 1115 | ret = i915_ggtt_enable_hw(dev_priv); |
0088e522 CW |
1116 | if (ret) { |
1117 | DRM_ERROR("failed to enable GGTT\n"); | |
4a0559ed | 1118 | goto err_ggtt; |
0088e522 CW |
1119 | } |
1120 | ||
52a05c30 | 1121 | pci_set_master(pdev); |
0673ad47 CW |
1122 | |
1123 | /* overlay on gen2 is broken and can't address above 1G */ | |
5db94019 | 1124 | if (IS_GEN2(dev_priv)) { |
52a05c30 | 1125 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); |
0673ad47 CW |
1126 | if (ret) { |
1127 | DRM_ERROR("failed to set DMA mask\n"); | |
1128 | ||
4a0559ed | 1129 | goto err_ggtt; |
0673ad47 CW |
1130 | } |
1131 | } | |
1132 | ||
0673ad47 CW |
1133 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1134 | * using 32bit addressing, overwriting memory if HWS is located | |
1135 | * above 4GB. | |
1136 | * | |
1137 | * The documentation also mentions an issue with undefined | |
1138 | * behaviour if any general state is accessed within a page above 4GB, | |
1139 | * which also needs to be handled carefully. | |
1140 | */ | |
c0f86832 | 1141 | if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) { |
52a05c30 | 1142 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
0673ad47 CW |
1143 | |
1144 | if (ret) { | |
1145 | DRM_ERROR("failed to set DMA mask\n"); | |
1146 | ||
4a0559ed | 1147 | goto err_ggtt; |
0673ad47 CW |
1148 | } |
1149 | } | |
1150 | ||
0673ad47 CW |
1151 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, |
1152 | PM_QOS_DEFAULT_VALUE); | |
1153 | ||
1154 | intel_uncore_sanitize(dev_priv); | |
1155 | ||
0673ad47 CW |
1156 | i915_gem_load_init_fences(dev_priv); |
1157 | ||
1158 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
1159 | * integrated graphics even though the support isn't actually there | |
1160 | * according to the published specs. It doesn't appear to function | |
1161 | * correctly in testing on 945G. | |
1162 | * This may be a side effect of MSI having been made available for PEG | |
1163 | * and the registers being closely associated. | |
1164 | * | |
1165 | * According to chipset errata, on the 965GM, MSI interrupts may | |
e38c2da0 VS |
1166 | * be lost or delayed, and was defeatured. MSI interrupts seem to |
1167 | * get lost on g4x as well, and interrupt delivery seems to stay | |
1168 | * properly dead afterwards. So we'll just disable them for all | |
1169 | * pre-gen5 chipsets. | |
8a29c778 LDM |
1170 | * |
1171 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy | |
1172 | * interrupts even when in MSI mode. This results in spurious | |
1173 | * interrupt warnings if the legacy irq no. is shared with another | |
1174 | * device. The kernel then disables that interrupt source and so | |
1175 | * prevents the other device from working properly. | |
0673ad47 | 1176 | */ |
e38c2da0 | 1177 | if (INTEL_GEN(dev_priv) >= 5) { |
52a05c30 | 1178 | if (pci_enable_msi(pdev) < 0) |
0673ad47 CW |
1179 | DRM_DEBUG_DRIVER("can't enable MSI"); |
1180 | } | |
1181 | ||
26f837e8 ZW |
1182 | ret = intel_gvt_init(dev_priv); |
1183 | if (ret) | |
7ab87ede CW |
1184 | goto err_msi; |
1185 | ||
1186 | intel_opregion_setup(dev_priv); | |
26f837e8 | 1187 | |
0673ad47 CW |
1188 | return 0; |
1189 | ||
7ab87ede CW |
1190 | err_msi: |
1191 | if (pdev->msi_enabled) | |
1192 | pci_disable_msi(pdev); | |
1193 | pm_qos_remove_request(&dev_priv->pm_qos); | |
4a0559ed | 1194 | err_ggtt: |
97d6d7ab | 1195 | i915_ggtt_cleanup_hw(dev_priv); |
4a0559ed CW |
1196 | err_perf: |
1197 | i915_perf_fini(dev_priv); | |
0673ad47 CW |
1198 | return ret; |
1199 | } | |
1200 | ||
1201 | /** | |
1202 | * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw() | |
1203 | * @dev_priv: device private | |
1204 | */ | |
1205 | static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv) | |
1206 | { | |
52a05c30 | 1207 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 | 1208 | |
9f9b2792 LL |
1209 | i915_perf_fini(dev_priv); |
1210 | ||
52a05c30 DW |
1211 | if (pdev->msi_enabled) |
1212 | pci_disable_msi(pdev); | |
0673ad47 CW |
1213 | |
1214 | pm_qos_remove_request(&dev_priv->pm_qos); | |
97d6d7ab | 1215 | i915_ggtt_cleanup_hw(dev_priv); |
0673ad47 CW |
1216 | } |
1217 | ||
1218 | /** | |
1219 | * i915_driver_register - register the driver with the rest of the system | |
1220 | * @dev_priv: device private | |
1221 | * | |
1222 | * Perform any steps necessary to make the driver available via kernel | |
1223 | * internal or userspace interfaces. | |
1224 | */ | |
1225 | static void i915_driver_register(struct drm_i915_private *dev_priv) | |
1226 | { | |
91c8a326 | 1227 | struct drm_device *dev = &dev_priv->drm; |
0673ad47 | 1228 | |
848b365d | 1229 | i915_gem_shrinker_register(dev_priv); |
b46a33e2 | 1230 | i915_pmu_register(dev_priv); |
0673ad47 CW |
1231 | |
1232 | /* | |
1233 | * Notify a valid surface after modesetting, | |
1234 | * when running inside a VM. | |
1235 | */ | |
1236 | if (intel_vgpu_active(dev_priv)) | |
1237 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); | |
1238 | ||
1239 | /* Reveal our presence to userspace */ | |
1240 | if (drm_dev_register(dev, 0) == 0) { | |
1241 | i915_debugfs_register(dev_priv); | |
694c2828 | 1242 | i915_setup_sysfs(dev_priv); |
442b8c06 RB |
1243 | |
1244 | /* Depends on sysfs having been initialized */ | |
1245 | i915_perf_register(dev_priv); | |
0673ad47 CW |
1246 | } else |
1247 | DRM_ERROR("Failed to register driver for userspace access!\n"); | |
1248 | ||
1249 | if (INTEL_INFO(dev_priv)->num_pipes) { | |
1250 | /* Must be done after probing outputs */ | |
1251 | intel_opregion_register(dev_priv); | |
1252 | acpi_video_register(); | |
1253 | } | |
1254 | ||
1255 | if (IS_GEN5(dev_priv)) | |
1256 | intel_gpu_ips_init(dev_priv); | |
1257 | ||
eef57324 | 1258 | intel_audio_init(dev_priv); |
0673ad47 CW |
1259 | |
1260 | /* | |
1261 | * Some ports require correctly set-up hpd registers for detection to | |
1262 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1263 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1264 | * irqs are fully enabled. We do it last so that the async config | |
1265 | * cannot run before the connectors are registered. | |
1266 | */ | |
1267 | intel_fbdev_initial_config_async(dev); | |
448aa911 CW |
1268 | |
1269 | /* | |
1270 | * We need to coordinate the hotplugs with the asynchronous fbdev | |
1271 | * configuration, for which we use the fbdev->async_cookie. | |
1272 | */ | |
1273 | if (INTEL_INFO(dev_priv)->num_pipes) | |
1274 | drm_kms_helper_poll_init(dev); | |
0673ad47 CW |
1275 | } |
1276 | ||
1277 | /** | |
1278 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() | |
1279 | * @dev_priv: device private | |
1280 | */ | |
1281 | static void i915_driver_unregister(struct drm_i915_private *dev_priv) | |
1282 | { | |
4f256d82 | 1283 | intel_fbdev_unregister(dev_priv); |
eef57324 | 1284 | intel_audio_deinit(dev_priv); |
0673ad47 | 1285 | |
448aa911 CW |
1286 | /* |
1287 | * After flushing the fbdev (incl. a late async config which will | |
1288 | * have delayed queuing of a hotplug event), then flush the hotplug | |
1289 | * events. | |
1290 | */ | |
1291 | drm_kms_helper_poll_fini(&dev_priv->drm); | |
1292 | ||
0673ad47 CW |
1293 | intel_gpu_ips_teardown(); |
1294 | acpi_video_unregister(); | |
1295 | intel_opregion_unregister(dev_priv); | |
1296 | ||
442b8c06 | 1297 | i915_perf_unregister(dev_priv); |
b46a33e2 | 1298 | i915_pmu_unregister(dev_priv); |
442b8c06 | 1299 | |
694c2828 | 1300 | i915_teardown_sysfs(dev_priv); |
91c8a326 | 1301 | drm_dev_unregister(&dev_priv->drm); |
0673ad47 | 1302 | |
848b365d | 1303 | i915_gem_shrinker_unregister(dev_priv); |
0673ad47 CW |
1304 | } |
1305 | ||
27d558a1 MW |
1306 | static void i915_welcome_messages(struct drm_i915_private *dev_priv) |
1307 | { | |
1308 | if (drm_debug & DRM_UT_DRIVER) { | |
1309 | struct drm_printer p = drm_debug_printer("i915 device info:"); | |
1310 | ||
1311 | intel_device_info_dump(&dev_priv->info, &p); | |
1312 | intel_device_info_dump_runtime(&dev_priv->info, &p); | |
1313 | } | |
1314 | ||
1315 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) | |
1316 | DRM_INFO("DRM_I915_DEBUG enabled\n"); | |
1317 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) | |
1318 | DRM_INFO("DRM_I915_DEBUG_GEM enabled\n"); | |
1319 | } | |
1320 | ||
0673ad47 CW |
1321 | /** |
1322 | * i915_driver_load - setup chip and create an initial config | |
d2ad3ae4 JL |
1323 | * @pdev: PCI device |
1324 | * @ent: matching PCI ID entry | |
0673ad47 CW |
1325 | * |
1326 | * The driver load routine has to do several things: | |
1327 | * - drive output discovery via intel_modeset_init() | |
1328 | * - initialize the memory manager | |
1329 | * - allocate initial config memory | |
1330 | * - setup the DRM framebuffer with the allocated memory | |
1331 | */ | |
42f5551d | 1332 | int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) |
0673ad47 | 1333 | { |
8d2b47dd ML |
1334 | const struct intel_device_info *match_info = |
1335 | (struct intel_device_info *)ent->driver_data; | |
0673ad47 CW |
1336 | struct drm_i915_private *dev_priv; |
1337 | int ret; | |
7d87a7f7 | 1338 | |
ff4c3b76 | 1339 | /* Enable nuclear pageflip on ILK+ */ |
4f044a88 | 1340 | if (!i915_modparams.nuclear_pageflip && match_info->gen < 5) |
8d2b47dd | 1341 | driver.driver_features &= ~DRIVER_ATOMIC; |
a09d0ba1 | 1342 | |
0673ad47 CW |
1343 | ret = -ENOMEM; |
1344 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
1345 | if (dev_priv) | |
1346 | ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev); | |
1347 | if (ret) { | |
87a6752c | 1348 | DRM_DEV_ERROR(&pdev->dev, "allocation failed\n"); |
cad3688f | 1349 | goto out_free; |
0673ad47 | 1350 | } |
72bbf0af | 1351 | |
0673ad47 CW |
1352 | dev_priv->drm.pdev = pdev; |
1353 | dev_priv->drm.dev_private = dev_priv; | |
719388e1 | 1354 | |
0673ad47 CW |
1355 | ret = pci_enable_device(pdev); |
1356 | if (ret) | |
cad3688f | 1357 | goto out_fini; |
1347f5b4 | 1358 | |
0673ad47 | 1359 | pci_set_drvdata(pdev, &dev_priv->drm); |
adfdf85d ID |
1360 | /* |
1361 | * Disable the system suspend direct complete optimization, which can | |
1362 | * leave the device suspended skipping the driver's suspend handlers | |
1363 | * if the device was already runtime suspended. This is needed due to | |
1364 | * the difference in our runtime and system suspend sequence and | |
1365 | * becaue the HDA driver may require us to enable the audio power | |
1366 | * domain during system suspend. | |
1367 | */ | |
c2eac4d3 | 1368 | dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); |
ef11bdb3 | 1369 | |
0673ad47 CW |
1370 | ret = i915_driver_init_early(dev_priv, ent); |
1371 | if (ret < 0) | |
1372 | goto out_pci_disable; | |
ef11bdb3 | 1373 | |
0673ad47 | 1374 | intel_runtime_pm_get(dev_priv); |
1da177e4 | 1375 | |
0673ad47 CW |
1376 | ret = i915_driver_init_mmio(dev_priv); |
1377 | if (ret < 0) | |
1378 | goto out_runtime_pm_put; | |
79e53945 | 1379 | |
0673ad47 CW |
1380 | ret = i915_driver_init_hw(dev_priv); |
1381 | if (ret < 0) | |
1382 | goto out_cleanup_mmio; | |
30c964a6 RB |
1383 | |
1384 | /* | |
0673ad47 CW |
1385 | * TODO: move the vblank init and parts of modeset init steps into one |
1386 | * of the i915_driver_init_/i915_driver_register functions according | |
1387 | * to the role/effect of the given init step. | |
30c964a6 | 1388 | */ |
0673ad47 | 1389 | if (INTEL_INFO(dev_priv)->num_pipes) { |
91c8a326 | 1390 | ret = drm_vblank_init(&dev_priv->drm, |
0673ad47 CW |
1391 | INTEL_INFO(dev_priv)->num_pipes); |
1392 | if (ret) | |
1393 | goto out_cleanup_hw; | |
30c964a6 RB |
1394 | } |
1395 | ||
91c8a326 | 1396 | ret = i915_load_modeset_init(&dev_priv->drm); |
0673ad47 | 1397 | if (ret < 0) |
baf54385 | 1398 | goto out_cleanup_hw; |
0673ad47 CW |
1399 | |
1400 | i915_driver_register(dev_priv); | |
1401 | ||
1402 | intel_runtime_pm_enable(dev_priv); | |
1403 | ||
2503a0fe | 1404 | intel_init_ipc(dev_priv); |
a3a8986c | 1405 | |
0673ad47 CW |
1406 | intel_runtime_pm_put(dev_priv); |
1407 | ||
27d558a1 MW |
1408 | i915_welcome_messages(dev_priv); |
1409 | ||
0673ad47 CW |
1410 | return 0; |
1411 | ||
0673ad47 CW |
1412 | out_cleanup_hw: |
1413 | i915_driver_cleanup_hw(dev_priv); | |
1414 | out_cleanup_mmio: | |
1415 | i915_driver_cleanup_mmio(dev_priv); | |
1416 | out_runtime_pm_put: | |
1417 | intel_runtime_pm_put(dev_priv); | |
1418 | i915_driver_cleanup_early(dev_priv); | |
1419 | out_pci_disable: | |
1420 | pci_disable_device(pdev); | |
cad3688f | 1421 | out_fini: |
0673ad47 | 1422 | i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret); |
cad3688f CW |
1423 | drm_dev_fini(&dev_priv->drm); |
1424 | out_free: | |
1425 | kfree(dev_priv); | |
159b69bc | 1426 | pci_set_drvdata(pdev, NULL); |
30c964a6 RB |
1427 | return ret; |
1428 | } | |
1429 | ||
42f5551d | 1430 | void i915_driver_unload(struct drm_device *dev) |
3bad0781 | 1431 | { |
fac5e23e | 1432 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1433 | struct pci_dev *pdev = dev_priv->drm.pdev; |
3bad0781 | 1434 | |
99c539be DV |
1435 | i915_driver_unregister(dev_priv); |
1436 | ||
bf9e8429 | 1437 | if (i915_gem_suspend(dev_priv)) |
42f5551d | 1438 | DRM_ERROR("failed to idle hardware; continuing to unload!\n"); |
ce1bb329 | 1439 | |
0673ad47 CW |
1440 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
1441 | ||
18dddadc | 1442 | drm_atomic_helper_shutdown(dev); |
a667fb40 | 1443 | |
26f837e8 ZW |
1444 | intel_gvt_cleanup(dev_priv); |
1445 | ||
0673ad47 CW |
1446 | intel_modeset_cleanup(dev); |
1447 | ||
785f076b | 1448 | intel_bios_cleanup(dev_priv); |
3bad0781 | 1449 | |
52a05c30 DW |
1450 | vga_switcheroo_unregister_client(pdev); |
1451 | vga_client_register(pdev, NULL, NULL, NULL); | |
bcdb72ac | 1452 | |
0673ad47 | 1453 | intel_csr_ucode_fini(dev_priv); |
bcdb72ac | 1454 | |
0673ad47 CW |
1455 | /* Free error state after interrupts are fully disabled. */ |
1456 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
5a4c6f1b | 1457 | i915_reset_error_state(dev_priv); |
0673ad47 | 1458 | |
fbbd37b3 | 1459 | i915_gem_fini(dev_priv); |
0673ad47 CW |
1460 | intel_fbc_cleanup_cfb(dev_priv); |
1461 | ||
1462 | intel_power_domains_fini(dev_priv); | |
1463 | ||
1464 | i915_driver_cleanup_hw(dev_priv); | |
1465 | i915_driver_cleanup_mmio(dev_priv); | |
1466 | ||
1467 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
cad3688f CW |
1468 | } |
1469 | ||
1470 | static void i915_driver_release(struct drm_device *dev) | |
1471 | { | |
1472 | struct drm_i915_private *dev_priv = to_i915(dev); | |
0673ad47 CW |
1473 | |
1474 | i915_driver_cleanup_early(dev_priv); | |
cad3688f CW |
1475 | drm_dev_fini(&dev_priv->drm); |
1476 | ||
1477 | kfree(dev_priv); | |
3bad0781 ZW |
1478 | } |
1479 | ||
0673ad47 | 1480 | static int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
2911a35b | 1481 | { |
829a0af2 | 1482 | struct drm_i915_private *i915 = to_i915(dev); |
0673ad47 | 1483 | int ret; |
2911a35b | 1484 | |
829a0af2 | 1485 | ret = i915_gem_open(i915, file); |
0673ad47 CW |
1486 | if (ret) |
1487 | return ret; | |
2911a35b | 1488 | |
0673ad47 CW |
1489 | return 0; |
1490 | } | |
71386ef9 | 1491 | |
0673ad47 CW |
1492 | /** |
1493 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1494 | * @dev: DRM device | |
1495 | * | |
1496 | * Take care of cleaning up after all DRM clients have exited. In the | |
1497 | * mode setting case, we want to restore the kernel's initial mode (just | |
1498 | * in case the last client left us in a bad state). | |
1499 | * | |
1500 | * Additionally, in the non-mode setting case, we'll tear down the GTT | |
1501 | * and DMA structures, since the kernel won't be using them, and clea | |
1502 | * up any GEM state. | |
1503 | */ | |
1504 | static void i915_driver_lastclose(struct drm_device *dev) | |
1505 | { | |
1506 | intel_fbdev_restore_mode(dev); | |
1507 | vga_switcheroo_process_delayed_switch(); | |
1508 | } | |
2911a35b | 1509 | |
7d2ec881 | 1510 | static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
0673ad47 | 1511 | { |
7d2ec881 DV |
1512 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1513 | ||
0673ad47 | 1514 | mutex_lock(&dev->struct_mutex); |
829a0af2 | 1515 | i915_gem_context_close(file); |
0673ad47 CW |
1516 | i915_gem_release(dev, file); |
1517 | mutex_unlock(&dev->struct_mutex); | |
0673ad47 CW |
1518 | |
1519 | kfree(file_priv); | |
2911a35b BW |
1520 | } |
1521 | ||
07f9cd0b ID |
1522 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
1523 | { | |
91c8a326 | 1524 | struct drm_device *dev = &dev_priv->drm; |
19c8054c | 1525 | struct intel_encoder *encoder; |
07f9cd0b ID |
1526 | |
1527 | drm_modeset_lock_all(dev); | |
19c8054c JN |
1528 | for_each_intel_encoder(dev, encoder) |
1529 | if (encoder->suspend) | |
1530 | encoder->suspend(encoder); | |
07f9cd0b ID |
1531 | drm_modeset_unlock_all(dev); |
1532 | } | |
1533 | ||
1a5df187 PZ |
1534 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1535 | bool rpm_resume); | |
507e126e | 1536 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv); |
f75a1985 | 1537 | |
bc87229f ID |
1538 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
1539 | { | |
1540 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
1541 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
1542 | return true; | |
1543 | #endif | |
1544 | return false; | |
1545 | } | |
ebc32824 | 1546 | |
73b66f87 CW |
1547 | static int i915_drm_prepare(struct drm_device *dev) |
1548 | { | |
1549 | struct drm_i915_private *i915 = to_i915(dev); | |
1550 | int err; | |
1551 | ||
1552 | /* | |
1553 | * NB intel_display_suspend() may issue new requests after we've | |
1554 | * ostensibly marked the GPU as ready-to-sleep here. We need to | |
1555 | * split out that work and pull it forward so that after point, | |
1556 | * the GPU is not woken again. | |
1557 | */ | |
1558 | err = i915_gem_suspend(i915); | |
1559 | if (err) | |
1560 | dev_err(&i915->drm.pdev->dev, | |
1561 | "GEM idle failed, suspend/resume might fail\n"); | |
1562 | ||
1563 | return err; | |
1564 | } | |
1565 | ||
5e365c39 | 1566 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 1567 | { |
fac5e23e | 1568 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1569 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e5747e3a | 1570 | pci_power_t opregion_target_state; |
61caf87c | 1571 | |
1f814dac ID |
1572 | disable_rpm_wakeref_asserts(dev_priv); |
1573 | ||
c67a470b PZ |
1574 | /* We do a lot of poking in a lot of registers, make sure they work |
1575 | * properly. */ | |
da7e29bd | 1576 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 1577 | |
5bcf719b DA |
1578 | drm_kms_helper_poll_disable(dev); |
1579 | ||
52a05c30 | 1580 | pci_save_state(pdev); |
ba8bbcf6 | 1581 | |
6b72d486 | 1582 | intel_display_suspend(dev); |
2eb5252e | 1583 | |
1a4313d1 | 1584 | intel_dp_mst_suspend(dev_priv); |
7d708ee4 | 1585 | |
d5818938 DV |
1586 | intel_runtime_pm_disable_interrupts(dev_priv); |
1587 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 1588 | |
d5818938 | 1589 | intel_suspend_encoders(dev_priv); |
0e32b39c | 1590 | |
712bf364 | 1591 | intel_suspend_hw(dev_priv); |
5669fcac | 1592 | |
275a991c | 1593 | i915_gem_suspend_gtt_mappings(dev_priv); |
828c7908 | 1594 | |
af6dc742 | 1595 | i915_save_state(dev_priv); |
9e06dd39 | 1596 | |
bc87229f | 1597 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
6f9f4b7a | 1598 | intel_opregion_notify_adapter(dev_priv, opregion_target_state); |
e5747e3a | 1599 | |
03d92e47 | 1600 | intel_opregion_unregister(dev_priv); |
8ee1c3db | 1601 | |
82e3b8c1 | 1602 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 1603 | |
62d5d69b MK |
1604 | dev_priv->suspend_count++; |
1605 | ||
f74ed08d | 1606 | intel_csr_ucode_suspend(dev_priv); |
f514c2d8 | 1607 | |
1f814dac ID |
1608 | enable_rpm_wakeref_asserts(dev_priv); |
1609 | ||
73b66f87 | 1610 | return 0; |
84b79f8d RW |
1611 | } |
1612 | ||
c49d13ee | 1613 | static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) |
c3c09c95 | 1614 | { |
c49d13ee | 1615 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1616 | struct pci_dev *pdev = dev_priv->drm.pdev; |
c3c09c95 ID |
1617 | int ret; |
1618 | ||
1f814dac ID |
1619 | disable_rpm_wakeref_asserts(dev_priv); |
1620 | ||
ec92ad00 CW |
1621 | i915_gem_suspend_late(dev_priv); |
1622 | ||
4c494a57 | 1623 | intel_display_set_init_power(dev_priv, false); |
ec92ad00 | 1624 | intel_uncore_suspend(dev_priv); |
4c494a57 | 1625 | |
bc87229f ID |
1626 | /* |
1627 | * In case of firmware assisted context save/restore don't manually | |
1628 | * deinit the power domains. This also means the CSR/DMC firmware will | |
1629 | * stay active, it will power down any HW resources as required and | |
1630 | * also enable deeper system power states that would be blocked if the | |
1631 | * firmware was inactive. | |
1632 | */ | |
300efa9e ID |
1633 | if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) || |
1634 | dev_priv->csr.dmc_payload == NULL) { | |
bc87229f | 1635 | intel_power_domains_suspend(dev_priv); |
300efa9e ID |
1636 | dev_priv->power_domains_suspended = true; |
1637 | } | |
73dfc227 | 1638 | |
507e126e | 1639 | ret = 0; |
b9fd799e | 1640 | if (IS_GEN9_LP(dev_priv)) |
507e126e | 1641 | bxt_enable_dc9(dev_priv); |
b8aea3d1 | 1642 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
507e126e ID |
1643 | hsw_enable_pc8(dev_priv); |
1644 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1645 | ret = vlv_suspend_complete(dev_priv); | |
c3c09c95 ID |
1646 | |
1647 | if (ret) { | |
1648 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
300efa9e | 1649 | if (dev_priv->power_domains_suspended) { |
bc87229f | 1650 | intel_power_domains_init_hw(dev_priv, true); |
300efa9e ID |
1651 | dev_priv->power_domains_suspended = false; |
1652 | } | |
c3c09c95 | 1653 | |
1f814dac | 1654 | goto out; |
c3c09c95 ID |
1655 | } |
1656 | ||
52a05c30 | 1657 | pci_disable_device(pdev); |
ab3be73f | 1658 | /* |
54875571 | 1659 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
1660 | * the device even though it's already in D3 and hang the machine. So |
1661 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
1662 | * power down the device properly. The issue was seen on multiple old |
1663 | * GENs with different BIOS vendors, so having an explicit blacklist | |
1664 | * is inpractical; apply the workaround on everything pre GEN6. The | |
1665 | * platforms where the issue was seen: | |
1666 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
1667 | * Fujitsu FSC S7110 | |
1668 | * Acer Aspire 1830T | |
ab3be73f | 1669 | */ |
514e1d64 | 1670 | if (!(hibernation && INTEL_GEN(dev_priv) < 6)) |
52a05c30 | 1671 | pci_set_power_state(pdev, PCI_D3hot); |
c3c09c95 | 1672 | |
1f814dac ID |
1673 | out: |
1674 | enable_rpm_wakeref_asserts(dev_priv); | |
1675 | ||
1676 | return ret; | |
c3c09c95 ID |
1677 | } |
1678 | ||
a9a251c2 | 1679 | static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
1680 | { |
1681 | int error; | |
1682 | ||
ded8b07d | 1683 | if (!dev) { |
84b79f8d RW |
1684 | DRM_ERROR("dev: %p\n", dev); |
1685 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
1686 | return -ENODEV; | |
1687 | } | |
1688 | ||
0b14cbd2 ID |
1689 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
1690 | state.event != PM_EVENT_FREEZE)) | |
1691 | return -EINVAL; | |
5bcf719b DA |
1692 | |
1693 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1694 | return 0; | |
6eecba33 | 1695 | |
5e365c39 | 1696 | error = i915_drm_suspend(dev); |
84b79f8d RW |
1697 | if (error) |
1698 | return error; | |
1699 | ||
ab3be73f | 1700 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
1701 | } |
1702 | ||
5e365c39 | 1703 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 | 1704 | { |
fac5e23e | 1705 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac840ae5 | 1706 | int ret; |
9d49c0ef | 1707 | |
1f814dac | 1708 | disable_rpm_wakeref_asserts(dev_priv); |
abc80abd | 1709 | intel_sanitize_gt_powersave(dev_priv); |
1f814dac | 1710 | |
1288786b CW |
1711 | i915_gem_sanitize(dev_priv); |
1712 | ||
97d6d7ab | 1713 | ret = i915_ggtt_enable_hw(dev_priv); |
ac840ae5 VS |
1714 | if (ret) |
1715 | DRM_ERROR("failed to re-enable GGTT\n"); | |
1716 | ||
f74ed08d ID |
1717 | intel_csr_ucode_resume(dev_priv); |
1718 | ||
af6dc742 | 1719 | i915_restore_state(dev_priv); |
8090ba8c | 1720 | intel_pps_unlock_regs_wa(dev_priv); |
6f9f4b7a | 1721 | intel_opregion_setup(dev_priv); |
61caf87c | 1722 | |
c39055b0 | 1723 | intel_init_pch_refclk(dev_priv); |
1833b134 | 1724 | |
364aece0 PA |
1725 | /* |
1726 | * Interrupts have to be enabled before any batches are run. If not the | |
1727 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
1728 | * update/restore the context. | |
1729 | * | |
908764f6 ID |
1730 | * drm_mode_config_reset() needs AUX interrupts. |
1731 | * | |
364aece0 PA |
1732 | * Modeset enabling in intel_modeset_init_hw() also needs working |
1733 | * interrupts. | |
1734 | */ | |
1735 | intel_runtime_pm_enable_interrupts(dev_priv); | |
1736 | ||
908764f6 ID |
1737 | drm_mode_config_reset(dev); |
1738 | ||
37cd3300 | 1739 | i915_gem_resume(dev_priv); |
226485e9 | 1740 | |
d5818938 | 1741 | intel_modeset_init_hw(dev); |
675f7ff3 | 1742 | intel_init_clock_gating(dev_priv); |
24576d23 | 1743 | |
d5818938 DV |
1744 | spin_lock_irq(&dev_priv->irq_lock); |
1745 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 1746 | dev_priv->display.hpd_irq_setup(dev_priv); |
d5818938 | 1747 | spin_unlock_irq(&dev_priv->irq_lock); |
0e32b39c | 1748 | |
1a4313d1 | 1749 | intel_dp_mst_resume(dev_priv); |
e7d6f7d7 | 1750 | |
a16b7658 L |
1751 | intel_display_resume(dev); |
1752 | ||
e0b70061 L |
1753 | drm_kms_helper_poll_enable(dev); |
1754 | ||
d5818938 DV |
1755 | /* |
1756 | * ... but also need to make sure that hotplug processing | |
1757 | * doesn't cause havoc. Like in the driver load code we don't | |
1758 | * bother with the tiny race here where we might loose hotplug | |
1759 | * notifications. | |
1760 | * */ | |
1761 | intel_hpd_init(dev_priv); | |
1daed3fb | 1762 | |
03d92e47 | 1763 | intel_opregion_register(dev_priv); |
44834a67 | 1764 | |
82e3b8c1 | 1765 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 1766 | |
6f9f4b7a | 1767 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
e5747e3a | 1768 | |
1f814dac ID |
1769 | enable_rpm_wakeref_asserts(dev_priv); |
1770 | ||
074c6ada | 1771 | return 0; |
84b79f8d RW |
1772 | } |
1773 | ||
5e365c39 | 1774 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 1775 | { |
fac5e23e | 1776 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1777 | struct pci_dev *pdev = dev_priv->drm.pdev; |
44410cd0 | 1778 | int ret; |
36d61e67 | 1779 | |
76c4b250 ID |
1780 | /* |
1781 | * We have a resume ordering issue with the snd-hda driver also | |
1782 | * requiring our device to be power up. Due to the lack of a | |
1783 | * parent/child relationship we currently solve this with an early | |
1784 | * resume hook. | |
1785 | * | |
1786 | * FIXME: This should be solved with a special hdmi sink device or | |
1787 | * similar so that power domains can be employed. | |
1788 | */ | |
44410cd0 ID |
1789 | |
1790 | /* | |
1791 | * Note that we need to set the power state explicitly, since we | |
1792 | * powered off the device during freeze and the PCI core won't power | |
1793 | * it back up for us during thaw. Powering off the device during | |
1794 | * freeze is not a hard requirement though, and during the | |
1795 | * suspend/resume phases the PCI core makes sure we get here with the | |
1796 | * device powered on. So in case we change our freeze logic and keep | |
1797 | * the device powered we can also remove the following set power state | |
1798 | * call. | |
1799 | */ | |
52a05c30 | 1800 | ret = pci_set_power_state(pdev, PCI_D0); |
44410cd0 ID |
1801 | if (ret) { |
1802 | DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret); | |
1803 | goto out; | |
1804 | } | |
1805 | ||
1806 | /* | |
1807 | * Note that pci_enable_device() first enables any parent bridge | |
1808 | * device and only then sets the power state for this device. The | |
1809 | * bridge enabling is a nop though, since bridge devices are resumed | |
1810 | * first. The order of enabling power and enabling the device is | |
1811 | * imposed by the PCI core as described above, so here we preserve the | |
1812 | * same order for the freeze/thaw phases. | |
1813 | * | |
1814 | * TODO: eventually we should remove pci_disable_device() / | |
1815 | * pci_enable_enable_device() from suspend/resume. Due to how they | |
1816 | * depend on the device enable refcount we can't anyway depend on them | |
1817 | * disabling/enabling the device. | |
1818 | */ | |
52a05c30 | 1819 | if (pci_enable_device(pdev)) { |
bc87229f ID |
1820 | ret = -EIO; |
1821 | goto out; | |
1822 | } | |
84b79f8d | 1823 | |
52a05c30 | 1824 | pci_set_master(pdev); |
84b79f8d | 1825 | |
1f814dac ID |
1826 | disable_rpm_wakeref_asserts(dev_priv); |
1827 | ||
666a4537 | 1828 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 | 1829 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 1830 | if (ret) |
ff0b187f DL |
1831 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
1832 | ret); | |
36d61e67 | 1833 | |
68f60946 | 1834 | intel_uncore_resume_early(dev_priv); |
efee833a | 1835 | |
b9fd799e | 1836 | if (IS_GEN9_LP(dev_priv)) { |
300efa9e | 1837 | gen9_sanitize_dc_state(dev_priv); |
507e126e | 1838 | bxt_disable_dc9(dev_priv); |
da2f41d1 | 1839 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
a9a6b73a | 1840 | hsw_disable_pc8(dev_priv); |
da2f41d1 | 1841 | } |
efee833a | 1842 | |
dc97997a | 1843 | intel_uncore_sanitize(dev_priv); |
bc87229f | 1844 | |
300efa9e | 1845 | if (dev_priv->power_domains_suspended) |
bc87229f | 1846 | intel_power_domains_init_hw(dev_priv, true); |
ac25dfed ML |
1847 | else |
1848 | intel_display_set_init_power(dev_priv, true); | |
bc87229f | 1849 | |
4fdd5b4e | 1850 | intel_engines_sanitize(dev_priv); |
24145517 | 1851 | |
6e35e8ab ID |
1852 | enable_rpm_wakeref_asserts(dev_priv); |
1853 | ||
bc87229f | 1854 | out: |
300efa9e | 1855 | dev_priv->power_domains_suspended = false; |
36d61e67 ID |
1856 | |
1857 | return ret; | |
76c4b250 ID |
1858 | } |
1859 | ||
7f26cb88 | 1860 | static int i915_resume_switcheroo(struct drm_device *dev) |
76c4b250 | 1861 | { |
50a0072f | 1862 | int ret; |
76c4b250 | 1863 | |
097dd837 ID |
1864 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1865 | return 0; | |
1866 | ||
5e365c39 | 1867 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
1868 | if (ret) |
1869 | return ret; | |
1870 | ||
5a17514e ID |
1871 | return i915_drm_resume(dev); |
1872 | } | |
1873 | ||
11ed50ec | 1874 | /** |
f3953dcb | 1875 | * i915_reset - reset chip after a hang |
535275d3 | 1876 | * @i915: #drm_i915_private to reset |
d0667e9c CW |
1877 | * @stalled_mask: mask of the stalled engines with the guilty requests |
1878 | * @reason: user error message for why we are resetting | |
11ed50ec | 1879 | * |
780f262a CW |
1880 | * Reset the chip. Useful if a hang is detected. Marks the device as wedged |
1881 | * on failure. | |
11ed50ec | 1882 | * |
221fe799 CW |
1883 | * Caller must hold the struct_mutex. |
1884 | * | |
11ed50ec BG |
1885 | * Procedure is fairly simple: |
1886 | * - reset the chip using the reset reg | |
1887 | * - re-init context state | |
1888 | * - re-init hardware status page | |
1889 | * - re-init ring buffer | |
1890 | * - re-init interrupt state | |
1891 | * - re-init display | |
1892 | */ | |
d0667e9c CW |
1893 | void i915_reset(struct drm_i915_private *i915, |
1894 | unsigned int stalled_mask, | |
1895 | const char *reason) | |
11ed50ec | 1896 | { |
535275d3 | 1897 | struct i915_gpu_error *error = &i915->gpu_error; |
0573ed4a | 1898 | int ret; |
f7096d40 | 1899 | int i; |
11ed50ec | 1900 | |
02866679 CW |
1901 | GEM_TRACE("flags=%lx\n", error->flags); |
1902 | ||
f7096d40 | 1903 | might_sleep(); |
535275d3 | 1904 | lockdep_assert_held(&i915->drm.struct_mutex); |
8c185eca | 1905 | GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags)); |
221fe799 | 1906 | |
8c185eca | 1907 | if (!test_bit(I915_RESET_HANDOFF, &error->flags)) |
780f262a | 1908 | return; |
11ed50ec | 1909 | |
d98c52cf | 1910 | /* Clear any previous failed attempts at recovery. Time to try again. */ |
535275d3 | 1911 | if (!i915_gem_unset_wedged(i915)) |
2e8f9d32 CW |
1912 | goto wakeup; |
1913 | ||
d0667e9c CW |
1914 | if (reason) |
1915 | dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason); | |
8af29b0c | 1916 | error->reset_count++; |
d98c52cf | 1917 | |
535275d3 CW |
1918 | disable_irq(i915->drm.irq); |
1919 | ret = i915_gem_reset_prepare(i915); | |
0e178aef | 1920 | if (ret) { |
107783d0 | 1921 | dev_err(i915->drm.dev, "GPU recovery failed\n"); |
107783d0 | 1922 | goto taint; |
0e178aef | 1923 | } |
9e60ab03 | 1924 | |
f7096d40 | 1925 | if (!intel_has_gpu_reset(i915)) { |
3ef98f50 CW |
1926 | if (i915_modparams.reset) |
1927 | dev_err(i915->drm.dev, "GPU reset not supported\n"); | |
1928 | else | |
1929 | DRM_DEBUG_DRIVER("GPU reset disabled\n"); | |
f7096d40 CW |
1930 | goto error; |
1931 | } | |
1932 | ||
1933 | for (i = 0; i < 3; i++) { | |
1934 | ret = intel_gpu_reset(i915, ALL_ENGINES); | |
1935 | if (ret == 0) | |
1936 | break; | |
1937 | ||
1938 | msleep(100); | |
1939 | } | |
0573ed4a | 1940 | if (ret) { |
f7096d40 | 1941 | dev_err(i915->drm.dev, "Failed to reset chip\n"); |
107783d0 | 1942 | goto taint; |
11ed50ec BG |
1943 | } |
1944 | ||
1945 | /* Ok, now get things going again... */ | |
1946 | ||
1947 | /* | |
1948 | * Everything depends on having the GTT running, so we need to start | |
0db8c961 CW |
1949 | * there. |
1950 | */ | |
1951 | ret = i915_ggtt_enable_hw(i915); | |
1952 | if (ret) { | |
8177e112 CW |
1953 | DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n", |
1954 | ret); | |
0db8c961 CW |
1955 | goto error; |
1956 | } | |
1957 | ||
d0667e9c | 1958 | i915_gem_reset(i915, stalled_mask); |
a31d73c3 CW |
1959 | intel_overlay_reset(i915); |
1960 | ||
0db8c961 | 1961 | /* |
11ed50ec BG |
1962 | * Next we need to restore the context, but we don't use those |
1963 | * yet either... | |
1964 | * | |
1965 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
1966 | * was running at the time of the reset (i.e. we weren't VT | |
1967 | * switched away). | |
1968 | */ | |
535275d3 | 1969 | ret = i915_gem_init_hw(i915); |
33d30a9c | 1970 | if (ret) { |
8177e112 CW |
1971 | DRM_ERROR("Failed to initialise HW following reset (%d)\n", |
1972 | ret); | |
d98c52cf | 1973 | goto error; |
11ed50ec BG |
1974 | } |
1975 | ||
535275d3 | 1976 | i915_queue_hangcheck(i915); |
c2a126a4 | 1977 | |
2e8f9d32 | 1978 | finish: |
535275d3 CW |
1979 | i915_gem_reset_finish(i915); |
1980 | enable_irq(i915->drm.irq); | |
8c185eca | 1981 | |
2e8f9d32 | 1982 | wakeup: |
8c185eca CW |
1983 | clear_bit(I915_RESET_HANDOFF, &error->flags); |
1984 | wake_up_bit(&error->flags, I915_RESET_HANDOFF); | |
780f262a | 1985 | return; |
d98c52cf | 1986 | |
107783d0 CW |
1987 | taint: |
1988 | /* | |
1989 | * History tells us that if we cannot reset the GPU now, we | |
1990 | * never will. This then impacts everything that is run | |
1991 | * subsequently. On failing the reset, we mark the driver | |
1992 | * as wedged, preventing further execution on the GPU. | |
1993 | * We also want to go one step further and add a taint to the | |
1994 | * kernel so that any subsequent faults can be traced back to | |
1995 | * this failure. This is important for CI, where if the | |
1996 | * GPU/driver fails we would like to reboot and restart testing | |
1997 | * rather than continue on into oblivion. For everyone else, | |
1998 | * the system should still plod along, but they have been warned! | |
1999 | */ | |
2000 | add_taint(TAINT_WARN, LOCKDEP_STILL_OK); | |
d98c52cf | 2001 | error: |
535275d3 | 2002 | i915_gem_set_wedged(i915); |
e61e0f51 | 2003 | i915_retire_requests(i915); |
2e8f9d32 | 2004 | goto finish; |
11ed50ec BG |
2005 | } |
2006 | ||
6acbea89 MT |
2007 | static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv, |
2008 | struct intel_engine_cs *engine) | |
2009 | { | |
2010 | return intel_gpu_reset(dev_priv, intel_engine_flag(engine)); | |
2011 | } | |
2012 | ||
142bc7d9 MT |
2013 | /** |
2014 | * i915_reset_engine - reset GPU engine to recover from a hang | |
2015 | * @engine: engine to reset | |
ce800754 | 2016 | * @msg: reason for GPU reset; or NULL for no dev_notice() |
142bc7d9 MT |
2017 | * |
2018 | * Reset a specific GPU engine. Useful if a hang is detected. | |
2019 | * Returns zero on successful reset or otherwise an error code. | |
a1ef70e1 MT |
2020 | * |
2021 | * Procedure is: | |
2022 | * - identifies the request that caused the hang and it is dropped | |
2023 | * - reset engine (which will force the engine to idle) | |
2024 | * - re-init/configure engine | |
142bc7d9 | 2025 | */ |
ce800754 | 2026 | int i915_reset_engine(struct intel_engine_cs *engine, const char *msg) |
142bc7d9 | 2027 | { |
a1ef70e1 | 2028 | struct i915_gpu_error *error = &engine->i915->gpu_error; |
e61e0f51 | 2029 | struct i915_request *active_request; |
a1ef70e1 MT |
2030 | int ret; |
2031 | ||
02866679 | 2032 | GEM_TRACE("%s flags=%lx\n", engine->name, error->flags); |
a1ef70e1 MT |
2033 | GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags)); |
2034 | ||
f6ba181a CW |
2035 | active_request = i915_gem_reset_prepare_engine(engine); |
2036 | if (IS_ERR_OR_NULL(active_request)) { | |
2037 | /* Either the previous reset failed, or we pardon the reset. */ | |
2038 | ret = PTR_ERR(active_request); | |
2039 | goto out; | |
2040 | } | |
2041 | ||
ce800754 | 2042 | if (msg) |
535275d3 | 2043 | dev_notice(engine->i915->drm.dev, |
ce800754 | 2044 | "Resetting %s for %s\n", engine->name, msg); |
7367612f | 2045 | error->reset_engine_count[engine->id]++; |
a1ef70e1 | 2046 | |
6acbea89 MT |
2047 | if (!engine->i915->guc.execbuf_client) |
2048 | ret = intel_gt_reset_engine(engine->i915, engine); | |
2049 | else | |
2050 | ret = intel_guc_reset_engine(&engine->i915->guc, engine); | |
0364cd19 CW |
2051 | if (ret) { |
2052 | /* If we fail here, we expect to fallback to a global reset */ | |
6acbea89 MT |
2053 | DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n", |
2054 | engine->i915->guc.execbuf_client ? "GuC " : "", | |
0364cd19 CW |
2055 | engine->name, ret); |
2056 | goto out; | |
2057 | } | |
b4f3e163 | 2058 | |
a1ef70e1 MT |
2059 | /* |
2060 | * The request that caused the hang is stuck on elsp, we know the | |
2061 | * active request and can drop it, adjust head to skip the offending | |
2062 | * request to resume executing remaining requests in the queue. | |
2063 | */ | |
bba0869b | 2064 | i915_gem_reset_engine(engine, active_request, true); |
a1ef70e1 | 2065 | |
a1ef70e1 MT |
2066 | /* |
2067 | * The engine and its registers (and workarounds in case of render) | |
2068 | * have been reset to their default values. Follow the init_ring | |
2069 | * process to program RING_MODE, HWSP and re-enable submission. | |
2070 | */ | |
2071 | ret = engine->init_hw(engine); | |
702c8f8e MT |
2072 | if (ret) |
2073 | goto out; | |
a1ef70e1 MT |
2074 | |
2075 | out: | |
0364cd19 | 2076 | i915_gem_reset_finish_engine(engine); |
a1ef70e1 | 2077 | return ret; |
142bc7d9 MT |
2078 | } |
2079 | ||
73b66f87 CW |
2080 | static int i915_pm_prepare(struct device *kdev) |
2081 | { | |
2082 | struct pci_dev *pdev = to_pci_dev(kdev); | |
2083 | struct drm_device *dev = pci_get_drvdata(pdev); | |
2084 | ||
2085 | if (!dev) { | |
2086 | dev_err(kdev, "DRM not initialized, aborting suspend.\n"); | |
2087 | return -ENODEV; | |
2088 | } | |
2089 | ||
2090 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2091 | return 0; | |
2092 | ||
2093 | return i915_drm_prepare(dev); | |
2094 | } | |
2095 | ||
c49d13ee | 2096 | static int i915_pm_suspend(struct device *kdev) |
112b715e | 2097 | { |
c49d13ee DW |
2098 | struct pci_dev *pdev = to_pci_dev(kdev); |
2099 | struct drm_device *dev = pci_get_drvdata(pdev); | |
112b715e | 2100 | |
c49d13ee DW |
2101 | if (!dev) { |
2102 | dev_err(kdev, "DRM not initialized, aborting suspend.\n"); | |
84b79f8d RW |
2103 | return -ENODEV; |
2104 | } | |
112b715e | 2105 | |
c49d13ee | 2106 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
5bcf719b DA |
2107 | return 0; |
2108 | ||
c49d13ee | 2109 | return i915_drm_suspend(dev); |
76c4b250 ID |
2110 | } |
2111 | ||
c49d13ee | 2112 | static int i915_pm_suspend_late(struct device *kdev) |
76c4b250 | 2113 | { |
c49d13ee | 2114 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
76c4b250 ID |
2115 | |
2116 | /* | |
c965d995 | 2117 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
2118 | * requiring our device to be power up. Due to the lack of a |
2119 | * parent/child relationship we currently solve this with an late | |
2120 | * suspend hook. | |
2121 | * | |
2122 | * FIXME: This should be solved with a special hdmi sink device or | |
2123 | * similar so that power domains can be employed. | |
2124 | */ | |
c49d13ee | 2125 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
76c4b250 | 2126 | return 0; |
112b715e | 2127 | |
c49d13ee | 2128 | return i915_drm_suspend_late(dev, false); |
ab3be73f ID |
2129 | } |
2130 | ||
c49d13ee | 2131 | static int i915_pm_poweroff_late(struct device *kdev) |
ab3be73f | 2132 | { |
c49d13ee | 2133 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
ab3be73f | 2134 | |
c49d13ee | 2135 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
ab3be73f ID |
2136 | return 0; |
2137 | ||
c49d13ee | 2138 | return i915_drm_suspend_late(dev, true); |
cbda12d7 ZW |
2139 | } |
2140 | ||
c49d13ee | 2141 | static int i915_pm_resume_early(struct device *kdev) |
76c4b250 | 2142 | { |
c49d13ee | 2143 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
76c4b250 | 2144 | |
c49d13ee | 2145 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
2146 | return 0; |
2147 | ||
c49d13ee | 2148 | return i915_drm_resume_early(dev); |
76c4b250 ID |
2149 | } |
2150 | ||
c49d13ee | 2151 | static int i915_pm_resume(struct device *kdev) |
cbda12d7 | 2152 | { |
c49d13ee | 2153 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
84b79f8d | 2154 | |
c49d13ee | 2155 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
2156 | return 0; |
2157 | ||
c49d13ee | 2158 | return i915_drm_resume(dev); |
cbda12d7 ZW |
2159 | } |
2160 | ||
1f19ac2a | 2161 | /* freeze: before creating the hibernation_image */ |
c49d13ee | 2162 | static int i915_pm_freeze(struct device *kdev) |
1f19ac2a | 2163 | { |
dd9f31c7 | 2164 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
6a800eab CW |
2165 | int ret; |
2166 | ||
dd9f31c7 ID |
2167 | if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) { |
2168 | ret = i915_drm_suspend(dev); | |
2169 | if (ret) | |
2170 | return ret; | |
2171 | } | |
6a800eab CW |
2172 | |
2173 | ret = i915_gem_freeze(kdev_to_i915(kdev)); | |
2174 | if (ret) | |
2175 | return ret; | |
2176 | ||
2177 | return 0; | |
1f19ac2a CW |
2178 | } |
2179 | ||
c49d13ee | 2180 | static int i915_pm_freeze_late(struct device *kdev) |
1f19ac2a | 2181 | { |
dd9f31c7 | 2182 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
461fb99c CW |
2183 | int ret; |
2184 | ||
dd9f31c7 ID |
2185 | if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) { |
2186 | ret = i915_drm_suspend_late(dev, true); | |
2187 | if (ret) | |
2188 | return ret; | |
2189 | } | |
461fb99c | 2190 | |
c49d13ee | 2191 | ret = i915_gem_freeze_late(kdev_to_i915(kdev)); |
461fb99c CW |
2192 | if (ret) |
2193 | return ret; | |
2194 | ||
2195 | return 0; | |
1f19ac2a CW |
2196 | } |
2197 | ||
2198 | /* thaw: called after creating the hibernation image, but before turning off. */ | |
c49d13ee | 2199 | static int i915_pm_thaw_early(struct device *kdev) |
1f19ac2a | 2200 | { |
c49d13ee | 2201 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
2202 | } |
2203 | ||
c49d13ee | 2204 | static int i915_pm_thaw(struct device *kdev) |
1f19ac2a | 2205 | { |
c49d13ee | 2206 | return i915_pm_resume(kdev); |
1f19ac2a CW |
2207 | } |
2208 | ||
2209 | /* restore: called after loading the hibernation image. */ | |
c49d13ee | 2210 | static int i915_pm_restore_early(struct device *kdev) |
1f19ac2a | 2211 | { |
c49d13ee | 2212 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
2213 | } |
2214 | ||
c49d13ee | 2215 | static int i915_pm_restore(struct device *kdev) |
1f19ac2a | 2216 | { |
c49d13ee | 2217 | return i915_pm_resume(kdev); |
1f19ac2a CW |
2218 | } |
2219 | ||
ddeea5b0 ID |
2220 | /* |
2221 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
2222 | * S0i[R123] transition. The list of registers needing a save/restore is | |
2223 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
2224 | * registers in the following way: | |
2225 | * - Driver: saved/restored by the driver | |
2226 | * - Punit : saved/restored by the Punit firmware | |
2227 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
2228 | * used internally by the HW in a way that doesn't depend | |
2229 | * keeping the content across a suspend/resume. | |
2230 | * - Debug : used for debugging | |
2231 | * | |
2232 | * We save/restore all registers marked with 'Driver', with the following | |
2233 | * exceptions: | |
2234 | * - Registers out of use, including also registers marked with 'Debug'. | |
2235 | * These have no effect on the driver's operation, so we don't save/restore | |
2236 | * them to reduce the overhead. | |
2237 | * - Registers that are fully setup by an initialization function called from | |
2238 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
2239 | * - Registers that provide the right functionality with their reset defaults. | |
2240 | * | |
2241 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
2242 | * ignored, we save/restore all others, practically treating the HW context as | |
2243 | * a black-box for the driver. Further investigation is needed to reduce the | |
2244 | * saved/restored registers even further, by following the same 3 criteria. | |
2245 | */ | |
2246 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
2247 | { | |
2248 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
2249 | int i; | |
2250 | ||
2251 | /* GAM 0x4000-0x4770 */ | |
2252 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
2253 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
2254 | s->arb_mode = I915_READ(ARB_MODE); | |
2255 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
2256 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
2257 | ||
2258 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 2259 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
2260 | |
2261 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 2262 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
2263 | |
2264 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
2265 | s->ecochk = I915_READ(GAM_ECOCHK); | |
2266 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
2267 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
2268 | ||
2269 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
2270 | ||
2271 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
2272 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
2273 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
2274 | s->mbctl = I915_READ(GEN6_MBCTL); | |
2275 | ||
2276 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2277 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
2278 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
2279 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
2280 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
2281 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
2282 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
2283 | ||
2284 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2285 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
2286 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
2287 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
2288 | s->ecobus = I915_READ(ECOBUS); | |
2289 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
2290 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
2291 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
2292 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
2293 | s->rcedata = I915_READ(VLV_RCEDATA); | |
2294 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
2295 | ||
2296 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2297 | s->gt_imr = I915_READ(GTIMR); | |
2298 | s->gt_ier = I915_READ(GTIER); | |
2299 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
2300 | s->pm_ier = I915_READ(GEN6_PMIER); | |
2301 | ||
2302 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2303 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
2304 | |
2305 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2306 | s->tilectl = I915_READ(TILECTL); | |
2307 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
2308 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2309 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2310 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
2311 | ||
2312 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2313 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
2314 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 2315 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
2316 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
2317 | ||
2318 | /* | |
2319 | * Not saving any of: | |
2320 | * DFT, 0x9800-0x9EC0 | |
2321 | * SARB, 0xB000-0xB1FC | |
2322 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
2323 | * PCI CFG | |
2324 | */ | |
2325 | } | |
2326 | ||
2327 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
2328 | { | |
2329 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
2330 | u32 val; | |
2331 | int i; | |
2332 | ||
2333 | /* GAM 0x4000-0x4770 */ | |
2334 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
2335 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
2336 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
2337 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
2338 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
2339 | ||
2340 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 2341 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
2342 | |
2343 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 2344 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
2345 | |
2346 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
2347 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
2348 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
2349 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
2350 | ||
2351 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
2352 | ||
2353 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
2354 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
2355 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
2356 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
2357 | ||
2358 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2359 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
2360 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
2361 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
2362 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
2363 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
2364 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
2365 | ||
2366 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2367 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
2368 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
2369 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
2370 | I915_WRITE(ECOBUS, s->ecobus); | |
2371 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
2372 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
2373 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
2374 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
2375 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
2376 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
2377 | ||
2378 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2379 | I915_WRITE(GTIMR, s->gt_imr); | |
2380 | I915_WRITE(GTIER, s->gt_ier); | |
2381 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
2382 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
2383 | ||
2384 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2385 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
2386 | |
2387 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2388 | I915_WRITE(TILECTL, s->tilectl); | |
2389 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
2390 | /* | |
2391 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
2392 | * be restored, as they are used to control the s0ix suspend/resume | |
2393 | * sequence by the caller. | |
2394 | */ | |
2395 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2396 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
2397 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
2398 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2399 | ||
2400 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2401 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
2402 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2403 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2404 | ||
2405 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
2406 | ||
2407 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2408 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
2409 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 2410 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
2411 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
2412 | } | |
2413 | ||
3dd14c04 CW |
2414 | static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv, |
2415 | u32 mask, u32 val) | |
2416 | { | |
2417 | /* The HW does not like us polling for PW_STATUS frequently, so | |
2418 | * use the sleeping loop rather than risk the busy spin within | |
2419 | * intel_wait_for_register(). | |
2420 | * | |
2421 | * Transitioning between RC6 states should be at most 2ms (see | |
2422 | * valleyview_enable_rps) so use a 3ms timeout. | |
2423 | */ | |
2424 | return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val, | |
2425 | 3); | |
2426 | } | |
2427 | ||
650ad970 ID |
2428 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
2429 | { | |
2430 | u32 val; | |
2431 | int err; | |
2432 | ||
650ad970 ID |
2433 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
2434 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2435 | if (force_on) | |
2436 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
2437 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2438 | ||
2439 | if (!force_on) | |
2440 | return 0; | |
2441 | ||
c6ddc5f3 CW |
2442 | err = intel_wait_for_register(dev_priv, |
2443 | VLV_GTLC_SURVIVABILITY_REG, | |
2444 | VLV_GFX_CLK_STATUS_BIT, | |
2445 | VLV_GFX_CLK_STATUS_BIT, | |
2446 | 20); | |
650ad970 ID |
2447 | if (err) |
2448 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
2449 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
2450 | ||
2451 | return err; | |
650ad970 ID |
2452 | } |
2453 | ||
ddeea5b0 ID |
2454 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
2455 | { | |
3dd14c04 | 2456 | u32 mask; |
ddeea5b0 | 2457 | u32 val; |
3dd14c04 | 2458 | int err; |
ddeea5b0 ID |
2459 | |
2460 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2461 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
2462 | if (allow) | |
2463 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
2464 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2465 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
2466 | ||
3dd14c04 CW |
2467 | mask = VLV_GTLC_ALLOWWAKEACK; |
2468 | val = allow ? mask : 0; | |
2469 | ||
2470 | err = vlv_wait_for_pw_status(dev_priv, mask, val); | |
ddeea5b0 ID |
2471 | if (err) |
2472 | DRM_ERROR("timeout disabling GT waking\n"); | |
b2736695 | 2473 | |
ddeea5b0 | 2474 | return err; |
ddeea5b0 ID |
2475 | } |
2476 | ||
3dd14c04 CW |
2477 | static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, |
2478 | bool wait_for_on) | |
ddeea5b0 ID |
2479 | { |
2480 | u32 mask; | |
2481 | u32 val; | |
ddeea5b0 ID |
2482 | |
2483 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
2484 | val = wait_for_on ? mask : 0; | |
ddeea5b0 ID |
2485 | |
2486 | /* | |
2487 | * RC6 transitioning can be delayed up to 2 msec (see | |
2488 | * valleyview_enable_rps), use 3 msec for safety. | |
e01569ab CW |
2489 | * |
2490 | * This can fail to turn off the rc6 if the GPU is stuck after a failed | |
2491 | * reset and we are trying to force the machine to sleep. | |
ddeea5b0 | 2492 | */ |
3dd14c04 | 2493 | if (vlv_wait_for_pw_status(dev_priv, mask, val)) |
e01569ab CW |
2494 | DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n", |
2495 | onoff(wait_for_on)); | |
ddeea5b0 ID |
2496 | } |
2497 | ||
2498 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
2499 | { | |
2500 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
2501 | return; | |
2502 | ||
6fa283b0 | 2503 | DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); |
ddeea5b0 ID |
2504 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
2505 | } | |
2506 | ||
ebc32824 | 2507 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
2508 | { |
2509 | u32 mask; | |
2510 | int err; | |
2511 | ||
2512 | /* | |
2513 | * Bspec defines the following GT well on flags as debug only, so | |
2514 | * don't treat them as hard failures. | |
2515 | */ | |
3dd14c04 | 2516 | vlv_wait_for_gt_wells(dev_priv, false); |
ddeea5b0 ID |
2517 | |
2518 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
2519 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
2520 | ||
2521 | vlv_check_no_gt_access(dev_priv); | |
2522 | ||
2523 | err = vlv_force_gfx_clock(dev_priv, true); | |
2524 | if (err) | |
2525 | goto err1; | |
2526 | ||
2527 | err = vlv_allow_gt_wake(dev_priv, false); | |
2528 | if (err) | |
2529 | goto err2; | |
98711167 | 2530 | |
2d1fe073 | 2531 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 2532 | vlv_save_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2533 | |
2534 | err = vlv_force_gfx_clock(dev_priv, false); | |
2535 | if (err) | |
2536 | goto err2; | |
2537 | ||
2538 | return 0; | |
2539 | ||
2540 | err2: | |
2541 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
2542 | vlv_allow_gt_wake(dev_priv, true); | |
2543 | err1: | |
2544 | vlv_force_gfx_clock(dev_priv, false); | |
2545 | ||
2546 | return err; | |
2547 | } | |
2548 | ||
016970be SK |
2549 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
2550 | bool rpm_resume) | |
ddeea5b0 | 2551 | { |
ddeea5b0 ID |
2552 | int err; |
2553 | int ret; | |
2554 | ||
2555 | /* | |
2556 | * If any of the steps fail just try to continue, that's the best we | |
2557 | * can do at this point. Return the first error code (which will also | |
2558 | * leave RPM permanently disabled). | |
2559 | */ | |
2560 | ret = vlv_force_gfx_clock(dev_priv, true); | |
2561 | ||
2d1fe073 | 2562 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 2563 | vlv_restore_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2564 | |
2565 | err = vlv_allow_gt_wake(dev_priv, true); | |
2566 | if (!ret) | |
2567 | ret = err; | |
2568 | ||
2569 | err = vlv_force_gfx_clock(dev_priv, false); | |
2570 | if (!ret) | |
2571 | ret = err; | |
2572 | ||
2573 | vlv_check_no_gt_access(dev_priv); | |
2574 | ||
7c108fd8 | 2575 | if (rpm_resume) |
46f16e63 | 2576 | intel_init_clock_gating(dev_priv); |
ddeea5b0 ID |
2577 | |
2578 | return ret; | |
2579 | } | |
2580 | ||
c49d13ee | 2581 | static int intel_runtime_suspend(struct device *kdev) |
8a187455 | 2582 | { |
c49d13ee | 2583 | struct pci_dev *pdev = to_pci_dev(kdev); |
8a187455 | 2584 | struct drm_device *dev = pci_get_drvdata(pdev); |
fac5e23e | 2585 | struct drm_i915_private *dev_priv = to_i915(dev); |
0ab9cfeb | 2586 | int ret; |
8a187455 | 2587 | |
fb6db0f5 | 2588 | if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv)))) |
c6df39b5 ID |
2589 | return -ENODEV; |
2590 | ||
6772ffe0 | 2591 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 ID |
2592 | return -ENODEV; |
2593 | ||
8a187455 PZ |
2594 | DRM_DEBUG_KMS("Suspending device\n"); |
2595 | ||
1f814dac ID |
2596 | disable_rpm_wakeref_asserts(dev_priv); |
2597 | ||
d6102977 ID |
2598 | /* |
2599 | * We are safe here against re-faults, since the fault handler takes | |
2600 | * an RPM reference. | |
2601 | */ | |
7c108fd8 | 2602 | i915_gem_runtime_suspend(dev_priv); |
d6102977 | 2603 | |
7cfca4af | 2604 | intel_uc_suspend(dev_priv); |
a1c41994 | 2605 | |
2eb5252e | 2606 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 2607 | |
01c799c9 HG |
2608 | intel_uncore_suspend(dev_priv); |
2609 | ||
507e126e | 2610 | ret = 0; |
b9fd799e | 2611 | if (IS_GEN9_LP(dev_priv)) { |
507e126e ID |
2612 | bxt_display_core_uninit(dev_priv); |
2613 | bxt_enable_dc9(dev_priv); | |
2614 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { | |
2615 | hsw_enable_pc8(dev_priv); | |
2616 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
2617 | ret = vlv_suspend_complete(dev_priv); | |
2618 | } | |
2619 | ||
0ab9cfeb ID |
2620 | if (ret) { |
2621 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
01c799c9 HG |
2622 | intel_uncore_runtime_resume(dev_priv); |
2623 | ||
b963291c | 2624 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb | 2625 | |
7cfca4af | 2626 | intel_uc_resume(dev_priv); |
1ed21cb4 SAK |
2627 | |
2628 | i915_gem_init_swizzling(dev_priv); | |
2629 | i915_gem_restore_fences(dev_priv); | |
2630 | ||
1f814dac ID |
2631 | enable_rpm_wakeref_asserts(dev_priv); |
2632 | ||
0ab9cfeb ID |
2633 | return ret; |
2634 | } | |
a8a8bd54 | 2635 | |
1f814dac | 2636 | enable_rpm_wakeref_asserts(dev_priv); |
ad1443f0 | 2637 | WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count)); |
55ec45c2 | 2638 | |
bc3b9346 | 2639 | if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) |
55ec45c2 MK |
2640 | DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
2641 | ||
ad1443f0 | 2642 | dev_priv->runtime_pm.suspended = true; |
1fb2362b KCA |
2643 | |
2644 | /* | |
c8a0bd42 PZ |
2645 | * FIXME: We really should find a document that references the arguments |
2646 | * used below! | |
1fb2362b | 2647 | */ |
6f9f4b7a | 2648 | if (IS_BROADWELL(dev_priv)) { |
d37ae19a PZ |
2649 | /* |
2650 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
2651 | * being detected, and the call we do at intel_runtime_resume() | |
2652 | * won't be able to restore them. Since PCI_D3hot matches the | |
2653 | * actual specification and appears to be working, use it. | |
2654 | */ | |
6f9f4b7a | 2655 | intel_opregion_notify_adapter(dev_priv, PCI_D3hot); |
d37ae19a | 2656 | } else { |
c8a0bd42 PZ |
2657 | /* |
2658 | * current versions of firmware which depend on this opregion | |
2659 | * notification have repurposed the D1 definition to mean | |
2660 | * "runtime suspended" vs. what you would normally expect (D3) | |
2661 | * to distinguish it from notifications that might be sent via | |
2662 | * the suspend path. | |
2663 | */ | |
6f9f4b7a | 2664 | intel_opregion_notify_adapter(dev_priv, PCI_D1); |
c8a0bd42 | 2665 | } |
8a187455 | 2666 | |
59bad947 | 2667 | assert_forcewakes_inactive(dev_priv); |
dc9fb09c | 2668 | |
21d6e0bd | 2669 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
19625e85 L |
2670 | intel_hpd_poll_init(dev_priv); |
2671 | ||
a8a8bd54 | 2672 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
2673 | return 0; |
2674 | } | |
2675 | ||
c49d13ee | 2676 | static int intel_runtime_resume(struct device *kdev) |
8a187455 | 2677 | { |
c49d13ee | 2678 | struct pci_dev *pdev = to_pci_dev(kdev); |
8a187455 | 2679 | struct drm_device *dev = pci_get_drvdata(pdev); |
fac5e23e | 2680 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a5df187 | 2681 | int ret = 0; |
8a187455 | 2682 | |
6772ffe0 | 2683 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 | 2684 | return -ENODEV; |
8a187455 PZ |
2685 | |
2686 | DRM_DEBUG_KMS("Resuming device\n"); | |
2687 | ||
ad1443f0 | 2688 | WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count)); |
1f814dac ID |
2689 | disable_rpm_wakeref_asserts(dev_priv); |
2690 | ||
6f9f4b7a | 2691 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
ad1443f0 | 2692 | dev_priv->runtime_pm.suspended = false; |
55ec45c2 MK |
2693 | if (intel_uncore_unclaimed_mmio(dev_priv)) |
2694 | DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); | |
8a187455 | 2695 | |
b9fd799e | 2696 | if (IS_GEN9_LP(dev_priv)) { |
507e126e ID |
2697 | bxt_disable_dc9(dev_priv); |
2698 | bxt_display_core_init(dev_priv, true); | |
f62c79b3 ID |
2699 | if (dev_priv->csr.dmc_payload && |
2700 | (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) | |
2701 | gen9_enable_dc5(dev_priv); | |
507e126e | 2702 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1a5df187 | 2703 | hsw_disable_pc8(dev_priv); |
507e126e | 2704 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
1a5df187 | 2705 | ret = vlv_resume_prepare(dev_priv, true); |
507e126e | 2706 | } |
1a5df187 | 2707 | |
bedf4d79 HG |
2708 | intel_uncore_runtime_resume(dev_priv); |
2709 | ||
1ed21cb4 SAK |
2710 | intel_runtime_pm_enable_interrupts(dev_priv); |
2711 | ||
7cfca4af | 2712 | intel_uc_resume(dev_priv); |
1ed21cb4 | 2713 | |
0ab9cfeb ID |
2714 | /* |
2715 | * No point of rolling back things in case of an error, as the best | |
2716 | * we can do is to hope that things will still work (and disable RPM). | |
2717 | */ | |
c6be607a | 2718 | i915_gem_init_swizzling(dev_priv); |
83bf6d55 | 2719 | i915_gem_restore_fences(dev_priv); |
92b806d3 | 2720 | |
08d8a232 VS |
2721 | /* |
2722 | * On VLV/CHV display interrupts are part of the display | |
2723 | * power well, so hpd is reinitialized from there. For | |
2724 | * everyone else do it here. | |
2725 | */ | |
666a4537 | 2726 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
08d8a232 VS |
2727 | intel_hpd_init(dev_priv); |
2728 | ||
2503a0fe KM |
2729 | intel_enable_ipc(dev_priv); |
2730 | ||
1f814dac ID |
2731 | enable_rpm_wakeref_asserts(dev_priv); |
2732 | ||
0ab9cfeb ID |
2733 | if (ret) |
2734 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
2735 | else | |
2736 | DRM_DEBUG_KMS("Device resumed\n"); | |
2737 | ||
2738 | return ret; | |
8a187455 PZ |
2739 | } |
2740 | ||
42f5551d | 2741 | const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
2742 | /* |
2743 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
2744 | * PMSG_RESUME] | |
2745 | */ | |
73b66f87 | 2746 | .prepare = i915_pm_prepare, |
0206e353 | 2747 | .suspend = i915_pm_suspend, |
76c4b250 ID |
2748 | .suspend_late = i915_pm_suspend_late, |
2749 | .resume_early = i915_pm_resume_early, | |
0206e353 | 2750 | .resume = i915_pm_resume, |
5545dbbf ID |
2751 | |
2752 | /* | |
2753 | * S4 event handlers | |
2754 | * @freeze, @freeze_late : called (1) before creating the | |
2755 | * hibernation image [PMSG_FREEZE] and | |
2756 | * (2) after rebooting, before restoring | |
2757 | * the image [PMSG_QUIESCE] | |
2758 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
2759 | * image, before writing it [PMSG_THAW] | |
2760 | * and (2) after failing to create or | |
2761 | * restore the image [PMSG_RECOVER] | |
2762 | * @poweroff, @poweroff_late: called after writing the hibernation | |
2763 | * image, before rebooting [PMSG_HIBERNATE] | |
2764 | * @restore, @restore_early : called after rebooting and restoring the | |
2765 | * hibernation image [PMSG_RESTORE] | |
2766 | */ | |
1f19ac2a CW |
2767 | .freeze = i915_pm_freeze, |
2768 | .freeze_late = i915_pm_freeze_late, | |
2769 | .thaw_early = i915_pm_thaw_early, | |
2770 | .thaw = i915_pm_thaw, | |
36d61e67 | 2771 | .poweroff = i915_pm_suspend, |
ab3be73f | 2772 | .poweroff_late = i915_pm_poweroff_late, |
1f19ac2a CW |
2773 | .restore_early = i915_pm_restore_early, |
2774 | .restore = i915_pm_restore, | |
5545dbbf ID |
2775 | |
2776 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
2777 | .runtime_suspend = intel_runtime_suspend, |
2778 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
2779 | }; |
2780 | ||
78b68556 | 2781 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 2782 | .fault = i915_gem_fault, |
ab00b3e5 JB |
2783 | .open = drm_gem_vm_open, |
2784 | .close = drm_gem_vm_close, | |
de151cf6 JB |
2785 | }; |
2786 | ||
e08e96de AV |
2787 | static const struct file_operations i915_driver_fops = { |
2788 | .owner = THIS_MODULE, | |
2789 | .open = drm_open, | |
2790 | .release = drm_release, | |
2791 | .unlocked_ioctl = drm_ioctl, | |
2792 | .mmap = drm_gem_mmap, | |
2793 | .poll = drm_poll, | |
e08e96de | 2794 | .read = drm_read, |
e08e96de | 2795 | .compat_ioctl = i915_compat_ioctl, |
e08e96de AV |
2796 | .llseek = noop_llseek, |
2797 | }; | |
2798 | ||
0673ad47 CW |
2799 | static int |
2800 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
2801 | struct drm_file *file) | |
2802 | { | |
2803 | return -ENODEV; | |
2804 | } | |
2805 | ||
2806 | static const struct drm_ioctl_desc i915_ioctls[] = { | |
2807 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2808 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
2809 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
2810 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
2811 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
2812 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
6a20fe7b | 2813 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
0673ad47 CW |
2814 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2815 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), | |
2816 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
2817 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2818 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), | |
2819 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2820 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2821 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), | |
2822 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
2823 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2824 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
6a20fe7b VS |
2825 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH), |
2826 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
0673ad47 CW |
2827 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), |
2828 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
2829 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
2830 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), | |
2831 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), | |
2832 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
2833 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2834 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2835 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), | |
2836 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), | |
2837 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), | |
2838 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), | |
2839 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW), | |
2840 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), | |
2841 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), | |
111dbcab CW |
2842 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), |
2843 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), | |
0673ad47 | 2844 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), |
6a20fe7b | 2845 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), |
0673ad47 | 2846 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), |
0cd54b03 DV |
2847 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), |
2848 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), | |
2849 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), | |
2850 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), | |
0673ad47 CW |
2851 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
2852 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), | |
2853 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), | |
2854 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), | |
2855 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), | |
2856 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), | |
2857 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), | |
2858 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), | |
eec688e1 | 2859 | DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), |
f89823c2 LL |
2860 | DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
2861 | DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
a446ae2c | 2862 | DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
0673ad47 CW |
2863 | }; |
2864 | ||
1da177e4 | 2865 | static struct drm_driver driver = { |
0c54781b MW |
2866 | /* Don't use MTRRs here; the Xserver or userspace app should |
2867 | * deal with them for Intel hardware. | |
792d2b9a | 2868 | */ |
673a394b | 2869 | .driver_features = |
10ba5012 | 2870 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
cf6e7bac | 2871 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ, |
cad3688f | 2872 | .release = i915_driver_release, |
673a394b | 2873 | .open = i915_driver_open, |
22eae947 | 2874 | .lastclose = i915_driver_lastclose, |
673a394b | 2875 | .postclose = i915_driver_postclose, |
d8e29209 | 2876 | |
b1f788c6 | 2877 | .gem_close_object = i915_gem_close_object, |
f0cd5182 | 2878 | .gem_free_object_unlocked = i915_gem_free_object, |
de151cf6 | 2879 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
2880 | |
2881 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
2882 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
2883 | .gem_prime_export = i915_gem_prime_export, | |
2884 | .gem_prime_import = i915_gem_prime_import, | |
2885 | ||
ff72145b | 2886 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 2887 | .dumb_map_offset = i915_gem_mmap_gtt, |
1da177e4 | 2888 | .ioctls = i915_ioctls, |
0673ad47 | 2889 | .num_ioctls = ARRAY_SIZE(i915_ioctls), |
e08e96de | 2890 | .fops = &i915_driver_fops, |
22eae947 DA |
2891 | .name = DRIVER_NAME, |
2892 | .desc = DRIVER_DESC, | |
2893 | .date = DRIVER_DATE, | |
2894 | .major = DRIVER_MAJOR, | |
2895 | .minor = DRIVER_MINOR, | |
2896 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 | 2897 | }; |
66d9cb5d CW |
2898 | |
2899 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
2900 | #include "selftests/mock_drm.c" | |
2901 | #endif |