]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/i915_drv.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
0673ad47
CW		 46#include <drm/i915_drm.h>
47
48#include "i915_drv.h"
49#include "i915_trace.h"
50#include "i915_vgpu.h"
51#include "intel_drv.h"
79e53945 52
112b715e
KH		 53static struct drm_driver driver;
54
0673ad47
CW		 55static unsigned int i915_load_fail_count;
56
57bool __i915_inject_load_failure(const char *func, int line)
58{
59 if (i915_load_fail_count >= i915.inject_load_failure)
60 return false;
61
62 if (++i915_load_fail_count == i915.inject_load_failure) {
63 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
64 i915.inject_load_failure, func, line);
65 return true;
66 }
67
68 return false;
69}
70
71#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
72#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
73 "providing the dmesg log by booting with drm.debug=0xf"
74
75void
76__i915_printk(struct drm_i915_private *dev_priv, const char *level,
77 const char *fmt, ...)
78{
79 static bool shown_bug_once;
fb939420 80 struct device *dev = dev_priv->drm.dev;
0673ad47
CW		 81 bool is_error = level[1] <= KERN_ERR[1];
82 bool is_debug = level[1] == KERN_DEBUG[1];
83 struct va_format vaf;
84 va_list args;
85
86 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
87 return;
88
89 va_start(args, fmt);
90
91 vaf.fmt = fmt;
92 vaf.va = &args;
93
94 dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
95 __builtin_return_address(0), &vaf);
96
97 if (is_error && !shown_bug_once) {
98 dev_notice(dev, "%s", FDO_BUG_MSG);
99 shown_bug_once = true;
100 }
101
102 va_end(args);
103}
104
105static bool i915_error_injected(struct drm_i915_private *dev_priv)
106{
107 return i915.inject_load_failure &&
108 i915_load_fail_count == i915.inject_load_failure;
109}
110
111#define i915_load_error(dev_priv, fmt, ...) \
112 __i915_printk(dev_priv, \
113 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
114 fmt, ##__VA_ARGS__)
115
116
117static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
118{
119 enum intel_pch ret = PCH_NOP;
120
121 /*
122 * In a virtualized passthrough environment we can be in a
123 * setup where the ISA bridge is not able to be passed through.
124 * In this case, a south bridge can be emulated and we have to
125 * make an educated guess as to which PCH is really there.
126 */
127
128 if (IS_GEN5(dev)) {
129 ret = PCH_IBX;
130 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
131 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
132 ret = PCH_CPT;
133 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
134 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
135 ret = PCH_LPT;
136 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
137 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
138 ret = PCH_SPT;
139 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
140 }
141
142 return ret;
143}
144
145static void intel_detect_pch(struct drm_device *dev)
146{
fac5e23e 147 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 148 struct pci_dev *pch = NULL;
149
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
152 */
153 if (INTEL_INFO(dev)->num_pipes == 0) {
154 dev_priv->pch_type = PCH_NOP;
155 return;
156 }
157
158 /*
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
163 *
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
168 */
169 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
170 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
171 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
172 dev_priv->pch_id = id;
173
174 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
175 dev_priv->pch_type = PCH_IBX;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
177 WARN_ON(!IS_GEN5(dev));
178 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
179 dev_priv->pch_type = PCH_CPT;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
181 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
182 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
183 /* PantherPoint is CPT compatible */
184 dev_priv->pch_type = PCH_CPT;
185 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
186 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
187 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
188 dev_priv->pch_type = PCH_LPT;
189 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
190 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
191 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
192 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
193 dev_priv->pch_type = PCH_LPT;
194 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
195 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
196 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
197 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
198 dev_priv->pch_type = PCH_SPT;
199 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
200 WARN_ON(!IS_SKYLAKE(dev) &&
201 !IS_KABYLAKE(dev));
202 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
203 dev_priv->pch_type = PCH_SPT;
204 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
205 WARN_ON(!IS_SKYLAKE(dev) &&
206 !IS_KABYLAKE(dev));
207 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
208 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
209 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
210 pch->subsystem_vendor ==
211 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
212 pch->subsystem_device ==
213 PCI_SUBDEVICE_ID_QEMU)) {
214 dev_priv->pch_type = intel_virt_detect_pch(dev);
215 } else
216 continue;
217
218 break;
219 }
220 }
221 if (!pch)
222 DRM_DEBUG_KMS("No PCH found.\n");
223
224 pci_dev_put(pch);
225}
226
227bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
228{
229 if (INTEL_GEN(dev_priv) < 6)
230 return false;
231
232 if (i915.semaphores >= 0)
233 return i915.semaphores;
234
235 /* TODO: make semaphores and Execlists play nicely together */
236 if (i915.enable_execlists)
237 return false;
238
239#ifdef CONFIG_INTEL_IOMMU
240 /* Enable semaphores on SNB when IO remapping is off */
241 if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped)
242 return false;
243#endif
244
245 return true;
246}
247
248static int i915_getparam(struct drm_device *dev, void *data,
249 struct drm_file *file_priv)
250{
fac5e23e 251 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 252 drm_i915_getparam_t *param = data;
253 int value;
254
255 switch (param->param) {
256 case I915_PARAM_IRQ_ACTIVE:
257 case I915_PARAM_ALLOW_BATCHBUFFER:
258 case I915_PARAM_LAST_DISPATCH:
259 /* Reject all old ums/dri params. */
260 return -ENODEV;
261 case I915_PARAM_CHIPSET_ID:
262 value = dev->pdev->device;
263 break;
264 case I915_PARAM_REVISION:
265 value = dev->pdev->revision;
266 break;
267 case I915_PARAM_HAS_GEM:
268 value = 1;
269 break;
270 case I915_PARAM_NUM_FENCES_AVAIL:
271 value = dev_priv->num_fence_regs;
272 break;
273 case I915_PARAM_HAS_OVERLAY:
274 value = dev_priv->overlay ? 1 : 0;
275 break;
276 case I915_PARAM_HAS_PAGEFLIPPING:
277 value = 1;
278 break;
279 case I915_PARAM_HAS_EXECBUF2:
280 /* depends on GEM */
281 value = 1;
282 break;
283 case I915_PARAM_HAS_BSD:
284 value = intel_engine_initialized(&dev_priv->engine[VCS]);
285 break;
286 case I915_PARAM_HAS_BLT:
287 value = intel_engine_initialized(&dev_priv->engine[BCS]);
288 break;
289 case I915_PARAM_HAS_VEBOX:
290 value = intel_engine_initialized(&dev_priv->engine[VECS]);
291 break;
292 case I915_PARAM_HAS_BSD2:
293 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
294 break;
295 case I915_PARAM_HAS_RELAXED_FENCING:
296 value = 1;
297 break;
298 case I915_PARAM_HAS_COHERENT_RINGS:
299 value = 1;
300 break;
301 case I915_PARAM_HAS_EXEC_CONSTANTS:
302 value = INTEL_INFO(dev)->gen >= 4;
303 break;
304 case I915_PARAM_HAS_RELAXED_DELTA:
305 value = 1;
306 break;
307 case I915_PARAM_HAS_GEN7_SOL_RESET:
308 value = 1;
309 break;
310 case I915_PARAM_HAS_LLC:
311 value = HAS_LLC(dev);
312 break;
313 case I915_PARAM_HAS_WT:
314 value = HAS_WT(dev);
315 break;
316 case I915_PARAM_HAS_ALIASING_PPGTT:
317 value = USES_PPGTT(dev);
318 break;
319 case I915_PARAM_HAS_WAIT_TIMEOUT:
320 value = 1;
321 break;
322 case I915_PARAM_HAS_SEMAPHORES:
323 value = i915_semaphore_is_enabled(dev_priv);
324 break;
325 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
326 value = 1;
327 break;
328 case I915_PARAM_HAS_SECURE_BATCHES:
329 value = capable(CAP_SYS_ADMIN);
330 break;
331 case I915_PARAM_HAS_PINNED_BATCHES:
332 value = 1;
333 break;
334 case I915_PARAM_HAS_EXEC_NO_RELOC:
335 value = 1;
336 break;
337 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
338 value = 1;
339 break;
340 case I915_PARAM_CMD_PARSER_VERSION:
341 value = i915_cmd_parser_get_version(dev_priv);
342 break;
343 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
344 value = 1;
345 break;
346 case I915_PARAM_MMAP_VERSION:
347 value = 1;
348 break;
349 case I915_PARAM_SUBSLICE_TOTAL:
350 value = INTEL_INFO(dev)->subslice_total;
351 if (!value)
352 return -ENODEV;
353 break;
354 case I915_PARAM_EU_TOTAL:
355 value = INTEL_INFO(dev)->eu_total;
356 if (!value)
357 return -ENODEV;
358 break;
359 case I915_PARAM_HAS_GPU_RESET:
360 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
361 break;
362 case I915_PARAM_HAS_RESOURCE_STREAMER:
363 value = HAS_RESOURCE_STREAMER(dev);
364 break;
365 case I915_PARAM_HAS_EXEC_SOFTPIN:
366 value = 1;
367 break;
37f501af 368 case I915_PARAM_HAS_POOLED_EU:
369 value = HAS_POOLED_EU(dev);
370 break;
371 case I915_PARAM_MIN_EU_IN_POOL:
372 value = INTEL_INFO(dev)->min_eu_in_pool;
373 break;
0673ad47
CW		 374 default:
375 DRM_DEBUG("Unknown parameter %d\n", param->param);
376 return -EINVAL;
377 }
378
dda33009 379 if (put_user(value, param->value))
0673ad47 380 return -EFAULT;
0673ad47
CW		 381
382 return 0;
383}
384
385static int i915_get_bridge_dev(struct drm_device *dev)
386{
fac5e23e 387 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 388
389 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
390 if (!dev_priv->bridge_dev) {
391 DRM_ERROR("bridge device not found\n");
392 return -1;
393 }
394 return 0;
395}
396
397/* Allocate space for the MCH regs if needed, return nonzero on error */
398static int
399intel_alloc_mchbar_resource(struct drm_device *dev)
400{
fac5e23e 401 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 402 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
403 u32 temp_lo, temp_hi = 0;
404 u64 mchbar_addr;
405 int ret;
406
407 if (INTEL_INFO(dev)->gen >= 4)
408 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
409 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
410 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
411
412 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
413#ifdef CONFIG_PNP
414 if (mchbar_addr &&
415 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
416 return 0;
417#endif
418
419 /* Get some space for it */
420 dev_priv->mch_res.name = "i915 MCHBAR";
421 dev_priv->mch_res.flags = IORESOURCE_MEM;
422 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
423 &dev_priv->mch_res,
424 MCHBAR_SIZE, MCHBAR_SIZE,
425 PCIBIOS_MIN_MEM,
426 0, pcibios_align_resource,
427 dev_priv->bridge_dev);
428 if (ret) {
429 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
430 dev_priv->mch_res.start = 0;
431 return ret;
432 }
433
434 if (INTEL_INFO(dev)->gen >= 4)
435 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
436 upper_32_bits(dev_priv->mch_res.start));
437
438 pci_write_config_dword(dev_priv->bridge_dev, reg,
439 lower_32_bits(dev_priv->mch_res.start));
440 return 0;
441}
442
443/* Setup MCHBAR if possible, return true if we should disable it again */
444static void
445intel_setup_mchbar(struct drm_device *dev)
446{
fac5e23e 447 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 448 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
449 u32 temp;
450 bool enabled;
451
452 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
453 return;
454
455 dev_priv->mchbar_need_disable = false;
456
457 if (IS_I915G(dev) || IS_I915GM(dev)) {
458 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
459 enabled = !!(temp & DEVEN_MCHBAR_EN);
460 } else {
461 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
462 enabled = temp & 1;
463 }
464
465 /* If it's already enabled, don't have to do anything */
466 if (enabled)
467 return;
468
469 if (intel_alloc_mchbar_resource(dev))
470 return;
471
472 dev_priv->mchbar_need_disable = true;
473
474 /* Space is allocated or reserved, so enable it. */
475 if (IS_I915G(dev) || IS_I915GM(dev)) {
476 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
477 temp | DEVEN_MCHBAR_EN);
478 } else {
479 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
480 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
481 }
482}
483
484static void
485intel_teardown_mchbar(struct drm_device *dev)
486{
fac5e23e 487 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 488 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
489
490 if (dev_priv->mchbar_need_disable) {
491 if (IS_I915G(dev) || IS_I915GM(dev)) {
492 u32 deven_val;
493
494 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
495 &deven_val);
496 deven_val &= ~DEVEN_MCHBAR_EN;
497 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
498 deven_val);
499 } else {
500 u32 mchbar_val;
501
502 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
503 &mchbar_val);
504 mchbar_val &= ~1;
505 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
506 mchbar_val);
507 }
508 }
509
510 if (dev_priv->mch_res.start)
511 release_resource(&dev_priv->mch_res);
512}
513
514/* true = enable decode, false = disable decoder */
515static unsigned int i915_vga_set_decode(void *cookie, bool state)
516{
517 struct drm_device *dev = cookie;
518
519 intel_modeset_vga_set_state(dev, state);
520 if (state)
521 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
522 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
523 else
524 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
525}
526
527static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
528{
529 struct drm_device *dev = pci_get_drvdata(pdev);
530 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
531
532 if (state == VGA_SWITCHEROO_ON) {
533 pr_info("switched on\n");
534 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
535 /* i915 resume handler doesn't set to D0 */
536 pci_set_power_state(dev->pdev, PCI_D0);
537 i915_resume_switcheroo(dev);
538 dev->switch_power_state = DRM_SWITCH_POWER_ON;
539 } else {
540 pr_info("switched off\n");
541 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
542 i915_suspend_switcheroo(dev, pmm);
543 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
544 }
545}
546
547static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
548{
549 struct drm_device *dev = pci_get_drvdata(pdev);
550
551 /*
552 * FIXME: open_count is protected by drm_global_mutex but that would lead to
553 * locking inversion with the driver load path. And the access here is
554 * completely racy anyway. So don't bother with locking for now.
555 */
556 return dev->open_count == 0;
557}
558
559static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
560 .set_gpu_state = i915_switcheroo_set_state,
561 .reprobe = NULL,
562 .can_switch = i915_switcheroo_can_switch,
563};
564
565static void i915_gem_fini(struct drm_device *dev)
566{
567 struct drm_i915_private *dev_priv = to_i915(dev);
568
569 /*
570 * Neither the BIOS, ourselves or any other kernel
571 * expects the system to be in execlists mode on startup,
572 * so we need to reset the GPU back to legacy mode. And the only
573 * known way to disable logical contexts is through a GPU reset.
574 *
575 * So in order to leave the system in a known default configuration,
576 * always reset the GPU upon unload. Afterwards we then clean up the
577 * GEM state tracking, flushing off the requests and leaving the
578 * system in a known idle state.
579 *
580 * Note that is of the upmost importance that the GPU is idle and
581 * all stray writes are flushed *before* we dismantle the backing
582 * storage for the pinned objects.
583 *
584 * However, since we are uncertain that reseting the GPU on older
585 * machines is a good idea, we don't - just in case it leaves the
586 * machine in an unusable condition.
587 */
588 if (HAS_HW_CONTEXTS(dev)) {
589 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
590 WARN_ON(reset && reset != -ENODEV);
591 }
592
593 mutex_lock(&dev->struct_mutex);
594 i915_gem_reset(dev);
595 i915_gem_cleanup_engines(dev);
596 i915_gem_context_fini(dev);
597 mutex_unlock(&dev->struct_mutex);
598
599 WARN_ON(!list_empty(&to_i915(dev)->context_list));
600}
601
602static int i915_load_modeset_init(struct drm_device *dev)
603{
fac5e23e 604 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 605 int ret;
606
607 if (i915_inject_load_failure())
608 return -ENODEV;
609
610 ret = intel_bios_init(dev_priv);
611 if (ret)
612 DRM_INFO("failed to find VBIOS tables\n");
613
614 /* If we have > 1 VGA cards, then we need to arbitrate access
615 * to the common VGA resources.
616 *
617 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
618 * then we do not take part in VGA arbitration and the
619 * vga_client_register() fails with -ENODEV.
620 */
621 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
622 if (ret && ret != -ENODEV)
623 goto out;
624
625 intel_register_dsm_handler();
626
627 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
628 if (ret)
629 goto cleanup_vga_client;
630
631 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
632 intel_update_rawclk(dev_priv);
633
634 intel_power_domains_init_hw(dev_priv, false);
635
636 intel_csr_ucode_init(dev_priv);
637
638 ret = intel_irq_install(dev_priv);
639 if (ret)
640 goto cleanup_csr;
641
642 intel_setup_gmbus(dev);
643
644 /* Important: The output setup functions called by modeset_init need
645 * working irqs for e.g. gmbus and dp aux transfers. */
646 intel_modeset_init(dev);
647
648 intel_guc_init(dev);
649
650 ret = i915_gem_init(dev);
651 if (ret)
652 goto cleanup_irq;
653
654 intel_modeset_gem_init(dev);
655
656 if (INTEL_INFO(dev)->num_pipes == 0)
657 return 0;
658
659 ret = intel_fbdev_init(dev);
660 if (ret)
661 goto cleanup_gem;
662
663 /* Only enable hotplug handling once the fbdev is fully set up. */
664 intel_hpd_init(dev_priv);
665
666 drm_kms_helper_poll_init(dev);
667
668 return 0;
669
670cleanup_gem:
671 i915_gem_fini(dev);
672cleanup_irq:
673 intel_guc_fini(dev);
674 drm_irq_uninstall(dev);
675 intel_teardown_gmbus(dev);
676cleanup_csr:
677 intel_csr_ucode_fini(dev_priv);
678 intel_power_domains_fini(dev_priv);
679 vga_switcheroo_unregister_client(dev->pdev);
680cleanup_vga_client:
681 vga_client_register(dev->pdev, NULL, NULL, NULL);
682out:
683 return ret;
684}
685
686#if IS_ENABLED(CONFIG_FB)
687static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
688{
689 struct apertures_struct *ap;
91c8a326 690 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 691 struct i915_ggtt *ggtt = &dev_priv->ggtt;
692 bool primary;
693 int ret;
694
695 ap = alloc_apertures(1);
696 if (!ap)
697 return -ENOMEM;
698
699 ap->ranges[0].base = ggtt->mappable_base;
700 ap->ranges[0].size = ggtt->mappable_end;
701
702 primary =
703 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
704
705 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
706
707 kfree(ap);
708
709 return ret;
710}
711#else
712static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
713{
714 return 0;
715}
716#endif
717
718#if !defined(CONFIG_VGA_CONSOLE)
719static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
720{
721 return 0;
722}
723#elif !defined(CONFIG_DUMMY_CONSOLE)
724static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
725{
726 return -ENODEV;
727}
728#else
729static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
730{
731 int ret = 0;
732
733 DRM_INFO("Replacing VGA console driver\n");
734
735 console_lock();
736 if (con_is_bound(&vga_con))
737 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
738 if (ret == 0) {
739 ret = do_unregister_con_driver(&vga_con);
740
741 /* Ignore "already unregistered". */
742 if (ret == -ENODEV)
743 ret = 0;
744 }
745 console_unlock();
746
747 return ret;
748}
749#endif
750
0673ad47
CW		 751static void intel_init_dpio(struct drm_i915_private *dev_priv)
752{
753 /*
754 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
755 * CHV x1 PHY (DP/HDMI D)
756 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
757 */
758 if (IS_CHERRYVIEW(dev_priv)) {
759 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
760 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
761 } else if (IS_VALLEYVIEW(dev_priv)) {
762 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
763 }
764}
765
766static int i915_workqueues_init(struct drm_i915_private *dev_priv)
767{
768 /*
769 * The i915 workqueue is primarily used for batched retirement of
770 * requests (and thus managing bo) once the task has been completed
771 * by the GPU. i915_gem_retire_requests() is called directly when we
772 * need high-priority retirement, such as waiting for an explicit
773 * bo.
774 *
775 * It is also used for periodic low-priority events, such as
776 * idle-timers and recording error state.
777 *
778 * All tasks on the workqueue are expected to acquire the dev mutex
779 * so there is no point in running more than one instance of the
780 * workqueue at any time. Use an ordered one.
781 */
782 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
783 if (dev_priv->wq == NULL)
784 goto out_err;
785
786 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
787 if (dev_priv->hotplug.dp_wq == NULL)
788 goto out_free_wq;
789
0673ad47
CW		 790 return 0;
791
0673ad47
CW		 792out_free_wq:
793 destroy_workqueue(dev_priv->wq);
794out_err:
795 DRM_ERROR("Failed to allocate workqueues.\n");
796
797 return -ENOMEM;
798}
799
800static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
801{
0673ad47
CW		 802 destroy_workqueue(dev_priv->hotplug.dp_wq);
803 destroy_workqueue(dev_priv->wq);
804}
805
806/**
807 * i915_driver_init_early - setup state not requiring device access
808 * @dev_priv: device private
809 *
810 * Initialize everything that is a "SW-only" state, that is state not
811 * requiring accessing the device or exposing the driver via kernel internal
812 * or userspace interfaces. Example steps belonging here: lock initialization,
813 * system memory allocation, setting up device specific attributes and
814 * function hooks not requiring accessing the device.
815 */
816static int i915_driver_init_early(struct drm_i915_private *dev_priv,
817 const struct pci_device_id *ent)
818{
819 const struct intel_device_info *match_info =
820 (struct intel_device_info *)ent->driver_data;
821 struct intel_device_info *device_info;
822 int ret = 0;
823
824 if (i915_inject_load_failure())
825 return -ENODEV;
826
827 /* Setup the write-once "constant" device info */
94b4f3ba 828 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 829 memcpy(device_info, match_info, sizeof(*device_info));
830 device_info->device_id = dev_priv->drm.pdev->device;
831
832 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
833 device_info->gen_mask = BIT(device_info->gen - 1);
834
835 spin_lock_init(&dev_priv->irq_lock);
836 spin_lock_init(&dev_priv->gpu_error.lock);
837 mutex_init(&dev_priv->backlight_lock);
838 spin_lock_init(&dev_priv->uncore.lock);
839 spin_lock_init(&dev_priv->mm.object_stat_lock);
840 spin_lock_init(&dev_priv->mmio_flip_lock);
841 mutex_init(&dev_priv->sb_lock);
842 mutex_init(&dev_priv->modeset_restore_lock);
843 mutex_init(&dev_priv->av_mutex);
844 mutex_init(&dev_priv->wm.wm_mutex);
845 mutex_init(&dev_priv->pps_mutex);
846
847 ret = i915_workqueues_init(dev_priv);
848 if (ret < 0)
849 return ret;
850
851 ret = intel_gvt_init(dev_priv);
852 if (ret < 0)
853 goto err_workqueues;
854
855 /* This must be called before any calls to HAS_PCH_* */
856 intel_detect_pch(&dev_priv->drm);
857
858 intel_pm_setup(&dev_priv->drm);
859 intel_init_dpio(dev_priv);
860 intel_power_domains_init(dev_priv);
861 intel_irq_init(dev_priv);
862 intel_init_display_hooks(dev_priv);
863 intel_init_clock_gating_hooks(dev_priv);
864 intel_init_audio_hooks(dev_priv);
865 i915_gem_load_init(&dev_priv->drm);
866
867 intel_display_crc_init(&dev_priv->drm);
868
94b4f3ba 869 intel_device_info_dump(dev_priv);
0673ad47
CW		 870
871 /* Not all pre-production machines fall into this category, only the
872 * very first ones. Almost everything should work, except for maybe
873 * suspend/resume. And we don't implement workarounds that affect only
874 * pre-production machines. */
875 if (IS_HSW_EARLY_SDV(dev_priv))
876 DRM_INFO("This is an early pre-production Haswell machine. "
877 "It may not be fully functional.\n");
878
879 return 0;
880
881err_workqueues:
882 i915_workqueues_cleanup(dev_priv);
883 return ret;
884}
885
886/**
887 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
888 * @dev_priv: device private
889 */
890static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
891{
91c8a326 892 i915_gem_load_cleanup(&dev_priv->drm);
0673ad47
CW		 893 i915_workqueues_cleanup(dev_priv);
894}
895
896static int i915_mmio_setup(struct drm_device *dev)
897{
898 struct drm_i915_private *dev_priv = to_i915(dev);
899 int mmio_bar;
900 int mmio_size;
901
902 mmio_bar = IS_GEN2(dev) ? 1 : 0;
903 /*
904 * Before gen4, the registers and the GTT are behind different BARs.
905 * However, from gen4 onwards, the registers and the GTT are shared
906 * in the same BAR, so we want to restrict this ioremap from
907 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
908 * the register BAR remains the same size for all the earlier
909 * generations up to Ironlake.
910 */
911 if (INTEL_INFO(dev)->gen < 5)
912 mmio_size = 512 * 1024;
913 else
914 mmio_size = 2 * 1024 * 1024;
915 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
916 if (dev_priv->regs == NULL) {
917 DRM_ERROR("failed to map registers\n");
918
919 return -EIO;
920 }
921
922 /* Try to make sure MCHBAR is enabled before poking at it */
923 intel_setup_mchbar(dev);
924
925 return 0;
926}
927
928static void i915_mmio_cleanup(struct drm_device *dev)
929{
930 struct drm_i915_private *dev_priv = to_i915(dev);
931
932 intel_teardown_mchbar(dev);
933 pci_iounmap(dev->pdev, dev_priv->regs);
934}
935
936/**
937 * i915_driver_init_mmio - setup device MMIO
938 * @dev_priv: device private
939 *
940 * Setup minimal device state necessary for MMIO accesses later in the
941 * initialization sequence. The setup here should avoid any other device-wide
942 * side effects or exposing the driver via kernel internal or user space
943 * interfaces.
944 */
945static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
946{
91c8a326 947 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 948 int ret;
949
950 if (i915_inject_load_failure())
951 return -ENODEV;
952
953 if (i915_get_bridge_dev(dev))
954 return -EIO;
955
956 ret = i915_mmio_setup(dev);
957 if (ret < 0)
958 goto put_bridge;
959
960 intel_uncore_init(dev_priv);
961
962 return 0;
963
964put_bridge:
965 pci_dev_put(dev_priv->bridge_dev);
966
967 return ret;
968}
969
970/**
971 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
972 * @dev_priv: device private
973 */
974static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
975{
91c8a326 976 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 977
978 intel_uncore_fini(dev_priv);
979 i915_mmio_cleanup(dev);
980 pci_dev_put(dev_priv->bridge_dev);
981}
982
94b4f3ba
CW		 983static void intel_sanitize_options(struct drm_i915_private *dev_priv)
984{
985 i915.enable_execlists =
986 intel_sanitize_enable_execlists(dev_priv,
987 i915.enable_execlists);
988
989 /*
990 * i915.enable_ppgtt is read-only, so do an early pass to validate the
991 * user's requested state against the hardware/driver capabilities. We
992 * do this now so that we can print out any log messages once rather
993 * than every time we check intel_enable_ppgtt().
994 */
995 i915.enable_ppgtt =
996 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
997 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
998}
999
0673ad47
CW		 1000/**
1001 * i915_driver_init_hw - setup state requiring device access
1002 * @dev_priv: device private
1003 *
1004 * Setup state that requires accessing the device, but doesn't require
1005 * exposing the driver via kernel internal or userspace interfaces.
1006 */
1007static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1008{
91c8a326 1009 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1010 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1011 uint32_t aperture_size;
1012 int ret;
1013
1014 if (i915_inject_load_failure())
1015 return -ENODEV;
1016
94b4f3ba
CW		 1017 intel_device_info_runtime_init(dev_priv);
1018
1019 intel_sanitize_options(dev_priv);
0673ad47
CW		 1020
1021 ret = i915_ggtt_init_hw(dev);
1022 if (ret)
1023 return ret;
1024
1025 ret = i915_ggtt_enable_hw(dev);
1026 if (ret) {
1027 DRM_ERROR("failed to enable GGTT\n");
1028 goto out_ggtt;
1029 }
1030
1031 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1032 * otherwise the vga fbdev driver falls over. */
1033 ret = i915_kick_out_firmware_fb(dev_priv);
1034 if (ret) {
1035 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1036 goto out_ggtt;
1037 }
1038
1039 ret = i915_kick_out_vgacon(dev_priv);
1040 if (ret) {
1041 DRM_ERROR("failed to remove conflicting VGA console\n");
1042 goto out_ggtt;
1043 }
1044
1045 pci_set_master(dev->pdev);
1046
1047 /* overlay on gen2 is broken and can't address above 1G */
1048 if (IS_GEN2(dev)) {
1049 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1050 if (ret) {
1051 DRM_ERROR("failed to set DMA mask\n");
1052
1053 goto out_ggtt;
1054 }
1055 }
1056
1057
1058 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1059 * using 32bit addressing, overwriting memory if HWS is located
1060 * above 4GB.
1061 *
1062 * The documentation also mentions an issue with undefined
1063 * behaviour if any general state is accessed within a page above 4GB,
1064 * which also needs to be handled carefully.
1065 */
1066 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1067 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1068
1069 if (ret) {
1070 DRM_ERROR("failed to set DMA mask\n");
1071
1072 goto out_ggtt;
1073 }
1074 }
1075
1076 aperture_size = ggtt->mappable_end;
1077
1078 ggtt->mappable =
1079 io_mapping_create_wc(ggtt->mappable_base,
1080 aperture_size);
1081 if (!ggtt->mappable) {
1082 ret = -EIO;
1083 goto out_ggtt;
1084 }
1085
1086 ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1087 aperture_size);
1088
1089 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1090 PM_QOS_DEFAULT_VALUE);
1091
1092 intel_uncore_sanitize(dev_priv);
1093
1094 intel_opregion_setup(dev_priv);
1095
1096 i915_gem_load_init_fences(dev_priv);
1097
1098 /* On the 945G/GM, the chipset reports the MSI capability on the
1099 * integrated graphics even though the support isn't actually there
1100 * according to the published specs. It doesn't appear to function
1101 * correctly in testing on 945G.
1102 * This may be a side effect of MSI having been made available for PEG
1103 * and the registers being closely associated.
1104 *
1105 * According to chipset errata, on the 965GM, MSI interrupts may
1106 * be lost or delayed, but we use them anyways to avoid
1107 * stuck interrupts on some machines.
1108 */
1109 if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1110 if (pci_enable_msi(dev->pdev) < 0)
1111 DRM_DEBUG_DRIVER("can't enable MSI");
1112 }
1113
1114 return 0;
1115
1116out_ggtt:
1117 i915_ggtt_cleanup_hw(dev);
1118
1119 return ret;
1120}
1121
1122/**
1123 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1124 * @dev_priv: device private
1125 */
1126static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1127{
91c8a326 1128 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1129 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1130
1131 if (dev->pdev->msi_enabled)
1132 pci_disable_msi(dev->pdev);
1133
1134 pm_qos_remove_request(&dev_priv->pm_qos);
1135 arch_phys_wc_del(ggtt->mtrr);
1136 io_mapping_free(ggtt->mappable);
1137 i915_ggtt_cleanup_hw(dev);
1138}
1139
1140/**
1141 * i915_driver_register - register the driver with the rest of the system
1142 * @dev_priv: device private
1143 *
1144 * Perform any steps necessary to make the driver available via kernel
1145 * internal or userspace interfaces.
1146 */
1147static void i915_driver_register(struct drm_i915_private *dev_priv)
1148{
91c8a326 1149 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1150
1151 i915_gem_shrinker_init(dev_priv);
1152
1153 /*
1154 * Notify a valid surface after modesetting,
1155 * when running inside a VM.
1156 */
1157 if (intel_vgpu_active(dev_priv))
1158 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1159
1160 /* Reveal our presence to userspace */
1161 if (drm_dev_register(dev, 0) == 0) {
1162 i915_debugfs_register(dev_priv);
1163 i915_setup_sysfs(dev);
1164 } else
1165 DRM_ERROR("Failed to register driver for userspace access!\n");
1166
1167 if (INTEL_INFO(dev_priv)->num_pipes) {
1168 /* Must be done after probing outputs */
1169 intel_opregion_register(dev_priv);
1170 acpi_video_register();
1171 }
1172
1173 if (IS_GEN5(dev_priv))
1174 intel_gpu_ips_init(dev_priv);
1175
1176 i915_audio_component_init(dev_priv);
1177
1178 /*
1179 * Some ports require correctly set-up hpd registers for detection to
1180 * work properly (leading to ghost connected connector status), e.g. VGA
1181 * on gm45. Hence we can only set up the initial fbdev config after hpd
1182 * irqs are fully enabled. We do it last so that the async config
1183 * cannot run before the connectors are registered.
1184 */
1185 intel_fbdev_initial_config_async(dev);
1186}
1187
1188/**
1189 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1190 * @dev_priv: device private
1191 */
1192static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1193{
1194 i915_audio_component_cleanup(dev_priv);
1195
1196 intel_gpu_ips_teardown();
1197 acpi_video_unregister();
1198 intel_opregion_unregister(dev_priv);
1199
91c8a326 1200 i915_teardown_sysfs(&dev_priv->drm);
0673ad47 1201 i915_debugfs_unregister(dev_priv);
91c8a326 1202 drm_dev_unregister(&dev_priv->drm);
0673ad47
CW		 1203
1204 i915_gem_shrinker_cleanup(dev_priv);
1205}
1206
1207/**
1208 * i915_driver_load - setup chip and create an initial config
1209 * @dev: DRM device
1210 * @flags: startup flags
1211 *
1212 * The driver load routine has to do several things:
1213 * - drive output discovery via intel_modeset_init()
1214 * - initialize the memory manager
1215 * - allocate initial config memory
1216 * - setup the DRM framebuffer with the allocated memory
1217 */
42f5551d 1218int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47
CW		 1219{
1220 struct drm_i915_private *dev_priv;
1221 int ret;
7d87a7f7 1222
a09d0ba1
CW		 1223 if (i915.nuclear_pageflip)
1224 driver.driver_features |= DRIVER_ATOMIC;
1225
0673ad47
CW		 1226 ret = -ENOMEM;
1227 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1228 if (dev_priv)
1229 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1230 if (ret) {
1231 dev_printk(KERN_ERR, &pdev->dev,
1232 "[" DRM_NAME ":%s] allocation failed\n", __func__);
1233 kfree(dev_priv);
1234 return ret;
1235 }
72bbf0af 1236
0673ad47
CW		 1237 dev_priv->drm.pdev = pdev;
1238 dev_priv->drm.dev_private = dev_priv;
719388e1 1239
0673ad47
CW		 1240 ret = pci_enable_device(pdev);
1241 if (ret)
1242 goto out_free_priv;
1347f5b4 1243
0673ad47 1244 pci_set_drvdata(pdev, &dev_priv->drm);
ef11bdb3 1245
0673ad47
CW		 1246 ret = i915_driver_init_early(dev_priv, ent);
1247 if (ret < 0)
1248 goto out_pci_disable;
ef11bdb3 1249
0673ad47 1250 intel_runtime_pm_get(dev_priv);
1da177e4 1251
0673ad47
CW		 1252 ret = i915_driver_init_mmio(dev_priv);
1253 if (ret < 0)
1254 goto out_runtime_pm_put;
79e53945 1255
0673ad47
CW		 1256 ret = i915_driver_init_hw(dev_priv);
1257 if (ret < 0)
1258 goto out_cleanup_mmio;
30c964a6
RB		 1259
1260 /*
0673ad47
CW		 1261 * TODO: move the vblank init and parts of modeset init steps into one
1262 * of the i915_driver_init_/i915_driver_register functions according
1263 * to the role/effect of the given init step.
30c964a6 1264 */
0673ad47 1265 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1266 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1267 INTEL_INFO(dev_priv)->num_pipes);
1268 if (ret)
1269 goto out_cleanup_hw;
30c964a6
RB		 1270 }
1271
91c8a326 1272 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47
CW		 1273 if (ret < 0)
1274 goto out_cleanup_vblank;
1275
1276 i915_driver_register(dev_priv);
1277
1278 intel_runtime_pm_enable(dev_priv);
1279
1280 intel_runtime_pm_put(dev_priv);
1281
1282 return 0;
1283
1284out_cleanup_vblank:
91c8a326 1285 drm_vblank_cleanup(&dev_priv->drm);
0673ad47
CW		 1286out_cleanup_hw:
1287 i915_driver_cleanup_hw(dev_priv);
1288out_cleanup_mmio:
1289 i915_driver_cleanup_mmio(dev_priv);
1290out_runtime_pm_put:
1291 intel_runtime_pm_put(dev_priv);
1292 i915_driver_cleanup_early(dev_priv);
1293out_pci_disable:
1294 pci_disable_device(pdev);
1295out_free_priv:
1296 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1297 drm_dev_unref(&dev_priv->drm);
30c964a6
RB		 1298 return ret;
1299}
1300
42f5551d 1301void i915_driver_unload(struct drm_device *dev)
3bad0781 1302{
fac5e23e 1303 struct drm_i915_private *dev_priv = to_i915(dev);
3bad0781 1304
0673ad47
CW		 1305 intel_fbdev_fini(dev);
1306
42f5551d
CW		 1307 if (i915_gem_suspend(dev))
1308 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1309
0673ad47
CW		 1310 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1311
1312 i915_driver_unregister(dev_priv);
1313
1314 drm_vblank_cleanup(dev);
1315
1316 intel_modeset_cleanup(dev);
1317
3bad0781 1318 /*
0673ad47
CW		 1319 * free the memory space allocated for the child device
1320 * config parsed from VBT
3bad0781 1321 */
0673ad47
CW		 1322 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1323 kfree(dev_priv->vbt.child_dev);
1324 dev_priv->vbt.child_dev = NULL;
1325 dev_priv->vbt.child_dev_num = 0;
1326 }
1327 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1328 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1329 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1330 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1331
0673ad47
CW		 1332 vga_switcheroo_unregister_client(dev->pdev);
1333 vga_client_register(dev->pdev, NULL, NULL, NULL);
bcdb72ac 1334
0673ad47 1335 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1336
0673ad47
CW		 1337 /* Free error state after interrupts are fully disabled. */
1338 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1339 i915_destroy_error_state(dev);
1340
1341 /* Flush any outstanding unpin_work. */
1342 flush_workqueue(dev_priv->wq);
1343
1344 intel_guc_fini(dev);
1345 i915_gem_fini(dev);
1346 intel_fbc_cleanup_cfb(dev_priv);
1347
1348 intel_power_domains_fini(dev_priv);
1349
1350 i915_driver_cleanup_hw(dev_priv);
1351 i915_driver_cleanup_mmio(dev_priv);
1352
1353 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1354
1355 i915_driver_cleanup_early(dev_priv);
3bad0781
ZW		 1356}
1357
0673ad47 1358static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1359{
0673ad47 1360 int ret;
2911a35b 1361
0673ad47
CW		 1362 ret = i915_gem_open(dev, file);
1363 if (ret)
1364 return ret;
2911a35b 1365
0673ad47
CW		 1366 return 0;
1367}
71386ef9 1368
0673ad47
CW		 1369/**
1370 * i915_driver_lastclose - clean up after all DRM clients have exited
1371 * @dev: DRM device
1372 *
1373 * Take care of cleaning up after all DRM clients have exited. In the
1374 * mode setting case, we want to restore the kernel's initial mode (just
1375 * in case the last client left us in a bad state).
1376 *
1377 * Additionally, in the non-mode setting case, we'll tear down the GTT
1378 * and DMA structures, since the kernel won't be using them, and clea
1379 * up any GEM state.
1380 */
1381static void i915_driver_lastclose(struct drm_device *dev)
1382{
1383 intel_fbdev_restore_mode(dev);
1384 vga_switcheroo_process_delayed_switch();
1385}
2911a35b 1386
0673ad47
CW		 1387static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1388{
1389 mutex_lock(&dev->struct_mutex);
1390 i915_gem_context_close(dev, file);
1391 i915_gem_release(dev, file);
1392 mutex_unlock(&dev->struct_mutex);
1393}
1394
1395static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1396{
1397 struct drm_i915_file_private *file_priv = file->driver_priv;
1398
1399 kfree(file_priv);
2911a35b
BW		 1400}
1401
07f9cd0b
ID		 1402static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1403{
91c8a326 1404 struct drm_device *dev = &dev_priv->drm;
19c8054c 1405 struct intel_encoder *encoder;
07f9cd0b
ID		 1406
1407 drm_modeset_lock_all(dev);
19c8054c
JN		 1408 for_each_intel_encoder(dev, encoder)
1409 if (encoder->suspend)
1410 encoder->suspend(encoder);
07f9cd0b
ID		 1411 drm_modeset_unlock_all(dev);
1412}
1413
1a5df187
PZ		 1414static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1415 bool rpm_resume);
507e126e 1416static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1417
bc87229f
ID		 1418static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1419{
1420#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1421 if (acpi_target_system_state() < ACPI_STATE_S3)
1422 return true;
1423#endif
1424 return false;
1425}
ebc32824 1426
5e365c39 1427static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1428{
fac5e23e 1429 struct drm_i915_private *dev_priv = to_i915(dev);
e5747e3a 1430 pci_power_t opregion_target_state;
d5818938 1431 int error;
61caf87c 1432
b8efb17b
ZR		 1433 /* ignore lid events during suspend */
1434 mutex_lock(&dev_priv->modeset_restore_lock);
1435 dev_priv->modeset_restore = MODESET_SUSPENDED;
1436 mutex_unlock(&dev_priv->modeset_restore_lock);
1437
1f814dac
ID		 1438 disable_rpm_wakeref_asserts(dev_priv);
1439
c67a470b
PZ		 1440 /* We do a lot of poking in a lot of registers, make sure they work
1441 * properly. */
da7e29bd 1442 intel_display_set_init_power(dev_priv, true);
cb10799c 1443
5bcf719b
DA		 1444 drm_kms_helper_poll_disable(dev);
1445
ba8bbcf6 1446 pci_save_state(dev->pdev);
ba8bbcf6 1447
d5818938
DV		 1448 error = i915_gem_suspend(dev);
1449 if (error) {
1450 dev_err(&dev->pdev->dev,
1451 "GEM idle failed, resume might fail\n");
1f814dac 1452 goto out;
d5818938 1453 }
db1b76ca 1454
a1c41994
AD		 1455 intel_guc_suspend(dev);
1456
dc97997a 1457 intel_suspend_gt_powersave(dev_priv);
a261b246 1458
6b72d486 1459 intel_display_suspend(dev);
2eb5252e 1460
d5818938 1461 intel_dp_mst_suspend(dev);
7d708ee4 1462
d5818938
DV		 1463 intel_runtime_pm_disable_interrupts(dev_priv);
1464 intel_hpd_cancel_work(dev_priv);
09b64267 1465
d5818938 1466 intel_suspend_encoders(dev_priv);
0e32b39c 1467
d5818938 1468 intel_suspend_hw(dev);
5669fcac 1469
828c7908
BW		 1470 i915_gem_suspend_gtt_mappings(dev);
1471
9e06dd39
JB		 1472 i915_save_state(dev);
1473
bc87229f 1474 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1475 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1476
dc97997a 1477 intel_uncore_forcewake_reset(dev_priv, false);
03d92e47 1478 intel_opregion_unregister(dev_priv);
8ee1c3db 1479
82e3b8c1 1480 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1481
62d5d69b
MK		 1482 dev_priv->suspend_count++;
1483
85e90679
KCA		 1484 intel_display_set_init_power(dev_priv, false);
1485
f74ed08d 1486 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1487
1f814dac
ID		 1488out:
1489 enable_rpm_wakeref_asserts(dev_priv);
1490
1491 return error;
84b79f8d
RW		 1492}
1493
ab3be73f 1494static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
c3c09c95 1495{
fac5e23e 1496 struct drm_i915_private *dev_priv = to_i915(drm_dev);
bc87229f 1497 bool fw_csr;
c3c09c95
ID		 1498 int ret;
1499
1f814dac
ID		 1500 disable_rpm_wakeref_asserts(dev_priv);
1501
a7c8125f
ID		 1502 fw_csr = !IS_BROXTON(dev_priv) &&
1503 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1504 /*
1505 * In case of firmware assisted context save/restore don't manually
1506 * deinit the power domains. This also means the CSR/DMC firmware will
1507 * stay active, it will power down any HW resources as required and
1508 * also enable deeper system power states that would be blocked if the
1509 * firmware was inactive.
1510 */
1511 if (!fw_csr)
1512 intel_power_domains_suspend(dev_priv);
73dfc227 1513
507e126e 1514 ret = 0;
b8aea3d1 1515 if (IS_BROXTON(dev_priv))
507e126e 1516 bxt_enable_dc9(dev_priv);
b8aea3d1 1517 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1518 hsw_enable_pc8(dev_priv);
1519 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1520 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1521
1522 if (ret) {
1523 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1524 if (!fw_csr)
1525 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1526
1f814dac 1527 goto out;
c3c09c95
ID		 1528 }
1529
1530 pci_disable_device(drm_dev->pdev);
ab3be73f 1531 /*
54875571 1532 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1533 * the device even though it's already in D3 and hang the machine. So
1534 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1535 * power down the device properly. The issue was seen on multiple old
1536 * GENs with different BIOS vendors, so having an explicit blacklist
1537 * is inpractical; apply the workaround on everything pre GEN6. The
1538 * platforms where the issue was seen:
1539 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1540 * Fujitsu FSC S7110
1541 * Acer Aspire 1830T
ab3be73f 1542 */
54875571 1543 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
ab3be73f 1544 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
c3c09c95 1545
bc87229f
ID		 1546 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1547
1f814dac
ID		 1548out:
1549 enable_rpm_wakeref_asserts(dev_priv);
1550
1551 return ret;
c3c09c95
ID		 1552}
1553
1751fcf9 1554int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1555{
1556 int error;
1557
ded8b07d 1558 if (!dev) {
84b79f8d
RW		 1559 DRM_ERROR("dev: %p\n", dev);
1560 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1561 return -ENODEV;
1562 }
1563
0b14cbd2
ID		 1564 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1565 state.event != PM_EVENT_FREEZE))
1566 return -EINVAL;
5bcf719b
DA		 1567
1568 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1569 return 0;
6eecba33 1570
5e365c39 1571 error = i915_drm_suspend(dev);
84b79f8d
RW		 1572 if (error)
1573 return error;
1574
ab3be73f 1575 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1576}
1577
5e365c39 1578static int i915_drm_resume(struct drm_device *dev)
76c4b250 1579{
fac5e23e 1580 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1581 int ret;
9d49c0ef 1582
1f814dac
ID		 1583 disable_rpm_wakeref_asserts(dev_priv);
1584
ac840ae5
VS		 1585 ret = i915_ggtt_enable_hw(dev);
1586 if (ret)
1587 DRM_ERROR("failed to re-enable GGTT\n");
1588
f74ed08d
ID		 1589 intel_csr_ucode_resume(dev_priv);
1590
d5818938
DV		 1591 mutex_lock(&dev->struct_mutex);
1592 i915_gem_restore_gtt_mappings(dev);
1593 mutex_unlock(&dev->struct_mutex);
9d49c0ef 1594
61caf87c 1595 i915_restore_state(dev);
6f9f4b7a 1596 intel_opregion_setup(dev_priv);
61caf87c 1597
d5818938
DV		 1598 intel_init_pch_refclk(dev);
1599 drm_mode_config_reset(dev);
1833b134 1600
364aece0
PA		 1601 /*
1602 * Interrupts have to be enabled before any batches are run. If not the
1603 * GPU will hang. i915_gem_init_hw() will initiate batches to
1604 * update/restore the context.
1605 *
1606 * Modeset enabling in intel_modeset_init_hw() also needs working
1607 * interrupts.
1608 */
1609 intel_runtime_pm_enable_interrupts(dev_priv);
1610
d5818938
DV		 1611 mutex_lock(&dev->struct_mutex);
1612 if (i915_gem_init_hw(dev)) {
1613 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
338d0eea 1614 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
d5818938
DV		 1615 }
1616 mutex_unlock(&dev->struct_mutex);
226485e9 1617
a1c41994
AD		 1618 intel_guc_resume(dev);
1619
d5818938 1620 intel_modeset_init_hw(dev);
24576d23 1621
d5818938
DV		 1622 spin_lock_irq(&dev_priv->irq_lock);
1623 if (dev_priv->display.hpd_irq_setup)
91d14251 1624 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1625 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1626
d5818938 1627 intel_dp_mst_resume(dev);
e7d6f7d7 1628
a16b7658
L		 1629 intel_display_resume(dev);
1630
d5818938
DV		 1631 /*
1632 * ... but also need to make sure that hotplug processing
1633 * doesn't cause havoc. Like in the driver load code we don't
1634 * bother with the tiny race here where we might loose hotplug
1635 * notifications.
1636 * */
1637 intel_hpd_init(dev_priv);
1638 /* Config may have changed between suspend and resume */
1639 drm_helper_hpd_irq_event(dev);
1daed3fb 1640
03d92e47 1641 intel_opregion_register(dev_priv);
44834a67 1642
82e3b8c1 1643 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1644
b8efb17b
ZR		 1645 mutex_lock(&dev_priv->modeset_restore_lock);
1646 dev_priv->modeset_restore = MODESET_DONE;
1647 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1648
6f9f4b7a 1649 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1650
ee6f280e
ID		 1651 drm_kms_helper_poll_enable(dev);
1652
1f814dac
ID		 1653 enable_rpm_wakeref_asserts(dev_priv);
1654
074c6ada 1655 return 0;
84b79f8d
RW		 1656}
1657
5e365c39 1658static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1659{
fac5e23e 1660 struct drm_i915_private *dev_priv = to_i915(dev);
44410cd0 1661 int ret;
36d61e67 1662
76c4b250
ID		 1663 /*
1664 * We have a resume ordering issue with the snd-hda driver also
1665 * requiring our device to be power up. Due to the lack of a
1666 * parent/child relationship we currently solve this with an early
1667 * resume hook.
1668 *
1669 * FIXME: This should be solved with a special hdmi sink device or
1670 * similar so that power domains can be employed.
1671 */
44410cd0
ID		 1672
1673 /*
1674 * Note that we need to set the power state explicitly, since we
1675 * powered off the device during freeze and the PCI core won't power
1676 * it back up for us during thaw. Powering off the device during
1677 * freeze is not a hard requirement though, and during the
1678 * suspend/resume phases the PCI core makes sure we get here with the
1679 * device powered on. So in case we change our freeze logic and keep
1680 * the device powered we can also remove the following set power state
1681 * call.
1682 */
1683 ret = pci_set_power_state(dev->pdev, PCI_D0);
1684 if (ret) {
1685 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1686 goto out;
1687 }
1688
1689 /*
1690 * Note that pci_enable_device() first enables any parent bridge
1691 * device and only then sets the power state for this device. The
1692 * bridge enabling is a nop though, since bridge devices are resumed
1693 * first. The order of enabling power and enabling the device is
1694 * imposed by the PCI core as described above, so here we preserve the
1695 * same order for the freeze/thaw phases.
1696 *
1697 * TODO: eventually we should remove pci_disable_device() /
1698 * pci_enable_enable_device() from suspend/resume. Due to how they
1699 * depend on the device enable refcount we can't anyway depend on them
1700 * disabling/enabling the device.
1701 */
bc87229f
ID		 1702 if (pci_enable_device(dev->pdev)) {
1703 ret = -EIO;
1704 goto out;
1705 }
84b79f8d
RW		 1706
1707 pci_set_master(dev->pdev);
1708
1f814dac
ID		 1709 disable_rpm_wakeref_asserts(dev_priv);
1710
666a4537 1711 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1712 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1713 if (ret)
ff0b187f
DL		 1714 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1715 ret);
36d61e67 1716
dc97997a 1717 intel_uncore_early_sanitize(dev_priv, true);
efee833a 1718
dc97997a 1719 if (IS_BROXTON(dev_priv)) {
da2f41d1
ID		 1720 if (!dev_priv->suspended_to_idle)
1721 gen9_sanitize_dc_state(dev_priv);
507e126e 1722 bxt_disable_dc9(dev_priv);
da2f41d1 1723 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1724 hsw_disable_pc8(dev_priv);
da2f41d1 1725 }
efee833a 1726
dc97997a 1727 intel_uncore_sanitize(dev_priv);
bc87229f 1728
a7c8125f
ID		 1729 if (IS_BROXTON(dev_priv) ||
1730 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 1731 intel_power_domains_init_hw(dev_priv, true);
1732
6e35e8ab
ID		 1733 enable_rpm_wakeref_asserts(dev_priv);
1734
bc87229f
ID		 1735out:
1736 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1737
1738 return ret;
76c4b250
ID		 1739}
1740
1751fcf9 1741int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1742{
50a0072f 1743 int ret;
76c4b250 1744
097dd837
ID		 1745 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1746 return 0;
1747
5e365c39 1748 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1749 if (ret)
1750 return ret;
1751
5a17514e
ID		 1752 return i915_drm_resume(dev);
1753}
1754
11ed50ec 1755/**
f3953dcb 1756 * i915_reset - reset chip after a hang
11ed50ec 1757 * @dev: drm device to reset
11ed50ec
BG		 1758 *
1759 * Reset the chip. Useful if a hang is detected. Returns zero on successful
1760 * reset or otherwise an error code.
1761 *
1762 * Procedure is fairly simple:
1763 * - reset the chip using the reset reg
1764 * - re-init context state
1765 * - re-init hardware status page
1766 * - re-init ring buffer
1767 * - re-init interrupt state
1768 * - re-init display
1769 */
c033666a 1770int i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 1771{
91c8a326 1772 struct drm_device *dev = &dev_priv->drm;
d98c52cf
CW		 1773 struct i915_gpu_error *error = &dev_priv->gpu_error;
1774 unsigned reset_counter;
0573ed4a 1775 int ret;
11ed50ec 1776
dc97997a 1777 intel_reset_gt_powersave(dev_priv);
dbea3cea 1778
d54a02c0 1779 mutex_lock(&dev->struct_mutex);
11ed50ec 1780
d98c52cf
CW		 1781 /* Clear any previous failed attempts at recovery. Time to try again. */
1782 atomic_andnot(I915_WEDGED, &error->reset_counter);
77f01230 1783
d98c52cf
CW		 1784 /* Clear the reset-in-progress flag and increment the reset epoch. */
1785 reset_counter = atomic_inc_return(&error->reset_counter);
1786 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
1787 ret = -EIO;
1788 goto error;
1789 }
1790
7b4d3a16
CW		 1791 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1792
d98c52cf 1793 i915_gem_reset(dev);
2e7c8ee7 1794
dc97997a 1795 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
0573ed4a 1796 if (ret) {
804e59a8
CW		 1797 if (ret != -ENODEV)
1798 DRM_ERROR("Failed to reset chip: %i\n", ret);
1799 else
1800 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 1801 goto error;
11ed50ec
BG		 1802 }
1803
1362b776
VS		 1804 intel_overlay_reset(dev_priv);
1805
11ed50ec
BG		 1806 /* Ok, now get things going again... */
1807
1808 /*
1809 * Everything depends on having the GTT running, so we need to start
1810 * there. Fortunately we don't need to do this unless we reset the
1811 * chip at a PCI level.
1812 *
1813 * Next we need to restore the context, but we don't use those
1814 * yet either...
1815 *
1816 * Ring buffer needs to be re-initialized in the KMS case, or if X
1817 * was running at the time of the reset (i.e. we weren't VT
1818 * switched away).
1819 */
33d30a9c 1820 ret = i915_gem_init_hw(dev);
33d30a9c
DV		 1821 if (ret) {
1822 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1823 goto error;
11ed50ec
BG		 1824 }
1825
d98c52cf
CW		 1826 mutex_unlock(&dev->struct_mutex);
1827
33d30a9c
DV		 1828 /*
1829 * rps/rc6 re-init is necessary to restore state lost after the
1830 * reset and the re-install of gt irqs. Skip for ironlake per
1831 * previous concerns that it doesn't respond well to some forms
1832 * of re-init after reset.
1833 */
1834 if (INTEL_INFO(dev)->gen > 5)
dc97997a 1835 intel_enable_gt_powersave(dev_priv);
33d30a9c 1836
11ed50ec 1837 return 0;
d98c52cf
CW		 1838
1839error:
1840 atomic_or(I915_WEDGED, &error->reset_counter);
1841 mutex_unlock(&dev->struct_mutex);
1842 return ret;
11ed50ec
BG		 1843}
1844
84b79f8d 1845static int i915_pm_suspend(struct device *dev)
112b715e 1846{
84b79f8d
RW		 1847 struct pci_dev *pdev = to_pci_dev(dev);
1848 struct drm_device *drm_dev = pci_get_drvdata(pdev);
112b715e 1849
ded8b07d 1850 if (!drm_dev) {
84b79f8d
RW		 1851 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1852 return -ENODEV;
1853 }
112b715e 1854
5bcf719b
DA		 1855 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1856 return 0;
1857
5e365c39 1858 return i915_drm_suspend(drm_dev);
76c4b250
ID		 1859}
1860
1861static int i915_pm_suspend_late(struct device *dev)
1862{
91c8a326 1863 struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
76c4b250
ID		 1864
1865 /*
c965d995 1866 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 1867 * requiring our device to be power up. Due to the lack of a
1868 * parent/child relationship we currently solve this with an late
1869 * suspend hook.
1870 *
1871 * FIXME: This should be solved with a special hdmi sink device or
1872 * similar so that power domains can be employed.
1873 */
1874 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1875 return 0;
112b715e 1876
ab3be73f
ID		 1877 return i915_drm_suspend_late(drm_dev, false);
1878}
1879
1880static int i915_pm_poweroff_late(struct device *dev)
1881{
91c8a326 1882 struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
ab3be73f
ID		 1883
1884 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1885 return 0;
1886
1887 return i915_drm_suspend_late(drm_dev, true);
cbda12d7
ZW		 1888}
1889
76c4b250
ID		 1890static int i915_pm_resume_early(struct device *dev)
1891{
91c8a326 1892 struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
76c4b250 1893
097dd837
ID		 1894 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1895 return 0;
1896
5e365c39 1897 return i915_drm_resume_early(drm_dev);
76c4b250
ID		 1898}
1899
84b79f8d 1900static int i915_pm_resume(struct device *dev)
cbda12d7 1901{
91c8a326 1902 struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
84b79f8d 1903
097dd837
ID		 1904 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1905 return 0;
1906
5a17514e 1907 return i915_drm_resume(drm_dev);
cbda12d7
ZW		 1908}
1909
1f19ac2a
CW		 1910/* freeze: before creating the hibernation_image */
1911static int i915_pm_freeze(struct device *dev)
1912{
1913 return i915_pm_suspend(dev);
1914}
1915
1916static int i915_pm_freeze_late(struct device *dev)
1917{
461fb99c
CW		 1918 int ret;
1919
1920 ret = i915_pm_suspend_late(dev);
1921 if (ret)
1922 return ret;
1923
1924 ret = i915_gem_freeze_late(dev_to_i915(dev));
1925 if (ret)
1926 return ret;
1927
1928 return 0;
1f19ac2a
CW		 1929}
1930
1931/* thaw: called after creating the hibernation image, but before turning off. */
1932static int i915_pm_thaw_early(struct device *dev)
1933{
1934 return i915_pm_resume_early(dev);
1935}
1936
1937static int i915_pm_thaw(struct device *dev)
1938{
1939 return i915_pm_resume(dev);
1940}
1941
1942/* restore: called after loading the hibernation image. */
1943static int i915_pm_restore_early(struct device *dev)
1944{
1945 return i915_pm_resume_early(dev);
1946}
1947
1948static int i915_pm_restore(struct device *dev)
1949{
1950 return i915_pm_resume(dev);
1951}
1952
ddeea5b0
ID		 1953/*
1954 * Save all Gunit registers that may be lost after a D3 and a subsequent
1955 * S0i[R123] transition. The list of registers needing a save/restore is
1956 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1957 * registers in the following way:
1958 * - Driver: saved/restored by the driver
1959 * - Punit : saved/restored by the Punit firmware
1960 * - No, w/o marking: no need to save/restore, since the register is R/O or
1961 * used internally by the HW in a way that doesn't depend
1962 * keeping the content across a suspend/resume.
1963 * - Debug : used for debugging
1964 *
1965 * We save/restore all registers marked with 'Driver', with the following
1966 * exceptions:
1967 * - Registers out of use, including also registers marked with 'Debug'.
1968 * These have no effect on the driver's operation, so we don't save/restore
1969 * them to reduce the overhead.
1970 * - Registers that are fully setup by an initialization function called from
1971 * the resume path. For example many clock gating and RPS/RC6 registers.
1972 * - Registers that provide the right functionality with their reset defaults.
1973 *
1974 * TODO: Except for registers that based on the above 3 criteria can be safely
1975 * ignored, we save/restore all others, practically treating the HW context as
1976 * a black-box for the driver. Further investigation is needed to reduce the
1977 * saved/restored registers even further, by following the same 3 criteria.
1978 */
1979static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1980{
1981 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1982 int i;
1983
1984 /* GAM 0x4000-0x4770 */
1985 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1986 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1987 s->arb_mode = I915_READ(ARB_MODE);
1988 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1989 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1990
1991 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 1992 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 1993
1994 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 1995 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 1996
1997 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1998 s->ecochk = I915_READ(GAM_ECOCHK);
1999 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2000 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2001
2002 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2003
2004 /* MBC 0x9024-0x91D0, 0x8500 */
2005 s->g3dctl = I915_READ(VLV_G3DCTL);
2006 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2007 s->mbctl = I915_READ(GEN6_MBCTL);
2008
2009 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2010 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2011 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2012 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2013 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2014 s->rstctl = I915_READ(GEN6_RSTCTL);
2015 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2016
2017 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2018 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2019 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2020 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2021 s->ecobus = I915_READ(ECOBUS);
2022 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2023 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2024 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2025 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2026 s->rcedata = I915_READ(VLV_RCEDATA);
2027 s->spare2gh = I915_READ(VLV_SPAREG2H);
2028
2029 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2030 s->gt_imr = I915_READ(GTIMR);
2031 s->gt_ier = I915_READ(GTIER);
2032 s->pm_imr = I915_READ(GEN6_PMIMR);
2033 s->pm_ier = I915_READ(GEN6_PMIER);
2034
2035 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2036 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2037
2038 /* GT SA CZ domain, 0x100000-0x138124 */
2039 s->tilectl = I915_READ(TILECTL);
2040 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2041 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2042 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2043 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2044
2045 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2046 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2047 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2048 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2049 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2050
2051 /*
2052 * Not saving any of:
2053 * DFT, 0x9800-0x9EC0
2054 * SARB, 0xB000-0xB1FC
2055 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2056 * PCI CFG
2057 */
2058}
2059
2060static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2061{
2062 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2063 u32 val;
2064 int i;
2065
2066 /* GAM 0x4000-0x4770 */
2067 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2068 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2069 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2070 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2071 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2072
2073 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2074 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2075
2076 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2077 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2078
2079 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2080 I915_WRITE(GAM_ECOCHK, s->ecochk);
2081 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2082 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2083
2084 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2085
2086 /* MBC 0x9024-0x91D0, 0x8500 */
2087 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2088 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2089 I915_WRITE(GEN6_MBCTL, s->mbctl);
2090
2091 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2092 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2093 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2094 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2095 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2096 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2097 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2098
2099 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2100 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2101 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2102 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2103 I915_WRITE(ECOBUS, s->ecobus);
2104 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2105 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2106 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2107 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2108 I915_WRITE(VLV_RCEDATA, s->rcedata);
2109 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2110
2111 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2112 I915_WRITE(GTIMR, s->gt_imr);
2113 I915_WRITE(GTIER, s->gt_ier);
2114 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2115 I915_WRITE(GEN6_PMIER, s->pm_ier);
2116
2117 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2118 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2119
2120 /* GT SA CZ domain, 0x100000-0x138124 */
2121 I915_WRITE(TILECTL, s->tilectl);
2122 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2123 /*
2124 * Preserve the GT allow wake and GFX force clock bit, they are not
2125 * be restored, as they are used to control the s0ix suspend/resume
2126 * sequence by the caller.
2127 */
2128 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2129 val &= VLV_GTLC_ALLOWWAKEREQ;
2130 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2131 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2132
2133 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2134 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2135 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2136 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2137
2138 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2139
2140 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2141 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2142 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2143 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2144 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2145}
2146
650ad970
ID		 2147int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2148{
2149 u32 val;
2150 int err;
2151
650ad970
ID		 2152 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2153 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2154 if (force_on)
2155 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2156 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2157
2158 if (!force_on)
2159 return 0;
2160
c6ddc5f3
CW		 2161 err = intel_wait_for_register(dev_priv,
2162 VLV_GTLC_SURVIVABILITY_REG,
2163 VLV_GFX_CLK_STATUS_BIT,
2164 VLV_GFX_CLK_STATUS_BIT,
2165 20);
650ad970
ID		 2166 if (err)
2167 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2168 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2169
2170 return err;
650ad970
ID		 2171}
2172
ddeea5b0
ID		 2173static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2174{
2175 u32 val;
2176 int err = 0;
2177
2178 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2179 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2180 if (allow)
2181 val |= VLV_GTLC_ALLOWWAKEREQ;
2182 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2183 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2184
b2736695
CW		 2185 err = intel_wait_for_register(dev_priv,
2186 VLV_GTLC_PW_STATUS,
2187 VLV_GTLC_ALLOWWAKEACK,
2188 allow,
2189 1);
ddeea5b0
ID		 2190 if (err)
2191 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2192
ddeea5b0 2193 return err;
ddeea5b0
ID		 2194}
2195
2196static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2197 bool wait_for_on)
2198{
2199 u32 mask;
2200 u32 val;
2201 int err;
2202
2203 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2204 val = wait_for_on ? mask : 0;
41ce405e 2205 if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
ddeea5b0
ID		 2206 return 0;
2207
2208 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
87ad3212
JN		 2209 onoff(wait_for_on),
2210 I915_READ(VLV_GTLC_PW_STATUS));
ddeea5b0
ID		 2211
2212 /*
2213 * RC6 transitioning can be delayed up to 2 msec (see
2214 * valleyview_enable_rps), use 3 msec for safety.
2215 */
41ce405e
CW		 2216 err = intel_wait_for_register(dev_priv,
2217 VLV_GTLC_PW_STATUS, mask, val,
2218 3);
ddeea5b0
ID		 2219 if (err)
2220 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2221 onoff(wait_for_on));
ddeea5b0
ID		 2222
2223 return err;
ddeea5b0
ID		 2224}
2225
2226static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2227{
2228 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2229 return;
2230
6fa283b0 2231 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2232 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2233}
2234
ebc32824 2235static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2236{
2237 u32 mask;
2238 int err;
2239
2240 /*
2241 * Bspec defines the following GT well on flags as debug only, so
2242 * don't treat them as hard failures.
2243 */
2244 (void)vlv_wait_for_gt_wells(dev_priv, false);
2245
2246 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2247 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2248
2249 vlv_check_no_gt_access(dev_priv);
2250
2251 err = vlv_force_gfx_clock(dev_priv, true);
2252 if (err)
2253 goto err1;
2254
2255 err = vlv_allow_gt_wake(dev_priv, false);
2256 if (err)
2257 goto err2;
98711167 2258
2d1fe073 2259 if (!IS_CHERRYVIEW(dev_priv))
98711167 2260 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2261
2262 err = vlv_force_gfx_clock(dev_priv, false);
2263 if (err)
2264 goto err2;
2265
2266 return 0;
2267
2268err2:
2269 /* For safety always re-enable waking and disable gfx clock forcing */
2270 vlv_allow_gt_wake(dev_priv, true);
2271err1:
2272 vlv_force_gfx_clock(dev_priv, false);
2273
2274 return err;
2275}
2276
016970be
SK		 2277static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2278 bool rpm_resume)
ddeea5b0 2279{
91c8a326 2280 struct drm_device *dev = &dev_priv->drm;
ddeea5b0
ID		 2281 int err;
2282 int ret;
2283
2284 /*
2285 * If any of the steps fail just try to continue, that's the best we
2286 * can do at this point. Return the first error code (which will also
2287 * leave RPM permanently disabled).
2288 */
2289 ret = vlv_force_gfx_clock(dev_priv, true);
2290
2d1fe073 2291 if (!IS_CHERRYVIEW(dev_priv))
98711167 2292 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2293
2294 err = vlv_allow_gt_wake(dev_priv, true);
2295 if (!ret)
2296 ret = err;
2297
2298 err = vlv_force_gfx_clock(dev_priv, false);
2299 if (!ret)
2300 ret = err;
2301
2302 vlv_check_no_gt_access(dev_priv);
2303
016970be
SK		 2304 if (rpm_resume) {
2305 intel_init_clock_gating(dev);
2306 i915_gem_restore_fences(dev);
2307 }
ddeea5b0
ID		 2308
2309 return ret;
2310}
2311
97bea207 2312static int intel_runtime_suspend(struct device *device)
8a187455
PZ		 2313{
2314 struct pci_dev *pdev = to_pci_dev(device);
2315 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2316 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2317 int ret;
8a187455 2318
dc97997a 2319 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2320 return -ENODEV;
2321
604effb7
ID		 2322 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2323 return -ENODEV;
2324
8a187455
PZ		 2325 DRM_DEBUG_KMS("Suspending device\n");
2326
d6102977
ID		 2327 /*
2328 * We could deadlock here in case another thread holding struct_mutex
2329 * calls RPM suspend concurrently, since the RPM suspend will wait
2330 * first for this RPM suspend to finish. In this case the concurrent
2331 * RPM resume will be followed by its RPM suspend counterpart. Still
2332 * for consistency return -EAGAIN, which will reschedule this suspend.
2333 */
2334 if (!mutex_trylock(&dev->struct_mutex)) {
2335 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2336 /*
2337 * Bump the expiration timestamp, otherwise the suspend won't
2338 * be rescheduled.
2339 */
2340 pm_runtime_mark_last_busy(device);
2341
2342 return -EAGAIN;
2343 }
1f814dac
ID		 2344
2345 disable_rpm_wakeref_asserts(dev_priv);
2346
d6102977
ID		 2347 /*
2348 * We are safe here against re-faults, since the fault handler takes
2349 * an RPM reference.
2350 */
2351 i915_gem_release_all_mmaps(dev_priv);
2352 mutex_unlock(&dev->struct_mutex);
2353
a1c41994
AD		 2354 intel_guc_suspend(dev);
2355
2eb5252e 2356 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2357
507e126e
ID		 2358 ret = 0;
2359 if (IS_BROXTON(dev_priv)) {
2360 bxt_display_core_uninit(dev_priv);
2361 bxt_enable_dc9(dev_priv);
2362 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2363 hsw_enable_pc8(dev_priv);
2364 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2365 ret = vlv_suspend_complete(dev_priv);
2366 }
2367
0ab9cfeb
ID		 2368 if (ret) {
2369 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2370 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2371
1f814dac
ID		 2372 enable_rpm_wakeref_asserts(dev_priv);
2373
0ab9cfeb
ID		 2374 return ret;
2375 }
a8a8bd54 2376
dc97997a 2377 intel_uncore_forcewake_reset(dev_priv, false);
1f814dac
ID		 2378
2379 enable_rpm_wakeref_asserts(dev_priv);
2380 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2381
bc3b9346 2382 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2383 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2384
8a187455 2385 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2386
2387 /*
c8a0bd42
PZ		 2388 * FIXME: We really should find a document that references the arguments
2389 * used below!
1fb2362b 2390 */
6f9f4b7a 2391 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2392 /*
2393 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2394 * being detected, and the call we do at intel_runtime_resume()
2395 * won't be able to restore them. Since PCI_D3hot matches the
2396 * actual specification and appears to be working, use it.
2397 */
6f9f4b7a 2398 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2399 } else {
c8a0bd42
PZ		 2400 /*
2401 * current versions of firmware which depend on this opregion
2402 * notification have repurposed the D1 definition to mean
2403 * "runtime suspended" vs. what you would normally expect (D3)
2404 * to distinguish it from notifications that might be sent via
2405 * the suspend path.
2406 */
6f9f4b7a 2407 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2408 }
8a187455 2409
59bad947 2410 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2411
a8a8bd54 2412 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2413 return 0;
2414}
2415
97bea207 2416static int intel_runtime_resume(struct device *device)
8a187455
PZ		 2417{
2418 struct pci_dev *pdev = to_pci_dev(device);
2419 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2420 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2421 int ret = 0;
8a187455 2422
604effb7
ID		 2423 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2424 return -ENODEV;
8a187455
PZ		 2425
2426 DRM_DEBUG_KMS("Resuming device\n");
2427
1f814dac
ID		 2428 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2429 disable_rpm_wakeref_asserts(dev_priv);
2430
6f9f4b7a 2431 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2432 dev_priv->pm.suspended = false;
55ec45c2
MK		 2433 if (intel_uncore_unclaimed_mmio(dev_priv))
2434 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2435
a1c41994
AD		 2436 intel_guc_resume(dev);
2437
1a5df187
PZ		 2438 if (IS_GEN6(dev_priv))
2439 intel_init_pch_refclk(dev);
31335cec 2440
507e126e
ID		 2441 if (IS_BROXTON(dev)) {
2442 bxt_disable_dc9(dev_priv);
2443 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2444 if (dev_priv->csr.dmc_payload &&
2445 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2446 gen9_enable_dc5(dev_priv);
507e126e 2447 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2448 hsw_disable_pc8(dev_priv);
507e126e 2449 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2450 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2451 }
1a5df187 2452
0ab9cfeb
ID		 2453 /*
2454 * No point of rolling back things in case of an error, as the best
2455 * we can do is to hope that things will still work (and disable RPM).
2456 */
92b806d3 2457 i915_gem_init_swizzling(dev);
dc97997a 2458 gen6_update_ring_freq(dev_priv);
92b806d3 2459
b963291c 2460 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2461
2462 /*
2463 * On VLV/CHV display interrupts are part of the display
2464 * power well, so hpd is reinitialized from there. For
2465 * everyone else do it here.
2466 */
666a4537 2467 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2468 intel_hpd_init(dev_priv);
2469
1f814dac
ID		 2470 enable_rpm_wakeref_asserts(dev_priv);
2471
0ab9cfeb
ID		 2472 if (ret)
2473 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2474 else
2475 DRM_DEBUG_KMS("Device resumed\n");
2476
2477 return ret;
8a187455
PZ		 2478}
2479
42f5551d 2480const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2481 /*
2482 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2483 * PMSG_RESUME]
2484 */
0206e353 2485 .suspend = i915_pm_suspend,
76c4b250
ID		 2486 .suspend_late = i915_pm_suspend_late,
2487 .resume_early = i915_pm_resume_early,
0206e353 2488 .resume = i915_pm_resume,
5545dbbf
ID		 2489
2490 /*
2491 * S4 event handlers
2492 * @freeze, @freeze_late : called (1) before creating the
2493 * hibernation image [PMSG_FREEZE] and
2494 * (2) after rebooting, before restoring
2495 * the image [PMSG_QUIESCE]
2496 * @thaw, @thaw_early : called (1) after creating the hibernation
2497 * image, before writing it [PMSG_THAW]
2498 * and (2) after failing to create or
2499 * restore the image [PMSG_RECOVER]
2500 * @poweroff, @poweroff_late: called after writing the hibernation
2501 * image, before rebooting [PMSG_HIBERNATE]
2502 * @restore, @restore_early : called after rebooting and restoring the
2503 * hibernation image [PMSG_RESTORE]
2504 */
1f19ac2a
CW		 2505 .freeze = i915_pm_freeze,
2506 .freeze_late = i915_pm_freeze_late,
2507 .thaw_early = i915_pm_thaw_early,
2508 .thaw = i915_pm_thaw,
36d61e67 2509 .poweroff = i915_pm_suspend,
ab3be73f 2510 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2511 .restore_early = i915_pm_restore_early,
2512 .restore = i915_pm_restore,
5545dbbf
ID		 2513
2514 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2515 .runtime_suspend = intel_runtime_suspend,
2516 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2517};
2518
78b68556 2519static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2520 .fault = i915_gem_fault,
ab00b3e5
JB		 2521 .open = drm_gem_vm_open,
2522 .close = drm_gem_vm_close,
de151cf6
JB		 2523};
2524
e08e96de
AV		 2525static const struct file_operations i915_driver_fops = {
2526 .owner = THIS_MODULE,
2527 .open = drm_open,
2528 .release = drm_release,
2529 .unlocked_ioctl = drm_ioctl,
2530 .mmap = drm_gem_mmap,
2531 .poll = drm_poll,
e08e96de
AV		 2532 .read = drm_read,
2533#ifdef CONFIG_COMPAT
2534 .compat_ioctl = i915_compat_ioctl,
2535#endif
2536 .llseek = noop_llseek,
2537};
2538
0673ad47
CW		 2539static int
2540i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2541 struct drm_file *file)
2542{
2543 return -ENODEV;
2544}
2545
2546static const struct drm_ioctl_desc i915_ioctls[] = {
2547 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2548 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2549 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2550 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2551 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2552 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2553 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2554 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2555 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2556 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2557 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2558 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2559 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2560 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2561 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2562 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2563 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2564 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2565 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2566 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2567 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2568 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2569 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2570 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2571 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2572 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2573 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2574 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2575 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2576 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2577 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2578 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2579 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2580 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2581 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2582 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2583 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2584 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2585 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2586 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2587 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2588 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2589 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2590 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2591 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2592 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2593 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2594 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2595 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2596 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2597 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2598 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2599};
2600
1da177e4 2601static struct drm_driver driver = {
0c54781b
MW		 2602 /* Don't use MTRRs here; the Xserver or userspace app should
2603 * deal with them for Intel hardware.
792d2b9a 2604 */
673a394b 2605 .driver_features =
10ba5012 2606 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1751fcf9 2607 DRIVER_RENDER | DRIVER_MODESET,
673a394b 2608 .open = i915_driver_open,
22eae947
DA		 2609 .lastclose = i915_driver_lastclose,
2610 .preclose = i915_driver_preclose,
673a394b 2611 .postclose = i915_driver_postclose,
915b4d11 2612 .set_busid = drm_pci_set_busid,
d8e29209 2613
673a394b 2614 .gem_free_object = i915_gem_free_object,
de151cf6 2615 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2616
2617 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2618 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2619 .gem_prime_export = i915_gem_prime_export,
2620 .gem_prime_import = i915_gem_prime_import,
2621
ff72145b 2622 .dumb_create = i915_gem_dumb_create,
da6b51d0 2623 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 2624 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 2625 .ioctls = i915_ioctls,
0673ad47 2626 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2627 .fops = &i915_driver_fops,
22eae947
DA		 2628 .name = DRIVER_NAME,
2629 .desc = DRIVER_DESC,
2630 .date = DRIVER_DATE,
2631 .major = DRIVER_MAJOR,
2632 .minor = DRIVER_MINOR,
2633 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2634};
ubuntu-bionic-kernel mirror