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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
e5747e3a | 31 | #include <linux/acpi.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/i915_drm.h> | |
1da177e4 | 34 | #include "i915_drv.h" |
990bbdad | 35 | #include "i915_trace.h" |
f49f0586 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
79e53945 | 38 | #include <linux/console.h> |
e0cd3608 | 39 | #include <linux/module.h> |
d6102977 | 40 | #include <linux/pm_runtime.h> |
760285e7 | 41 | #include <drm/drm_crtc_helper.h> |
79e53945 | 42 | |
112b715e KH |
43 | static struct drm_driver driver; |
44 | ||
a57c774a AK |
45 | #define GEN_DEFAULT_PIPEOFFSETS \ |
46 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
47 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
48 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
49 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
a57c774a AK |
50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
51 | ||
84fd4f4e RB |
52 | #define GEN_CHV_PIPEOFFSETS \ |
53 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
54 | CHV_PIPE_C_OFFSET }, \ | |
55 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
56 | CHV_TRANSCODER_C_OFFSET, }, \ | |
84fd4f4e RB |
57 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
58 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 59 | |
5efb3e28 VS |
60 | #define CURSOR_OFFSETS \ |
61 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
62 | ||
63 | #define IVB_CURSOR_OFFSETS \ | |
64 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
65 | ||
9a7e8492 | 66 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 67 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 68 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 69 | .ring_mask = RENDER_RING, |
a57c774a | 70 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 71 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
72 | }; |
73 | ||
9a7e8492 | 74 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 75 | .gen = 2, .num_pipes = 1, |
31578148 | 76 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 77 | .ring_mask = RENDER_RING, |
a57c774a | 78 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 79 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
80 | }; |
81 | ||
9a7e8492 | 82 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 83 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 84 | .cursor_needs_physical = 1, |
31578148 | 85 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 86 | .has_fbc = 1, |
73ae478c | 87 | .ring_mask = RENDER_RING, |
a57c774a | 88 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 89 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
90 | }; |
91 | ||
9a7e8492 | 92 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 93 | .gen = 2, .num_pipes = 1, |
31578148 | 94 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 95 | .ring_mask = RENDER_RING, |
a57c774a | 96 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 97 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
98 | }; |
99 | ||
9a7e8492 | 100 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 101 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 102 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 103 | .ring_mask = RENDER_RING, |
a57c774a | 104 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 105 | CURSOR_OFFSETS, |
cfdf1fa2 | 106 | }; |
9a7e8492 | 107 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 108 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 109 | .cursor_needs_physical = 1, |
31578148 | 110 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 111 | .supports_tv = 1, |
fd70d52a | 112 | .has_fbc = 1, |
73ae478c | 113 | .ring_mask = RENDER_RING, |
a57c774a | 114 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 115 | CURSOR_OFFSETS, |
cfdf1fa2 | 116 | }; |
9a7e8492 | 117 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 118 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 119 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 120 | .ring_mask = RENDER_RING, |
a57c774a | 121 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 122 | CURSOR_OFFSETS, |
cfdf1fa2 | 123 | }; |
9a7e8492 | 124 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 125 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 126 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 127 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 128 | .supports_tv = 1, |
fd70d52a | 129 | .has_fbc = 1, |
73ae478c | 130 | .ring_mask = RENDER_RING, |
a57c774a | 131 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 132 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
133 | }; |
134 | ||
9a7e8492 | 135 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 136 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 137 | .has_hotplug = 1, |
31578148 | 138 | .has_overlay = 1, |
73ae478c | 139 | .ring_mask = RENDER_RING, |
a57c774a | 140 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 141 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
142 | }; |
143 | ||
9a7e8492 | 144 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 145 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 146 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 147 | .has_overlay = 1, |
a6c45cf0 | 148 | .supports_tv = 1, |
73ae478c | 149 | .ring_mask = RENDER_RING, |
a57c774a | 150 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 151 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
152 | }; |
153 | ||
9a7e8492 | 154 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 155 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 156 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 157 | .has_overlay = 1, |
73ae478c | 158 | .ring_mask = RENDER_RING, |
a57c774a | 159 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 160 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
161 | }; |
162 | ||
9a7e8492 | 163 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 164 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 165 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 166 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 167 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 168 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
169 | }; |
170 | ||
9a7e8492 | 171 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 172 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 173 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 174 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 175 | .supports_tv = 1, |
73ae478c | 176 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 177 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 178 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
179 | }; |
180 | ||
9a7e8492 | 181 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 182 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 183 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 184 | .has_overlay = 1, |
a57c774a | 185 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 186 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
187 | }; |
188 | ||
9a7e8492 | 189 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 190 | .gen = 5, .num_pipes = 2, |
5a117db7 | 191 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 192 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 193 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 194 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
195 | }; |
196 | ||
9a7e8492 | 197 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 198 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 199 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 200 | .has_fbc = 1, |
73ae478c | 201 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 202 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 203 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
204 | }; |
205 | ||
9a7e8492 | 206 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 207 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 208 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 209 | .has_fbc = 1, |
73ae478c | 210 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 211 | .has_llc = 1, |
a57c774a | 212 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 213 | CURSOR_OFFSETS, |
f6e450a6 EA |
214 | }; |
215 | ||
9a7e8492 | 216 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 217 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 218 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 219 | .has_fbc = 1, |
73ae478c | 220 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 221 | .has_llc = 1, |
a57c774a | 222 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 223 | CURSOR_OFFSETS, |
a13e4093 EA |
224 | }; |
225 | ||
219f4fdb BW |
226 | #define GEN7_FEATURES \ |
227 | .gen = 7, .num_pipes = 3, \ | |
228 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 229 | .has_fbc = 1, \ |
73ae478c | 230 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 231 | .has_llc = 1 |
219f4fdb | 232 | |
c76b615c | 233 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
234 | GEN7_FEATURES, |
235 | .is_ivybridge = 1, | |
a57c774a | 236 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 237 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
238 | }; |
239 | ||
240 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
241 | GEN7_FEATURES, |
242 | .is_ivybridge = 1, | |
243 | .is_mobile = 1, | |
a57c774a | 244 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 245 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
246 | }; |
247 | ||
999bcdea BW |
248 | static const struct intel_device_info intel_ivybridge_q_info = { |
249 | GEN7_FEATURES, | |
250 | .is_ivybridge = 1, | |
251 | .num_pipes = 0, /* legal, last one wins */ | |
a57c774a | 252 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 253 | IVB_CURSOR_OFFSETS, |
999bcdea BW |
254 | }; |
255 | ||
70a3eb7a | 256 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
257 | GEN7_FEATURES, |
258 | .is_mobile = 1, | |
259 | .num_pipes = 2, | |
70a3eb7a | 260 | .is_valleyview = 1, |
fba5d532 | 261 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 262 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 263 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 264 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 265 | CURSOR_OFFSETS, |
70a3eb7a JB |
266 | }; |
267 | ||
268 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
269 | GEN7_FEATURES, |
270 | .num_pipes = 2, | |
70a3eb7a | 271 | .is_valleyview = 1, |
fba5d532 | 272 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 273 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 274 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 275 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 276 | CURSOR_OFFSETS, |
70a3eb7a JB |
277 | }; |
278 | ||
4cae9ae0 | 279 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
280 | GEN7_FEATURES, |
281 | .is_haswell = 1, | |
dd93be58 | 282 | .has_ddi = 1, |
30568c45 | 283 | .has_fpga_dbg = 1, |
73ae478c | 284 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 285 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 286 | IVB_CURSOR_OFFSETS, |
4cae9ae0 ED |
287 | }; |
288 | ||
289 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
290 | GEN7_FEATURES, |
291 | .is_haswell = 1, | |
292 | .is_mobile = 1, | |
dd93be58 | 293 | .has_ddi = 1, |
30568c45 | 294 | .has_fpga_dbg = 1, |
73ae478c | 295 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 296 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 297 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
298 | }; |
299 | ||
4d4dead6 | 300 | static const struct intel_device_info intel_broadwell_d_info = { |
4b30553d | 301 | .gen = 8, .num_pipes = 3, |
4d4dead6 BW |
302 | .need_gfx_hws = 1, .has_hotplug = 1, |
303 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
304 | .has_llc = 1, | |
305 | .has_ddi = 1, | |
66bc2cab | 306 | .has_fpga_dbg = 1, |
8f94d24b | 307 | .has_fbc = 1, |
a57c774a | 308 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 309 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
310 | }; |
311 | ||
312 | static const struct intel_device_info intel_broadwell_m_info = { | |
4b30553d | 313 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
4d4dead6 BW |
314 | .need_gfx_hws = 1, .has_hotplug = 1, |
315 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
316 | .has_llc = 1, | |
317 | .has_ddi = 1, | |
66bc2cab | 318 | .has_fpga_dbg = 1, |
8f94d24b | 319 | .has_fbc = 1, |
a57c774a | 320 | GEN_DEFAULT_PIPEOFFSETS, |
15d24aa5 | 321 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
322 | }; |
323 | ||
fd3c269f ZY |
324 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
325 | .gen = 8, .num_pipes = 3, | |
326 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 327 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
328 | .has_llc = 1, |
329 | .has_ddi = 1, | |
66bc2cab | 330 | .has_fpga_dbg = 1, |
fd3c269f ZY |
331 | .has_fbc = 1, |
332 | GEN_DEFAULT_PIPEOFFSETS, | |
15d24aa5 | 333 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
334 | }; |
335 | ||
336 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
337 | .gen = 8, .is_mobile = 1, .num_pipes = 3, | |
338 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 339 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
340 | .has_llc = 1, |
341 | .has_ddi = 1, | |
66bc2cab | 342 | .has_fpga_dbg = 1, |
fd3c269f ZY |
343 | .has_fbc = 1, |
344 | GEN_DEFAULT_PIPEOFFSETS, | |
5efb3e28 | 345 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
346 | }; |
347 | ||
7d87a7f7 | 348 | static const struct intel_device_info intel_cherryview_info = { |
07fddb14 | 349 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
350 | .need_gfx_hws = 1, .has_hotplug = 1, |
351 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
352 | .is_valleyview = 1, | |
353 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
84fd4f4e | 354 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 355 | CURSOR_OFFSETS, |
7d87a7f7 VS |
356 | }; |
357 | ||
72bbf0af | 358 | static const struct intel_device_info intel_skylake_info = { |
7201c0b3 | 359 | .is_skylake = 1, |
72bbf0af DL |
360 | .gen = 9, .num_pipes = 3, |
361 | .need_gfx_hws = 1, .has_hotplug = 1, | |
362 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
363 | .has_llc = 1, | |
364 | .has_ddi = 1, | |
6c908bf4 | 365 | .has_fpga_dbg = 1, |
043efb11 | 366 | .has_fbc = 1, |
72bbf0af DL |
367 | GEN_DEFAULT_PIPEOFFSETS, |
368 | IVB_CURSOR_OFFSETS, | |
369 | }; | |
370 | ||
719388e1 | 371 | static const struct intel_device_info intel_skylake_gt3_info = { |
719388e1 DL |
372 | .is_skylake = 1, |
373 | .gen = 9, .num_pipes = 3, | |
374 | .need_gfx_hws = 1, .has_hotplug = 1, | |
375 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, | |
376 | .has_llc = 1, | |
377 | .has_ddi = 1, | |
6c908bf4 | 378 | .has_fpga_dbg = 1, |
719388e1 DL |
379 | .has_fbc = 1, |
380 | GEN_DEFAULT_PIPEOFFSETS, | |
381 | IVB_CURSOR_OFFSETS, | |
382 | }; | |
383 | ||
1347f5b4 DL |
384 | static const struct intel_device_info intel_broxton_info = { |
385 | .is_preliminary = 1, | |
386 | .gen = 9, | |
387 | .need_gfx_hws = 1, .has_hotplug = 1, | |
388 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
389 | .num_pipes = 3, | |
390 | .has_ddi = 1, | |
6c908bf4 | 391 | .has_fpga_dbg = 1, |
ce89db2e | 392 | .has_fbc = 1, |
1347f5b4 DL |
393 | GEN_DEFAULT_PIPEOFFSETS, |
394 | IVB_CURSOR_OFFSETS, | |
395 | }; | |
396 | ||
a0a18075 JB |
397 | /* |
398 | * Make sure any device matches here are from most specific to most | |
399 | * general. For example, since the Quanta match is based on the subsystem | |
400 | * and subvendor IDs, we need it to come before the more general IVB | |
401 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
402 | */ | |
3cb27f38 JN |
403 | static const struct pci_device_id pciidlist[] = { |
404 | INTEL_I830_IDS(&intel_i830_info), | |
405 | INTEL_I845G_IDS(&intel_845g_info), | |
406 | INTEL_I85X_IDS(&intel_i85x_info), | |
407 | INTEL_I865G_IDS(&intel_i865g_info), | |
408 | INTEL_I915G_IDS(&intel_i915g_info), | |
409 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
410 | INTEL_I945G_IDS(&intel_i945g_info), | |
411 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
412 | INTEL_I965G_IDS(&intel_i965g_info), | |
413 | INTEL_G33_IDS(&intel_g33_info), | |
414 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
415 | INTEL_GM45_IDS(&intel_gm45_info), | |
416 | INTEL_G45_IDS(&intel_g45_info), | |
417 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
418 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
419 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
420 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), | |
421 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), | |
422 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ | |
423 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), | |
424 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), | |
425 | INTEL_HSW_D_IDS(&intel_haswell_d_info), | |
426 | INTEL_HSW_M_IDS(&intel_haswell_m_info), | |
427 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), | |
428 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), | |
429 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), | |
430 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), | |
431 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), | |
432 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), | |
433 | INTEL_CHV_IDS(&intel_cherryview_info), | |
434 | INTEL_SKL_GT1_IDS(&intel_skylake_info), | |
435 | INTEL_SKL_GT2_IDS(&intel_skylake_info), | |
436 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), | |
437 | INTEL_BXT_IDS(&intel_broxton_info), | |
49ae35f2 | 438 | {0, 0, 0} |
1da177e4 LT |
439 | }; |
440 | ||
79e53945 | 441 | MODULE_DEVICE_TABLE(pci, pciidlist); |
79e53945 | 442 | |
30c964a6 RB |
443 | static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) |
444 | { | |
445 | enum intel_pch ret = PCH_NOP; | |
446 | ||
447 | /* | |
448 | * In a virtualized passthrough environment we can be in a | |
449 | * setup where the ISA bridge is not able to be passed through. | |
450 | * In this case, a south bridge can be emulated and we have to | |
451 | * make an educated guess as to which PCH is really there. | |
452 | */ | |
453 | ||
454 | if (IS_GEN5(dev)) { | |
455 | ret = PCH_IBX; | |
456 | DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); | |
457 | } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { | |
458 | ret = PCH_CPT; | |
459 | DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); | |
460 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
461 | ret = PCH_LPT; | |
462 | DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); | |
463 | } else if (IS_SKYLAKE(dev)) { | |
464 | ret = PCH_SPT; | |
465 | DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); | |
466 | } | |
467 | ||
468 | return ret; | |
469 | } | |
470 | ||
0206e353 | 471 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
472 | { |
473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 474 | struct pci_dev *pch = NULL; |
3bad0781 | 475 | |
ce1bb329 BW |
476 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
477 | * (which really amounts to a PCH but no South Display). | |
478 | */ | |
479 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
480 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
481 | return; |
482 | } | |
483 | ||
3bad0781 ZW |
484 | /* |
485 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
486 | * make graphics device passthrough work easy for VMM, that only | |
487 | * need to expose ISA bridge to let driver know the real hardware | |
488 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
489 | * |
490 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
491 | * ISA bridge in the system. To work reliably, we should scan trhough | |
492 | * all the ISA bridge devices and check for the first match, instead | |
493 | * of only checking the first one. | |
3bad0781 | 494 | */ |
bcdb72ac | 495 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 496 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 497 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 498 | dev_priv->pch_id = id; |
3bad0781 | 499 | |
90711d50 JB |
500 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
501 | dev_priv->pch_type = PCH_IBX; | |
502 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 503 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 504 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
505 | dev_priv->pch_type = PCH_CPT; |
506 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 507 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
508 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
509 | /* PantherPoint is CPT compatible */ | |
510 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 511 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 512 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
513 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
514 | dev_priv->pch_type = PCH_LPT; | |
515 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
a35cc9d0 RV |
516 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
517 | WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); | |
e76e0634 BW |
518 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
519 | dev_priv->pch_type = PCH_LPT; | |
520 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
a35cc9d0 RV |
521 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
522 | WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); | |
e7e7ea20 S |
523 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
524 | dev_priv->pch_type = PCH_SPT; | |
525 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
526 | WARN_ON(!IS_SKYLAKE(dev)); | |
e7e7ea20 S |
527 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
528 | dev_priv->pch_type = PCH_SPT; | |
529 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
530 | WARN_ON(!IS_SKYLAKE(dev)); | |
30c964a6 RB |
531 | } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) { |
532 | dev_priv->pch_type = intel_virt_detect_pch(dev); | |
bcdb72ac ID |
533 | } else |
534 | continue; | |
535 | ||
6a9c4b35 | 536 | break; |
3bad0781 | 537 | } |
3bad0781 | 538 | } |
6a9c4b35 | 539 | if (!pch) |
bcdb72ac ID |
540 | DRM_DEBUG_KMS("No PCH found.\n"); |
541 | ||
542 | pci_dev_put(pch); | |
3bad0781 ZW |
543 | } |
544 | ||
2911a35b BW |
545 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
546 | { | |
547 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 548 | return false; |
2911a35b | 549 | |
d330a953 JN |
550 | if (i915.semaphores >= 0) |
551 | return i915.semaphores; | |
2911a35b | 552 | |
71386ef9 OM |
553 | /* TODO: make semaphores and Execlists play nicely together */ |
554 | if (i915.enable_execlists) | |
555 | return false; | |
556 | ||
be71eabe RV |
557 | /* Until we get further testing... */ |
558 | if (IS_GEN8(dev)) | |
559 | return false; | |
560 | ||
59de3295 | 561 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 562 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
563 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
564 | return false; | |
565 | #endif | |
2911a35b | 566 | |
a08acaf2 | 567 | return true; |
2911a35b BW |
568 | } |
569 | ||
eb805623 DV |
570 | void i915_firmware_load_error_print(const char *fw_path, int err) |
571 | { | |
572 | DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err); | |
573 | ||
574 | /* | |
575 | * If the reason is not known assume -ENOENT since that's the most | |
576 | * usual failure mode. | |
577 | */ | |
578 | if (!err) | |
579 | err = -ENOENT; | |
580 | ||
581 | if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT)) | |
582 | return; | |
583 | ||
584 | DRM_ERROR( | |
585 | "The driver is built-in, so to load the firmware you need to\n" | |
586 | "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n" | |
587 | "in your initrd/initramfs image.\n"); | |
588 | } | |
589 | ||
07f9cd0b ID |
590 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
591 | { | |
592 | struct drm_device *dev = dev_priv->dev; | |
593 | struct drm_encoder *encoder; | |
594 | ||
595 | drm_modeset_lock_all(dev); | |
596 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
597 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
598 | ||
599 | if (intel_encoder->suspend) | |
600 | intel_encoder->suspend(intel_encoder); | |
601 | } | |
602 | drm_modeset_unlock_all(dev); | |
603 | } | |
604 | ||
ebc32824 | 605 | static int intel_suspend_complete(struct drm_i915_private *dev_priv); |
1a5df187 PZ |
606 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
607 | bool rpm_resume); | |
f75a1985 | 608 | static int skl_resume_prepare(struct drm_i915_private *dev_priv); |
a9a6b73a | 609 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv); |
f75a1985 | 610 | |
ebc32824 | 611 | |
5e365c39 | 612 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 613 | { |
61caf87c | 614 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5747e3a | 615 | pci_power_t opregion_target_state; |
d5818938 | 616 | int error; |
61caf87c | 617 | |
b8efb17b ZR |
618 | /* ignore lid events during suspend */ |
619 | mutex_lock(&dev_priv->modeset_restore_lock); | |
620 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
621 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
622 | ||
c67a470b PZ |
623 | /* We do a lot of poking in a lot of registers, make sure they work |
624 | * properly. */ | |
da7e29bd | 625 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 626 | |
5bcf719b DA |
627 | drm_kms_helper_poll_disable(dev); |
628 | ||
ba8bbcf6 | 629 | pci_save_state(dev->pdev); |
ba8bbcf6 | 630 | |
d5818938 DV |
631 | error = i915_gem_suspend(dev); |
632 | if (error) { | |
633 | dev_err(&dev->pdev->dev, | |
634 | "GEM idle failed, resume might fail\n"); | |
635 | return error; | |
636 | } | |
db1b76ca | 637 | |
a1c41994 AD |
638 | intel_guc_suspend(dev); |
639 | ||
d5818938 | 640 | intel_suspend_gt_powersave(dev); |
a261b246 | 641 | |
d5818938 DV |
642 | /* |
643 | * Disable CRTCs directly since we want to preserve sw state | |
644 | * for _thaw. Also, power gate the CRTC power wells. | |
645 | */ | |
646 | drm_modeset_lock_all(dev); | |
6b72d486 | 647 | intel_display_suspend(dev); |
d5818938 | 648 | drm_modeset_unlock_all(dev); |
2eb5252e | 649 | |
d5818938 | 650 | intel_dp_mst_suspend(dev); |
7d708ee4 | 651 | |
d5818938 DV |
652 | intel_runtime_pm_disable_interrupts(dev_priv); |
653 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 654 | |
d5818938 | 655 | intel_suspend_encoders(dev_priv); |
0e32b39c | 656 | |
d5818938 | 657 | intel_suspend_hw(dev); |
5669fcac | 658 | |
828c7908 BW |
659 | i915_gem_suspend_gtt_mappings(dev); |
660 | ||
9e06dd39 JB |
661 | i915_save_state(dev); |
662 | ||
95fa2eee ID |
663 | opregion_target_state = PCI_D3cold; |
664 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
665 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
e5747e3a | 666 | opregion_target_state = PCI_D1; |
95fa2eee | 667 | #endif |
e5747e3a JB |
668 | intel_opregion_notify_adapter(dev, opregion_target_state); |
669 | ||
156c7ca0 | 670 | intel_uncore_forcewake_reset(dev, false); |
44834a67 | 671 | intel_opregion_fini(dev); |
8ee1c3db | 672 | |
82e3b8c1 | 673 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 674 | |
62d5d69b MK |
675 | dev_priv->suspend_count++; |
676 | ||
85e90679 KCA |
677 | intel_display_set_init_power(dev_priv, false); |
678 | ||
61caf87c | 679 | return 0; |
84b79f8d RW |
680 | } |
681 | ||
ab3be73f | 682 | static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) |
c3c09c95 ID |
683 | { |
684 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
685 | int ret; | |
686 | ||
687 | ret = intel_suspend_complete(dev_priv); | |
688 | ||
689 | if (ret) { | |
690 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
691 | ||
692 | return ret; | |
693 | } | |
694 | ||
695 | pci_disable_device(drm_dev->pdev); | |
ab3be73f | 696 | /* |
54875571 | 697 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
698 | * the device even though it's already in D3 and hang the machine. So |
699 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
700 | * power down the device properly. The issue was seen on multiple old |
701 | * GENs with different BIOS vendors, so having an explicit blacklist | |
702 | * is inpractical; apply the workaround on everything pre GEN6. The | |
703 | * platforms where the issue was seen: | |
704 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
705 | * Fujitsu FSC S7110 | |
706 | * Acer Aspire 1830T | |
ab3be73f | 707 | */ |
54875571 | 708 | if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) |
ab3be73f | 709 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); |
c3c09c95 ID |
710 | |
711 | return 0; | |
712 | } | |
713 | ||
1751fcf9 | 714 | int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
715 | { |
716 | int error; | |
717 | ||
718 | if (!dev || !dev->dev_private) { | |
719 | DRM_ERROR("dev: %p\n", dev); | |
720 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
721 | return -ENODEV; | |
722 | } | |
723 | ||
0b14cbd2 ID |
724 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
725 | state.event != PM_EVENT_FREEZE)) | |
726 | return -EINVAL; | |
5bcf719b DA |
727 | |
728 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
729 | return 0; | |
6eecba33 | 730 | |
5e365c39 | 731 | error = i915_drm_suspend(dev); |
84b79f8d RW |
732 | if (error) |
733 | return error; | |
734 | ||
ab3be73f | 735 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
736 | } |
737 | ||
5e365c39 | 738 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 ID |
739 | { |
740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9d49c0ef | 741 | |
d5818938 DV |
742 | mutex_lock(&dev->struct_mutex); |
743 | i915_gem_restore_gtt_mappings(dev); | |
744 | mutex_unlock(&dev->struct_mutex); | |
9d49c0ef | 745 | |
61caf87c | 746 | i915_restore_state(dev); |
44834a67 | 747 | intel_opregion_setup(dev); |
61caf87c | 748 | |
d5818938 DV |
749 | intel_init_pch_refclk(dev); |
750 | drm_mode_config_reset(dev); | |
1833b134 | 751 | |
364aece0 PA |
752 | /* |
753 | * Interrupts have to be enabled before any batches are run. If not the | |
754 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
755 | * update/restore the context. | |
756 | * | |
757 | * Modeset enabling in intel_modeset_init_hw() also needs working | |
758 | * interrupts. | |
759 | */ | |
760 | intel_runtime_pm_enable_interrupts(dev_priv); | |
761 | ||
d5818938 DV |
762 | mutex_lock(&dev->struct_mutex); |
763 | if (i915_gem_init_hw(dev)) { | |
764 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
805de8f4 | 765 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
d5818938 DV |
766 | } |
767 | mutex_unlock(&dev->struct_mutex); | |
226485e9 | 768 | |
a1c41994 AD |
769 | intel_guc_resume(dev); |
770 | ||
d5818938 | 771 | intel_modeset_init_hw(dev); |
24576d23 | 772 | |
d5818938 DV |
773 | spin_lock_irq(&dev_priv->irq_lock); |
774 | if (dev_priv->display.hpd_irq_setup) | |
775 | dev_priv->display.hpd_irq_setup(dev); | |
776 | spin_unlock_irq(&dev_priv->irq_lock); | |
0e32b39c | 777 | |
d5818938 | 778 | drm_modeset_lock_all(dev); |
043e9bda | 779 | intel_display_resume(dev); |
d5818938 | 780 | drm_modeset_unlock_all(dev); |
15239099 | 781 | |
d5818938 | 782 | intel_dp_mst_resume(dev); |
e7d6f7d7 | 783 | |
d5818938 DV |
784 | /* |
785 | * ... but also need to make sure that hotplug processing | |
786 | * doesn't cause havoc. Like in the driver load code we don't | |
787 | * bother with the tiny race here where we might loose hotplug | |
788 | * notifications. | |
789 | * */ | |
790 | intel_hpd_init(dev_priv); | |
791 | /* Config may have changed between suspend and resume */ | |
792 | drm_helper_hpd_irq_event(dev); | |
1daed3fb | 793 | |
44834a67 CW |
794 | intel_opregion_init(dev); |
795 | ||
82e3b8c1 | 796 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 797 | |
b8efb17b ZR |
798 | mutex_lock(&dev_priv->modeset_restore_lock); |
799 | dev_priv->modeset_restore = MODESET_DONE; | |
800 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 801 | |
e5747e3a JB |
802 | intel_opregion_notify_adapter(dev, PCI_D0); |
803 | ||
ee6f280e ID |
804 | drm_kms_helper_poll_enable(dev); |
805 | ||
074c6ada | 806 | return 0; |
84b79f8d RW |
807 | } |
808 | ||
5e365c39 | 809 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 810 | { |
36d61e67 | 811 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a5df187 | 812 | int ret = 0; |
36d61e67 | 813 | |
76c4b250 ID |
814 | /* |
815 | * We have a resume ordering issue with the snd-hda driver also | |
816 | * requiring our device to be power up. Due to the lack of a | |
817 | * parent/child relationship we currently solve this with an early | |
818 | * resume hook. | |
819 | * | |
820 | * FIXME: This should be solved with a special hdmi sink device or | |
821 | * similar so that power domains can be employed. | |
822 | */ | |
84b79f8d RW |
823 | if (pci_enable_device(dev->pdev)) |
824 | return -EIO; | |
825 | ||
826 | pci_set_master(dev->pdev); | |
827 | ||
efee833a | 828 | if (IS_VALLEYVIEW(dev_priv)) |
1a5df187 | 829 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 830 | if (ret) |
ff0b187f DL |
831 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
832 | ret); | |
36d61e67 ID |
833 | |
834 | intel_uncore_early_sanitize(dev, true); | |
efee833a | 835 | |
a9a6b73a DL |
836 | if (IS_BROXTON(dev)) |
837 | ret = bxt_resume_prepare(dev_priv); | |
f75a1985 SS |
838 | else if (IS_SKYLAKE(dev_priv)) |
839 | ret = skl_resume_prepare(dev_priv); | |
a9a6b73a DL |
840 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
841 | hsw_disable_pc8(dev_priv); | |
efee833a | 842 | |
36d61e67 ID |
843 | intel_uncore_sanitize(dev); |
844 | intel_power_domains_init_hw(dev_priv); | |
845 | ||
846 | return ret; | |
76c4b250 ID |
847 | } |
848 | ||
1751fcf9 | 849 | int i915_resume_switcheroo(struct drm_device *dev) |
76c4b250 | 850 | { |
50a0072f | 851 | int ret; |
76c4b250 | 852 | |
097dd837 ID |
853 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
854 | return 0; | |
855 | ||
5e365c39 | 856 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
857 | if (ret) |
858 | return ret; | |
859 | ||
5a17514e ID |
860 | return i915_drm_resume(dev); |
861 | } | |
862 | ||
11ed50ec | 863 | /** |
f3953dcb | 864 | * i915_reset - reset chip after a hang |
11ed50ec | 865 | * @dev: drm device to reset |
11ed50ec BG |
866 | * |
867 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
868 | * reset or otherwise an error code. | |
869 | * | |
870 | * Procedure is fairly simple: | |
871 | * - reset the chip using the reset reg | |
872 | * - re-init context state | |
873 | * - re-init hardware status page | |
874 | * - re-init ring buffer | |
875 | * - re-init interrupt state | |
876 | * - re-init display | |
877 | */ | |
d4b8bb2a | 878 | int i915_reset(struct drm_device *dev) |
11ed50ec | 879 | { |
50227e1c | 880 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 881 | bool simulated; |
0573ed4a | 882 | int ret; |
11ed50ec | 883 | |
dbea3cea ID |
884 | intel_reset_gt_powersave(dev); |
885 | ||
d54a02c0 | 886 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 887 | |
069efc1d | 888 | i915_gem_reset(dev); |
77f01230 | 889 | |
2e7c8ee7 CW |
890 | simulated = dev_priv->gpu_error.stop_rings != 0; |
891 | ||
be62acb4 MK |
892 | ret = intel_gpu_reset(dev); |
893 | ||
894 | /* Also reset the gpu hangman. */ | |
895 | if (simulated) { | |
896 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
897 | dev_priv->gpu_error.stop_rings = 0; | |
898 | if (ret == -ENODEV) { | |
f2d91a2c DV |
899 | DRM_INFO("Reset not implemented, but ignoring " |
900 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
901 | ret = 0; |
902 | } | |
2e7c8ee7 | 903 | } |
be62acb4 | 904 | |
d8f2716a DV |
905 | if (i915_stop_ring_allow_warn(dev_priv)) |
906 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); | |
907 | ||
0573ed4a | 908 | if (ret) { |
f2d91a2c | 909 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 910 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 911 | return ret; |
11ed50ec BG |
912 | } |
913 | ||
1362b776 VS |
914 | intel_overlay_reset(dev_priv); |
915 | ||
11ed50ec BG |
916 | /* Ok, now get things going again... */ |
917 | ||
918 | /* | |
919 | * Everything depends on having the GTT running, so we need to start | |
920 | * there. Fortunately we don't need to do this unless we reset the | |
921 | * chip at a PCI level. | |
922 | * | |
923 | * Next we need to restore the context, but we don't use those | |
924 | * yet either... | |
925 | * | |
926 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
927 | * was running at the time of the reset (i.e. we weren't VT | |
928 | * switched away). | |
929 | */ | |
6689c167 | 930 | |
33d30a9c DV |
931 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
932 | dev_priv->gpu_error.reload_in_reset = true; | |
6689c167 | 933 | |
33d30a9c | 934 | ret = i915_gem_init_hw(dev); |
6689c167 | 935 | |
33d30a9c | 936 | dev_priv->gpu_error.reload_in_reset = false; |
f817586c | 937 | |
33d30a9c DV |
938 | mutex_unlock(&dev->struct_mutex); |
939 | if (ret) { | |
940 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
941 | return ret; | |
11ed50ec BG |
942 | } |
943 | ||
33d30a9c DV |
944 | /* |
945 | * rps/rc6 re-init is necessary to restore state lost after the | |
946 | * reset and the re-install of gt irqs. Skip for ironlake per | |
947 | * previous concerns that it doesn't respond well to some forms | |
948 | * of re-init after reset. | |
949 | */ | |
950 | if (INTEL_INFO(dev)->gen > 5) | |
951 | intel_enable_gt_powersave(dev); | |
952 | ||
11ed50ec BG |
953 | return 0; |
954 | } | |
955 | ||
56550d94 | 956 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 957 | { |
01a06850 DV |
958 | struct intel_device_info *intel_info = |
959 | (struct intel_device_info *) ent->driver_data; | |
960 | ||
d330a953 | 961 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
962 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
963 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
964 | return -ENODEV; | |
965 | } | |
966 | ||
5fe49d86 CW |
967 | /* Only bind to function 0 of the device. Early generations |
968 | * used function 1 as a placeholder for multi-head. This causes | |
969 | * us confusion instead, especially on the systems where both | |
970 | * functions have the same PCI-ID! | |
971 | */ | |
972 | if (PCI_FUNC(pdev->devfn)) | |
973 | return -ENODEV; | |
974 | ||
dcdb1674 | 975 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
976 | } |
977 | ||
978 | static void | |
979 | i915_pci_remove(struct pci_dev *pdev) | |
980 | { | |
981 | struct drm_device *dev = pci_get_drvdata(pdev); | |
982 | ||
983 | drm_put_dev(dev); | |
984 | } | |
985 | ||
84b79f8d | 986 | static int i915_pm_suspend(struct device *dev) |
112b715e | 987 | { |
84b79f8d RW |
988 | struct pci_dev *pdev = to_pci_dev(dev); |
989 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 990 | |
84b79f8d RW |
991 | if (!drm_dev || !drm_dev->dev_private) { |
992 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
993 | return -ENODEV; | |
994 | } | |
112b715e | 995 | |
5bcf719b DA |
996 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
997 | return 0; | |
998 | ||
5e365c39 | 999 | return i915_drm_suspend(drm_dev); |
76c4b250 ID |
1000 | } |
1001 | ||
1002 | static int i915_pm_suspend_late(struct device *dev) | |
1003 | { | |
888d0d42 | 1004 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 ID |
1005 | |
1006 | /* | |
c965d995 | 1007 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
1008 | * requiring our device to be power up. Due to the lack of a |
1009 | * parent/child relationship we currently solve this with an late | |
1010 | * suspend hook. | |
1011 | * | |
1012 | * FIXME: This should be solved with a special hdmi sink device or | |
1013 | * similar so that power domains can be employed. | |
1014 | */ | |
1015 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1016 | return 0; | |
112b715e | 1017 | |
ab3be73f ID |
1018 | return i915_drm_suspend_late(drm_dev, false); |
1019 | } | |
1020 | ||
1021 | static int i915_pm_poweroff_late(struct device *dev) | |
1022 | { | |
1023 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; | |
1024 | ||
1025 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1026 | return 0; | |
1027 | ||
1028 | return i915_drm_suspend_late(drm_dev, true); | |
cbda12d7 ZW |
1029 | } |
1030 | ||
76c4b250 ID |
1031 | static int i915_pm_resume_early(struct device *dev) |
1032 | { | |
888d0d42 | 1033 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 | 1034 | |
097dd837 ID |
1035 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1036 | return 0; | |
1037 | ||
5e365c39 | 1038 | return i915_drm_resume_early(drm_dev); |
76c4b250 ID |
1039 | } |
1040 | ||
84b79f8d | 1041 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 1042 | { |
888d0d42 | 1043 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
84b79f8d | 1044 | |
097dd837 ID |
1045 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1046 | return 0; | |
1047 | ||
5a17514e | 1048 | return i915_drm_resume(drm_dev); |
cbda12d7 ZW |
1049 | } |
1050 | ||
f75a1985 SS |
1051 | static int skl_suspend_complete(struct drm_i915_private *dev_priv) |
1052 | { | |
0a9d2bed | 1053 | enum csr_state state; |
f75a1985 SS |
1054 | /* Enabling DC6 is not a hard requirement to enter runtime D3 */ |
1055 | ||
5d96d8af DL |
1056 | skl_uninit_cdclk(dev_priv); |
1057 | ||
0a9d2bed AM |
1058 | /* TODO: wait for a completion event or |
1059 | * similar here instead of busy | |
1060 | * waiting using wait_for function. | |
1061 | */ | |
1062 | wait_for((state = intel_csr_load_status_get(dev_priv)) != | |
1063 | FW_UNINITIALIZED, 1000); | |
1064 | if (state == FW_LOADED) | |
1065 | skl_enable_dc6(dev_priv); | |
1066 | ||
f75a1985 SS |
1067 | return 0; |
1068 | } | |
1069 | ||
ebc32824 | 1070 | static int hsw_suspend_complete(struct drm_i915_private *dev_priv) |
97bea207 | 1071 | { |
414de7a0 | 1072 | hsw_enable_pc8(dev_priv); |
0ab9cfeb ID |
1073 | |
1074 | return 0; | |
97bea207 PZ |
1075 | } |
1076 | ||
31335cec SS |
1077 | static int bxt_suspend_complete(struct drm_i915_private *dev_priv) |
1078 | { | |
1079 | struct drm_device *dev = dev_priv->dev; | |
1080 | ||
1081 | /* TODO: when DC5 support is added disable DC5 here. */ | |
1082 | ||
1083 | broxton_ddi_phy_uninit(dev); | |
1084 | broxton_uninit_cdclk(dev); | |
1085 | bxt_enable_dc9(dev_priv); | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv) | |
1091 | { | |
1092 | struct drm_device *dev = dev_priv->dev; | |
1093 | ||
1094 | /* TODO: when CSR FW support is added make sure the FW is loaded */ | |
1095 | ||
1096 | bxt_disable_dc9(dev_priv); | |
1097 | ||
1098 | /* | |
1099 | * TODO: when DC5 support is added enable DC5 here if the CSR FW | |
1100 | * is available. | |
1101 | */ | |
1102 | broxton_init_cdclk(dev); | |
1103 | broxton_ddi_phy_init(dev); | |
1104 | intel_prepare_ddi(dev); | |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
f75a1985 SS |
1109 | static int skl_resume_prepare(struct drm_i915_private *dev_priv) |
1110 | { | |
1111 | struct drm_device *dev = dev_priv->dev; | |
1112 | ||
0a9d2bed AM |
1113 | if (intel_csr_load_status_get(dev_priv) == FW_LOADED) |
1114 | skl_disable_dc6(dev_priv); | |
1115 | ||
5d96d8af | 1116 | skl_init_cdclk(dev_priv); |
f75a1985 SS |
1117 | intel_csr_load_program(dev); |
1118 | ||
1119 | return 0; | |
1120 | } | |
1121 | ||
ddeea5b0 ID |
1122 | /* |
1123 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
1124 | * S0i[R123] transition. The list of registers needing a save/restore is | |
1125 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
1126 | * registers in the following way: | |
1127 | * - Driver: saved/restored by the driver | |
1128 | * - Punit : saved/restored by the Punit firmware | |
1129 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
1130 | * used internally by the HW in a way that doesn't depend | |
1131 | * keeping the content across a suspend/resume. | |
1132 | * - Debug : used for debugging | |
1133 | * | |
1134 | * We save/restore all registers marked with 'Driver', with the following | |
1135 | * exceptions: | |
1136 | * - Registers out of use, including also registers marked with 'Debug'. | |
1137 | * These have no effect on the driver's operation, so we don't save/restore | |
1138 | * them to reduce the overhead. | |
1139 | * - Registers that are fully setup by an initialization function called from | |
1140 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1141 | * - Registers that provide the right functionality with their reset defaults. | |
1142 | * | |
1143 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1144 | * ignored, we save/restore all others, practically treating the HW context as | |
1145 | * a black-box for the driver. Further investigation is needed to reduce the | |
1146 | * saved/restored registers even further, by following the same 3 criteria. | |
1147 | */ | |
1148 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1149 | { | |
1150 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1151 | int i; | |
1152 | ||
1153 | /* GAM 0x4000-0x4770 */ | |
1154 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1155 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1156 | s->arb_mode = I915_READ(ARB_MODE); | |
1157 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1158 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1159 | ||
1160 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1161 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
1162 | |
1163 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 1164 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
1165 | |
1166 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1167 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1168 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1169 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1170 | ||
1171 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1172 | ||
1173 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1174 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1175 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1176 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1177 | ||
1178 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1179 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1180 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1181 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1182 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1183 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1184 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1185 | ||
1186 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1187 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1188 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1189 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1190 | s->ecobus = I915_READ(ECOBUS); | |
1191 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1192 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1193 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1194 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1195 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1196 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1197 | ||
1198 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1199 | s->gt_imr = I915_READ(GTIMR); | |
1200 | s->gt_ier = I915_READ(GTIER); | |
1201 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1202 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1203 | ||
1204 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1205 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
1206 | |
1207 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1208 | s->tilectl = I915_READ(TILECTL); | |
1209 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1210 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1211 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1212 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1213 | ||
1214 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1215 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1216 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 1217 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
1218 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
1219 | ||
1220 | /* | |
1221 | * Not saving any of: | |
1222 | * DFT, 0x9800-0x9EC0 | |
1223 | * SARB, 0xB000-0xB1FC | |
1224 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1225 | * PCI CFG | |
1226 | */ | |
1227 | } | |
1228 | ||
1229 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1230 | { | |
1231 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1232 | u32 val; | |
1233 | int i; | |
1234 | ||
1235 | /* GAM 0x4000-0x4770 */ | |
1236 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1237 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1238 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1239 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1240 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1241 | ||
1242 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1243 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
1244 | |
1245 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 1246 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
1247 | |
1248 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1249 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1250 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1251 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1252 | ||
1253 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1254 | ||
1255 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1256 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1257 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1258 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1259 | ||
1260 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1261 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1262 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1263 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1264 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1265 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1266 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1267 | ||
1268 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1269 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1270 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1271 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1272 | I915_WRITE(ECOBUS, s->ecobus); | |
1273 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1274 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1275 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1276 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1277 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1278 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1279 | ||
1280 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1281 | I915_WRITE(GTIMR, s->gt_imr); | |
1282 | I915_WRITE(GTIER, s->gt_ier); | |
1283 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1284 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1285 | ||
1286 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1287 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
1288 | |
1289 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1290 | I915_WRITE(TILECTL, s->tilectl); | |
1291 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1292 | /* | |
1293 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1294 | * be restored, as they are used to control the s0ix suspend/resume | |
1295 | * sequence by the caller. | |
1296 | */ | |
1297 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1298 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1299 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1300 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1301 | ||
1302 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1303 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1304 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1305 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1306 | ||
1307 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1308 | ||
1309 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1310 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1311 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 1312 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
1313 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
1314 | } | |
1315 | ||
650ad970 ID |
1316 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1317 | { | |
1318 | u32 val; | |
1319 | int err; | |
1320 | ||
650ad970 | 1321 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) |
650ad970 ID |
1322 | |
1323 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1324 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1325 | if (force_on) | |
1326 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1327 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1328 | ||
1329 | if (!force_on) | |
1330 | return 0; | |
1331 | ||
8d4eee9c | 1332 | err = wait_for(COND, 20); |
650ad970 ID |
1333 | if (err) |
1334 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1335 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1336 | ||
1337 | return err; | |
1338 | #undef COND | |
1339 | } | |
1340 | ||
ddeea5b0 ID |
1341 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1342 | { | |
1343 | u32 val; | |
1344 | int err = 0; | |
1345 | ||
1346 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1347 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1348 | if (allow) | |
1349 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1350 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1351 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1352 | ||
1353 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1354 | allow) | |
1355 | err = wait_for(COND, 1); | |
1356 | if (err) | |
1357 | DRM_ERROR("timeout disabling GT waking\n"); | |
1358 | return err; | |
1359 | #undef COND | |
1360 | } | |
1361 | ||
1362 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1363 | bool wait_for_on) | |
1364 | { | |
1365 | u32 mask; | |
1366 | u32 val; | |
1367 | int err; | |
1368 | ||
1369 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1370 | val = wait_for_on ? mask : 0; | |
1371 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1372 | if (COND) | |
1373 | return 0; | |
1374 | ||
1375 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
1376 | wait_for_on ? "on" : "off", | |
1377 | I915_READ(VLV_GTLC_PW_STATUS)); | |
1378 | ||
1379 | /* | |
1380 | * RC6 transitioning can be delayed up to 2 msec (see | |
1381 | * valleyview_enable_rps), use 3 msec for safety. | |
1382 | */ | |
1383 | err = wait_for(COND, 3); | |
1384 | if (err) | |
1385 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
1386 | wait_for_on ? "on" : "off"); | |
1387 | ||
1388 | return err; | |
1389 | #undef COND | |
1390 | } | |
1391 | ||
1392 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1393 | { | |
1394 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1395 | return; | |
1396 | ||
1397 | DRM_ERROR("GT register access while GT waking disabled\n"); | |
1398 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); | |
1399 | } | |
1400 | ||
ebc32824 | 1401 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
1402 | { |
1403 | u32 mask; | |
1404 | int err; | |
1405 | ||
1406 | /* | |
1407 | * Bspec defines the following GT well on flags as debug only, so | |
1408 | * don't treat them as hard failures. | |
1409 | */ | |
1410 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1411 | ||
1412 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1413 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1414 | ||
1415 | vlv_check_no_gt_access(dev_priv); | |
1416 | ||
1417 | err = vlv_force_gfx_clock(dev_priv, true); | |
1418 | if (err) | |
1419 | goto err1; | |
1420 | ||
1421 | err = vlv_allow_gt_wake(dev_priv, false); | |
1422 | if (err) | |
1423 | goto err2; | |
98711167 D |
1424 | |
1425 | if (!IS_CHERRYVIEW(dev_priv->dev)) | |
1426 | vlv_save_gunit_s0ix_state(dev_priv); | |
ddeea5b0 ID |
1427 | |
1428 | err = vlv_force_gfx_clock(dev_priv, false); | |
1429 | if (err) | |
1430 | goto err2; | |
1431 | ||
1432 | return 0; | |
1433 | ||
1434 | err2: | |
1435 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1436 | vlv_allow_gt_wake(dev_priv, true); | |
1437 | err1: | |
1438 | vlv_force_gfx_clock(dev_priv, false); | |
1439 | ||
1440 | return err; | |
1441 | } | |
1442 | ||
016970be SK |
1443 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1444 | bool rpm_resume) | |
ddeea5b0 ID |
1445 | { |
1446 | struct drm_device *dev = dev_priv->dev; | |
1447 | int err; | |
1448 | int ret; | |
1449 | ||
1450 | /* | |
1451 | * If any of the steps fail just try to continue, that's the best we | |
1452 | * can do at this point. Return the first error code (which will also | |
1453 | * leave RPM permanently disabled). | |
1454 | */ | |
1455 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1456 | ||
98711167 D |
1457 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
1458 | vlv_restore_gunit_s0ix_state(dev_priv); | |
ddeea5b0 ID |
1459 | |
1460 | err = vlv_allow_gt_wake(dev_priv, true); | |
1461 | if (!ret) | |
1462 | ret = err; | |
1463 | ||
1464 | err = vlv_force_gfx_clock(dev_priv, false); | |
1465 | if (!ret) | |
1466 | ret = err; | |
1467 | ||
1468 | vlv_check_no_gt_access(dev_priv); | |
1469 | ||
016970be SK |
1470 | if (rpm_resume) { |
1471 | intel_init_clock_gating(dev); | |
1472 | i915_gem_restore_fences(dev); | |
1473 | } | |
ddeea5b0 ID |
1474 | |
1475 | return ret; | |
1476 | } | |
1477 | ||
97bea207 | 1478 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1479 | { |
1480 | struct pci_dev *pdev = to_pci_dev(device); | |
1481 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1483 | int ret; |
8a187455 | 1484 | |
aeab0b5a | 1485 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1486 | return -ENODEV; |
1487 | ||
604effb7 ID |
1488 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1489 | return -ENODEV; | |
1490 | ||
8a187455 PZ |
1491 | DRM_DEBUG_KMS("Suspending device\n"); |
1492 | ||
d6102977 ID |
1493 | /* |
1494 | * We could deadlock here in case another thread holding struct_mutex | |
1495 | * calls RPM suspend concurrently, since the RPM suspend will wait | |
1496 | * first for this RPM suspend to finish. In this case the concurrent | |
1497 | * RPM resume will be followed by its RPM suspend counterpart. Still | |
1498 | * for consistency return -EAGAIN, which will reschedule this suspend. | |
1499 | */ | |
1500 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1501 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); | |
1502 | /* | |
1503 | * Bump the expiration timestamp, otherwise the suspend won't | |
1504 | * be rescheduled. | |
1505 | */ | |
1506 | pm_runtime_mark_last_busy(device); | |
1507 | ||
1508 | return -EAGAIN; | |
1509 | } | |
1510 | /* | |
1511 | * We are safe here against re-faults, since the fault handler takes | |
1512 | * an RPM reference. | |
1513 | */ | |
1514 | i915_gem_release_all_mmaps(dev_priv); | |
1515 | mutex_unlock(&dev->struct_mutex); | |
1516 | ||
a1c41994 AD |
1517 | intel_guc_suspend(dev); |
1518 | ||
fac6adb0 | 1519 | intel_suspend_gt_powersave(dev); |
2eb5252e | 1520 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 1521 | |
ebc32824 | 1522 | ret = intel_suspend_complete(dev_priv); |
0ab9cfeb ID |
1523 | if (ret) { |
1524 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
b963291c | 1525 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb ID |
1526 | |
1527 | return ret; | |
1528 | } | |
a8a8bd54 | 1529 | |
737b1506 | 1530 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
dc9fb09c | 1531 | intel_uncore_forcewake_reset(dev, false); |
8a187455 | 1532 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1533 | |
1534 | /* | |
c8a0bd42 PZ |
1535 | * FIXME: We really should find a document that references the arguments |
1536 | * used below! | |
1fb2362b | 1537 | */ |
d37ae19a PZ |
1538 | if (IS_BROADWELL(dev)) { |
1539 | /* | |
1540 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
1541 | * being detected, and the call we do at intel_runtime_resume() | |
1542 | * won't be able to restore them. Since PCI_D3hot matches the | |
1543 | * actual specification and appears to be working, use it. | |
1544 | */ | |
1545 | intel_opregion_notify_adapter(dev, PCI_D3hot); | |
1546 | } else { | |
c8a0bd42 PZ |
1547 | /* |
1548 | * current versions of firmware which depend on this opregion | |
1549 | * notification have repurposed the D1 definition to mean | |
1550 | * "runtime suspended" vs. what you would normally expect (D3) | |
1551 | * to distinguish it from notifications that might be sent via | |
1552 | * the suspend path. | |
1553 | */ | |
1554 | intel_opregion_notify_adapter(dev, PCI_D1); | |
c8a0bd42 | 1555 | } |
8a187455 | 1556 | |
59bad947 | 1557 | assert_forcewakes_inactive(dev_priv); |
dc9fb09c | 1558 | |
a8a8bd54 | 1559 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1560 | return 0; |
1561 | } | |
1562 | ||
97bea207 | 1563 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1564 | { |
1565 | struct pci_dev *pdev = to_pci_dev(device); | |
1566 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1a5df187 | 1568 | int ret = 0; |
8a187455 | 1569 | |
604effb7 ID |
1570 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1571 | return -ENODEV; | |
8a187455 PZ |
1572 | |
1573 | DRM_DEBUG_KMS("Resuming device\n"); | |
1574 | ||
cd2e9e90 | 1575 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 PZ |
1576 | dev_priv->pm.suspended = false; |
1577 | ||
a1c41994 AD |
1578 | intel_guc_resume(dev); |
1579 | ||
1a5df187 PZ |
1580 | if (IS_GEN6(dev_priv)) |
1581 | intel_init_pch_refclk(dev); | |
31335cec SS |
1582 | |
1583 | if (IS_BROXTON(dev)) | |
1584 | ret = bxt_resume_prepare(dev_priv); | |
f75a1985 SS |
1585 | else if (IS_SKYLAKE(dev)) |
1586 | ret = skl_resume_prepare(dev_priv); | |
1a5df187 PZ |
1587 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
1588 | hsw_disable_pc8(dev_priv); | |
1589 | else if (IS_VALLEYVIEW(dev_priv)) | |
1590 | ret = vlv_resume_prepare(dev_priv, true); | |
1591 | ||
0ab9cfeb ID |
1592 | /* |
1593 | * No point of rolling back things in case of an error, as the best | |
1594 | * we can do is to hope that things will still work (and disable RPM). | |
1595 | */ | |
92b806d3 ID |
1596 | i915_gem_init_swizzling(dev); |
1597 | gen6_update_ring_freq(dev); | |
1598 | ||
b963291c | 1599 | intel_runtime_pm_enable_interrupts(dev_priv); |
08d8a232 VS |
1600 | |
1601 | /* | |
1602 | * On VLV/CHV display interrupts are part of the display | |
1603 | * power well, so hpd is reinitialized from there. For | |
1604 | * everyone else do it here. | |
1605 | */ | |
1606 | if (!IS_VALLEYVIEW(dev_priv)) | |
1607 | intel_hpd_init(dev_priv); | |
1608 | ||
fac6adb0 | 1609 | intel_enable_gt_powersave(dev); |
b5478bcd | 1610 | |
0ab9cfeb ID |
1611 | if (ret) |
1612 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1613 | else | |
1614 | DRM_DEBUG_KMS("Device resumed\n"); | |
1615 | ||
1616 | return ret; | |
8a187455 PZ |
1617 | } |
1618 | ||
016970be SK |
1619 | /* |
1620 | * This function implements common functionality of runtime and system | |
1621 | * suspend sequence. | |
1622 | */ | |
ebc32824 SK |
1623 | static int intel_suspend_complete(struct drm_i915_private *dev_priv) |
1624 | { | |
ebc32824 SK |
1625 | int ret; |
1626 | ||
16e44e3e | 1627 | if (IS_BROXTON(dev_priv)) |
31335cec | 1628 | ret = bxt_suspend_complete(dev_priv); |
16e44e3e | 1629 | else if (IS_SKYLAKE(dev_priv)) |
f75a1985 | 1630 | ret = skl_suspend_complete(dev_priv); |
16e44e3e | 1631 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ebc32824 | 1632 | ret = hsw_suspend_complete(dev_priv); |
16e44e3e | 1633 | else if (IS_VALLEYVIEW(dev_priv)) |
ebc32824 | 1634 | ret = vlv_suspend_complete(dev_priv); |
604effb7 ID |
1635 | else |
1636 | ret = 0; | |
ebc32824 SK |
1637 | |
1638 | return ret; | |
1639 | } | |
1640 | ||
b4b78d12 | 1641 | static const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
1642 | /* |
1643 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
1644 | * PMSG_RESUME] | |
1645 | */ | |
0206e353 | 1646 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1647 | .suspend_late = i915_pm_suspend_late, |
1648 | .resume_early = i915_pm_resume_early, | |
0206e353 | 1649 | .resume = i915_pm_resume, |
5545dbbf ID |
1650 | |
1651 | /* | |
1652 | * S4 event handlers | |
1653 | * @freeze, @freeze_late : called (1) before creating the | |
1654 | * hibernation image [PMSG_FREEZE] and | |
1655 | * (2) after rebooting, before restoring | |
1656 | * the image [PMSG_QUIESCE] | |
1657 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
1658 | * image, before writing it [PMSG_THAW] | |
1659 | * and (2) after failing to create or | |
1660 | * restore the image [PMSG_RECOVER] | |
1661 | * @poweroff, @poweroff_late: called after writing the hibernation | |
1662 | * image, before rebooting [PMSG_HIBERNATE] | |
1663 | * @restore, @restore_early : called after rebooting and restoring the | |
1664 | * hibernation image [PMSG_RESTORE] | |
1665 | */ | |
36d61e67 ID |
1666 | .freeze = i915_pm_suspend, |
1667 | .freeze_late = i915_pm_suspend_late, | |
1668 | .thaw_early = i915_pm_resume_early, | |
1669 | .thaw = i915_pm_resume, | |
1670 | .poweroff = i915_pm_suspend, | |
ab3be73f | 1671 | .poweroff_late = i915_pm_poweroff_late, |
76c4b250 | 1672 | .restore_early = i915_pm_resume_early, |
0206e353 | 1673 | .restore = i915_pm_resume, |
5545dbbf ID |
1674 | |
1675 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
1676 | .runtime_suspend = intel_runtime_suspend, |
1677 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1678 | }; |
1679 | ||
78b68556 | 1680 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1681 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1682 | .open = drm_gem_vm_open, |
1683 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1684 | }; |
1685 | ||
e08e96de AV |
1686 | static const struct file_operations i915_driver_fops = { |
1687 | .owner = THIS_MODULE, | |
1688 | .open = drm_open, | |
1689 | .release = drm_release, | |
1690 | .unlocked_ioctl = drm_ioctl, | |
1691 | .mmap = drm_gem_mmap, | |
1692 | .poll = drm_poll, | |
e08e96de AV |
1693 | .read = drm_read, |
1694 | #ifdef CONFIG_COMPAT | |
1695 | .compat_ioctl = i915_compat_ioctl, | |
1696 | #endif | |
1697 | .llseek = noop_llseek, | |
1698 | }; | |
1699 | ||
1da177e4 | 1700 | static struct drm_driver driver = { |
0c54781b MW |
1701 | /* Don't use MTRRs here; the Xserver or userspace app should |
1702 | * deal with them for Intel hardware. | |
792d2b9a | 1703 | */ |
673a394b | 1704 | .driver_features = |
10ba5012 | 1705 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1751fcf9 | 1706 | DRIVER_RENDER | DRIVER_MODESET, |
22eae947 | 1707 | .load = i915_driver_load, |
ba8bbcf6 | 1708 | .unload = i915_driver_unload, |
673a394b | 1709 | .open = i915_driver_open, |
22eae947 DA |
1710 | .lastclose = i915_driver_lastclose, |
1711 | .preclose = i915_driver_preclose, | |
673a394b | 1712 | .postclose = i915_driver_postclose, |
915b4d11 | 1713 | .set_busid = drm_pci_set_busid, |
d8e29209 | 1714 | |
955b12de | 1715 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1716 | .debugfs_init = i915_debugfs_init, |
1717 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1718 | #endif |
673a394b | 1719 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1720 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1721 | |
1722 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1723 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1724 | .gem_prime_export = i915_gem_prime_export, | |
1725 | .gem_prime_import = i915_gem_prime_import, | |
1726 | ||
ff72145b | 1727 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 1728 | .dumb_map_offset = i915_gem_mmap_gtt, |
43387b37 | 1729 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1730 | .ioctls = i915_ioctls, |
e08e96de | 1731 | .fops = &i915_driver_fops, |
22eae947 DA |
1732 | .name = DRIVER_NAME, |
1733 | .desc = DRIVER_DESC, | |
1734 | .date = DRIVER_DATE, | |
1735 | .major = DRIVER_MAJOR, | |
1736 | .minor = DRIVER_MINOR, | |
1737 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1738 | }; |
1739 | ||
8410ea3b DA |
1740 | static struct pci_driver i915_pci_driver = { |
1741 | .name = DRIVER_NAME, | |
1742 | .id_table = pciidlist, | |
1743 | .probe = i915_pci_probe, | |
1744 | .remove = i915_pci_remove, | |
1745 | .driver.pm = &i915_pm_ops, | |
1746 | }; | |
1747 | ||
1da177e4 LT |
1748 | static int __init i915_init(void) |
1749 | { | |
1750 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1751 | |
1752 | /* | |
fd930478 CW |
1753 | * Enable KMS by default, unless explicitly overriden by |
1754 | * either the i915.modeset prarameter or by the | |
1755 | * vga_text_mode_force boot option. | |
79e53945 | 1756 | */ |
fd930478 CW |
1757 | |
1758 | if (i915.modeset == 0) | |
1759 | driver.driver_features &= ~DRIVER_MODESET; | |
79e53945 JB |
1760 | |
1761 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 1762 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
1763 | driver.driver_features &= ~DRIVER_MODESET; |
1764 | #endif | |
1765 | ||
b30324ad | 1766 | if (!(driver.driver_features & DRIVER_MODESET)) { |
b30324ad | 1767 | /* Silently fail loading to not upset userspace. */ |
c9cd7b65 | 1768 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
b30324ad | 1769 | return 0; |
b30324ad | 1770 | } |
3885c6bb | 1771 | |
c5b852f3 | 1772 | if (i915.nuclear_pageflip) |
b2e7723b MR |
1773 | driver.driver_features |= DRIVER_ATOMIC; |
1774 | ||
8410ea3b | 1775 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1776 | } |
1777 | ||
1778 | static void __exit i915_exit(void) | |
1779 | { | |
b33ecdd1 DV |
1780 | if (!(driver.driver_features & DRIVER_MODESET)) |
1781 | return; /* Never loaded a driver. */ | |
b33ecdd1 | 1782 | |
8410ea3b | 1783 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1784 | } |
1785 | ||
1786 | module_init(i915_init); | |
1787 | module_exit(i915_exit); | |
1788 | ||
0a6d1631 | 1789 | MODULE_AUTHOR("Tungsten Graphics, Inc."); |
1eab9234 | 1790 | MODULE_AUTHOR("Intel Corporation"); |
0a6d1631 | 1791 | |
b5e89ed5 | 1792 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 | 1793 | MODULE_LICENSE("GPL and additional rights"); |