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drm/i915: Split out the PCI driver interface to i915_pci.c
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
79e53945 31#include <linux/console.h>
0673ad47
CW		 32#include <linux/device.h>
33#include <linux/oom.h>
e0cd3608 34#include <linux/module.h>
0673ad47
CW		 35#include <linux/pci.h>
36#include <linux/pm.h>
d6102977 37#include <linux/pm_runtime.h>
0673ad47
CW		 38#include <linux/pnp.h>
39#include <linux/slab.h>
40#include <linux/vgaarb.h>
704ab614 41#include <linux/vga_switcheroo.h>
0673ad47
CW		 42#include <linux/vt.h>
43#include <acpi/video.h>
44
45#include <drm/drmP.h>
760285e7 46#include <drm/drm_crtc_helper.h>
0673ad47
CW		 47#include <drm/i915_drm.h>
48
49#include "i915_drv.h"
50#include "i915_trace.h"
51#include "i915_vgpu.h"
52#include "intel_drv.h"
79e53945 53
112b715e
KH		 54static struct drm_driver driver;
55
0673ad47
CW		 56static unsigned int i915_load_fail_count;
57
58bool __i915_inject_load_failure(const char *func, int line)
59{
60 if (i915_load_fail_count >= i915.inject_load_failure)
61 return false;
62
63 if (++i915_load_fail_count == i915.inject_load_failure) {
64 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
65 i915.inject_load_failure, func, line);
66 return true;
67 }
68
69 return false;
70}
71
72#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
73#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
74 "providing the dmesg log by booting with drm.debug=0xf"
75
76void
77__i915_printk(struct drm_i915_private *dev_priv, const char *level,
78 const char *fmt, ...)
79{
80 static bool shown_bug_once;
81 struct device *dev = dev_priv->dev->dev;
82 bool is_error = level[1] <= KERN_ERR[1];
83 bool is_debug = level[1] == KERN_DEBUG[1];
84 struct va_format vaf;
85 va_list args;
86
87 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
88 return;
89
90 va_start(args, fmt);
91
92 vaf.fmt = fmt;
93 vaf.va = &args;
94
95 dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
96 __builtin_return_address(0), &vaf);
97
98 if (is_error && !shown_bug_once) {
99 dev_notice(dev, "%s", FDO_BUG_MSG);
100 shown_bug_once = true;
101 }
102
103 va_end(args);
104}
105
106static bool i915_error_injected(struct drm_i915_private *dev_priv)
107{
108 return i915.inject_load_failure &&
109 i915_load_fail_count == i915.inject_load_failure;
110}
111
112#define i915_load_error(dev_priv, fmt, ...) \
113 __i915_printk(dev_priv, \
114 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
115 fmt, ##__VA_ARGS__)
116
117
118static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
119{
120 enum intel_pch ret = PCH_NOP;
121
122 /*
123 * In a virtualized passthrough environment we can be in a
124 * setup where the ISA bridge is not able to be passed through.
125 * In this case, a south bridge can be emulated and we have to
126 * make an educated guess as to which PCH is really there.
127 */
128
129 if (IS_GEN5(dev)) {
130 ret = PCH_IBX;
131 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
132 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
133 ret = PCH_CPT;
134 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
135 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
136 ret = PCH_LPT;
137 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
138 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
139 ret = PCH_SPT;
140 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
141 }
142
143 return ret;
144}
145
146static void intel_detect_pch(struct drm_device *dev)
147{
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 struct pci_dev *pch = NULL;
150
151 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
152 * (which really amounts to a PCH but no South Display).
153 */
154 if (INTEL_INFO(dev)->num_pipes == 0) {
155 dev_priv->pch_type = PCH_NOP;
156 return;
157 }
158
159 /*
160 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
161 * make graphics device passthrough work easy for VMM, that only
162 * need to expose ISA bridge to let driver know the real hardware
163 * underneath. This is a requirement from virtualization team.
164 *
165 * In some virtualized environments (e.g. XEN), there is irrelevant
166 * ISA bridge in the system. To work reliably, we should scan trhough
167 * all the ISA bridge devices and check for the first match, instead
168 * of only checking the first one.
169 */
170 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
171 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
172 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
173 dev_priv->pch_id = id;
174
175 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
176 dev_priv->pch_type = PCH_IBX;
177 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
178 WARN_ON(!IS_GEN5(dev));
179 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
180 dev_priv->pch_type = PCH_CPT;
181 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
182 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
183 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
184 /* PantherPoint is CPT compatible */
185 dev_priv->pch_type = PCH_CPT;
186 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
187 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
188 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
189 dev_priv->pch_type = PCH_LPT;
190 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
191 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
192 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
193 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
194 dev_priv->pch_type = PCH_LPT;
195 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
196 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
197 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
198 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
199 dev_priv->pch_type = PCH_SPT;
200 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
201 WARN_ON(!IS_SKYLAKE(dev) &&
202 !IS_KABYLAKE(dev));
203 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
204 dev_priv->pch_type = PCH_SPT;
205 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
206 WARN_ON(!IS_SKYLAKE(dev) &&
207 !IS_KABYLAKE(dev));
208 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
209 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
210 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
211 pch->subsystem_vendor ==
212 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
213 pch->subsystem_device ==
214 PCI_SUBDEVICE_ID_QEMU)) {
215 dev_priv->pch_type = intel_virt_detect_pch(dev);
216 } else
217 continue;
218
219 break;
220 }
221 }
222 if (!pch)
223 DRM_DEBUG_KMS("No PCH found.\n");
224
225 pci_dev_put(pch);
226}
227
228bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
229{
230 if (INTEL_GEN(dev_priv) < 6)
231 return false;
232
233 if (i915.semaphores >= 0)
234 return i915.semaphores;
235
236 /* TODO: make semaphores and Execlists play nicely together */
237 if (i915.enable_execlists)
238 return false;
239
240#ifdef CONFIG_INTEL_IOMMU
241 /* Enable semaphores on SNB when IO remapping is off */
242 if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped)
243 return false;
244#endif
245
246 return true;
247}
248
249static int i915_getparam(struct drm_device *dev, void *data,
250 struct drm_file *file_priv)
251{
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 drm_i915_getparam_t *param = data;
254 int value;
255
256 switch (param->param) {
257 case I915_PARAM_IRQ_ACTIVE:
258 case I915_PARAM_ALLOW_BATCHBUFFER:
259 case I915_PARAM_LAST_DISPATCH:
260 /* Reject all old ums/dri params. */
261 return -ENODEV;
262 case I915_PARAM_CHIPSET_ID:
263 value = dev->pdev->device;
264 break;
265 case I915_PARAM_REVISION:
266 value = dev->pdev->revision;
267 break;
268 case I915_PARAM_HAS_GEM:
269 value = 1;
270 break;
271 case I915_PARAM_NUM_FENCES_AVAIL:
272 value = dev_priv->num_fence_regs;
273 break;
274 case I915_PARAM_HAS_OVERLAY:
275 value = dev_priv->overlay ? 1 : 0;
276 break;
277 case I915_PARAM_HAS_PAGEFLIPPING:
278 value = 1;
279 break;
280 case I915_PARAM_HAS_EXECBUF2:
281 /* depends on GEM */
282 value = 1;
283 break;
284 case I915_PARAM_HAS_BSD:
285 value = intel_engine_initialized(&dev_priv->engine[VCS]);
286 break;
287 case I915_PARAM_HAS_BLT:
288 value = intel_engine_initialized(&dev_priv->engine[BCS]);
289 break;
290 case I915_PARAM_HAS_VEBOX:
291 value = intel_engine_initialized(&dev_priv->engine[VECS]);
292 break;
293 case I915_PARAM_HAS_BSD2:
294 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
295 break;
296 case I915_PARAM_HAS_RELAXED_FENCING:
297 value = 1;
298 break;
299 case I915_PARAM_HAS_COHERENT_RINGS:
300 value = 1;
301 break;
302 case I915_PARAM_HAS_EXEC_CONSTANTS:
303 value = INTEL_INFO(dev)->gen >= 4;
304 break;
305 case I915_PARAM_HAS_RELAXED_DELTA:
306 value = 1;
307 break;
308 case I915_PARAM_HAS_GEN7_SOL_RESET:
309 value = 1;
310 break;
311 case I915_PARAM_HAS_LLC:
312 value = HAS_LLC(dev);
313 break;
314 case I915_PARAM_HAS_WT:
315 value = HAS_WT(dev);
316 break;
317 case I915_PARAM_HAS_ALIASING_PPGTT:
318 value = USES_PPGTT(dev);
319 break;
320 case I915_PARAM_HAS_WAIT_TIMEOUT:
321 value = 1;
322 break;
323 case I915_PARAM_HAS_SEMAPHORES:
324 value = i915_semaphore_is_enabled(dev_priv);
325 break;
326 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
327 value = 1;
328 break;
329 case I915_PARAM_HAS_SECURE_BATCHES:
330 value = capable(CAP_SYS_ADMIN);
331 break;
332 case I915_PARAM_HAS_PINNED_BATCHES:
333 value = 1;
334 break;
335 case I915_PARAM_HAS_EXEC_NO_RELOC:
336 value = 1;
337 break;
338 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
339 value = 1;
340 break;
341 case I915_PARAM_CMD_PARSER_VERSION:
342 value = i915_cmd_parser_get_version(dev_priv);
343 break;
344 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
345 value = 1;
346 break;
347 case I915_PARAM_MMAP_VERSION:
348 value = 1;
349 break;
350 case I915_PARAM_SUBSLICE_TOTAL:
351 value = INTEL_INFO(dev)->subslice_total;
352 if (!value)
353 return -ENODEV;
354 break;
355 case I915_PARAM_EU_TOTAL:
356 value = INTEL_INFO(dev)->eu_total;
357 if (!value)
358 return -ENODEV;
359 break;
360 case I915_PARAM_HAS_GPU_RESET:
361 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
362 break;
363 case I915_PARAM_HAS_RESOURCE_STREAMER:
364 value = HAS_RESOURCE_STREAMER(dev);
365 break;
366 case I915_PARAM_HAS_EXEC_SOFTPIN:
367 value = 1;
368 break;
369 default:
370 DRM_DEBUG("Unknown parameter %d\n", param->param);
371 return -EINVAL;
372 }
373
dda33009 374 if (put_user(value, param->value))
0673ad47 375 return -EFAULT;
0673ad47
CW		 376
377 return 0;
378}
379
380static int i915_get_bridge_dev(struct drm_device *dev)
381{
382 struct drm_i915_private *dev_priv = dev->dev_private;
383
384 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
385 if (!dev_priv->bridge_dev) {
386 DRM_ERROR("bridge device not found\n");
387 return -1;
388 }
389 return 0;
390}
391
392/* Allocate space for the MCH regs if needed, return nonzero on error */
393static int
394intel_alloc_mchbar_resource(struct drm_device *dev)
395{
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
398 u32 temp_lo, temp_hi = 0;
399 u64 mchbar_addr;
400 int ret;
401
402 if (INTEL_INFO(dev)->gen >= 4)
403 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
404 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
405 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
406
407 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
408#ifdef CONFIG_PNP
409 if (mchbar_addr &&
410 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
411 return 0;
412#endif
413
414 /* Get some space for it */
415 dev_priv->mch_res.name = "i915 MCHBAR";
416 dev_priv->mch_res.flags = IORESOURCE_MEM;
417 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
418 &dev_priv->mch_res,
419 MCHBAR_SIZE, MCHBAR_SIZE,
420 PCIBIOS_MIN_MEM,
421 0, pcibios_align_resource,
422 dev_priv->bridge_dev);
423 if (ret) {
424 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
425 dev_priv->mch_res.start = 0;
426 return ret;
427 }
428
429 if (INTEL_INFO(dev)->gen >= 4)
430 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
431 upper_32_bits(dev_priv->mch_res.start));
432
433 pci_write_config_dword(dev_priv->bridge_dev, reg,
434 lower_32_bits(dev_priv->mch_res.start));
435 return 0;
436}
437
438/* Setup MCHBAR if possible, return true if we should disable it again */
439static void
440intel_setup_mchbar(struct drm_device *dev)
441{
442 struct drm_i915_private *dev_priv = dev->dev_private;
443 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
444 u32 temp;
445 bool enabled;
446
447 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
448 return;
449
450 dev_priv->mchbar_need_disable = false;
451
452 if (IS_I915G(dev) || IS_I915GM(dev)) {
453 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
454 enabled = !!(temp & DEVEN_MCHBAR_EN);
455 } else {
456 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
457 enabled = temp & 1;
458 }
459
460 /* If it's already enabled, don't have to do anything */
461 if (enabled)
462 return;
463
464 if (intel_alloc_mchbar_resource(dev))
465 return;
466
467 dev_priv->mchbar_need_disable = true;
468
469 /* Space is allocated or reserved, so enable it. */
470 if (IS_I915G(dev) || IS_I915GM(dev)) {
471 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
472 temp | DEVEN_MCHBAR_EN);
473 } else {
474 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
475 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
476 }
477}
478
479static void
480intel_teardown_mchbar(struct drm_device *dev)
481{
482 struct drm_i915_private *dev_priv = dev->dev_private;
483 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
484
485 if (dev_priv->mchbar_need_disable) {
486 if (IS_I915G(dev) || IS_I915GM(dev)) {
487 u32 deven_val;
488
489 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
490 &deven_val);
491 deven_val &= ~DEVEN_MCHBAR_EN;
492 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
493 deven_val);
494 } else {
495 u32 mchbar_val;
496
497 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
498 &mchbar_val);
499 mchbar_val &= ~1;
500 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
501 mchbar_val);
502 }
503 }
504
505 if (dev_priv->mch_res.start)
506 release_resource(&dev_priv->mch_res);
507}
508
509/* true = enable decode, false = disable decoder */
510static unsigned int i915_vga_set_decode(void *cookie, bool state)
511{
512 struct drm_device *dev = cookie;
513
514 intel_modeset_vga_set_state(dev, state);
515 if (state)
516 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
517 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
518 else
519 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
520}
521
522static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
523{
524 struct drm_device *dev = pci_get_drvdata(pdev);
525 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
526
527 if (state == VGA_SWITCHEROO_ON) {
528 pr_info("switched on\n");
529 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
530 /* i915 resume handler doesn't set to D0 */
531 pci_set_power_state(dev->pdev, PCI_D0);
532 i915_resume_switcheroo(dev);
533 dev->switch_power_state = DRM_SWITCH_POWER_ON;
534 } else {
535 pr_info("switched off\n");
536 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
537 i915_suspend_switcheroo(dev, pmm);
538 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
539 }
540}
541
542static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
543{
544 struct drm_device *dev = pci_get_drvdata(pdev);
545
546 /*
547 * FIXME: open_count is protected by drm_global_mutex but that would lead to
548 * locking inversion with the driver load path. And the access here is
549 * completely racy anyway. So don't bother with locking for now.
550 */
551 return dev->open_count == 0;
552}
553
554static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
555 .set_gpu_state = i915_switcheroo_set_state,
556 .reprobe = NULL,
557 .can_switch = i915_switcheroo_can_switch,
558};
559
560static void i915_gem_fini(struct drm_device *dev)
561{
562 struct drm_i915_private *dev_priv = to_i915(dev);
563
564 /*
565 * Neither the BIOS, ourselves or any other kernel
566 * expects the system to be in execlists mode on startup,
567 * so we need to reset the GPU back to legacy mode. And the only
568 * known way to disable logical contexts is through a GPU reset.
569 *
570 * So in order to leave the system in a known default configuration,
571 * always reset the GPU upon unload. Afterwards we then clean up the
572 * GEM state tracking, flushing off the requests and leaving the
573 * system in a known idle state.
574 *
575 * Note that is of the upmost importance that the GPU is idle and
576 * all stray writes are flushed *before* we dismantle the backing
577 * storage for the pinned objects.
578 *
579 * However, since we are uncertain that reseting the GPU on older
580 * machines is a good idea, we don't - just in case it leaves the
581 * machine in an unusable condition.
582 */
583 if (HAS_HW_CONTEXTS(dev)) {
584 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
585 WARN_ON(reset && reset != -ENODEV);
586 }
587
588 mutex_lock(&dev->struct_mutex);
589 i915_gem_reset(dev);
590 i915_gem_cleanup_engines(dev);
591 i915_gem_context_fini(dev);
592 mutex_unlock(&dev->struct_mutex);
593
594 WARN_ON(!list_empty(&to_i915(dev)->context_list));
595}
596
597static int i915_load_modeset_init(struct drm_device *dev)
598{
599 struct drm_i915_private *dev_priv = dev->dev_private;
600 int ret;
601
602 if (i915_inject_load_failure())
603 return -ENODEV;
604
605 ret = intel_bios_init(dev_priv);
606 if (ret)
607 DRM_INFO("failed to find VBIOS tables\n");
608
609 /* If we have > 1 VGA cards, then we need to arbitrate access
610 * to the common VGA resources.
611 *
612 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
613 * then we do not take part in VGA arbitration and the
614 * vga_client_register() fails with -ENODEV.
615 */
616 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
617 if (ret && ret != -ENODEV)
618 goto out;
619
620 intel_register_dsm_handler();
621
622 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
623 if (ret)
624 goto cleanup_vga_client;
625
626 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
627 intel_update_rawclk(dev_priv);
628
629 intel_power_domains_init_hw(dev_priv, false);
630
631 intel_csr_ucode_init(dev_priv);
632
633 ret = intel_irq_install(dev_priv);
634 if (ret)
635 goto cleanup_csr;
636
637 intel_setup_gmbus(dev);
638
639 /* Important: The output setup functions called by modeset_init need
640 * working irqs for e.g. gmbus and dp aux transfers. */
641 intel_modeset_init(dev);
642
643 intel_guc_init(dev);
644
645 ret = i915_gem_init(dev);
646 if (ret)
647 goto cleanup_irq;
648
649 intel_modeset_gem_init(dev);
650
651 if (INTEL_INFO(dev)->num_pipes == 0)
652 return 0;
653
654 ret = intel_fbdev_init(dev);
655 if (ret)
656 goto cleanup_gem;
657
658 /* Only enable hotplug handling once the fbdev is fully set up. */
659 intel_hpd_init(dev_priv);
660
661 drm_kms_helper_poll_init(dev);
662
663 return 0;
664
665cleanup_gem:
666 i915_gem_fini(dev);
667cleanup_irq:
668 intel_guc_fini(dev);
669 drm_irq_uninstall(dev);
670 intel_teardown_gmbus(dev);
671cleanup_csr:
672 intel_csr_ucode_fini(dev_priv);
673 intel_power_domains_fini(dev_priv);
674 vga_switcheroo_unregister_client(dev->pdev);
675cleanup_vga_client:
676 vga_client_register(dev->pdev, NULL, NULL, NULL);
677out:
678 return ret;
679}
680
681#if IS_ENABLED(CONFIG_FB)
682static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
683{
684 struct apertures_struct *ap;
685 struct pci_dev *pdev = dev_priv->dev->pdev;
686 struct i915_ggtt *ggtt = &dev_priv->ggtt;
687 bool primary;
688 int ret;
689
690 ap = alloc_apertures(1);
691 if (!ap)
692 return -ENOMEM;
693
694 ap->ranges[0].base = ggtt->mappable_base;
695 ap->ranges[0].size = ggtt->mappable_end;
696
697 primary =
698 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
699
700 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
701
702 kfree(ap);
703
704 return ret;
705}
706#else
707static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
708{
709 return 0;
710}
711#endif
712
713#if !defined(CONFIG_VGA_CONSOLE)
714static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
715{
716 return 0;
717}
718#elif !defined(CONFIG_DUMMY_CONSOLE)
719static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
720{
721 return -ENODEV;
722}
723#else
724static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
725{
726 int ret = 0;
727
728 DRM_INFO("Replacing VGA console driver\n");
729
730 console_lock();
731 if (con_is_bound(&vga_con))
732 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
733 if (ret == 0) {
734 ret = do_unregister_con_driver(&vga_con);
735
736 /* Ignore "already unregistered". */
737 if (ret == -ENODEV)
738 ret = 0;
739 }
740 console_unlock();
741
742 return ret;
743}
744#endif
745
746static void i915_dump_device_info(struct drm_i915_private *dev_priv)
747{
748 const struct intel_device_info *info = &dev_priv->info;
749
750#define PRINT_S(name) "%s"
751#define SEP_EMPTY
752#define PRINT_FLAG(name) info->name ? #name "," : ""
753#define SEP_COMMA ,
754 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
755 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
756 info->gen,
757 dev_priv->dev->pdev->device,
758 dev_priv->dev->pdev->revision,
759 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
760#undef PRINT_S
761#undef SEP_EMPTY
762#undef PRINT_FLAG
763#undef SEP_COMMA
764}
765
766static void cherryview_sseu_info_init(struct drm_device *dev)
767{
768 struct drm_i915_private *dev_priv = dev->dev_private;
769 struct intel_device_info *info;
770 u32 fuse, eu_dis;
771
772 info = (struct intel_device_info *)&dev_priv->info;
773 fuse = I915_READ(CHV_FUSE_GT);
774
775 info->slice_total = 1;
776
777 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
778 info->subslice_per_slice++;
779 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
780 CHV_FGT_EU_DIS_SS0_R1_MASK);
781 info->eu_total += 8 - hweight32(eu_dis);
782 }
783
784 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
785 info->subslice_per_slice++;
786 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
787 CHV_FGT_EU_DIS_SS1_R1_MASK);
788 info->eu_total += 8 - hweight32(eu_dis);
789 }
790
791 info->subslice_total = info->subslice_per_slice;
792 /*
793 * CHV expected to always have a uniform distribution of EU
794 * across subslices.
795 */
796 info->eu_per_subslice = info->subslice_total ?
797 info->eu_total / info->subslice_total :
798 0;
799 /*
800 * CHV supports subslice power gating on devices with more than
801 * one subslice, and supports EU power gating on devices with
802 * more than one EU pair per subslice.
803 */
804 info->has_slice_pg = 0;
805 info->has_subslice_pg = (info->subslice_total > 1);
806 info->has_eu_pg = (info->eu_per_subslice > 2);
807}
808
809static void gen9_sseu_info_init(struct drm_device *dev)
810{
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 struct intel_device_info *info;
813 int s_max = 3, ss_max = 4, eu_max = 8;
814 int s, ss;
815 u32 fuse2, s_enable, ss_disable, eu_disable;
816 u8 eu_mask = 0xff;
817
818 info = (struct intel_device_info *)&dev_priv->info;
819 fuse2 = I915_READ(GEN8_FUSE2);
820 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
821 GEN8_F2_S_ENA_SHIFT;
822 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
823 GEN9_F2_SS_DIS_SHIFT;
824
825 info->slice_total = hweight32(s_enable);
826 /*
827 * The subslice disable field is global, i.e. it applies
828 * to each of the enabled slices.
829 */
830 info->subslice_per_slice = ss_max - hweight32(ss_disable);
831 info->subslice_total = info->slice_total *
832 info->subslice_per_slice;
833
834 /*
835 * Iterate through enabled slices and subslices to
836 * count the total enabled EU.
837 */
838 for (s = 0; s < s_max; s++) {
839 if (!(s_enable & (0x1 << s)))
840 /* skip disabled slice */
841 continue;
842
843 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
844 for (ss = 0; ss < ss_max; ss++) {
845 int eu_per_ss;
846
847 if (ss_disable & (0x1 << ss))
848 /* skip disabled subslice */
849 continue;
850
851 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
852 eu_mask);
853
854 /*
855 * Record which subslice(s) has(have) 7 EUs. we
856 * can tune the hash used to spread work among
857 * subslices if they are unbalanced.
858 */
859 if (eu_per_ss == 7)
860 info->subslice_7eu[s] |= 1 << ss;
861
862 info->eu_total += eu_per_ss;
863 }
864 }
865
866 /*
867 * SKL is expected to always have a uniform distribution
868 * of EU across subslices with the exception that any one
869 * EU in any one subslice may be fused off for die
870 * recovery. BXT is expected to be perfectly uniform in EU
871 * distribution.
872 */
873 info->eu_per_subslice = info->subslice_total ?
874 DIV_ROUND_UP(info->eu_total,
875 info->subslice_total) : 0;
876 /*
877 * SKL supports slice power gating on devices with more than
878 * one slice, and supports EU power gating on devices with
879 * more than one EU pair per subslice. BXT supports subslice
880 * power gating on devices with more than one subslice, and
881 * supports EU power gating on devices with more than one EU
882 * pair per subslice.
883 */
884 info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
885 (info->slice_total > 1));
886 info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
887 info->has_eu_pg = (info->eu_per_subslice > 2);
888
889 if (IS_BROXTON(dev)) {
890#define IS_SS_DISABLED(_ss_disable, ss) (_ss_disable & (0x1 << ss))
891 /*
892 * There is a HW issue in 2x6 fused down parts that requires
893 * Pooled EU to be enabled as a WA. The pool configuration
894 * changes depending upon which subslice is fused down. This
895 * doesn't affect if the device has all 3 subslices enabled.
896 */
897 /* WaEnablePooledEuFor2x6:bxt */
898 info->has_pooled_eu = ((info->subslice_per_slice == 3) ||
899 (info->subslice_per_slice == 2 &&
900 INTEL_REVID(dev) < BXT_REVID_C0));
901
902 info->min_eu_in_pool = 0;
903 if (info->has_pooled_eu) {
904 if (IS_SS_DISABLED(ss_disable, 0) ||
905 IS_SS_DISABLED(ss_disable, 2))
906 info->min_eu_in_pool = 3;
907 else if (IS_SS_DISABLED(ss_disable, 1))
908 info->min_eu_in_pool = 6;
909 else
910 info->min_eu_in_pool = 9;
911 }
912#undef IS_SS_DISABLED
913 }
914}
915
916static void broadwell_sseu_info_init(struct drm_device *dev)
917{
918 struct drm_i915_private *dev_priv = dev->dev_private;
919 struct intel_device_info *info;
920 const int s_max = 3, ss_max = 3, eu_max = 8;
921 int s, ss;
922 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
923
924 fuse2 = I915_READ(GEN8_FUSE2);
925 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
926 ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
927
928 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
929 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
930 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
931 (32 - GEN8_EU_DIS0_S1_SHIFT));
932 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
933 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
934 (32 - GEN8_EU_DIS1_S2_SHIFT));
935
936
937 info = (struct intel_device_info *)&dev_priv->info;
938 info->slice_total = hweight32(s_enable);
939
940 /*
941 * The subslice disable field is global, i.e. it applies
942 * to each of the enabled slices.
943 */
944 info->subslice_per_slice = ss_max - hweight32(ss_disable);
945 info->subslice_total = info->slice_total * info->subslice_per_slice;
946
947 /*
948 * Iterate through enabled slices and subslices to
949 * count the total enabled EU.
950 */
951 for (s = 0; s < s_max; s++) {
952 if (!(s_enable & (0x1 << s)))
953 /* skip disabled slice */
954 continue;
955
956 for (ss = 0; ss < ss_max; ss++) {
957 u32 n_disabled;
958
959 if (ss_disable & (0x1 << ss))
960 /* skip disabled subslice */
961 continue;
962
963 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
964
965 /*
966 * Record which subslices have 7 EUs.
967 */
968 if (eu_max - n_disabled == 7)
969 info->subslice_7eu[s] |= 1 << ss;
970
971 info->eu_total += eu_max - n_disabled;
972 }
973 }
974
975 /*
976 * BDW is expected to always have a uniform distribution of EU across
977 * subslices with the exception that any one EU in any one subslice may
978 * be fused off for die recovery.
979 */
980 info->eu_per_subslice = info->subslice_total ?
981 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
982
983 /*
984 * BDW supports slice power gating on devices with more than
985 * one slice.
986 */
987 info->has_slice_pg = (info->slice_total > 1);
988 info->has_subslice_pg = 0;
989 info->has_eu_pg = 0;
990}
991
992/*
993 * Determine various intel_device_info fields at runtime.
994 *
995 * Use it when either:
996 * - it's judged too laborious to fill n static structures with the limit
997 * when a simple if statement does the job,
998 * - run-time checks (eg read fuse/strap registers) are needed.
999 *
1000 * This function needs to be called:
1001 * - after the MMIO has been setup as we are reading registers,
1002 * - after the PCH has been detected,
1003 * - before the first usage of the fields it can tweak.
1004 */
1005static void intel_device_info_runtime_init(struct drm_device *dev)
1006{
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 struct intel_device_info *info;
1009 enum pipe pipe;
1010
1011 info = (struct intel_device_info *)&dev_priv->info;
1012
1013 /*
1014 * Skylake and Broxton currently don't expose the topmost plane as its
1015 * use is exclusive with the legacy cursor and we only want to expose
1016 * one of those, not both. Until we can safely expose the topmost plane
1017 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
1018 * we don't expose the topmost plane at all to prevent ABI breakage
1019 * down the line.
1020 */
1021 if (IS_BROXTON(dev)) {
1022 info->num_sprites[PIPE_A] = 2;
1023 info->num_sprites[PIPE_B] = 2;
1024 info->num_sprites[PIPE_C] = 1;
1025 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1026 for_each_pipe(dev_priv, pipe)
1027 info->num_sprites[pipe] = 2;
1028 else
1029 for_each_pipe(dev_priv, pipe)
1030 info->num_sprites[pipe] = 1;
1031
1032 if (i915.disable_display) {
1033 DRM_INFO("Display disabled (module parameter)\n");
1034 info->num_pipes = 0;
1035 } else if (info->num_pipes > 0 &&
1036 (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
1037 HAS_PCH_SPLIT(dev)) {
1038 u32 fuse_strap = I915_READ(FUSE_STRAP);
1039 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1040
1041 /*
1042 * SFUSE_STRAP is supposed to have a bit signalling the display
1043 * is fused off. Unfortunately it seems that, at least in
1044 * certain cases, fused off display means that PCH display
1045 * reads don't land anywhere. In that case, we read 0s.
1046 *
1047 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1048 * should be set when taking over after the firmware.
1049 */
1050 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1051 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1052 (dev_priv->pch_type == PCH_CPT &&
1053 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1054 DRM_INFO("Display fused off, disabling\n");
1055 info->num_pipes = 0;
1056 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
1057 DRM_INFO("PipeC fused off\n");
1058 info->num_pipes -= 1;
1059 }
1060 } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
1061 u32 dfsm = I915_READ(SKL_DFSM);
1062 u8 disabled_mask = 0;
1063 bool invalid;
1064 int num_bits;
1065
1066 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
1067 disabled_mask |= BIT(PIPE_A);
1068 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
1069 disabled_mask |= BIT(PIPE_B);
1070 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
1071 disabled_mask |= BIT(PIPE_C);
1072
1073 num_bits = hweight8(disabled_mask);
1074
1075 switch (disabled_mask) {
1076 case BIT(PIPE_A):
1077 case BIT(PIPE_B):
1078 case BIT(PIPE_A) | BIT(PIPE_B):
1079 case BIT(PIPE_A) | BIT(PIPE_C):
1080 invalid = true;
1081 break;
1082 default:
1083 invalid = false;
1084 }
1085
1086 if (num_bits > info->num_pipes || invalid)
1087 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
1088 disabled_mask);
1089 else
1090 info->num_pipes -= num_bits;
1091 }
1092
1093 /* Initialize slice/subslice/EU info */
1094 if (IS_CHERRYVIEW(dev))
1095 cherryview_sseu_info_init(dev);
1096 else if (IS_BROADWELL(dev))
1097 broadwell_sseu_info_init(dev);
1098 else if (INTEL_INFO(dev)->gen >= 9)
1099 gen9_sseu_info_init(dev);
1100
1101 info->has_snoop = !info->has_llc;
1102
1103 /* Snooping is broken on BXT A stepping. */
1104 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1105 info->has_snoop = false;
1106
1107 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
1108 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
1109 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
1110 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
1111 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
1112 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
1113 info->has_slice_pg ? "y" : "n");
1114 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
1115 info->has_subslice_pg ? "y" : "n");
1116 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
1117 info->has_eu_pg ? "y" : "n");
1118
1119 i915.enable_execlists =
1120 intel_sanitize_enable_execlists(dev_priv,
1121 i915.enable_execlists);
1122
1123 /*
1124 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1125 * user's requested state against the hardware/driver capabilities. We
1126 * do this now so that we can print out any log messages once rather
1127 * than every time we check intel_enable_ppgtt().
1128 */
1129 i915.enable_ppgtt =
1130 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1131 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1132}
1133
1134static void intel_init_dpio(struct drm_i915_private *dev_priv)
1135{
1136 /*
1137 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1138 * CHV x1 PHY (DP/HDMI D)
1139 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1140 */
1141 if (IS_CHERRYVIEW(dev_priv)) {
1142 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1143 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1144 } else if (IS_VALLEYVIEW(dev_priv)) {
1145 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1146 }
1147}
1148
1149static int i915_workqueues_init(struct drm_i915_private *dev_priv)
1150{
1151 /*
1152 * The i915 workqueue is primarily used for batched retirement of
1153 * requests (and thus managing bo) once the task has been completed
1154 * by the GPU. i915_gem_retire_requests() is called directly when we
1155 * need high-priority retirement, such as waiting for an explicit
1156 * bo.
1157 *
1158 * It is also used for periodic low-priority events, such as
1159 * idle-timers and recording error state.
1160 *
1161 * All tasks on the workqueue are expected to acquire the dev mutex
1162 * so there is no point in running more than one instance of the
1163 * workqueue at any time. Use an ordered one.
1164 */
1165 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1166 if (dev_priv->wq == NULL)
1167 goto out_err;
1168
1169 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1170 if (dev_priv->hotplug.dp_wq == NULL)
1171 goto out_free_wq;
1172
1173 dev_priv->gpu_error.hangcheck_wq =
1174 alloc_ordered_workqueue("i915-hangcheck", 0);
1175 if (dev_priv->gpu_error.hangcheck_wq == NULL)
1176 goto out_free_dp_wq;
1177
1178 return 0;
1179
1180out_free_dp_wq:
1181 destroy_workqueue(dev_priv->hotplug.dp_wq);
1182out_free_wq:
1183 destroy_workqueue(dev_priv->wq);
1184out_err:
1185 DRM_ERROR("Failed to allocate workqueues.\n");
1186
1187 return -ENOMEM;
1188}
1189
1190static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
1191{
1192 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1193 destroy_workqueue(dev_priv->hotplug.dp_wq);
1194 destroy_workqueue(dev_priv->wq);
1195}
1196
1197/**
1198 * i915_driver_init_early - setup state not requiring device access
1199 * @dev_priv: device private
1200 *
1201 * Initialize everything that is a "SW-only" state, that is state not
1202 * requiring accessing the device or exposing the driver via kernel internal
1203 * or userspace interfaces. Example steps belonging here: lock initialization,
1204 * system memory allocation, setting up device specific attributes and
1205 * function hooks not requiring accessing the device.
1206 */
1207static int i915_driver_init_early(struct drm_i915_private *dev_priv,
1208 const struct pci_device_id *ent)
1209{
1210 const struct intel_device_info *match_info =
1211 (struct intel_device_info *)ent->driver_data;
1212 struct intel_device_info *device_info;
1213 int ret = 0;
1214
1215 if (i915_inject_load_failure())
1216 return -ENODEV;
1217
1218 /* Setup the write-once "constant" device info */
1219 device_info = (struct intel_device_info *)&dev_priv->info;
1220 memcpy(device_info, match_info, sizeof(*device_info));
1221 device_info->device_id = dev_priv->drm.pdev->device;
1222
1223 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
1224 device_info->gen_mask = BIT(device_info->gen - 1);
1225
1226 spin_lock_init(&dev_priv->irq_lock);
1227 spin_lock_init(&dev_priv->gpu_error.lock);
1228 mutex_init(&dev_priv->backlight_lock);
1229 spin_lock_init(&dev_priv->uncore.lock);
1230 spin_lock_init(&dev_priv->mm.object_stat_lock);
1231 spin_lock_init(&dev_priv->mmio_flip_lock);
1232 mutex_init(&dev_priv->sb_lock);
1233 mutex_init(&dev_priv->modeset_restore_lock);
1234 mutex_init(&dev_priv->av_mutex);
1235 mutex_init(&dev_priv->wm.wm_mutex);
1236 mutex_init(&dev_priv->pps_mutex);
1237
1238 ret = i915_workqueues_init(dev_priv);
1239 if (ret < 0)
1240 return ret;
1241
1242 ret = intel_gvt_init(dev_priv);
1243 if (ret < 0)
1244 goto err_workqueues;
1245
1246 /* This must be called before any calls to HAS_PCH_* */
1247 intel_detect_pch(&dev_priv->drm);
1248
1249 intel_pm_setup(&dev_priv->drm);
1250 intel_init_dpio(dev_priv);
1251 intel_power_domains_init(dev_priv);
1252 intel_irq_init(dev_priv);
1253 intel_init_display_hooks(dev_priv);
1254 intel_init_clock_gating_hooks(dev_priv);
1255 intel_init_audio_hooks(dev_priv);
1256 i915_gem_load_init(&dev_priv->drm);
1257
1258 intel_display_crc_init(&dev_priv->drm);
1259
1260 i915_dump_device_info(dev_priv);
1261
1262 /* Not all pre-production machines fall into this category, only the
1263 * very first ones. Almost everything should work, except for maybe
1264 * suspend/resume. And we don't implement workarounds that affect only
1265 * pre-production machines. */
1266 if (IS_HSW_EARLY_SDV(dev_priv))
1267 DRM_INFO("This is an early pre-production Haswell machine. "
1268 "It may not be fully functional.\n");
1269
1270 return 0;
1271
1272err_workqueues:
1273 i915_workqueues_cleanup(dev_priv);
1274 return ret;
1275}
1276
1277/**
1278 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
1279 * @dev_priv: device private
1280 */
1281static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
1282{
1283 i915_gem_load_cleanup(dev_priv->dev);
1284 i915_workqueues_cleanup(dev_priv);
1285}
1286
1287static int i915_mmio_setup(struct drm_device *dev)
1288{
1289 struct drm_i915_private *dev_priv = to_i915(dev);
1290 int mmio_bar;
1291 int mmio_size;
1292
1293 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1294 /*
1295 * Before gen4, the registers and the GTT are behind different BARs.
1296 * However, from gen4 onwards, the registers and the GTT are shared
1297 * in the same BAR, so we want to restrict this ioremap from
1298 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1299 * the register BAR remains the same size for all the earlier
1300 * generations up to Ironlake.
1301 */
1302 if (INTEL_INFO(dev)->gen < 5)
1303 mmio_size = 512 * 1024;
1304 else
1305 mmio_size = 2 * 1024 * 1024;
1306 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1307 if (dev_priv->regs == NULL) {
1308 DRM_ERROR("failed to map registers\n");
1309
1310 return -EIO;
1311 }
1312
1313 /* Try to make sure MCHBAR is enabled before poking at it */
1314 intel_setup_mchbar(dev);
1315
1316 return 0;
1317}
1318
1319static void i915_mmio_cleanup(struct drm_device *dev)
1320{
1321 struct drm_i915_private *dev_priv = to_i915(dev);
1322
1323 intel_teardown_mchbar(dev);
1324 pci_iounmap(dev->pdev, dev_priv->regs);
1325}
1326
1327/**
1328 * i915_driver_init_mmio - setup device MMIO
1329 * @dev_priv: device private
1330 *
1331 * Setup minimal device state necessary for MMIO accesses later in the
1332 * initialization sequence. The setup here should avoid any other device-wide
1333 * side effects or exposing the driver via kernel internal or user space
1334 * interfaces.
1335 */
1336static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1337{
1338 struct drm_device *dev = dev_priv->dev;
1339 int ret;
1340
1341 if (i915_inject_load_failure())
1342 return -ENODEV;
1343
1344 if (i915_get_bridge_dev(dev))
1345 return -EIO;
1346
1347 ret = i915_mmio_setup(dev);
1348 if (ret < 0)
1349 goto put_bridge;
1350
1351 intel_uncore_init(dev_priv);
1352
1353 return 0;
1354
1355put_bridge:
1356 pci_dev_put(dev_priv->bridge_dev);
1357
1358 return ret;
1359}
1360
1361/**
1362 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1363 * @dev_priv: device private
1364 */
1365static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1366{
1367 struct drm_device *dev = dev_priv->dev;
1368
1369 intel_uncore_fini(dev_priv);
1370 i915_mmio_cleanup(dev);
1371 pci_dev_put(dev_priv->bridge_dev);
1372}
1373
1374/**
1375 * i915_driver_init_hw - setup state requiring device access
1376 * @dev_priv: device private
1377 *
1378 * Setup state that requires accessing the device, but doesn't require
1379 * exposing the driver via kernel internal or userspace interfaces.
1380 */
1381static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1382{
1383 struct drm_device *dev = dev_priv->dev;
1384 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1385 uint32_t aperture_size;
1386 int ret;
1387
1388 if (i915_inject_load_failure())
1389 return -ENODEV;
1390
1391 intel_device_info_runtime_init(dev);
1392
1393 ret = i915_ggtt_init_hw(dev);
1394 if (ret)
1395 return ret;
1396
1397 ret = i915_ggtt_enable_hw(dev);
1398 if (ret) {
1399 DRM_ERROR("failed to enable GGTT\n");
1400 goto out_ggtt;
1401 }
1402
1403 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1404 * otherwise the vga fbdev driver falls over. */
1405 ret = i915_kick_out_firmware_fb(dev_priv);
1406 if (ret) {
1407 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1408 goto out_ggtt;
1409 }
1410
1411 ret = i915_kick_out_vgacon(dev_priv);
1412 if (ret) {
1413 DRM_ERROR("failed to remove conflicting VGA console\n");
1414 goto out_ggtt;
1415 }
1416
1417 pci_set_master(dev->pdev);
1418
1419 /* overlay on gen2 is broken and can't address above 1G */
1420 if (IS_GEN2(dev)) {
1421 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1422 if (ret) {
1423 DRM_ERROR("failed to set DMA mask\n");
1424
1425 goto out_ggtt;
1426 }
1427 }
1428
1429
1430 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1431 * using 32bit addressing, overwriting memory if HWS is located
1432 * above 4GB.
1433 *
1434 * The documentation also mentions an issue with undefined
1435 * behaviour if any general state is accessed within a page above 4GB,
1436 * which also needs to be handled carefully.
1437 */
1438 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1439 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1440
1441 if (ret) {
1442 DRM_ERROR("failed to set DMA mask\n");
1443
1444 goto out_ggtt;
1445 }
1446 }
1447
1448 aperture_size = ggtt->mappable_end;
1449
1450 ggtt->mappable =
1451 io_mapping_create_wc(ggtt->mappable_base,
1452 aperture_size);
1453 if (!ggtt->mappable) {
1454 ret = -EIO;
1455 goto out_ggtt;
1456 }
1457
1458 ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1459 aperture_size);
1460
1461 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1462 PM_QOS_DEFAULT_VALUE);
1463
1464 intel_uncore_sanitize(dev_priv);
1465
1466 intel_opregion_setup(dev_priv);
1467
1468 i915_gem_load_init_fences(dev_priv);
1469
1470 /* On the 945G/GM, the chipset reports the MSI capability on the
1471 * integrated graphics even though the support isn't actually there
1472 * according to the published specs. It doesn't appear to function
1473 * correctly in testing on 945G.
1474 * This may be a side effect of MSI having been made available for PEG
1475 * and the registers being closely associated.
1476 *
1477 * According to chipset errata, on the 965GM, MSI interrupts may
1478 * be lost or delayed, but we use them anyways to avoid
1479 * stuck interrupts on some machines.
1480 */
1481 if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1482 if (pci_enable_msi(dev->pdev) < 0)
1483 DRM_DEBUG_DRIVER("can't enable MSI");
1484 }
1485
1486 return 0;
1487
1488out_ggtt:
1489 i915_ggtt_cleanup_hw(dev);
1490
1491 return ret;
1492}
1493
1494/**
1495 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1496 * @dev_priv: device private
1497 */
1498static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1499{
1500 struct drm_device *dev = dev_priv->dev;
1501 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1502
1503 if (dev->pdev->msi_enabled)
1504 pci_disable_msi(dev->pdev);
1505
1506 pm_qos_remove_request(&dev_priv->pm_qos);
1507 arch_phys_wc_del(ggtt->mtrr);
1508 io_mapping_free(ggtt->mappable);
1509 i915_ggtt_cleanup_hw(dev);
1510}
1511
1512/**
1513 * i915_driver_register - register the driver with the rest of the system
1514 * @dev_priv: device private
1515 *
1516 * Perform any steps necessary to make the driver available via kernel
1517 * internal or userspace interfaces.
1518 */
1519static void i915_driver_register(struct drm_i915_private *dev_priv)
1520{
1521 struct drm_device *dev = dev_priv->dev;
1522
1523 i915_gem_shrinker_init(dev_priv);
1524
1525 /*
1526 * Notify a valid surface after modesetting,
1527 * when running inside a VM.
1528 */
1529 if (intel_vgpu_active(dev_priv))
1530 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1531
1532 /* Reveal our presence to userspace */
1533 if (drm_dev_register(dev, 0) == 0) {
1534 i915_debugfs_register(dev_priv);
1535 i915_setup_sysfs(dev);
1536 } else
1537 DRM_ERROR("Failed to register driver for userspace access!\n");
1538
1539 if (INTEL_INFO(dev_priv)->num_pipes) {
1540 /* Must be done after probing outputs */
1541 intel_opregion_register(dev_priv);
1542 acpi_video_register();
1543 }
1544
1545 if (IS_GEN5(dev_priv))
1546 intel_gpu_ips_init(dev_priv);
1547
1548 i915_audio_component_init(dev_priv);
1549
1550 /*
1551 * Some ports require correctly set-up hpd registers for detection to
1552 * work properly (leading to ghost connected connector status), e.g. VGA
1553 * on gm45. Hence we can only set up the initial fbdev config after hpd
1554 * irqs are fully enabled. We do it last so that the async config
1555 * cannot run before the connectors are registered.
1556 */
1557 intel_fbdev_initial_config_async(dev);
1558}
1559
1560/**
1561 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1562 * @dev_priv: device private
1563 */
1564static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1565{
1566 i915_audio_component_cleanup(dev_priv);
1567
1568 intel_gpu_ips_teardown();
1569 acpi_video_unregister();
1570 intel_opregion_unregister(dev_priv);
1571
1572 i915_teardown_sysfs(dev_priv->dev);
1573 i915_debugfs_unregister(dev_priv);
1574 drm_dev_unregister(dev_priv->dev);
1575
1576 i915_gem_shrinker_cleanup(dev_priv);
1577}
1578
1579/**
1580 * i915_driver_load - setup chip and create an initial config
1581 * @dev: DRM device
1582 * @flags: startup flags
1583 *
1584 * The driver load routine has to do several things:
1585 * - drive output discovery via intel_modeset_init()
1586 * - initialize the memory manager
1587 * - allocate initial config memory
1588 * - setup the DRM framebuffer with the allocated memory
1589 */
42f5551d 1590int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47
CW		 1591{
1592 struct drm_i915_private *dev_priv;
1593 int ret;
7d87a7f7 1594
0673ad47
CW		 1595 ret = -ENOMEM;
1596 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1597 if (dev_priv)
1598 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1599 if (ret) {
1600 dev_printk(KERN_ERR, &pdev->dev,
1601 "[" DRM_NAME ":%s] allocation failed\n", __func__);
1602 kfree(dev_priv);
1603 return ret;
1604 }
72bbf0af 1605
0673ad47
CW		 1606 /* Must be set before calling __i915_printk */
1607 dev_priv->drm.pdev = pdev;
1608 dev_priv->drm.dev_private = dev_priv;
1609 dev_priv->dev = &dev_priv->drm;
719388e1 1610
0673ad47
CW		 1611 ret = pci_enable_device(pdev);
1612 if (ret)
1613 goto out_free_priv;
1347f5b4 1614
0673ad47 1615 pci_set_drvdata(pdev, &dev_priv->drm);
ef11bdb3 1616
0673ad47
CW		 1617 ret = i915_driver_init_early(dev_priv, ent);
1618 if (ret < 0)
1619 goto out_pci_disable;
ef11bdb3 1620
0673ad47 1621 intel_runtime_pm_get(dev_priv);
1da177e4 1622
0673ad47
CW		 1623 ret = i915_driver_init_mmio(dev_priv);
1624 if (ret < 0)
1625 goto out_runtime_pm_put;
79e53945 1626
0673ad47
CW		 1627 ret = i915_driver_init_hw(dev_priv);
1628 if (ret < 0)
1629 goto out_cleanup_mmio;
30c964a6
RB		 1630
1631 /*
0673ad47
CW		 1632 * TODO: move the vblank init and parts of modeset init steps into one
1633 * of the i915_driver_init_/i915_driver_register functions according
1634 * to the role/effect of the given init step.
30c964a6 1635 */
0673ad47
CW		 1636 if (INTEL_INFO(dev_priv)->num_pipes) {
1637 ret = drm_vblank_init(dev_priv->dev,
1638 INTEL_INFO(dev_priv)->num_pipes);
1639 if (ret)
1640 goto out_cleanup_hw;
30c964a6
RB		 1641 }
1642
0673ad47
CW		 1643 ret = i915_load_modeset_init(dev_priv->dev);
1644 if (ret < 0)
1645 goto out_cleanup_vblank;
1646
1647 i915_driver_register(dev_priv);
1648
1649 intel_runtime_pm_enable(dev_priv);
1650
1651 intel_runtime_pm_put(dev_priv);
1652
1653 return 0;
1654
1655out_cleanup_vblank:
1656 drm_vblank_cleanup(dev_priv->dev);
1657out_cleanup_hw:
1658 i915_driver_cleanup_hw(dev_priv);
1659out_cleanup_mmio:
1660 i915_driver_cleanup_mmio(dev_priv);
1661out_runtime_pm_put:
1662 intel_runtime_pm_put(dev_priv);
1663 i915_driver_cleanup_early(dev_priv);
1664out_pci_disable:
1665 pci_disable_device(pdev);
1666out_free_priv:
1667 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1668 drm_dev_unref(&dev_priv->drm);
30c964a6
RB		 1669 return ret;
1670}
1671
42f5551d 1672void i915_driver_unload(struct drm_device *dev)
3bad0781
ZW		 1673{
1674 struct drm_i915_private *dev_priv = dev->dev_private;
3bad0781 1675
0673ad47
CW		 1676 intel_fbdev_fini(dev);
1677
42f5551d
CW		 1678 if (i915_gem_suspend(dev))
1679 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1680
0673ad47
CW		 1681 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1682
1683 i915_driver_unregister(dev_priv);
1684
1685 drm_vblank_cleanup(dev);
1686
1687 intel_modeset_cleanup(dev);
1688
3bad0781 1689 /*
0673ad47
CW		 1690 * free the memory space allocated for the child device
1691 * config parsed from VBT
3bad0781 1692 */
0673ad47
CW		 1693 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1694 kfree(dev_priv->vbt.child_dev);
1695 dev_priv->vbt.child_dev = NULL;
1696 dev_priv->vbt.child_dev_num = 0;
1697 }
1698 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1699 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1700 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1701 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1702
0673ad47
CW		 1703 vga_switcheroo_unregister_client(dev->pdev);
1704 vga_client_register(dev->pdev, NULL, NULL, NULL);
bcdb72ac 1705
0673ad47 1706 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1707
0673ad47
CW		 1708 /* Free error state after interrupts are fully disabled. */
1709 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1710 i915_destroy_error_state(dev);
1711
1712 /* Flush any outstanding unpin_work. */
1713 flush_workqueue(dev_priv->wq);
1714
1715 intel_guc_fini(dev);
1716 i915_gem_fini(dev);
1717 intel_fbc_cleanup_cfb(dev_priv);
1718
1719 intel_power_domains_fini(dev_priv);
1720
1721 i915_driver_cleanup_hw(dev_priv);
1722 i915_driver_cleanup_mmio(dev_priv);
1723
1724 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1725
1726 i915_driver_cleanup_early(dev_priv);
3bad0781
ZW		 1727}
1728
0673ad47 1729static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1730{
0673ad47 1731 int ret;
2911a35b 1732
0673ad47
CW		 1733 ret = i915_gem_open(dev, file);
1734 if (ret)
1735 return ret;
2911a35b 1736
0673ad47
CW		 1737 return 0;
1738}
71386ef9 1739
0673ad47
CW		 1740/**
1741 * i915_driver_lastclose - clean up after all DRM clients have exited
1742 * @dev: DRM device
1743 *
1744 * Take care of cleaning up after all DRM clients have exited. In the
1745 * mode setting case, we want to restore the kernel's initial mode (just
1746 * in case the last client left us in a bad state).
1747 *
1748 * Additionally, in the non-mode setting case, we'll tear down the GTT
1749 * and DMA structures, since the kernel won't be using them, and clea
1750 * up any GEM state.
1751 */
1752static void i915_driver_lastclose(struct drm_device *dev)
1753{
1754 intel_fbdev_restore_mode(dev);
1755 vga_switcheroo_process_delayed_switch();
1756}
2911a35b 1757
0673ad47
CW		 1758static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1759{
1760 mutex_lock(&dev->struct_mutex);
1761 i915_gem_context_close(dev, file);
1762 i915_gem_release(dev, file);
1763 mutex_unlock(&dev->struct_mutex);
1764}
1765
1766static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1767{
1768 struct drm_i915_file_private *file_priv = file->driver_priv;
1769
1770 kfree(file_priv);
2911a35b
BW		 1771}
1772
07f9cd0b
ID		 1773static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1774{
1775 struct drm_device *dev = dev_priv->dev;
19c8054c 1776 struct intel_encoder *encoder;
07f9cd0b
ID		 1777
1778 drm_modeset_lock_all(dev);
19c8054c
JN		 1779 for_each_intel_encoder(dev, encoder)
1780 if (encoder->suspend)
1781 encoder->suspend(encoder);
07f9cd0b
ID		 1782 drm_modeset_unlock_all(dev);
1783}
1784
1a5df187
PZ		 1785static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1786 bool rpm_resume);
507e126e 1787static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1788
bc87229f
ID		 1789static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1790{
1791#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1792 if (acpi_target_system_state() < ACPI_STATE_S3)
1793 return true;
1794#endif
1795 return false;
1796}
ebc32824 1797
5e365c39 1798static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1799{
61caf87c 1800 struct drm_i915_private *dev_priv = dev->dev_private;
e5747e3a 1801 pci_power_t opregion_target_state;
d5818938 1802 int error;
61caf87c 1803
b8efb17b
ZR		 1804 /* ignore lid events during suspend */
1805 mutex_lock(&dev_priv->modeset_restore_lock);
1806 dev_priv->modeset_restore = MODESET_SUSPENDED;
1807 mutex_unlock(&dev_priv->modeset_restore_lock);
1808
1f814dac
ID		 1809 disable_rpm_wakeref_asserts(dev_priv);
1810
c67a470b
PZ		 1811 /* We do a lot of poking in a lot of registers, make sure they work
1812 * properly. */
da7e29bd 1813 intel_display_set_init_power(dev_priv, true);
cb10799c 1814
5bcf719b
DA		 1815 drm_kms_helper_poll_disable(dev);
1816
ba8bbcf6 1817 pci_save_state(dev->pdev);
ba8bbcf6 1818
d5818938
DV		 1819 error = i915_gem_suspend(dev);
1820 if (error) {
1821 dev_err(&dev->pdev->dev,
1822 "GEM idle failed, resume might fail\n");
1f814dac 1823 goto out;
d5818938 1824 }
db1b76ca 1825
a1c41994
AD		 1826 intel_guc_suspend(dev);
1827
dc97997a 1828 intel_suspend_gt_powersave(dev_priv);
a261b246 1829
6b72d486 1830 intel_display_suspend(dev);
2eb5252e 1831
d5818938 1832 intel_dp_mst_suspend(dev);
7d708ee4 1833
d5818938
DV		 1834 intel_runtime_pm_disable_interrupts(dev_priv);
1835 intel_hpd_cancel_work(dev_priv);
09b64267 1836
d5818938 1837 intel_suspend_encoders(dev_priv);
0e32b39c 1838
d5818938 1839 intel_suspend_hw(dev);
5669fcac 1840
828c7908
BW		 1841 i915_gem_suspend_gtt_mappings(dev);
1842
9e06dd39
JB		 1843 i915_save_state(dev);
1844
bc87229f 1845 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1846 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1847
dc97997a 1848 intel_uncore_forcewake_reset(dev_priv, false);
03d92e47 1849 intel_opregion_unregister(dev_priv);
8ee1c3db 1850
82e3b8c1 1851 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1852
62d5d69b
MK		 1853 dev_priv->suspend_count++;
1854
85e90679
KCA		 1855 intel_display_set_init_power(dev_priv, false);
1856
f74ed08d 1857 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1858
1f814dac
ID		 1859out:
1860 enable_rpm_wakeref_asserts(dev_priv);
1861
1862 return error;
84b79f8d
RW		 1863}
1864
ab3be73f 1865static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
c3c09c95
ID		 1866{
1867 struct drm_i915_private *dev_priv = drm_dev->dev_private;
bc87229f 1868 bool fw_csr;
c3c09c95
ID		 1869 int ret;
1870
1f814dac
ID		 1871 disable_rpm_wakeref_asserts(dev_priv);
1872
a7c8125f
ID		 1873 fw_csr = !IS_BROXTON(dev_priv) &&
1874 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1875 /*
1876 * In case of firmware assisted context save/restore don't manually
1877 * deinit the power domains. This also means the CSR/DMC firmware will
1878 * stay active, it will power down any HW resources as required and
1879 * also enable deeper system power states that would be blocked if the
1880 * firmware was inactive.
1881 */
1882 if (!fw_csr)
1883 intel_power_domains_suspend(dev_priv);
73dfc227 1884
507e126e 1885 ret = 0;
b8aea3d1 1886 if (IS_BROXTON(dev_priv))
507e126e 1887 bxt_enable_dc9(dev_priv);
b8aea3d1 1888 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1889 hsw_enable_pc8(dev_priv);
1890 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1891 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1892
1893 if (ret) {
1894 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1895 if (!fw_csr)
1896 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1897
1f814dac 1898 goto out;
c3c09c95
ID		 1899 }
1900
1901 pci_disable_device(drm_dev->pdev);
ab3be73f 1902 /*
54875571 1903 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1904 * the device even though it's already in D3 and hang the machine. So
1905 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1906 * power down the device properly. The issue was seen on multiple old
1907 * GENs with different BIOS vendors, so having an explicit blacklist
1908 * is inpractical; apply the workaround on everything pre GEN6. The
1909 * platforms where the issue was seen:
1910 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1911 * Fujitsu FSC S7110
1912 * Acer Aspire 1830T
ab3be73f 1913 */
54875571 1914 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
ab3be73f 1915 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
c3c09c95 1916
bc87229f
ID		 1917 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1918
1f814dac
ID		 1919out:
1920 enable_rpm_wakeref_asserts(dev_priv);
1921
1922 return ret;
c3c09c95
ID		 1923}
1924
1751fcf9 1925int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1926{
1927 int error;
1928
1929 if (!dev || !dev->dev_private) {
1930 DRM_ERROR("dev: %p\n", dev);
1931 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1932 return -ENODEV;
1933 }
1934
0b14cbd2
ID		 1935 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1936 state.event != PM_EVENT_FREEZE))
1937 return -EINVAL;
5bcf719b
DA		 1938
1939 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1940 return 0;
6eecba33 1941
5e365c39 1942 error = i915_drm_suspend(dev);
84b79f8d
RW		 1943 if (error)
1944 return error;
1945
ab3be73f 1946 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1947}
1948
5e365c39 1949static int i915_drm_resume(struct drm_device *dev)
76c4b250
ID		 1950{
1951 struct drm_i915_private *dev_priv = dev->dev_private;
ac840ae5 1952 int ret;
9d49c0ef 1953
1f814dac
ID		 1954 disable_rpm_wakeref_asserts(dev_priv);
1955
ac840ae5
VS		 1956 ret = i915_ggtt_enable_hw(dev);
1957 if (ret)
1958 DRM_ERROR("failed to re-enable GGTT\n");
1959
f74ed08d
ID		 1960 intel_csr_ucode_resume(dev_priv);
1961
d5818938
DV		 1962 mutex_lock(&dev->struct_mutex);
1963 i915_gem_restore_gtt_mappings(dev);
1964 mutex_unlock(&dev->struct_mutex);
9d49c0ef 1965
61caf87c 1966 i915_restore_state(dev);
6f9f4b7a 1967 intel_opregion_setup(dev_priv);
61caf87c 1968
d5818938
DV		 1969 intel_init_pch_refclk(dev);
1970 drm_mode_config_reset(dev);
1833b134 1971
364aece0
PA		 1972 /*
1973 * Interrupts have to be enabled before any batches are run. If not the
1974 * GPU will hang. i915_gem_init_hw() will initiate batches to
1975 * update/restore the context.
1976 *
1977 * Modeset enabling in intel_modeset_init_hw() also needs working
1978 * interrupts.
1979 */
1980 intel_runtime_pm_enable_interrupts(dev_priv);
1981
d5818938
DV		 1982 mutex_lock(&dev->struct_mutex);
1983 if (i915_gem_init_hw(dev)) {
1984 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
805de8f4 1985 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
d5818938
DV		 1986 }
1987 mutex_unlock(&dev->struct_mutex);
226485e9 1988
a1c41994
AD		 1989 intel_guc_resume(dev);
1990
d5818938 1991 intel_modeset_init_hw(dev);
24576d23 1992
d5818938
DV		 1993 spin_lock_irq(&dev_priv->irq_lock);
1994 if (dev_priv->display.hpd_irq_setup)
91d14251 1995 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1996 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1997
d5818938 1998 intel_dp_mst_resume(dev);
e7d6f7d7 1999
a16b7658
L		 2000 intel_display_resume(dev);
2001
d5818938
DV		 2002 /*
2003 * ... but also need to make sure that hotplug processing
2004 * doesn't cause havoc. Like in the driver load code we don't
2005 * bother with the tiny race here where we might loose hotplug
2006 * notifications.
2007 * */
2008 intel_hpd_init(dev_priv);
2009 /* Config may have changed between suspend and resume */
2010 drm_helper_hpd_irq_event(dev);
1daed3fb 2011
03d92e47 2012 intel_opregion_register(dev_priv);
44834a67 2013
82e3b8c1 2014 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 2015
b8efb17b
ZR		 2016 mutex_lock(&dev_priv->modeset_restore_lock);
2017 dev_priv->modeset_restore = MODESET_DONE;
2018 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 2019
6f9f4b7a 2020 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 2021
ee6f280e
ID		 2022 drm_kms_helper_poll_enable(dev);
2023
1f814dac
ID		 2024 enable_rpm_wakeref_asserts(dev_priv);
2025
074c6ada 2026 return 0;
84b79f8d
RW		 2027}
2028
5e365c39 2029static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 2030{
36d61e67 2031 struct drm_i915_private *dev_priv = dev->dev_private;
44410cd0 2032 int ret;
36d61e67 2033
76c4b250
ID		 2034 /*
2035 * We have a resume ordering issue with the snd-hda driver also
2036 * requiring our device to be power up. Due to the lack of a
2037 * parent/child relationship we currently solve this with an early
2038 * resume hook.
2039 *
2040 * FIXME: This should be solved with a special hdmi sink device or
2041 * similar so that power domains can be employed.
2042 */
44410cd0
ID		 2043
2044 /*
2045 * Note that we need to set the power state explicitly, since we
2046 * powered off the device during freeze and the PCI core won't power
2047 * it back up for us during thaw. Powering off the device during
2048 * freeze is not a hard requirement though, and during the
2049 * suspend/resume phases the PCI core makes sure we get here with the
2050 * device powered on. So in case we change our freeze logic and keep
2051 * the device powered we can also remove the following set power state
2052 * call.
2053 */
2054 ret = pci_set_power_state(dev->pdev, PCI_D0);
2055 if (ret) {
2056 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2057 goto out;
2058 }
2059
2060 /*
2061 * Note that pci_enable_device() first enables any parent bridge
2062 * device and only then sets the power state for this device. The
2063 * bridge enabling is a nop though, since bridge devices are resumed
2064 * first. The order of enabling power and enabling the device is
2065 * imposed by the PCI core as described above, so here we preserve the
2066 * same order for the freeze/thaw phases.
2067 *
2068 * TODO: eventually we should remove pci_disable_device() /
2069 * pci_enable_enable_device() from suspend/resume. Due to how they
2070 * depend on the device enable refcount we can't anyway depend on them
2071 * disabling/enabling the device.
2072 */
bc87229f
ID		 2073 if (pci_enable_device(dev->pdev)) {
2074 ret = -EIO;
2075 goto out;
2076 }
84b79f8d
RW		 2077
2078 pci_set_master(dev->pdev);
2079
1f814dac
ID		 2080 disable_rpm_wakeref_asserts(dev_priv);
2081
666a4537 2082 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 2083 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 2084 if (ret)
ff0b187f
DL		 2085 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2086 ret);
36d61e67 2087
dc97997a 2088 intel_uncore_early_sanitize(dev_priv, true);
efee833a 2089
dc97997a 2090 if (IS_BROXTON(dev_priv)) {
da2f41d1
ID		 2091 if (!dev_priv->suspended_to_idle)
2092 gen9_sanitize_dc_state(dev_priv);
507e126e 2093 bxt_disable_dc9(dev_priv);
da2f41d1 2094 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 2095 hsw_disable_pc8(dev_priv);
da2f41d1 2096 }
efee833a 2097
dc97997a 2098 intel_uncore_sanitize(dev_priv);
bc87229f 2099
a7c8125f
ID		 2100 if (IS_BROXTON(dev_priv) ||
2101 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 2102 intel_power_domains_init_hw(dev_priv, true);
2103
6e35e8ab
ID		 2104 enable_rpm_wakeref_asserts(dev_priv);
2105
bc87229f
ID		 2106out:
2107 dev_priv->suspended_to_idle = false;
36d61e67
ID		 2108
2109 return ret;
76c4b250
ID		 2110}
2111
1751fcf9 2112int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 2113{
50a0072f 2114 int ret;
76c4b250 2115
097dd837
ID		 2116 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2117 return 0;
2118
5e365c39 2119 ret = i915_drm_resume_early(dev);
50a0072f
ID		 2120 if (ret)
2121 return ret;
2122
5a17514e
ID		 2123 return i915_drm_resume(dev);
2124}
2125
11ed50ec 2126/**
f3953dcb 2127 * i915_reset - reset chip after a hang
11ed50ec 2128 * @dev: drm device to reset
11ed50ec
BG		 2129 *
2130 * Reset the chip. Useful if a hang is detected. Returns zero on successful
2131 * reset or otherwise an error code.
2132 *
2133 * Procedure is fairly simple:
2134 * - reset the chip using the reset reg
2135 * - re-init context state
2136 * - re-init hardware status page
2137 * - re-init ring buffer
2138 * - re-init interrupt state
2139 * - re-init display
2140 */
c033666a 2141int i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 2142{
c033666a 2143 struct drm_device *dev = dev_priv->dev;
d98c52cf
CW		 2144 struct i915_gpu_error *error = &dev_priv->gpu_error;
2145 unsigned reset_counter;
0573ed4a 2146 int ret;
11ed50ec 2147
dc97997a 2148 intel_reset_gt_powersave(dev_priv);
dbea3cea 2149
d54a02c0 2150 mutex_lock(&dev->struct_mutex);
11ed50ec 2151
d98c52cf
CW		 2152 /* Clear any previous failed attempts at recovery. Time to try again. */
2153 atomic_andnot(I915_WEDGED, &error->reset_counter);
77f01230 2154
d98c52cf
CW		 2155 /* Clear the reset-in-progress flag and increment the reset epoch. */
2156 reset_counter = atomic_inc_return(&error->reset_counter);
2157 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
2158 ret = -EIO;
2159 goto error;
2160 }
2161
2162 i915_gem_reset(dev);
2e7c8ee7 2163
dc97997a 2164 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
be62acb4
MK		 2165
2166 /* Also reset the gpu hangman. */
d98c52cf 2167 if (error->stop_rings != 0) {
be62acb4 2168 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
d98c52cf 2169 error->stop_rings = 0;
be62acb4 2170 if (ret == -ENODEV) {
f2d91a2c
DV		 2171 DRM_INFO("Reset not implemented, but ignoring "
2172 "error for simulated gpu hangs\n");
be62acb4
MK		 2173 ret = 0;
2174 }
2e7c8ee7 2175 }
be62acb4 2176
d8f2716a
DV		 2177 if (i915_stop_ring_allow_warn(dev_priv))
2178 pr_notice("drm/i915: Resetting chip after gpu hang\n");
2179
0573ed4a 2180 if (ret) {
804e59a8
CW		 2181 if (ret != -ENODEV)
2182 DRM_ERROR("Failed to reset chip: %i\n", ret);
2183 else
2184 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 2185 goto error;
11ed50ec
BG		 2186 }
2187
1362b776
VS		 2188 intel_overlay_reset(dev_priv);
2189
11ed50ec
BG		 2190 /* Ok, now get things going again... */
2191
2192 /*
2193 * Everything depends on having the GTT running, so we need to start
2194 * there. Fortunately we don't need to do this unless we reset the
2195 * chip at a PCI level.
2196 *
2197 * Next we need to restore the context, but we don't use those
2198 * yet either...
2199 *
2200 * Ring buffer needs to be re-initialized in the KMS case, or if X
2201 * was running at the time of the reset (i.e. we weren't VT
2202 * switched away).
2203 */
33d30a9c 2204 ret = i915_gem_init_hw(dev);
33d30a9c
DV		 2205 if (ret) {
2206 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 2207 goto error;
11ed50ec
BG		 2208 }
2209
d98c52cf
CW		 2210 mutex_unlock(&dev->struct_mutex);
2211
33d30a9c
DV		 2212 /*
2213 * rps/rc6 re-init is necessary to restore state lost after the
2214 * reset and the re-install of gt irqs. Skip for ironlake per
2215 * previous concerns that it doesn't respond well to some forms
2216 * of re-init after reset.
2217 */
2218 if (INTEL_INFO(dev)->gen > 5)
dc97997a 2219 intel_enable_gt_powersave(dev_priv);
33d30a9c 2220
11ed50ec 2221 return 0;
d98c52cf
CW		 2222
2223error:
2224 atomic_or(I915_WEDGED, &error->reset_counter);
2225 mutex_unlock(&dev->struct_mutex);
2226 return ret;
11ed50ec
BG		 2227}
2228
84b79f8d 2229static int i915_pm_suspend(struct device *dev)
112b715e 2230{
84b79f8d
RW		 2231 struct pci_dev *pdev = to_pci_dev(dev);
2232 struct drm_device *drm_dev = pci_get_drvdata(pdev);
112b715e 2233
84b79f8d
RW		 2234 if (!drm_dev || !drm_dev->dev_private) {
2235 dev_err(dev, "DRM not initialized, aborting suspend.\n");
2236 return -ENODEV;
2237 }
112b715e 2238
5bcf719b
DA		 2239 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2240 return 0;
2241
5e365c39 2242 return i915_drm_suspend(drm_dev);
76c4b250
ID		 2243}
2244
2245static int i915_pm_suspend_late(struct device *dev)
2246{
888d0d42 2247 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
76c4b250
ID		 2248
2249 /*
c965d995 2250 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 2251 * requiring our device to be power up. Due to the lack of a
2252 * parent/child relationship we currently solve this with an late
2253 * suspend hook.
2254 *
2255 * FIXME: This should be solved with a special hdmi sink device or
2256 * similar so that power domains can be employed.
2257 */
2258 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2259 return 0;
112b715e 2260
ab3be73f
ID		 2261 return i915_drm_suspend_late(drm_dev, false);
2262}
2263
2264static int i915_pm_poweroff_late(struct device *dev)
2265{
2266 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
2267
2268 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2269 return 0;
2270
2271 return i915_drm_suspend_late(drm_dev, true);
cbda12d7
ZW		 2272}
2273
76c4b250
ID		 2274static int i915_pm_resume_early(struct device *dev)
2275{
888d0d42 2276 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
76c4b250 2277
097dd837
ID		 2278 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2279 return 0;
2280
5e365c39 2281 return i915_drm_resume_early(drm_dev);
76c4b250
ID		 2282}
2283
84b79f8d 2284static int i915_pm_resume(struct device *dev)
cbda12d7 2285{
888d0d42 2286 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
84b79f8d 2287
097dd837
ID		 2288 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2289 return 0;
2290
5a17514e 2291 return i915_drm_resume(drm_dev);
cbda12d7
ZW		 2292}
2293
1f19ac2a
CW		 2294/* freeze: before creating the hibernation_image */
2295static int i915_pm_freeze(struct device *dev)
2296{
2297 return i915_pm_suspend(dev);
2298}
2299
2300static int i915_pm_freeze_late(struct device *dev)
2301{
461fb99c
CW		 2302 int ret;
2303
2304 ret = i915_pm_suspend_late(dev);
2305 if (ret)
2306 return ret;
2307
2308 ret = i915_gem_freeze_late(dev_to_i915(dev));
2309 if (ret)
2310 return ret;
2311
2312 return 0;
1f19ac2a
CW		 2313}
2314
2315/* thaw: called after creating the hibernation image, but before turning off. */
2316static int i915_pm_thaw_early(struct device *dev)
2317{
2318 return i915_pm_resume_early(dev);
2319}
2320
2321static int i915_pm_thaw(struct device *dev)
2322{
2323 return i915_pm_resume(dev);
2324}
2325
2326/* restore: called after loading the hibernation image. */
2327static int i915_pm_restore_early(struct device *dev)
2328{
2329 return i915_pm_resume_early(dev);
2330}
2331
2332static int i915_pm_restore(struct device *dev)
2333{
2334 return i915_pm_resume(dev);
2335}
2336
ddeea5b0
ID		 2337/*
2338 * Save all Gunit registers that may be lost after a D3 and a subsequent
2339 * S0i[R123] transition. The list of registers needing a save/restore is
2340 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2341 * registers in the following way:
2342 * - Driver: saved/restored by the driver
2343 * - Punit : saved/restored by the Punit firmware
2344 * - No, w/o marking: no need to save/restore, since the register is R/O or
2345 * used internally by the HW in a way that doesn't depend
2346 * keeping the content across a suspend/resume.
2347 * - Debug : used for debugging
2348 *
2349 * We save/restore all registers marked with 'Driver', with the following
2350 * exceptions:
2351 * - Registers out of use, including also registers marked with 'Debug'.
2352 * These have no effect on the driver's operation, so we don't save/restore
2353 * them to reduce the overhead.
2354 * - Registers that are fully setup by an initialization function called from
2355 * the resume path. For example many clock gating and RPS/RC6 registers.
2356 * - Registers that provide the right functionality with their reset defaults.
2357 *
2358 * TODO: Except for registers that based on the above 3 criteria can be safely
2359 * ignored, we save/restore all others, practically treating the HW context as
2360 * a black-box for the driver. Further investigation is needed to reduce the
2361 * saved/restored registers even further, by following the same 3 criteria.
2362 */
2363static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2364{
2365 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2366 int i;
2367
2368 /* GAM 0x4000-0x4770 */
2369 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2370 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2371 s->arb_mode = I915_READ(ARB_MODE);
2372 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2373 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2374
2375 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2376 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 2377
2378 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 2379 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 2380
2381 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2382 s->ecochk = I915_READ(GAM_ECOCHK);
2383 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2384 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2385
2386 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2387
2388 /* MBC 0x9024-0x91D0, 0x8500 */
2389 s->g3dctl = I915_READ(VLV_G3DCTL);
2390 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2391 s->mbctl = I915_READ(GEN6_MBCTL);
2392
2393 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2394 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2395 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2396 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2397 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2398 s->rstctl = I915_READ(GEN6_RSTCTL);
2399 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2400
2401 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2402 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2403 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2404 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2405 s->ecobus = I915_READ(ECOBUS);
2406 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2407 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2408 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2409 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2410 s->rcedata = I915_READ(VLV_RCEDATA);
2411 s->spare2gh = I915_READ(VLV_SPAREG2H);
2412
2413 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2414 s->gt_imr = I915_READ(GTIMR);
2415 s->gt_ier = I915_READ(GTIER);
2416 s->pm_imr = I915_READ(GEN6_PMIMR);
2417 s->pm_ier = I915_READ(GEN6_PMIER);
2418
2419 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2420 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2421
2422 /* GT SA CZ domain, 0x100000-0x138124 */
2423 s->tilectl = I915_READ(TILECTL);
2424 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2425 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2426 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2427 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2428
2429 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2430 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2431 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2432 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2433 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2434
2435 /*
2436 * Not saving any of:
2437 * DFT, 0x9800-0x9EC0
2438 * SARB, 0xB000-0xB1FC
2439 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2440 * PCI CFG
2441 */
2442}
2443
2444static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2445{
2446 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2447 u32 val;
2448 int i;
2449
2450 /* GAM 0x4000-0x4770 */
2451 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2452 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2453 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2454 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2455 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2456
2457 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2458 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2459
2460 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2461 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2462
2463 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2464 I915_WRITE(GAM_ECOCHK, s->ecochk);
2465 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2466 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2467
2468 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2469
2470 /* MBC 0x9024-0x91D0, 0x8500 */
2471 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2472 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2473 I915_WRITE(GEN6_MBCTL, s->mbctl);
2474
2475 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2476 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2477 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2478 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2479 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2480 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2481 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2482
2483 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2484 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2485 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2486 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2487 I915_WRITE(ECOBUS, s->ecobus);
2488 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2489 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2490 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2491 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2492 I915_WRITE(VLV_RCEDATA, s->rcedata);
2493 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2494
2495 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2496 I915_WRITE(GTIMR, s->gt_imr);
2497 I915_WRITE(GTIER, s->gt_ier);
2498 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2499 I915_WRITE(GEN6_PMIER, s->pm_ier);
2500
2501 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2502 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2503
2504 /* GT SA CZ domain, 0x100000-0x138124 */
2505 I915_WRITE(TILECTL, s->tilectl);
2506 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2507 /*
2508 * Preserve the GT allow wake and GFX force clock bit, they are not
2509 * be restored, as they are used to control the s0ix suspend/resume
2510 * sequence by the caller.
2511 */
2512 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2513 val &= VLV_GTLC_ALLOWWAKEREQ;
2514 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2515 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2516
2517 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2518 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2519 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2520 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2521
2522 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2523
2524 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2525 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2526 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2527 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2528 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2529}
2530
650ad970
ID		 2531int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2532{
2533 u32 val;
2534 int err;
2535
650ad970 2536#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
650ad970
ID		 2537
2538 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2539 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2540 if (force_on)
2541 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2542 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2543
2544 if (!force_on)
2545 return 0;
2546
8d4eee9c 2547 err = wait_for(COND, 20);
650ad970
ID		 2548 if (err)
2549 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2550 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2551
2552 return err;
2553#undef COND
2554}
2555
ddeea5b0
ID		 2556static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2557{
2558 u32 val;
2559 int err = 0;
2560
2561 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2562 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2563 if (allow)
2564 val |= VLV_GTLC_ALLOWWAKEREQ;
2565 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2566 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2567
2568#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
2569 allow)
2570 err = wait_for(COND, 1);
2571 if (err)
2572 DRM_ERROR("timeout disabling GT waking\n");
2573 return err;
2574#undef COND
2575}
2576
2577static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2578 bool wait_for_on)
2579{
2580 u32 mask;
2581 u32 val;
2582 int err;
2583
2584 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2585 val = wait_for_on ? mask : 0;
2586#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2587 if (COND)
2588 return 0;
2589
2590 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
87ad3212
JN		 2591 onoff(wait_for_on),
2592 I915_READ(VLV_GTLC_PW_STATUS));
ddeea5b0
ID		 2593
2594 /*
2595 * RC6 transitioning can be delayed up to 2 msec (see
2596 * valleyview_enable_rps), use 3 msec for safety.
2597 */
2598 err = wait_for(COND, 3);
2599 if (err)
2600 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2601 onoff(wait_for_on));
ddeea5b0
ID		 2602
2603 return err;
2604#undef COND
2605}
2606
2607static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2608{
2609 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2610 return;
2611
6fa283b0 2612 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2613 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2614}
2615
ebc32824 2616static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2617{
2618 u32 mask;
2619 int err;
2620
2621 /*
2622 * Bspec defines the following GT well on flags as debug only, so
2623 * don't treat them as hard failures.
2624 */
2625 (void)vlv_wait_for_gt_wells(dev_priv, false);
2626
2627 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2628 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2629
2630 vlv_check_no_gt_access(dev_priv);
2631
2632 err = vlv_force_gfx_clock(dev_priv, true);
2633 if (err)
2634 goto err1;
2635
2636 err = vlv_allow_gt_wake(dev_priv, false);
2637 if (err)
2638 goto err2;
98711167 2639
2d1fe073 2640 if (!IS_CHERRYVIEW(dev_priv))
98711167 2641 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2642
2643 err = vlv_force_gfx_clock(dev_priv, false);
2644 if (err)
2645 goto err2;
2646
2647 return 0;
2648
2649err2:
2650 /* For safety always re-enable waking and disable gfx clock forcing */
2651 vlv_allow_gt_wake(dev_priv, true);
2652err1:
2653 vlv_force_gfx_clock(dev_priv, false);
2654
2655 return err;
2656}
2657
016970be
SK		 2658static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2659 bool rpm_resume)
ddeea5b0
ID		 2660{
2661 struct drm_device *dev = dev_priv->dev;
2662 int err;
2663 int ret;
2664
2665 /*
2666 * If any of the steps fail just try to continue, that's the best we
2667 * can do at this point. Return the first error code (which will also
2668 * leave RPM permanently disabled).
2669 */
2670 ret = vlv_force_gfx_clock(dev_priv, true);
2671
2d1fe073 2672 if (!IS_CHERRYVIEW(dev_priv))
98711167 2673 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2674
2675 err = vlv_allow_gt_wake(dev_priv, true);
2676 if (!ret)
2677 ret = err;
2678
2679 err = vlv_force_gfx_clock(dev_priv, false);
2680 if (!ret)
2681 ret = err;
2682
2683 vlv_check_no_gt_access(dev_priv);
2684
016970be
SK		 2685 if (rpm_resume) {
2686 intel_init_clock_gating(dev);
2687 i915_gem_restore_fences(dev);
2688 }
ddeea5b0
ID		 2689
2690 return ret;
2691}
2692
97bea207 2693static int intel_runtime_suspend(struct device *device)
8a187455
PZ		 2694{
2695 struct pci_dev *pdev = to_pci_dev(device);
2696 struct drm_device *dev = pci_get_drvdata(pdev);
2697 struct drm_i915_private *dev_priv = dev->dev_private;
0ab9cfeb 2698 int ret;
8a187455 2699
dc97997a 2700 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2701 return -ENODEV;
2702
604effb7
ID		 2703 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2704 return -ENODEV;
2705
8a187455
PZ		 2706 DRM_DEBUG_KMS("Suspending device\n");
2707
d6102977
ID		 2708 /*
2709 * We could deadlock here in case another thread holding struct_mutex
2710 * calls RPM suspend concurrently, since the RPM suspend will wait
2711 * first for this RPM suspend to finish. In this case the concurrent
2712 * RPM resume will be followed by its RPM suspend counterpart. Still
2713 * for consistency return -EAGAIN, which will reschedule this suspend.
2714 */
2715 if (!mutex_trylock(&dev->struct_mutex)) {
2716 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2717 /*
2718 * Bump the expiration timestamp, otherwise the suspend won't
2719 * be rescheduled.
2720 */
2721 pm_runtime_mark_last_busy(device);
2722
2723 return -EAGAIN;
2724 }
1f814dac
ID		 2725
2726 disable_rpm_wakeref_asserts(dev_priv);
2727
d6102977
ID		 2728 /*
2729 * We are safe here against re-faults, since the fault handler takes
2730 * an RPM reference.
2731 */
2732 i915_gem_release_all_mmaps(dev_priv);
2733 mutex_unlock(&dev->struct_mutex);
2734
825f2728
JL		 2735 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
2736
a1c41994
AD		 2737 intel_guc_suspend(dev);
2738
dc97997a 2739 intel_suspend_gt_powersave(dev_priv);
2eb5252e 2740 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2741
507e126e
ID		 2742 ret = 0;
2743 if (IS_BROXTON(dev_priv)) {
2744 bxt_display_core_uninit(dev_priv);
2745 bxt_enable_dc9(dev_priv);
2746 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2747 hsw_enable_pc8(dev_priv);
2748 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2749 ret = vlv_suspend_complete(dev_priv);
2750 }
2751
0ab9cfeb
ID		 2752 if (ret) {
2753 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2754 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2755
1f814dac
ID		 2756 enable_rpm_wakeref_asserts(dev_priv);
2757
0ab9cfeb
ID		 2758 return ret;
2759 }
a8a8bd54 2760
dc97997a 2761 intel_uncore_forcewake_reset(dev_priv, false);
1f814dac
ID		 2762
2763 enable_rpm_wakeref_asserts(dev_priv);
2764 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2765
bc3b9346 2766 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2767 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2768
8a187455 2769 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2770
2771 /*
c8a0bd42
PZ		 2772 * FIXME: We really should find a document that references the arguments
2773 * used below!
1fb2362b 2774 */
6f9f4b7a 2775 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2776 /*
2777 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2778 * being detected, and the call we do at intel_runtime_resume()
2779 * won't be able to restore them. Since PCI_D3hot matches the
2780 * actual specification and appears to be working, use it.
2781 */
6f9f4b7a 2782 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2783 } else {
c8a0bd42
PZ		 2784 /*
2785 * current versions of firmware which depend on this opregion
2786 * notification have repurposed the D1 definition to mean
2787 * "runtime suspended" vs. what you would normally expect (D3)
2788 * to distinguish it from notifications that might be sent via
2789 * the suspend path.
2790 */
6f9f4b7a 2791 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2792 }
8a187455 2793
59bad947 2794 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2795
a8a8bd54 2796 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2797 return 0;
2798}
2799
97bea207 2800static int intel_runtime_resume(struct device *device)
8a187455
PZ		 2801{
2802 struct pci_dev *pdev = to_pci_dev(device);
2803 struct drm_device *dev = pci_get_drvdata(pdev);
2804 struct drm_i915_private *dev_priv = dev->dev_private;
1a5df187 2805 int ret = 0;
8a187455 2806
604effb7
ID		 2807 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2808 return -ENODEV;
8a187455
PZ		 2809
2810 DRM_DEBUG_KMS("Resuming device\n");
2811
1f814dac
ID		 2812 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2813 disable_rpm_wakeref_asserts(dev_priv);
2814
6f9f4b7a 2815 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2816 dev_priv->pm.suspended = false;
55ec45c2
MK		 2817 if (intel_uncore_unclaimed_mmio(dev_priv))
2818 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2819
a1c41994
AD		 2820 intel_guc_resume(dev);
2821
1a5df187
PZ		 2822 if (IS_GEN6(dev_priv))
2823 intel_init_pch_refclk(dev);
31335cec 2824
507e126e
ID		 2825 if (IS_BROXTON(dev)) {
2826 bxt_disable_dc9(dev_priv);
2827 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2828 if (dev_priv->csr.dmc_payload &&
2829 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2830 gen9_enable_dc5(dev_priv);
507e126e 2831 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2832 hsw_disable_pc8(dev_priv);
507e126e 2833 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2834 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2835 }
1a5df187 2836
0ab9cfeb
ID		 2837 /*
2838 * No point of rolling back things in case of an error, as the best
2839 * we can do is to hope that things will still work (and disable RPM).
2840 */
92b806d3 2841 i915_gem_init_swizzling(dev);
dc97997a 2842 gen6_update_ring_freq(dev_priv);
92b806d3 2843
b963291c 2844 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2845
2846 /*
2847 * On VLV/CHV display interrupts are part of the display
2848 * power well, so hpd is reinitialized from there. For
2849 * everyone else do it here.
2850 */
666a4537 2851 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2852 intel_hpd_init(dev_priv);
2853
dc97997a 2854 intel_enable_gt_powersave(dev_priv);
b5478bcd 2855
1f814dac
ID		 2856 enable_rpm_wakeref_asserts(dev_priv);
2857
0ab9cfeb
ID		 2858 if (ret)
2859 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2860 else
2861 DRM_DEBUG_KMS("Device resumed\n");
2862
2863 return ret;
8a187455
PZ		 2864}
2865
42f5551d 2866const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2867 /*
2868 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2869 * PMSG_RESUME]
2870 */
0206e353 2871 .suspend = i915_pm_suspend,
76c4b250
ID		 2872 .suspend_late = i915_pm_suspend_late,
2873 .resume_early = i915_pm_resume_early,
0206e353 2874 .resume = i915_pm_resume,
5545dbbf
ID		 2875
2876 /*
2877 * S4 event handlers
2878 * @freeze, @freeze_late : called (1) before creating the
2879 * hibernation image [PMSG_FREEZE] and
2880 * (2) after rebooting, before restoring
2881 * the image [PMSG_QUIESCE]
2882 * @thaw, @thaw_early : called (1) after creating the hibernation
2883 * image, before writing it [PMSG_THAW]
2884 * and (2) after failing to create or
2885 * restore the image [PMSG_RECOVER]
2886 * @poweroff, @poweroff_late: called after writing the hibernation
2887 * image, before rebooting [PMSG_HIBERNATE]
2888 * @restore, @restore_early : called after rebooting and restoring the
2889 * hibernation image [PMSG_RESTORE]
2890 */
1f19ac2a
CW		 2891 .freeze = i915_pm_freeze,
2892 .freeze_late = i915_pm_freeze_late,
2893 .thaw_early = i915_pm_thaw_early,
2894 .thaw = i915_pm_thaw,
36d61e67 2895 .poweroff = i915_pm_suspend,
ab3be73f 2896 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2897 .restore_early = i915_pm_restore_early,
2898 .restore = i915_pm_restore,
5545dbbf
ID		 2899
2900 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2901 .runtime_suspend = intel_runtime_suspend,
2902 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2903};
2904
78b68556 2905static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2906 .fault = i915_gem_fault,
ab00b3e5
JB		 2907 .open = drm_gem_vm_open,
2908 .close = drm_gem_vm_close,
de151cf6
JB		 2909};
2910
e08e96de
AV		 2911static const struct file_operations i915_driver_fops = {
2912 .owner = THIS_MODULE,
2913 .open = drm_open,
2914 .release = drm_release,
2915 .unlocked_ioctl = drm_ioctl,
2916 .mmap = drm_gem_mmap,
2917 .poll = drm_poll,
e08e96de
AV		 2918 .read = drm_read,
2919#ifdef CONFIG_COMPAT
2920 .compat_ioctl = i915_compat_ioctl,
2921#endif
2922 .llseek = noop_llseek,
2923};
2924
0673ad47
CW		 2925static int
2926i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2927 struct drm_file *file)
2928{
2929 return -ENODEV;
2930}
2931
2932static const struct drm_ioctl_desc i915_ioctls[] = {
2933 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2934 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2935 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2936 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2937 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2938 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2939 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2940 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2941 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2942 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2943 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2944 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2945 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2946 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2947 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2948 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2949 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2950 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2951 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2952 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2953 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2954 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2955 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2956 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2957 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2958 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2959 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2960 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2961 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2962 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2963 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2964 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2965 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2966 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2967 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2968 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2969 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2970 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2971 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2972 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2973 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2974 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2975 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2976 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2977 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2978 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2979 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2980 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2981 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2982 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2983 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2984 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2985};
2986
1da177e4 2987static struct drm_driver driver = {
0c54781b
MW		 2988 /* Don't use MTRRs here; the Xserver or userspace app should
2989 * deal with them for Intel hardware.
792d2b9a 2990 */
673a394b 2991 .driver_features =
10ba5012 2992 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1751fcf9 2993 DRIVER_RENDER | DRIVER_MODESET,
673a394b 2994 .open = i915_driver_open,
22eae947
DA		 2995 .lastclose = i915_driver_lastclose,
2996 .preclose = i915_driver_preclose,
673a394b 2997 .postclose = i915_driver_postclose,
915b4d11 2998 .set_busid = drm_pci_set_busid,
d8e29209 2999
673a394b 3000 .gem_free_object = i915_gem_free_object,
de151cf6 3001 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 3002
3003 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3004 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3005 .gem_prime_export = i915_gem_prime_export,
3006 .gem_prime_import = i915_gem_prime_import,
3007
ff72145b 3008 .dumb_create = i915_gem_dumb_create,
da6b51d0 3009 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 3010 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 3011 .ioctls = i915_ioctls,
0673ad47 3012 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 3013 .fops = &i915_driver_fops,
22eae947
DA		 3014 .name = DRIVER_NAME,
3015 .desc = DRIVER_DESC,
3016 .date = DRIVER_DATE,
3017 .major = DRIVER_MAJOR,
3018 .minor = DRIVER_MINOR,
3019 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 3020};
3021
3022static int __init i915_init(void)
3023{
42f5551d
CW		 3024 extern struct pci_driver i915_pci_driver;
3025
79e53945 3026 /*
fd930478
CW		 3027 * Enable KMS by default, unless explicitly overriden by
3028 * either the i915.modeset prarameter or by the
3029 * vga_text_mode_force boot option.
79e53945 3030 */
fd930478
CW		 3031
3032 if (i915.modeset == 0)
3033 driver.driver_features &= ~DRIVER_MODESET;
79e53945 3034
d330a953 3035 if (vgacon_text_force() && i915.modeset == -1)
79e53945 3036 driver.driver_features &= ~DRIVER_MODESET;
79e53945 3037
b30324ad 3038 if (!(driver.driver_features & DRIVER_MODESET)) {
b30324ad 3039 /* Silently fail loading to not upset userspace. */
c2dac868 3040 DRM_DEBUG_DRIVER("KMS disabled.\n");
b30324ad 3041 return 0;
b30324ad 3042 }
3885c6bb 3043
c5b852f3 3044 if (i915.nuclear_pageflip)
b2e7723b
MR		 3045 driver.driver_features |= DRIVER_ATOMIC;
3046
8410ea3b 3047 return drm_pci_init(&driver, &i915_pci_driver);
1da177e4
LT		 3048}
3049
3050static void __exit i915_exit(void)
3051{
42f5551d
CW		 3052 extern struct pci_driver i915_pci_driver;
3053
b33ecdd1
DV		 3054 if (!(driver.driver_features & DRIVER_MODESET))
3055 return; /* Never loaded a driver. */
b33ecdd1 3056
8410ea3b 3057 drm_pci_exit(&driver, &i915_pci_driver);
1da177e4
LT		 3058}
3059
3060module_init(i915_init);
3061module_exit(i915_exit);
3062
0a6d1631 3063MODULE_AUTHOR("Tungsten Graphics, Inc.");
1eab9234 3064MODULE_AUTHOR("Intel Corporation");
0a6d1631 3065
b5e89ed5 3066MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 3067MODULE_LICENSE("GPL and additional rights");
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