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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
354ff967 | 39 | #include "drm_crtc_helper.h" |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a35d9d3c | 50 | int i915_panel_ignore_lid __read_mostly = 0; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 BW |
52 | MODULE_PARM_DESC(panel_ignore_lid, |
53 | "Override lid status (0=autodetect [default], 1=lid open, " | |
54 | "-1=lid closed)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
f57f9c16 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
112b715e | 121 | static struct drm_driver driver; |
1f7a6e37 | 122 | extern int intel_agp_enabled; |
112b715e | 123 | |
cfdf1fa2 | 124 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 125 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 126 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
127 | .vendor = 0x8086, \ |
128 | .device = id, \ | |
129 | .subvendor = PCI_ANY_ID, \ | |
130 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
131 | .driver_data = (unsigned long) info } |
132 | ||
9a7e8492 | 133 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 134 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 135 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
136 | }; |
137 | ||
9a7e8492 | 138 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 139 | .gen = 2, |
31578148 | 140 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
141 | }; |
142 | ||
9a7e8492 | 143 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 144 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 145 | .cursor_needs_physical = 1, |
31578148 | 146 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
147 | }; |
148 | ||
9a7e8492 | 149 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 150 | .gen = 2, |
31578148 | 151 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
152 | }; |
153 | ||
9a7e8492 | 154 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 155 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 156 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 157 | }; |
9a7e8492 | 158 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 159 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 160 | .cursor_needs_physical = 1, |
31578148 | 161 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 162 | .supports_tv = 1, |
cfdf1fa2 | 163 | }; |
9a7e8492 | 164 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 165 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 166 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 167 | }; |
9a7e8492 | 168 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 169 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 170 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 171 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 172 | .supports_tv = 1, |
cfdf1fa2 KH |
173 | }; |
174 | ||
9a7e8492 | 175 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 176 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 177 | .has_hotplug = 1, |
31578148 | 178 | .has_overlay = 1, |
cfdf1fa2 KH |
179 | }; |
180 | ||
9a7e8492 | 181 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 182 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 183 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 184 | .has_overlay = 1, |
a6c45cf0 | 185 | .supports_tv = 1, |
cfdf1fa2 KH |
186 | }; |
187 | ||
9a7e8492 | 188 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 189 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 190 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 191 | .has_overlay = 1, |
cfdf1fa2 KH |
192 | }; |
193 | ||
9a7e8492 | 194 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 195 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 196 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 197 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
198 | }; |
199 | ||
9a7e8492 | 200 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 201 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 202 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 203 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 204 | .supports_tv = 1, |
92f49d9c | 205 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
206 | }; |
207 | ||
9a7e8492 | 208 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 209 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 210 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 211 | .has_overlay = 1, |
cfdf1fa2 KH |
212 | }; |
213 | ||
9a7e8492 | 214 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 215 | .gen = 5, |
5a117db7 | 216 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 217 | .has_bsd_ring = 1, |
7e508a27 | 218 | .has_pch_split = 1, |
cfdf1fa2 KH |
219 | }; |
220 | ||
9a7e8492 | 221 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 222 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 223 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 224 | .has_fbc = 1, |
92f49d9c | 225 | .has_bsd_ring = 1, |
7e508a27 | 226 | .has_pch_split = 1, |
cfdf1fa2 KH |
227 | }; |
228 | ||
9a7e8492 | 229 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 230 | .gen = 6, |
c96c3a8c | 231 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 232 | .has_bsd_ring = 1, |
549f7365 | 233 | .has_blt_ring = 1, |
3d29b842 | 234 | .has_llc = 1, |
7e508a27 | 235 | .has_pch_split = 1, |
f6e450a6 EA |
236 | }; |
237 | ||
9a7e8492 | 238 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 239 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 240 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 241 | .has_fbc = 1, |
881f47b6 | 242 | .has_bsd_ring = 1, |
549f7365 | 243 | .has_blt_ring = 1, |
3d29b842 | 244 | .has_llc = 1, |
7e508a27 | 245 | .has_pch_split = 1, |
a13e4093 EA |
246 | }; |
247 | ||
c76b615c JB |
248 | static const struct intel_device_info intel_ivybridge_d_info = { |
249 | .is_ivybridge = 1, .gen = 7, | |
250 | .need_gfx_hws = 1, .has_hotplug = 1, | |
251 | .has_bsd_ring = 1, | |
252 | .has_blt_ring = 1, | |
3d29b842 | 253 | .has_llc = 1, |
7e508a27 | 254 | .has_pch_split = 1, |
c76b615c JB |
255 | }; |
256 | ||
257 | static const struct intel_device_info intel_ivybridge_m_info = { | |
258 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, | |
259 | .need_gfx_hws = 1, .has_hotplug = 1, | |
260 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ | |
261 | .has_bsd_ring = 1, | |
262 | .has_blt_ring = 1, | |
3d29b842 | 263 | .has_llc = 1, |
7e508a27 | 264 | .has_pch_split = 1, |
c76b615c JB |
265 | }; |
266 | ||
70a3eb7a JB |
267 | static const struct intel_device_info intel_valleyview_m_info = { |
268 | .gen = 7, .is_mobile = 1, | |
269 | .need_gfx_hws = 1, .has_hotplug = 1, | |
270 | .has_fbc = 0, | |
271 | .has_bsd_ring = 1, | |
272 | .has_blt_ring = 1, | |
273 | .is_valleyview = 1, | |
274 | }; | |
275 | ||
276 | static const struct intel_device_info intel_valleyview_d_info = { | |
277 | .gen = 7, | |
278 | .need_gfx_hws = 1, .has_hotplug = 1, | |
279 | .has_fbc = 0, | |
280 | .has_bsd_ring = 1, | |
281 | .has_blt_ring = 1, | |
282 | .is_valleyview = 1, | |
283 | }; | |
284 | ||
4cae9ae0 ED |
285 | static const struct intel_device_info intel_haswell_d_info = { |
286 | .is_haswell = 1, .gen = 7, | |
287 | .need_gfx_hws = 1, .has_hotplug = 1, | |
288 | .has_bsd_ring = 1, | |
289 | .has_blt_ring = 1, | |
290 | .has_llc = 1, | |
291 | .has_pch_split = 1, | |
292 | }; | |
293 | ||
294 | static const struct intel_device_info intel_haswell_m_info = { | |
295 | .is_haswell = 1, .gen = 7, .is_mobile = 1, | |
296 | .need_gfx_hws = 1, .has_hotplug = 1, | |
297 | .has_bsd_ring = 1, | |
298 | .has_blt_ring = 1, | |
299 | .has_llc = 1, | |
300 | .has_pch_split = 1, | |
c76b615c JB |
301 | }; |
302 | ||
6103da0d CW |
303 | static const struct pci_device_id pciidlist[] = { /* aka */ |
304 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
305 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
306 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 307 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
308 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
309 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
310 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
311 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
312 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
313 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
314 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
315 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
316 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
317 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
318 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
319 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
320 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
321 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
322 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
323 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
324 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
325 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
326 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
327 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
328 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
329 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 330 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
331 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
332 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
333 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
334 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 335 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
336 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
337 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 338 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 339 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 340 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 341 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
342 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
343 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
344 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
345 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
346 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
cc22a938 | 347 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
49ae35f2 | 348 | {0, 0, 0} |
1da177e4 LT |
349 | }; |
350 | ||
79e53945 JB |
351 | #if defined(CONFIG_DRM_I915_KMS) |
352 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
353 | #endif | |
354 | ||
3bad0781 | 355 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
90711d50 | 356 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
3bad0781 | 357 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
c792513b | 358 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
eb877ebf | 359 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
3bad0781 | 360 | |
0206e353 | 361 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
362 | { |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
364 | struct pci_dev *pch; | |
365 | ||
366 | /* | |
367 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
368 | * make graphics device passthrough work easy for VMM, that only | |
369 | * need to expose ISA bridge to let driver know the real hardware | |
370 | * underneath. This is a requirement from virtualization team. | |
371 | */ | |
372 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
373 | if (pch) { | |
374 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
375 | int id; | |
376 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
377 | ||
90711d50 JB |
378 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
379 | dev_priv->pch_type = PCH_IBX; | |
ee7b9f93 | 380 | dev_priv->num_pch_pll = 2; |
90711d50 JB |
381 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
382 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
3bad0781 | 383 | dev_priv->pch_type = PCH_CPT; |
ee7b9f93 | 384 | dev_priv->num_pch_pll = 2; |
3bad0781 | 385 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
c792513b JB |
386 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
387 | /* PantherPoint is CPT compatible */ | |
388 | dev_priv->pch_type = PCH_CPT; | |
ee7b9f93 | 389 | dev_priv->num_pch_pll = 2; |
c792513b | 390 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
eb877ebf ED |
391 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
392 | dev_priv->pch_type = PCH_LPT; | |
ee7b9f93 | 393 | dev_priv->num_pch_pll = 0; |
eb877ebf | 394 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
3bad0781 | 395 | } |
ee7b9f93 | 396 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
3bad0781 ZW |
397 | } |
398 | pci_dev_put(pch); | |
399 | } | |
400 | } | |
401 | ||
2911a35b BW |
402 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
403 | { | |
404 | if (INTEL_INFO(dev)->gen < 6) | |
405 | return 0; | |
406 | ||
407 | if (i915_semaphores >= 0) | |
408 | return i915_semaphores; | |
409 | ||
410 | /* Enable semaphores on SNB when IO remapping is off */ | |
411 | if (INTEL_INFO(dev)->gen == 6) | |
412 | return !intel_iommu_enabled; | |
413 | ||
414 | return 1; | |
415 | } | |
416 | ||
8d715f00 | 417 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
eb43f4af CW |
418 | { |
419 | int count; | |
420 | ||
421 | count = 0; | |
422 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
423 | udelay(10); | |
424 | ||
425 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
426 | POSTING_READ(FORCEWAKE); | |
427 | ||
428 | count = 0; | |
429 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) | |
430 | udelay(10); | |
431 | } | |
432 | ||
8d715f00 KP |
433 | void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
434 | { | |
435 | int count; | |
436 | ||
437 | count = 0; | |
438 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) | |
439 | udelay(10); | |
440 | ||
6b26c86d | 441 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1)); |
8d715f00 KP |
442 | POSTING_READ(FORCEWAKE_MT); |
443 | ||
444 | count = 0; | |
445 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) | |
446 | udelay(10); | |
447 | } | |
448 | ||
fcca7926 BW |
449 | /* |
450 | * Generally this is called implicitly by the register read function. However, | |
451 | * if some sequence requires the GT to not power down then this function should | |
452 | * be called at the beginning of the sequence followed by a call to | |
453 | * gen6_gt_force_wake_put() at the end of the sequence. | |
454 | */ | |
455 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
456 | { | |
9f1f46a4 | 457 | unsigned long irqflags; |
fcca7926 | 458 | |
9f1f46a4 DV |
459 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
460 | if (dev_priv->forcewake_count++ == 0) | |
8d715f00 | 461 | dev_priv->display.force_wake_get(dev_priv); |
9f1f46a4 | 462 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
463 | } |
464 | ||
ee64cbdb BW |
465 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
466 | { | |
467 | u32 gtfifodbg; | |
468 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); | |
469 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, | |
470 | "MMIO read or write has been dropped %x\n", gtfifodbg)) | |
471 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); | |
472 | } | |
473 | ||
8d715f00 | 474 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
eb43f4af CW |
475 | { |
476 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
ee64cbdb BW |
477 | /* The below doubles as a POSTING_READ */ |
478 | gen6_gt_check_fifodbg(dev_priv); | |
eb43f4af CW |
479 | } |
480 | ||
8d715f00 KP |
481 | void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
482 | { | |
6b26c86d | 483 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1)); |
ee64cbdb BW |
484 | /* The below doubles as a POSTING_READ */ |
485 | gen6_gt_check_fifodbg(dev_priv); | |
8d715f00 KP |
486 | } |
487 | ||
fcca7926 BW |
488 | /* |
489 | * see gen6_gt_force_wake_get() | |
490 | */ | |
491 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
492 | { | |
9f1f46a4 | 493 | unsigned long irqflags; |
fcca7926 | 494 | |
9f1f46a4 DV |
495 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
496 | if (--dev_priv->forcewake_count == 0) | |
8d715f00 | 497 | dev_priv->display.force_wake_put(dev_priv); |
9f1f46a4 | 498 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
499 | } |
500 | ||
67a3744f | 501 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
91355834 | 502 | { |
67a3744f BW |
503 | int ret = 0; |
504 | ||
0206e353 | 505 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
95736720 CW |
506 | int loop = 500; |
507 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
508 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { | |
509 | udelay(10); | |
510 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
511 | } | |
67a3744f BW |
512 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
513 | ++ret; | |
95736720 | 514 | dev_priv->gt_fifo_count = fifo; |
91355834 | 515 | } |
95736720 | 516 | dev_priv->gt_fifo_count--; |
67a3744f BW |
517 | |
518 | return ret; | |
91355834 CW |
519 | } |
520 | ||
575155a9 JB |
521 | void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
522 | { | |
523 | int count; | |
524 | ||
525 | count = 0; | |
526 | ||
527 | /* Already awake? */ | |
528 | if ((I915_READ(0x130094) & 0xa1) == 0xa1) | |
529 | return; | |
530 | ||
531 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff); | |
532 | POSTING_READ(FORCEWAKE_VLV); | |
533 | ||
534 | count = 0; | |
535 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0) | |
536 | udelay(10); | |
537 | } | |
538 | ||
539 | void vlv_force_wake_put(struct drm_i915_private *dev_priv) | |
540 | { | |
541 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000); | |
542 | /* FIXME: confirm VLV behavior with Punit folks */ | |
543 | POSTING_READ(FORCEWAKE_VLV); | |
544 | } | |
545 | ||
84b79f8d | 546 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 547 | { |
61caf87c RW |
548 | struct drm_i915_private *dev_priv = dev->dev_private; |
549 | ||
5bcf719b DA |
550 | drm_kms_helper_poll_disable(dev); |
551 | ||
ba8bbcf6 | 552 | pci_save_state(dev->pdev); |
ba8bbcf6 | 553 | |
5669fcac | 554 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 555 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
556 | int error = i915_gem_idle(dev); |
557 | if (error) { | |
226485e9 | 558 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
559 | "GEM idle failed, resume might fail\n"); |
560 | return error; | |
561 | } | |
226485e9 | 562 | drm_irq_uninstall(dev); |
5669fcac JB |
563 | } |
564 | ||
9e06dd39 JB |
565 | i915_save_state(dev); |
566 | ||
44834a67 | 567 | intel_opregion_fini(dev); |
8ee1c3db | 568 | |
84b79f8d RW |
569 | /* Modeset on resume, not lid events */ |
570 | dev_priv->modeset_on_lid = 0; | |
61caf87c | 571 | |
3fa016a0 DA |
572 | console_lock(); |
573 | intel_fbdev_set_suspend(dev, 1); | |
574 | console_unlock(); | |
575 | ||
61caf87c | 576 | return 0; |
84b79f8d RW |
577 | } |
578 | ||
6a9ee8af | 579 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
580 | { |
581 | int error; | |
582 | ||
583 | if (!dev || !dev->dev_private) { | |
584 | DRM_ERROR("dev: %p\n", dev); | |
585 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
586 | return -ENODEV; | |
587 | } | |
588 | ||
589 | if (state.event == PM_EVENT_PRETHAW) | |
590 | return 0; | |
591 | ||
5bcf719b DA |
592 | |
593 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
594 | return 0; | |
6eecba33 | 595 | |
84b79f8d RW |
596 | error = i915_drm_freeze(dev); |
597 | if (error) | |
598 | return error; | |
599 | ||
b932ccb5 DA |
600 | if (state.event == PM_EVENT_SUSPEND) { |
601 | /* Shut down the device */ | |
602 | pci_disable_device(dev->pdev); | |
603 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
604 | } | |
ba8bbcf6 JB |
605 | |
606 | return 0; | |
607 | } | |
608 | ||
84b79f8d | 609 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 610 | { |
5669fcac | 611 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 612 | int error = 0; |
8ee1c3db | 613 | |
d1c3b177 CW |
614 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
615 | mutex_lock(&dev->struct_mutex); | |
616 | i915_gem_restore_gtt_mappings(dev); | |
617 | mutex_unlock(&dev->struct_mutex); | |
618 | } | |
619 | ||
61caf87c | 620 | i915_restore_state(dev); |
44834a67 | 621 | intel_opregion_setup(dev); |
61caf87c | 622 | |
5669fcac JB |
623 | /* KMS EnterVT equivalent */ |
624 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
625 | mutex_lock(&dev->struct_mutex); | |
626 | dev_priv->mm.suspended = 0; | |
627 | ||
f691e2f4 | 628 | error = i915_gem_init_hw(dev); |
5669fcac | 629 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 630 | |
9fb526db KP |
631 | if (HAS_PCH_SPLIT(dev)) |
632 | ironlake_init_pch_refclk(dev); | |
633 | ||
500f7147 | 634 | drm_mode_config_reset(dev); |
226485e9 | 635 | drm_irq_install(dev); |
84b79f8d | 636 | |
354ff967 | 637 | /* Resume the modeset for every activated CRTC */ |
927a2f11 | 638 | mutex_lock(&dev->mode_config.mutex); |
354ff967 | 639 | drm_helper_resume_force_mode(dev); |
927a2f11 | 640 | mutex_unlock(&dev->mode_config.mutex); |
5669fcac | 641 | |
ac668088 | 642 | if (IS_IRONLAKE_M(dev)) |
d5bb081b JB |
643 | ironlake_enable_rc6(dev); |
644 | } | |
1daed3fb | 645 | |
44834a67 CW |
646 | intel_opregion_init(dev); |
647 | ||
c9354c85 | 648 | dev_priv->modeset_on_lid = 0; |
06891e27 | 649 | |
3fa016a0 DA |
650 | console_lock(); |
651 | intel_fbdev_set_suspend(dev, 0); | |
652 | console_unlock(); | |
84b79f8d RW |
653 | return error; |
654 | } | |
655 | ||
6a9ee8af | 656 | int i915_resume(struct drm_device *dev) |
84b79f8d | 657 | { |
6eecba33 CW |
658 | int ret; |
659 | ||
5bcf719b DA |
660 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
661 | return 0; | |
662 | ||
84b79f8d RW |
663 | if (pci_enable_device(dev->pdev)) |
664 | return -EIO; | |
665 | ||
666 | pci_set_master(dev->pdev); | |
667 | ||
6eecba33 CW |
668 | ret = i915_drm_thaw(dev); |
669 | if (ret) | |
670 | return ret; | |
671 | ||
672 | drm_kms_helper_poll_enable(dev); | |
673 | return 0; | |
ba8bbcf6 JB |
674 | } |
675 | ||
d4b8bb2a | 676 | static int i8xx_do_reset(struct drm_device *dev) |
dc96e9b8 CW |
677 | { |
678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
679 | ||
680 | if (IS_I85X(dev)) | |
681 | return -ENODEV; | |
682 | ||
683 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
684 | POSTING_READ(D_STATE); | |
685 | ||
686 | if (IS_I830(dev) || IS_845G(dev)) { | |
687 | I915_WRITE(DEBUG_RESET_I830, | |
688 | DEBUG_RESET_DISPLAY | | |
689 | DEBUG_RESET_RENDER | | |
690 | DEBUG_RESET_FULL); | |
691 | POSTING_READ(DEBUG_RESET_I830); | |
692 | msleep(1); | |
693 | ||
694 | I915_WRITE(DEBUG_RESET_I830, 0); | |
695 | POSTING_READ(DEBUG_RESET_I830); | |
696 | } | |
697 | ||
698 | msleep(1); | |
699 | ||
700 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
701 | POSTING_READ(D_STATE); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
f49f0586 KG |
706 | static int i965_reset_complete(struct drm_device *dev) |
707 | { | |
708 | u8 gdrst; | |
eeccdcac | 709 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
f49f0586 KG |
710 | return gdrst & 0x1; |
711 | } | |
712 | ||
d4b8bb2a | 713 | static int i965_do_reset(struct drm_device *dev) |
0573ed4a | 714 | { |
5ccce180 | 715 | int ret; |
0573ed4a KG |
716 | u8 gdrst; |
717 | ||
ae681d96 CW |
718 | /* |
719 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
720 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
721 | * triggers the reset; when done, the hardware will clear it. | |
722 | */ | |
0573ed4a | 723 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
d4b8bb2a | 724 | pci_write_config_byte(dev->pdev, I965_GDRST, |
5ccce180 DV |
725 | gdrst | GRDOM_RENDER | |
726 | GRDOM_RESET_ENABLE); | |
727 | ret = wait_for(i965_reset_complete(dev), 500); | |
728 | if (ret) | |
729 | return ret; | |
730 | ||
731 | /* We can't reset render&media without also resetting display ... */ | |
732 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | |
733 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
734 | gdrst | GRDOM_MEDIA | | |
735 | GRDOM_RESET_ENABLE); | |
0573ed4a KG |
736 | |
737 | return wait_for(i965_reset_complete(dev), 500); | |
738 | } | |
739 | ||
d4b8bb2a | 740 | static int ironlake_do_reset(struct drm_device *dev) |
0573ed4a KG |
741 | { |
742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5ccce180 DV |
743 | u32 gdrst; |
744 | int ret; | |
745 | ||
746 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
747 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
748 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
749 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
750 | if (ret) | |
751 | return ret; | |
752 | ||
753 | /* We can't reset render&media without also resetting display ... */ | |
754 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
d4b8bb2a | 755 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
5ccce180 | 756 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
0573ed4a | 757 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
ba8bbcf6 JB |
758 | } |
759 | ||
d4b8bb2a | 760 | static int gen6_do_reset(struct drm_device *dev) |
cff458c2 EA |
761 | { |
762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b6e45f86 KP |
763 | int ret; |
764 | unsigned long irqflags; | |
cff458c2 | 765 | |
286fed41 KP |
766 | /* Hold gt_lock across reset to prevent any register access |
767 | * with forcewake not set correctly | |
768 | */ | |
b6e45f86 | 769 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
286fed41 KP |
770 | |
771 | /* Reset the chip */ | |
772 | ||
773 | /* GEN6_GDRST is not in the gt power well, no need to check | |
774 | * for fifo space for the write or forcewake the chip for | |
775 | * the read | |
776 | */ | |
777 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
778 | ||
779 | /* Spin waiting for the device to ack the reset request */ | |
780 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
781 | ||
782 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | |
b6e45f86 KP |
783 | if (dev_priv->forcewake_count) |
784 | dev_priv->display.force_wake_get(dev_priv); | |
286fed41 KP |
785 | else |
786 | dev_priv->display.force_wake_put(dev_priv); | |
787 | ||
788 | /* Restore fifo count */ | |
789 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
790 | ||
b6e45f86 KP |
791 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
792 | return ret; | |
cff458c2 EA |
793 | } |
794 | ||
d4b8bb2a | 795 | static int intel_gpu_reset(struct drm_device *dev) |
350d2706 | 796 | { |
2b9dc9a2 | 797 | struct drm_i915_private *dev_priv = dev->dev_private; |
350d2706 DV |
798 | int ret = -ENODEV; |
799 | ||
800 | switch (INTEL_INFO(dev)->gen) { | |
801 | case 7: | |
802 | case 6: | |
d4b8bb2a | 803 | ret = gen6_do_reset(dev); |
350d2706 DV |
804 | break; |
805 | case 5: | |
d4b8bb2a | 806 | ret = ironlake_do_reset(dev); |
350d2706 DV |
807 | break; |
808 | case 4: | |
d4b8bb2a | 809 | ret = i965_do_reset(dev); |
350d2706 DV |
810 | break; |
811 | case 2: | |
d4b8bb2a | 812 | ret = i8xx_do_reset(dev); |
350d2706 DV |
813 | break; |
814 | } | |
815 | ||
2b9dc9a2 DV |
816 | /* Also reset the gpu hangman. */ |
817 | if (dev_priv->stop_rings) { | |
818 | DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); | |
819 | dev_priv->stop_rings = 0; | |
820 | if (ret == -ENODEV) { | |
821 | DRM_ERROR("Reset not implemented, but ignoring " | |
822 | "error for simulated gpu hangs\n"); | |
823 | ret = 0; | |
824 | } | |
825 | } | |
826 | ||
350d2706 DV |
827 | return ret; |
828 | } | |
829 | ||
11ed50ec | 830 | /** |
f3953dcb | 831 | * i915_reset - reset chip after a hang |
11ed50ec | 832 | * @dev: drm device to reset |
11ed50ec BG |
833 | * |
834 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
835 | * reset or otherwise an error code. | |
836 | * | |
837 | * Procedure is fairly simple: | |
838 | * - reset the chip using the reset reg | |
839 | * - re-init context state | |
840 | * - re-init hardware status page | |
841 | * - re-init ring buffer | |
842 | * - re-init interrupt state | |
843 | * - re-init display | |
844 | */ | |
d4b8bb2a | 845 | int i915_reset(struct drm_device *dev) |
11ed50ec BG |
846 | { |
847 | drm_i915_private_t *dev_priv = dev->dev_private; | |
0573ed4a | 848 | int ret; |
11ed50ec | 849 | |
d78cb50b CW |
850 | if (!i915_try_reset) |
851 | return 0; | |
852 | ||
340479aa CW |
853 | if (!mutex_trylock(&dev->struct_mutex)) |
854 | return -EBUSY; | |
11ed50ec | 855 | |
e5eb3d63 DV |
856 | dev_priv->stop_rings = 0; |
857 | ||
069efc1d | 858 | i915_gem_reset(dev); |
77f01230 | 859 | |
f803aa55 | 860 | ret = -ENODEV; |
350d2706 | 861 | if (get_seconds() - dev_priv->last_gpu_reset < 5) |
ae681d96 | 862 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
350d2706 | 863 | else |
d4b8bb2a | 864 | ret = intel_gpu_reset(dev); |
350d2706 | 865 | |
ae681d96 | 866 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 867 | if (ret) { |
f803aa55 | 868 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 869 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 870 | return ret; |
11ed50ec BG |
871 | } |
872 | ||
873 | /* Ok, now get things going again... */ | |
874 | ||
875 | /* | |
876 | * Everything depends on having the GTT running, so we need to start | |
877 | * there. Fortunately we don't need to do this unless we reset the | |
878 | * chip at a PCI level. | |
879 | * | |
880 | * Next we need to restore the context, but we don't use those | |
881 | * yet either... | |
882 | * | |
883 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
884 | * was running at the time of the reset (i.e. we weren't VT | |
885 | * switched away). | |
886 | */ | |
887 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 888 | !dev_priv->mm.suspended) { |
11ed50ec | 889 | dev_priv->mm.suspended = 0; |
75a6898f | 890 | |
f691e2f4 DV |
891 | i915_gem_init_swizzling(dev); |
892 | ||
1ec14ad3 | 893 | dev_priv->ring[RCS].init(&dev_priv->ring[RCS]); |
75a6898f | 894 | if (HAS_BSD(dev)) |
1ec14ad3 | 895 | dev_priv->ring[VCS].init(&dev_priv->ring[VCS]); |
75a6898f | 896 | if (HAS_BLT(dev)) |
1ec14ad3 | 897 | dev_priv->ring[BCS].init(&dev_priv->ring[BCS]); |
75a6898f | 898 | |
e21af88d DV |
899 | i915_gem_init_ppgtt(dev); |
900 | ||
11ed50ec | 901 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
902 | |
903 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
904 | intel_modeset_init_hw(dev); | |
905 | ||
11ed50ec BG |
906 | drm_irq_uninstall(dev); |
907 | drm_irq_install(dev); | |
bcbc324a DV |
908 | } else { |
909 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
910 | } |
911 | ||
11ed50ec BG |
912 | return 0; |
913 | } | |
914 | ||
915 | ||
112b715e KH |
916 | static int __devinit |
917 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
918 | { | |
5fe49d86 CW |
919 | /* Only bind to function 0 of the device. Early generations |
920 | * used function 1 as a placeholder for multi-head. This causes | |
921 | * us confusion instead, especially on the systems where both | |
922 | * functions have the same PCI-ID! | |
923 | */ | |
924 | if (PCI_FUNC(pdev->devfn)) | |
925 | return -ENODEV; | |
926 | ||
dcdb1674 | 927 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
928 | } |
929 | ||
930 | static void | |
931 | i915_pci_remove(struct pci_dev *pdev) | |
932 | { | |
933 | struct drm_device *dev = pci_get_drvdata(pdev); | |
934 | ||
935 | drm_put_dev(dev); | |
936 | } | |
937 | ||
84b79f8d | 938 | static int i915_pm_suspend(struct device *dev) |
112b715e | 939 | { |
84b79f8d RW |
940 | struct pci_dev *pdev = to_pci_dev(dev); |
941 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
942 | int error; | |
112b715e | 943 | |
84b79f8d RW |
944 | if (!drm_dev || !drm_dev->dev_private) { |
945 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
946 | return -ENODEV; | |
947 | } | |
112b715e | 948 | |
5bcf719b DA |
949 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
950 | return 0; | |
951 | ||
84b79f8d RW |
952 | error = i915_drm_freeze(drm_dev); |
953 | if (error) | |
954 | return error; | |
112b715e | 955 | |
84b79f8d RW |
956 | pci_disable_device(pdev); |
957 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 958 | |
84b79f8d | 959 | return 0; |
cbda12d7 ZW |
960 | } |
961 | ||
84b79f8d | 962 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 963 | { |
84b79f8d RW |
964 | struct pci_dev *pdev = to_pci_dev(dev); |
965 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
966 | ||
967 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
968 | } |
969 | ||
84b79f8d | 970 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 971 | { |
84b79f8d RW |
972 | struct pci_dev *pdev = to_pci_dev(dev); |
973 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
974 | ||
975 | if (!drm_dev || !drm_dev->dev_private) { | |
976 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
977 | return -ENODEV; | |
978 | } | |
979 | ||
980 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
981 | } |
982 | ||
84b79f8d | 983 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 984 | { |
84b79f8d RW |
985 | struct pci_dev *pdev = to_pci_dev(dev); |
986 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
987 | ||
988 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
989 | } |
990 | ||
84b79f8d | 991 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 992 | { |
84b79f8d RW |
993 | struct pci_dev *pdev = to_pci_dev(dev); |
994 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 995 | |
61caf87c | 996 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
997 | } |
998 | ||
b4b78d12 | 999 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
1000 | .suspend = i915_pm_suspend, |
1001 | .resume = i915_pm_resume, | |
1002 | .freeze = i915_pm_freeze, | |
1003 | .thaw = i915_pm_thaw, | |
1004 | .poweroff = i915_pm_poweroff, | |
1005 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
1006 | }; |
1007 | ||
de151cf6 JB |
1008 | static struct vm_operations_struct i915_gem_vm_ops = { |
1009 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
1010 | .open = drm_gem_vm_open, |
1011 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1012 | }; |
1013 | ||
e08e96de AV |
1014 | static const struct file_operations i915_driver_fops = { |
1015 | .owner = THIS_MODULE, | |
1016 | .open = drm_open, | |
1017 | .release = drm_release, | |
1018 | .unlocked_ioctl = drm_ioctl, | |
1019 | .mmap = drm_gem_mmap, | |
1020 | .poll = drm_poll, | |
1021 | .fasync = drm_fasync, | |
1022 | .read = drm_read, | |
1023 | #ifdef CONFIG_COMPAT | |
1024 | .compat_ioctl = i915_compat_ioctl, | |
1025 | #endif | |
1026 | .llseek = noop_llseek, | |
1027 | }; | |
1028 | ||
1da177e4 | 1029 | static struct drm_driver driver = { |
0c54781b MW |
1030 | /* Don't use MTRRs here; the Xserver or userspace app should |
1031 | * deal with them for Intel hardware. | |
792d2b9a | 1032 | */ |
673a394b EA |
1033 | .driver_features = |
1034 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
1035 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 1036 | .load = i915_driver_load, |
ba8bbcf6 | 1037 | .unload = i915_driver_unload, |
673a394b | 1038 | .open = i915_driver_open, |
22eae947 DA |
1039 | .lastclose = i915_driver_lastclose, |
1040 | .preclose = i915_driver_preclose, | |
673a394b | 1041 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1042 | |
1043 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1044 | .suspend = i915_suspend, | |
1045 | .resume = i915_resume, | |
1046 | ||
cda17380 | 1047 | .device_is_agp = i915_driver_device_is_agp, |
1da177e4 | 1048 | .reclaim_buffers = drm_core_reclaim_buffers, |
7c1c2871 DA |
1049 | .master_create = i915_master_create, |
1050 | .master_destroy = i915_master_destroy, | |
955b12de | 1051 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1052 | .debugfs_init = i915_debugfs_init, |
1053 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1054 | #endif |
673a394b EA |
1055 | .gem_init_object = i915_gem_init_object, |
1056 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 1057 | .gem_vm_ops = &i915_gem_vm_ops, |
ff72145b DA |
1058 | .dumb_create = i915_gem_dumb_create, |
1059 | .dumb_map_offset = i915_gem_mmap_gtt, | |
1060 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 | 1061 | .ioctls = i915_ioctls, |
e08e96de | 1062 | .fops = &i915_driver_fops, |
22eae947 DA |
1063 | .name = DRIVER_NAME, |
1064 | .desc = DRIVER_DESC, | |
1065 | .date = DRIVER_DATE, | |
1066 | .major = DRIVER_MAJOR, | |
1067 | .minor = DRIVER_MINOR, | |
1068 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1069 | }; |
1070 | ||
8410ea3b DA |
1071 | static struct pci_driver i915_pci_driver = { |
1072 | .name = DRIVER_NAME, | |
1073 | .id_table = pciidlist, | |
1074 | .probe = i915_pci_probe, | |
1075 | .remove = i915_pci_remove, | |
1076 | .driver.pm = &i915_pm_ops, | |
1077 | }; | |
1078 | ||
1da177e4 LT |
1079 | static int __init i915_init(void) |
1080 | { | |
1f7a6e37 ZW |
1081 | if (!intel_agp_enabled) { |
1082 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
1083 | return -ENODEV; | |
1084 | } | |
1085 | ||
1da177e4 | 1086 | driver.num_ioctls = i915_max_ioctl; |
79e53945 JB |
1087 | |
1088 | /* | |
1089 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1090 | * explicitly disabled with the module pararmeter. | |
1091 | * | |
1092 | * Otherwise, just follow the parameter (defaulting to off). | |
1093 | * | |
1094 | * Allow optional vga_text_mode_force boot option to override | |
1095 | * the default behavior. | |
1096 | */ | |
1097 | #if defined(CONFIG_DRM_I915_KMS) | |
1098 | if (i915_modeset != 0) | |
1099 | driver.driver_features |= DRIVER_MODESET; | |
1100 | #endif | |
1101 | if (i915_modeset == 1) | |
1102 | driver.driver_features |= DRIVER_MODESET; | |
1103 | ||
1104 | #ifdef CONFIG_VGA_CONSOLE | |
1105 | if (vgacon_text_force() && i915_modeset == -1) | |
1106 | driver.driver_features &= ~DRIVER_MODESET; | |
1107 | #endif | |
1108 | ||
3885c6bb CW |
1109 | if (!(driver.driver_features & DRIVER_MODESET)) |
1110 | driver.get_vblank_timestamp = NULL; | |
1111 | ||
8410ea3b | 1112 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1113 | } |
1114 | ||
1115 | static void __exit i915_exit(void) | |
1116 | { | |
8410ea3b | 1117 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1118 | } |
1119 | ||
1120 | module_init(i915_init); | |
1121 | module_exit(i915_exit); | |
1122 | ||
b5e89ed5 DA |
1123 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1124 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1125 | MODULE_LICENSE("GPL and additional rights"); |
f7000883 | 1126 | |
b7d84096 JB |
1127 | /* We give fast paths for the really cool registers */ |
1128 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
1129 | (((dev_priv)->info->gen >= 6) && \ | |
1130 | ((reg) < 0x40000) && \ | |
575155a9 JB |
1131 | ((reg) != FORCEWAKE)) && \ |
1132 | (!IS_VALLEYVIEW((dev_priv)->dev)) | |
b7d84096 | 1133 | |
f7000883 AK |
1134 | #define __i915_read(x, y) \ |
1135 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
1136 | u##x val = 0; \ | |
1137 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
c937504e KP |
1138 | unsigned long irqflags; \ |
1139 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | |
1140 | if (dev_priv->forcewake_count == 0) \ | |
1141 | dev_priv->display.force_wake_get(dev_priv); \ | |
f7000883 | 1142 | val = read##y(dev_priv->regs + reg); \ |
c937504e KP |
1143 | if (dev_priv->forcewake_count == 0) \ |
1144 | dev_priv->display.force_wake_put(dev_priv); \ | |
1145 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | |
f7000883 AK |
1146 | } else { \ |
1147 | val = read##y(dev_priv->regs + reg); \ | |
1148 | } \ | |
1149 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | |
1150 | return val; \ | |
1151 | } | |
1152 | ||
1153 | __i915_read(8, b) | |
1154 | __i915_read(16, w) | |
1155 | __i915_read(32, l) | |
1156 | __i915_read(64, q) | |
1157 | #undef __i915_read | |
1158 | ||
1159 | #define __i915_write(x, y) \ | |
1160 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
67a3744f | 1161 | u32 __fifo_ret = 0; \ |
f7000883 AK |
1162 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1163 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
67a3744f | 1164 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
f7000883 AK |
1165 | } \ |
1166 | write##y(val, dev_priv->regs + reg); \ | |
67a3744f BW |
1167 | if (unlikely(__fifo_ret)) { \ |
1168 | gen6_gt_check_fifodbg(dev_priv); \ | |
1169 | } \ | |
f7000883 AK |
1170 | } |
1171 | __i915_write(8, b) | |
1172 | __i915_write(16, w) | |
1173 | __i915_write(32, l) | |
1174 | __i915_write(64, q) | |
1175 | #undef __i915_write |