]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
354ff967 | 38 | #include "drm_crtc_helper.h" |
79e53945 | 39 | |
d6073d77 | 40 | static int i915_modeset = -1; |
79e53945 JB |
41 | module_param_named(modeset, i915_modeset, int, 0400); |
42 | ||
43 | unsigned int i915_fbpercrtc = 0; | |
44 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); | |
1da177e4 | 45 | |
652c393a JB |
46 | unsigned int i915_powersave = 1; |
47 | module_param_named(powersave, i915_powersave, int, 0400); | |
48 | ||
33814341 JB |
49 | unsigned int i915_lvds_downclock = 0; |
50 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); | |
51 | ||
112b715e | 52 | static struct drm_driver driver; |
1f7a6e37 | 53 | extern int intel_agp_enabled; |
112b715e | 54 | |
cfdf1fa2 | 55 | #define INTEL_VGA_DEVICE(id, info) { \ |
49ae35f2 KH |
56 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ |
57 | .class_mask = 0xffff00, \ | |
58 | .vendor = 0x8086, \ | |
59 | .device = id, \ | |
60 | .subvendor = PCI_ANY_ID, \ | |
61 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
62 | .driver_data = (unsigned long) info } |
63 | ||
9a7e8492 | 64 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 65 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 66 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
67 | }; |
68 | ||
9a7e8492 | 69 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 70 | .gen = 2, |
31578148 | 71 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
72 | }; |
73 | ||
9a7e8492 | 74 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 75 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 76 | .cursor_needs_physical = 1, |
31578148 | 77 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
78 | }; |
79 | ||
9a7e8492 | 80 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 81 | .gen = 2, |
31578148 | 82 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
83 | }; |
84 | ||
9a7e8492 | 85 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 86 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 87 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 88 | }; |
9a7e8492 | 89 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 90 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 91 | .cursor_needs_physical = 1, |
31578148 | 92 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 93 | .supports_tv = 1, |
cfdf1fa2 | 94 | }; |
9a7e8492 | 95 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 96 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 97 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 98 | }; |
9a7e8492 | 99 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 100 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 101 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 102 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 103 | .supports_tv = 1, |
cfdf1fa2 KH |
104 | }; |
105 | ||
9a7e8492 | 106 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 107 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 108 | .has_hotplug = 1, |
31578148 | 109 | .has_overlay = 1, |
cfdf1fa2 KH |
110 | }; |
111 | ||
9a7e8492 | 112 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 113 | .gen = 4, .is_crestline = 1, |
c96c3a8c | 114 | .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1, |
31578148 | 115 | .has_overlay = 1, |
a6c45cf0 | 116 | .supports_tv = 1, |
cfdf1fa2 KH |
117 | }; |
118 | ||
9a7e8492 | 119 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 120 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 121 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 122 | .has_overlay = 1, |
cfdf1fa2 KH |
123 | }; |
124 | ||
9a7e8492 | 125 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 126 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 127 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 128 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
129 | }; |
130 | ||
9a7e8492 | 131 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 132 | .gen = 4, .is_g4x = 1, |
cfdf1fa2 | 133 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, |
c96c3a8c | 134 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 135 | .supports_tv = 1, |
92f49d9c | 136 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
137 | }; |
138 | ||
9a7e8492 | 139 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 140 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 141 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 142 | .has_overlay = 1, |
cfdf1fa2 KH |
143 | }; |
144 | ||
9a7e8492 | 145 | static const struct intel_device_info intel_ironlake_d_info = { |
a6c45cf0 | 146 | .gen = 5, .is_ironlake = 1, |
c96c3a8c | 147 | .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 148 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
149 | }; |
150 | ||
9a7e8492 | 151 | static const struct intel_device_info intel_ironlake_m_info = { |
a6c45cf0 | 152 | .gen = 5, .is_ironlake = 1, .is_mobile = 1, |
c96c3a8c | 153 | .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1, |
92f49d9c | 154 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
155 | }; |
156 | ||
9a7e8492 | 157 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 158 | .gen = 6, |
c96c3a8c | 159 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 160 | .has_bsd_ring = 1, |
549f7365 | 161 | .has_blt_ring = 1, |
f6e450a6 EA |
162 | }; |
163 | ||
9a7e8492 | 164 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 165 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 166 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 167 | .has_bsd_ring = 1, |
549f7365 | 168 | .has_blt_ring = 1, |
a13e4093 EA |
169 | }; |
170 | ||
6103da0d CW |
171 | static const struct pci_device_id pciidlist[] = { /* aka */ |
172 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
173 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
174 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 175 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
176 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
177 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
178 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
179 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
180 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
181 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
182 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
183 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
184 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
185 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
186 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
187 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
188 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
189 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
190 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
191 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
192 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
193 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
194 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
195 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
196 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
197 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 198 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
199 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
200 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
201 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
202 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 203 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
204 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
205 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 206 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 207 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 208 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 209 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
49ae35f2 | 210 | {0, 0, 0} |
1da177e4 LT |
211 | }; |
212 | ||
79e53945 JB |
213 | #if defined(CONFIG_DRM_I915_KMS) |
214 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
215 | #endif | |
216 | ||
3bad0781 ZW |
217 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
218 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
219 | ||
220 | void intel_detect_pch (struct drm_device *dev) | |
221 | { | |
222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
223 | struct pci_dev *pch; | |
224 | ||
225 | /* | |
226 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
227 | * make graphics device passthrough work easy for VMM, that only | |
228 | * need to expose ISA bridge to let driver know the real hardware | |
229 | * underneath. This is a requirement from virtualization team. | |
230 | */ | |
231 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
232 | if (pch) { | |
233 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
234 | int id; | |
235 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
236 | ||
237 | if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
238 | dev_priv->pch_type = PCH_CPT; | |
239 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
240 | } | |
241 | } | |
242 | pci_dev_put(pch); | |
243 | } | |
244 | } | |
245 | ||
84b79f8d | 246 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 247 | { |
61caf87c RW |
248 | struct drm_i915_private *dev_priv = dev->dev_private; |
249 | ||
ba8bbcf6 | 250 | pci_save_state(dev->pdev); |
ba8bbcf6 | 251 | |
5669fcac | 252 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 253 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
254 | int error = i915_gem_idle(dev); |
255 | if (error) { | |
226485e9 | 256 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
257 | "GEM idle failed, resume might fail\n"); |
258 | return error; | |
259 | } | |
226485e9 | 260 | drm_irq_uninstall(dev); |
5669fcac JB |
261 | } |
262 | ||
9e06dd39 JB |
263 | i915_save_state(dev); |
264 | ||
44834a67 | 265 | intel_opregion_fini(dev); |
8ee1c3db | 266 | |
84b79f8d RW |
267 | /* Modeset on resume, not lid events */ |
268 | dev_priv->modeset_on_lid = 0; | |
61caf87c RW |
269 | |
270 | return 0; | |
84b79f8d RW |
271 | } |
272 | ||
6a9ee8af | 273 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
274 | { |
275 | int error; | |
276 | ||
277 | if (!dev || !dev->dev_private) { | |
278 | DRM_ERROR("dev: %p\n", dev); | |
279 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
280 | return -ENODEV; | |
281 | } | |
282 | ||
283 | if (state.event == PM_EVENT_PRETHAW) | |
284 | return 0; | |
285 | ||
6eecba33 CW |
286 | drm_kms_helper_poll_disable(dev); |
287 | ||
84b79f8d RW |
288 | error = i915_drm_freeze(dev); |
289 | if (error) | |
290 | return error; | |
291 | ||
b932ccb5 DA |
292 | if (state.event == PM_EVENT_SUSPEND) { |
293 | /* Shut down the device */ | |
294 | pci_disable_device(dev->pdev); | |
295 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
296 | } | |
ba8bbcf6 JB |
297 | |
298 | return 0; | |
299 | } | |
300 | ||
84b79f8d | 301 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 302 | { |
5669fcac | 303 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 304 | int error = 0; |
8ee1c3db | 305 | |
61caf87c | 306 | i915_restore_state(dev); |
44834a67 | 307 | intel_opregion_setup(dev); |
61caf87c | 308 | |
5669fcac JB |
309 | /* KMS EnterVT equivalent */ |
310 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
311 | mutex_lock(&dev->struct_mutex); | |
312 | dev_priv->mm.suspended = 0; | |
313 | ||
84b79f8d | 314 | error = i915_gem_init_ringbuffer(dev); |
5669fcac | 315 | mutex_unlock(&dev->struct_mutex); |
226485e9 JB |
316 | |
317 | drm_irq_install(dev); | |
84b79f8d | 318 | |
354ff967 ZY |
319 | /* Resume the modeset for every activated CRTC */ |
320 | drm_helper_resume_force_mode(dev); | |
321 | } | |
5669fcac | 322 | |
44834a67 CW |
323 | intel_opregion_init(dev); |
324 | ||
c9354c85 | 325 | dev_priv->modeset_on_lid = 0; |
06891e27 | 326 | |
84b79f8d RW |
327 | return error; |
328 | } | |
329 | ||
6a9ee8af | 330 | int i915_resume(struct drm_device *dev) |
84b79f8d | 331 | { |
6eecba33 CW |
332 | int ret; |
333 | ||
84b79f8d RW |
334 | if (pci_enable_device(dev->pdev)) |
335 | return -EIO; | |
336 | ||
337 | pci_set_master(dev->pdev); | |
338 | ||
6eecba33 CW |
339 | ret = i915_drm_thaw(dev); |
340 | if (ret) | |
341 | return ret; | |
342 | ||
343 | drm_kms_helper_poll_enable(dev); | |
344 | return 0; | |
ba8bbcf6 JB |
345 | } |
346 | ||
dc96e9b8 CW |
347 | static int i8xx_do_reset(struct drm_device *dev, u8 flags) |
348 | { | |
349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
350 | ||
351 | if (IS_I85X(dev)) | |
352 | return -ENODEV; | |
353 | ||
354 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
355 | POSTING_READ(D_STATE); | |
356 | ||
357 | if (IS_I830(dev) || IS_845G(dev)) { | |
358 | I915_WRITE(DEBUG_RESET_I830, | |
359 | DEBUG_RESET_DISPLAY | | |
360 | DEBUG_RESET_RENDER | | |
361 | DEBUG_RESET_FULL); | |
362 | POSTING_READ(DEBUG_RESET_I830); | |
363 | msleep(1); | |
364 | ||
365 | I915_WRITE(DEBUG_RESET_I830, 0); | |
366 | POSTING_READ(DEBUG_RESET_I830); | |
367 | } | |
368 | ||
369 | msleep(1); | |
370 | ||
371 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
372 | POSTING_READ(D_STATE); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
f49f0586 KG |
377 | static int i965_reset_complete(struct drm_device *dev) |
378 | { | |
379 | u8 gdrst; | |
eeccdcac | 380 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
f49f0586 KG |
381 | return gdrst & 0x1; |
382 | } | |
383 | ||
0573ed4a KG |
384 | static int i965_do_reset(struct drm_device *dev, u8 flags) |
385 | { | |
386 | u8 gdrst; | |
387 | ||
ae681d96 CW |
388 | /* |
389 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
390 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
391 | * triggers the reset; when done, the hardware will clear it. | |
392 | */ | |
0573ed4a KG |
393 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
394 | pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1); | |
395 | ||
396 | return wait_for(i965_reset_complete(dev), 500); | |
397 | } | |
398 | ||
399 | static int ironlake_do_reset(struct drm_device *dev, u8 flags) | |
400 | { | |
401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
402 | u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
403 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); | |
404 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
405 | } | |
406 | ||
11ed50ec BG |
407 | /** |
408 | * i965_reset - reset chip after a hang | |
409 | * @dev: drm device to reset | |
410 | * @flags: reset domains | |
411 | * | |
412 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
413 | * reset or otherwise an error code. | |
414 | * | |
415 | * Procedure is fairly simple: | |
416 | * - reset the chip using the reset reg | |
417 | * - re-init context state | |
418 | * - re-init hardware status page | |
419 | * - re-init ring buffer | |
420 | * - re-init interrupt state | |
421 | * - re-init display | |
422 | */ | |
f803aa55 | 423 | int i915_reset(struct drm_device *dev, u8 flags) |
11ed50ec BG |
424 | { |
425 | drm_i915_private_t *dev_priv = dev->dev_private; | |
11ed50ec BG |
426 | /* |
427 | * We really should only reset the display subsystem if we actually | |
428 | * need to | |
429 | */ | |
430 | bool need_display = true; | |
0573ed4a | 431 | int ret; |
11ed50ec BG |
432 | |
433 | mutex_lock(&dev->struct_mutex); | |
434 | ||
069efc1d | 435 | i915_gem_reset(dev); |
77f01230 | 436 | |
f803aa55 | 437 | ret = -ENODEV; |
ae681d96 CW |
438 | if (get_seconds() - dev_priv->last_gpu_reset < 5) { |
439 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); | |
440 | } else switch (INTEL_INFO(dev)->gen) { | |
f803aa55 | 441 | case 5: |
0573ed4a | 442 | ret = ironlake_do_reset(dev, flags); |
f803aa55 CW |
443 | break; |
444 | case 4: | |
0573ed4a | 445 | ret = i965_do_reset(dev, flags); |
f803aa55 | 446 | break; |
dc96e9b8 CW |
447 | case 2: |
448 | ret = i8xx_do_reset(dev, flags); | |
449 | break; | |
f803aa55 | 450 | } |
ae681d96 | 451 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 452 | if (ret) { |
f803aa55 | 453 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 454 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 455 | return ret; |
11ed50ec BG |
456 | } |
457 | ||
458 | /* Ok, now get things going again... */ | |
459 | ||
460 | /* | |
461 | * Everything depends on having the GTT running, so we need to start | |
462 | * there. Fortunately we don't need to do this unless we reset the | |
463 | * chip at a PCI level. | |
464 | * | |
465 | * Next we need to restore the context, but we don't use those | |
466 | * yet either... | |
467 | * | |
468 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
469 | * was running at the time of the reset (i.e. we weren't VT | |
470 | * switched away). | |
471 | */ | |
472 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 ZN |
473 | !dev_priv->mm.suspended) { |
474 | struct intel_ring_buffer *ring = &dev_priv->render_ring; | |
11ed50ec | 475 | dev_priv->mm.suspended = 0; |
8187a2b7 | 476 | ring->init(dev, ring); |
11ed50ec BG |
477 | mutex_unlock(&dev->struct_mutex); |
478 | drm_irq_uninstall(dev); | |
479 | drm_irq_install(dev); | |
480 | mutex_lock(&dev->struct_mutex); | |
481 | } | |
482 | ||
9fd98141 CW |
483 | mutex_unlock(&dev->struct_mutex); |
484 | ||
11ed50ec | 485 | /* |
9fd98141 CW |
486 | * Perform a full modeset as on later generations, e.g. Ironlake, we may |
487 | * need to retrain the display link and cannot just restore the register | |
488 | * values. | |
11ed50ec | 489 | */ |
9fd98141 CW |
490 | if (need_display) { |
491 | mutex_lock(&dev->mode_config.mutex); | |
492 | drm_helper_resume_force_mode(dev); | |
493 | mutex_unlock(&dev->mode_config.mutex); | |
494 | } | |
11ed50ec | 495 | |
11ed50ec BG |
496 | return 0; |
497 | } | |
498 | ||
499 | ||
112b715e KH |
500 | static int __devinit |
501 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
502 | { | |
dcdb1674 | 503 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
504 | } |
505 | ||
506 | static void | |
507 | i915_pci_remove(struct pci_dev *pdev) | |
508 | { | |
509 | struct drm_device *dev = pci_get_drvdata(pdev); | |
510 | ||
511 | drm_put_dev(dev); | |
512 | } | |
513 | ||
84b79f8d | 514 | static int i915_pm_suspend(struct device *dev) |
112b715e | 515 | { |
84b79f8d RW |
516 | struct pci_dev *pdev = to_pci_dev(dev); |
517 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
518 | int error; | |
112b715e | 519 | |
84b79f8d RW |
520 | if (!drm_dev || !drm_dev->dev_private) { |
521 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
522 | return -ENODEV; | |
523 | } | |
112b715e | 524 | |
84b79f8d RW |
525 | error = i915_drm_freeze(drm_dev); |
526 | if (error) | |
527 | return error; | |
112b715e | 528 | |
84b79f8d RW |
529 | pci_disable_device(pdev); |
530 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 531 | |
84b79f8d | 532 | return 0; |
cbda12d7 ZW |
533 | } |
534 | ||
84b79f8d | 535 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 536 | { |
84b79f8d RW |
537 | struct pci_dev *pdev = to_pci_dev(dev); |
538 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
539 | ||
540 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
541 | } |
542 | ||
84b79f8d | 543 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 544 | { |
84b79f8d RW |
545 | struct pci_dev *pdev = to_pci_dev(dev); |
546 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
547 | ||
548 | if (!drm_dev || !drm_dev->dev_private) { | |
549 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
550 | return -ENODEV; | |
551 | } | |
552 | ||
553 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
554 | } |
555 | ||
84b79f8d | 556 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 557 | { |
84b79f8d RW |
558 | struct pci_dev *pdev = to_pci_dev(dev); |
559 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
560 | ||
561 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
562 | } |
563 | ||
84b79f8d | 564 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 565 | { |
84b79f8d RW |
566 | struct pci_dev *pdev = to_pci_dev(dev); |
567 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 568 | |
61caf87c | 569 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
570 | } |
571 | ||
b4b78d12 | 572 | static const struct dev_pm_ops i915_pm_ops = { |
cbda12d7 ZW |
573 | .suspend = i915_pm_suspend, |
574 | .resume = i915_pm_resume, | |
575 | .freeze = i915_pm_freeze, | |
576 | .thaw = i915_pm_thaw, | |
577 | .poweroff = i915_pm_poweroff, | |
84b79f8d | 578 | .restore = i915_pm_resume, |
cbda12d7 ZW |
579 | }; |
580 | ||
de151cf6 JB |
581 | static struct vm_operations_struct i915_gem_vm_ops = { |
582 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
583 | .open = drm_gem_vm_open, |
584 | .close = drm_gem_vm_close, | |
de151cf6 JB |
585 | }; |
586 | ||
1da177e4 | 587 | static struct drm_driver driver = { |
792d2b9a DA |
588 | /* don't use mtrr's here, the Xserver or user space app should |
589 | * deal with them for intel hardware. | |
590 | */ | |
673a394b EA |
591 | .driver_features = |
592 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
593 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 594 | .load = i915_driver_load, |
ba8bbcf6 | 595 | .unload = i915_driver_unload, |
673a394b | 596 | .open = i915_driver_open, |
22eae947 DA |
597 | .lastclose = i915_driver_lastclose, |
598 | .preclose = i915_driver_preclose, | |
673a394b | 599 | .postclose = i915_driver_postclose, |
d8e29209 RW |
600 | |
601 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
602 | .suspend = i915_suspend, | |
603 | .resume = i915_resume, | |
604 | ||
cda17380 | 605 | .device_is_agp = i915_driver_device_is_agp, |
0a3e67a4 JB |
606 | .enable_vblank = i915_enable_vblank, |
607 | .disable_vblank = i915_disable_vblank, | |
1da177e4 LT |
608 | .irq_preinstall = i915_driver_irq_preinstall, |
609 | .irq_postinstall = i915_driver_irq_postinstall, | |
610 | .irq_uninstall = i915_driver_irq_uninstall, | |
611 | .irq_handler = i915_driver_irq_handler, | |
612 | .reclaim_buffers = drm_core_reclaim_buffers, | |
7c1c2871 DA |
613 | .master_create = i915_master_create, |
614 | .master_destroy = i915_master_destroy, | |
955b12de | 615 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
616 | .debugfs_init = i915_debugfs_init, |
617 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 618 | #endif |
673a394b EA |
619 | .gem_init_object = i915_gem_init_object, |
620 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 621 | .gem_vm_ops = &i915_gem_vm_ops, |
1da177e4 LT |
622 | .ioctls = i915_ioctls, |
623 | .fops = { | |
b5e89ed5 DA |
624 | .owner = THIS_MODULE, |
625 | .open = drm_open, | |
626 | .release = drm_release, | |
ed8b6704 | 627 | .unlocked_ioctl = drm_ioctl, |
de151cf6 | 628 | .mmap = drm_gem_mmap, |
b5e89ed5 DA |
629 | .poll = drm_poll, |
630 | .fasync = drm_fasync, | |
c9a9c5e0 | 631 | .read = drm_read, |
8ca7c1df | 632 | #ifdef CONFIG_COMPAT |
b5e89ed5 | 633 | .compat_ioctl = i915_compat_ioctl, |
8ca7c1df | 634 | #endif |
22eae947 DA |
635 | }, |
636 | ||
1da177e4 | 637 | .pci_driver = { |
22eae947 DA |
638 | .name = DRIVER_NAME, |
639 | .id_table = pciidlist, | |
112b715e KH |
640 | .probe = i915_pci_probe, |
641 | .remove = i915_pci_remove, | |
cbda12d7 | 642 | .driver.pm = &i915_pm_ops, |
22eae947 | 643 | }, |
bc5f4523 | 644 | |
22eae947 DA |
645 | .name = DRIVER_NAME, |
646 | .desc = DRIVER_DESC, | |
647 | .date = DRIVER_DATE, | |
648 | .major = DRIVER_MAJOR, | |
649 | .minor = DRIVER_MINOR, | |
650 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
651 | }; |
652 | ||
653 | static int __init i915_init(void) | |
654 | { | |
1f7a6e37 ZW |
655 | if (!intel_agp_enabled) { |
656 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
657 | return -ENODEV; | |
658 | } | |
659 | ||
1da177e4 | 660 | driver.num_ioctls = i915_max_ioctl; |
79e53945 | 661 | |
31169714 CW |
662 | i915_gem_shrinker_init(); |
663 | ||
79e53945 JB |
664 | /* |
665 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
666 | * explicitly disabled with the module pararmeter. | |
667 | * | |
668 | * Otherwise, just follow the parameter (defaulting to off). | |
669 | * | |
670 | * Allow optional vga_text_mode_force boot option to override | |
671 | * the default behavior. | |
672 | */ | |
673 | #if defined(CONFIG_DRM_I915_KMS) | |
674 | if (i915_modeset != 0) | |
675 | driver.driver_features |= DRIVER_MODESET; | |
676 | #endif | |
677 | if (i915_modeset == 1) | |
678 | driver.driver_features |= DRIVER_MODESET; | |
679 | ||
680 | #ifdef CONFIG_VGA_CONSOLE | |
681 | if (vgacon_text_force() && i915_modeset == -1) | |
682 | driver.driver_features &= ~DRIVER_MODESET; | |
683 | #endif | |
684 | ||
f97108d1 JB |
685 | if (!(driver.driver_features & DRIVER_MODESET)) { |
686 | driver.suspend = i915_suspend; | |
687 | driver.resume = i915_resume; | |
688 | } | |
689 | ||
1da177e4 LT |
690 | return drm_init(&driver); |
691 | } | |
692 | ||
693 | static void __exit i915_exit(void) | |
694 | { | |
31169714 | 695 | i915_gem_shrinker_exit(); |
1da177e4 LT |
696 | drm_exit(&driver); |
697 | } | |
698 | ||
699 | module_init(i915_init); | |
700 | module_exit(i915_exit); | |
701 | ||
b5e89ed5 DA |
702 | MODULE_AUTHOR(DRIVER_AUTHOR); |
703 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 704 | MODULE_LICENSE("GPL and additional rights"); |