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drm/i915: Make INTEL_GEN only take dev_priv
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
0673ad47
CW		 46#include <drm/i915_drm.h>
47
48#include "i915_drv.h"
49#include "i915_trace.h"
50#include "i915_vgpu.h"
51#include "intel_drv.h"
79e53945 52
112b715e
KH		 53static struct drm_driver driver;
54
0673ad47
CW		 55static unsigned int i915_load_fail_count;
56
57bool __i915_inject_load_failure(const char *func, int line)
58{
59 if (i915_load_fail_count >= i915.inject_load_failure)
60 return false;
61
62 if (++i915_load_fail_count == i915.inject_load_failure) {
63 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
64 i915.inject_load_failure, func, line);
65 return true;
66 }
67
68 return false;
69}
70
71#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
72#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
73 "providing the dmesg log by booting with drm.debug=0xf"
74
75void
76__i915_printk(struct drm_i915_private *dev_priv, const char *level,
77 const char *fmt, ...)
78{
79 static bool shown_bug_once;
c49d13ee 80 struct device *kdev = dev_priv->drm.dev;
0673ad47
CW		 81 bool is_error = level[1] <= KERN_ERR[1];
82 bool is_debug = level[1] == KERN_DEBUG[1];
83 struct va_format vaf;
84 va_list args;
85
86 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
87 return;
88
89 va_start(args, fmt);
90
91 vaf.fmt = fmt;
92 vaf.va = &args;
93
c49d13ee 94 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
0673ad47
CW		 95 __builtin_return_address(0), &vaf);
96
97 if (is_error && !shown_bug_once) {
c49d13ee 98 dev_notice(kdev, "%s", FDO_BUG_MSG);
0673ad47
CW		 99 shown_bug_once = true;
100 }
101
102 va_end(args);
103}
104
105static bool i915_error_injected(struct drm_i915_private *dev_priv)
106{
107 return i915.inject_load_failure &&
108 i915_load_fail_count == i915.inject_load_failure;
109}
110
111#define i915_load_error(dev_priv, fmt, ...) \
112 __i915_printk(dev_priv, \
113 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
114 fmt, ##__VA_ARGS__)
115
116
fd6b8f43 117static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
0673ad47
CW		 118{
119 enum intel_pch ret = PCH_NOP;
120
121 /*
122 * In a virtualized passthrough environment we can be in a
123 * setup where the ISA bridge is not able to be passed through.
124 * In this case, a south bridge can be emulated and we have to
125 * make an educated guess as to which PCH is really there.
126 */
127
fd6b8f43 128 if (IS_GEN5(dev_priv)) {
0673ad47
CW		 129 ret = PCH_IBX;
130 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
fd6b8f43 131 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
0673ad47
CW		 132 ret = PCH_CPT;
133 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
fd6b8f43 134 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0673ad47
CW		 135 ret = PCH_LPT;
136 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
fd6b8f43 137 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
0673ad47
CW		 138 ret = PCH_SPT;
139 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
140 }
141
142 return ret;
143}
144
145static void intel_detect_pch(struct drm_device *dev)
146{
fac5e23e 147 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 148 struct pci_dev *pch = NULL;
149
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
152 */
153 if (INTEL_INFO(dev)->num_pipes == 0) {
154 dev_priv->pch_type = PCH_NOP;
155 return;
156 }
157
158 /*
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
163 *
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
168 */
169 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
170 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
171 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
172 dev_priv->pch_id = id;
173
174 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
175 dev_priv->pch_type = PCH_IBX;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
177 WARN_ON(!IS_GEN5(dev));
178 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
179 dev_priv->pch_type = PCH_CPT;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
fd6b8f43
TU		 181 WARN_ON(!(IS_GEN6(dev_priv) ||
182 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 183 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
184 /* PantherPoint is CPT compatible */
185 dev_priv->pch_type = PCH_CPT;
186 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
fd6b8f43
TU		 187 WARN_ON(!(IS_GEN6(dev_priv) ||
188 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 189 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
190 dev_priv->pch_type = PCH_LPT;
191 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
8652744b
TU		 192 WARN_ON(!IS_HASWELL(dev_priv) &&
193 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 194 WARN_ON(IS_HSW_ULT(dev_priv) ||
195 IS_BDW_ULT(dev_priv));
0673ad47
CW		 196 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
197 dev_priv->pch_type = PCH_LPT;
198 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
8652744b
TU		 199 WARN_ON(!IS_HASWELL(dev_priv) &&
200 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 201 WARN_ON(!IS_HSW_ULT(dev_priv) &&
202 !IS_BDW_ULT(dev_priv));
0673ad47
CW		 203 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
204 dev_priv->pch_type = PCH_SPT;
205 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
0853723b
TU		 206 WARN_ON(!IS_SKYLAKE(dev_priv) &&
207 !IS_KABYLAKE(dev_priv));
0673ad47
CW		 208 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
209 dev_priv->pch_type = PCH_SPT;
210 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
0853723b
TU		 211 WARN_ON(!IS_SKYLAKE(dev_priv) &&
212 !IS_KABYLAKE(dev_priv));
22dea0be
RV		 213 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
214 dev_priv->pch_type = PCH_KBP;
215 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
0853723b 216 WARN_ON(!IS_KABYLAKE(dev_priv));
0673ad47
CW		 217 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
218 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
219 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
220 pch->subsystem_vendor ==
221 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
222 pch->subsystem_device ==
223 PCI_SUBDEVICE_ID_QEMU)) {
fd6b8f43
TU		 224 dev_priv->pch_type =
225 intel_virt_detect_pch(dev_priv);
0673ad47
CW		 226 } else
227 continue;
228
229 break;
230 }
231 }
232 if (!pch)
233 DRM_DEBUG_KMS("No PCH found.\n");
234
235 pci_dev_put(pch);
236}
237
0673ad47
CW		 238static int i915_getparam(struct drm_device *dev, void *data,
239 struct drm_file *file_priv)
240{
fac5e23e 241 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 242 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 243 drm_i915_getparam_t *param = data;
244 int value;
245
246 switch (param->param) {
247 case I915_PARAM_IRQ_ACTIVE:
248 case I915_PARAM_ALLOW_BATCHBUFFER:
249 case I915_PARAM_LAST_DISPATCH:
250 /* Reject all old ums/dri params. */
251 return -ENODEV;
252 case I915_PARAM_CHIPSET_ID:
52a05c30 253 value = pdev->device;
0673ad47
CW		 254 break;
255 case I915_PARAM_REVISION:
52a05c30 256 value = pdev->revision;
0673ad47 257 break;
0673ad47
CW		 258 case I915_PARAM_NUM_FENCES_AVAIL:
259 value = dev_priv->num_fence_regs;
260 break;
261 case I915_PARAM_HAS_OVERLAY:
262 value = dev_priv->overlay ? 1 : 0;
263 break;
0673ad47 264 case I915_PARAM_HAS_BSD:
3b3f1650 265 value = !!dev_priv->engine[VCS];
0673ad47
CW		 266 break;
267 case I915_PARAM_HAS_BLT:
3b3f1650 268 value = !!dev_priv->engine[BCS];
0673ad47
CW		 269 break;
270 case I915_PARAM_HAS_VEBOX:
3b3f1650 271 value = !!dev_priv->engine[VECS];
0673ad47
CW		 272 break;
273 case I915_PARAM_HAS_BSD2:
3b3f1650 274 value = !!dev_priv->engine[VCS2];
0673ad47 275 break;
0673ad47 276 case I915_PARAM_HAS_EXEC_CONSTANTS:
16162470 277 value = INTEL_GEN(dev_priv) >= 4;
0673ad47
CW		 278 break;
279 case I915_PARAM_HAS_LLC:
16162470 280 value = HAS_LLC(dev_priv);
0673ad47
CW		 281 break;
282 case I915_PARAM_HAS_WT:
16162470 283 value = HAS_WT(dev_priv);
0673ad47
CW		 284 break;
285 case I915_PARAM_HAS_ALIASING_PPGTT:
16162470 286 value = USES_PPGTT(dev_priv);
0673ad47
CW		 287 break;
288 case I915_PARAM_HAS_SEMAPHORES:
39df9190 289 value = i915.semaphores;
0673ad47 290 break;
0673ad47
CW		 291 case I915_PARAM_HAS_SECURE_BATCHES:
292 value = capable(CAP_SYS_ADMIN);
293 break;
0673ad47
CW		 294 case I915_PARAM_CMD_PARSER_VERSION:
295 value = i915_cmd_parser_get_version(dev_priv);
296 break;
0673ad47 297 case I915_PARAM_SUBSLICE_TOTAL:
57ec171e 298 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
0673ad47
CW		 299 if (!value)
300 return -ENODEV;
301 break;
302 case I915_PARAM_EU_TOTAL:
43b67998 303 value = INTEL_INFO(dev_priv)->sseu.eu_total;
0673ad47
CW		 304 if (!value)
305 return -ENODEV;
306 break;
307 case I915_PARAM_HAS_GPU_RESET:
308 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
309 break;
310 case I915_PARAM_HAS_RESOURCE_STREAMER:
16162470 311 value = HAS_RESOURCE_STREAMER(dev_priv);
0673ad47 312 break;
37f501af 313 case I915_PARAM_HAS_POOLED_EU:
16162470 314 value = HAS_POOLED_EU(dev_priv);
37f501af 315 break;
316 case I915_PARAM_MIN_EU_IN_POOL:
43b67998 317 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
37f501af 318 break;
4cc69075
CW		 319 case I915_PARAM_MMAP_GTT_VERSION:
320 /* Though we've started our numbering from 1, and so class all
321 * earlier versions as 0, in effect their value is undefined as
322 * the ioctl will report EINVAL for the unknown param!
323 */
324 value = i915_gem_mmap_gtt_version();
325 break;
16162470
DW		 326 case I915_PARAM_MMAP_VERSION:
327 /* Remember to bump this if the version changes! */
328 case I915_PARAM_HAS_GEM:
329 case I915_PARAM_HAS_PAGEFLIPPING:
330 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
331 case I915_PARAM_HAS_RELAXED_FENCING:
332 case I915_PARAM_HAS_COHERENT_RINGS:
333 case I915_PARAM_HAS_RELAXED_DELTA:
334 case I915_PARAM_HAS_GEN7_SOL_RESET:
335 case I915_PARAM_HAS_WAIT_TIMEOUT:
336 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
337 case I915_PARAM_HAS_PINNED_BATCHES:
338 case I915_PARAM_HAS_EXEC_NO_RELOC:
339 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
340 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
341 case I915_PARAM_HAS_EXEC_SOFTPIN:
342 /* For the time being all of these are always true;
343 * if some supported hardware does not have one of these
344 * features this value needs to be provided from
345 * INTEL_INFO(), a feature macro, or similar.
346 */
347 value = 1;
348 break;
0673ad47
CW		 349 default:
350 DRM_DEBUG("Unknown parameter %d\n", param->param);
351 return -EINVAL;
352 }
353
dda33009 354 if (put_user(value, param->value))
0673ad47 355 return -EFAULT;
0673ad47
CW		 356
357 return 0;
358}
359
360static int i915_get_bridge_dev(struct drm_device *dev)
361{
fac5e23e 362 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 363
364 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
365 if (!dev_priv->bridge_dev) {
366 DRM_ERROR("bridge device not found\n");
367 return -1;
368 }
369 return 0;
370}
371
372/* Allocate space for the MCH regs if needed, return nonzero on error */
373static int
374intel_alloc_mchbar_resource(struct drm_device *dev)
375{
fac5e23e 376 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 377 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
378 u32 temp_lo, temp_hi = 0;
379 u64 mchbar_addr;
380 int ret;
381
382 if (INTEL_INFO(dev)->gen >= 4)
383 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
384 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
385 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
386
387 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
388#ifdef CONFIG_PNP
389 if (mchbar_addr &&
390 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
391 return 0;
392#endif
393
394 /* Get some space for it */
395 dev_priv->mch_res.name = "i915 MCHBAR";
396 dev_priv->mch_res.flags = IORESOURCE_MEM;
397 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
398 &dev_priv->mch_res,
399 MCHBAR_SIZE, MCHBAR_SIZE,
400 PCIBIOS_MIN_MEM,
401 0, pcibios_align_resource,
402 dev_priv->bridge_dev);
403 if (ret) {
404 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
405 dev_priv->mch_res.start = 0;
406 return ret;
407 }
408
409 if (INTEL_INFO(dev)->gen >= 4)
410 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
411 upper_32_bits(dev_priv->mch_res.start));
412
413 pci_write_config_dword(dev_priv->bridge_dev, reg,
414 lower_32_bits(dev_priv->mch_res.start));
415 return 0;
416}
417
418/* Setup MCHBAR if possible, return true if we should disable it again */
419static void
420intel_setup_mchbar(struct drm_device *dev)
421{
fac5e23e 422 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 423 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
424 u32 temp;
425 bool enabled;
426
920a14b2 427 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0673ad47
CW		 428 return;
429
430 dev_priv->mchbar_need_disable = false;
431
50a0bc90 432 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 433 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
434 enabled = !!(temp & DEVEN_MCHBAR_EN);
435 } else {
436 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
437 enabled = temp & 1;
438 }
439
440 /* If it's already enabled, don't have to do anything */
441 if (enabled)
442 return;
443
444 if (intel_alloc_mchbar_resource(dev))
445 return;
446
447 dev_priv->mchbar_need_disable = true;
448
449 /* Space is allocated or reserved, so enable it. */
50a0bc90 450 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 451 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
452 temp | DEVEN_MCHBAR_EN);
453 } else {
454 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
455 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
456 }
457}
458
459static void
460intel_teardown_mchbar(struct drm_device *dev)
461{
fac5e23e 462 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 463 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
464
465 if (dev_priv->mchbar_need_disable) {
50a0bc90 466 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 467 u32 deven_val;
468
469 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
470 &deven_val);
471 deven_val &= ~DEVEN_MCHBAR_EN;
472 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
473 deven_val);
474 } else {
475 u32 mchbar_val;
476
477 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
478 &mchbar_val);
479 mchbar_val &= ~1;
480 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
481 mchbar_val);
482 }
483 }
484
485 if (dev_priv->mch_res.start)
486 release_resource(&dev_priv->mch_res);
487}
488
489/* true = enable decode, false = disable decoder */
490static unsigned int i915_vga_set_decode(void *cookie, bool state)
491{
492 struct drm_device *dev = cookie;
493
494 intel_modeset_vga_set_state(dev, state);
495 if (state)
496 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
497 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
498 else
499 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
500}
501
502static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
503{
504 struct drm_device *dev = pci_get_drvdata(pdev);
505 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
506
507 if (state == VGA_SWITCHEROO_ON) {
508 pr_info("switched on\n");
509 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
510 /* i915 resume handler doesn't set to D0 */
52a05c30 511 pci_set_power_state(pdev, PCI_D0);
0673ad47
CW		 512 i915_resume_switcheroo(dev);
513 dev->switch_power_state = DRM_SWITCH_POWER_ON;
514 } else {
515 pr_info("switched off\n");
516 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
517 i915_suspend_switcheroo(dev, pmm);
518 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
519 }
520}
521
522static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
523{
524 struct drm_device *dev = pci_get_drvdata(pdev);
525
526 /*
527 * FIXME: open_count is protected by drm_global_mutex but that would lead to
528 * locking inversion with the driver load path. And the access here is
529 * completely racy anyway. So don't bother with locking for now.
530 */
531 return dev->open_count == 0;
532}
533
534static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
535 .set_gpu_state = i915_switcheroo_set_state,
536 .reprobe = NULL,
537 .can_switch = i915_switcheroo_can_switch,
538};
539
540static void i915_gem_fini(struct drm_device *dev)
541{
0673ad47 542 mutex_lock(&dev->struct_mutex);
0673ad47
CW		 543 i915_gem_cleanup_engines(dev);
544 i915_gem_context_fini(dev);
545 mutex_unlock(&dev->struct_mutex);
546
547 WARN_ON(!list_empty(&to_i915(dev)->context_list));
548}
549
550static int i915_load_modeset_init(struct drm_device *dev)
551{
fac5e23e 552 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 553 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 554 int ret;
555
556 if (i915_inject_load_failure())
557 return -ENODEV;
558
559 ret = intel_bios_init(dev_priv);
560 if (ret)
561 DRM_INFO("failed to find VBIOS tables\n");
562
563 /* If we have > 1 VGA cards, then we need to arbitrate access
564 * to the common VGA resources.
565 *
566 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
567 * then we do not take part in VGA arbitration and the
568 * vga_client_register() fails with -ENODEV.
569 */
52a05c30 570 ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
0673ad47
CW		 571 if (ret && ret != -ENODEV)
572 goto out;
573
574 intel_register_dsm_handler();
575
52a05c30 576 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
0673ad47
CW		 577 if (ret)
578 goto cleanup_vga_client;
579
580 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
581 intel_update_rawclk(dev_priv);
582
583 intel_power_domains_init_hw(dev_priv, false);
584
585 intel_csr_ucode_init(dev_priv);
586
587 ret = intel_irq_install(dev_priv);
588 if (ret)
589 goto cleanup_csr;
590
591 intel_setup_gmbus(dev);
592
593 /* Important: The output setup functions called by modeset_init need
594 * working irqs for e.g. gmbus and dp aux transfers. */
595 intel_modeset_init(dev);
596
597 intel_guc_init(dev);
598
599 ret = i915_gem_init(dev);
600 if (ret)
601 goto cleanup_irq;
602
603 intel_modeset_gem_init(dev);
604
605 if (INTEL_INFO(dev)->num_pipes == 0)
606 return 0;
607
608 ret = intel_fbdev_init(dev);
609 if (ret)
610 goto cleanup_gem;
611
612 /* Only enable hotplug handling once the fbdev is fully set up. */
613 intel_hpd_init(dev_priv);
614
615 drm_kms_helper_poll_init(dev);
616
617 return 0;
618
619cleanup_gem:
1c777c5d
ID		 620 if (i915_gem_suspend(dev))
621 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
0673ad47
CW		 622 i915_gem_fini(dev);
623cleanup_irq:
624 intel_guc_fini(dev);
625 drm_irq_uninstall(dev);
626 intel_teardown_gmbus(dev);
627cleanup_csr:
628 intel_csr_ucode_fini(dev_priv);
629 intel_power_domains_fini(dev_priv);
52a05c30 630 vga_switcheroo_unregister_client(pdev);
0673ad47 631cleanup_vga_client:
52a05c30 632 vga_client_register(pdev, NULL, NULL, NULL);
0673ad47
CW		 633out:
634 return ret;
635}
636
637#if IS_ENABLED(CONFIG_FB)
638static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
639{
640 struct apertures_struct *ap;
91c8a326 641 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 642 struct i915_ggtt *ggtt = &dev_priv->ggtt;
643 bool primary;
644 int ret;
645
646 ap = alloc_apertures(1);
647 if (!ap)
648 return -ENOMEM;
649
650 ap->ranges[0].base = ggtt->mappable_base;
651 ap->ranges[0].size = ggtt->mappable_end;
652
653 primary =
654 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
655
44adece5 656 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
0673ad47
CW		 657
658 kfree(ap);
659
660 return ret;
661}
662#else
663static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
664{
665 return 0;
666}
667#endif
668
669#if !defined(CONFIG_VGA_CONSOLE)
670static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
671{
672 return 0;
673}
674#elif !defined(CONFIG_DUMMY_CONSOLE)
675static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
676{
677 return -ENODEV;
678}
679#else
680static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
681{
682 int ret = 0;
683
684 DRM_INFO("Replacing VGA console driver\n");
685
686 console_lock();
687 if (con_is_bound(&vga_con))
688 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
689 if (ret == 0) {
690 ret = do_unregister_con_driver(&vga_con);
691
692 /* Ignore "already unregistered". */
693 if (ret == -ENODEV)
694 ret = 0;
695 }
696 console_unlock();
697
698 return ret;
699}
700#endif
701
0673ad47
CW		 702static void intel_init_dpio(struct drm_i915_private *dev_priv)
703{
704 /*
705 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
706 * CHV x1 PHY (DP/HDMI D)
707 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
708 */
709 if (IS_CHERRYVIEW(dev_priv)) {
710 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
711 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
712 } else if (IS_VALLEYVIEW(dev_priv)) {
713 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
714 }
715}
716
717static int i915_workqueues_init(struct drm_i915_private *dev_priv)
718{
719 /*
720 * The i915 workqueue is primarily used for batched retirement of
721 * requests (and thus managing bo) once the task has been completed
722 * by the GPU. i915_gem_retire_requests() is called directly when we
723 * need high-priority retirement, such as waiting for an explicit
724 * bo.
725 *
726 * It is also used for periodic low-priority events, such as
727 * idle-timers and recording error state.
728 *
729 * All tasks on the workqueue are expected to acquire the dev mutex
730 * so there is no point in running more than one instance of the
731 * workqueue at any time. Use an ordered one.
732 */
733 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
734 if (dev_priv->wq == NULL)
735 goto out_err;
736
737 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
738 if (dev_priv->hotplug.dp_wq == NULL)
739 goto out_free_wq;
740
0673ad47
CW		 741 return 0;
742
0673ad47
CW		 743out_free_wq:
744 destroy_workqueue(dev_priv->wq);
745out_err:
746 DRM_ERROR("Failed to allocate workqueues.\n");
747
748 return -ENOMEM;
749}
750
751static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
752{
0673ad47
CW		 753 destroy_workqueue(dev_priv->hotplug.dp_wq);
754 destroy_workqueue(dev_priv->wq);
755}
756
4fc7e845
PZ		 757/*
758 * We don't keep the workarounds for pre-production hardware, so we expect our
759 * driver to fail on these machines in one way or another. A little warning on
760 * dmesg may help both the user and the bug triagers.
761 */
762static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
763{
764 if (IS_HSW_EARLY_SDV(dev_priv) ||
765 IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
766 DRM_ERROR("This is a pre-production stepping. "
767 "It may not be fully functional.\n");
768}
769
0673ad47
CW		 770/**
771 * i915_driver_init_early - setup state not requiring device access
772 * @dev_priv: device private
773 *
774 * Initialize everything that is a "SW-only" state, that is state not
775 * requiring accessing the device or exposing the driver via kernel internal
776 * or userspace interfaces. Example steps belonging here: lock initialization,
777 * system memory allocation, setting up device specific attributes and
778 * function hooks not requiring accessing the device.
779 */
780static int i915_driver_init_early(struct drm_i915_private *dev_priv,
781 const struct pci_device_id *ent)
782{
783 const struct intel_device_info *match_info =
784 (struct intel_device_info *)ent->driver_data;
785 struct intel_device_info *device_info;
786 int ret = 0;
787
788 if (i915_inject_load_failure())
789 return -ENODEV;
790
791 /* Setup the write-once "constant" device info */
94b4f3ba 792 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 793 memcpy(device_info, match_info, sizeof(*device_info));
794 device_info->device_id = dev_priv->drm.pdev->device;
795
796 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
797 device_info->gen_mask = BIT(device_info->gen - 1);
798
799 spin_lock_init(&dev_priv->irq_lock);
800 spin_lock_init(&dev_priv->gpu_error.lock);
801 mutex_init(&dev_priv->backlight_lock);
802 spin_lock_init(&dev_priv->uncore.lock);
803 spin_lock_init(&dev_priv->mm.object_stat_lock);
804 spin_lock_init(&dev_priv->mmio_flip_lock);
805 mutex_init(&dev_priv->sb_lock);
806 mutex_init(&dev_priv->modeset_restore_lock);
807 mutex_init(&dev_priv->av_mutex);
808 mutex_init(&dev_priv->wm.wm_mutex);
809 mutex_init(&dev_priv->pps_mutex);
810
0b1de5d5
CW		 811 i915_memcpy_init_early(dev_priv);
812
0673ad47
CW		 813 ret = i915_workqueues_init(dev_priv);
814 if (ret < 0)
815 return ret;
816
817 ret = intel_gvt_init(dev_priv);
818 if (ret < 0)
819 goto err_workqueues;
820
821 /* This must be called before any calls to HAS_PCH_* */
822 intel_detect_pch(&dev_priv->drm);
823
824 intel_pm_setup(&dev_priv->drm);
825 intel_init_dpio(dev_priv);
826 intel_power_domains_init(dev_priv);
827 intel_irq_init(dev_priv);
828 intel_init_display_hooks(dev_priv);
829 intel_init_clock_gating_hooks(dev_priv);
830 intel_init_audio_hooks(dev_priv);
831 i915_gem_load_init(&dev_priv->drm);
832
36cdd013 833 intel_display_crc_init(dev_priv);
0673ad47 834
94b4f3ba 835 intel_device_info_dump(dev_priv);
0673ad47 836
4fc7e845 837 intel_detect_preproduction_hw(dev_priv);
0673ad47
CW		 838
839 return 0;
840
841err_workqueues:
842 i915_workqueues_cleanup(dev_priv);
843 return ret;
844}
845
846/**
847 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
848 * @dev_priv: device private
849 */
850static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
851{
91c8a326 852 i915_gem_load_cleanup(&dev_priv->drm);
0673ad47
CW		 853 i915_workqueues_cleanup(dev_priv);
854}
855
856static int i915_mmio_setup(struct drm_device *dev)
857{
858 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 859 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 860 int mmio_bar;
861 int mmio_size;
862
863 mmio_bar = IS_GEN2(dev) ? 1 : 0;
864 /*
865 * Before gen4, the registers and the GTT are behind different BARs.
866 * However, from gen4 onwards, the registers and the GTT are shared
867 * in the same BAR, so we want to restrict this ioremap from
868 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
869 * the register BAR remains the same size for all the earlier
870 * generations up to Ironlake.
871 */
872 if (INTEL_INFO(dev)->gen < 5)
873 mmio_size = 512 * 1024;
874 else
875 mmio_size = 2 * 1024 * 1024;
52a05c30 876 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
0673ad47
CW		 877 if (dev_priv->regs == NULL) {
878 DRM_ERROR("failed to map registers\n");
879
880 return -EIO;
881 }
882
883 /* Try to make sure MCHBAR is enabled before poking at it */
884 intel_setup_mchbar(dev);
885
886 return 0;
887}
888
889static void i915_mmio_cleanup(struct drm_device *dev)
890{
891 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 892 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 893
894 intel_teardown_mchbar(dev);
52a05c30 895 pci_iounmap(pdev, dev_priv->regs);
0673ad47
CW		 896}
897
898/**
899 * i915_driver_init_mmio - setup device MMIO
900 * @dev_priv: device private
901 *
902 * Setup minimal device state necessary for MMIO accesses later in the
903 * initialization sequence. The setup here should avoid any other device-wide
904 * side effects or exposing the driver via kernel internal or user space
905 * interfaces.
906 */
907static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
908{
91c8a326 909 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 910 int ret;
911
912 if (i915_inject_load_failure())
913 return -ENODEV;
914
915 if (i915_get_bridge_dev(dev))
916 return -EIO;
917
918 ret = i915_mmio_setup(dev);
919 if (ret < 0)
920 goto put_bridge;
921
922 intel_uncore_init(dev_priv);
923
924 return 0;
925
926put_bridge:
927 pci_dev_put(dev_priv->bridge_dev);
928
929 return ret;
930}
931
932/**
933 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
934 * @dev_priv: device private
935 */
936static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
937{
91c8a326 938 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 939
940 intel_uncore_fini(dev_priv);
941 i915_mmio_cleanup(dev);
942 pci_dev_put(dev_priv->bridge_dev);
943}
944
94b4f3ba
CW		 945static void intel_sanitize_options(struct drm_i915_private *dev_priv)
946{
947 i915.enable_execlists =
948 intel_sanitize_enable_execlists(dev_priv,
949 i915.enable_execlists);
950
951 /*
952 * i915.enable_ppgtt is read-only, so do an early pass to validate the
953 * user's requested state against the hardware/driver capabilities. We
954 * do this now so that we can print out any log messages once rather
955 * than every time we check intel_enable_ppgtt().
956 */
957 i915.enable_ppgtt =
958 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
959 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
39df9190
CW		 960
961 i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
962 DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
94b4f3ba
CW		 963}
964
0673ad47
CW		 965/**
966 * i915_driver_init_hw - setup state requiring device access
967 * @dev_priv: device private
968 *
969 * Setup state that requires accessing the device, but doesn't require
970 * exposing the driver via kernel internal or userspace interfaces.
971 */
972static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
973{
52a05c30 974 struct pci_dev *pdev = dev_priv->drm.pdev;
91c8a326 975 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 976 int ret;
977
978 if (i915_inject_load_failure())
979 return -ENODEV;
980
94b4f3ba
CW		 981 intel_device_info_runtime_init(dev_priv);
982
983 intel_sanitize_options(dev_priv);
0673ad47 984
97d6d7ab 985 ret = i915_ggtt_probe_hw(dev_priv);
0673ad47
CW		 986 if (ret)
987 return ret;
988
0673ad47
CW		 989 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
990 * otherwise the vga fbdev driver falls over. */
991 ret = i915_kick_out_firmware_fb(dev_priv);
992 if (ret) {
993 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
994 goto out_ggtt;
995 }
996
997 ret = i915_kick_out_vgacon(dev_priv);
998 if (ret) {
999 DRM_ERROR("failed to remove conflicting VGA console\n");
1000 goto out_ggtt;
1001 }
1002
97d6d7ab 1003 ret = i915_ggtt_init_hw(dev_priv);
0088e522
CW		 1004 if (ret)
1005 return ret;
1006
97d6d7ab 1007 ret = i915_ggtt_enable_hw(dev_priv);
0088e522
CW		 1008 if (ret) {
1009 DRM_ERROR("failed to enable GGTT\n");
1010 goto out_ggtt;
1011 }
1012
52a05c30 1013 pci_set_master(pdev);
0673ad47
CW		 1014
1015 /* overlay on gen2 is broken and can't address above 1G */
1016 if (IS_GEN2(dev)) {
52a05c30 1017 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
0673ad47
CW		 1018 if (ret) {
1019 DRM_ERROR("failed to set DMA mask\n");
1020
1021 goto out_ggtt;
1022 }
1023 }
1024
0673ad47
CW		 1025 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1026 * using 32bit addressing, overwriting memory if HWS is located
1027 * above 4GB.
1028 *
1029 * The documentation also mentions an issue with undefined
1030 * behaviour if any general state is accessed within a page above 4GB,
1031 * which also needs to be handled carefully.
1032 */
1033 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
52a05c30 1034 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0673ad47
CW		 1035
1036 if (ret) {
1037 DRM_ERROR("failed to set DMA mask\n");
1038
1039 goto out_ggtt;
1040 }
1041 }
1042
0673ad47
CW		 1043 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1044 PM_QOS_DEFAULT_VALUE);
1045
1046 intel_uncore_sanitize(dev_priv);
1047
1048 intel_opregion_setup(dev_priv);
1049
1050 i915_gem_load_init_fences(dev_priv);
1051
1052 /* On the 945G/GM, the chipset reports the MSI capability on the
1053 * integrated graphics even though the support isn't actually there
1054 * according to the published specs. It doesn't appear to function
1055 * correctly in testing on 945G.
1056 * This may be a side effect of MSI having been made available for PEG
1057 * and the registers being closely associated.
1058 *
1059 * According to chipset errata, on the 965GM, MSI interrupts may
1060 * be lost or delayed, but we use them anyways to avoid
1061 * stuck interrupts on some machines.
1062 */
50a0bc90 1063 if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
52a05c30 1064 if (pci_enable_msi(pdev) < 0)
0673ad47
CW		 1065 DRM_DEBUG_DRIVER("can't enable MSI");
1066 }
1067
1068 return 0;
1069
1070out_ggtt:
97d6d7ab 1071 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1072
1073 return ret;
1074}
1075
1076/**
1077 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1078 * @dev_priv: device private
1079 */
1080static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1081{
52a05c30 1082 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 1083
52a05c30
DW		 1084 if (pdev->msi_enabled)
1085 pci_disable_msi(pdev);
0673ad47
CW		 1086
1087 pm_qos_remove_request(&dev_priv->pm_qos);
97d6d7ab 1088 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1089}
1090
1091/**
1092 * i915_driver_register - register the driver with the rest of the system
1093 * @dev_priv: device private
1094 *
1095 * Perform any steps necessary to make the driver available via kernel
1096 * internal or userspace interfaces.
1097 */
1098static void i915_driver_register(struct drm_i915_private *dev_priv)
1099{
91c8a326 1100 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1101
1102 i915_gem_shrinker_init(dev_priv);
1103
1104 /*
1105 * Notify a valid surface after modesetting,
1106 * when running inside a VM.
1107 */
1108 if (intel_vgpu_active(dev_priv))
1109 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1110
1111 /* Reveal our presence to userspace */
1112 if (drm_dev_register(dev, 0) == 0) {
1113 i915_debugfs_register(dev_priv);
694c2828 1114 i915_setup_sysfs(dev_priv);
0673ad47
CW		 1115 } else
1116 DRM_ERROR("Failed to register driver for userspace access!\n");
1117
1118 if (INTEL_INFO(dev_priv)->num_pipes) {
1119 /* Must be done after probing outputs */
1120 intel_opregion_register(dev_priv);
1121 acpi_video_register();
1122 }
1123
1124 if (IS_GEN5(dev_priv))
1125 intel_gpu_ips_init(dev_priv);
1126
1127 i915_audio_component_init(dev_priv);
1128
1129 /*
1130 * Some ports require correctly set-up hpd registers for detection to
1131 * work properly (leading to ghost connected connector status), e.g. VGA
1132 * on gm45. Hence we can only set up the initial fbdev config after hpd
1133 * irqs are fully enabled. We do it last so that the async config
1134 * cannot run before the connectors are registered.
1135 */
1136 intel_fbdev_initial_config_async(dev);
1137}
1138
1139/**
1140 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1141 * @dev_priv: device private
1142 */
1143static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1144{
1145 i915_audio_component_cleanup(dev_priv);
1146
1147 intel_gpu_ips_teardown();
1148 acpi_video_unregister();
1149 intel_opregion_unregister(dev_priv);
1150
694c2828 1151 i915_teardown_sysfs(dev_priv);
0673ad47 1152 i915_debugfs_unregister(dev_priv);
91c8a326 1153 drm_dev_unregister(&dev_priv->drm);
0673ad47
CW		 1154
1155 i915_gem_shrinker_cleanup(dev_priv);
1156}
1157
1158/**
1159 * i915_driver_load - setup chip and create an initial config
1160 * @dev: DRM device
1161 * @flags: startup flags
1162 *
1163 * The driver load routine has to do several things:
1164 * - drive output discovery via intel_modeset_init()
1165 * - initialize the memory manager
1166 * - allocate initial config memory
1167 * - setup the DRM framebuffer with the allocated memory
1168 */
42f5551d 1169int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47
CW		 1170{
1171 struct drm_i915_private *dev_priv;
1172 int ret;
7d87a7f7 1173
a09d0ba1
CW		 1174 if (i915.nuclear_pageflip)
1175 driver.driver_features |= DRIVER_ATOMIC;
1176
0673ad47
CW		 1177 ret = -ENOMEM;
1178 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1179 if (dev_priv)
1180 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1181 if (ret) {
1182 dev_printk(KERN_ERR, &pdev->dev,
1183 "[" DRM_NAME ":%s] allocation failed\n", __func__);
1184 kfree(dev_priv);
1185 return ret;
1186 }
72bbf0af 1187
0673ad47
CW		 1188 dev_priv->drm.pdev = pdev;
1189 dev_priv->drm.dev_private = dev_priv;
719388e1 1190
0673ad47
CW		 1191 ret = pci_enable_device(pdev);
1192 if (ret)
1193 goto out_free_priv;
1347f5b4 1194
0673ad47 1195 pci_set_drvdata(pdev, &dev_priv->drm);
ef11bdb3 1196
0673ad47
CW		 1197 ret = i915_driver_init_early(dev_priv, ent);
1198 if (ret < 0)
1199 goto out_pci_disable;
ef11bdb3 1200
0673ad47 1201 intel_runtime_pm_get(dev_priv);
1da177e4 1202
0673ad47
CW		 1203 ret = i915_driver_init_mmio(dev_priv);
1204 if (ret < 0)
1205 goto out_runtime_pm_put;
79e53945 1206
0673ad47
CW		 1207 ret = i915_driver_init_hw(dev_priv);
1208 if (ret < 0)
1209 goto out_cleanup_mmio;
30c964a6
RB		 1210
1211 /*
0673ad47
CW		 1212 * TODO: move the vblank init and parts of modeset init steps into one
1213 * of the i915_driver_init_/i915_driver_register functions according
1214 * to the role/effect of the given init step.
30c964a6 1215 */
0673ad47 1216 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1217 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1218 INTEL_INFO(dev_priv)->num_pipes);
1219 if (ret)
1220 goto out_cleanup_hw;
30c964a6
RB		 1221 }
1222
91c8a326 1223 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47
CW		 1224 if (ret < 0)
1225 goto out_cleanup_vblank;
1226
1227 i915_driver_register(dev_priv);
1228
1229 intel_runtime_pm_enable(dev_priv);
1230
bc5ca47c
CW		 1231 /* Everything is in place, we can now relax! */
1232 DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1233 driver.name, driver.major, driver.minor, driver.patchlevel,
1234 driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1235
0673ad47
CW		 1236 intel_runtime_pm_put(dev_priv);
1237
1238 return 0;
1239
1240out_cleanup_vblank:
91c8a326 1241 drm_vblank_cleanup(&dev_priv->drm);
0673ad47
CW		 1242out_cleanup_hw:
1243 i915_driver_cleanup_hw(dev_priv);
1244out_cleanup_mmio:
1245 i915_driver_cleanup_mmio(dev_priv);
1246out_runtime_pm_put:
1247 intel_runtime_pm_put(dev_priv);
1248 i915_driver_cleanup_early(dev_priv);
1249out_pci_disable:
1250 pci_disable_device(pdev);
1251out_free_priv:
1252 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1253 drm_dev_unref(&dev_priv->drm);
30c964a6
RB		 1254 return ret;
1255}
1256
42f5551d 1257void i915_driver_unload(struct drm_device *dev)
3bad0781 1258{
fac5e23e 1259 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1260 struct pci_dev *pdev = dev_priv->drm.pdev;
3bad0781 1261
0673ad47
CW		 1262 intel_fbdev_fini(dev);
1263
42f5551d
CW		 1264 if (i915_gem_suspend(dev))
1265 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1266
0673ad47
CW		 1267 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1268
1269 i915_driver_unregister(dev_priv);
1270
1271 drm_vblank_cleanup(dev);
1272
1273 intel_modeset_cleanup(dev);
1274
3bad0781 1275 /*
0673ad47
CW		 1276 * free the memory space allocated for the child device
1277 * config parsed from VBT
3bad0781 1278 */
0673ad47
CW		 1279 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1280 kfree(dev_priv->vbt.child_dev);
1281 dev_priv->vbt.child_dev = NULL;
1282 dev_priv->vbt.child_dev_num = 0;
1283 }
1284 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1285 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1286 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1287 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1288
52a05c30
DW		 1289 vga_switcheroo_unregister_client(pdev);
1290 vga_client_register(pdev, NULL, NULL, NULL);
bcdb72ac 1291
0673ad47 1292 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1293
0673ad47
CW		 1294 /* Free error state after interrupts are fully disabled. */
1295 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1296 i915_destroy_error_state(dev);
1297
1298 /* Flush any outstanding unpin_work. */
b7137e0c 1299 drain_workqueue(dev_priv->wq);
0673ad47
CW		 1300
1301 intel_guc_fini(dev);
1302 i915_gem_fini(dev);
1303 intel_fbc_cleanup_cfb(dev_priv);
1304
1305 intel_power_domains_fini(dev_priv);
1306
1307 i915_driver_cleanup_hw(dev_priv);
1308 i915_driver_cleanup_mmio(dev_priv);
1309
1310 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1311
1312 i915_driver_cleanup_early(dev_priv);
3bad0781
ZW		 1313}
1314
0673ad47 1315static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1316{
0673ad47 1317 int ret;
2911a35b 1318
0673ad47
CW		 1319 ret = i915_gem_open(dev, file);
1320 if (ret)
1321 return ret;
2911a35b 1322
0673ad47
CW		 1323 return 0;
1324}
71386ef9 1325
0673ad47
CW		 1326/**
1327 * i915_driver_lastclose - clean up after all DRM clients have exited
1328 * @dev: DRM device
1329 *
1330 * Take care of cleaning up after all DRM clients have exited. In the
1331 * mode setting case, we want to restore the kernel's initial mode (just
1332 * in case the last client left us in a bad state).
1333 *
1334 * Additionally, in the non-mode setting case, we'll tear down the GTT
1335 * and DMA structures, since the kernel won't be using them, and clea
1336 * up any GEM state.
1337 */
1338static void i915_driver_lastclose(struct drm_device *dev)
1339{
1340 intel_fbdev_restore_mode(dev);
1341 vga_switcheroo_process_delayed_switch();
1342}
2911a35b 1343
0673ad47
CW		 1344static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1345{
1346 mutex_lock(&dev->struct_mutex);
1347 i915_gem_context_close(dev, file);
1348 i915_gem_release(dev, file);
1349 mutex_unlock(&dev->struct_mutex);
1350}
1351
1352static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1353{
1354 struct drm_i915_file_private *file_priv = file->driver_priv;
1355
1356 kfree(file_priv);
2911a35b
BW		 1357}
1358
07f9cd0b
ID		 1359static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1360{
91c8a326 1361 struct drm_device *dev = &dev_priv->drm;
19c8054c 1362 struct intel_encoder *encoder;
07f9cd0b
ID		 1363
1364 drm_modeset_lock_all(dev);
19c8054c
JN		 1365 for_each_intel_encoder(dev, encoder)
1366 if (encoder->suspend)
1367 encoder->suspend(encoder);
07f9cd0b
ID		 1368 drm_modeset_unlock_all(dev);
1369}
1370
1a5df187
PZ		 1371static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1372 bool rpm_resume);
507e126e 1373static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1374
bc87229f
ID		 1375static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1376{
1377#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1378 if (acpi_target_system_state() < ACPI_STATE_S3)
1379 return true;
1380#endif
1381 return false;
1382}
ebc32824 1383
5e365c39 1384static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1385{
fac5e23e 1386 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1387 struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3a 1388 pci_power_t opregion_target_state;
d5818938 1389 int error;
61caf87c 1390
b8efb17b
ZR		 1391 /* ignore lid events during suspend */
1392 mutex_lock(&dev_priv->modeset_restore_lock);
1393 dev_priv->modeset_restore = MODESET_SUSPENDED;
1394 mutex_unlock(&dev_priv->modeset_restore_lock);
1395
1f814dac
ID		 1396 disable_rpm_wakeref_asserts(dev_priv);
1397
c67a470b
PZ		 1398 /* We do a lot of poking in a lot of registers, make sure they work
1399 * properly. */
da7e29bd 1400 intel_display_set_init_power(dev_priv, true);
cb10799c 1401
5bcf719b
DA		 1402 drm_kms_helper_poll_disable(dev);
1403
52a05c30 1404 pci_save_state(pdev);
ba8bbcf6 1405
d5818938
DV		 1406 error = i915_gem_suspend(dev);
1407 if (error) {
52a05c30 1408 dev_err(&pdev->dev,
d5818938 1409 "GEM idle failed, resume might fail\n");
1f814dac 1410 goto out;
d5818938 1411 }
db1b76ca 1412
a1c41994
AD		 1413 intel_guc_suspend(dev);
1414
6b72d486 1415 intel_display_suspend(dev);
2eb5252e 1416
d5818938 1417 intel_dp_mst_suspend(dev);
7d708ee4 1418
d5818938
DV		 1419 intel_runtime_pm_disable_interrupts(dev_priv);
1420 intel_hpd_cancel_work(dev_priv);
09b64267 1421
d5818938 1422 intel_suspend_encoders(dev_priv);
0e32b39c 1423
d5818938 1424 intel_suspend_hw(dev);
5669fcac 1425
828c7908
BW		 1426 i915_gem_suspend_gtt_mappings(dev);
1427
9e06dd39
JB		 1428 i915_save_state(dev);
1429
bc87229f 1430 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1431 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1432
dc97997a 1433 intel_uncore_forcewake_reset(dev_priv, false);
03d92e47 1434 intel_opregion_unregister(dev_priv);
8ee1c3db 1435
82e3b8c1 1436 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1437
62d5d69b
MK		 1438 dev_priv->suspend_count++;
1439
85e90679
KCA		 1440 intel_display_set_init_power(dev_priv, false);
1441
f74ed08d 1442 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1443
1f814dac
ID		 1444out:
1445 enable_rpm_wakeref_asserts(dev_priv);
1446
1447 return error;
84b79f8d
RW		 1448}
1449
c49d13ee 1450static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
c3c09c95 1451{
c49d13ee 1452 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1453 struct pci_dev *pdev = dev_priv->drm.pdev;
bc87229f 1454 bool fw_csr;
c3c09c95
ID		 1455 int ret;
1456
1f814dac
ID		 1457 disable_rpm_wakeref_asserts(dev_priv);
1458
a7c8125f
ID		 1459 fw_csr = !IS_BROXTON(dev_priv) &&
1460 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1461 /*
1462 * In case of firmware assisted context save/restore don't manually
1463 * deinit the power domains. This also means the CSR/DMC firmware will
1464 * stay active, it will power down any HW resources as required and
1465 * also enable deeper system power states that would be blocked if the
1466 * firmware was inactive.
1467 */
1468 if (!fw_csr)
1469 intel_power_domains_suspend(dev_priv);
73dfc227 1470
507e126e 1471 ret = 0;
b8aea3d1 1472 if (IS_BROXTON(dev_priv))
507e126e 1473 bxt_enable_dc9(dev_priv);
b8aea3d1 1474 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1475 hsw_enable_pc8(dev_priv);
1476 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1477 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1478
1479 if (ret) {
1480 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1481 if (!fw_csr)
1482 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1483
1f814dac 1484 goto out;
c3c09c95
ID		 1485 }
1486
52a05c30 1487 pci_disable_device(pdev);
ab3be73f 1488 /*
54875571 1489 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1490 * the device even though it's already in D3 and hang the machine. So
1491 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1492 * power down the device properly. The issue was seen on multiple old
1493 * GENs with different BIOS vendors, so having an explicit blacklist
1494 * is inpractical; apply the workaround on everything pre GEN6. The
1495 * platforms where the issue was seen:
1496 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1497 * Fujitsu FSC S7110
1498 * Acer Aspire 1830T
ab3be73f 1499 */
54875571 1500 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
52a05c30 1501 pci_set_power_state(pdev, PCI_D3hot);
c3c09c95 1502
bc87229f
ID		 1503 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1504
1f814dac
ID		 1505out:
1506 enable_rpm_wakeref_asserts(dev_priv);
1507
1508 return ret;
c3c09c95
ID		 1509}
1510
1751fcf9 1511int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1512{
1513 int error;
1514
ded8b07d 1515 if (!dev) {
84b79f8d
RW		 1516 DRM_ERROR("dev: %p\n", dev);
1517 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1518 return -ENODEV;
1519 }
1520
0b14cbd2
ID		 1521 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1522 state.event != PM_EVENT_FREEZE))
1523 return -EINVAL;
5bcf719b
DA		 1524
1525 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1526 return 0;
6eecba33 1527
5e365c39 1528 error = i915_drm_suspend(dev);
84b79f8d
RW		 1529 if (error)
1530 return error;
1531
ab3be73f 1532 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1533}
1534
5e365c39 1535static int i915_drm_resume(struct drm_device *dev)
76c4b250 1536{
fac5e23e 1537 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1538 int ret;
9d49c0ef 1539
1f814dac 1540 disable_rpm_wakeref_asserts(dev_priv);
abc80abd 1541 intel_sanitize_gt_powersave(dev_priv);
1f814dac 1542
97d6d7ab 1543 ret = i915_ggtt_enable_hw(dev_priv);
ac840ae5
VS		 1544 if (ret)
1545 DRM_ERROR("failed to re-enable GGTT\n");
1546
f74ed08d
ID		 1547 intel_csr_ucode_resume(dev_priv);
1548
5ab57c70 1549 i915_gem_resume(dev);
9d49c0ef 1550
61caf87c 1551 i915_restore_state(dev);
8090ba8c 1552 intel_pps_unlock_regs_wa(dev_priv);
6f9f4b7a 1553 intel_opregion_setup(dev_priv);
61caf87c 1554
d5818938
DV		 1555 intel_init_pch_refclk(dev);
1556 drm_mode_config_reset(dev);
1833b134 1557
364aece0
PA		 1558 /*
1559 * Interrupts have to be enabled before any batches are run. If not the
1560 * GPU will hang. i915_gem_init_hw() will initiate batches to
1561 * update/restore the context.
1562 *
1563 * Modeset enabling in intel_modeset_init_hw() also needs working
1564 * interrupts.
1565 */
1566 intel_runtime_pm_enable_interrupts(dev_priv);
1567
d5818938
DV		 1568 mutex_lock(&dev->struct_mutex);
1569 if (i915_gem_init_hw(dev)) {
1570 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
821ed7df 1571 i915_gem_set_wedged(dev_priv);
d5818938
DV		 1572 }
1573 mutex_unlock(&dev->struct_mutex);
226485e9 1574
a1c41994
AD		 1575 intel_guc_resume(dev);
1576
d5818938 1577 intel_modeset_init_hw(dev);
24576d23 1578
d5818938
DV		 1579 spin_lock_irq(&dev_priv->irq_lock);
1580 if (dev_priv->display.hpd_irq_setup)
91d14251 1581 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1582 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1583
d5818938 1584 intel_dp_mst_resume(dev);
e7d6f7d7 1585
a16b7658
L		 1586 intel_display_resume(dev);
1587
d5818938
DV		 1588 /*
1589 * ... but also need to make sure that hotplug processing
1590 * doesn't cause havoc. Like in the driver load code we don't
1591 * bother with the tiny race here where we might loose hotplug
1592 * notifications.
1593 * */
1594 intel_hpd_init(dev_priv);
1595 /* Config may have changed between suspend and resume */
1596 drm_helper_hpd_irq_event(dev);
1daed3fb 1597
03d92e47 1598 intel_opregion_register(dev_priv);
44834a67 1599
82e3b8c1 1600 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1601
b8efb17b
ZR		 1602 mutex_lock(&dev_priv->modeset_restore_lock);
1603 dev_priv->modeset_restore = MODESET_DONE;
1604 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1605
6f9f4b7a 1606 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1607
54b4f68f 1608 intel_autoenable_gt_powersave(dev_priv);
ee6f280e
ID		 1609 drm_kms_helper_poll_enable(dev);
1610
1f814dac
ID		 1611 enable_rpm_wakeref_asserts(dev_priv);
1612
074c6ada 1613 return 0;
84b79f8d
RW		 1614}
1615
5e365c39 1616static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1617{
fac5e23e 1618 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1619 struct pci_dev *pdev = dev_priv->drm.pdev;
44410cd0 1620 int ret;
36d61e67 1621
76c4b250
ID		 1622 /*
1623 * We have a resume ordering issue with the snd-hda driver also
1624 * requiring our device to be power up. Due to the lack of a
1625 * parent/child relationship we currently solve this with an early
1626 * resume hook.
1627 *
1628 * FIXME: This should be solved with a special hdmi sink device or
1629 * similar so that power domains can be employed.
1630 */
44410cd0
ID		 1631
1632 /*
1633 * Note that we need to set the power state explicitly, since we
1634 * powered off the device during freeze and the PCI core won't power
1635 * it back up for us during thaw. Powering off the device during
1636 * freeze is not a hard requirement though, and during the
1637 * suspend/resume phases the PCI core makes sure we get here with the
1638 * device powered on. So in case we change our freeze logic and keep
1639 * the device powered we can also remove the following set power state
1640 * call.
1641 */
52a05c30 1642 ret = pci_set_power_state(pdev, PCI_D0);
44410cd0
ID		 1643 if (ret) {
1644 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1645 goto out;
1646 }
1647
1648 /*
1649 * Note that pci_enable_device() first enables any parent bridge
1650 * device and only then sets the power state for this device. The
1651 * bridge enabling is a nop though, since bridge devices are resumed
1652 * first. The order of enabling power and enabling the device is
1653 * imposed by the PCI core as described above, so here we preserve the
1654 * same order for the freeze/thaw phases.
1655 *
1656 * TODO: eventually we should remove pci_disable_device() /
1657 * pci_enable_enable_device() from suspend/resume. Due to how they
1658 * depend on the device enable refcount we can't anyway depend on them
1659 * disabling/enabling the device.
1660 */
52a05c30 1661 if (pci_enable_device(pdev)) {
bc87229f
ID		 1662 ret = -EIO;
1663 goto out;
1664 }
84b79f8d 1665
52a05c30 1666 pci_set_master(pdev);
84b79f8d 1667
1f814dac
ID		 1668 disable_rpm_wakeref_asserts(dev_priv);
1669
666a4537 1670 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1671 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1672 if (ret)
ff0b187f
DL		 1673 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1674 ret);
36d61e67 1675
dc97997a 1676 intel_uncore_early_sanitize(dev_priv, true);
efee833a 1677
dc97997a 1678 if (IS_BROXTON(dev_priv)) {
da2f41d1
ID		 1679 if (!dev_priv->suspended_to_idle)
1680 gen9_sanitize_dc_state(dev_priv);
507e126e 1681 bxt_disable_dc9(dev_priv);
da2f41d1 1682 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1683 hsw_disable_pc8(dev_priv);
da2f41d1 1684 }
efee833a 1685
dc97997a 1686 intel_uncore_sanitize(dev_priv);
bc87229f 1687
a7c8125f
ID		 1688 if (IS_BROXTON(dev_priv) ||
1689 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 1690 intel_power_domains_init_hw(dev_priv, true);
1691
6e35e8ab
ID		 1692 enable_rpm_wakeref_asserts(dev_priv);
1693
bc87229f
ID		 1694out:
1695 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1696
1697 return ret;
76c4b250
ID		 1698}
1699
1751fcf9 1700int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1701{
50a0072f 1702 int ret;
76c4b250 1703
097dd837
ID		 1704 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1705 return 0;
1706
5e365c39 1707 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1708 if (ret)
1709 return ret;
1710
5a17514e
ID		 1711 return i915_drm_resume(dev);
1712}
1713
9e60ab03
CW		 1714static void disable_engines_irq(struct drm_i915_private *dev_priv)
1715{
1716 struct intel_engine_cs *engine;
3b3f1650 1717 enum intel_engine_id id;
9e60ab03
CW		 1718
1719 /* Ensure irq handler finishes, and not run again. */
1720 disable_irq(dev_priv->drm.irq);
3b3f1650 1721 for_each_engine(engine, dev_priv, id)
9e60ab03
CW		 1722 tasklet_kill(&engine->irq_tasklet);
1723}
1724
1725static void enable_engines_irq(struct drm_i915_private *dev_priv)
1726{
1727 enable_irq(dev_priv->drm.irq);
1728}
1729
11ed50ec 1730/**
f3953dcb 1731 * i915_reset - reset chip after a hang
11ed50ec 1732 * @dev: drm device to reset
11ed50ec 1733 *
780f262a
CW		 1734 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1735 * on failure.
11ed50ec 1736 *
221fe799
CW		 1737 * Caller must hold the struct_mutex.
1738 *
11ed50ec
BG		 1739 * Procedure is fairly simple:
1740 * - reset the chip using the reset reg
1741 * - re-init context state
1742 * - re-init hardware status page
1743 * - re-init ring buffer
1744 * - re-init interrupt state
1745 * - re-init display
1746 */
780f262a 1747void i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 1748{
91c8a326 1749 struct drm_device *dev = &dev_priv->drm;
d98c52cf 1750 struct i915_gpu_error *error = &dev_priv->gpu_error;
0573ed4a 1751 int ret;
11ed50ec 1752
221fe799
CW		 1753 lockdep_assert_held(&dev->struct_mutex);
1754
1755 if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
780f262a 1756 return;
11ed50ec 1757
d98c52cf 1758 /* Clear any previous failed attempts at recovery. Time to try again. */
8af29b0c
CW		 1759 __clear_bit(I915_WEDGED, &error->flags);
1760 error->reset_count++;
d98c52cf 1761
7b4d3a16 1762 pr_notice("drm/i915: Resetting chip after gpu hang\n");
9e60ab03
CW		 1763
1764 disable_engines_irq(dev_priv);
dc97997a 1765 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
9e60ab03
CW		 1766 enable_engines_irq(dev_priv);
1767
0573ed4a 1768 if (ret) {
804e59a8
CW		 1769 if (ret != -ENODEV)
1770 DRM_ERROR("Failed to reset chip: %i\n", ret);
1771 else
1772 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 1773 goto error;
11ed50ec
BG		 1774 }
1775
821ed7df 1776 i915_gem_reset(dev_priv);
1362b776
VS		 1777 intel_overlay_reset(dev_priv);
1778
11ed50ec
BG		 1779 /* Ok, now get things going again... */
1780
1781 /*
1782 * Everything depends on having the GTT running, so we need to start
1783 * there. Fortunately we don't need to do this unless we reset the
1784 * chip at a PCI level.
1785 *
1786 * Next we need to restore the context, but we don't use those
1787 * yet either...
1788 *
1789 * Ring buffer needs to be re-initialized in the KMS case, or if X
1790 * was running at the time of the reset (i.e. we weren't VT
1791 * switched away).
1792 */
33d30a9c 1793 ret = i915_gem_init_hw(dev);
33d30a9c
DV		 1794 if (ret) {
1795 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1796 goto error;
11ed50ec
BG		 1797 }
1798
780f262a
CW		 1799wakeup:
1800 wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1801 return;
d98c52cf
CW		 1802
1803error:
821ed7df 1804 i915_gem_set_wedged(dev_priv);
780f262a 1805 goto wakeup;
11ed50ec
BG		 1806}
1807
c49d13ee 1808static int i915_pm_suspend(struct device *kdev)
112b715e 1809{
c49d13ee
DW		 1810 struct pci_dev *pdev = to_pci_dev(kdev);
1811 struct drm_device *dev = pci_get_drvdata(pdev);
112b715e 1812
c49d13ee
DW		 1813 if (!dev) {
1814 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
84b79f8d
RW		 1815 return -ENODEV;
1816 }
112b715e 1817
c49d13ee 1818 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
5bcf719b
DA		 1819 return 0;
1820
c49d13ee 1821 return i915_drm_suspend(dev);
76c4b250
ID		 1822}
1823
c49d13ee 1824static int i915_pm_suspend_late(struct device *kdev)
76c4b250 1825{
c49d13ee 1826 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250
ID		 1827
1828 /*
c965d995 1829 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 1830 * requiring our device to be power up. Due to the lack of a
1831 * parent/child relationship we currently solve this with an late
1832 * suspend hook.
1833 *
1834 * FIXME: This should be solved with a special hdmi sink device or
1835 * similar so that power domains can be employed.
1836 */
c49d13ee 1837 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
76c4b250 1838 return 0;
112b715e 1839
c49d13ee 1840 return i915_drm_suspend_late(dev, false);
ab3be73f
ID		 1841}
1842
c49d13ee 1843static int i915_pm_poweroff_late(struct device *kdev)
ab3be73f 1844{
c49d13ee 1845 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
ab3be73f 1846
c49d13ee 1847 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
ab3be73f
ID		 1848 return 0;
1849
c49d13ee 1850 return i915_drm_suspend_late(dev, true);
cbda12d7
ZW		 1851}
1852
c49d13ee 1853static int i915_pm_resume_early(struct device *kdev)
76c4b250 1854{
c49d13ee 1855 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250 1856
c49d13ee 1857 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1858 return 0;
1859
c49d13ee 1860 return i915_drm_resume_early(dev);
76c4b250
ID		 1861}
1862
c49d13ee 1863static int i915_pm_resume(struct device *kdev)
cbda12d7 1864{
c49d13ee 1865 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
84b79f8d 1866
c49d13ee 1867 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1868 return 0;
1869
c49d13ee 1870 return i915_drm_resume(dev);
cbda12d7
ZW		 1871}
1872
1f19ac2a 1873/* freeze: before creating the hibernation_image */
c49d13ee 1874static int i915_pm_freeze(struct device *kdev)
1f19ac2a 1875{
6a800eab
CW		 1876 int ret;
1877
1878 ret = i915_pm_suspend(kdev);
1879 if (ret)
1880 return ret;
1881
1882 ret = i915_gem_freeze(kdev_to_i915(kdev));
1883 if (ret)
1884 return ret;
1885
1886 return 0;
1f19ac2a
CW		 1887}
1888
c49d13ee 1889static int i915_pm_freeze_late(struct device *kdev)
1f19ac2a 1890{
461fb99c
CW		 1891 int ret;
1892
c49d13ee 1893 ret = i915_pm_suspend_late(kdev);
461fb99c
CW		 1894 if (ret)
1895 return ret;
1896
c49d13ee 1897 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
461fb99c
CW		 1898 if (ret)
1899 return ret;
1900
1901 return 0;
1f19ac2a
CW		 1902}
1903
1904/* thaw: called after creating the hibernation image, but before turning off. */
c49d13ee 1905static int i915_pm_thaw_early(struct device *kdev)
1f19ac2a 1906{
c49d13ee 1907 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1908}
1909
c49d13ee 1910static int i915_pm_thaw(struct device *kdev)
1f19ac2a 1911{
c49d13ee 1912 return i915_pm_resume(kdev);
1f19ac2a
CW		 1913}
1914
1915/* restore: called after loading the hibernation image. */
c49d13ee 1916static int i915_pm_restore_early(struct device *kdev)
1f19ac2a 1917{
c49d13ee 1918 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1919}
1920
c49d13ee 1921static int i915_pm_restore(struct device *kdev)
1f19ac2a 1922{
c49d13ee 1923 return i915_pm_resume(kdev);
1f19ac2a
CW		 1924}
1925
ddeea5b0
ID		 1926/*
1927 * Save all Gunit registers that may be lost after a D3 and a subsequent
1928 * S0i[R123] transition. The list of registers needing a save/restore is
1929 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1930 * registers in the following way:
1931 * - Driver: saved/restored by the driver
1932 * - Punit : saved/restored by the Punit firmware
1933 * - No, w/o marking: no need to save/restore, since the register is R/O or
1934 * used internally by the HW in a way that doesn't depend
1935 * keeping the content across a suspend/resume.
1936 * - Debug : used for debugging
1937 *
1938 * We save/restore all registers marked with 'Driver', with the following
1939 * exceptions:
1940 * - Registers out of use, including also registers marked with 'Debug'.
1941 * These have no effect on the driver's operation, so we don't save/restore
1942 * them to reduce the overhead.
1943 * - Registers that are fully setup by an initialization function called from
1944 * the resume path. For example many clock gating and RPS/RC6 registers.
1945 * - Registers that provide the right functionality with their reset defaults.
1946 *
1947 * TODO: Except for registers that based on the above 3 criteria can be safely
1948 * ignored, we save/restore all others, practically treating the HW context as
1949 * a black-box for the driver. Further investigation is needed to reduce the
1950 * saved/restored registers even further, by following the same 3 criteria.
1951 */
1952static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1953{
1954 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1955 int i;
1956
1957 /* GAM 0x4000-0x4770 */
1958 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1959 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1960 s->arb_mode = I915_READ(ARB_MODE);
1961 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1962 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1963
1964 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 1965 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 1966
1967 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 1968 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 1969
1970 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1971 s->ecochk = I915_READ(GAM_ECOCHK);
1972 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1973 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1974
1975 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1976
1977 /* MBC 0x9024-0x91D0, 0x8500 */
1978 s->g3dctl = I915_READ(VLV_G3DCTL);
1979 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1980 s->mbctl = I915_READ(GEN6_MBCTL);
1981
1982 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1983 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1984 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1985 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1986 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1987 s->rstctl = I915_READ(GEN6_RSTCTL);
1988 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1989
1990 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1991 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1992 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1993 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1994 s->ecobus = I915_READ(ECOBUS);
1995 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1996 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1997 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1998 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1999 s->rcedata = I915_READ(VLV_RCEDATA);
2000 s->spare2gh = I915_READ(VLV_SPAREG2H);
2001
2002 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2003 s->gt_imr = I915_READ(GTIMR);
2004 s->gt_ier = I915_READ(GTIER);
2005 s->pm_imr = I915_READ(GEN6_PMIMR);
2006 s->pm_ier = I915_READ(GEN6_PMIER);
2007
2008 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2009 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2010
2011 /* GT SA CZ domain, 0x100000-0x138124 */
2012 s->tilectl = I915_READ(TILECTL);
2013 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2014 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2015 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2016 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2017
2018 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2019 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2020 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2021 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2022 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2023
2024 /*
2025 * Not saving any of:
2026 * DFT, 0x9800-0x9EC0
2027 * SARB, 0xB000-0xB1FC
2028 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2029 * PCI CFG
2030 */
2031}
2032
2033static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2034{
2035 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2036 u32 val;
2037 int i;
2038
2039 /* GAM 0x4000-0x4770 */
2040 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2041 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2042 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2043 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2044 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2045
2046 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2047 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2048
2049 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2050 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2051
2052 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2053 I915_WRITE(GAM_ECOCHK, s->ecochk);
2054 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2055 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2056
2057 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2058
2059 /* MBC 0x9024-0x91D0, 0x8500 */
2060 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2061 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2062 I915_WRITE(GEN6_MBCTL, s->mbctl);
2063
2064 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2065 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2066 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2067 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2068 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2069 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2070 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2071
2072 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2073 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2074 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2075 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2076 I915_WRITE(ECOBUS, s->ecobus);
2077 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2078 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2079 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2080 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2081 I915_WRITE(VLV_RCEDATA, s->rcedata);
2082 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2083
2084 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2085 I915_WRITE(GTIMR, s->gt_imr);
2086 I915_WRITE(GTIER, s->gt_ier);
2087 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2088 I915_WRITE(GEN6_PMIER, s->pm_ier);
2089
2090 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2091 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2092
2093 /* GT SA CZ domain, 0x100000-0x138124 */
2094 I915_WRITE(TILECTL, s->tilectl);
2095 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2096 /*
2097 * Preserve the GT allow wake and GFX force clock bit, they are not
2098 * be restored, as they are used to control the s0ix suspend/resume
2099 * sequence by the caller.
2100 */
2101 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2102 val &= VLV_GTLC_ALLOWWAKEREQ;
2103 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2104 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2105
2106 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2107 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2108 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2109 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2110
2111 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2112
2113 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2114 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2115 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2116 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2117 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2118}
2119
650ad970
ID		 2120int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2121{
2122 u32 val;
2123 int err;
2124
650ad970
ID		 2125 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2126 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2127 if (force_on)
2128 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2129 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2130
2131 if (!force_on)
2132 return 0;
2133
c6ddc5f3
CW		 2134 err = intel_wait_for_register(dev_priv,
2135 VLV_GTLC_SURVIVABILITY_REG,
2136 VLV_GFX_CLK_STATUS_BIT,
2137 VLV_GFX_CLK_STATUS_BIT,
2138 20);
650ad970
ID		 2139 if (err)
2140 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2141 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2142
2143 return err;
650ad970
ID		 2144}
2145
ddeea5b0
ID		 2146static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2147{
2148 u32 val;
2149 int err = 0;
2150
2151 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2152 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2153 if (allow)
2154 val |= VLV_GTLC_ALLOWWAKEREQ;
2155 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2156 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2157
b2736695
CW		 2158 err = intel_wait_for_register(dev_priv,
2159 VLV_GTLC_PW_STATUS,
2160 VLV_GTLC_ALLOWWAKEACK,
2161 allow,
2162 1);
ddeea5b0
ID		 2163 if (err)
2164 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2165
ddeea5b0 2166 return err;
ddeea5b0
ID		 2167}
2168
2169static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2170 bool wait_for_on)
2171{
2172 u32 mask;
2173 u32 val;
2174 int err;
2175
2176 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2177 val = wait_for_on ? mask : 0;
41ce405e 2178 if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
ddeea5b0
ID		 2179 return 0;
2180
2181 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
87ad3212
JN		 2182 onoff(wait_for_on),
2183 I915_READ(VLV_GTLC_PW_STATUS));
ddeea5b0
ID		 2184
2185 /*
2186 * RC6 transitioning can be delayed up to 2 msec (see
2187 * valleyview_enable_rps), use 3 msec for safety.
2188 */
41ce405e
CW		 2189 err = intel_wait_for_register(dev_priv,
2190 VLV_GTLC_PW_STATUS, mask, val,
2191 3);
ddeea5b0
ID		 2192 if (err)
2193 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2194 onoff(wait_for_on));
ddeea5b0
ID		 2195
2196 return err;
ddeea5b0
ID		 2197}
2198
2199static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2200{
2201 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2202 return;
2203
6fa283b0 2204 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2205 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2206}
2207
ebc32824 2208static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2209{
2210 u32 mask;
2211 int err;
2212
2213 /*
2214 * Bspec defines the following GT well on flags as debug only, so
2215 * don't treat them as hard failures.
2216 */
2217 (void)vlv_wait_for_gt_wells(dev_priv, false);
2218
2219 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2220 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2221
2222 vlv_check_no_gt_access(dev_priv);
2223
2224 err = vlv_force_gfx_clock(dev_priv, true);
2225 if (err)
2226 goto err1;
2227
2228 err = vlv_allow_gt_wake(dev_priv, false);
2229 if (err)
2230 goto err2;
98711167 2231
2d1fe073 2232 if (!IS_CHERRYVIEW(dev_priv))
98711167 2233 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2234
2235 err = vlv_force_gfx_clock(dev_priv, false);
2236 if (err)
2237 goto err2;
2238
2239 return 0;
2240
2241err2:
2242 /* For safety always re-enable waking and disable gfx clock forcing */
2243 vlv_allow_gt_wake(dev_priv, true);
2244err1:
2245 vlv_force_gfx_clock(dev_priv, false);
2246
2247 return err;
2248}
2249
016970be
SK		 2250static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2251 bool rpm_resume)
ddeea5b0 2252{
91c8a326 2253 struct drm_device *dev = &dev_priv->drm;
ddeea5b0
ID		 2254 int err;
2255 int ret;
2256
2257 /*
2258 * If any of the steps fail just try to continue, that's the best we
2259 * can do at this point. Return the first error code (which will also
2260 * leave RPM permanently disabled).
2261 */
2262 ret = vlv_force_gfx_clock(dev_priv, true);
2263
2d1fe073 2264 if (!IS_CHERRYVIEW(dev_priv))
98711167 2265 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2266
2267 err = vlv_allow_gt_wake(dev_priv, true);
2268 if (!ret)
2269 ret = err;
2270
2271 err = vlv_force_gfx_clock(dev_priv, false);
2272 if (!ret)
2273 ret = err;
2274
2275 vlv_check_no_gt_access(dev_priv);
2276
016970be
SK		 2277 if (rpm_resume) {
2278 intel_init_clock_gating(dev);
2279 i915_gem_restore_fences(dev);
2280 }
ddeea5b0
ID		 2281
2282 return ret;
2283}
2284
c49d13ee 2285static int intel_runtime_suspend(struct device *kdev)
8a187455 2286{
c49d13ee 2287 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2288 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2289 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2290 int ret;
8a187455 2291
dc97997a 2292 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2293 return -ENODEV;
2294
6772ffe0 2295 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7
ID		 2296 return -ENODEV;
2297
8a187455
PZ		 2298 DRM_DEBUG_KMS("Suspending device\n");
2299
d6102977
ID		 2300 /*
2301 * We could deadlock here in case another thread holding struct_mutex
2302 * calls RPM suspend concurrently, since the RPM suspend will wait
2303 * first for this RPM suspend to finish. In this case the concurrent
2304 * RPM resume will be followed by its RPM suspend counterpart. Still
2305 * for consistency return -EAGAIN, which will reschedule this suspend.
2306 */
2307 if (!mutex_trylock(&dev->struct_mutex)) {
2308 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2309 /*
2310 * Bump the expiration timestamp, otherwise the suspend won't
2311 * be rescheduled.
2312 */
c49d13ee 2313 pm_runtime_mark_last_busy(kdev);
d6102977
ID		 2314
2315 return -EAGAIN;
2316 }
1f814dac
ID		 2317
2318 disable_rpm_wakeref_asserts(dev_priv);
2319
d6102977
ID		 2320 /*
2321 * We are safe here against re-faults, since the fault handler takes
2322 * an RPM reference.
2323 */
2324 i915_gem_release_all_mmaps(dev_priv);
2325 mutex_unlock(&dev->struct_mutex);
2326
a1c41994
AD		 2327 intel_guc_suspend(dev);
2328
2eb5252e 2329 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2330
507e126e
ID		 2331 ret = 0;
2332 if (IS_BROXTON(dev_priv)) {
2333 bxt_display_core_uninit(dev_priv);
2334 bxt_enable_dc9(dev_priv);
2335 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2336 hsw_enable_pc8(dev_priv);
2337 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2338 ret = vlv_suspend_complete(dev_priv);
2339 }
2340
0ab9cfeb
ID		 2341 if (ret) {
2342 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2343 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2344
1f814dac
ID		 2345 enable_rpm_wakeref_asserts(dev_priv);
2346
0ab9cfeb
ID		 2347 return ret;
2348 }
a8a8bd54 2349
dc97997a 2350 intel_uncore_forcewake_reset(dev_priv, false);
1f814dac
ID		 2351
2352 enable_rpm_wakeref_asserts(dev_priv);
2353 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2354
bc3b9346 2355 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2356 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2357
8a187455 2358 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2359
2360 /*
c8a0bd42
PZ		 2361 * FIXME: We really should find a document that references the arguments
2362 * used below!
1fb2362b 2363 */
6f9f4b7a 2364 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2365 /*
2366 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2367 * being detected, and the call we do at intel_runtime_resume()
2368 * won't be able to restore them. Since PCI_D3hot matches the
2369 * actual specification and appears to be working, use it.
2370 */
6f9f4b7a 2371 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2372 } else {
c8a0bd42
PZ		 2373 /*
2374 * current versions of firmware which depend on this opregion
2375 * notification have repurposed the D1 definition to mean
2376 * "runtime suspended" vs. what you would normally expect (D3)
2377 * to distinguish it from notifications that might be sent via
2378 * the suspend path.
2379 */
6f9f4b7a 2380 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2381 }
8a187455 2382
59bad947 2383 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2384
19625e85
L		 2385 if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2386 intel_hpd_poll_init(dev_priv);
2387
a8a8bd54 2388 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2389 return 0;
2390}
2391
c49d13ee 2392static int intel_runtime_resume(struct device *kdev)
8a187455 2393{
c49d13ee 2394 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2395 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2396 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2397 int ret = 0;
8a187455 2398
6772ffe0 2399 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7 2400 return -ENODEV;
8a187455
PZ		 2401
2402 DRM_DEBUG_KMS("Resuming device\n");
2403
1f814dac
ID		 2404 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2405 disable_rpm_wakeref_asserts(dev_priv);
2406
6f9f4b7a 2407 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2408 dev_priv->pm.suspended = false;
55ec45c2
MK		 2409 if (intel_uncore_unclaimed_mmio(dev_priv))
2410 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2411
a1c41994
AD		 2412 intel_guc_resume(dev);
2413
1a5df187
PZ		 2414 if (IS_GEN6(dev_priv))
2415 intel_init_pch_refclk(dev);
31335cec 2416
e2d214ae 2417 if (IS_BROXTON(dev_priv)) {
507e126e
ID		 2418 bxt_disable_dc9(dev_priv);
2419 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2420 if (dev_priv->csr.dmc_payload &&
2421 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2422 gen9_enable_dc5(dev_priv);
507e126e 2423 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2424 hsw_disable_pc8(dev_priv);
507e126e 2425 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2426 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2427 }
1a5df187 2428
0ab9cfeb
ID		 2429 /*
2430 * No point of rolling back things in case of an error, as the best
2431 * we can do is to hope that things will still work (and disable RPM).
2432 */
92b806d3 2433 i915_gem_init_swizzling(dev);
92b806d3 2434
b963291c 2435 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2436
2437 /*
2438 * On VLV/CHV display interrupts are part of the display
2439 * power well, so hpd is reinitialized from there. For
2440 * everyone else do it here.
2441 */
666a4537 2442 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2443 intel_hpd_init(dev_priv);
2444
1f814dac
ID		 2445 enable_rpm_wakeref_asserts(dev_priv);
2446
0ab9cfeb
ID		 2447 if (ret)
2448 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2449 else
2450 DRM_DEBUG_KMS("Device resumed\n");
2451
2452 return ret;
8a187455
PZ		 2453}
2454
42f5551d 2455const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2456 /*
2457 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2458 * PMSG_RESUME]
2459 */
0206e353 2460 .suspend = i915_pm_suspend,
76c4b250
ID		 2461 .suspend_late = i915_pm_suspend_late,
2462 .resume_early = i915_pm_resume_early,
0206e353 2463 .resume = i915_pm_resume,
5545dbbf
ID		 2464
2465 /*
2466 * S4 event handlers
2467 * @freeze, @freeze_late : called (1) before creating the
2468 * hibernation image [PMSG_FREEZE] and
2469 * (2) after rebooting, before restoring
2470 * the image [PMSG_QUIESCE]
2471 * @thaw, @thaw_early : called (1) after creating the hibernation
2472 * image, before writing it [PMSG_THAW]
2473 * and (2) after failing to create or
2474 * restore the image [PMSG_RECOVER]
2475 * @poweroff, @poweroff_late: called after writing the hibernation
2476 * image, before rebooting [PMSG_HIBERNATE]
2477 * @restore, @restore_early : called after rebooting and restoring the
2478 * hibernation image [PMSG_RESTORE]
2479 */
1f19ac2a
CW		 2480 .freeze = i915_pm_freeze,
2481 .freeze_late = i915_pm_freeze_late,
2482 .thaw_early = i915_pm_thaw_early,
2483 .thaw = i915_pm_thaw,
36d61e67 2484 .poweroff = i915_pm_suspend,
ab3be73f 2485 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2486 .restore_early = i915_pm_restore_early,
2487 .restore = i915_pm_restore,
5545dbbf
ID		 2488
2489 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2490 .runtime_suspend = intel_runtime_suspend,
2491 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2492};
2493
78b68556 2494static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2495 .fault = i915_gem_fault,
ab00b3e5
JB		 2496 .open = drm_gem_vm_open,
2497 .close = drm_gem_vm_close,
de151cf6
JB		 2498};
2499
e08e96de
AV		 2500static const struct file_operations i915_driver_fops = {
2501 .owner = THIS_MODULE,
2502 .open = drm_open,
2503 .release = drm_release,
2504 .unlocked_ioctl = drm_ioctl,
2505 .mmap = drm_gem_mmap,
2506 .poll = drm_poll,
e08e96de
AV		 2507 .read = drm_read,
2508#ifdef CONFIG_COMPAT
2509 .compat_ioctl = i915_compat_ioctl,
2510#endif
2511 .llseek = noop_llseek,
2512};
2513
0673ad47
CW		 2514static int
2515i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2516 struct drm_file *file)
2517{
2518 return -ENODEV;
2519}
2520
2521static const struct drm_ioctl_desc i915_ioctls[] = {
2522 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2523 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2524 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2525 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2526 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2527 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2528 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2529 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2530 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2531 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2532 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2533 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2534 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2535 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2536 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2537 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2538 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2539 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2540 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2541 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2542 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2543 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2544 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2545 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2546 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2547 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2548 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2549 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2550 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2551 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2552 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2553 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2554 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2555 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2556 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2557 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2558 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2559 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2560 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2561 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2562 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2563 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2564 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2565 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2566 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2567 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2568 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2569 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2570 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2571 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2572 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2573 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2574};
2575
1da177e4 2576static struct drm_driver driver = {
0c54781b
MW		 2577 /* Don't use MTRRs here; the Xserver or userspace app should
2578 * deal with them for Intel hardware.
792d2b9a 2579 */
673a394b 2580 .driver_features =
10ba5012 2581 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1751fcf9 2582 DRIVER_RENDER | DRIVER_MODESET,
673a394b 2583 .open = i915_driver_open,
22eae947
DA		 2584 .lastclose = i915_driver_lastclose,
2585 .preclose = i915_driver_preclose,
673a394b 2586 .postclose = i915_driver_postclose,
915b4d11 2587 .set_busid = drm_pci_set_busid,
d8e29209 2588
b1f788c6 2589 .gem_close_object = i915_gem_close_object,
673a394b 2590 .gem_free_object = i915_gem_free_object,
de151cf6 2591 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2592
2593 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2594 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2595 .gem_prime_export = i915_gem_prime_export,
2596 .gem_prime_import = i915_gem_prime_import,
2597
ff72145b 2598 .dumb_create = i915_gem_dumb_create,
da6b51d0 2599 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 2600 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 2601 .ioctls = i915_ioctls,
0673ad47 2602 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2603 .fops = &i915_driver_fops,
22eae947
DA		 2604 .name = DRIVER_NAME,
2605 .desc = DRIVER_DESC,
2606 .date = DRIVER_DATE,
2607 .major = DRIVER_MAJOR,
2608 .minor = DRIVER_MINOR,
2609 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2610};
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