]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/i915_drv.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Remove superfluous powersave work flushing
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
0673ad47
CW		 46#include <drm/i915_drm.h>
47
48#include "i915_drv.h"
49#include "i915_trace.h"
50#include "i915_vgpu.h"
51#include "intel_drv.h"
79e53945 52
112b715e
KH		 53static struct drm_driver driver;
54
0673ad47
CW		 55static unsigned int i915_load_fail_count;
56
57bool __i915_inject_load_failure(const char *func, int line)
58{
59 if (i915_load_fail_count >= i915.inject_load_failure)
60 return false;
61
62 if (++i915_load_fail_count == i915.inject_load_failure) {
63 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
64 i915.inject_load_failure, func, line);
65 return true;
66 }
67
68 return false;
69}
70
71#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
72#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
73 "providing the dmesg log by booting with drm.debug=0xf"
74
75void
76__i915_printk(struct drm_i915_private *dev_priv, const char *level,
77 const char *fmt, ...)
78{
79 static bool shown_bug_once;
fb939420 80 struct device *dev = dev_priv->drm.dev;
0673ad47
CW		 81 bool is_error = level[1] <= KERN_ERR[1];
82 bool is_debug = level[1] == KERN_DEBUG[1];
83 struct va_format vaf;
84 va_list args;
85
86 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
87 return;
88
89 va_start(args, fmt);
90
91 vaf.fmt = fmt;
92 vaf.va = &args;
93
94 dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
95 __builtin_return_address(0), &vaf);
96
97 if (is_error && !shown_bug_once) {
98 dev_notice(dev, "%s", FDO_BUG_MSG);
99 shown_bug_once = true;
100 }
101
102 va_end(args);
103}
104
105static bool i915_error_injected(struct drm_i915_private *dev_priv)
106{
107 return i915.inject_load_failure &&
108 i915_load_fail_count == i915.inject_load_failure;
109}
110
111#define i915_load_error(dev_priv, fmt, ...) \
112 __i915_printk(dev_priv, \
113 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
114 fmt, ##__VA_ARGS__)
115
116
117static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
118{
119 enum intel_pch ret = PCH_NOP;
120
121 /*
122 * In a virtualized passthrough environment we can be in a
123 * setup where the ISA bridge is not able to be passed through.
124 * In this case, a south bridge can be emulated and we have to
125 * make an educated guess as to which PCH is really there.
126 */
127
128 if (IS_GEN5(dev)) {
129 ret = PCH_IBX;
130 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
131 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
132 ret = PCH_CPT;
133 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
134 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
135 ret = PCH_LPT;
136 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
137 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
138 ret = PCH_SPT;
139 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
140 }
141
142 return ret;
143}
144
145static void intel_detect_pch(struct drm_device *dev)
146{
fac5e23e 147 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 148 struct pci_dev *pch = NULL;
149
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
152 */
153 if (INTEL_INFO(dev)->num_pipes == 0) {
154 dev_priv->pch_type = PCH_NOP;
155 return;
156 }
157
158 /*
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
163 *
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
168 */
169 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
170 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
171 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
172 dev_priv->pch_id = id;
173
174 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
175 dev_priv->pch_type = PCH_IBX;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
177 WARN_ON(!IS_GEN5(dev));
178 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
179 dev_priv->pch_type = PCH_CPT;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
181 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
182 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
183 /* PantherPoint is CPT compatible */
184 dev_priv->pch_type = PCH_CPT;
185 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
186 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
187 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
188 dev_priv->pch_type = PCH_LPT;
189 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
190 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
191 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
192 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
193 dev_priv->pch_type = PCH_LPT;
194 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
195 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
196 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
197 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
198 dev_priv->pch_type = PCH_SPT;
199 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
200 WARN_ON(!IS_SKYLAKE(dev) &&
201 !IS_KABYLAKE(dev));
202 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
203 dev_priv->pch_type = PCH_SPT;
204 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
205 WARN_ON(!IS_SKYLAKE(dev) &&
206 !IS_KABYLAKE(dev));
22dea0be
RV		 207 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
208 dev_priv->pch_type = PCH_KBP;
209 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
210 WARN_ON(!IS_KABYLAKE(dev));
0673ad47
CW		 211 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
212 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
213 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
214 pch->subsystem_vendor ==
215 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
216 pch->subsystem_device ==
217 PCI_SUBDEVICE_ID_QEMU)) {
218 dev_priv->pch_type = intel_virt_detect_pch(dev);
219 } else
220 continue;
221
222 break;
223 }
224 }
225 if (!pch)
226 DRM_DEBUG_KMS("No PCH found.\n");
227
228 pci_dev_put(pch);
229}
230
231bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
232{
233 if (INTEL_GEN(dev_priv) < 6)
234 return false;
235
236 if (i915.semaphores >= 0)
237 return i915.semaphores;
238
239 /* TODO: make semaphores and Execlists play nicely together */
240 if (i915.enable_execlists)
241 return false;
242
243#ifdef CONFIG_INTEL_IOMMU
244 /* Enable semaphores on SNB when IO remapping is off */
245 if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped)
246 return false;
247#endif
248
249 return true;
250}
251
252static int i915_getparam(struct drm_device *dev, void *data,
253 struct drm_file *file_priv)
254{
fac5e23e 255 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 256 drm_i915_getparam_t *param = data;
257 int value;
258
259 switch (param->param) {
260 case I915_PARAM_IRQ_ACTIVE:
261 case I915_PARAM_ALLOW_BATCHBUFFER:
262 case I915_PARAM_LAST_DISPATCH:
263 /* Reject all old ums/dri params. */
264 return -ENODEV;
265 case I915_PARAM_CHIPSET_ID:
266 value = dev->pdev->device;
267 break;
268 case I915_PARAM_REVISION:
269 value = dev->pdev->revision;
270 break;
271 case I915_PARAM_HAS_GEM:
272 value = 1;
273 break;
274 case I915_PARAM_NUM_FENCES_AVAIL:
275 value = dev_priv->num_fence_regs;
276 break;
277 case I915_PARAM_HAS_OVERLAY:
278 value = dev_priv->overlay ? 1 : 0;
279 break;
280 case I915_PARAM_HAS_PAGEFLIPPING:
281 value = 1;
282 break;
283 case I915_PARAM_HAS_EXECBUF2:
284 /* depends on GEM */
285 value = 1;
286 break;
287 case I915_PARAM_HAS_BSD:
288 value = intel_engine_initialized(&dev_priv->engine[VCS]);
289 break;
290 case I915_PARAM_HAS_BLT:
291 value = intel_engine_initialized(&dev_priv->engine[BCS]);
292 break;
293 case I915_PARAM_HAS_VEBOX:
294 value = intel_engine_initialized(&dev_priv->engine[VECS]);
295 break;
296 case I915_PARAM_HAS_BSD2:
297 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
298 break;
299 case I915_PARAM_HAS_RELAXED_FENCING:
300 value = 1;
301 break;
302 case I915_PARAM_HAS_COHERENT_RINGS:
303 value = 1;
304 break;
305 case I915_PARAM_HAS_EXEC_CONSTANTS:
306 value = INTEL_INFO(dev)->gen >= 4;
307 break;
308 case I915_PARAM_HAS_RELAXED_DELTA:
309 value = 1;
310 break;
311 case I915_PARAM_HAS_GEN7_SOL_RESET:
312 value = 1;
313 break;
314 case I915_PARAM_HAS_LLC:
315 value = HAS_LLC(dev);
316 break;
317 case I915_PARAM_HAS_WT:
318 value = HAS_WT(dev);
319 break;
320 case I915_PARAM_HAS_ALIASING_PPGTT:
321 value = USES_PPGTT(dev);
322 break;
323 case I915_PARAM_HAS_WAIT_TIMEOUT:
324 value = 1;
325 break;
326 case I915_PARAM_HAS_SEMAPHORES:
327 value = i915_semaphore_is_enabled(dev_priv);
328 break;
329 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
330 value = 1;
331 break;
332 case I915_PARAM_HAS_SECURE_BATCHES:
333 value = capable(CAP_SYS_ADMIN);
334 break;
335 case I915_PARAM_HAS_PINNED_BATCHES:
336 value = 1;
337 break;
338 case I915_PARAM_HAS_EXEC_NO_RELOC:
339 value = 1;
340 break;
341 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
342 value = 1;
343 break;
344 case I915_PARAM_CMD_PARSER_VERSION:
345 value = i915_cmd_parser_get_version(dev_priv);
346 break;
347 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
348 value = 1;
349 break;
350 case I915_PARAM_MMAP_VERSION:
351 value = 1;
352 break;
353 case I915_PARAM_SUBSLICE_TOTAL:
354 value = INTEL_INFO(dev)->subslice_total;
355 if (!value)
356 return -ENODEV;
357 break;
358 case I915_PARAM_EU_TOTAL:
359 value = INTEL_INFO(dev)->eu_total;
360 if (!value)
361 return -ENODEV;
362 break;
363 case I915_PARAM_HAS_GPU_RESET:
364 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
365 break;
366 case I915_PARAM_HAS_RESOURCE_STREAMER:
367 value = HAS_RESOURCE_STREAMER(dev);
368 break;
369 case I915_PARAM_HAS_EXEC_SOFTPIN:
370 value = 1;
371 break;
37f501af 372 case I915_PARAM_HAS_POOLED_EU:
373 value = HAS_POOLED_EU(dev);
374 break;
375 case I915_PARAM_MIN_EU_IN_POOL:
376 value = INTEL_INFO(dev)->min_eu_in_pool;
377 break;
0673ad47
CW		 378 default:
379 DRM_DEBUG("Unknown parameter %d\n", param->param);
380 return -EINVAL;
381 }
382
dda33009 383 if (put_user(value, param->value))
0673ad47 384 return -EFAULT;
0673ad47
CW		 385
386 return 0;
387}
388
389static int i915_get_bridge_dev(struct drm_device *dev)
390{
fac5e23e 391 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 392
393 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
394 if (!dev_priv->bridge_dev) {
395 DRM_ERROR("bridge device not found\n");
396 return -1;
397 }
398 return 0;
399}
400
401/* Allocate space for the MCH regs if needed, return nonzero on error */
402static int
403intel_alloc_mchbar_resource(struct drm_device *dev)
404{
fac5e23e 405 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 406 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
407 u32 temp_lo, temp_hi = 0;
408 u64 mchbar_addr;
409 int ret;
410
411 if (INTEL_INFO(dev)->gen >= 4)
412 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
413 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
414 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
415
416 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
417#ifdef CONFIG_PNP
418 if (mchbar_addr &&
419 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
420 return 0;
421#endif
422
423 /* Get some space for it */
424 dev_priv->mch_res.name = "i915 MCHBAR";
425 dev_priv->mch_res.flags = IORESOURCE_MEM;
426 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
427 &dev_priv->mch_res,
428 MCHBAR_SIZE, MCHBAR_SIZE,
429 PCIBIOS_MIN_MEM,
430 0, pcibios_align_resource,
431 dev_priv->bridge_dev);
432 if (ret) {
433 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
434 dev_priv->mch_res.start = 0;
435 return ret;
436 }
437
438 if (INTEL_INFO(dev)->gen >= 4)
439 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
440 upper_32_bits(dev_priv->mch_res.start));
441
442 pci_write_config_dword(dev_priv->bridge_dev, reg,
443 lower_32_bits(dev_priv->mch_res.start));
444 return 0;
445}
446
447/* Setup MCHBAR if possible, return true if we should disable it again */
448static void
449intel_setup_mchbar(struct drm_device *dev)
450{
fac5e23e 451 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 452 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
453 u32 temp;
454 bool enabled;
455
456 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
457 return;
458
459 dev_priv->mchbar_need_disable = false;
460
461 if (IS_I915G(dev) || IS_I915GM(dev)) {
462 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
463 enabled = !!(temp & DEVEN_MCHBAR_EN);
464 } else {
465 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
466 enabled = temp & 1;
467 }
468
469 /* If it's already enabled, don't have to do anything */
470 if (enabled)
471 return;
472
473 if (intel_alloc_mchbar_resource(dev))
474 return;
475
476 dev_priv->mchbar_need_disable = true;
477
478 /* Space is allocated or reserved, so enable it. */
479 if (IS_I915G(dev) || IS_I915GM(dev)) {
480 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
481 temp | DEVEN_MCHBAR_EN);
482 } else {
483 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
484 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
485 }
486}
487
488static void
489intel_teardown_mchbar(struct drm_device *dev)
490{
fac5e23e 491 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 492 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
493
494 if (dev_priv->mchbar_need_disable) {
495 if (IS_I915G(dev) || IS_I915GM(dev)) {
496 u32 deven_val;
497
498 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
499 &deven_val);
500 deven_val &= ~DEVEN_MCHBAR_EN;
501 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
502 deven_val);
503 } else {
504 u32 mchbar_val;
505
506 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
507 &mchbar_val);
508 mchbar_val &= ~1;
509 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
510 mchbar_val);
511 }
512 }
513
514 if (dev_priv->mch_res.start)
515 release_resource(&dev_priv->mch_res);
516}
517
518/* true = enable decode, false = disable decoder */
519static unsigned int i915_vga_set_decode(void *cookie, bool state)
520{
521 struct drm_device *dev = cookie;
522
523 intel_modeset_vga_set_state(dev, state);
524 if (state)
525 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
526 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
527 else
528 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
529}
530
531static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
532{
533 struct drm_device *dev = pci_get_drvdata(pdev);
534 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
535
536 if (state == VGA_SWITCHEROO_ON) {
537 pr_info("switched on\n");
538 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
539 /* i915 resume handler doesn't set to D0 */
540 pci_set_power_state(dev->pdev, PCI_D0);
541 i915_resume_switcheroo(dev);
542 dev->switch_power_state = DRM_SWITCH_POWER_ON;
543 } else {
544 pr_info("switched off\n");
545 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
546 i915_suspend_switcheroo(dev, pmm);
547 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
548 }
549}
550
551static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
552{
553 struct drm_device *dev = pci_get_drvdata(pdev);
554
555 /*
556 * FIXME: open_count is protected by drm_global_mutex but that would lead to
557 * locking inversion with the driver load path. And the access here is
558 * completely racy anyway. So don't bother with locking for now.
559 */
560 return dev->open_count == 0;
561}
562
563static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
564 .set_gpu_state = i915_switcheroo_set_state,
565 .reprobe = NULL,
566 .can_switch = i915_switcheroo_can_switch,
567};
568
569static void i915_gem_fini(struct drm_device *dev)
570{
571 struct drm_i915_private *dev_priv = to_i915(dev);
572
573 /*
574 * Neither the BIOS, ourselves or any other kernel
575 * expects the system to be in execlists mode on startup,
576 * so we need to reset the GPU back to legacy mode. And the only
577 * known way to disable logical contexts is through a GPU reset.
578 *
579 * So in order to leave the system in a known default configuration,
580 * always reset the GPU upon unload. Afterwards we then clean up the
581 * GEM state tracking, flushing off the requests and leaving the
582 * system in a known idle state.
583 *
584 * Note that is of the upmost importance that the GPU is idle and
585 * all stray writes are flushed *before* we dismantle the backing
586 * storage for the pinned objects.
587 *
588 * However, since we are uncertain that reseting the GPU on older
589 * machines is a good idea, we don't - just in case it leaves the
590 * machine in an unusable condition.
591 */
592 if (HAS_HW_CONTEXTS(dev)) {
593 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
594 WARN_ON(reset && reset != -ENODEV);
595 }
596
597 mutex_lock(&dev->struct_mutex);
598 i915_gem_reset(dev);
599 i915_gem_cleanup_engines(dev);
600 i915_gem_context_fini(dev);
601 mutex_unlock(&dev->struct_mutex);
602
603 WARN_ON(!list_empty(&to_i915(dev)->context_list));
604}
605
606static int i915_load_modeset_init(struct drm_device *dev)
607{
fac5e23e 608 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 609 int ret;
610
611 if (i915_inject_load_failure())
612 return -ENODEV;
613
614 ret = intel_bios_init(dev_priv);
615 if (ret)
616 DRM_INFO("failed to find VBIOS tables\n");
617
618 /* If we have > 1 VGA cards, then we need to arbitrate access
619 * to the common VGA resources.
620 *
621 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
622 * then we do not take part in VGA arbitration and the
623 * vga_client_register() fails with -ENODEV.
624 */
625 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
626 if (ret && ret != -ENODEV)
627 goto out;
628
629 intel_register_dsm_handler();
630
631 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
632 if (ret)
633 goto cleanup_vga_client;
634
635 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
636 intel_update_rawclk(dev_priv);
637
638 intel_power_domains_init_hw(dev_priv, false);
639
640 intel_csr_ucode_init(dev_priv);
641
642 ret = intel_irq_install(dev_priv);
643 if (ret)
644 goto cleanup_csr;
645
646 intel_setup_gmbus(dev);
647
648 /* Important: The output setup functions called by modeset_init need
649 * working irqs for e.g. gmbus and dp aux transfers. */
650 intel_modeset_init(dev);
651
652 intel_guc_init(dev);
653
654 ret = i915_gem_init(dev);
655 if (ret)
656 goto cleanup_irq;
657
658 intel_modeset_gem_init(dev);
659
660 if (INTEL_INFO(dev)->num_pipes == 0)
661 return 0;
662
663 ret = intel_fbdev_init(dev);
664 if (ret)
665 goto cleanup_gem;
666
667 /* Only enable hotplug handling once the fbdev is fully set up. */
668 intel_hpd_init(dev_priv);
669
670 drm_kms_helper_poll_init(dev);
671
672 return 0;
673
674cleanup_gem:
675 i915_gem_fini(dev);
676cleanup_irq:
677 intel_guc_fini(dev);
678 drm_irq_uninstall(dev);
679 intel_teardown_gmbus(dev);
680cleanup_csr:
681 intel_csr_ucode_fini(dev_priv);
682 intel_power_domains_fini(dev_priv);
683 vga_switcheroo_unregister_client(dev->pdev);
684cleanup_vga_client:
685 vga_client_register(dev->pdev, NULL, NULL, NULL);
686out:
687 return ret;
688}
689
690#if IS_ENABLED(CONFIG_FB)
691static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
692{
693 struct apertures_struct *ap;
91c8a326 694 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 695 struct i915_ggtt *ggtt = &dev_priv->ggtt;
696 bool primary;
697 int ret;
698
699 ap = alloc_apertures(1);
700 if (!ap)
701 return -ENOMEM;
702
703 ap->ranges[0].base = ggtt->mappable_base;
704 ap->ranges[0].size = ggtt->mappable_end;
705
706 primary =
707 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
708
709 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
710
711 kfree(ap);
712
713 return ret;
714}
715#else
716static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
717{
718 return 0;
719}
720#endif
721
722#if !defined(CONFIG_VGA_CONSOLE)
723static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
724{
725 return 0;
726}
727#elif !defined(CONFIG_DUMMY_CONSOLE)
728static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
729{
730 return -ENODEV;
731}
732#else
733static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
734{
735 int ret = 0;
736
737 DRM_INFO("Replacing VGA console driver\n");
738
739 console_lock();
740 if (con_is_bound(&vga_con))
741 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
742 if (ret == 0) {
743 ret = do_unregister_con_driver(&vga_con);
744
745 /* Ignore "already unregistered". */
746 if (ret == -ENODEV)
747 ret = 0;
748 }
749 console_unlock();
750
751 return ret;
752}
753#endif
754
0673ad47
CW		 755static void intel_init_dpio(struct drm_i915_private *dev_priv)
756{
757 /*
758 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
759 * CHV x1 PHY (DP/HDMI D)
760 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
761 */
762 if (IS_CHERRYVIEW(dev_priv)) {
763 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
764 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
765 } else if (IS_VALLEYVIEW(dev_priv)) {
766 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
767 }
768}
769
770static int i915_workqueues_init(struct drm_i915_private *dev_priv)
771{
772 /*
773 * The i915 workqueue is primarily used for batched retirement of
774 * requests (and thus managing bo) once the task has been completed
775 * by the GPU. i915_gem_retire_requests() is called directly when we
776 * need high-priority retirement, such as waiting for an explicit
777 * bo.
778 *
779 * It is also used for periodic low-priority events, such as
780 * idle-timers and recording error state.
781 *
782 * All tasks on the workqueue are expected to acquire the dev mutex
783 * so there is no point in running more than one instance of the
784 * workqueue at any time. Use an ordered one.
785 */
786 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
787 if (dev_priv->wq == NULL)
788 goto out_err;
789
790 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
791 if (dev_priv->hotplug.dp_wq == NULL)
792 goto out_free_wq;
793
0673ad47
CW		 794 return 0;
795
0673ad47
CW		 796out_free_wq:
797 destroy_workqueue(dev_priv->wq);
798out_err:
799 DRM_ERROR("Failed to allocate workqueues.\n");
800
801 return -ENOMEM;
802}
803
804static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
805{
0673ad47
CW		 806 destroy_workqueue(dev_priv->hotplug.dp_wq);
807 destroy_workqueue(dev_priv->wq);
808}
809
810/**
811 * i915_driver_init_early - setup state not requiring device access
812 * @dev_priv: device private
813 *
814 * Initialize everything that is a "SW-only" state, that is state not
815 * requiring accessing the device or exposing the driver via kernel internal
816 * or userspace interfaces. Example steps belonging here: lock initialization,
817 * system memory allocation, setting up device specific attributes and
818 * function hooks not requiring accessing the device.
819 */
820static int i915_driver_init_early(struct drm_i915_private *dev_priv,
821 const struct pci_device_id *ent)
822{
823 const struct intel_device_info *match_info =
824 (struct intel_device_info *)ent->driver_data;
825 struct intel_device_info *device_info;
826 int ret = 0;
827
828 if (i915_inject_load_failure())
829 return -ENODEV;
830
831 /* Setup the write-once "constant" device info */
94b4f3ba 832 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 833 memcpy(device_info, match_info, sizeof(*device_info));
834 device_info->device_id = dev_priv->drm.pdev->device;
835
836 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
837 device_info->gen_mask = BIT(device_info->gen - 1);
838
839 spin_lock_init(&dev_priv->irq_lock);
840 spin_lock_init(&dev_priv->gpu_error.lock);
841 mutex_init(&dev_priv->backlight_lock);
842 spin_lock_init(&dev_priv->uncore.lock);
843 spin_lock_init(&dev_priv->mm.object_stat_lock);
844 spin_lock_init(&dev_priv->mmio_flip_lock);
845 mutex_init(&dev_priv->sb_lock);
846 mutex_init(&dev_priv->modeset_restore_lock);
847 mutex_init(&dev_priv->av_mutex);
848 mutex_init(&dev_priv->wm.wm_mutex);
849 mutex_init(&dev_priv->pps_mutex);
850
851 ret = i915_workqueues_init(dev_priv);
852 if (ret < 0)
853 return ret;
854
855 ret = intel_gvt_init(dev_priv);
856 if (ret < 0)
857 goto err_workqueues;
858
859 /* This must be called before any calls to HAS_PCH_* */
860 intel_detect_pch(&dev_priv->drm);
861
862 intel_pm_setup(&dev_priv->drm);
863 intel_init_dpio(dev_priv);
864 intel_power_domains_init(dev_priv);
865 intel_irq_init(dev_priv);
866 intel_init_display_hooks(dev_priv);
867 intel_init_clock_gating_hooks(dev_priv);
868 intel_init_audio_hooks(dev_priv);
869 i915_gem_load_init(&dev_priv->drm);
870
871 intel_display_crc_init(&dev_priv->drm);
872
94b4f3ba 873 intel_device_info_dump(dev_priv);
0673ad47
CW		 874
875 /* Not all pre-production machines fall into this category, only the
876 * very first ones. Almost everything should work, except for maybe
877 * suspend/resume. And we don't implement workarounds that affect only
878 * pre-production machines. */
879 if (IS_HSW_EARLY_SDV(dev_priv))
880 DRM_INFO("This is an early pre-production Haswell machine. "
881 "It may not be fully functional.\n");
882
883 return 0;
884
885err_workqueues:
886 i915_workqueues_cleanup(dev_priv);
887 return ret;
888}
889
890/**
891 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
892 * @dev_priv: device private
893 */
894static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
895{
91c8a326 896 i915_gem_load_cleanup(&dev_priv->drm);
0673ad47
CW		 897 i915_workqueues_cleanup(dev_priv);
898}
899
900static int i915_mmio_setup(struct drm_device *dev)
901{
902 struct drm_i915_private *dev_priv = to_i915(dev);
903 int mmio_bar;
904 int mmio_size;
905
906 mmio_bar = IS_GEN2(dev) ? 1 : 0;
907 /*
908 * Before gen4, the registers and the GTT are behind different BARs.
909 * However, from gen4 onwards, the registers and the GTT are shared
910 * in the same BAR, so we want to restrict this ioremap from
911 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
912 * the register BAR remains the same size for all the earlier
913 * generations up to Ironlake.
914 */
915 if (INTEL_INFO(dev)->gen < 5)
916 mmio_size = 512 * 1024;
917 else
918 mmio_size = 2 * 1024 * 1024;
919 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
920 if (dev_priv->regs == NULL) {
921 DRM_ERROR("failed to map registers\n");
922
923 return -EIO;
924 }
925
926 /* Try to make sure MCHBAR is enabled before poking at it */
927 intel_setup_mchbar(dev);
928
929 return 0;
930}
931
932static void i915_mmio_cleanup(struct drm_device *dev)
933{
934 struct drm_i915_private *dev_priv = to_i915(dev);
935
936 intel_teardown_mchbar(dev);
937 pci_iounmap(dev->pdev, dev_priv->regs);
938}
939
940/**
941 * i915_driver_init_mmio - setup device MMIO
942 * @dev_priv: device private
943 *
944 * Setup minimal device state necessary for MMIO accesses later in the
945 * initialization sequence. The setup here should avoid any other device-wide
946 * side effects or exposing the driver via kernel internal or user space
947 * interfaces.
948 */
949static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
950{
91c8a326 951 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 952 int ret;
953
954 if (i915_inject_load_failure())
955 return -ENODEV;
956
957 if (i915_get_bridge_dev(dev))
958 return -EIO;
959
960 ret = i915_mmio_setup(dev);
961 if (ret < 0)
962 goto put_bridge;
963
964 intel_uncore_init(dev_priv);
965
966 return 0;
967
968put_bridge:
969 pci_dev_put(dev_priv->bridge_dev);
970
971 return ret;
972}
973
974/**
975 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
976 * @dev_priv: device private
977 */
978static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
979{
91c8a326 980 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 981
982 intel_uncore_fini(dev_priv);
983 i915_mmio_cleanup(dev);
984 pci_dev_put(dev_priv->bridge_dev);
985}
986
94b4f3ba
CW		 987static void intel_sanitize_options(struct drm_i915_private *dev_priv)
988{
989 i915.enable_execlists =
990 intel_sanitize_enable_execlists(dev_priv,
991 i915.enable_execlists);
992
993 /*
994 * i915.enable_ppgtt is read-only, so do an early pass to validate the
995 * user's requested state against the hardware/driver capabilities. We
996 * do this now so that we can print out any log messages once rather
997 * than every time we check intel_enable_ppgtt().
998 */
999 i915.enable_ppgtt =
1000 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1001 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1002}
1003
0673ad47
CW		 1004/**
1005 * i915_driver_init_hw - setup state requiring device access
1006 * @dev_priv: device private
1007 *
1008 * Setup state that requires accessing the device, but doesn't require
1009 * exposing the driver via kernel internal or userspace interfaces.
1010 */
1011static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1012{
91c8a326 1013 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1014 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1015 uint32_t aperture_size;
1016 int ret;
1017
1018 if (i915_inject_load_failure())
1019 return -ENODEV;
1020
94b4f3ba
CW		 1021 intel_device_info_runtime_init(dev_priv);
1022
1023 intel_sanitize_options(dev_priv);
0673ad47
CW		 1024
1025 ret = i915_ggtt_init_hw(dev);
1026 if (ret)
1027 return ret;
1028
1029 ret = i915_ggtt_enable_hw(dev);
1030 if (ret) {
1031 DRM_ERROR("failed to enable GGTT\n");
1032 goto out_ggtt;
1033 }
1034
1035 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1036 * otherwise the vga fbdev driver falls over. */
1037 ret = i915_kick_out_firmware_fb(dev_priv);
1038 if (ret) {
1039 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1040 goto out_ggtt;
1041 }
1042
1043 ret = i915_kick_out_vgacon(dev_priv);
1044 if (ret) {
1045 DRM_ERROR("failed to remove conflicting VGA console\n");
1046 goto out_ggtt;
1047 }
1048
1049 pci_set_master(dev->pdev);
1050
1051 /* overlay on gen2 is broken and can't address above 1G */
1052 if (IS_GEN2(dev)) {
1053 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1054 if (ret) {
1055 DRM_ERROR("failed to set DMA mask\n");
1056
1057 goto out_ggtt;
1058 }
1059 }
1060
1061
1062 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1063 * using 32bit addressing, overwriting memory if HWS is located
1064 * above 4GB.
1065 *
1066 * The documentation also mentions an issue with undefined
1067 * behaviour if any general state is accessed within a page above 4GB,
1068 * which also needs to be handled carefully.
1069 */
1070 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1071 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1072
1073 if (ret) {
1074 DRM_ERROR("failed to set DMA mask\n");
1075
1076 goto out_ggtt;
1077 }
1078 }
1079
1080 aperture_size = ggtt->mappable_end;
1081
1082 ggtt->mappable =
1083 io_mapping_create_wc(ggtt->mappable_base,
1084 aperture_size);
1085 if (!ggtt->mappable) {
1086 ret = -EIO;
1087 goto out_ggtt;
1088 }
1089
1090 ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1091 aperture_size);
1092
1093 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1094 PM_QOS_DEFAULT_VALUE);
1095
1096 intel_uncore_sanitize(dev_priv);
1097
1098 intel_opregion_setup(dev_priv);
1099
1100 i915_gem_load_init_fences(dev_priv);
1101
1102 /* On the 945G/GM, the chipset reports the MSI capability on the
1103 * integrated graphics even though the support isn't actually there
1104 * according to the published specs. It doesn't appear to function
1105 * correctly in testing on 945G.
1106 * This may be a side effect of MSI having been made available for PEG
1107 * and the registers being closely associated.
1108 *
1109 * According to chipset errata, on the 965GM, MSI interrupts may
1110 * be lost or delayed, but we use them anyways to avoid
1111 * stuck interrupts on some machines.
1112 */
1113 if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1114 if (pci_enable_msi(dev->pdev) < 0)
1115 DRM_DEBUG_DRIVER("can't enable MSI");
1116 }
1117
1118 return 0;
1119
1120out_ggtt:
1121 i915_ggtt_cleanup_hw(dev);
1122
1123 return ret;
1124}
1125
1126/**
1127 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1128 * @dev_priv: device private
1129 */
1130static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1131{
91c8a326 1132 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1133 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1134
1135 if (dev->pdev->msi_enabled)
1136 pci_disable_msi(dev->pdev);
1137
1138 pm_qos_remove_request(&dev_priv->pm_qos);
1139 arch_phys_wc_del(ggtt->mtrr);
1140 io_mapping_free(ggtt->mappable);
1141 i915_ggtt_cleanup_hw(dev);
1142}
1143
1144/**
1145 * i915_driver_register - register the driver with the rest of the system
1146 * @dev_priv: device private
1147 *
1148 * Perform any steps necessary to make the driver available via kernel
1149 * internal or userspace interfaces.
1150 */
1151static void i915_driver_register(struct drm_i915_private *dev_priv)
1152{
91c8a326 1153 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1154
1155 i915_gem_shrinker_init(dev_priv);
1156
1157 /*
1158 * Notify a valid surface after modesetting,
1159 * when running inside a VM.
1160 */
1161 if (intel_vgpu_active(dev_priv))
1162 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1163
1164 /* Reveal our presence to userspace */
1165 if (drm_dev_register(dev, 0) == 0) {
1166 i915_debugfs_register(dev_priv);
1167 i915_setup_sysfs(dev);
1168 } else
1169 DRM_ERROR("Failed to register driver for userspace access!\n");
1170
1171 if (INTEL_INFO(dev_priv)->num_pipes) {
1172 /* Must be done after probing outputs */
1173 intel_opregion_register(dev_priv);
1174 acpi_video_register();
1175 }
1176
1177 if (IS_GEN5(dev_priv))
1178 intel_gpu_ips_init(dev_priv);
1179
1180 i915_audio_component_init(dev_priv);
1181
1182 /*
1183 * Some ports require correctly set-up hpd registers for detection to
1184 * work properly (leading to ghost connected connector status), e.g. VGA
1185 * on gm45. Hence we can only set up the initial fbdev config after hpd
1186 * irqs are fully enabled. We do it last so that the async config
1187 * cannot run before the connectors are registered.
1188 */
1189 intel_fbdev_initial_config_async(dev);
1190}
1191
1192/**
1193 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1194 * @dev_priv: device private
1195 */
1196static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1197{
1198 i915_audio_component_cleanup(dev_priv);
1199
1200 intel_gpu_ips_teardown();
1201 acpi_video_unregister();
1202 intel_opregion_unregister(dev_priv);
1203
91c8a326 1204 i915_teardown_sysfs(&dev_priv->drm);
0673ad47 1205 i915_debugfs_unregister(dev_priv);
91c8a326 1206 drm_dev_unregister(&dev_priv->drm);
0673ad47
CW		 1207
1208 i915_gem_shrinker_cleanup(dev_priv);
1209}
1210
1211/**
1212 * i915_driver_load - setup chip and create an initial config
1213 * @dev: DRM device
1214 * @flags: startup flags
1215 *
1216 * The driver load routine has to do several things:
1217 * - drive output discovery via intel_modeset_init()
1218 * - initialize the memory manager
1219 * - allocate initial config memory
1220 * - setup the DRM framebuffer with the allocated memory
1221 */
42f5551d 1222int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47
CW		 1223{
1224 struct drm_i915_private *dev_priv;
1225 int ret;
7d87a7f7 1226
a09d0ba1
CW		 1227 if (i915.nuclear_pageflip)
1228 driver.driver_features |= DRIVER_ATOMIC;
1229
0673ad47
CW		 1230 ret = -ENOMEM;
1231 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1232 if (dev_priv)
1233 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1234 if (ret) {
1235 dev_printk(KERN_ERR, &pdev->dev,
1236 "[" DRM_NAME ":%s] allocation failed\n", __func__);
1237 kfree(dev_priv);
1238 return ret;
1239 }
72bbf0af 1240
0673ad47
CW		 1241 dev_priv->drm.pdev = pdev;
1242 dev_priv->drm.dev_private = dev_priv;
719388e1 1243
0673ad47
CW		 1244 ret = pci_enable_device(pdev);
1245 if (ret)
1246 goto out_free_priv;
1347f5b4 1247
0673ad47 1248 pci_set_drvdata(pdev, &dev_priv->drm);
ef11bdb3 1249
0673ad47
CW		 1250 ret = i915_driver_init_early(dev_priv, ent);
1251 if (ret < 0)
1252 goto out_pci_disable;
ef11bdb3 1253
0673ad47 1254 intel_runtime_pm_get(dev_priv);
1da177e4 1255
0673ad47
CW		 1256 ret = i915_driver_init_mmio(dev_priv);
1257 if (ret < 0)
1258 goto out_runtime_pm_put;
79e53945 1259
0673ad47
CW		 1260 ret = i915_driver_init_hw(dev_priv);
1261 if (ret < 0)
1262 goto out_cleanup_mmio;
30c964a6
RB		 1263
1264 /*
0673ad47
CW		 1265 * TODO: move the vblank init and parts of modeset init steps into one
1266 * of the i915_driver_init_/i915_driver_register functions according
1267 * to the role/effect of the given init step.
30c964a6 1268 */
0673ad47 1269 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1270 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1271 INTEL_INFO(dev_priv)->num_pipes);
1272 if (ret)
1273 goto out_cleanup_hw;
30c964a6
RB		 1274 }
1275
91c8a326 1276 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47
CW		 1277 if (ret < 0)
1278 goto out_cleanup_vblank;
1279
1280 i915_driver_register(dev_priv);
1281
1282 intel_runtime_pm_enable(dev_priv);
1283
1284 intel_runtime_pm_put(dev_priv);
1285
1286 return 0;
1287
1288out_cleanup_vblank:
91c8a326 1289 drm_vblank_cleanup(&dev_priv->drm);
0673ad47
CW		 1290out_cleanup_hw:
1291 i915_driver_cleanup_hw(dev_priv);
1292out_cleanup_mmio:
1293 i915_driver_cleanup_mmio(dev_priv);
1294out_runtime_pm_put:
1295 intel_runtime_pm_put(dev_priv);
1296 i915_driver_cleanup_early(dev_priv);
1297out_pci_disable:
1298 pci_disable_device(pdev);
1299out_free_priv:
1300 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1301 drm_dev_unref(&dev_priv->drm);
30c964a6
RB		 1302 return ret;
1303}
1304
42f5551d 1305void i915_driver_unload(struct drm_device *dev)
3bad0781 1306{
fac5e23e 1307 struct drm_i915_private *dev_priv = to_i915(dev);
3bad0781 1308
0673ad47
CW		 1309 intel_fbdev_fini(dev);
1310
42f5551d
CW		 1311 if (i915_gem_suspend(dev))
1312 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1313
0673ad47
CW		 1314 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1315
1316 i915_driver_unregister(dev_priv);
1317
1318 drm_vblank_cleanup(dev);
1319
1320 intel_modeset_cleanup(dev);
1321
3bad0781 1322 /*
0673ad47
CW		 1323 * free the memory space allocated for the child device
1324 * config parsed from VBT
3bad0781 1325 */
0673ad47
CW		 1326 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1327 kfree(dev_priv->vbt.child_dev);
1328 dev_priv->vbt.child_dev = NULL;
1329 dev_priv->vbt.child_dev_num = 0;
1330 }
1331 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1332 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1333 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1334 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1335
0673ad47
CW		 1336 vga_switcheroo_unregister_client(dev->pdev);
1337 vga_client_register(dev->pdev, NULL, NULL, NULL);
bcdb72ac 1338
0673ad47 1339 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1340
0673ad47
CW		 1341 /* Free error state after interrupts are fully disabled. */
1342 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1343 i915_destroy_error_state(dev);
1344
1345 /* Flush any outstanding unpin_work. */
1346 flush_workqueue(dev_priv->wq);
1347
1348 intel_guc_fini(dev);
1349 i915_gem_fini(dev);
1350 intel_fbc_cleanup_cfb(dev_priv);
1351
1352 intel_power_domains_fini(dev_priv);
1353
1354 i915_driver_cleanup_hw(dev_priv);
1355 i915_driver_cleanup_mmio(dev_priv);
1356
1357 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1358
1359 i915_driver_cleanup_early(dev_priv);
3bad0781
ZW		 1360}
1361
0673ad47 1362static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1363{
0673ad47 1364 int ret;
2911a35b 1365
0673ad47
CW		 1366 ret = i915_gem_open(dev, file);
1367 if (ret)
1368 return ret;
2911a35b 1369
0673ad47
CW		 1370 return 0;
1371}
71386ef9 1372
0673ad47
CW		 1373/**
1374 * i915_driver_lastclose - clean up after all DRM clients have exited
1375 * @dev: DRM device
1376 *
1377 * Take care of cleaning up after all DRM clients have exited. In the
1378 * mode setting case, we want to restore the kernel's initial mode (just
1379 * in case the last client left us in a bad state).
1380 *
1381 * Additionally, in the non-mode setting case, we'll tear down the GTT
1382 * and DMA structures, since the kernel won't be using them, and clea
1383 * up any GEM state.
1384 */
1385static void i915_driver_lastclose(struct drm_device *dev)
1386{
1387 intel_fbdev_restore_mode(dev);
1388 vga_switcheroo_process_delayed_switch();
1389}
2911a35b 1390
0673ad47
CW		 1391static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1392{
1393 mutex_lock(&dev->struct_mutex);
1394 i915_gem_context_close(dev, file);
1395 i915_gem_release(dev, file);
1396 mutex_unlock(&dev->struct_mutex);
1397}
1398
1399static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1400{
1401 struct drm_i915_file_private *file_priv = file->driver_priv;
1402
1403 kfree(file_priv);
2911a35b
BW		 1404}
1405
07f9cd0b
ID		 1406static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1407{
91c8a326 1408 struct drm_device *dev = &dev_priv->drm;
19c8054c 1409 struct intel_encoder *encoder;
07f9cd0b
ID		 1410
1411 drm_modeset_lock_all(dev);
19c8054c
JN		 1412 for_each_intel_encoder(dev, encoder)
1413 if (encoder->suspend)
1414 encoder->suspend(encoder);
07f9cd0b
ID		 1415 drm_modeset_unlock_all(dev);
1416}
1417
1a5df187
PZ		 1418static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1419 bool rpm_resume);
507e126e 1420static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1421
bc87229f
ID		 1422static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1423{
1424#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1425 if (acpi_target_system_state() < ACPI_STATE_S3)
1426 return true;
1427#endif
1428 return false;
1429}
ebc32824 1430
5e365c39 1431static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1432{
fac5e23e 1433 struct drm_i915_private *dev_priv = to_i915(dev);
e5747e3a 1434 pci_power_t opregion_target_state;
d5818938 1435 int error;
61caf87c 1436
b8efb17b
ZR		 1437 /* ignore lid events during suspend */
1438 mutex_lock(&dev_priv->modeset_restore_lock);
1439 dev_priv->modeset_restore = MODESET_SUSPENDED;
1440 mutex_unlock(&dev_priv->modeset_restore_lock);
1441
1f814dac
ID		 1442 disable_rpm_wakeref_asserts(dev_priv);
1443
c67a470b
PZ		 1444 /* We do a lot of poking in a lot of registers, make sure they work
1445 * properly. */
da7e29bd 1446 intel_display_set_init_power(dev_priv, true);
cb10799c 1447
5bcf719b
DA		 1448 drm_kms_helper_poll_disable(dev);
1449
ba8bbcf6 1450 pci_save_state(dev->pdev);
ba8bbcf6 1451
d5818938
DV		 1452 error = i915_gem_suspend(dev);
1453 if (error) {
1454 dev_err(&dev->pdev->dev,
1455 "GEM idle failed, resume might fail\n");
1f814dac 1456 goto out;
d5818938 1457 }
db1b76ca 1458
a1c41994
AD		 1459 intel_guc_suspend(dev);
1460
dc97997a 1461 intel_suspend_gt_powersave(dev_priv);
a261b246 1462
6b72d486 1463 intel_display_suspend(dev);
2eb5252e 1464
d5818938 1465 intel_dp_mst_suspend(dev);
7d708ee4 1466
d5818938
DV		 1467 intel_runtime_pm_disable_interrupts(dev_priv);
1468 intel_hpd_cancel_work(dev_priv);
09b64267 1469
d5818938 1470 intel_suspend_encoders(dev_priv);
0e32b39c 1471
d5818938 1472 intel_suspend_hw(dev);
5669fcac 1473
828c7908
BW		 1474 i915_gem_suspend_gtt_mappings(dev);
1475
9e06dd39
JB		 1476 i915_save_state(dev);
1477
bc87229f 1478 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1479 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1480
dc97997a 1481 intel_uncore_forcewake_reset(dev_priv, false);
03d92e47 1482 intel_opregion_unregister(dev_priv);
8ee1c3db 1483
82e3b8c1 1484 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1485
62d5d69b
MK		 1486 dev_priv->suspend_count++;
1487
85e90679
KCA		 1488 intel_display_set_init_power(dev_priv, false);
1489
f74ed08d 1490 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1491
1f814dac
ID		 1492out:
1493 enable_rpm_wakeref_asserts(dev_priv);
1494
1495 return error;
84b79f8d
RW		 1496}
1497
ab3be73f 1498static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
c3c09c95 1499{
fac5e23e 1500 struct drm_i915_private *dev_priv = to_i915(drm_dev);
bc87229f 1501 bool fw_csr;
c3c09c95
ID		 1502 int ret;
1503
1f814dac
ID		 1504 disable_rpm_wakeref_asserts(dev_priv);
1505
a7c8125f
ID		 1506 fw_csr = !IS_BROXTON(dev_priv) &&
1507 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1508 /*
1509 * In case of firmware assisted context save/restore don't manually
1510 * deinit the power domains. This also means the CSR/DMC firmware will
1511 * stay active, it will power down any HW resources as required and
1512 * also enable deeper system power states that would be blocked if the
1513 * firmware was inactive.
1514 */
1515 if (!fw_csr)
1516 intel_power_domains_suspend(dev_priv);
73dfc227 1517
507e126e 1518 ret = 0;
b8aea3d1 1519 if (IS_BROXTON(dev_priv))
507e126e 1520 bxt_enable_dc9(dev_priv);
b8aea3d1 1521 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1522 hsw_enable_pc8(dev_priv);
1523 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1524 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1525
1526 if (ret) {
1527 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1528 if (!fw_csr)
1529 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1530
1f814dac 1531 goto out;
c3c09c95
ID		 1532 }
1533
1534 pci_disable_device(drm_dev->pdev);
ab3be73f 1535 /*
54875571 1536 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1537 * the device even though it's already in D3 and hang the machine. So
1538 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1539 * power down the device properly. The issue was seen on multiple old
1540 * GENs with different BIOS vendors, so having an explicit blacklist
1541 * is inpractical; apply the workaround on everything pre GEN6. The
1542 * platforms where the issue was seen:
1543 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1544 * Fujitsu FSC S7110
1545 * Acer Aspire 1830T
ab3be73f 1546 */
54875571 1547 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
ab3be73f 1548 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
c3c09c95 1549
bc87229f
ID		 1550 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1551
1f814dac
ID		 1552out:
1553 enable_rpm_wakeref_asserts(dev_priv);
1554
1555 return ret;
c3c09c95
ID		 1556}
1557
1751fcf9 1558int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1559{
1560 int error;
1561
ded8b07d 1562 if (!dev) {
84b79f8d
RW		 1563 DRM_ERROR("dev: %p\n", dev);
1564 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1565 return -ENODEV;
1566 }
1567
0b14cbd2
ID		 1568 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1569 state.event != PM_EVENT_FREEZE))
1570 return -EINVAL;
5bcf719b
DA		 1571
1572 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1573 return 0;
6eecba33 1574
5e365c39 1575 error = i915_drm_suspend(dev);
84b79f8d
RW		 1576 if (error)
1577 return error;
1578
ab3be73f 1579 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1580}
1581
5e365c39 1582static int i915_drm_resume(struct drm_device *dev)
76c4b250 1583{
fac5e23e 1584 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1585 int ret;
9d49c0ef 1586
1f814dac
ID		 1587 disable_rpm_wakeref_asserts(dev_priv);
1588
ac840ae5
VS		 1589 ret = i915_ggtt_enable_hw(dev);
1590 if (ret)
1591 DRM_ERROR("failed to re-enable GGTT\n");
1592
f74ed08d
ID		 1593 intel_csr_ucode_resume(dev_priv);
1594
d5818938
DV		 1595 mutex_lock(&dev->struct_mutex);
1596 i915_gem_restore_gtt_mappings(dev);
1597 mutex_unlock(&dev->struct_mutex);
9d49c0ef 1598
61caf87c 1599 i915_restore_state(dev);
6f9f4b7a 1600 intel_opregion_setup(dev_priv);
61caf87c 1601
d5818938
DV		 1602 intel_init_pch_refclk(dev);
1603 drm_mode_config_reset(dev);
1833b134 1604
364aece0
PA		 1605 /*
1606 * Interrupts have to be enabled before any batches are run. If not the
1607 * GPU will hang. i915_gem_init_hw() will initiate batches to
1608 * update/restore the context.
1609 *
1610 * Modeset enabling in intel_modeset_init_hw() also needs working
1611 * interrupts.
1612 */
1613 intel_runtime_pm_enable_interrupts(dev_priv);
1614
d5818938
DV		 1615 mutex_lock(&dev->struct_mutex);
1616 if (i915_gem_init_hw(dev)) {
1617 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
338d0eea 1618 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
d5818938
DV		 1619 }
1620 mutex_unlock(&dev->struct_mutex);
226485e9 1621
a1c41994
AD		 1622 intel_guc_resume(dev);
1623
d5818938 1624 intel_modeset_init_hw(dev);
24576d23 1625
d5818938
DV		 1626 spin_lock_irq(&dev_priv->irq_lock);
1627 if (dev_priv->display.hpd_irq_setup)
91d14251 1628 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1629 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1630
d5818938 1631 intel_dp_mst_resume(dev);
e7d6f7d7 1632
a16b7658
L		 1633 intel_display_resume(dev);
1634
d5818938
DV		 1635 /*
1636 * ... but also need to make sure that hotplug processing
1637 * doesn't cause havoc. Like in the driver load code we don't
1638 * bother with the tiny race here where we might loose hotplug
1639 * notifications.
1640 * */
1641 intel_hpd_init(dev_priv);
1642 /* Config may have changed between suspend and resume */
1643 drm_helper_hpd_irq_event(dev);
1daed3fb 1644
03d92e47 1645 intel_opregion_register(dev_priv);
44834a67 1646
82e3b8c1 1647 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1648
b8efb17b
ZR		 1649 mutex_lock(&dev_priv->modeset_restore_lock);
1650 dev_priv->modeset_restore = MODESET_DONE;
1651 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1652
6f9f4b7a 1653 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1654
ee6f280e
ID		 1655 drm_kms_helper_poll_enable(dev);
1656
1f814dac
ID		 1657 enable_rpm_wakeref_asserts(dev_priv);
1658
074c6ada 1659 return 0;
84b79f8d
RW		 1660}
1661
5e365c39 1662static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1663{
fac5e23e 1664 struct drm_i915_private *dev_priv = to_i915(dev);
44410cd0 1665 int ret;
36d61e67 1666
76c4b250
ID		 1667 /*
1668 * We have a resume ordering issue with the snd-hda driver also
1669 * requiring our device to be power up. Due to the lack of a
1670 * parent/child relationship we currently solve this with an early
1671 * resume hook.
1672 *
1673 * FIXME: This should be solved with a special hdmi sink device or
1674 * similar so that power domains can be employed.
1675 */
44410cd0
ID		 1676
1677 /*
1678 * Note that we need to set the power state explicitly, since we
1679 * powered off the device during freeze and the PCI core won't power
1680 * it back up for us during thaw. Powering off the device during
1681 * freeze is not a hard requirement though, and during the
1682 * suspend/resume phases the PCI core makes sure we get here with the
1683 * device powered on. So in case we change our freeze logic and keep
1684 * the device powered we can also remove the following set power state
1685 * call.
1686 */
1687 ret = pci_set_power_state(dev->pdev, PCI_D0);
1688 if (ret) {
1689 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1690 goto out;
1691 }
1692
1693 /*
1694 * Note that pci_enable_device() first enables any parent bridge
1695 * device and only then sets the power state for this device. The
1696 * bridge enabling is a nop though, since bridge devices are resumed
1697 * first. The order of enabling power and enabling the device is
1698 * imposed by the PCI core as described above, so here we preserve the
1699 * same order for the freeze/thaw phases.
1700 *
1701 * TODO: eventually we should remove pci_disable_device() /
1702 * pci_enable_enable_device() from suspend/resume. Due to how they
1703 * depend on the device enable refcount we can't anyway depend on them
1704 * disabling/enabling the device.
1705 */
bc87229f
ID		 1706 if (pci_enable_device(dev->pdev)) {
1707 ret = -EIO;
1708 goto out;
1709 }
84b79f8d
RW		 1710
1711 pci_set_master(dev->pdev);
1712
1f814dac
ID		 1713 disable_rpm_wakeref_asserts(dev_priv);
1714
666a4537 1715 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1716 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1717 if (ret)
ff0b187f
DL		 1718 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1719 ret);
36d61e67 1720
dc97997a 1721 intel_uncore_early_sanitize(dev_priv, true);
efee833a 1722
dc97997a 1723 if (IS_BROXTON(dev_priv)) {
da2f41d1
ID		 1724 if (!dev_priv->suspended_to_idle)
1725 gen9_sanitize_dc_state(dev_priv);
507e126e 1726 bxt_disable_dc9(dev_priv);
da2f41d1 1727 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1728 hsw_disable_pc8(dev_priv);
da2f41d1 1729 }
efee833a 1730
dc97997a 1731 intel_uncore_sanitize(dev_priv);
bc87229f 1732
a7c8125f
ID		 1733 if (IS_BROXTON(dev_priv) ||
1734 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 1735 intel_power_domains_init_hw(dev_priv, true);
1736
6e35e8ab
ID		 1737 enable_rpm_wakeref_asserts(dev_priv);
1738
bc87229f
ID		 1739out:
1740 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1741
1742 return ret;
76c4b250
ID		 1743}
1744
1751fcf9 1745int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1746{
50a0072f 1747 int ret;
76c4b250 1748
097dd837
ID		 1749 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1750 return 0;
1751
5e365c39 1752 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1753 if (ret)
1754 return ret;
1755
5a17514e
ID		 1756 return i915_drm_resume(dev);
1757}
1758
11ed50ec 1759/**
f3953dcb 1760 * i915_reset - reset chip after a hang
11ed50ec 1761 * @dev: drm device to reset
11ed50ec
BG		 1762 *
1763 * Reset the chip. Useful if a hang is detected. Returns zero on successful
1764 * reset or otherwise an error code.
1765 *
1766 * Procedure is fairly simple:
1767 * - reset the chip using the reset reg
1768 * - re-init context state
1769 * - re-init hardware status page
1770 * - re-init ring buffer
1771 * - re-init interrupt state
1772 * - re-init display
1773 */
c033666a 1774int i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 1775{
91c8a326 1776 struct drm_device *dev = &dev_priv->drm;
d98c52cf
CW		 1777 struct i915_gpu_error *error = &dev_priv->gpu_error;
1778 unsigned reset_counter;
0573ed4a 1779 int ret;
11ed50ec 1780
dc97997a 1781 intel_reset_gt_powersave(dev_priv);
dbea3cea 1782
d54a02c0 1783 mutex_lock(&dev->struct_mutex);
11ed50ec 1784
d98c52cf
CW		 1785 /* Clear any previous failed attempts at recovery. Time to try again. */
1786 atomic_andnot(I915_WEDGED, &error->reset_counter);
77f01230 1787
d98c52cf
CW		 1788 /* Clear the reset-in-progress flag and increment the reset epoch. */
1789 reset_counter = atomic_inc_return(&error->reset_counter);
1790 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
1791 ret = -EIO;
1792 goto error;
1793 }
1794
7b4d3a16
CW		 1795 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1796
d98c52cf 1797 i915_gem_reset(dev);
2e7c8ee7 1798
dc97997a 1799 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
0573ed4a 1800 if (ret) {
804e59a8
CW		 1801 if (ret != -ENODEV)
1802 DRM_ERROR("Failed to reset chip: %i\n", ret);
1803 else
1804 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 1805 goto error;
11ed50ec
BG		 1806 }
1807
1362b776
VS		 1808 intel_overlay_reset(dev_priv);
1809
11ed50ec
BG		 1810 /* Ok, now get things going again... */
1811
1812 /*
1813 * Everything depends on having the GTT running, so we need to start
1814 * there. Fortunately we don't need to do this unless we reset the
1815 * chip at a PCI level.
1816 *
1817 * Next we need to restore the context, but we don't use those
1818 * yet either...
1819 *
1820 * Ring buffer needs to be re-initialized in the KMS case, or if X
1821 * was running at the time of the reset (i.e. we weren't VT
1822 * switched away).
1823 */
33d30a9c 1824 ret = i915_gem_init_hw(dev);
33d30a9c
DV		 1825 if (ret) {
1826 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1827 goto error;
11ed50ec
BG		 1828 }
1829
d98c52cf
CW		 1830 mutex_unlock(&dev->struct_mutex);
1831
33d30a9c
DV		 1832 /*
1833 * rps/rc6 re-init is necessary to restore state lost after the
1834 * reset and the re-install of gt irqs. Skip for ironlake per
1835 * previous concerns that it doesn't respond well to some forms
1836 * of re-init after reset.
1837 */
1838 if (INTEL_INFO(dev)->gen > 5)
dc97997a 1839 intel_enable_gt_powersave(dev_priv);
33d30a9c 1840
11ed50ec 1841 return 0;
d98c52cf
CW		 1842
1843error:
1844 atomic_or(I915_WEDGED, &error->reset_counter);
1845 mutex_unlock(&dev->struct_mutex);
1846 return ret;
11ed50ec
BG		 1847}
1848
84b79f8d 1849static int i915_pm_suspend(struct device *dev)
112b715e 1850{
84b79f8d
RW		 1851 struct pci_dev *pdev = to_pci_dev(dev);
1852 struct drm_device *drm_dev = pci_get_drvdata(pdev);
112b715e 1853
ded8b07d 1854 if (!drm_dev) {
84b79f8d
RW		 1855 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1856 return -ENODEV;
1857 }
112b715e 1858
5bcf719b
DA		 1859 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1860 return 0;
1861
5e365c39 1862 return i915_drm_suspend(drm_dev);
76c4b250
ID		 1863}
1864
1865static int i915_pm_suspend_late(struct device *dev)
1866{
91c8a326 1867 struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
76c4b250
ID		 1868
1869 /*
c965d995 1870 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 1871 * requiring our device to be power up. Due to the lack of a
1872 * parent/child relationship we currently solve this with an late
1873 * suspend hook.
1874 *
1875 * FIXME: This should be solved with a special hdmi sink device or
1876 * similar so that power domains can be employed.
1877 */
1878 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1879 return 0;
112b715e 1880
ab3be73f
ID		 1881 return i915_drm_suspend_late(drm_dev, false);
1882}
1883
1884static int i915_pm_poweroff_late(struct device *dev)
1885{
91c8a326 1886 struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
ab3be73f
ID		 1887
1888 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1889 return 0;
1890
1891 return i915_drm_suspend_late(drm_dev, true);
cbda12d7
ZW		 1892}
1893
76c4b250
ID		 1894static int i915_pm_resume_early(struct device *dev)
1895{
91c8a326 1896 struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
76c4b250 1897
097dd837
ID		 1898 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1899 return 0;
1900
5e365c39 1901 return i915_drm_resume_early(drm_dev);
76c4b250
ID		 1902}
1903
84b79f8d 1904static int i915_pm_resume(struct device *dev)
cbda12d7 1905{
91c8a326 1906 struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
84b79f8d 1907
097dd837
ID		 1908 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1909 return 0;
1910
5a17514e 1911 return i915_drm_resume(drm_dev);
cbda12d7
ZW		 1912}
1913
1f19ac2a
CW		 1914/* freeze: before creating the hibernation_image */
1915static int i915_pm_freeze(struct device *dev)
1916{
1917 return i915_pm_suspend(dev);
1918}
1919
1920static int i915_pm_freeze_late(struct device *dev)
1921{
461fb99c
CW		 1922 int ret;
1923
1924 ret = i915_pm_suspend_late(dev);
1925 if (ret)
1926 return ret;
1927
1928 ret = i915_gem_freeze_late(dev_to_i915(dev));
1929 if (ret)
1930 return ret;
1931
1932 return 0;
1f19ac2a
CW		 1933}
1934
1935/* thaw: called after creating the hibernation image, but before turning off. */
1936static int i915_pm_thaw_early(struct device *dev)
1937{
1938 return i915_pm_resume_early(dev);
1939}
1940
1941static int i915_pm_thaw(struct device *dev)
1942{
1943 return i915_pm_resume(dev);
1944}
1945
1946/* restore: called after loading the hibernation image. */
1947static int i915_pm_restore_early(struct device *dev)
1948{
1949 return i915_pm_resume_early(dev);
1950}
1951
1952static int i915_pm_restore(struct device *dev)
1953{
1954 return i915_pm_resume(dev);
1955}
1956
ddeea5b0
ID		 1957/*
1958 * Save all Gunit registers that may be lost after a D3 and a subsequent
1959 * S0i[R123] transition. The list of registers needing a save/restore is
1960 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1961 * registers in the following way:
1962 * - Driver: saved/restored by the driver
1963 * - Punit : saved/restored by the Punit firmware
1964 * - No, w/o marking: no need to save/restore, since the register is R/O or
1965 * used internally by the HW in a way that doesn't depend
1966 * keeping the content across a suspend/resume.
1967 * - Debug : used for debugging
1968 *
1969 * We save/restore all registers marked with 'Driver', with the following
1970 * exceptions:
1971 * - Registers out of use, including also registers marked with 'Debug'.
1972 * These have no effect on the driver's operation, so we don't save/restore
1973 * them to reduce the overhead.
1974 * - Registers that are fully setup by an initialization function called from
1975 * the resume path. For example many clock gating and RPS/RC6 registers.
1976 * - Registers that provide the right functionality with their reset defaults.
1977 *
1978 * TODO: Except for registers that based on the above 3 criteria can be safely
1979 * ignored, we save/restore all others, practically treating the HW context as
1980 * a black-box for the driver. Further investigation is needed to reduce the
1981 * saved/restored registers even further, by following the same 3 criteria.
1982 */
1983static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1984{
1985 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1986 int i;
1987
1988 /* GAM 0x4000-0x4770 */
1989 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1990 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1991 s->arb_mode = I915_READ(ARB_MODE);
1992 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1993 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1994
1995 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 1996 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 1997
1998 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 1999 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 2000
2001 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2002 s->ecochk = I915_READ(GAM_ECOCHK);
2003 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2004 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2005
2006 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2007
2008 /* MBC 0x9024-0x91D0, 0x8500 */
2009 s->g3dctl = I915_READ(VLV_G3DCTL);
2010 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2011 s->mbctl = I915_READ(GEN6_MBCTL);
2012
2013 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2014 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2015 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2016 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2017 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2018 s->rstctl = I915_READ(GEN6_RSTCTL);
2019 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2020
2021 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2022 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2023 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2024 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2025 s->ecobus = I915_READ(ECOBUS);
2026 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2027 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2028 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2029 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2030 s->rcedata = I915_READ(VLV_RCEDATA);
2031 s->spare2gh = I915_READ(VLV_SPAREG2H);
2032
2033 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2034 s->gt_imr = I915_READ(GTIMR);
2035 s->gt_ier = I915_READ(GTIER);
2036 s->pm_imr = I915_READ(GEN6_PMIMR);
2037 s->pm_ier = I915_READ(GEN6_PMIER);
2038
2039 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2040 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2041
2042 /* GT SA CZ domain, 0x100000-0x138124 */
2043 s->tilectl = I915_READ(TILECTL);
2044 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2045 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2046 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2047 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2048
2049 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2050 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2051 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2052 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2053 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2054
2055 /*
2056 * Not saving any of:
2057 * DFT, 0x9800-0x9EC0
2058 * SARB, 0xB000-0xB1FC
2059 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2060 * PCI CFG
2061 */
2062}
2063
2064static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2065{
2066 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2067 u32 val;
2068 int i;
2069
2070 /* GAM 0x4000-0x4770 */
2071 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2072 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2073 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2074 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2075 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2076
2077 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2078 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2079
2080 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2081 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2082
2083 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2084 I915_WRITE(GAM_ECOCHK, s->ecochk);
2085 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2086 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2087
2088 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2089
2090 /* MBC 0x9024-0x91D0, 0x8500 */
2091 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2092 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2093 I915_WRITE(GEN6_MBCTL, s->mbctl);
2094
2095 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2096 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2097 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2098 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2099 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2100 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2101 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2102
2103 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2104 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2105 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2106 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2107 I915_WRITE(ECOBUS, s->ecobus);
2108 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2109 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2110 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2111 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2112 I915_WRITE(VLV_RCEDATA, s->rcedata);
2113 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2114
2115 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2116 I915_WRITE(GTIMR, s->gt_imr);
2117 I915_WRITE(GTIER, s->gt_ier);
2118 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2119 I915_WRITE(GEN6_PMIER, s->pm_ier);
2120
2121 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2122 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2123
2124 /* GT SA CZ domain, 0x100000-0x138124 */
2125 I915_WRITE(TILECTL, s->tilectl);
2126 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2127 /*
2128 * Preserve the GT allow wake and GFX force clock bit, they are not
2129 * be restored, as they are used to control the s0ix suspend/resume
2130 * sequence by the caller.
2131 */
2132 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2133 val &= VLV_GTLC_ALLOWWAKEREQ;
2134 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2135 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2136
2137 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2138 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2139 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2140 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2141
2142 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2143
2144 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2145 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2146 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2147 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2148 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2149}
2150
650ad970
ID		 2151int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2152{
2153 u32 val;
2154 int err;
2155
650ad970
ID		 2156 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2157 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2158 if (force_on)
2159 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2160 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2161
2162 if (!force_on)
2163 return 0;
2164
c6ddc5f3
CW		 2165 err = intel_wait_for_register(dev_priv,
2166 VLV_GTLC_SURVIVABILITY_REG,
2167 VLV_GFX_CLK_STATUS_BIT,
2168 VLV_GFX_CLK_STATUS_BIT,
2169 20);
650ad970
ID		 2170 if (err)
2171 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2172 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2173
2174 return err;
650ad970
ID		 2175}
2176
ddeea5b0
ID		 2177static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2178{
2179 u32 val;
2180 int err = 0;
2181
2182 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2183 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2184 if (allow)
2185 val |= VLV_GTLC_ALLOWWAKEREQ;
2186 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2187 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2188
b2736695
CW		 2189 err = intel_wait_for_register(dev_priv,
2190 VLV_GTLC_PW_STATUS,
2191 VLV_GTLC_ALLOWWAKEACK,
2192 allow,
2193 1);
ddeea5b0
ID		 2194 if (err)
2195 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2196
ddeea5b0 2197 return err;
ddeea5b0
ID		 2198}
2199
2200static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2201 bool wait_for_on)
2202{
2203 u32 mask;
2204 u32 val;
2205 int err;
2206
2207 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2208 val = wait_for_on ? mask : 0;
41ce405e 2209 if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
ddeea5b0
ID		 2210 return 0;
2211
2212 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
87ad3212
JN		 2213 onoff(wait_for_on),
2214 I915_READ(VLV_GTLC_PW_STATUS));
ddeea5b0
ID		 2215
2216 /*
2217 * RC6 transitioning can be delayed up to 2 msec (see
2218 * valleyview_enable_rps), use 3 msec for safety.
2219 */
41ce405e
CW		 2220 err = intel_wait_for_register(dev_priv,
2221 VLV_GTLC_PW_STATUS, mask, val,
2222 3);
ddeea5b0
ID		 2223 if (err)
2224 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2225 onoff(wait_for_on));
ddeea5b0
ID		 2226
2227 return err;
ddeea5b0
ID		 2228}
2229
2230static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2231{
2232 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2233 return;
2234
6fa283b0 2235 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2236 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2237}
2238
ebc32824 2239static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2240{
2241 u32 mask;
2242 int err;
2243
2244 /*
2245 * Bspec defines the following GT well on flags as debug only, so
2246 * don't treat them as hard failures.
2247 */
2248 (void)vlv_wait_for_gt_wells(dev_priv, false);
2249
2250 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2251 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2252
2253 vlv_check_no_gt_access(dev_priv);
2254
2255 err = vlv_force_gfx_clock(dev_priv, true);
2256 if (err)
2257 goto err1;
2258
2259 err = vlv_allow_gt_wake(dev_priv, false);
2260 if (err)
2261 goto err2;
98711167 2262
2d1fe073 2263 if (!IS_CHERRYVIEW(dev_priv))
98711167 2264 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2265
2266 err = vlv_force_gfx_clock(dev_priv, false);
2267 if (err)
2268 goto err2;
2269
2270 return 0;
2271
2272err2:
2273 /* For safety always re-enable waking and disable gfx clock forcing */
2274 vlv_allow_gt_wake(dev_priv, true);
2275err1:
2276 vlv_force_gfx_clock(dev_priv, false);
2277
2278 return err;
2279}
2280
016970be
SK		 2281static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2282 bool rpm_resume)
ddeea5b0 2283{
91c8a326 2284 struct drm_device *dev = &dev_priv->drm;
ddeea5b0
ID		 2285 int err;
2286 int ret;
2287
2288 /*
2289 * If any of the steps fail just try to continue, that's the best we
2290 * can do at this point. Return the first error code (which will also
2291 * leave RPM permanently disabled).
2292 */
2293 ret = vlv_force_gfx_clock(dev_priv, true);
2294
2d1fe073 2295 if (!IS_CHERRYVIEW(dev_priv))
98711167 2296 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2297
2298 err = vlv_allow_gt_wake(dev_priv, true);
2299 if (!ret)
2300 ret = err;
2301
2302 err = vlv_force_gfx_clock(dev_priv, false);
2303 if (!ret)
2304 ret = err;
2305
2306 vlv_check_no_gt_access(dev_priv);
2307
016970be
SK		 2308 if (rpm_resume) {
2309 intel_init_clock_gating(dev);
2310 i915_gem_restore_fences(dev);
2311 }
ddeea5b0
ID		 2312
2313 return ret;
2314}
2315
97bea207 2316static int intel_runtime_suspend(struct device *device)
8a187455
PZ		 2317{
2318 struct pci_dev *pdev = to_pci_dev(device);
2319 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2320 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2321 int ret;
8a187455 2322
dc97997a 2323 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2324 return -ENODEV;
2325
604effb7
ID		 2326 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2327 return -ENODEV;
2328
8a187455
PZ		 2329 DRM_DEBUG_KMS("Suspending device\n");
2330
d6102977
ID		 2331 /*
2332 * We could deadlock here in case another thread holding struct_mutex
2333 * calls RPM suspend concurrently, since the RPM suspend will wait
2334 * first for this RPM suspend to finish. In this case the concurrent
2335 * RPM resume will be followed by its RPM suspend counterpart. Still
2336 * for consistency return -EAGAIN, which will reschedule this suspend.
2337 */
2338 if (!mutex_trylock(&dev->struct_mutex)) {
2339 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2340 /*
2341 * Bump the expiration timestamp, otherwise the suspend won't
2342 * be rescheduled.
2343 */
2344 pm_runtime_mark_last_busy(device);
2345
2346 return -EAGAIN;
2347 }
1f814dac
ID		 2348
2349 disable_rpm_wakeref_asserts(dev_priv);
2350
d6102977
ID		 2351 /*
2352 * We are safe here against re-faults, since the fault handler takes
2353 * an RPM reference.
2354 */
2355 i915_gem_release_all_mmaps(dev_priv);
2356 mutex_unlock(&dev->struct_mutex);
2357
a1c41994
AD		 2358 intel_guc_suspend(dev);
2359
2eb5252e 2360 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2361
507e126e
ID		 2362 ret = 0;
2363 if (IS_BROXTON(dev_priv)) {
2364 bxt_display_core_uninit(dev_priv);
2365 bxt_enable_dc9(dev_priv);
2366 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2367 hsw_enable_pc8(dev_priv);
2368 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2369 ret = vlv_suspend_complete(dev_priv);
2370 }
2371
0ab9cfeb
ID		 2372 if (ret) {
2373 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2374 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2375
1f814dac
ID		 2376 enable_rpm_wakeref_asserts(dev_priv);
2377
0ab9cfeb
ID		 2378 return ret;
2379 }
a8a8bd54 2380
dc97997a 2381 intel_uncore_forcewake_reset(dev_priv, false);
1f814dac
ID		 2382
2383 enable_rpm_wakeref_asserts(dev_priv);
2384 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2385
bc3b9346 2386 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2387 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2388
8a187455 2389 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2390
2391 /*
c8a0bd42
PZ		 2392 * FIXME: We really should find a document that references the arguments
2393 * used below!
1fb2362b 2394 */
6f9f4b7a 2395 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2396 /*
2397 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2398 * being detected, and the call we do at intel_runtime_resume()
2399 * won't be able to restore them. Since PCI_D3hot matches the
2400 * actual specification and appears to be working, use it.
2401 */
6f9f4b7a 2402 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2403 } else {
c8a0bd42
PZ		 2404 /*
2405 * current versions of firmware which depend on this opregion
2406 * notification have repurposed the D1 definition to mean
2407 * "runtime suspended" vs. what you would normally expect (D3)
2408 * to distinguish it from notifications that might be sent via
2409 * the suspend path.
2410 */
6f9f4b7a 2411 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2412 }
8a187455 2413
59bad947 2414 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2415
a8a8bd54 2416 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2417 return 0;
2418}
2419
97bea207 2420static int intel_runtime_resume(struct device *device)
8a187455
PZ		 2421{
2422 struct pci_dev *pdev = to_pci_dev(device);
2423 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2424 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2425 int ret = 0;
8a187455 2426
604effb7
ID		 2427 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2428 return -ENODEV;
8a187455
PZ		 2429
2430 DRM_DEBUG_KMS("Resuming device\n");
2431
1f814dac
ID		 2432 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2433 disable_rpm_wakeref_asserts(dev_priv);
2434
6f9f4b7a 2435 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2436 dev_priv->pm.suspended = false;
55ec45c2
MK		 2437 if (intel_uncore_unclaimed_mmio(dev_priv))
2438 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2439
a1c41994
AD		 2440 intel_guc_resume(dev);
2441
1a5df187
PZ		 2442 if (IS_GEN6(dev_priv))
2443 intel_init_pch_refclk(dev);
31335cec 2444
507e126e
ID		 2445 if (IS_BROXTON(dev)) {
2446 bxt_disable_dc9(dev_priv);
2447 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2448 if (dev_priv->csr.dmc_payload &&
2449 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2450 gen9_enable_dc5(dev_priv);
507e126e 2451 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2452 hsw_disable_pc8(dev_priv);
507e126e 2453 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2454 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2455 }
1a5df187 2456
0ab9cfeb
ID		 2457 /*
2458 * No point of rolling back things in case of an error, as the best
2459 * we can do is to hope that things will still work (and disable RPM).
2460 */
92b806d3 2461 i915_gem_init_swizzling(dev);
dc97997a 2462 gen6_update_ring_freq(dev_priv);
92b806d3 2463
b963291c 2464 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2465
2466 /*
2467 * On VLV/CHV display interrupts are part of the display
2468 * power well, so hpd is reinitialized from there. For
2469 * everyone else do it here.
2470 */
666a4537 2471 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2472 intel_hpd_init(dev_priv);
2473
1f814dac
ID		 2474 enable_rpm_wakeref_asserts(dev_priv);
2475
0ab9cfeb
ID		 2476 if (ret)
2477 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2478 else
2479 DRM_DEBUG_KMS("Device resumed\n");
2480
2481 return ret;
8a187455
PZ		 2482}
2483
42f5551d 2484const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2485 /*
2486 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2487 * PMSG_RESUME]
2488 */
0206e353 2489 .suspend = i915_pm_suspend,
76c4b250
ID		 2490 .suspend_late = i915_pm_suspend_late,
2491 .resume_early = i915_pm_resume_early,
0206e353 2492 .resume = i915_pm_resume,
5545dbbf
ID		 2493
2494 /*
2495 * S4 event handlers
2496 * @freeze, @freeze_late : called (1) before creating the
2497 * hibernation image [PMSG_FREEZE] and
2498 * (2) after rebooting, before restoring
2499 * the image [PMSG_QUIESCE]
2500 * @thaw, @thaw_early : called (1) after creating the hibernation
2501 * image, before writing it [PMSG_THAW]
2502 * and (2) after failing to create or
2503 * restore the image [PMSG_RECOVER]
2504 * @poweroff, @poweroff_late: called after writing the hibernation
2505 * image, before rebooting [PMSG_HIBERNATE]
2506 * @restore, @restore_early : called after rebooting and restoring the
2507 * hibernation image [PMSG_RESTORE]
2508 */
1f19ac2a
CW		 2509 .freeze = i915_pm_freeze,
2510 .freeze_late = i915_pm_freeze_late,
2511 .thaw_early = i915_pm_thaw_early,
2512 .thaw = i915_pm_thaw,
36d61e67 2513 .poweroff = i915_pm_suspend,
ab3be73f 2514 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2515 .restore_early = i915_pm_restore_early,
2516 .restore = i915_pm_restore,
5545dbbf
ID		 2517
2518 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2519 .runtime_suspend = intel_runtime_suspend,
2520 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2521};
2522
78b68556 2523static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2524 .fault = i915_gem_fault,
ab00b3e5
JB		 2525 .open = drm_gem_vm_open,
2526 .close = drm_gem_vm_close,
de151cf6
JB		 2527};
2528
e08e96de
AV		 2529static const struct file_operations i915_driver_fops = {
2530 .owner = THIS_MODULE,
2531 .open = drm_open,
2532 .release = drm_release,
2533 .unlocked_ioctl = drm_ioctl,
2534 .mmap = drm_gem_mmap,
2535 .poll = drm_poll,
e08e96de
AV		 2536 .read = drm_read,
2537#ifdef CONFIG_COMPAT
2538 .compat_ioctl = i915_compat_ioctl,
2539#endif
2540 .llseek = noop_llseek,
2541};
2542
0673ad47
CW		 2543static int
2544i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2545 struct drm_file *file)
2546{
2547 return -ENODEV;
2548}
2549
2550static const struct drm_ioctl_desc i915_ioctls[] = {
2551 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2552 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2553 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2554 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2555 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2556 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2557 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2558 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2559 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2560 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2561 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2562 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2563 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2564 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2565 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2566 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2567 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2568 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2569 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2570 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2571 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2572 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2573 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2574 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2575 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2576 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2577 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2578 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2579 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2580 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2581 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2582 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2583 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2584 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2585 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2586 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2587 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2588 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2589 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2590 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2591 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2592 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2593 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2594 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2595 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2596 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2597 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2598 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2599 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2600 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2601 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2602 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2603};
2604
1da177e4 2605static struct drm_driver driver = {
0c54781b
MW		 2606 /* Don't use MTRRs here; the Xserver or userspace app should
2607 * deal with them for Intel hardware.
792d2b9a 2608 */
673a394b 2609 .driver_features =
10ba5012 2610 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1751fcf9 2611 DRIVER_RENDER | DRIVER_MODESET,
673a394b 2612 .open = i915_driver_open,
22eae947
DA		 2613 .lastclose = i915_driver_lastclose,
2614 .preclose = i915_driver_preclose,
673a394b 2615 .postclose = i915_driver_postclose,
915b4d11 2616 .set_busid = drm_pci_set_busid,
d8e29209 2617
673a394b 2618 .gem_free_object = i915_gem_free_object,
de151cf6 2619 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2620
2621 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2622 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2623 .gem_prime_export = i915_gem_prime_export,
2624 .gem_prime_import = i915_gem_prime_import,
2625
ff72145b 2626 .dumb_create = i915_gem_dumb_create,
da6b51d0 2627 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 2628 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 2629 .ioctls = i915_ioctls,
0673ad47 2630 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2631 .fops = &i915_driver_fops,
22eae947
DA		 2632 .name = DRIVER_NAME,
2633 .desc = DRIVER_DESC,
2634 .date = DRIVER_DATE,
2635 .major = DRIVER_MAJOR,
2636 .minor = DRIVER_MINOR,
2637 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2638};
ubuntu-bionic-kernel mirror