]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
112b715e KH |
41 | static struct drm_driver driver; |
42 | ||
a57c774a AK |
43 | #define GEN_DEFAULT_PIPEOFFSETS \ |
44 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
45 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
46 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
47 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
48 | .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \ | |
49 | .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \ | |
50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } | |
51 | ||
52 | ||
9a7e8492 | 53 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 54 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 55 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 56 | .ring_mask = RENDER_RING, |
a57c774a | 57 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
58 | }; |
59 | ||
9a7e8492 | 60 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 61 | .gen = 2, .num_pipes = 1, |
31578148 | 62 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 63 | .ring_mask = RENDER_RING, |
a57c774a | 64 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
65 | }; |
66 | ||
9a7e8492 | 67 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 68 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 69 | .cursor_needs_physical = 1, |
31578148 | 70 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 71 | .has_fbc = 1, |
73ae478c | 72 | .ring_mask = RENDER_RING, |
a57c774a | 73 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
74 | }; |
75 | ||
9a7e8492 | 76 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 77 | .gen = 2, .num_pipes = 1, |
31578148 | 78 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 79 | .ring_mask = RENDER_RING, |
a57c774a | 80 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
81 | }; |
82 | ||
9a7e8492 | 83 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 84 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 85 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 86 | .ring_mask = RENDER_RING, |
a57c774a | 87 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 | 88 | }; |
9a7e8492 | 89 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 90 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 91 | .cursor_needs_physical = 1, |
31578148 | 92 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 93 | .supports_tv = 1, |
fd70d52a | 94 | .has_fbc = 1, |
73ae478c | 95 | .ring_mask = RENDER_RING, |
a57c774a | 96 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 | 97 | }; |
9a7e8492 | 98 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 99 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 100 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 101 | .ring_mask = RENDER_RING, |
a57c774a | 102 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 | 103 | }; |
9a7e8492 | 104 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 105 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 106 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 107 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 108 | .supports_tv = 1, |
fd70d52a | 109 | .has_fbc = 1, |
73ae478c | 110 | .ring_mask = RENDER_RING, |
a57c774a | 111 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
112 | }; |
113 | ||
9a7e8492 | 114 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 115 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 116 | .has_hotplug = 1, |
31578148 | 117 | .has_overlay = 1, |
73ae478c | 118 | .ring_mask = RENDER_RING, |
a57c774a | 119 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
120 | }; |
121 | ||
9a7e8492 | 122 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 123 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 124 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 125 | .has_overlay = 1, |
a6c45cf0 | 126 | .supports_tv = 1, |
73ae478c | 127 | .ring_mask = RENDER_RING, |
a57c774a | 128 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
129 | }; |
130 | ||
9a7e8492 | 131 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 132 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 133 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 134 | .has_overlay = 1, |
73ae478c | 135 | .ring_mask = RENDER_RING, |
a57c774a | 136 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
137 | }; |
138 | ||
9a7e8492 | 139 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 140 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 141 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 142 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 143 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
144 | }; |
145 | ||
9a7e8492 | 146 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 147 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 148 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 149 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 150 | .supports_tv = 1, |
73ae478c | 151 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 152 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
153 | }; |
154 | ||
9a7e8492 | 155 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 156 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 157 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 158 | .has_overlay = 1, |
a57c774a | 159 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
160 | }; |
161 | ||
9a7e8492 | 162 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 163 | .gen = 5, .num_pipes = 2, |
5a117db7 | 164 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 165 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 166 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
167 | }; |
168 | ||
9a7e8492 | 169 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 170 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 171 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 172 | .has_fbc = 1, |
73ae478c | 173 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 174 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
175 | }; |
176 | ||
9a7e8492 | 177 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 178 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 179 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 180 | .has_fbc = 1, |
73ae478c | 181 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 182 | .has_llc = 1, |
a57c774a | 183 | GEN_DEFAULT_PIPEOFFSETS, |
f6e450a6 EA |
184 | }; |
185 | ||
9a7e8492 | 186 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 187 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 188 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 189 | .has_fbc = 1, |
73ae478c | 190 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 191 | .has_llc = 1, |
a57c774a | 192 | GEN_DEFAULT_PIPEOFFSETS, |
a13e4093 EA |
193 | }; |
194 | ||
219f4fdb BW |
195 | #define GEN7_FEATURES \ |
196 | .gen = 7, .num_pipes = 3, \ | |
197 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 198 | .has_fbc = 1, \ |
73ae478c | 199 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 200 | .has_llc = 1 |
219f4fdb | 201 | |
c76b615c | 202 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
203 | GEN7_FEATURES, |
204 | .is_ivybridge = 1, | |
a57c774a | 205 | GEN_DEFAULT_PIPEOFFSETS, |
c76b615c JB |
206 | }; |
207 | ||
208 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
209 | GEN7_FEATURES, |
210 | .is_ivybridge = 1, | |
211 | .is_mobile = 1, | |
a57c774a | 212 | GEN_DEFAULT_PIPEOFFSETS, |
c76b615c JB |
213 | }; |
214 | ||
999bcdea BW |
215 | static const struct intel_device_info intel_ivybridge_q_info = { |
216 | GEN7_FEATURES, | |
217 | .is_ivybridge = 1, | |
218 | .num_pipes = 0, /* legal, last one wins */ | |
a57c774a | 219 | GEN_DEFAULT_PIPEOFFSETS, |
999bcdea BW |
220 | }; |
221 | ||
70a3eb7a | 222 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
223 | GEN7_FEATURES, |
224 | .is_mobile = 1, | |
225 | .num_pipes = 2, | |
70a3eb7a | 226 | .is_valleyview = 1, |
fba5d532 | 227 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 228 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 229 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 230 | GEN_DEFAULT_PIPEOFFSETS, |
70a3eb7a JB |
231 | }; |
232 | ||
233 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
234 | GEN7_FEATURES, |
235 | .num_pipes = 2, | |
70a3eb7a | 236 | .is_valleyview = 1, |
fba5d532 | 237 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 238 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 239 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 240 | GEN_DEFAULT_PIPEOFFSETS, |
70a3eb7a JB |
241 | }; |
242 | ||
4cae9ae0 | 243 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
244 | GEN7_FEATURES, |
245 | .is_haswell = 1, | |
dd93be58 | 246 | .has_ddi = 1, |
30568c45 | 247 | .has_fpga_dbg = 1, |
73ae478c | 248 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 249 | GEN_DEFAULT_PIPEOFFSETS, |
4cae9ae0 ED |
250 | }; |
251 | ||
252 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
253 | GEN7_FEATURES, |
254 | .is_haswell = 1, | |
255 | .is_mobile = 1, | |
dd93be58 | 256 | .has_ddi = 1, |
30568c45 | 257 | .has_fpga_dbg = 1, |
73ae478c | 258 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 259 | GEN_DEFAULT_PIPEOFFSETS, |
c76b615c JB |
260 | }; |
261 | ||
4d4dead6 | 262 | static const struct intel_device_info intel_broadwell_d_info = { |
4b30553d | 263 | .gen = 8, .num_pipes = 3, |
4d4dead6 BW |
264 | .need_gfx_hws = 1, .has_hotplug = 1, |
265 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
266 | .has_llc = 1, | |
267 | .has_ddi = 1, | |
8f94d24b | 268 | .has_fbc = 1, |
a57c774a | 269 | GEN_DEFAULT_PIPEOFFSETS, |
4d4dead6 BW |
270 | }; |
271 | ||
272 | static const struct intel_device_info intel_broadwell_m_info = { | |
4b30553d | 273 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
4d4dead6 BW |
274 | .need_gfx_hws = 1, .has_hotplug = 1, |
275 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
276 | .has_llc = 1, | |
277 | .has_ddi = 1, | |
8f94d24b | 278 | .has_fbc = 1, |
a57c774a | 279 | GEN_DEFAULT_PIPEOFFSETS, |
4d4dead6 BW |
280 | }; |
281 | ||
a0a18075 JB |
282 | /* |
283 | * Make sure any device matches here are from most specific to most | |
284 | * general. For example, since the Quanta match is based on the subsystem | |
285 | * and subvendor IDs, we need it to come before the more general IVB | |
286 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
287 | */ | |
288 | #define INTEL_PCI_IDS \ | |
289 | INTEL_I830_IDS(&intel_i830_info), \ | |
290 | INTEL_I845G_IDS(&intel_845g_info), \ | |
291 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
292 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
293 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
294 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
295 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
296 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
297 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
298 | INTEL_G33_IDS(&intel_g33_info), \ | |
299 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
300 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
301 | INTEL_G45_IDS(&intel_g45_info), \ | |
302 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
303 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
304 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
305 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
306 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
307 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
308 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
309 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
310 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
311 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
312 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
4d4dead6 BW |
313 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ |
314 | INTEL_BDW_M_IDS(&intel_broadwell_m_info), \ | |
315 | INTEL_BDW_D_IDS(&intel_broadwell_d_info) | |
a0a18075 | 316 | |
6103da0d | 317 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 318 | INTEL_PCI_IDS, |
49ae35f2 | 319 | {0, 0, 0} |
1da177e4 LT |
320 | }; |
321 | ||
79e53945 JB |
322 | #if defined(CONFIG_DRM_I915_KMS) |
323 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
324 | #endif | |
325 | ||
0206e353 | 326 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
327 | { |
328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 329 | struct pci_dev *pch = NULL; |
3bad0781 | 330 | |
ce1bb329 BW |
331 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
332 | * (which really amounts to a PCH but no South Display). | |
333 | */ | |
334 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
335 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
336 | return; |
337 | } | |
338 | ||
3bad0781 ZW |
339 | /* |
340 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
341 | * make graphics device passthrough work easy for VMM, that only | |
342 | * need to expose ISA bridge to let driver know the real hardware | |
343 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
344 | * |
345 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
346 | * ISA bridge in the system. To work reliably, we should scan trhough | |
347 | * all the ISA bridge devices and check for the first match, instead | |
348 | * of only checking the first one. | |
3bad0781 | 349 | */ |
bcdb72ac | 350 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 351 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 352 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 353 | dev_priv->pch_id = id; |
3bad0781 | 354 | |
90711d50 JB |
355 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
356 | dev_priv->pch_type = PCH_IBX; | |
357 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 358 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 359 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
360 | dev_priv->pch_type = PCH_CPT; |
361 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 362 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
363 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
364 | /* PantherPoint is CPT compatible */ | |
365 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 366 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 367 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
368 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
369 | dev_priv->pch_type = PCH_LPT; | |
370 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 371 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 372 | WARN_ON(IS_ULT(dev)); |
018f52c9 PZ |
373 | } else if (IS_BROADWELL(dev)) { |
374 | dev_priv->pch_type = PCH_LPT; | |
375 | dev_priv->pch_id = | |
376 | INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
377 | DRM_DEBUG_KMS("This is Broadwell, assuming " | |
378 | "LynxPoint LP PCH\n"); | |
e76e0634 BW |
379 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
380 | dev_priv->pch_type = PCH_LPT; | |
381 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
382 | WARN_ON(!IS_HASWELL(dev)); | |
383 | WARN_ON(!IS_ULT(dev)); | |
bcdb72ac ID |
384 | } else |
385 | continue; | |
386 | ||
6a9c4b35 | 387 | break; |
3bad0781 | 388 | } |
3bad0781 | 389 | } |
6a9c4b35 | 390 | if (!pch) |
bcdb72ac ID |
391 | DRM_DEBUG_KMS("No PCH found.\n"); |
392 | ||
393 | pci_dev_put(pch); | |
3bad0781 ZW |
394 | } |
395 | ||
2911a35b BW |
396 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
397 | { | |
398 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 399 | return false; |
2911a35b | 400 | |
d330a953 JN |
401 | if (i915.semaphores >= 0) |
402 | return i915.semaphores; | |
2911a35b | 403 | |
c923facd JN |
404 | /* Until we get further testing... */ |
405 | if (IS_GEN8(dev)) | |
406 | return false; | |
407 | ||
59de3295 | 408 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 409 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
410 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
411 | return false; | |
412 | #endif | |
2911a35b | 413 | |
a08acaf2 | 414 | return true; |
2911a35b BW |
415 | } |
416 | ||
84b79f8d | 417 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 418 | { |
61caf87c | 419 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 420 | struct drm_crtc *crtc; |
61caf87c | 421 | |
8a187455 PZ |
422 | intel_runtime_pm_get(dev_priv); |
423 | ||
b8efb17b ZR |
424 | /* ignore lid events during suspend */ |
425 | mutex_lock(&dev_priv->modeset_restore_lock); | |
426 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
427 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
428 | ||
c67a470b PZ |
429 | /* We do a lot of poking in a lot of registers, make sure they work |
430 | * properly. */ | |
da7e29bd | 431 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 432 | |
5bcf719b DA |
433 | drm_kms_helper_poll_disable(dev); |
434 | ||
ba8bbcf6 | 435 | pci_save_state(dev->pdev); |
ba8bbcf6 | 436 | |
5669fcac | 437 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 438 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
439 | int error; |
440 | ||
45c5f202 | 441 | error = i915_gem_suspend(dev); |
84b79f8d | 442 | if (error) { |
226485e9 | 443 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
444 | "GEM idle failed, resume might fail\n"); |
445 | return error; | |
446 | } | |
a261b246 | 447 | |
1a01ab3b JB |
448 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
449 | ||
226485e9 | 450 | drm_irq_uninstall(dev); |
15239099 | 451 | dev_priv->enable_hotplug_processing = false; |
24576d23 JB |
452 | /* |
453 | * Disable CRTCs directly since we want to preserve sw state | |
454 | * for _thaw. | |
455 | */ | |
7c063c72 | 456 | mutex_lock(&dev->mode_config.mutex); |
24576d23 JB |
457 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
458 | dev_priv->display.crtc_disable(crtc); | |
7c063c72 | 459 | mutex_unlock(&dev->mode_config.mutex); |
7d708ee4 ID |
460 | |
461 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
462 | } |
463 | ||
828c7908 BW |
464 | i915_gem_suspend_gtt_mappings(dev); |
465 | ||
9e06dd39 JB |
466 | i915_save_state(dev); |
467 | ||
44834a67 | 468 | intel_opregion_fini(dev); |
28d85cd3 | 469 | intel_uncore_fini(dev); |
8ee1c3db | 470 | |
3fa016a0 | 471 | console_lock(); |
b6f3eff7 | 472 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
473 | console_unlock(); |
474 | ||
62d5d69b MK |
475 | dev_priv->suspend_count++; |
476 | ||
61caf87c | 477 | return 0; |
84b79f8d RW |
478 | } |
479 | ||
6a9ee8af | 480 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
481 | { |
482 | int error; | |
483 | ||
484 | if (!dev || !dev->dev_private) { | |
485 | DRM_ERROR("dev: %p\n", dev); | |
486 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
487 | return -ENODEV; | |
488 | } | |
489 | ||
490 | if (state.event == PM_EVENT_PRETHAW) | |
491 | return 0; | |
492 | ||
5bcf719b DA |
493 | |
494 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
495 | return 0; | |
6eecba33 | 496 | |
84b79f8d RW |
497 | error = i915_drm_freeze(dev); |
498 | if (error) | |
499 | return error; | |
500 | ||
b932ccb5 DA |
501 | if (state.event == PM_EVENT_SUSPEND) { |
502 | /* Shut down the device */ | |
503 | pci_disable_device(dev->pdev); | |
504 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
505 | } | |
ba8bbcf6 JB |
506 | |
507 | return 0; | |
508 | } | |
509 | ||
073f34d9 JB |
510 | void intel_console_resume(struct work_struct *work) |
511 | { | |
512 | struct drm_i915_private *dev_priv = | |
513 | container_of(work, struct drm_i915_private, | |
514 | console_resume_work); | |
515 | struct drm_device *dev = dev_priv->dev; | |
516 | ||
517 | console_lock(); | |
b6f3eff7 | 518 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
519 | console_unlock(); |
520 | } | |
521 | ||
bb60b969 JB |
522 | static void intel_resume_hotplug(struct drm_device *dev) |
523 | { | |
524 | struct drm_mode_config *mode_config = &dev->mode_config; | |
525 | struct intel_encoder *encoder; | |
526 | ||
527 | mutex_lock(&mode_config->mutex); | |
528 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); | |
529 | ||
530 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
531 | if (encoder->hot_plug) | |
532 | encoder->hot_plug(encoder); | |
533 | ||
534 | mutex_unlock(&mode_config->mutex); | |
535 | ||
536 | /* Just fire off a uevent and let userspace tell us what to do */ | |
537 | drm_helper_hpd_irq_event(dev); | |
538 | } | |
539 | ||
9d49c0ef | 540 | static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) |
ba8bbcf6 | 541 | { |
5669fcac | 542 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 543 | int error = 0; |
8ee1c3db | 544 | |
c9f7fbf9 VS |
545 | intel_uncore_early_sanitize(dev); |
546 | ||
9d49c0ef PZ |
547 | intel_uncore_sanitize(dev); |
548 | ||
549 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
550 | restore_gtt_mappings) { | |
551 | mutex_lock(&dev->struct_mutex); | |
552 | i915_gem_restore_gtt_mappings(dev); | |
553 | mutex_unlock(&dev->struct_mutex); | |
554 | } | |
555 | ||
da7e29bd | 556 | intel_power_domains_init_hw(dev_priv); |
ebdcefc6 | 557 | |
61caf87c | 558 | i915_restore_state(dev); |
44834a67 | 559 | intel_opregion_setup(dev); |
61caf87c | 560 | |
5669fcac JB |
561 | /* KMS EnterVT equivalent */ |
562 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 563 | intel_init_pch_refclk(dev); |
754970ee | 564 | drm_mode_config_reset(dev); |
1833b134 | 565 | |
5669fcac | 566 | mutex_lock(&dev->struct_mutex); |
5669fcac | 567 | |
f691e2f4 | 568 | error = i915_gem_init_hw(dev); |
5669fcac | 569 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 570 | |
15239099 DV |
571 | /* We need working interrupts for modeset enabling ... */ |
572 | drm_irq_install(dev); | |
573 | ||
1833b134 | 574 | intel_modeset_init_hw(dev); |
24576d23 JB |
575 | |
576 | drm_modeset_lock_all(dev); | |
577 | intel_modeset_setup_hw_state(dev, true); | |
578 | drm_modeset_unlock_all(dev); | |
15239099 DV |
579 | |
580 | /* | |
581 | * ... but also need to make sure that hotplug processing | |
582 | * doesn't cause havoc. Like in the driver load code we don't | |
583 | * bother with the tiny race here where we might loose hotplug | |
584 | * notifications. | |
585 | * */ | |
20afbda2 | 586 | intel_hpd_init(dev); |
15239099 | 587 | dev_priv->enable_hotplug_processing = true; |
bb60b969 JB |
588 | /* Config may have changed between suspend and resume */ |
589 | intel_resume_hotplug(dev); | |
d5bb081b | 590 | } |
1daed3fb | 591 | |
44834a67 CW |
592 | intel_opregion_init(dev); |
593 | ||
073f34d9 JB |
594 | /* |
595 | * The console lock can be pretty contented on resume due | |
596 | * to all the printk activity. Try to keep it out of the hot | |
597 | * path of resume if possible. | |
598 | */ | |
599 | if (console_trylock()) { | |
b6f3eff7 | 600 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
601 | console_unlock(); |
602 | } else { | |
603 | schedule_work(&dev_priv->console_resume_work); | |
604 | } | |
605 | ||
b8efb17b ZR |
606 | mutex_lock(&dev_priv->modeset_restore_lock); |
607 | dev_priv->modeset_restore = MODESET_DONE; | |
608 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 PZ |
609 | |
610 | intel_runtime_pm_put(dev_priv); | |
84b79f8d RW |
611 | return error; |
612 | } | |
613 | ||
1abd02e2 JB |
614 | static int i915_drm_thaw(struct drm_device *dev) |
615 | { | |
7f16e5c1 | 616 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
828c7908 | 617 | i915_check_and_clear_faults(dev); |
1abd02e2 | 618 | |
9d49c0ef | 619 | return __i915_drm_thaw(dev, true); |
84b79f8d RW |
620 | } |
621 | ||
6a9ee8af | 622 | int i915_resume(struct drm_device *dev) |
84b79f8d | 623 | { |
1abd02e2 | 624 | struct drm_i915_private *dev_priv = dev->dev_private; |
6eecba33 CW |
625 | int ret; |
626 | ||
5bcf719b DA |
627 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
628 | return 0; | |
629 | ||
84b79f8d RW |
630 | if (pci_enable_device(dev->pdev)) |
631 | return -EIO; | |
632 | ||
633 | pci_set_master(dev->pdev); | |
634 | ||
1abd02e2 JB |
635 | /* |
636 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
9d49c0ef PZ |
637 | * earlier) need to restore the GTT mappings since the BIOS might clear |
638 | * all our scratch PTEs. | |
1abd02e2 | 639 | */ |
9d49c0ef | 640 | ret = __i915_drm_thaw(dev, !dev_priv->opregion.header); |
6eecba33 CW |
641 | if (ret) |
642 | return ret; | |
643 | ||
644 | drm_kms_helper_poll_enable(dev); | |
645 | return 0; | |
ba8bbcf6 JB |
646 | } |
647 | ||
11ed50ec | 648 | /** |
f3953dcb | 649 | * i915_reset - reset chip after a hang |
11ed50ec | 650 | * @dev: drm device to reset |
11ed50ec BG |
651 | * |
652 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
653 | * reset or otherwise an error code. | |
654 | * | |
655 | * Procedure is fairly simple: | |
656 | * - reset the chip using the reset reg | |
657 | * - re-init context state | |
658 | * - re-init hardware status page | |
659 | * - re-init ring buffer | |
660 | * - re-init interrupt state | |
661 | * - re-init display | |
662 | */ | |
d4b8bb2a | 663 | int i915_reset(struct drm_device *dev) |
11ed50ec | 664 | { |
50227e1c | 665 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 666 | bool simulated; |
0573ed4a | 667 | int ret; |
11ed50ec | 668 | |
d330a953 | 669 | if (!i915.reset) |
d78cb50b CW |
670 | return 0; |
671 | ||
d54a02c0 | 672 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 673 | |
069efc1d | 674 | i915_gem_reset(dev); |
77f01230 | 675 | |
2e7c8ee7 CW |
676 | simulated = dev_priv->gpu_error.stop_rings != 0; |
677 | ||
be62acb4 MK |
678 | ret = intel_gpu_reset(dev); |
679 | ||
680 | /* Also reset the gpu hangman. */ | |
681 | if (simulated) { | |
682 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
683 | dev_priv->gpu_error.stop_rings = 0; | |
684 | if (ret == -ENODEV) { | |
f2d91a2c DV |
685 | DRM_INFO("Reset not implemented, but ignoring " |
686 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
687 | ret = 0; |
688 | } | |
2e7c8ee7 | 689 | } |
be62acb4 | 690 | |
0573ed4a | 691 | if (ret) { |
f2d91a2c | 692 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 693 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 694 | return ret; |
11ed50ec BG |
695 | } |
696 | ||
697 | /* Ok, now get things going again... */ | |
698 | ||
699 | /* | |
700 | * Everything depends on having the GTT running, so we need to start | |
701 | * there. Fortunately we don't need to do this unless we reset the | |
702 | * chip at a PCI level. | |
703 | * | |
704 | * Next we need to restore the context, but we don't use those | |
705 | * yet either... | |
706 | * | |
707 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
708 | * was running at the time of the reset (i.e. we weren't VT | |
709 | * switched away). | |
710 | */ | |
711 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 712 | !dev_priv->ums.mm_suspended) { |
db1b76ca | 713 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 714 | |
3d57e5bd | 715 | ret = i915_gem_init_hw(dev); |
8e88a2bd | 716 | mutex_unlock(&dev->struct_mutex); |
3d57e5bd BW |
717 | if (ret) { |
718 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
719 | return ret; | |
720 | } | |
f817586c | 721 | |
11ed50ec BG |
722 | drm_irq_uninstall(dev); |
723 | drm_irq_install(dev); | |
dd0a1aa1 JM |
724 | |
725 | /* rps/rc6 re-init is necessary to restore state lost after the | |
726 | * reset and the re-install of drm irq. Skip for ironlake per | |
727 | * previous concerns that it doesn't respond well to some forms | |
728 | * of re-init after reset. */ | |
729 | if (INTEL_INFO(dev)->gen > 5) { | |
730 | mutex_lock(&dev->struct_mutex); | |
731 | intel_enable_gt_powersave(dev); | |
732 | mutex_unlock(&dev->struct_mutex); | |
733 | } | |
734 | ||
20afbda2 | 735 | intel_hpd_init(dev); |
bcbc324a DV |
736 | } else { |
737 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
738 | } |
739 | ||
11ed50ec BG |
740 | return 0; |
741 | } | |
742 | ||
56550d94 | 743 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 744 | { |
01a06850 DV |
745 | struct intel_device_info *intel_info = |
746 | (struct intel_device_info *) ent->driver_data; | |
747 | ||
d330a953 | 748 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
749 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
750 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
751 | return -ENODEV; | |
752 | } | |
753 | ||
5fe49d86 CW |
754 | /* Only bind to function 0 of the device. Early generations |
755 | * used function 1 as a placeholder for multi-head. This causes | |
756 | * us confusion instead, especially on the systems where both | |
757 | * functions have the same PCI-ID! | |
758 | */ | |
759 | if (PCI_FUNC(pdev->devfn)) | |
760 | return -ENODEV; | |
761 | ||
24986ee0 | 762 | driver.driver_features &= ~(DRIVER_USE_AGP); |
01a06850 | 763 | |
dcdb1674 | 764 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
765 | } |
766 | ||
767 | static void | |
768 | i915_pci_remove(struct pci_dev *pdev) | |
769 | { | |
770 | struct drm_device *dev = pci_get_drvdata(pdev); | |
771 | ||
772 | drm_put_dev(dev); | |
773 | } | |
774 | ||
84b79f8d | 775 | static int i915_pm_suspend(struct device *dev) |
112b715e | 776 | { |
84b79f8d RW |
777 | struct pci_dev *pdev = to_pci_dev(dev); |
778 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
779 | int error; | |
112b715e | 780 | |
84b79f8d RW |
781 | if (!drm_dev || !drm_dev->dev_private) { |
782 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
783 | return -ENODEV; | |
784 | } | |
112b715e | 785 | |
5bcf719b DA |
786 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
787 | return 0; | |
788 | ||
84b79f8d RW |
789 | error = i915_drm_freeze(drm_dev); |
790 | if (error) | |
791 | return error; | |
112b715e | 792 | |
84b79f8d RW |
793 | pci_disable_device(pdev); |
794 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 795 | |
84b79f8d | 796 | return 0; |
cbda12d7 ZW |
797 | } |
798 | ||
84b79f8d | 799 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 800 | { |
84b79f8d RW |
801 | struct pci_dev *pdev = to_pci_dev(dev); |
802 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
803 | ||
804 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
805 | } |
806 | ||
84b79f8d | 807 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 808 | { |
84b79f8d RW |
809 | struct pci_dev *pdev = to_pci_dev(dev); |
810 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
811 | ||
812 | if (!drm_dev || !drm_dev->dev_private) { | |
813 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
814 | return -ENODEV; | |
815 | } | |
816 | ||
817 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
818 | } |
819 | ||
84b79f8d | 820 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 821 | { |
84b79f8d RW |
822 | struct pci_dev *pdev = to_pci_dev(dev); |
823 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
824 | ||
825 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
826 | } |
827 | ||
84b79f8d | 828 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 829 | { |
84b79f8d RW |
830 | struct pci_dev *pdev = to_pci_dev(dev); |
831 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 832 | |
61caf87c | 833 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
834 | } |
835 | ||
8a187455 PZ |
836 | static int i915_runtime_suspend(struct device *device) |
837 | { | |
838 | struct pci_dev *pdev = to_pci_dev(device); | |
839 | struct drm_device *dev = pci_get_drvdata(pdev); | |
840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
841 | ||
842 | WARN_ON(!HAS_RUNTIME_PM(dev)); | |
e998c40f | 843 | assert_force_wake_inactive(dev_priv); |
8a187455 PZ |
844 | |
845 | DRM_DEBUG_KMS("Suspending device\n"); | |
846 | ||
a8a8bd54 | 847 | if (HAS_PC8(dev)) |
a14cb6fc | 848 | hsw_enable_pc8(dev_priv); |
a8a8bd54 | 849 | |
48018a57 PZ |
850 | i915_gem_release_all_mmaps(dev_priv); |
851 | ||
16a3d6ef | 852 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
8a187455 | 853 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
854 | |
855 | /* | |
856 | * current versions of firmware which depend on this opregion | |
857 | * notification have repurposed the D1 definition to mean | |
858 | * "runtime suspended" vs. what you would normally expect (D3) | |
859 | * to distinguish it from notifications that might be sent | |
860 | * via the suspend path. | |
861 | */ | |
862 | intel_opregion_notify_adapter(dev, PCI_D1); | |
8a187455 | 863 | |
a8a8bd54 | 864 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
865 | return 0; |
866 | } | |
867 | ||
868 | static int i915_runtime_resume(struct device *device) | |
869 | { | |
870 | struct pci_dev *pdev = to_pci_dev(device); | |
871 | struct drm_device *dev = pci_get_drvdata(pdev); | |
872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
873 | ||
874 | WARN_ON(!HAS_RUNTIME_PM(dev)); | |
875 | ||
876 | DRM_DEBUG_KMS("Resuming device\n"); | |
877 | ||
cd2e9e90 | 878 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 PZ |
879 | dev_priv->pm.suspended = false; |
880 | ||
a8a8bd54 | 881 | if (HAS_PC8(dev)) |
a14cb6fc | 882 | hsw_disable_pc8(dev_priv); |
a8a8bd54 PZ |
883 | |
884 | DRM_DEBUG_KMS("Device resumed\n"); | |
8a187455 PZ |
885 | return 0; |
886 | } | |
887 | ||
b4b78d12 | 888 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
889 | .suspend = i915_pm_suspend, |
890 | .resume = i915_pm_resume, | |
891 | .freeze = i915_pm_freeze, | |
892 | .thaw = i915_pm_thaw, | |
893 | .poweroff = i915_pm_poweroff, | |
894 | .restore = i915_pm_resume, | |
8a187455 PZ |
895 | .runtime_suspend = i915_runtime_suspend, |
896 | .runtime_resume = i915_runtime_resume, | |
cbda12d7 ZW |
897 | }; |
898 | ||
78b68556 | 899 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 900 | .fault = i915_gem_fault, |
ab00b3e5 JB |
901 | .open = drm_gem_vm_open, |
902 | .close = drm_gem_vm_close, | |
de151cf6 JB |
903 | }; |
904 | ||
e08e96de AV |
905 | static const struct file_operations i915_driver_fops = { |
906 | .owner = THIS_MODULE, | |
907 | .open = drm_open, | |
908 | .release = drm_release, | |
909 | .unlocked_ioctl = drm_ioctl, | |
910 | .mmap = drm_gem_mmap, | |
911 | .poll = drm_poll, | |
e08e96de AV |
912 | .read = drm_read, |
913 | #ifdef CONFIG_COMPAT | |
914 | .compat_ioctl = i915_compat_ioctl, | |
915 | #endif | |
916 | .llseek = noop_llseek, | |
917 | }; | |
918 | ||
1da177e4 | 919 | static struct drm_driver driver = { |
0c54781b MW |
920 | /* Don't use MTRRs here; the Xserver or userspace app should |
921 | * deal with them for Intel hardware. | |
792d2b9a | 922 | */ |
673a394b | 923 | .driver_features = |
24986ee0 | 924 | DRIVER_USE_AGP | |
10ba5012 KH |
925 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
926 | DRIVER_RENDER, | |
22eae947 | 927 | .load = i915_driver_load, |
ba8bbcf6 | 928 | .unload = i915_driver_unload, |
673a394b | 929 | .open = i915_driver_open, |
22eae947 DA |
930 | .lastclose = i915_driver_lastclose, |
931 | .preclose = i915_driver_preclose, | |
673a394b | 932 | .postclose = i915_driver_postclose, |
d8e29209 RW |
933 | |
934 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
935 | .suspend = i915_suspend, | |
936 | .resume = i915_resume, | |
937 | ||
cda17380 | 938 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
939 | .master_create = i915_master_create, |
940 | .master_destroy = i915_master_destroy, | |
955b12de | 941 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
942 | .debugfs_init = i915_debugfs_init, |
943 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 944 | #endif |
673a394b | 945 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 946 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
947 | |
948 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
949 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
950 | .gem_prime_export = i915_gem_prime_export, | |
951 | .gem_prime_import = i915_gem_prime_import, | |
952 | ||
ff72145b DA |
953 | .dumb_create = i915_gem_dumb_create, |
954 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 955 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 956 | .ioctls = i915_ioctls, |
e08e96de | 957 | .fops = &i915_driver_fops, |
22eae947 DA |
958 | .name = DRIVER_NAME, |
959 | .desc = DRIVER_DESC, | |
960 | .date = DRIVER_DATE, | |
961 | .major = DRIVER_MAJOR, | |
962 | .minor = DRIVER_MINOR, | |
963 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
964 | }; |
965 | ||
8410ea3b DA |
966 | static struct pci_driver i915_pci_driver = { |
967 | .name = DRIVER_NAME, | |
968 | .id_table = pciidlist, | |
969 | .probe = i915_pci_probe, | |
970 | .remove = i915_pci_remove, | |
971 | .driver.pm = &i915_pm_ops, | |
972 | }; | |
973 | ||
1da177e4 LT |
974 | static int __init i915_init(void) |
975 | { | |
976 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
977 | |
978 | /* | |
979 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
980 | * explicitly disabled with the module pararmeter. | |
981 | * | |
982 | * Otherwise, just follow the parameter (defaulting to off). | |
983 | * | |
984 | * Allow optional vga_text_mode_force boot option to override | |
985 | * the default behavior. | |
986 | */ | |
987 | #if defined(CONFIG_DRM_I915_KMS) | |
d330a953 | 988 | if (i915.modeset != 0) |
79e53945 JB |
989 | driver.driver_features |= DRIVER_MODESET; |
990 | #endif | |
d330a953 | 991 | if (i915.modeset == 1) |
79e53945 JB |
992 | driver.driver_features |= DRIVER_MODESET; |
993 | ||
994 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 995 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
996 | driver.driver_features &= ~DRIVER_MODESET; |
997 | #endif | |
998 | ||
b30324ad | 999 | if (!(driver.driver_features & DRIVER_MODESET)) { |
3885c6bb | 1000 | driver.get_vblank_timestamp = NULL; |
b30324ad DV |
1001 | #ifndef CONFIG_DRM_I915_UMS |
1002 | /* Silently fail loading to not upset userspace. */ | |
1003 | return 0; | |
1004 | #endif | |
1005 | } | |
3885c6bb | 1006 | |
8410ea3b | 1007 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1008 | } |
1009 | ||
1010 | static void __exit i915_exit(void) | |
1011 | { | |
b33ecdd1 DV |
1012 | #ifndef CONFIG_DRM_I915_UMS |
1013 | if (!(driver.driver_features & DRIVER_MODESET)) | |
1014 | return; /* Never loaded a driver. */ | |
1015 | #endif | |
1016 | ||
8410ea3b | 1017 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1018 | } |
1019 | ||
1020 | module_init(i915_init); | |
1021 | module_exit(i915_exit); | |
1022 | ||
b5e89ed5 DA |
1023 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1024 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1025 | MODULE_LICENSE("GPL and additional rights"); |