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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
354ff967 | 39 | #include "drm_crtc_helper.h" |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a35d9d3c | 50 | int i915_panel_ignore_lid __read_mostly = 0; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 BW |
52 | MODULE_PARM_DESC(panel_ignore_lid, |
53 | "Override lid status (0=autodetect [default], 1=lid open, " | |
54 | "-1=lid closed)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
f57f9c16 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
112b715e | 121 | static struct drm_driver driver; |
1f7a6e37 | 122 | extern int intel_agp_enabled; |
112b715e | 123 | |
cfdf1fa2 | 124 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 125 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 126 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
127 | .vendor = 0x8086, \ |
128 | .device = id, \ | |
129 | .subvendor = PCI_ANY_ID, \ | |
130 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
131 | .driver_data = (unsigned long) info } |
132 | ||
9a7e8492 | 133 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 134 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 135 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
136 | }; |
137 | ||
9a7e8492 | 138 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 139 | .gen = 2, |
31578148 | 140 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
141 | }; |
142 | ||
9a7e8492 | 143 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 144 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 145 | .cursor_needs_physical = 1, |
31578148 | 146 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
147 | }; |
148 | ||
9a7e8492 | 149 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 150 | .gen = 2, |
31578148 | 151 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
152 | }; |
153 | ||
9a7e8492 | 154 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 155 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 156 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 157 | }; |
9a7e8492 | 158 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 159 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 160 | .cursor_needs_physical = 1, |
31578148 | 161 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 162 | .supports_tv = 1, |
cfdf1fa2 | 163 | }; |
9a7e8492 | 164 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 165 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 166 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 167 | }; |
9a7e8492 | 168 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 169 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 170 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 171 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 172 | .supports_tv = 1, |
cfdf1fa2 KH |
173 | }; |
174 | ||
9a7e8492 | 175 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 176 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 177 | .has_hotplug = 1, |
31578148 | 178 | .has_overlay = 1, |
cfdf1fa2 KH |
179 | }; |
180 | ||
9a7e8492 | 181 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 182 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 183 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 184 | .has_overlay = 1, |
a6c45cf0 | 185 | .supports_tv = 1, |
cfdf1fa2 KH |
186 | }; |
187 | ||
9a7e8492 | 188 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 189 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 190 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 191 | .has_overlay = 1, |
cfdf1fa2 KH |
192 | }; |
193 | ||
9a7e8492 | 194 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 195 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 196 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 197 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
198 | }; |
199 | ||
9a7e8492 | 200 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 201 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 202 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 203 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 204 | .supports_tv = 1, |
92f49d9c | 205 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
206 | }; |
207 | ||
9a7e8492 | 208 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 209 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 210 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 211 | .has_overlay = 1, |
cfdf1fa2 KH |
212 | }; |
213 | ||
9a7e8492 | 214 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 215 | .gen = 5, |
5a117db7 | 216 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 217 | .has_bsd_ring = 1, |
7e508a27 | 218 | .has_pch_split = 1, |
cfdf1fa2 KH |
219 | }; |
220 | ||
9a7e8492 | 221 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 222 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 223 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 224 | .has_fbc = 1, |
92f49d9c | 225 | .has_bsd_ring = 1, |
7e508a27 | 226 | .has_pch_split = 1, |
cfdf1fa2 KH |
227 | }; |
228 | ||
9a7e8492 | 229 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 230 | .gen = 6, |
c96c3a8c | 231 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 232 | .has_bsd_ring = 1, |
549f7365 | 233 | .has_blt_ring = 1, |
3d29b842 | 234 | .has_llc = 1, |
7e508a27 | 235 | .has_pch_split = 1, |
f6e450a6 EA |
236 | }; |
237 | ||
9a7e8492 | 238 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 239 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 240 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 241 | .has_fbc = 1, |
881f47b6 | 242 | .has_bsd_ring = 1, |
549f7365 | 243 | .has_blt_ring = 1, |
3d29b842 | 244 | .has_llc = 1, |
7e508a27 | 245 | .has_pch_split = 1, |
a13e4093 EA |
246 | }; |
247 | ||
c76b615c JB |
248 | static const struct intel_device_info intel_ivybridge_d_info = { |
249 | .is_ivybridge = 1, .gen = 7, | |
250 | .need_gfx_hws = 1, .has_hotplug = 1, | |
251 | .has_bsd_ring = 1, | |
252 | .has_blt_ring = 1, | |
3d29b842 | 253 | .has_llc = 1, |
7e508a27 | 254 | .has_pch_split = 1, |
c76b615c JB |
255 | }; |
256 | ||
257 | static const struct intel_device_info intel_ivybridge_m_info = { | |
258 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, | |
259 | .need_gfx_hws = 1, .has_hotplug = 1, | |
260 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ | |
261 | .has_bsd_ring = 1, | |
262 | .has_blt_ring = 1, | |
3d29b842 | 263 | .has_llc = 1, |
7e508a27 | 264 | .has_pch_split = 1, |
c76b615c JB |
265 | }; |
266 | ||
70a3eb7a JB |
267 | static const struct intel_device_info intel_valleyview_m_info = { |
268 | .gen = 7, .is_mobile = 1, | |
269 | .need_gfx_hws = 1, .has_hotplug = 1, | |
270 | .has_fbc = 0, | |
271 | .has_bsd_ring = 1, | |
272 | .has_blt_ring = 1, | |
273 | .is_valleyview = 1, | |
274 | }; | |
275 | ||
276 | static const struct intel_device_info intel_valleyview_d_info = { | |
277 | .gen = 7, | |
278 | .need_gfx_hws = 1, .has_hotplug = 1, | |
279 | .has_fbc = 0, | |
280 | .has_bsd_ring = 1, | |
281 | .has_blt_ring = 1, | |
282 | .is_valleyview = 1, | |
283 | }; | |
284 | ||
4cae9ae0 ED |
285 | static const struct intel_device_info intel_haswell_d_info = { |
286 | .is_haswell = 1, .gen = 7, | |
287 | .need_gfx_hws = 1, .has_hotplug = 1, | |
288 | .has_bsd_ring = 1, | |
289 | .has_blt_ring = 1, | |
290 | .has_llc = 1, | |
291 | .has_pch_split = 1, | |
292 | }; | |
293 | ||
294 | static const struct intel_device_info intel_haswell_m_info = { | |
295 | .is_haswell = 1, .gen = 7, .is_mobile = 1, | |
296 | .need_gfx_hws = 1, .has_hotplug = 1, | |
297 | .has_bsd_ring = 1, | |
298 | .has_blt_ring = 1, | |
299 | .has_llc = 1, | |
300 | .has_pch_split = 1, | |
c76b615c JB |
301 | }; |
302 | ||
6103da0d CW |
303 | static const struct pci_device_id pciidlist[] = { /* aka */ |
304 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
305 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
306 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 307 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
308 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
309 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
310 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
311 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
312 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
313 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
314 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
315 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
316 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
317 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
318 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
319 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
320 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
321 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
322 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
323 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
324 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
325 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
326 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
327 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
328 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
329 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 330 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
331 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
332 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
333 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
334 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 335 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
336 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
337 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 338 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 339 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 340 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 341 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
342 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
343 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
344 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
345 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
346 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
cc22a938 | 347 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
c14f5286 ED |
348 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
349 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ | |
350 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ | |
351 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ | |
352 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ | |
353 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ | |
354 | INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */ | |
49ae35f2 | 355 | {0, 0, 0} |
1da177e4 LT |
356 | }; |
357 | ||
79e53945 JB |
358 | #if defined(CONFIG_DRM_I915_KMS) |
359 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
360 | #endif | |
361 | ||
3bad0781 | 362 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
90711d50 | 363 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
3bad0781 | 364 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
c792513b | 365 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
eb877ebf | 366 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
3bad0781 | 367 | |
0206e353 | 368 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
369 | { |
370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
371 | struct pci_dev *pch; | |
372 | ||
373 | /* | |
374 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
375 | * make graphics device passthrough work easy for VMM, that only | |
376 | * need to expose ISA bridge to let driver know the real hardware | |
377 | * underneath. This is a requirement from virtualization team. | |
378 | */ | |
379 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
380 | if (pch) { | |
381 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
382 | int id; | |
383 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
384 | ||
90711d50 JB |
385 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
386 | dev_priv->pch_type = PCH_IBX; | |
ee7b9f93 | 387 | dev_priv->num_pch_pll = 2; |
90711d50 JB |
388 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
389 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
3bad0781 | 390 | dev_priv->pch_type = PCH_CPT; |
ee7b9f93 | 391 | dev_priv->num_pch_pll = 2; |
3bad0781 | 392 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
c792513b JB |
393 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
394 | /* PantherPoint is CPT compatible */ | |
395 | dev_priv->pch_type = PCH_CPT; | |
ee7b9f93 | 396 | dev_priv->num_pch_pll = 2; |
c792513b | 397 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
eb877ebf ED |
398 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
399 | dev_priv->pch_type = PCH_LPT; | |
ee7b9f93 | 400 | dev_priv->num_pch_pll = 0; |
eb877ebf | 401 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
3bad0781 | 402 | } |
ee7b9f93 | 403 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
3bad0781 ZW |
404 | } |
405 | pci_dev_put(pch); | |
406 | } | |
407 | } | |
408 | ||
2911a35b BW |
409 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
410 | { | |
411 | if (INTEL_INFO(dev)->gen < 6) | |
412 | return 0; | |
413 | ||
414 | if (i915_semaphores >= 0) | |
415 | return i915_semaphores; | |
416 | ||
59de3295 | 417 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 418 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
419 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
420 | return false; | |
421 | #endif | |
2911a35b BW |
422 | |
423 | return 1; | |
424 | } | |
425 | ||
8d715f00 | 426 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
eb43f4af CW |
427 | { |
428 | int count; | |
429 | ||
430 | count = 0; | |
431 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
432 | udelay(10); | |
433 | ||
434 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
435 | POSTING_READ(FORCEWAKE); | |
436 | ||
437 | count = 0; | |
438 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) | |
439 | udelay(10); | |
440 | } | |
441 | ||
8d715f00 KP |
442 | void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
443 | { | |
444 | int count; | |
445 | ||
446 | count = 0; | |
447 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) | |
448 | udelay(10); | |
449 | ||
6b26c86d | 450 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1)); |
8d715f00 KP |
451 | POSTING_READ(FORCEWAKE_MT); |
452 | ||
453 | count = 0; | |
454 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) | |
455 | udelay(10); | |
456 | } | |
457 | ||
fcca7926 BW |
458 | /* |
459 | * Generally this is called implicitly by the register read function. However, | |
460 | * if some sequence requires the GT to not power down then this function should | |
461 | * be called at the beginning of the sequence followed by a call to | |
462 | * gen6_gt_force_wake_put() at the end of the sequence. | |
463 | */ | |
464 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
465 | { | |
9f1f46a4 | 466 | unsigned long irqflags; |
fcca7926 | 467 | |
9f1f46a4 DV |
468 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
469 | if (dev_priv->forcewake_count++ == 0) | |
8d715f00 | 470 | dev_priv->display.force_wake_get(dev_priv); |
9f1f46a4 | 471 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
472 | } |
473 | ||
ee64cbdb BW |
474 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
475 | { | |
476 | u32 gtfifodbg; | |
477 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); | |
478 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, | |
479 | "MMIO read or write has been dropped %x\n", gtfifodbg)) | |
480 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); | |
481 | } | |
482 | ||
8d715f00 | 483 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
eb43f4af CW |
484 | { |
485 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
ee64cbdb BW |
486 | /* The below doubles as a POSTING_READ */ |
487 | gen6_gt_check_fifodbg(dev_priv); | |
eb43f4af CW |
488 | } |
489 | ||
8d715f00 KP |
490 | void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
491 | { | |
6b26c86d | 492 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1)); |
ee64cbdb BW |
493 | /* The below doubles as a POSTING_READ */ |
494 | gen6_gt_check_fifodbg(dev_priv); | |
8d715f00 KP |
495 | } |
496 | ||
fcca7926 BW |
497 | /* |
498 | * see gen6_gt_force_wake_get() | |
499 | */ | |
500 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
501 | { | |
9f1f46a4 | 502 | unsigned long irqflags; |
fcca7926 | 503 | |
9f1f46a4 DV |
504 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
505 | if (--dev_priv->forcewake_count == 0) | |
8d715f00 | 506 | dev_priv->display.force_wake_put(dev_priv); |
9f1f46a4 | 507 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
508 | } |
509 | ||
67a3744f | 510 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
91355834 | 511 | { |
67a3744f BW |
512 | int ret = 0; |
513 | ||
0206e353 | 514 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
95736720 CW |
515 | int loop = 500; |
516 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
517 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { | |
518 | udelay(10); | |
519 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
520 | } | |
67a3744f BW |
521 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
522 | ++ret; | |
95736720 | 523 | dev_priv->gt_fifo_count = fifo; |
91355834 | 524 | } |
95736720 | 525 | dev_priv->gt_fifo_count--; |
67a3744f BW |
526 | |
527 | return ret; | |
91355834 CW |
528 | } |
529 | ||
575155a9 JB |
530 | void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
531 | { | |
532 | int count; | |
533 | ||
534 | count = 0; | |
535 | ||
536 | /* Already awake? */ | |
537 | if ((I915_READ(0x130094) & 0xa1) == 0xa1) | |
538 | return; | |
539 | ||
540 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff); | |
541 | POSTING_READ(FORCEWAKE_VLV); | |
542 | ||
543 | count = 0; | |
544 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0) | |
545 | udelay(10); | |
546 | } | |
547 | ||
548 | void vlv_force_wake_put(struct drm_i915_private *dev_priv) | |
549 | { | |
550 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000); | |
551 | /* FIXME: confirm VLV behavior with Punit folks */ | |
552 | POSTING_READ(FORCEWAKE_VLV); | |
553 | } | |
554 | ||
84b79f8d | 555 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 556 | { |
61caf87c RW |
557 | struct drm_i915_private *dev_priv = dev->dev_private; |
558 | ||
5bcf719b DA |
559 | drm_kms_helper_poll_disable(dev); |
560 | ||
ba8bbcf6 | 561 | pci_save_state(dev->pdev); |
ba8bbcf6 | 562 | |
5669fcac | 563 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 564 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
565 | int error = i915_gem_idle(dev); |
566 | if (error) { | |
226485e9 | 567 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
568 | "GEM idle failed, resume might fail\n"); |
569 | return error; | |
570 | } | |
226485e9 | 571 | drm_irq_uninstall(dev); |
5669fcac JB |
572 | } |
573 | ||
9e06dd39 JB |
574 | i915_save_state(dev); |
575 | ||
44834a67 | 576 | intel_opregion_fini(dev); |
8ee1c3db | 577 | |
84b79f8d RW |
578 | /* Modeset on resume, not lid events */ |
579 | dev_priv->modeset_on_lid = 0; | |
61caf87c | 580 | |
3fa016a0 DA |
581 | console_lock(); |
582 | intel_fbdev_set_suspend(dev, 1); | |
583 | console_unlock(); | |
584 | ||
61caf87c | 585 | return 0; |
84b79f8d RW |
586 | } |
587 | ||
6a9ee8af | 588 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
589 | { |
590 | int error; | |
591 | ||
592 | if (!dev || !dev->dev_private) { | |
593 | DRM_ERROR("dev: %p\n", dev); | |
594 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
595 | return -ENODEV; | |
596 | } | |
597 | ||
598 | if (state.event == PM_EVENT_PRETHAW) | |
599 | return 0; | |
600 | ||
5bcf719b DA |
601 | |
602 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
603 | return 0; | |
6eecba33 | 604 | |
84b79f8d RW |
605 | error = i915_drm_freeze(dev); |
606 | if (error) | |
607 | return error; | |
608 | ||
b932ccb5 DA |
609 | if (state.event == PM_EVENT_SUSPEND) { |
610 | /* Shut down the device */ | |
611 | pci_disable_device(dev->pdev); | |
612 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
613 | } | |
ba8bbcf6 JB |
614 | |
615 | return 0; | |
616 | } | |
617 | ||
84b79f8d | 618 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 619 | { |
5669fcac | 620 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 621 | int error = 0; |
8ee1c3db | 622 | |
d1c3b177 CW |
623 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
624 | mutex_lock(&dev->struct_mutex); | |
625 | i915_gem_restore_gtt_mappings(dev); | |
626 | mutex_unlock(&dev->struct_mutex); | |
627 | } | |
628 | ||
61caf87c | 629 | i915_restore_state(dev); |
44834a67 | 630 | intel_opregion_setup(dev); |
61caf87c | 631 | |
5669fcac JB |
632 | /* KMS EnterVT equivalent */ |
633 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
1833b134 CW |
634 | if (HAS_PCH_SPLIT(dev)) |
635 | ironlake_init_pch_refclk(dev); | |
636 | ||
5669fcac JB |
637 | mutex_lock(&dev->struct_mutex); |
638 | dev_priv->mm.suspended = 0; | |
639 | ||
f691e2f4 | 640 | error = i915_gem_init_hw(dev); |
5669fcac | 641 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 642 | |
1833b134 | 643 | intel_modeset_init_hw(dev); |
500f7147 | 644 | drm_mode_config_reset(dev); |
226485e9 | 645 | drm_irq_install(dev); |
84b79f8d | 646 | |
354ff967 | 647 | /* Resume the modeset for every activated CRTC */ |
927a2f11 | 648 | mutex_lock(&dev->mode_config.mutex); |
354ff967 | 649 | drm_helper_resume_force_mode(dev); |
927a2f11 | 650 | mutex_unlock(&dev->mode_config.mutex); |
d5bb081b | 651 | } |
1daed3fb | 652 | |
44834a67 CW |
653 | intel_opregion_init(dev); |
654 | ||
c9354c85 | 655 | dev_priv->modeset_on_lid = 0; |
06891e27 | 656 | |
3fa016a0 DA |
657 | console_lock(); |
658 | intel_fbdev_set_suspend(dev, 0); | |
659 | console_unlock(); | |
84b79f8d RW |
660 | return error; |
661 | } | |
662 | ||
6a9ee8af | 663 | int i915_resume(struct drm_device *dev) |
84b79f8d | 664 | { |
6eecba33 CW |
665 | int ret; |
666 | ||
5bcf719b DA |
667 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
668 | return 0; | |
669 | ||
84b79f8d RW |
670 | if (pci_enable_device(dev->pdev)) |
671 | return -EIO; | |
672 | ||
673 | pci_set_master(dev->pdev); | |
674 | ||
6eecba33 CW |
675 | ret = i915_drm_thaw(dev); |
676 | if (ret) | |
677 | return ret; | |
678 | ||
679 | drm_kms_helper_poll_enable(dev); | |
680 | return 0; | |
ba8bbcf6 JB |
681 | } |
682 | ||
d4b8bb2a | 683 | static int i8xx_do_reset(struct drm_device *dev) |
dc96e9b8 CW |
684 | { |
685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
686 | ||
687 | if (IS_I85X(dev)) | |
688 | return -ENODEV; | |
689 | ||
690 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
691 | POSTING_READ(D_STATE); | |
692 | ||
693 | if (IS_I830(dev) || IS_845G(dev)) { | |
694 | I915_WRITE(DEBUG_RESET_I830, | |
695 | DEBUG_RESET_DISPLAY | | |
696 | DEBUG_RESET_RENDER | | |
697 | DEBUG_RESET_FULL); | |
698 | POSTING_READ(DEBUG_RESET_I830); | |
699 | msleep(1); | |
700 | ||
701 | I915_WRITE(DEBUG_RESET_I830, 0); | |
702 | POSTING_READ(DEBUG_RESET_I830); | |
703 | } | |
704 | ||
705 | msleep(1); | |
706 | ||
707 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
708 | POSTING_READ(D_STATE); | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
f49f0586 KG |
713 | static int i965_reset_complete(struct drm_device *dev) |
714 | { | |
715 | u8 gdrst; | |
eeccdcac | 716 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
5fe9fe8c | 717 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
f49f0586 KG |
718 | } |
719 | ||
d4b8bb2a | 720 | static int i965_do_reset(struct drm_device *dev) |
0573ed4a | 721 | { |
5ccce180 | 722 | int ret; |
0573ed4a KG |
723 | u8 gdrst; |
724 | ||
ae681d96 CW |
725 | /* |
726 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
727 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
728 | * triggers the reset; when done, the hardware will clear it. | |
729 | */ | |
0573ed4a | 730 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
d4b8bb2a | 731 | pci_write_config_byte(dev->pdev, I965_GDRST, |
5ccce180 DV |
732 | gdrst | GRDOM_RENDER | |
733 | GRDOM_RESET_ENABLE); | |
734 | ret = wait_for(i965_reset_complete(dev), 500); | |
735 | if (ret) | |
736 | return ret; | |
737 | ||
738 | /* We can't reset render&media without also resetting display ... */ | |
739 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | |
740 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
741 | gdrst | GRDOM_MEDIA | | |
742 | GRDOM_RESET_ENABLE); | |
0573ed4a KG |
743 | |
744 | return wait_for(i965_reset_complete(dev), 500); | |
745 | } | |
746 | ||
d4b8bb2a | 747 | static int ironlake_do_reset(struct drm_device *dev) |
0573ed4a KG |
748 | { |
749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5ccce180 DV |
750 | u32 gdrst; |
751 | int ret; | |
752 | ||
753 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
754 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
755 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
756 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
757 | if (ret) | |
758 | return ret; | |
759 | ||
760 | /* We can't reset render&media without also resetting display ... */ | |
761 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
d4b8bb2a | 762 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
5ccce180 | 763 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
0573ed4a | 764 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
ba8bbcf6 JB |
765 | } |
766 | ||
d4b8bb2a | 767 | static int gen6_do_reset(struct drm_device *dev) |
cff458c2 EA |
768 | { |
769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b6e45f86 KP |
770 | int ret; |
771 | unsigned long irqflags; | |
cff458c2 | 772 | |
286fed41 KP |
773 | /* Hold gt_lock across reset to prevent any register access |
774 | * with forcewake not set correctly | |
775 | */ | |
b6e45f86 | 776 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
286fed41 KP |
777 | |
778 | /* Reset the chip */ | |
779 | ||
780 | /* GEN6_GDRST is not in the gt power well, no need to check | |
781 | * for fifo space for the write or forcewake the chip for | |
782 | * the read | |
783 | */ | |
784 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
785 | ||
786 | /* Spin waiting for the device to ack the reset request */ | |
787 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
788 | ||
789 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | |
b6e45f86 KP |
790 | if (dev_priv->forcewake_count) |
791 | dev_priv->display.force_wake_get(dev_priv); | |
286fed41 KP |
792 | else |
793 | dev_priv->display.force_wake_put(dev_priv); | |
794 | ||
795 | /* Restore fifo count */ | |
796 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
797 | ||
b6e45f86 KP |
798 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
799 | return ret; | |
cff458c2 EA |
800 | } |
801 | ||
8e96d9c4 | 802 | int intel_gpu_reset(struct drm_device *dev) |
350d2706 | 803 | { |
2b9dc9a2 | 804 | struct drm_i915_private *dev_priv = dev->dev_private; |
350d2706 DV |
805 | int ret = -ENODEV; |
806 | ||
807 | switch (INTEL_INFO(dev)->gen) { | |
808 | case 7: | |
809 | case 6: | |
d4b8bb2a | 810 | ret = gen6_do_reset(dev); |
350d2706 DV |
811 | break; |
812 | case 5: | |
d4b8bb2a | 813 | ret = ironlake_do_reset(dev); |
350d2706 DV |
814 | break; |
815 | case 4: | |
d4b8bb2a | 816 | ret = i965_do_reset(dev); |
350d2706 DV |
817 | break; |
818 | case 2: | |
d4b8bb2a | 819 | ret = i8xx_do_reset(dev); |
350d2706 DV |
820 | break; |
821 | } | |
822 | ||
2b9dc9a2 DV |
823 | /* Also reset the gpu hangman. */ |
824 | if (dev_priv->stop_rings) { | |
825 | DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); | |
826 | dev_priv->stop_rings = 0; | |
827 | if (ret == -ENODEV) { | |
828 | DRM_ERROR("Reset not implemented, but ignoring " | |
829 | "error for simulated gpu hangs\n"); | |
830 | ret = 0; | |
831 | } | |
832 | } | |
833 | ||
350d2706 DV |
834 | return ret; |
835 | } | |
836 | ||
11ed50ec | 837 | /** |
f3953dcb | 838 | * i915_reset - reset chip after a hang |
11ed50ec | 839 | * @dev: drm device to reset |
11ed50ec BG |
840 | * |
841 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
842 | * reset or otherwise an error code. | |
843 | * | |
844 | * Procedure is fairly simple: | |
845 | * - reset the chip using the reset reg | |
846 | * - re-init context state | |
847 | * - re-init hardware status page | |
848 | * - re-init ring buffer | |
849 | * - re-init interrupt state | |
850 | * - re-init display | |
851 | */ | |
d4b8bb2a | 852 | int i915_reset(struct drm_device *dev) |
11ed50ec BG |
853 | { |
854 | drm_i915_private_t *dev_priv = dev->dev_private; | |
0573ed4a | 855 | int ret; |
11ed50ec | 856 | |
d78cb50b CW |
857 | if (!i915_try_reset) |
858 | return 0; | |
859 | ||
340479aa CW |
860 | if (!mutex_trylock(&dev->struct_mutex)) |
861 | return -EBUSY; | |
11ed50ec | 862 | |
069efc1d | 863 | i915_gem_reset(dev); |
77f01230 | 864 | |
f803aa55 | 865 | ret = -ENODEV; |
350d2706 | 866 | if (get_seconds() - dev_priv->last_gpu_reset < 5) |
ae681d96 | 867 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
350d2706 | 868 | else |
d4b8bb2a | 869 | ret = intel_gpu_reset(dev); |
350d2706 | 870 | |
ae681d96 | 871 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 872 | if (ret) { |
f803aa55 | 873 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 874 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 875 | return ret; |
11ed50ec BG |
876 | } |
877 | ||
878 | /* Ok, now get things going again... */ | |
879 | ||
880 | /* | |
881 | * Everything depends on having the GTT running, so we need to start | |
882 | * there. Fortunately we don't need to do this unless we reset the | |
883 | * chip at a PCI level. | |
884 | * | |
885 | * Next we need to restore the context, but we don't use those | |
886 | * yet either... | |
887 | * | |
888 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
889 | * was running at the time of the reset (i.e. we weren't VT | |
890 | * switched away). | |
891 | */ | |
892 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 893 | !dev_priv->mm.suspended) { |
b4519513 CW |
894 | struct intel_ring_buffer *ring; |
895 | int i; | |
896 | ||
11ed50ec | 897 | dev_priv->mm.suspended = 0; |
75a6898f | 898 | |
f691e2f4 DV |
899 | i915_gem_init_swizzling(dev); |
900 | ||
b4519513 CW |
901 | for_each_ring(ring, dev_priv, i) |
902 | ring->init(ring); | |
75a6898f | 903 | |
254f965c | 904 | i915_gem_context_init(dev); |
e21af88d DV |
905 | i915_gem_init_ppgtt(dev); |
906 | ||
8e88a2bd DV |
907 | /* |
908 | * It would make sense to re-init all the other hw state, at | |
909 | * least the rps/rc6/emon init done within modeset_init_hw. For | |
910 | * some unknown reason, this blows up my ilk, so don't. | |
911 | */ | |
f817586c | 912 | |
8e88a2bd | 913 | mutex_unlock(&dev->struct_mutex); |
f817586c | 914 | |
11ed50ec BG |
915 | drm_irq_uninstall(dev); |
916 | drm_irq_install(dev); | |
bcbc324a DV |
917 | } else { |
918 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
919 | } |
920 | ||
11ed50ec BG |
921 | return 0; |
922 | } | |
923 | ||
924 | ||
112b715e KH |
925 | static int __devinit |
926 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
927 | { | |
5fe49d86 CW |
928 | /* Only bind to function 0 of the device. Early generations |
929 | * used function 1 as a placeholder for multi-head. This causes | |
930 | * us confusion instead, especially on the systems where both | |
931 | * functions have the same PCI-ID! | |
932 | */ | |
933 | if (PCI_FUNC(pdev->devfn)) | |
934 | return -ENODEV; | |
935 | ||
dcdb1674 | 936 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
937 | } |
938 | ||
939 | static void | |
940 | i915_pci_remove(struct pci_dev *pdev) | |
941 | { | |
942 | struct drm_device *dev = pci_get_drvdata(pdev); | |
943 | ||
944 | drm_put_dev(dev); | |
945 | } | |
946 | ||
84b79f8d | 947 | static int i915_pm_suspend(struct device *dev) |
112b715e | 948 | { |
84b79f8d RW |
949 | struct pci_dev *pdev = to_pci_dev(dev); |
950 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
951 | int error; | |
112b715e | 952 | |
84b79f8d RW |
953 | if (!drm_dev || !drm_dev->dev_private) { |
954 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
955 | return -ENODEV; | |
956 | } | |
112b715e | 957 | |
5bcf719b DA |
958 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
959 | return 0; | |
960 | ||
84b79f8d RW |
961 | error = i915_drm_freeze(drm_dev); |
962 | if (error) | |
963 | return error; | |
112b715e | 964 | |
84b79f8d RW |
965 | pci_disable_device(pdev); |
966 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 967 | |
84b79f8d | 968 | return 0; |
cbda12d7 ZW |
969 | } |
970 | ||
84b79f8d | 971 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 972 | { |
84b79f8d RW |
973 | struct pci_dev *pdev = to_pci_dev(dev); |
974 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
975 | ||
976 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
977 | } |
978 | ||
84b79f8d | 979 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 980 | { |
84b79f8d RW |
981 | struct pci_dev *pdev = to_pci_dev(dev); |
982 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
983 | ||
984 | if (!drm_dev || !drm_dev->dev_private) { | |
985 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
986 | return -ENODEV; | |
987 | } | |
988 | ||
989 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
990 | } |
991 | ||
84b79f8d | 992 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 993 | { |
84b79f8d RW |
994 | struct pci_dev *pdev = to_pci_dev(dev); |
995 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
996 | ||
997 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
998 | } |
999 | ||
84b79f8d | 1000 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 1001 | { |
84b79f8d RW |
1002 | struct pci_dev *pdev = to_pci_dev(dev); |
1003 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 1004 | |
61caf87c | 1005 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
1006 | } |
1007 | ||
b4b78d12 | 1008 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
1009 | .suspend = i915_pm_suspend, |
1010 | .resume = i915_pm_resume, | |
1011 | .freeze = i915_pm_freeze, | |
1012 | .thaw = i915_pm_thaw, | |
1013 | .poweroff = i915_pm_poweroff, | |
1014 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
1015 | }; |
1016 | ||
78b68556 | 1017 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1018 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1019 | .open = drm_gem_vm_open, |
1020 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1021 | }; |
1022 | ||
e08e96de AV |
1023 | static const struct file_operations i915_driver_fops = { |
1024 | .owner = THIS_MODULE, | |
1025 | .open = drm_open, | |
1026 | .release = drm_release, | |
1027 | .unlocked_ioctl = drm_ioctl, | |
1028 | .mmap = drm_gem_mmap, | |
1029 | .poll = drm_poll, | |
1030 | .fasync = drm_fasync, | |
1031 | .read = drm_read, | |
1032 | #ifdef CONFIG_COMPAT | |
1033 | .compat_ioctl = i915_compat_ioctl, | |
1034 | #endif | |
1035 | .llseek = noop_llseek, | |
1036 | }; | |
1037 | ||
1da177e4 | 1038 | static struct drm_driver driver = { |
0c54781b MW |
1039 | /* Don't use MTRRs here; the Xserver or userspace app should |
1040 | * deal with them for Intel hardware. | |
792d2b9a | 1041 | */ |
673a394b EA |
1042 | .driver_features = |
1043 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
1286ff73 | 1044 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME, |
22eae947 | 1045 | .load = i915_driver_load, |
ba8bbcf6 | 1046 | .unload = i915_driver_unload, |
673a394b | 1047 | .open = i915_driver_open, |
22eae947 DA |
1048 | .lastclose = i915_driver_lastclose, |
1049 | .preclose = i915_driver_preclose, | |
673a394b | 1050 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1051 | |
1052 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1053 | .suspend = i915_suspend, | |
1054 | .resume = i915_resume, | |
1055 | ||
cda17380 | 1056 | .device_is_agp = i915_driver_device_is_agp, |
1da177e4 | 1057 | .reclaim_buffers = drm_core_reclaim_buffers, |
7c1c2871 DA |
1058 | .master_create = i915_master_create, |
1059 | .master_destroy = i915_master_destroy, | |
955b12de | 1060 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1061 | .debugfs_init = i915_debugfs_init, |
1062 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1063 | #endif |
673a394b EA |
1064 | .gem_init_object = i915_gem_init_object, |
1065 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 1066 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1067 | |
1068 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1069 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1070 | .gem_prime_export = i915_gem_prime_export, | |
1071 | .gem_prime_import = i915_gem_prime_import, | |
1072 | ||
ff72145b DA |
1073 | .dumb_create = i915_gem_dumb_create, |
1074 | .dumb_map_offset = i915_gem_mmap_gtt, | |
1075 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 | 1076 | .ioctls = i915_ioctls, |
e08e96de | 1077 | .fops = &i915_driver_fops, |
22eae947 DA |
1078 | .name = DRIVER_NAME, |
1079 | .desc = DRIVER_DESC, | |
1080 | .date = DRIVER_DATE, | |
1081 | .major = DRIVER_MAJOR, | |
1082 | .minor = DRIVER_MINOR, | |
1083 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1084 | }; |
1085 | ||
8410ea3b DA |
1086 | static struct pci_driver i915_pci_driver = { |
1087 | .name = DRIVER_NAME, | |
1088 | .id_table = pciidlist, | |
1089 | .probe = i915_pci_probe, | |
1090 | .remove = i915_pci_remove, | |
1091 | .driver.pm = &i915_pm_ops, | |
1092 | }; | |
1093 | ||
1da177e4 LT |
1094 | static int __init i915_init(void) |
1095 | { | |
1f7a6e37 ZW |
1096 | if (!intel_agp_enabled) { |
1097 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
1098 | return -ENODEV; | |
1099 | } | |
1100 | ||
1da177e4 | 1101 | driver.num_ioctls = i915_max_ioctl; |
79e53945 JB |
1102 | |
1103 | /* | |
1104 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1105 | * explicitly disabled with the module pararmeter. | |
1106 | * | |
1107 | * Otherwise, just follow the parameter (defaulting to off). | |
1108 | * | |
1109 | * Allow optional vga_text_mode_force boot option to override | |
1110 | * the default behavior. | |
1111 | */ | |
1112 | #if defined(CONFIG_DRM_I915_KMS) | |
1113 | if (i915_modeset != 0) | |
1114 | driver.driver_features |= DRIVER_MODESET; | |
1115 | #endif | |
1116 | if (i915_modeset == 1) | |
1117 | driver.driver_features |= DRIVER_MODESET; | |
1118 | ||
1119 | #ifdef CONFIG_VGA_CONSOLE | |
1120 | if (vgacon_text_force() && i915_modeset == -1) | |
1121 | driver.driver_features &= ~DRIVER_MODESET; | |
1122 | #endif | |
1123 | ||
3885c6bb CW |
1124 | if (!(driver.driver_features & DRIVER_MODESET)) |
1125 | driver.get_vblank_timestamp = NULL; | |
1126 | ||
8410ea3b | 1127 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1128 | } |
1129 | ||
1130 | static void __exit i915_exit(void) | |
1131 | { | |
8410ea3b | 1132 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1133 | } |
1134 | ||
1135 | module_init(i915_init); | |
1136 | module_exit(i915_exit); | |
1137 | ||
b5e89ed5 DA |
1138 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1139 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1140 | MODULE_LICENSE("GPL and additional rights"); |
f7000883 | 1141 | |
b7d84096 JB |
1142 | /* We give fast paths for the really cool registers */ |
1143 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
1144 | (((dev_priv)->info->gen >= 6) && \ | |
1145 | ((reg) < 0x40000) && \ | |
575155a9 JB |
1146 | ((reg) != FORCEWAKE)) && \ |
1147 | (!IS_VALLEYVIEW((dev_priv)->dev)) | |
b7d84096 | 1148 | |
f7dff0c9 JB |
1149 | static bool IS_DISPLAYREG(u32 reg) |
1150 | { | |
1151 | /* | |
1152 | * This should make it easier to transition modules over to the | |
1153 | * new register block scheme, since we can do it incrementally. | |
1154 | */ | |
1155 | if (reg >= 0x180000) | |
1156 | return false; | |
1157 | ||
1158 | if (reg >= RENDER_RING_BASE && | |
1159 | reg < RENDER_RING_BASE + 0xff) | |
1160 | return false; | |
1161 | if (reg >= GEN6_BSD_RING_BASE && | |
1162 | reg < GEN6_BSD_RING_BASE + 0xff) | |
1163 | return false; | |
1164 | if (reg >= BLT_RING_BASE && | |
1165 | reg < BLT_RING_BASE + 0xff) | |
1166 | return false; | |
1167 | ||
1168 | if (reg == PGTBL_ER) | |
1169 | return false; | |
1170 | ||
1171 | if (reg >= IPEIR_I965 && | |
1172 | reg < HWSTAM) | |
1173 | return false; | |
1174 | ||
1175 | if (reg == MI_MODE) | |
1176 | return false; | |
1177 | ||
1178 | if (reg == GFX_MODE_GEN7) | |
1179 | return false; | |
1180 | ||
1181 | if (reg == RENDER_HWS_PGA_GEN7 || | |
1182 | reg == BSD_HWS_PGA_GEN7 || | |
1183 | reg == BLT_HWS_PGA_GEN7) | |
1184 | return false; | |
1185 | ||
1186 | if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || | |
1187 | reg == GEN6_BSD_RNCID) | |
1188 | return false; | |
1189 | ||
1190 | if (reg == GEN6_BLITTER_ECOSKPD) | |
1191 | return false; | |
1192 | ||
1193 | if (reg >= 0x4000c && | |
1194 | reg <= 0x4002c) | |
1195 | return false; | |
1196 | ||
1197 | if (reg >= 0x4f000 && | |
1198 | reg <= 0x4f08f) | |
1199 | return false; | |
1200 | ||
1201 | if (reg >= 0x4f100 && | |
1202 | reg <= 0x4f11f) | |
1203 | return false; | |
1204 | ||
1205 | if (reg >= VLV_MASTER_IER && | |
1206 | reg <= GEN6_PMIER) | |
1207 | return false; | |
1208 | ||
1209 | if (reg >= FENCE_REG_SANDYBRIDGE_0 && | |
1210 | reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) | |
1211 | return false; | |
1212 | ||
1213 | if (reg >= VLV_IIR_RW && | |
1214 | reg <= VLV_ISR) | |
1215 | return false; | |
1216 | ||
1217 | if (reg == FORCEWAKE_VLV || | |
1218 | reg == FORCEWAKE_ACK_VLV) | |
1219 | return false; | |
1220 | ||
1221 | if (reg == GEN6_GDRST) | |
1222 | return false; | |
1223 | ||
1224 | return true; | |
1225 | } | |
1226 | ||
f7000883 AK |
1227 | #define __i915_read(x, y) \ |
1228 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
1229 | u##x val = 0; \ | |
1230 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
c937504e KP |
1231 | unsigned long irqflags; \ |
1232 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | |
1233 | if (dev_priv->forcewake_count == 0) \ | |
1234 | dev_priv->display.force_wake_get(dev_priv); \ | |
f7000883 | 1235 | val = read##y(dev_priv->regs + reg); \ |
c937504e KP |
1236 | if (dev_priv->forcewake_count == 0) \ |
1237 | dev_priv->display.force_wake_put(dev_priv); \ | |
1238 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | |
f7dff0c9 JB |
1239 | } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
1240 | val = read##y(dev_priv->regs + reg + 0x180000); \ | |
f7000883 AK |
1241 | } else { \ |
1242 | val = read##y(dev_priv->regs + reg); \ | |
1243 | } \ | |
1244 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | |
1245 | return val; \ | |
1246 | } | |
1247 | ||
1248 | __i915_read(8, b) | |
1249 | __i915_read(16, w) | |
1250 | __i915_read(32, l) | |
1251 | __i915_read(64, q) | |
1252 | #undef __i915_read | |
1253 | ||
1254 | #define __i915_write(x, y) \ | |
1255 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
67a3744f | 1256 | u32 __fifo_ret = 0; \ |
f7000883 AK |
1257 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1258 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
67a3744f | 1259 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
f7000883 | 1260 | } \ |
f7dff0c9 JB |
1261 | if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
1262 | write##y(val, dev_priv->regs + reg + 0x180000); \ | |
1263 | } else { \ | |
1264 | write##y(val, dev_priv->regs + reg); \ | |
1265 | } \ | |
67a3744f BW |
1266 | if (unlikely(__fifo_ret)) { \ |
1267 | gen6_gt_check_fifodbg(dev_priv); \ | |
1268 | } \ | |
f7000883 AK |
1269 | } |
1270 | __i915_write(8, b) | |
1271 | __i915_write(16, w) | |
1272 | __i915_write(32, l) | |
1273 | __i915_write(64, q) | |
1274 | #undef __i915_write |