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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
354ff967 | 39 | #include "drm_crtc_helper.h" |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a35d9d3c | 50 | int i915_panel_ignore_lid __read_mostly = 0; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 BW |
52 | MODULE_PARM_DESC(panel_ignore_lid, |
53 | "Override lid status (0=autodetect [default], 1=lid open, " | |
54 | "-1=lid closed)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
ac668088 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
c0f372b3 | 69 | "Enable power-saving render C-state 6 (default: -1 (use per-chip default)"); |
ac668088 | 70 | |
4415e63b | 71 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 72 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
73 | MODULE_PARM_DESC(i915_enable_fbc, |
74 | "Enable frame buffer compression for power savings " | |
cd0de039 | 75 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 76 | |
a35d9d3c | 77 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 78 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
79 | MODULE_PARM_DESC(lvds_downclock, |
80 | "Use panel (LVDS/eDP) downclocking for power savings " | |
81 | "(default: false)"); | |
33814341 | 82 | |
4415e63b | 83 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 84 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
85 | MODULE_PARM_DESC(lvds_use_ssc, |
86 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 87 | "(default: auto from VBT)"); |
a7615030 | 88 | |
a35d9d3c | 89 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 90 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 BW |
91 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
92 | "Override selection of SDVO panel mode in the VBT " | |
93 | "(default: auto)"); | |
5a1e5b6c | 94 | |
a35d9d3c | 95 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 96 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 97 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 98 | |
a35d9d3c | 99 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 100 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
101 | MODULE_PARM_DESC(enable_hangcheck, |
102 | "Periodically check GPU activity for detecting hangs. " | |
103 | "WARNING: Disabling this can cause system wide hangs. " | |
104 | "(default: true)"); | |
3e0dc6b0 | 105 | |
e21af88d DV |
106 | bool i915_enable_ppgtt __read_mostly = 1; |
107 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600); | |
108 | MODULE_PARM_DESC(i915_enable_ppgtt, | |
109 | "Enable PPGTT (default: true)"); | |
110 | ||
112b715e | 111 | static struct drm_driver driver; |
1f7a6e37 | 112 | extern int intel_agp_enabled; |
112b715e | 113 | |
cfdf1fa2 | 114 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 115 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 116 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
117 | .vendor = 0x8086, \ |
118 | .device = id, \ | |
119 | .subvendor = PCI_ANY_ID, \ | |
120 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
121 | .driver_data = (unsigned long) info } |
122 | ||
9a7e8492 | 123 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 124 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 125 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
126 | }; |
127 | ||
9a7e8492 | 128 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 129 | .gen = 2, |
31578148 | 130 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
131 | }; |
132 | ||
9a7e8492 | 133 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 134 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 135 | .cursor_needs_physical = 1, |
31578148 | 136 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
137 | }; |
138 | ||
9a7e8492 | 139 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 140 | .gen = 2, |
31578148 | 141 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
142 | }; |
143 | ||
9a7e8492 | 144 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 145 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 146 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 147 | }; |
9a7e8492 | 148 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 149 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 150 | .cursor_needs_physical = 1, |
31578148 | 151 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 152 | .supports_tv = 1, |
cfdf1fa2 | 153 | }; |
9a7e8492 | 154 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 155 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 156 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 157 | }; |
9a7e8492 | 158 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 159 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 160 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 161 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 162 | .supports_tv = 1, |
cfdf1fa2 KH |
163 | }; |
164 | ||
9a7e8492 | 165 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 166 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 167 | .has_hotplug = 1, |
31578148 | 168 | .has_overlay = 1, |
cfdf1fa2 KH |
169 | }; |
170 | ||
9a7e8492 | 171 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 172 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 173 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 174 | .has_overlay = 1, |
a6c45cf0 | 175 | .supports_tv = 1, |
cfdf1fa2 KH |
176 | }; |
177 | ||
9a7e8492 | 178 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 179 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 180 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 181 | .has_overlay = 1, |
cfdf1fa2 KH |
182 | }; |
183 | ||
9a7e8492 | 184 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 185 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 186 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 187 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
188 | }; |
189 | ||
9a7e8492 | 190 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 191 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 192 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 193 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 194 | .supports_tv = 1, |
92f49d9c | 195 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
196 | }; |
197 | ||
9a7e8492 | 198 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 199 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 200 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 201 | .has_overlay = 1, |
cfdf1fa2 KH |
202 | }; |
203 | ||
9a7e8492 | 204 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 205 | .gen = 5, |
5a117db7 | 206 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 207 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
208 | }; |
209 | ||
9a7e8492 | 210 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 211 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 212 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 213 | .has_fbc = 1, |
92f49d9c | 214 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
215 | }; |
216 | ||
9a7e8492 | 217 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 218 | .gen = 6, |
c96c3a8c | 219 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 220 | .has_bsd_ring = 1, |
549f7365 | 221 | .has_blt_ring = 1, |
3d29b842 | 222 | .has_llc = 1, |
f6e450a6 EA |
223 | }; |
224 | ||
9a7e8492 | 225 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 226 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 227 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 228 | .has_fbc = 1, |
881f47b6 | 229 | .has_bsd_ring = 1, |
549f7365 | 230 | .has_blt_ring = 1, |
3d29b842 | 231 | .has_llc = 1, |
a13e4093 EA |
232 | }; |
233 | ||
c76b615c JB |
234 | static const struct intel_device_info intel_ivybridge_d_info = { |
235 | .is_ivybridge = 1, .gen = 7, | |
236 | .need_gfx_hws = 1, .has_hotplug = 1, | |
237 | .has_bsd_ring = 1, | |
238 | .has_blt_ring = 1, | |
3d29b842 | 239 | .has_llc = 1, |
c76b615c JB |
240 | }; |
241 | ||
242 | static const struct intel_device_info intel_ivybridge_m_info = { | |
243 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, | |
244 | .need_gfx_hws = 1, .has_hotplug = 1, | |
245 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ | |
246 | .has_bsd_ring = 1, | |
247 | .has_blt_ring = 1, | |
3d29b842 | 248 | .has_llc = 1, |
c76b615c JB |
249 | }; |
250 | ||
6103da0d CW |
251 | static const struct pci_device_id pciidlist[] = { /* aka */ |
252 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
253 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
254 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 255 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
256 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
257 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
258 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
259 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
260 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
261 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
262 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
263 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
264 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
265 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
266 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
267 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
268 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
269 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
270 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
271 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
272 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
273 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
274 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
275 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
276 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
277 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 278 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
279 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
280 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
281 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
282 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 283 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
284 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
285 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 286 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 287 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 288 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 289 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
290 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
291 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
292 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
293 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
294 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
49ae35f2 | 295 | {0, 0, 0} |
1da177e4 LT |
296 | }; |
297 | ||
79e53945 JB |
298 | #if defined(CONFIG_DRM_I915_KMS) |
299 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
300 | #endif | |
301 | ||
3bad0781 | 302 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
90711d50 | 303 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
3bad0781 | 304 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
c792513b | 305 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
3bad0781 | 306 | |
0206e353 | 307 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
308 | { |
309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
310 | struct pci_dev *pch; | |
311 | ||
312 | /* | |
313 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
314 | * make graphics device passthrough work easy for VMM, that only | |
315 | * need to expose ISA bridge to let driver know the real hardware | |
316 | * underneath. This is a requirement from virtualization team. | |
317 | */ | |
318 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
319 | if (pch) { | |
320 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
321 | int id; | |
322 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
323 | ||
90711d50 JB |
324 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
325 | dev_priv->pch_type = PCH_IBX; | |
326 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
327 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
3bad0781 ZW |
328 | dev_priv->pch_type = PCH_CPT; |
329 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
c792513b JB |
330 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
331 | /* PantherPoint is CPT compatible */ | |
332 | dev_priv->pch_type = PCH_CPT; | |
333 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | |
3bad0781 ZW |
334 | } |
335 | } | |
336 | pci_dev_put(pch); | |
337 | } | |
338 | } | |
339 | ||
8d715f00 | 340 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
eb43f4af CW |
341 | { |
342 | int count; | |
343 | ||
344 | count = 0; | |
345 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
346 | udelay(10); | |
347 | ||
348 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
349 | POSTING_READ(FORCEWAKE); | |
350 | ||
351 | count = 0; | |
352 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) | |
353 | udelay(10); | |
354 | } | |
355 | ||
8d715f00 KP |
356 | void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
357 | { | |
358 | int count; | |
359 | ||
360 | count = 0; | |
361 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) | |
362 | udelay(10); | |
363 | ||
364 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1); | |
365 | POSTING_READ(FORCEWAKE_MT); | |
366 | ||
367 | count = 0; | |
368 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) | |
369 | udelay(10); | |
370 | } | |
371 | ||
fcca7926 BW |
372 | /* |
373 | * Generally this is called implicitly by the register read function. However, | |
374 | * if some sequence requires the GT to not power down then this function should | |
375 | * be called at the beginning of the sequence followed by a call to | |
376 | * gen6_gt_force_wake_put() at the end of the sequence. | |
377 | */ | |
378 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
379 | { | |
9f1f46a4 | 380 | unsigned long irqflags; |
fcca7926 | 381 | |
9f1f46a4 DV |
382 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
383 | if (dev_priv->forcewake_count++ == 0) | |
8d715f00 | 384 | dev_priv->display.force_wake_get(dev_priv); |
9f1f46a4 | 385 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
386 | } |
387 | ||
ee64cbdb BW |
388 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
389 | { | |
390 | u32 gtfifodbg; | |
391 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); | |
392 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, | |
393 | "MMIO read or write has been dropped %x\n", gtfifodbg)) | |
394 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); | |
395 | } | |
396 | ||
8d715f00 | 397 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
eb43f4af CW |
398 | { |
399 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
ee64cbdb BW |
400 | /* The below doubles as a POSTING_READ */ |
401 | gen6_gt_check_fifodbg(dev_priv); | |
eb43f4af CW |
402 | } |
403 | ||
8d715f00 KP |
404 | void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
405 | { | |
406 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0); | |
ee64cbdb BW |
407 | /* The below doubles as a POSTING_READ */ |
408 | gen6_gt_check_fifodbg(dev_priv); | |
8d715f00 KP |
409 | } |
410 | ||
fcca7926 BW |
411 | /* |
412 | * see gen6_gt_force_wake_get() | |
413 | */ | |
414 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
415 | { | |
9f1f46a4 | 416 | unsigned long irqflags; |
fcca7926 | 417 | |
9f1f46a4 DV |
418 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
419 | if (--dev_priv->forcewake_count == 0) | |
8d715f00 | 420 | dev_priv->display.force_wake_put(dev_priv); |
9f1f46a4 | 421 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
422 | } |
423 | ||
67a3744f | 424 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
91355834 | 425 | { |
67a3744f BW |
426 | int ret = 0; |
427 | ||
0206e353 | 428 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
95736720 CW |
429 | int loop = 500; |
430 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
431 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { | |
432 | udelay(10); | |
433 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
434 | } | |
67a3744f BW |
435 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
436 | ++ret; | |
95736720 | 437 | dev_priv->gt_fifo_count = fifo; |
91355834 | 438 | } |
95736720 | 439 | dev_priv->gt_fifo_count--; |
67a3744f BW |
440 | |
441 | return ret; | |
91355834 CW |
442 | } |
443 | ||
84b79f8d | 444 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 445 | { |
61caf87c RW |
446 | struct drm_i915_private *dev_priv = dev->dev_private; |
447 | ||
5bcf719b DA |
448 | drm_kms_helper_poll_disable(dev); |
449 | ||
ba8bbcf6 | 450 | pci_save_state(dev->pdev); |
ba8bbcf6 | 451 | |
5669fcac | 452 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 453 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
454 | int error = i915_gem_idle(dev); |
455 | if (error) { | |
226485e9 | 456 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
457 | "GEM idle failed, resume might fail\n"); |
458 | return error; | |
459 | } | |
226485e9 | 460 | drm_irq_uninstall(dev); |
5669fcac JB |
461 | } |
462 | ||
9e06dd39 JB |
463 | i915_save_state(dev); |
464 | ||
44834a67 | 465 | intel_opregion_fini(dev); |
8ee1c3db | 466 | |
84b79f8d RW |
467 | /* Modeset on resume, not lid events */ |
468 | dev_priv->modeset_on_lid = 0; | |
61caf87c | 469 | |
3fa016a0 DA |
470 | console_lock(); |
471 | intel_fbdev_set_suspend(dev, 1); | |
472 | console_unlock(); | |
473 | ||
61caf87c | 474 | return 0; |
84b79f8d RW |
475 | } |
476 | ||
6a9ee8af | 477 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
478 | { |
479 | int error; | |
480 | ||
481 | if (!dev || !dev->dev_private) { | |
482 | DRM_ERROR("dev: %p\n", dev); | |
483 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
484 | return -ENODEV; | |
485 | } | |
486 | ||
487 | if (state.event == PM_EVENT_PRETHAW) | |
488 | return 0; | |
489 | ||
5bcf719b DA |
490 | |
491 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
492 | return 0; | |
6eecba33 | 493 | |
84b79f8d RW |
494 | error = i915_drm_freeze(dev); |
495 | if (error) | |
496 | return error; | |
497 | ||
b932ccb5 DA |
498 | if (state.event == PM_EVENT_SUSPEND) { |
499 | /* Shut down the device */ | |
500 | pci_disable_device(dev->pdev); | |
501 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
502 | } | |
ba8bbcf6 JB |
503 | |
504 | return 0; | |
505 | } | |
506 | ||
84b79f8d | 507 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 508 | { |
5669fcac | 509 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 510 | int error = 0; |
8ee1c3db | 511 | |
d1c3b177 CW |
512 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
513 | mutex_lock(&dev->struct_mutex); | |
514 | i915_gem_restore_gtt_mappings(dev); | |
515 | mutex_unlock(&dev->struct_mutex); | |
516 | } | |
517 | ||
61caf87c | 518 | i915_restore_state(dev); |
44834a67 | 519 | intel_opregion_setup(dev); |
61caf87c | 520 | |
5669fcac JB |
521 | /* KMS EnterVT equivalent */ |
522 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
523 | mutex_lock(&dev->struct_mutex); | |
524 | dev_priv->mm.suspended = 0; | |
525 | ||
f691e2f4 | 526 | error = i915_gem_init_hw(dev); |
5669fcac | 527 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 528 | |
9fb526db KP |
529 | if (HAS_PCH_SPLIT(dev)) |
530 | ironlake_init_pch_refclk(dev); | |
531 | ||
500f7147 | 532 | drm_mode_config_reset(dev); |
226485e9 | 533 | drm_irq_install(dev); |
84b79f8d | 534 | |
354ff967 ZY |
535 | /* Resume the modeset for every activated CRTC */ |
536 | drm_helper_resume_force_mode(dev); | |
5669fcac | 537 | |
ac668088 | 538 | if (IS_IRONLAKE_M(dev)) |
d5bb081b JB |
539 | ironlake_enable_rc6(dev); |
540 | } | |
1daed3fb | 541 | |
44834a67 CW |
542 | intel_opregion_init(dev); |
543 | ||
c9354c85 | 544 | dev_priv->modeset_on_lid = 0; |
06891e27 | 545 | |
3fa016a0 DA |
546 | console_lock(); |
547 | intel_fbdev_set_suspend(dev, 0); | |
548 | console_unlock(); | |
84b79f8d RW |
549 | return error; |
550 | } | |
551 | ||
6a9ee8af | 552 | int i915_resume(struct drm_device *dev) |
84b79f8d | 553 | { |
6eecba33 CW |
554 | int ret; |
555 | ||
5bcf719b DA |
556 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
557 | return 0; | |
558 | ||
84b79f8d RW |
559 | if (pci_enable_device(dev->pdev)) |
560 | return -EIO; | |
561 | ||
562 | pci_set_master(dev->pdev); | |
563 | ||
6eecba33 CW |
564 | ret = i915_drm_thaw(dev); |
565 | if (ret) | |
566 | return ret; | |
567 | ||
568 | drm_kms_helper_poll_enable(dev); | |
569 | return 0; | |
ba8bbcf6 JB |
570 | } |
571 | ||
dc96e9b8 CW |
572 | static int i8xx_do_reset(struct drm_device *dev, u8 flags) |
573 | { | |
574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
575 | ||
576 | if (IS_I85X(dev)) | |
577 | return -ENODEV; | |
578 | ||
579 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
580 | POSTING_READ(D_STATE); | |
581 | ||
582 | if (IS_I830(dev) || IS_845G(dev)) { | |
583 | I915_WRITE(DEBUG_RESET_I830, | |
584 | DEBUG_RESET_DISPLAY | | |
585 | DEBUG_RESET_RENDER | | |
586 | DEBUG_RESET_FULL); | |
587 | POSTING_READ(DEBUG_RESET_I830); | |
588 | msleep(1); | |
589 | ||
590 | I915_WRITE(DEBUG_RESET_I830, 0); | |
591 | POSTING_READ(DEBUG_RESET_I830); | |
592 | } | |
593 | ||
594 | msleep(1); | |
595 | ||
596 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
597 | POSTING_READ(D_STATE); | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
f49f0586 KG |
602 | static int i965_reset_complete(struct drm_device *dev) |
603 | { | |
604 | u8 gdrst; | |
eeccdcac | 605 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
f49f0586 KG |
606 | return gdrst & 0x1; |
607 | } | |
608 | ||
0573ed4a KG |
609 | static int i965_do_reset(struct drm_device *dev, u8 flags) |
610 | { | |
611 | u8 gdrst; | |
612 | ||
ae681d96 CW |
613 | /* |
614 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
615 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
616 | * triggers the reset; when done, the hardware will clear it. | |
617 | */ | |
0573ed4a KG |
618 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
619 | pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1); | |
620 | ||
621 | return wait_for(i965_reset_complete(dev), 500); | |
622 | } | |
623 | ||
624 | static int ironlake_do_reset(struct drm_device *dev, u8 flags) | |
625 | { | |
626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
627 | u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
628 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); | |
629 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
ba8bbcf6 JB |
630 | } |
631 | ||
cff458c2 EA |
632 | static int gen6_do_reset(struct drm_device *dev, u8 flags) |
633 | { | |
634 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b6e45f86 KP |
635 | int ret; |
636 | unsigned long irqflags; | |
cff458c2 | 637 | |
286fed41 KP |
638 | /* Hold gt_lock across reset to prevent any register access |
639 | * with forcewake not set correctly | |
640 | */ | |
b6e45f86 | 641 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
286fed41 KP |
642 | |
643 | /* Reset the chip */ | |
644 | ||
645 | /* GEN6_GDRST is not in the gt power well, no need to check | |
646 | * for fifo space for the write or forcewake the chip for | |
647 | * the read | |
648 | */ | |
649 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
650 | ||
651 | /* Spin waiting for the device to ack the reset request */ | |
652 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
653 | ||
654 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | |
b6e45f86 KP |
655 | if (dev_priv->forcewake_count) |
656 | dev_priv->display.force_wake_get(dev_priv); | |
286fed41 KP |
657 | else |
658 | dev_priv->display.force_wake_put(dev_priv); | |
659 | ||
660 | /* Restore fifo count */ | |
661 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
662 | ||
b6e45f86 KP |
663 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
664 | return ret; | |
cff458c2 EA |
665 | } |
666 | ||
11ed50ec | 667 | /** |
f3953dcb | 668 | * i915_reset - reset chip after a hang |
11ed50ec BG |
669 | * @dev: drm device to reset |
670 | * @flags: reset domains | |
671 | * | |
672 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
673 | * reset or otherwise an error code. | |
674 | * | |
675 | * Procedure is fairly simple: | |
676 | * - reset the chip using the reset reg | |
677 | * - re-init context state | |
678 | * - re-init hardware status page | |
679 | * - re-init ring buffer | |
680 | * - re-init interrupt state | |
681 | * - re-init display | |
682 | */ | |
f803aa55 | 683 | int i915_reset(struct drm_device *dev, u8 flags) |
11ed50ec BG |
684 | { |
685 | drm_i915_private_t *dev_priv = dev->dev_private; | |
11ed50ec BG |
686 | /* |
687 | * We really should only reset the display subsystem if we actually | |
688 | * need to | |
689 | */ | |
690 | bool need_display = true; | |
0573ed4a | 691 | int ret; |
11ed50ec | 692 | |
d78cb50b CW |
693 | if (!i915_try_reset) |
694 | return 0; | |
695 | ||
340479aa CW |
696 | if (!mutex_trylock(&dev->struct_mutex)) |
697 | return -EBUSY; | |
11ed50ec | 698 | |
069efc1d | 699 | i915_gem_reset(dev); |
77f01230 | 700 | |
f803aa55 | 701 | ret = -ENODEV; |
ae681d96 CW |
702 | if (get_seconds() - dev_priv->last_gpu_reset < 5) { |
703 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); | |
704 | } else switch (INTEL_INFO(dev)->gen) { | |
1083694a | 705 | case 7: |
cff458c2 EA |
706 | case 6: |
707 | ret = gen6_do_reset(dev, flags); | |
708 | break; | |
f803aa55 | 709 | case 5: |
0573ed4a | 710 | ret = ironlake_do_reset(dev, flags); |
f803aa55 CW |
711 | break; |
712 | case 4: | |
0573ed4a | 713 | ret = i965_do_reset(dev, flags); |
f803aa55 | 714 | break; |
dc96e9b8 CW |
715 | case 2: |
716 | ret = i8xx_do_reset(dev, flags); | |
717 | break; | |
f803aa55 | 718 | } |
ae681d96 | 719 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 720 | if (ret) { |
f803aa55 | 721 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 722 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 723 | return ret; |
11ed50ec BG |
724 | } |
725 | ||
726 | /* Ok, now get things going again... */ | |
727 | ||
728 | /* | |
729 | * Everything depends on having the GTT running, so we need to start | |
730 | * there. Fortunately we don't need to do this unless we reset the | |
731 | * chip at a PCI level. | |
732 | * | |
733 | * Next we need to restore the context, but we don't use those | |
734 | * yet either... | |
735 | * | |
736 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
737 | * was running at the time of the reset (i.e. we weren't VT | |
738 | * switched away). | |
739 | */ | |
740 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 741 | !dev_priv->mm.suspended) { |
11ed50ec | 742 | dev_priv->mm.suspended = 0; |
75a6898f | 743 | |
f691e2f4 DV |
744 | i915_gem_init_swizzling(dev); |
745 | ||
1ec14ad3 | 746 | dev_priv->ring[RCS].init(&dev_priv->ring[RCS]); |
75a6898f | 747 | if (HAS_BSD(dev)) |
1ec14ad3 | 748 | dev_priv->ring[VCS].init(&dev_priv->ring[VCS]); |
75a6898f | 749 | if (HAS_BLT(dev)) |
1ec14ad3 | 750 | dev_priv->ring[BCS].init(&dev_priv->ring[BCS]); |
75a6898f | 751 | |
e21af88d DV |
752 | i915_gem_init_ppgtt(dev); |
753 | ||
11ed50ec BG |
754 | mutex_unlock(&dev->struct_mutex); |
755 | drm_irq_uninstall(dev); | |
500f7147 | 756 | drm_mode_config_reset(dev); |
11ed50ec BG |
757 | drm_irq_install(dev); |
758 | mutex_lock(&dev->struct_mutex); | |
759 | } | |
760 | ||
9fd98141 CW |
761 | mutex_unlock(&dev->struct_mutex); |
762 | ||
11ed50ec | 763 | /* |
9fd98141 CW |
764 | * Perform a full modeset as on later generations, e.g. Ironlake, we may |
765 | * need to retrain the display link and cannot just restore the register | |
766 | * values. | |
11ed50ec | 767 | */ |
9fd98141 CW |
768 | if (need_display) { |
769 | mutex_lock(&dev->mode_config.mutex); | |
770 | drm_helper_resume_force_mode(dev); | |
771 | mutex_unlock(&dev->mode_config.mutex); | |
772 | } | |
11ed50ec | 773 | |
11ed50ec BG |
774 | return 0; |
775 | } | |
776 | ||
777 | ||
112b715e KH |
778 | static int __devinit |
779 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
780 | { | |
5fe49d86 CW |
781 | /* Only bind to function 0 of the device. Early generations |
782 | * used function 1 as a placeholder for multi-head. This causes | |
783 | * us confusion instead, especially on the systems where both | |
784 | * functions have the same PCI-ID! | |
785 | */ | |
786 | if (PCI_FUNC(pdev->devfn)) | |
787 | return -ENODEV; | |
788 | ||
dcdb1674 | 789 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
790 | } |
791 | ||
792 | static void | |
793 | i915_pci_remove(struct pci_dev *pdev) | |
794 | { | |
795 | struct drm_device *dev = pci_get_drvdata(pdev); | |
796 | ||
797 | drm_put_dev(dev); | |
798 | } | |
799 | ||
84b79f8d | 800 | static int i915_pm_suspend(struct device *dev) |
112b715e | 801 | { |
84b79f8d RW |
802 | struct pci_dev *pdev = to_pci_dev(dev); |
803 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
804 | int error; | |
112b715e | 805 | |
84b79f8d RW |
806 | if (!drm_dev || !drm_dev->dev_private) { |
807 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
808 | return -ENODEV; | |
809 | } | |
112b715e | 810 | |
5bcf719b DA |
811 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
812 | return 0; | |
813 | ||
84b79f8d RW |
814 | error = i915_drm_freeze(drm_dev); |
815 | if (error) | |
816 | return error; | |
112b715e | 817 | |
84b79f8d RW |
818 | pci_disable_device(pdev); |
819 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 820 | |
84b79f8d | 821 | return 0; |
cbda12d7 ZW |
822 | } |
823 | ||
84b79f8d | 824 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 825 | { |
84b79f8d RW |
826 | struct pci_dev *pdev = to_pci_dev(dev); |
827 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
828 | ||
829 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
830 | } |
831 | ||
84b79f8d | 832 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 833 | { |
84b79f8d RW |
834 | struct pci_dev *pdev = to_pci_dev(dev); |
835 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
836 | ||
837 | if (!drm_dev || !drm_dev->dev_private) { | |
838 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
839 | return -ENODEV; | |
840 | } | |
841 | ||
842 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
843 | } |
844 | ||
84b79f8d | 845 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 846 | { |
84b79f8d RW |
847 | struct pci_dev *pdev = to_pci_dev(dev); |
848 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
849 | ||
850 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
851 | } |
852 | ||
84b79f8d | 853 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 854 | { |
84b79f8d RW |
855 | struct pci_dev *pdev = to_pci_dev(dev); |
856 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 857 | |
61caf87c | 858 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
859 | } |
860 | ||
b4b78d12 | 861 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
862 | .suspend = i915_pm_suspend, |
863 | .resume = i915_pm_resume, | |
864 | .freeze = i915_pm_freeze, | |
865 | .thaw = i915_pm_thaw, | |
866 | .poweroff = i915_pm_poweroff, | |
867 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
868 | }; |
869 | ||
de151cf6 JB |
870 | static struct vm_operations_struct i915_gem_vm_ops = { |
871 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
872 | .open = drm_gem_vm_open, |
873 | .close = drm_gem_vm_close, | |
de151cf6 JB |
874 | }; |
875 | ||
e08e96de AV |
876 | static const struct file_operations i915_driver_fops = { |
877 | .owner = THIS_MODULE, | |
878 | .open = drm_open, | |
879 | .release = drm_release, | |
880 | .unlocked_ioctl = drm_ioctl, | |
881 | .mmap = drm_gem_mmap, | |
882 | .poll = drm_poll, | |
883 | .fasync = drm_fasync, | |
884 | .read = drm_read, | |
885 | #ifdef CONFIG_COMPAT | |
886 | .compat_ioctl = i915_compat_ioctl, | |
887 | #endif | |
888 | .llseek = noop_llseek, | |
889 | }; | |
890 | ||
1da177e4 | 891 | static struct drm_driver driver = { |
0c54781b MW |
892 | /* Don't use MTRRs here; the Xserver or userspace app should |
893 | * deal with them for Intel hardware. | |
792d2b9a | 894 | */ |
673a394b EA |
895 | .driver_features = |
896 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
897 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 898 | .load = i915_driver_load, |
ba8bbcf6 | 899 | .unload = i915_driver_unload, |
673a394b | 900 | .open = i915_driver_open, |
22eae947 DA |
901 | .lastclose = i915_driver_lastclose, |
902 | .preclose = i915_driver_preclose, | |
673a394b | 903 | .postclose = i915_driver_postclose, |
d8e29209 RW |
904 | |
905 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
906 | .suspend = i915_suspend, | |
907 | .resume = i915_resume, | |
908 | ||
cda17380 | 909 | .device_is_agp = i915_driver_device_is_agp, |
1da177e4 | 910 | .reclaim_buffers = drm_core_reclaim_buffers, |
7c1c2871 DA |
911 | .master_create = i915_master_create, |
912 | .master_destroy = i915_master_destroy, | |
955b12de | 913 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
914 | .debugfs_init = i915_debugfs_init, |
915 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 916 | #endif |
673a394b EA |
917 | .gem_init_object = i915_gem_init_object, |
918 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 919 | .gem_vm_ops = &i915_gem_vm_ops, |
ff72145b DA |
920 | .dumb_create = i915_gem_dumb_create, |
921 | .dumb_map_offset = i915_gem_mmap_gtt, | |
922 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 | 923 | .ioctls = i915_ioctls, |
e08e96de | 924 | .fops = &i915_driver_fops, |
22eae947 DA |
925 | .name = DRIVER_NAME, |
926 | .desc = DRIVER_DESC, | |
927 | .date = DRIVER_DATE, | |
928 | .major = DRIVER_MAJOR, | |
929 | .minor = DRIVER_MINOR, | |
930 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
931 | }; |
932 | ||
8410ea3b DA |
933 | static struct pci_driver i915_pci_driver = { |
934 | .name = DRIVER_NAME, | |
935 | .id_table = pciidlist, | |
936 | .probe = i915_pci_probe, | |
937 | .remove = i915_pci_remove, | |
938 | .driver.pm = &i915_pm_ops, | |
939 | }; | |
940 | ||
1da177e4 LT |
941 | static int __init i915_init(void) |
942 | { | |
1f7a6e37 ZW |
943 | if (!intel_agp_enabled) { |
944 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
945 | return -ENODEV; | |
946 | } | |
947 | ||
1da177e4 | 948 | driver.num_ioctls = i915_max_ioctl; |
79e53945 JB |
949 | |
950 | /* | |
951 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
952 | * explicitly disabled with the module pararmeter. | |
953 | * | |
954 | * Otherwise, just follow the parameter (defaulting to off). | |
955 | * | |
956 | * Allow optional vga_text_mode_force boot option to override | |
957 | * the default behavior. | |
958 | */ | |
959 | #if defined(CONFIG_DRM_I915_KMS) | |
960 | if (i915_modeset != 0) | |
961 | driver.driver_features |= DRIVER_MODESET; | |
962 | #endif | |
963 | if (i915_modeset == 1) | |
964 | driver.driver_features |= DRIVER_MODESET; | |
965 | ||
966 | #ifdef CONFIG_VGA_CONSOLE | |
967 | if (vgacon_text_force() && i915_modeset == -1) | |
968 | driver.driver_features &= ~DRIVER_MODESET; | |
969 | #endif | |
970 | ||
3885c6bb CW |
971 | if (!(driver.driver_features & DRIVER_MODESET)) |
972 | driver.get_vblank_timestamp = NULL; | |
973 | ||
8410ea3b | 974 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
975 | } |
976 | ||
977 | static void __exit i915_exit(void) | |
978 | { | |
8410ea3b | 979 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
980 | } |
981 | ||
982 | module_init(i915_init); | |
983 | module_exit(i915_exit); | |
984 | ||
b5e89ed5 DA |
985 | MODULE_AUTHOR(DRIVER_AUTHOR); |
986 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 987 | MODULE_LICENSE("GPL and additional rights"); |
f7000883 | 988 | |
f7000883 AK |
989 | #define __i915_read(x, y) \ |
990 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
991 | u##x val = 0; \ | |
992 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
c937504e KP |
993 | unsigned long irqflags; \ |
994 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | |
995 | if (dev_priv->forcewake_count == 0) \ | |
996 | dev_priv->display.force_wake_get(dev_priv); \ | |
f7000883 | 997 | val = read##y(dev_priv->regs + reg); \ |
c937504e KP |
998 | if (dev_priv->forcewake_count == 0) \ |
999 | dev_priv->display.force_wake_put(dev_priv); \ | |
1000 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | |
f7000883 AK |
1001 | } else { \ |
1002 | val = read##y(dev_priv->regs + reg); \ | |
1003 | } \ | |
1004 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | |
1005 | return val; \ | |
1006 | } | |
1007 | ||
1008 | __i915_read(8, b) | |
1009 | __i915_read(16, w) | |
1010 | __i915_read(32, l) | |
1011 | __i915_read(64, q) | |
1012 | #undef __i915_read | |
1013 | ||
1014 | #define __i915_write(x, y) \ | |
1015 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
67a3744f | 1016 | u32 __fifo_ret = 0; \ |
f7000883 AK |
1017 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1018 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
67a3744f | 1019 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
f7000883 AK |
1020 | } \ |
1021 | write##y(val, dev_priv->regs + reg); \ | |
67a3744f BW |
1022 | if (unlikely(__fifo_ret)) { \ |
1023 | gen6_gt_check_fifodbg(dev_priv); \ | |
1024 | } \ | |
f7000883 AK |
1025 | } |
1026 | __i915_write(8, b) | |
1027 | __i915_write(16, w) | |
1028 | __i915_write(32, l) | |
1029 | __i915_write(64, q) | |
1030 | #undef __i915_write |