]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
354ff967 | 38 | #include "drm_crtc_helper.h" |
79e53945 | 39 | |
d6073d77 | 40 | static int i915_modeset = -1; |
79e53945 JB |
41 | module_param_named(modeset, i915_modeset, int, 0400); |
42 | ||
43 | unsigned int i915_fbpercrtc = 0; | |
44 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); | |
1da177e4 | 45 | |
652c393a | 46 | unsigned int i915_powersave = 1; |
0aa99277 | 47 | module_param_named(powersave, i915_powersave, int, 0600); |
652c393a | 48 | |
ac668088 CW |
49 | unsigned int i915_enable_rc6 = 0; |
50 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); | |
51 | ||
33814341 JB |
52 | unsigned int i915_lvds_downclock = 0; |
53 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); | |
54 | ||
a7615030 CW |
55 | unsigned int i915_panel_use_ssc = 1; |
56 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); | |
57 | ||
d78cb50b CW |
58 | bool i915_try_reset = true; |
59 | module_param_named(reset, i915_try_reset, bool, 0600); | |
60 | ||
112b715e | 61 | static struct drm_driver driver; |
1f7a6e37 | 62 | extern int intel_agp_enabled; |
112b715e | 63 | |
cfdf1fa2 | 64 | #define INTEL_VGA_DEVICE(id, info) { \ |
49ae35f2 | 65 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ |
934f992c | 66 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
67 | .vendor = 0x8086, \ |
68 | .device = id, \ | |
69 | .subvendor = PCI_ANY_ID, \ | |
70 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
71 | .driver_data = (unsigned long) info } |
72 | ||
9a7e8492 | 73 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 74 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 75 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
76 | }; |
77 | ||
9a7e8492 | 78 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 79 | .gen = 2, |
31578148 | 80 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
81 | }; |
82 | ||
9a7e8492 | 83 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 84 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 85 | .cursor_needs_physical = 1, |
31578148 | 86 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
87 | }; |
88 | ||
9a7e8492 | 89 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 90 | .gen = 2, |
31578148 | 91 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
92 | }; |
93 | ||
9a7e8492 | 94 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 95 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 96 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 97 | }; |
9a7e8492 | 98 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 99 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 100 | .cursor_needs_physical = 1, |
31578148 | 101 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 102 | .supports_tv = 1, |
cfdf1fa2 | 103 | }; |
9a7e8492 | 104 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 105 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 106 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 107 | }; |
9a7e8492 | 108 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 109 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 110 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 111 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 112 | .supports_tv = 1, |
cfdf1fa2 KH |
113 | }; |
114 | ||
9a7e8492 | 115 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 116 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 117 | .has_hotplug = 1, |
31578148 | 118 | .has_overlay = 1, |
cfdf1fa2 KH |
119 | }; |
120 | ||
9a7e8492 | 121 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 122 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 123 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 124 | .has_overlay = 1, |
a6c45cf0 | 125 | .supports_tv = 1, |
cfdf1fa2 KH |
126 | }; |
127 | ||
9a7e8492 | 128 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 129 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 130 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 131 | .has_overlay = 1, |
cfdf1fa2 KH |
132 | }; |
133 | ||
9a7e8492 | 134 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 135 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 136 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 137 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
138 | }; |
139 | ||
9a7e8492 | 140 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 141 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 142 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 143 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 144 | .supports_tv = 1, |
92f49d9c | 145 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
146 | }; |
147 | ||
9a7e8492 | 148 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 149 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 150 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 151 | .has_overlay = 1, |
cfdf1fa2 KH |
152 | }; |
153 | ||
9a7e8492 | 154 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 155 | .gen = 5, |
c96c3a8c | 156 | .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 157 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
158 | }; |
159 | ||
9a7e8492 | 160 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 161 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 162 | .need_gfx_hws = 1, .has_hotplug = 1, |
16c59ef3 | 163 | .has_fbc = 0, /* disabled due to buggy hardware */ |
92f49d9c | 164 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
165 | }; |
166 | ||
9a7e8492 | 167 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 168 | .gen = 6, |
c96c3a8c | 169 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 170 | .has_bsd_ring = 1, |
549f7365 | 171 | .has_blt_ring = 1, |
f6e450a6 EA |
172 | }; |
173 | ||
9a7e8492 | 174 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 175 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 176 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 177 | .has_fbc = 1, |
881f47b6 | 178 | .has_bsd_ring = 1, |
549f7365 | 179 | .has_blt_ring = 1, |
a13e4093 EA |
180 | }; |
181 | ||
6103da0d CW |
182 | static const struct pci_device_id pciidlist[] = { /* aka */ |
183 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
184 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
185 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 186 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
187 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
188 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
189 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
190 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
191 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
192 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
193 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
194 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
195 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
196 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
197 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
198 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
199 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
200 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
201 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
202 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
203 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
204 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
205 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
206 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
207 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
208 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 209 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
210 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
211 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
212 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
213 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 214 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
215 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
216 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 217 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 218 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 219 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 220 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
49ae35f2 | 221 | {0, 0, 0} |
1da177e4 LT |
222 | }; |
223 | ||
79e53945 JB |
224 | #if defined(CONFIG_DRM_I915_KMS) |
225 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
226 | #endif | |
227 | ||
3bad0781 ZW |
228 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
229 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
230 | ||
231 | void intel_detect_pch (struct drm_device *dev) | |
232 | { | |
233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
234 | struct pci_dev *pch; | |
235 | ||
236 | /* | |
237 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
238 | * make graphics device passthrough work easy for VMM, that only | |
239 | * need to expose ISA bridge to let driver know the real hardware | |
240 | * underneath. This is a requirement from virtualization team. | |
241 | */ | |
242 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
243 | if (pch) { | |
244 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
245 | int id; | |
246 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
247 | ||
248 | if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
249 | dev_priv->pch_type = PCH_CPT; | |
250 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
251 | } | |
252 | } | |
253 | pci_dev_put(pch); | |
254 | } | |
255 | } | |
256 | ||
91355834 | 257 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
eb43f4af CW |
258 | { |
259 | int count; | |
260 | ||
261 | count = 0; | |
262 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
263 | udelay(10); | |
264 | ||
265 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
266 | POSTING_READ(FORCEWAKE); | |
267 | ||
268 | count = 0; | |
269 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) | |
270 | udelay(10); | |
271 | } | |
272 | ||
91355834 | 273 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
eb43f4af CW |
274 | { |
275 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
276 | POSTING_READ(FORCEWAKE); | |
277 | } | |
278 | ||
91355834 CW |
279 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
280 | { | |
281 | int loop = 500; | |
282 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
283 | while (fifo < 20 && loop--) { | |
284 | udelay(10); | |
285 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
286 | } | |
287 | } | |
288 | ||
84b79f8d | 289 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 290 | { |
61caf87c RW |
291 | struct drm_i915_private *dev_priv = dev->dev_private; |
292 | ||
5bcf719b DA |
293 | drm_kms_helper_poll_disable(dev); |
294 | ||
ba8bbcf6 | 295 | pci_save_state(dev->pdev); |
ba8bbcf6 | 296 | |
5669fcac | 297 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 298 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
299 | int error = i915_gem_idle(dev); |
300 | if (error) { | |
226485e9 | 301 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
302 | "GEM idle failed, resume might fail\n"); |
303 | return error; | |
304 | } | |
226485e9 | 305 | drm_irq_uninstall(dev); |
5669fcac JB |
306 | } |
307 | ||
9e06dd39 JB |
308 | i915_save_state(dev); |
309 | ||
44834a67 | 310 | intel_opregion_fini(dev); |
8ee1c3db | 311 | |
84b79f8d RW |
312 | /* Modeset on resume, not lid events */ |
313 | dev_priv->modeset_on_lid = 0; | |
61caf87c RW |
314 | |
315 | return 0; | |
84b79f8d RW |
316 | } |
317 | ||
6a9ee8af | 318 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
319 | { |
320 | int error; | |
321 | ||
322 | if (!dev || !dev->dev_private) { | |
323 | DRM_ERROR("dev: %p\n", dev); | |
324 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
325 | return -ENODEV; | |
326 | } | |
327 | ||
328 | if (state.event == PM_EVENT_PRETHAW) | |
329 | return 0; | |
330 | ||
5bcf719b DA |
331 | |
332 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
333 | return 0; | |
6eecba33 | 334 | |
84b79f8d RW |
335 | error = i915_drm_freeze(dev); |
336 | if (error) | |
337 | return error; | |
338 | ||
b932ccb5 DA |
339 | if (state.event == PM_EVENT_SUSPEND) { |
340 | /* Shut down the device */ | |
341 | pci_disable_device(dev->pdev); | |
342 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
343 | } | |
ba8bbcf6 JB |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
84b79f8d | 348 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 349 | { |
5669fcac | 350 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 351 | int error = 0; |
8ee1c3db | 352 | |
d1c3b177 CW |
353 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
354 | mutex_lock(&dev->struct_mutex); | |
355 | i915_gem_restore_gtt_mappings(dev); | |
356 | mutex_unlock(&dev->struct_mutex); | |
357 | } | |
358 | ||
61caf87c | 359 | i915_restore_state(dev); |
44834a67 | 360 | intel_opregion_setup(dev); |
61caf87c | 361 | |
5669fcac JB |
362 | /* KMS EnterVT equivalent */ |
363 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
364 | mutex_lock(&dev->struct_mutex); | |
365 | dev_priv->mm.suspended = 0; | |
366 | ||
84b79f8d | 367 | error = i915_gem_init_ringbuffer(dev); |
5669fcac | 368 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 369 | |
500f7147 | 370 | drm_mode_config_reset(dev); |
226485e9 | 371 | drm_irq_install(dev); |
84b79f8d | 372 | |
354ff967 ZY |
373 | /* Resume the modeset for every activated CRTC */ |
374 | drm_helper_resume_force_mode(dev); | |
5669fcac | 375 | |
ac668088 | 376 | if (IS_IRONLAKE_M(dev)) |
d5bb081b JB |
377 | ironlake_enable_rc6(dev); |
378 | } | |
1daed3fb | 379 | |
44834a67 CW |
380 | intel_opregion_init(dev); |
381 | ||
c9354c85 | 382 | dev_priv->modeset_on_lid = 0; |
06891e27 | 383 | |
84b79f8d RW |
384 | return error; |
385 | } | |
386 | ||
6a9ee8af | 387 | int i915_resume(struct drm_device *dev) |
84b79f8d | 388 | { |
6eecba33 CW |
389 | int ret; |
390 | ||
5bcf719b DA |
391 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
392 | return 0; | |
393 | ||
84b79f8d RW |
394 | if (pci_enable_device(dev->pdev)) |
395 | return -EIO; | |
396 | ||
397 | pci_set_master(dev->pdev); | |
398 | ||
6eecba33 CW |
399 | ret = i915_drm_thaw(dev); |
400 | if (ret) | |
401 | return ret; | |
402 | ||
403 | drm_kms_helper_poll_enable(dev); | |
404 | return 0; | |
ba8bbcf6 JB |
405 | } |
406 | ||
dc96e9b8 CW |
407 | static int i8xx_do_reset(struct drm_device *dev, u8 flags) |
408 | { | |
409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
410 | ||
411 | if (IS_I85X(dev)) | |
412 | return -ENODEV; | |
413 | ||
414 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
415 | POSTING_READ(D_STATE); | |
416 | ||
417 | if (IS_I830(dev) || IS_845G(dev)) { | |
418 | I915_WRITE(DEBUG_RESET_I830, | |
419 | DEBUG_RESET_DISPLAY | | |
420 | DEBUG_RESET_RENDER | | |
421 | DEBUG_RESET_FULL); | |
422 | POSTING_READ(DEBUG_RESET_I830); | |
423 | msleep(1); | |
424 | ||
425 | I915_WRITE(DEBUG_RESET_I830, 0); | |
426 | POSTING_READ(DEBUG_RESET_I830); | |
427 | } | |
428 | ||
429 | msleep(1); | |
430 | ||
431 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
432 | POSTING_READ(D_STATE); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
f49f0586 KG |
437 | static int i965_reset_complete(struct drm_device *dev) |
438 | { | |
439 | u8 gdrst; | |
eeccdcac | 440 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
f49f0586 KG |
441 | return gdrst & 0x1; |
442 | } | |
443 | ||
0573ed4a KG |
444 | static int i965_do_reset(struct drm_device *dev, u8 flags) |
445 | { | |
446 | u8 gdrst; | |
447 | ||
ae681d96 CW |
448 | /* |
449 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
450 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
451 | * triggers the reset; when done, the hardware will clear it. | |
452 | */ | |
0573ed4a KG |
453 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
454 | pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1); | |
455 | ||
456 | return wait_for(i965_reset_complete(dev), 500); | |
457 | } | |
458 | ||
459 | static int ironlake_do_reset(struct drm_device *dev, u8 flags) | |
460 | { | |
461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
462 | u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
463 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); | |
464 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
ba8bbcf6 JB |
465 | } |
466 | ||
cff458c2 EA |
467 | static int gen6_do_reset(struct drm_device *dev, u8 flags) |
468 | { | |
469 | struct drm_i915_private *dev_priv = dev->dev_private; | |
470 | ||
471 | I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
472 | return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
473 | } | |
474 | ||
11ed50ec BG |
475 | /** |
476 | * i965_reset - reset chip after a hang | |
477 | * @dev: drm device to reset | |
478 | * @flags: reset domains | |
479 | * | |
480 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
481 | * reset or otherwise an error code. | |
482 | * | |
483 | * Procedure is fairly simple: | |
484 | * - reset the chip using the reset reg | |
485 | * - re-init context state | |
486 | * - re-init hardware status page | |
487 | * - re-init ring buffer | |
488 | * - re-init interrupt state | |
489 | * - re-init display | |
490 | */ | |
f803aa55 | 491 | int i915_reset(struct drm_device *dev, u8 flags) |
11ed50ec BG |
492 | { |
493 | drm_i915_private_t *dev_priv = dev->dev_private; | |
11ed50ec BG |
494 | /* |
495 | * We really should only reset the display subsystem if we actually | |
496 | * need to | |
497 | */ | |
498 | bool need_display = true; | |
0573ed4a | 499 | int ret; |
11ed50ec | 500 | |
d78cb50b CW |
501 | if (!i915_try_reset) |
502 | return 0; | |
503 | ||
340479aa CW |
504 | if (!mutex_trylock(&dev->struct_mutex)) |
505 | return -EBUSY; | |
11ed50ec | 506 | |
069efc1d | 507 | i915_gem_reset(dev); |
77f01230 | 508 | |
f803aa55 | 509 | ret = -ENODEV; |
ae681d96 CW |
510 | if (get_seconds() - dev_priv->last_gpu_reset < 5) { |
511 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); | |
512 | } else switch (INTEL_INFO(dev)->gen) { | |
cff458c2 EA |
513 | case 6: |
514 | ret = gen6_do_reset(dev, flags); | |
515 | break; | |
f803aa55 | 516 | case 5: |
0573ed4a | 517 | ret = ironlake_do_reset(dev, flags); |
f803aa55 CW |
518 | break; |
519 | case 4: | |
0573ed4a | 520 | ret = i965_do_reset(dev, flags); |
f803aa55 | 521 | break; |
dc96e9b8 CW |
522 | case 2: |
523 | ret = i8xx_do_reset(dev, flags); | |
524 | break; | |
f803aa55 | 525 | } |
ae681d96 | 526 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 527 | if (ret) { |
f803aa55 | 528 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 529 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 530 | return ret; |
11ed50ec BG |
531 | } |
532 | ||
533 | /* Ok, now get things going again... */ | |
534 | ||
535 | /* | |
536 | * Everything depends on having the GTT running, so we need to start | |
537 | * there. Fortunately we don't need to do this unless we reset the | |
538 | * chip at a PCI level. | |
539 | * | |
540 | * Next we need to restore the context, but we don't use those | |
541 | * yet either... | |
542 | * | |
543 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
544 | * was running at the time of the reset (i.e. we weren't VT | |
545 | * switched away). | |
546 | */ | |
547 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 548 | !dev_priv->mm.suspended) { |
11ed50ec | 549 | dev_priv->mm.suspended = 0; |
75a6898f | 550 | |
1ec14ad3 | 551 | dev_priv->ring[RCS].init(&dev_priv->ring[RCS]); |
75a6898f | 552 | if (HAS_BSD(dev)) |
1ec14ad3 | 553 | dev_priv->ring[VCS].init(&dev_priv->ring[VCS]); |
75a6898f | 554 | if (HAS_BLT(dev)) |
1ec14ad3 | 555 | dev_priv->ring[BCS].init(&dev_priv->ring[BCS]); |
75a6898f | 556 | |
11ed50ec BG |
557 | mutex_unlock(&dev->struct_mutex); |
558 | drm_irq_uninstall(dev); | |
500f7147 | 559 | drm_mode_config_reset(dev); |
11ed50ec BG |
560 | drm_irq_install(dev); |
561 | mutex_lock(&dev->struct_mutex); | |
562 | } | |
563 | ||
9fd98141 CW |
564 | mutex_unlock(&dev->struct_mutex); |
565 | ||
11ed50ec | 566 | /* |
9fd98141 CW |
567 | * Perform a full modeset as on later generations, e.g. Ironlake, we may |
568 | * need to retrain the display link and cannot just restore the register | |
569 | * values. | |
11ed50ec | 570 | */ |
9fd98141 CW |
571 | if (need_display) { |
572 | mutex_lock(&dev->mode_config.mutex); | |
573 | drm_helper_resume_force_mode(dev); | |
574 | mutex_unlock(&dev->mode_config.mutex); | |
575 | } | |
11ed50ec | 576 | |
11ed50ec BG |
577 | return 0; |
578 | } | |
579 | ||
580 | ||
112b715e KH |
581 | static int __devinit |
582 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
583 | { | |
5fe49d86 CW |
584 | /* Only bind to function 0 of the device. Early generations |
585 | * used function 1 as a placeholder for multi-head. This causes | |
586 | * us confusion instead, especially on the systems where both | |
587 | * functions have the same PCI-ID! | |
588 | */ | |
589 | if (PCI_FUNC(pdev->devfn)) | |
590 | return -ENODEV; | |
591 | ||
dcdb1674 | 592 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
593 | } |
594 | ||
595 | static void | |
596 | i915_pci_remove(struct pci_dev *pdev) | |
597 | { | |
598 | struct drm_device *dev = pci_get_drvdata(pdev); | |
599 | ||
600 | drm_put_dev(dev); | |
601 | } | |
602 | ||
84b79f8d | 603 | static int i915_pm_suspend(struct device *dev) |
112b715e | 604 | { |
84b79f8d RW |
605 | struct pci_dev *pdev = to_pci_dev(dev); |
606 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
607 | int error; | |
112b715e | 608 | |
84b79f8d RW |
609 | if (!drm_dev || !drm_dev->dev_private) { |
610 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
611 | return -ENODEV; | |
612 | } | |
112b715e | 613 | |
5bcf719b DA |
614 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
615 | return 0; | |
616 | ||
84b79f8d RW |
617 | error = i915_drm_freeze(drm_dev); |
618 | if (error) | |
619 | return error; | |
112b715e | 620 | |
84b79f8d RW |
621 | pci_disable_device(pdev); |
622 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 623 | |
84b79f8d | 624 | return 0; |
cbda12d7 ZW |
625 | } |
626 | ||
84b79f8d | 627 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 628 | { |
84b79f8d RW |
629 | struct pci_dev *pdev = to_pci_dev(dev); |
630 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
631 | ||
632 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
633 | } |
634 | ||
84b79f8d | 635 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 636 | { |
84b79f8d RW |
637 | struct pci_dev *pdev = to_pci_dev(dev); |
638 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
639 | ||
640 | if (!drm_dev || !drm_dev->dev_private) { | |
641 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
642 | return -ENODEV; | |
643 | } | |
644 | ||
645 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
646 | } |
647 | ||
84b79f8d | 648 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 649 | { |
84b79f8d RW |
650 | struct pci_dev *pdev = to_pci_dev(dev); |
651 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
652 | ||
653 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
654 | } |
655 | ||
84b79f8d | 656 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 657 | { |
84b79f8d RW |
658 | struct pci_dev *pdev = to_pci_dev(dev); |
659 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 660 | |
61caf87c | 661 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
662 | } |
663 | ||
b4b78d12 | 664 | static const struct dev_pm_ops i915_pm_ops = { |
cbda12d7 ZW |
665 | .suspend = i915_pm_suspend, |
666 | .resume = i915_pm_resume, | |
667 | .freeze = i915_pm_freeze, | |
668 | .thaw = i915_pm_thaw, | |
669 | .poweroff = i915_pm_poweroff, | |
84b79f8d | 670 | .restore = i915_pm_resume, |
cbda12d7 ZW |
671 | }; |
672 | ||
de151cf6 JB |
673 | static struct vm_operations_struct i915_gem_vm_ops = { |
674 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
675 | .open = drm_gem_vm_open, |
676 | .close = drm_gem_vm_close, | |
de151cf6 JB |
677 | }; |
678 | ||
1da177e4 | 679 | static struct drm_driver driver = { |
792d2b9a DA |
680 | /* don't use mtrr's here, the Xserver or user space app should |
681 | * deal with them for intel hardware. | |
682 | */ | |
673a394b EA |
683 | .driver_features = |
684 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
685 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 686 | .load = i915_driver_load, |
ba8bbcf6 | 687 | .unload = i915_driver_unload, |
673a394b | 688 | .open = i915_driver_open, |
22eae947 DA |
689 | .lastclose = i915_driver_lastclose, |
690 | .preclose = i915_driver_preclose, | |
673a394b | 691 | .postclose = i915_driver_postclose, |
d8e29209 RW |
692 | |
693 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
694 | .suspend = i915_suspend, | |
695 | .resume = i915_resume, | |
696 | ||
cda17380 | 697 | .device_is_agp = i915_driver_device_is_agp, |
0a3e67a4 JB |
698 | .enable_vblank = i915_enable_vblank, |
699 | .disable_vblank = i915_disable_vblank, | |
0af7e4df MK |
700 | .get_vblank_timestamp = i915_get_vblank_timestamp, |
701 | .get_scanout_position = i915_get_crtc_scanoutpos, | |
1da177e4 LT |
702 | .irq_preinstall = i915_driver_irq_preinstall, |
703 | .irq_postinstall = i915_driver_irq_postinstall, | |
704 | .irq_uninstall = i915_driver_irq_uninstall, | |
705 | .irq_handler = i915_driver_irq_handler, | |
706 | .reclaim_buffers = drm_core_reclaim_buffers, | |
7c1c2871 DA |
707 | .master_create = i915_master_create, |
708 | .master_destroy = i915_master_destroy, | |
955b12de | 709 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
710 | .debugfs_init = i915_debugfs_init, |
711 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 712 | #endif |
673a394b EA |
713 | .gem_init_object = i915_gem_init_object, |
714 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 715 | .gem_vm_ops = &i915_gem_vm_ops, |
1da177e4 LT |
716 | .ioctls = i915_ioctls, |
717 | .fops = { | |
b5e89ed5 DA |
718 | .owner = THIS_MODULE, |
719 | .open = drm_open, | |
720 | .release = drm_release, | |
ed8b6704 | 721 | .unlocked_ioctl = drm_ioctl, |
de151cf6 | 722 | .mmap = drm_gem_mmap, |
b5e89ed5 DA |
723 | .poll = drm_poll, |
724 | .fasync = drm_fasync, | |
c9a9c5e0 | 725 | .read = drm_read, |
8ca7c1df | 726 | #ifdef CONFIG_COMPAT |
b5e89ed5 | 727 | .compat_ioctl = i915_compat_ioctl, |
8ca7c1df | 728 | #endif |
dc880abe | 729 | .llseek = noop_llseek, |
22eae947 DA |
730 | }, |
731 | ||
1da177e4 | 732 | .pci_driver = { |
22eae947 DA |
733 | .name = DRIVER_NAME, |
734 | .id_table = pciidlist, | |
112b715e KH |
735 | .probe = i915_pci_probe, |
736 | .remove = i915_pci_remove, | |
cbda12d7 | 737 | .driver.pm = &i915_pm_ops, |
22eae947 | 738 | }, |
bc5f4523 | 739 | |
22eae947 DA |
740 | .name = DRIVER_NAME, |
741 | .desc = DRIVER_DESC, | |
742 | .date = DRIVER_DATE, | |
743 | .major = DRIVER_MAJOR, | |
744 | .minor = DRIVER_MINOR, | |
745 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
746 | }; |
747 | ||
748 | static int __init i915_init(void) | |
749 | { | |
1f7a6e37 ZW |
750 | if (!intel_agp_enabled) { |
751 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
752 | return -ENODEV; | |
753 | } | |
754 | ||
1da177e4 | 755 | driver.num_ioctls = i915_max_ioctl; |
79e53945 JB |
756 | |
757 | /* | |
758 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
759 | * explicitly disabled with the module pararmeter. | |
760 | * | |
761 | * Otherwise, just follow the parameter (defaulting to off). | |
762 | * | |
763 | * Allow optional vga_text_mode_force boot option to override | |
764 | * the default behavior. | |
765 | */ | |
766 | #if defined(CONFIG_DRM_I915_KMS) | |
767 | if (i915_modeset != 0) | |
768 | driver.driver_features |= DRIVER_MODESET; | |
769 | #endif | |
770 | if (i915_modeset == 1) | |
771 | driver.driver_features |= DRIVER_MODESET; | |
772 | ||
773 | #ifdef CONFIG_VGA_CONSOLE | |
774 | if (vgacon_text_force() && i915_modeset == -1) | |
775 | driver.driver_features &= ~DRIVER_MODESET; | |
776 | #endif | |
777 | ||
3885c6bb CW |
778 | if (!(driver.driver_features & DRIVER_MODESET)) |
779 | driver.get_vblank_timestamp = NULL; | |
780 | ||
1da177e4 LT |
781 | return drm_init(&driver); |
782 | } | |
783 | ||
784 | static void __exit i915_exit(void) | |
785 | { | |
786 | drm_exit(&driver); | |
787 | } | |
788 | ||
789 | module_init(i915_init); | |
790 | module_exit(i915_exit); | |
791 | ||
b5e89ed5 DA |
792 | MODULE_AUTHOR(DRIVER_AUTHOR); |
793 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 794 | MODULE_LICENSE("GPL and additional rights"); |