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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a726915c | 50 | int i915_panel_ignore_lid __read_mostly = 1; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 | 52 | MODULE_PARM_DESC(panel_ignore_lid, |
a726915c DV |
53 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " |
54 | "-1=force lid closed, -2=force lid open)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
f57f9c16 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
105b7c11 RV |
121 | int i915_enable_psr __read_mostly = 0; |
122 | module_param_named(enable_psr, i915_enable_psr, int, 0600); | |
123 | MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)"); | |
124 | ||
99486b8e | 125 | unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT); |
0a3af268 RV |
126 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); |
127 | MODULE_PARM_DESC(preliminary_hw_support, | |
99486b8e | 128 | "Enable preliminary hardware support."); |
0a3af268 | 129 | |
bf51d5e2 | 130 | int i915_disable_power_well __read_mostly = 1; |
2124b72e PZ |
131 | module_param_named(disable_power_well, i915_disable_power_well, int, 0600); |
132 | MODULE_PARM_DESC(disable_power_well, | |
bf51d5e2 | 133 | "Disable the power well when possible (default: true)"); |
2124b72e | 134 | |
3c4ca58c PZ |
135 | int i915_enable_ips __read_mostly = 1; |
136 | module_param_named(enable_ips, i915_enable_ips, int, 0600); | |
137 | MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); | |
138 | ||
2385bdf0 JB |
139 | bool i915_fastboot __read_mostly = 0; |
140 | module_param_named(fastboot, i915_fastboot, bool, 0600); | |
141 | MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time " | |
142 | "(default: false)"); | |
143 | ||
e27e9708 | 144 | int i915_enable_pc8 __read_mostly = 1; |
c67a470b | 145 | module_param_named(enable_pc8, i915_enable_pc8, int, 0600); |
e27e9708 | 146 | MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)"); |
c67a470b | 147 | |
90058745 PZ |
148 | int i915_pc8_timeout __read_mostly = 5000; |
149 | module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600); | |
150 | MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)"); | |
151 | ||
0b74b508 XZ |
152 | bool i915_prefault_disable __read_mostly; |
153 | module_param_named(prefault_disable, i915_prefault_disable, bool, 0600); | |
154 | MODULE_PARM_DESC(prefault_disable, | |
155 | "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); | |
156 | ||
112b715e | 157 | static struct drm_driver driver; |
1f7a6e37 | 158 | extern int intel_agp_enabled; |
112b715e | 159 | |
9a7e8492 | 160 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 161 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 162 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
163 | }; |
164 | ||
9a7e8492 | 165 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 166 | .gen = 2, .num_pipes = 1, |
31578148 | 167 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
168 | }; |
169 | ||
9a7e8492 | 170 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 171 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 172 | .cursor_needs_physical = 1, |
31578148 | 173 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
174 | }; |
175 | ||
9a7e8492 | 176 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 177 | .gen = 2, .num_pipes = 1, |
31578148 | 178 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
179 | }; |
180 | ||
9a7e8492 | 181 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 182 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 183 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 184 | }; |
9a7e8492 | 185 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 186 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 187 | .cursor_needs_physical = 1, |
31578148 | 188 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 189 | .supports_tv = 1, |
cfdf1fa2 | 190 | }; |
9a7e8492 | 191 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 192 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 193 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 194 | }; |
9a7e8492 | 195 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 196 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 197 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 198 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 199 | .supports_tv = 1, |
cfdf1fa2 KH |
200 | }; |
201 | ||
9a7e8492 | 202 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 203 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 204 | .has_hotplug = 1, |
31578148 | 205 | .has_overlay = 1, |
cfdf1fa2 KH |
206 | }; |
207 | ||
9a7e8492 | 208 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 209 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 210 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 211 | .has_overlay = 1, |
a6c45cf0 | 212 | .supports_tv = 1, |
cfdf1fa2 KH |
213 | }; |
214 | ||
9a7e8492 | 215 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 216 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 217 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 218 | .has_overlay = 1, |
cfdf1fa2 KH |
219 | }; |
220 | ||
9a7e8492 | 221 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 222 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 223 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 224 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
225 | }; |
226 | ||
9a7e8492 | 227 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 228 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 229 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 230 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 231 | .supports_tv = 1, |
92f49d9c | 232 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
233 | }; |
234 | ||
9a7e8492 | 235 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 236 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 237 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 238 | .has_overlay = 1, |
cfdf1fa2 KH |
239 | }; |
240 | ||
9a7e8492 | 241 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 242 | .gen = 5, .num_pipes = 2, |
5a117db7 | 243 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 244 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
245 | }; |
246 | ||
9a7e8492 | 247 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 248 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 249 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 250 | .has_fbc = 1, |
92f49d9c | 251 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
252 | }; |
253 | ||
9a7e8492 | 254 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 255 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 256 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 257 | .has_bsd_ring = 1, |
549f7365 | 258 | .has_blt_ring = 1, |
3d29b842 | 259 | .has_llc = 1, |
b7884eb4 | 260 | .has_force_wake = 1, |
f6e450a6 EA |
261 | }; |
262 | ||
9a7e8492 | 263 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 264 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 265 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 266 | .has_fbc = 1, |
881f47b6 | 267 | .has_bsd_ring = 1, |
549f7365 | 268 | .has_blt_ring = 1, |
3d29b842 | 269 | .has_llc = 1, |
b7884eb4 | 270 | .has_force_wake = 1, |
a13e4093 EA |
271 | }; |
272 | ||
219f4fdb BW |
273 | #define GEN7_FEATURES \ |
274 | .gen = 7, .num_pipes = 3, \ | |
275 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
276 | .has_bsd_ring = 1, \ | |
277 | .has_blt_ring = 1, \ | |
278 | .has_llc = 1, \ | |
279 | .has_force_wake = 1 | |
280 | ||
c76b615c | 281 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
282 | GEN7_FEATURES, |
283 | .is_ivybridge = 1, | |
c76b615c JB |
284 | }; |
285 | ||
286 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
287 | GEN7_FEATURES, |
288 | .is_ivybridge = 1, | |
289 | .is_mobile = 1, | |
abe959c7 | 290 | .has_fbc = 1, |
c76b615c JB |
291 | }; |
292 | ||
999bcdea BW |
293 | static const struct intel_device_info intel_ivybridge_q_info = { |
294 | GEN7_FEATURES, | |
295 | .is_ivybridge = 1, | |
296 | .num_pipes = 0, /* legal, last one wins */ | |
297 | }; | |
298 | ||
70a3eb7a | 299 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
300 | GEN7_FEATURES, |
301 | .is_mobile = 1, | |
302 | .num_pipes = 2, | |
70a3eb7a | 303 | .is_valleyview = 1, |
fba5d532 | 304 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 305 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
306 | }; |
307 | ||
308 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
309 | GEN7_FEATURES, |
310 | .num_pipes = 2, | |
70a3eb7a | 311 | .is_valleyview = 1, |
fba5d532 | 312 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 313 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
314 | }; |
315 | ||
4cae9ae0 | 316 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
317 | GEN7_FEATURES, |
318 | .is_haswell = 1, | |
dd93be58 | 319 | .has_ddi = 1, |
30568c45 | 320 | .has_fpga_dbg = 1, |
f72a1183 | 321 | .has_vebox_ring = 1, |
4cae9ae0 ED |
322 | }; |
323 | ||
324 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
325 | GEN7_FEATURES, |
326 | .is_haswell = 1, | |
327 | .is_mobile = 1, | |
dd93be58 | 328 | .has_ddi = 1, |
30568c45 | 329 | .has_fpga_dbg = 1, |
891348b2 | 330 | .has_fbc = 1, |
f72a1183 | 331 | .has_vebox_ring = 1, |
c76b615c JB |
332 | }; |
333 | ||
a0a18075 JB |
334 | /* |
335 | * Make sure any device matches here are from most specific to most | |
336 | * general. For example, since the Quanta match is based on the subsystem | |
337 | * and subvendor IDs, we need it to come before the more general IVB | |
338 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
339 | */ | |
340 | #define INTEL_PCI_IDS \ | |
341 | INTEL_I830_IDS(&intel_i830_info), \ | |
342 | INTEL_I845G_IDS(&intel_845g_info), \ | |
343 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
344 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
345 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
346 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
347 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
348 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
349 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
350 | INTEL_G33_IDS(&intel_g33_info), \ | |
351 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
352 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
353 | INTEL_G45_IDS(&intel_g45_info), \ | |
354 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
355 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
356 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
357 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
358 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
359 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
360 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
361 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
362 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
363 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
364 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
365 | INTEL_VLV_D_IDS(&intel_valleyview_d_info) | |
366 | ||
6103da0d | 367 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 368 | INTEL_PCI_IDS, |
49ae35f2 | 369 | {0, 0, 0} |
1da177e4 LT |
370 | }; |
371 | ||
79e53945 JB |
372 | #if defined(CONFIG_DRM_I915_KMS) |
373 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
374 | #endif | |
375 | ||
0206e353 | 376 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
377 | { |
378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
379 | struct pci_dev *pch; | |
380 | ||
ce1bb329 BW |
381 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
382 | * (which really amounts to a PCH but no South Display). | |
383 | */ | |
384 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
385 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
386 | return; |
387 | } | |
388 | ||
3bad0781 ZW |
389 | /* |
390 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
391 | * make graphics device passthrough work easy for VMM, that only | |
392 | * need to expose ISA bridge to let driver know the real hardware | |
393 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
394 | * |
395 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
396 | * ISA bridge in the system. To work reliably, we should scan trhough | |
397 | * all the ISA bridge devices and check for the first match, instead | |
398 | * of only checking the first one. | |
3bad0781 ZW |
399 | */ |
400 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
6a9c4b35 RG |
401 | while (pch) { |
402 | struct pci_dev *curr = pch; | |
3bad0781 | 403 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
17a303ec | 404 | unsigned short id; |
3bad0781 | 405 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 406 | dev_priv->pch_id = id; |
3bad0781 | 407 | |
90711d50 JB |
408 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
409 | dev_priv->pch_type = PCH_IBX; | |
410 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 411 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 412 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
413 | dev_priv->pch_type = PCH_CPT; |
414 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 415 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
416 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
417 | /* PantherPoint is CPT compatible */ | |
418 | dev_priv->pch_type = PCH_CPT; | |
419 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | |
7fcb83cd | 420 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
421 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
422 | dev_priv->pch_type = PCH_LPT; | |
423 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 424 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 425 | WARN_ON(IS_ULT(dev)); |
ae6935dd WSC |
426 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
427 | dev_priv->pch_type = PCH_LPT; | |
ae6935dd WSC |
428 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
429 | WARN_ON(!IS_HASWELL(dev)); | |
08e1413d | 430 | WARN_ON(!IS_ULT(dev)); |
6a9c4b35 RG |
431 | } else { |
432 | goto check_next; | |
3bad0781 | 433 | } |
6a9c4b35 RG |
434 | pci_dev_put(pch); |
435 | break; | |
3bad0781 | 436 | } |
6a9c4b35 RG |
437 | check_next: |
438 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr); | |
439 | pci_dev_put(curr); | |
3bad0781 | 440 | } |
6a9c4b35 RG |
441 | if (!pch) |
442 | DRM_DEBUG_KMS("No PCH found?\n"); | |
3bad0781 ZW |
443 | } |
444 | ||
2911a35b BW |
445 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
446 | { | |
447 | if (INTEL_INFO(dev)->gen < 6) | |
448 | return 0; | |
449 | ||
450 | if (i915_semaphores >= 0) | |
451 | return i915_semaphores; | |
452 | ||
59de3295 | 453 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 454 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
455 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
456 | return false; | |
457 | #endif | |
2911a35b BW |
458 | |
459 | return 1; | |
460 | } | |
461 | ||
84b79f8d | 462 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 463 | { |
61caf87c | 464 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 465 | struct drm_crtc *crtc; |
61caf87c | 466 | |
b8efb17b ZR |
467 | /* ignore lid events during suspend */ |
468 | mutex_lock(&dev_priv->modeset_restore_lock); | |
469 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
470 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
471 | ||
c67a470b PZ |
472 | /* We do a lot of poking in a lot of registers, make sure they work |
473 | * properly. */ | |
474 | hsw_disable_package_c8(dev_priv); | |
cb10799c PZ |
475 | intel_set_power_well(dev, true); |
476 | ||
5bcf719b DA |
477 | drm_kms_helper_poll_disable(dev); |
478 | ||
ba8bbcf6 | 479 | pci_save_state(dev->pdev); |
ba8bbcf6 | 480 | |
5669fcac | 481 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 482 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
483 | int error; |
484 | ||
485 | mutex_lock(&dev->struct_mutex); | |
486 | error = i915_gem_idle(dev); | |
487 | mutex_unlock(&dev->struct_mutex); | |
84b79f8d | 488 | if (error) { |
226485e9 | 489 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
490 | "GEM idle failed, resume might fail\n"); |
491 | return error; | |
492 | } | |
a261b246 | 493 | |
1a01ab3b JB |
494 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
495 | ||
226485e9 | 496 | drm_irq_uninstall(dev); |
15239099 | 497 | dev_priv->enable_hotplug_processing = false; |
24576d23 JB |
498 | /* |
499 | * Disable CRTCs directly since we want to preserve sw state | |
500 | * for _thaw. | |
501 | */ | |
502 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
503 | dev_priv->display.crtc_disable(crtc); | |
7d708ee4 ID |
504 | |
505 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
506 | } |
507 | ||
9e06dd39 JB |
508 | i915_save_state(dev); |
509 | ||
44834a67 | 510 | intel_opregion_fini(dev); |
8ee1c3db | 511 | |
3fa016a0 | 512 | console_lock(); |
b6f3eff7 | 513 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
514 | console_unlock(); |
515 | ||
61caf87c | 516 | return 0; |
84b79f8d RW |
517 | } |
518 | ||
6a9ee8af | 519 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
520 | { |
521 | int error; | |
522 | ||
523 | if (!dev || !dev->dev_private) { | |
524 | DRM_ERROR("dev: %p\n", dev); | |
525 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
526 | return -ENODEV; | |
527 | } | |
528 | ||
529 | if (state.event == PM_EVENT_PRETHAW) | |
530 | return 0; | |
531 | ||
5bcf719b DA |
532 | |
533 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
534 | return 0; | |
6eecba33 | 535 | |
84b79f8d RW |
536 | error = i915_drm_freeze(dev); |
537 | if (error) | |
538 | return error; | |
539 | ||
b932ccb5 DA |
540 | if (state.event == PM_EVENT_SUSPEND) { |
541 | /* Shut down the device */ | |
542 | pci_disable_device(dev->pdev); | |
543 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
544 | } | |
ba8bbcf6 JB |
545 | |
546 | return 0; | |
547 | } | |
548 | ||
073f34d9 JB |
549 | void intel_console_resume(struct work_struct *work) |
550 | { | |
551 | struct drm_i915_private *dev_priv = | |
552 | container_of(work, struct drm_i915_private, | |
553 | console_resume_work); | |
554 | struct drm_device *dev = dev_priv->dev; | |
555 | ||
556 | console_lock(); | |
b6f3eff7 | 557 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
558 | console_unlock(); |
559 | } | |
560 | ||
bb60b969 JB |
561 | static void intel_resume_hotplug(struct drm_device *dev) |
562 | { | |
563 | struct drm_mode_config *mode_config = &dev->mode_config; | |
564 | struct intel_encoder *encoder; | |
565 | ||
566 | mutex_lock(&mode_config->mutex); | |
567 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); | |
568 | ||
569 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
570 | if (encoder->hot_plug) | |
571 | encoder->hot_plug(encoder); | |
572 | ||
573 | mutex_unlock(&mode_config->mutex); | |
574 | ||
575 | /* Just fire off a uevent and let userspace tell us what to do */ | |
576 | drm_helper_hpd_irq_event(dev); | |
577 | } | |
578 | ||
1abd02e2 | 579 | static int __i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 580 | { |
5669fcac | 581 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 582 | int error = 0; |
8ee1c3db | 583 | |
61caf87c | 584 | i915_restore_state(dev); |
44834a67 | 585 | intel_opregion_setup(dev); |
61caf87c | 586 | |
5669fcac JB |
587 | /* KMS EnterVT equivalent */ |
588 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 589 | intel_init_pch_refclk(dev); |
1833b134 | 590 | |
5669fcac | 591 | mutex_lock(&dev->struct_mutex); |
5669fcac | 592 | |
f691e2f4 | 593 | error = i915_gem_init_hw(dev); |
5669fcac | 594 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 595 | |
15239099 DV |
596 | /* We need working interrupts for modeset enabling ... */ |
597 | drm_irq_install(dev); | |
598 | ||
1833b134 | 599 | intel_modeset_init_hw(dev); |
24576d23 JB |
600 | |
601 | drm_modeset_lock_all(dev); | |
602 | intel_modeset_setup_hw_state(dev, true); | |
603 | drm_modeset_unlock_all(dev); | |
15239099 DV |
604 | |
605 | /* | |
606 | * ... but also need to make sure that hotplug processing | |
607 | * doesn't cause havoc. Like in the driver load code we don't | |
608 | * bother with the tiny race here where we might loose hotplug | |
609 | * notifications. | |
610 | * */ | |
20afbda2 | 611 | intel_hpd_init(dev); |
15239099 | 612 | dev_priv->enable_hotplug_processing = true; |
bb60b969 JB |
613 | /* Config may have changed between suspend and resume */ |
614 | intel_resume_hotplug(dev); | |
d5bb081b | 615 | } |
1daed3fb | 616 | |
44834a67 CW |
617 | intel_opregion_init(dev); |
618 | ||
073f34d9 JB |
619 | /* |
620 | * The console lock can be pretty contented on resume due | |
621 | * to all the printk activity. Try to keep it out of the hot | |
622 | * path of resume if possible. | |
623 | */ | |
624 | if (console_trylock()) { | |
b6f3eff7 | 625 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
626 | console_unlock(); |
627 | } else { | |
628 | schedule_work(&dev_priv->console_resume_work); | |
629 | } | |
630 | ||
c67a470b PZ |
631 | /* Undo what we did at i915_drm_freeze so the refcount goes back to the |
632 | * expected level. */ | |
633 | hsw_enable_package_c8(dev_priv); | |
634 | ||
b8efb17b ZR |
635 | mutex_lock(&dev_priv->modeset_restore_lock); |
636 | dev_priv->modeset_restore = MODESET_DONE; | |
637 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
84b79f8d RW |
638 | return error; |
639 | } | |
640 | ||
1abd02e2 JB |
641 | static int i915_drm_thaw(struct drm_device *dev) |
642 | { | |
643 | int error = 0; | |
644 | ||
907b28c5 | 645 | intel_uncore_sanitize(dev); |
1abd02e2 JB |
646 | |
647 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
648 | mutex_lock(&dev->struct_mutex); | |
649 | i915_gem_restore_gtt_mappings(dev); | |
650 | mutex_unlock(&dev->struct_mutex); | |
651 | } | |
652 | ||
653 | __i915_drm_thaw(dev); | |
654 | ||
84b79f8d RW |
655 | return error; |
656 | } | |
657 | ||
6a9ee8af | 658 | int i915_resume(struct drm_device *dev) |
84b79f8d | 659 | { |
1abd02e2 | 660 | struct drm_i915_private *dev_priv = dev->dev_private; |
6eecba33 CW |
661 | int ret; |
662 | ||
5bcf719b DA |
663 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
664 | return 0; | |
665 | ||
84b79f8d RW |
666 | if (pci_enable_device(dev->pdev)) |
667 | return -EIO; | |
668 | ||
669 | pci_set_master(dev->pdev); | |
670 | ||
907b28c5 | 671 | intel_uncore_sanitize(dev); |
1abd02e2 JB |
672 | |
673 | /* | |
674 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
675 | * earlier) need this since the BIOS might clear all our scratch PTEs. | |
676 | */ | |
677 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
678 | !dev_priv->opregion.header) { | |
679 | mutex_lock(&dev->struct_mutex); | |
680 | i915_gem_restore_gtt_mappings(dev); | |
681 | mutex_unlock(&dev->struct_mutex); | |
682 | } | |
683 | ||
684 | ret = __i915_drm_thaw(dev); | |
6eecba33 CW |
685 | if (ret) |
686 | return ret; | |
687 | ||
688 | drm_kms_helper_poll_enable(dev); | |
689 | return 0; | |
ba8bbcf6 JB |
690 | } |
691 | ||
11ed50ec | 692 | /** |
f3953dcb | 693 | * i915_reset - reset chip after a hang |
11ed50ec | 694 | * @dev: drm device to reset |
11ed50ec BG |
695 | * |
696 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
697 | * reset or otherwise an error code. | |
698 | * | |
699 | * Procedure is fairly simple: | |
700 | * - reset the chip using the reset reg | |
701 | * - re-init context state | |
702 | * - re-init hardware status page | |
703 | * - re-init ring buffer | |
704 | * - re-init interrupt state | |
705 | * - re-init display | |
706 | */ | |
d4b8bb2a | 707 | int i915_reset(struct drm_device *dev) |
11ed50ec BG |
708 | { |
709 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2e7c8ee7 | 710 | bool simulated; |
0573ed4a | 711 | int ret; |
11ed50ec | 712 | |
d78cb50b CW |
713 | if (!i915_try_reset) |
714 | return 0; | |
715 | ||
d54a02c0 | 716 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 717 | |
069efc1d | 718 | i915_gem_reset(dev); |
77f01230 | 719 | |
2e7c8ee7 CW |
720 | simulated = dev_priv->gpu_error.stop_rings != 0; |
721 | ||
722 | if (!simulated && get_seconds() - dev_priv->gpu_error.last_reset < 5) { | |
ae681d96 | 723 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
2e7c8ee7 CW |
724 | ret = -ENODEV; |
725 | } else { | |
d4b8bb2a | 726 | ret = intel_gpu_reset(dev); |
350d2706 | 727 | |
2e7c8ee7 CW |
728 | /* Also reset the gpu hangman. */ |
729 | if (simulated) { | |
730 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
731 | dev_priv->gpu_error.stop_rings = 0; | |
732 | if (ret == -ENODEV) { | |
733 | DRM_ERROR("Reset not implemented, but ignoring " | |
734 | "error for simulated gpu hangs\n"); | |
735 | ret = 0; | |
736 | } | |
737 | } else | |
738 | dev_priv->gpu_error.last_reset = get_seconds(); | |
739 | } | |
0573ed4a | 740 | if (ret) { |
f803aa55 | 741 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 742 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 743 | return ret; |
11ed50ec BG |
744 | } |
745 | ||
746 | /* Ok, now get things going again... */ | |
747 | ||
748 | /* | |
749 | * Everything depends on having the GTT running, so we need to start | |
750 | * there. Fortunately we don't need to do this unless we reset the | |
751 | * chip at a PCI level. | |
752 | * | |
753 | * Next we need to restore the context, but we don't use those | |
754 | * yet either... | |
755 | * | |
756 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
757 | * was running at the time of the reset (i.e. we weren't VT | |
758 | * switched away). | |
759 | */ | |
760 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 761 | !dev_priv->ums.mm_suspended) { |
b4519513 CW |
762 | struct intel_ring_buffer *ring; |
763 | int i; | |
764 | ||
db1b76ca | 765 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 766 | |
f691e2f4 DV |
767 | i915_gem_init_swizzling(dev); |
768 | ||
b4519513 CW |
769 | for_each_ring(ring, dev_priv, i) |
770 | ring->init(ring); | |
75a6898f | 771 | |
254f965c | 772 | i915_gem_context_init(dev); |
b7c36d25 BW |
773 | if (dev_priv->mm.aliasing_ppgtt) { |
774 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
775 | if (ret) | |
776 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
777 | } | |
e21af88d | 778 | |
8e88a2bd DV |
779 | /* |
780 | * It would make sense to re-init all the other hw state, at | |
781 | * least the rps/rc6/emon init done within modeset_init_hw. For | |
782 | * some unknown reason, this blows up my ilk, so don't. | |
783 | */ | |
f817586c | 784 | |
8e88a2bd | 785 | mutex_unlock(&dev->struct_mutex); |
f817586c | 786 | |
11ed50ec BG |
787 | drm_irq_uninstall(dev); |
788 | drm_irq_install(dev); | |
20afbda2 | 789 | intel_hpd_init(dev); |
bcbc324a DV |
790 | } else { |
791 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
792 | } |
793 | ||
11ed50ec BG |
794 | return 0; |
795 | } | |
796 | ||
56550d94 | 797 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 798 | { |
01a06850 DV |
799 | struct intel_device_info *intel_info = |
800 | (struct intel_device_info *) ent->driver_data; | |
801 | ||
5fe49d86 CW |
802 | /* Only bind to function 0 of the device. Early generations |
803 | * used function 1 as a placeholder for multi-head. This causes | |
804 | * us confusion instead, especially on the systems where both | |
805 | * functions have the same PCI-ID! | |
806 | */ | |
807 | if (PCI_FUNC(pdev->devfn)) | |
808 | return -ENODEV; | |
809 | ||
01a06850 DV |
810 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
811 | * implementation for gen3 (and only gen3) that used legacy drm maps | |
812 | * (gasp!) to share buffers between X and the client. Hence we need to | |
813 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ | |
814 | if (intel_info->gen != 3) { | |
815 | driver.driver_features &= | |
816 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); | |
817 | } else if (!intel_agp_enabled) { | |
818 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
819 | return -ENODEV; | |
820 | } | |
821 | ||
dcdb1674 | 822 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
823 | } |
824 | ||
825 | static void | |
826 | i915_pci_remove(struct pci_dev *pdev) | |
827 | { | |
828 | struct drm_device *dev = pci_get_drvdata(pdev); | |
829 | ||
830 | drm_put_dev(dev); | |
831 | } | |
832 | ||
84b79f8d | 833 | static int i915_pm_suspend(struct device *dev) |
112b715e | 834 | { |
84b79f8d RW |
835 | struct pci_dev *pdev = to_pci_dev(dev); |
836 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
837 | int error; | |
112b715e | 838 | |
84b79f8d RW |
839 | if (!drm_dev || !drm_dev->dev_private) { |
840 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
841 | return -ENODEV; | |
842 | } | |
112b715e | 843 | |
5bcf719b DA |
844 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
845 | return 0; | |
846 | ||
84b79f8d RW |
847 | error = i915_drm_freeze(drm_dev); |
848 | if (error) | |
849 | return error; | |
112b715e | 850 | |
84b79f8d RW |
851 | pci_disable_device(pdev); |
852 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 853 | |
84b79f8d | 854 | return 0; |
cbda12d7 ZW |
855 | } |
856 | ||
84b79f8d | 857 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 858 | { |
84b79f8d RW |
859 | struct pci_dev *pdev = to_pci_dev(dev); |
860 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
861 | ||
862 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
863 | } |
864 | ||
84b79f8d | 865 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 866 | { |
84b79f8d RW |
867 | struct pci_dev *pdev = to_pci_dev(dev); |
868 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
869 | ||
870 | if (!drm_dev || !drm_dev->dev_private) { | |
871 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
872 | return -ENODEV; | |
873 | } | |
874 | ||
875 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
876 | } |
877 | ||
84b79f8d | 878 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 879 | { |
84b79f8d RW |
880 | struct pci_dev *pdev = to_pci_dev(dev); |
881 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
882 | ||
883 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
884 | } |
885 | ||
84b79f8d | 886 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 887 | { |
84b79f8d RW |
888 | struct pci_dev *pdev = to_pci_dev(dev); |
889 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 890 | |
61caf87c | 891 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
892 | } |
893 | ||
b4b78d12 | 894 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
895 | .suspend = i915_pm_suspend, |
896 | .resume = i915_pm_resume, | |
897 | .freeze = i915_pm_freeze, | |
898 | .thaw = i915_pm_thaw, | |
899 | .poweroff = i915_pm_poweroff, | |
900 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
901 | }; |
902 | ||
78b68556 | 903 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 904 | .fault = i915_gem_fault, |
ab00b3e5 JB |
905 | .open = drm_gem_vm_open, |
906 | .close = drm_gem_vm_close, | |
de151cf6 JB |
907 | }; |
908 | ||
e08e96de AV |
909 | static const struct file_operations i915_driver_fops = { |
910 | .owner = THIS_MODULE, | |
911 | .open = drm_open, | |
912 | .release = drm_release, | |
913 | .unlocked_ioctl = drm_ioctl, | |
914 | .mmap = drm_gem_mmap, | |
915 | .poll = drm_poll, | |
e08e96de AV |
916 | .read = drm_read, |
917 | #ifdef CONFIG_COMPAT | |
918 | .compat_ioctl = i915_compat_ioctl, | |
919 | #endif | |
920 | .llseek = noop_llseek, | |
921 | }; | |
922 | ||
1da177e4 | 923 | static struct drm_driver driver = { |
0c54781b MW |
924 | /* Don't use MTRRs here; the Xserver or userspace app should |
925 | * deal with them for Intel hardware. | |
792d2b9a | 926 | */ |
673a394b | 927 | .driver_features = |
28185647 | 928 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | |
10ba5012 KH |
929 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
930 | DRIVER_RENDER, | |
22eae947 | 931 | .load = i915_driver_load, |
ba8bbcf6 | 932 | .unload = i915_driver_unload, |
673a394b | 933 | .open = i915_driver_open, |
22eae947 DA |
934 | .lastclose = i915_driver_lastclose, |
935 | .preclose = i915_driver_preclose, | |
673a394b | 936 | .postclose = i915_driver_postclose, |
d8e29209 RW |
937 | |
938 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
939 | .suspend = i915_suspend, | |
940 | .resume = i915_resume, | |
941 | ||
cda17380 | 942 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
943 | .master_create = i915_master_create, |
944 | .master_destroy = i915_master_destroy, | |
955b12de | 945 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
946 | .debugfs_init = i915_debugfs_init, |
947 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 948 | #endif |
673a394b EA |
949 | .gem_init_object = i915_gem_init_object, |
950 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 951 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
952 | |
953 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
954 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
955 | .gem_prime_export = i915_gem_prime_export, | |
956 | .gem_prime_import = i915_gem_prime_import, | |
957 | ||
ff72145b DA |
958 | .dumb_create = i915_gem_dumb_create, |
959 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 960 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 961 | .ioctls = i915_ioctls, |
e08e96de | 962 | .fops = &i915_driver_fops, |
22eae947 DA |
963 | .name = DRIVER_NAME, |
964 | .desc = DRIVER_DESC, | |
965 | .date = DRIVER_DATE, | |
966 | .major = DRIVER_MAJOR, | |
967 | .minor = DRIVER_MINOR, | |
968 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
969 | }; |
970 | ||
8410ea3b DA |
971 | static struct pci_driver i915_pci_driver = { |
972 | .name = DRIVER_NAME, | |
973 | .id_table = pciidlist, | |
974 | .probe = i915_pci_probe, | |
975 | .remove = i915_pci_remove, | |
976 | .driver.pm = &i915_pm_ops, | |
977 | }; | |
978 | ||
1da177e4 LT |
979 | static int __init i915_init(void) |
980 | { | |
981 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
982 | |
983 | /* | |
984 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
985 | * explicitly disabled with the module pararmeter. | |
986 | * | |
987 | * Otherwise, just follow the parameter (defaulting to off). | |
988 | * | |
989 | * Allow optional vga_text_mode_force boot option to override | |
990 | * the default behavior. | |
991 | */ | |
992 | #if defined(CONFIG_DRM_I915_KMS) | |
993 | if (i915_modeset != 0) | |
994 | driver.driver_features |= DRIVER_MODESET; | |
995 | #endif | |
996 | if (i915_modeset == 1) | |
997 | driver.driver_features |= DRIVER_MODESET; | |
998 | ||
999 | #ifdef CONFIG_VGA_CONSOLE | |
1000 | if (vgacon_text_force() && i915_modeset == -1) | |
1001 | driver.driver_features &= ~DRIVER_MODESET; | |
1002 | #endif | |
1003 | ||
3885c6bb CW |
1004 | if (!(driver.driver_features & DRIVER_MODESET)) |
1005 | driver.get_vblank_timestamp = NULL; | |
1006 | ||
8410ea3b | 1007 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1008 | } |
1009 | ||
1010 | static void __exit i915_exit(void) | |
1011 | { | |
8410ea3b | 1012 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1013 | } |
1014 | ||
1015 | module_init(i915_init); | |
1016 | module_exit(i915_exit); | |
1017 | ||
b5e89ed5 DA |
1018 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1019 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1020 | MODULE_LICENSE("GPL and additional rights"); |