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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
354ff967 | 39 | #include "drm_crtc_helper.h" |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a35d9d3c | 50 | int i915_panel_ignore_lid __read_mostly = 0; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 BW |
52 | MODULE_PARM_DESC(panel_ignore_lid, |
53 | "Override lid status (0=autodetect [default], 1=lid open, " | |
54 | "-1=lid closed)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
ac668088 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
112b715e | 121 | static struct drm_driver driver; |
1f7a6e37 | 122 | extern int intel_agp_enabled; |
112b715e | 123 | |
cfdf1fa2 | 124 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 125 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 126 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
127 | .vendor = 0x8086, \ |
128 | .device = id, \ | |
129 | .subvendor = PCI_ANY_ID, \ | |
130 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
131 | .driver_data = (unsigned long) info } |
132 | ||
9a7e8492 | 133 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 134 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 135 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
136 | }; |
137 | ||
9a7e8492 | 138 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 139 | .gen = 2, |
31578148 | 140 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
141 | }; |
142 | ||
9a7e8492 | 143 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 144 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 145 | .cursor_needs_physical = 1, |
31578148 | 146 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
147 | }; |
148 | ||
9a7e8492 | 149 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 150 | .gen = 2, |
31578148 | 151 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
152 | }; |
153 | ||
9a7e8492 | 154 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 155 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 156 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 157 | }; |
9a7e8492 | 158 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 159 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 160 | .cursor_needs_physical = 1, |
31578148 | 161 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 162 | .supports_tv = 1, |
cfdf1fa2 | 163 | }; |
9a7e8492 | 164 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 165 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 166 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 167 | }; |
9a7e8492 | 168 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 169 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 170 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 171 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 172 | .supports_tv = 1, |
cfdf1fa2 KH |
173 | }; |
174 | ||
9a7e8492 | 175 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 176 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 177 | .has_hotplug = 1, |
31578148 | 178 | .has_overlay = 1, |
cfdf1fa2 KH |
179 | }; |
180 | ||
9a7e8492 | 181 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 182 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 183 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 184 | .has_overlay = 1, |
a6c45cf0 | 185 | .supports_tv = 1, |
cfdf1fa2 KH |
186 | }; |
187 | ||
9a7e8492 | 188 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 189 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 190 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 191 | .has_overlay = 1, |
cfdf1fa2 KH |
192 | }; |
193 | ||
9a7e8492 | 194 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 195 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 196 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 197 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
198 | }; |
199 | ||
9a7e8492 | 200 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 201 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 202 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 203 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 204 | .supports_tv = 1, |
92f49d9c | 205 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
206 | }; |
207 | ||
9a7e8492 | 208 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 209 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 210 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 211 | .has_overlay = 1, |
cfdf1fa2 KH |
212 | }; |
213 | ||
9a7e8492 | 214 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 215 | .gen = 5, |
5a117db7 | 216 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 217 | .has_bsd_ring = 1, |
7e508a27 | 218 | .has_pch_split = 1, |
cfdf1fa2 KH |
219 | }; |
220 | ||
9a7e8492 | 221 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 222 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 223 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 224 | .has_fbc = 1, |
92f49d9c | 225 | .has_bsd_ring = 1, |
7e508a27 | 226 | .has_pch_split = 1, |
cfdf1fa2 KH |
227 | }; |
228 | ||
9a7e8492 | 229 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 230 | .gen = 6, |
c96c3a8c | 231 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 232 | .has_bsd_ring = 1, |
549f7365 | 233 | .has_blt_ring = 1, |
3d29b842 | 234 | .has_llc = 1, |
7e508a27 | 235 | .has_pch_split = 1, |
f6e450a6 EA |
236 | }; |
237 | ||
9a7e8492 | 238 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 239 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 240 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 241 | .has_fbc = 1, |
881f47b6 | 242 | .has_bsd_ring = 1, |
549f7365 | 243 | .has_blt_ring = 1, |
3d29b842 | 244 | .has_llc = 1, |
7e508a27 | 245 | .has_pch_split = 1, |
a13e4093 EA |
246 | }; |
247 | ||
c76b615c JB |
248 | static const struct intel_device_info intel_ivybridge_d_info = { |
249 | .is_ivybridge = 1, .gen = 7, | |
250 | .need_gfx_hws = 1, .has_hotplug = 1, | |
251 | .has_bsd_ring = 1, | |
252 | .has_blt_ring = 1, | |
3d29b842 | 253 | .has_llc = 1, |
7e508a27 | 254 | .has_pch_split = 1, |
c76b615c JB |
255 | }; |
256 | ||
257 | static const struct intel_device_info intel_ivybridge_m_info = { | |
258 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, | |
259 | .need_gfx_hws = 1, .has_hotplug = 1, | |
260 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ | |
261 | .has_bsd_ring = 1, | |
262 | .has_blt_ring = 1, | |
3d29b842 | 263 | .has_llc = 1, |
7e508a27 | 264 | .has_pch_split = 1, |
c76b615c JB |
265 | }; |
266 | ||
70a3eb7a JB |
267 | static const struct intel_device_info intel_valleyview_m_info = { |
268 | .gen = 7, .is_mobile = 1, | |
269 | .need_gfx_hws = 1, .has_hotplug = 1, | |
270 | .has_fbc = 0, | |
271 | .has_bsd_ring = 1, | |
272 | .has_blt_ring = 1, | |
273 | .is_valleyview = 1, | |
274 | }; | |
275 | ||
276 | static const struct intel_device_info intel_valleyview_d_info = { | |
277 | .gen = 7, | |
278 | .need_gfx_hws = 1, .has_hotplug = 1, | |
279 | .has_fbc = 0, | |
280 | .has_bsd_ring = 1, | |
281 | .has_blt_ring = 1, | |
282 | .is_valleyview = 1, | |
283 | }; | |
284 | ||
4cae9ae0 ED |
285 | static const struct intel_device_info intel_haswell_d_info = { |
286 | .is_haswell = 1, .gen = 7, | |
287 | .need_gfx_hws = 1, .has_hotplug = 1, | |
288 | .has_bsd_ring = 1, | |
289 | .has_blt_ring = 1, | |
290 | .has_llc = 1, | |
291 | .has_pch_split = 1, | |
292 | }; | |
293 | ||
294 | static const struct intel_device_info intel_haswell_m_info = { | |
295 | .is_haswell = 1, .gen = 7, .is_mobile = 1, | |
296 | .need_gfx_hws = 1, .has_hotplug = 1, | |
297 | .has_bsd_ring = 1, | |
298 | .has_blt_ring = 1, | |
299 | .has_llc = 1, | |
300 | .has_pch_split = 1, | |
c76b615c JB |
301 | }; |
302 | ||
6103da0d CW |
303 | static const struct pci_device_id pciidlist[] = { /* aka */ |
304 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
305 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
306 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 307 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
308 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
309 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
310 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
311 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
312 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
313 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
314 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
315 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
316 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
317 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
318 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
319 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
320 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
321 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
322 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
323 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
324 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
325 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
326 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
327 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
328 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
329 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 330 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
331 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
332 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
333 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
334 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 335 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
336 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
337 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 338 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 339 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 340 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 341 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
342 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
343 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
344 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
345 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
346 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
cc22a938 | 347 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
49ae35f2 | 348 | {0, 0, 0} |
1da177e4 LT |
349 | }; |
350 | ||
79e53945 JB |
351 | #if defined(CONFIG_DRM_I915_KMS) |
352 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
353 | #endif | |
354 | ||
3bad0781 | 355 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
90711d50 | 356 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
3bad0781 | 357 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
c792513b | 358 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
eb877ebf | 359 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
3bad0781 | 360 | |
0206e353 | 361 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
362 | { |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
364 | struct pci_dev *pch; | |
365 | ||
366 | /* | |
367 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
368 | * make graphics device passthrough work easy for VMM, that only | |
369 | * need to expose ISA bridge to let driver know the real hardware | |
370 | * underneath. This is a requirement from virtualization team. | |
371 | */ | |
372 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
373 | if (pch) { | |
374 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
375 | int id; | |
376 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
377 | ||
90711d50 JB |
378 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
379 | dev_priv->pch_type = PCH_IBX; | |
380 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
381 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
3bad0781 ZW |
382 | dev_priv->pch_type = PCH_CPT; |
383 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
c792513b JB |
384 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
385 | /* PantherPoint is CPT compatible */ | |
386 | dev_priv->pch_type = PCH_CPT; | |
387 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | |
eb877ebf ED |
388 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
389 | dev_priv->pch_type = PCH_LPT; | |
390 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
3bad0781 ZW |
391 | } |
392 | } | |
393 | pci_dev_put(pch); | |
394 | } | |
395 | } | |
396 | ||
8d715f00 | 397 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
eb43f4af CW |
398 | { |
399 | int count; | |
400 | ||
401 | count = 0; | |
402 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
403 | udelay(10); | |
404 | ||
405 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
406 | POSTING_READ(FORCEWAKE); | |
407 | ||
408 | count = 0; | |
409 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) | |
410 | udelay(10); | |
411 | } | |
412 | ||
8d715f00 KP |
413 | void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
414 | { | |
415 | int count; | |
416 | ||
417 | count = 0; | |
418 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) | |
419 | udelay(10); | |
420 | ||
421 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1); | |
422 | POSTING_READ(FORCEWAKE_MT); | |
423 | ||
424 | count = 0; | |
425 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) | |
426 | udelay(10); | |
427 | } | |
428 | ||
fcca7926 BW |
429 | /* |
430 | * Generally this is called implicitly by the register read function. However, | |
431 | * if some sequence requires the GT to not power down then this function should | |
432 | * be called at the beginning of the sequence followed by a call to | |
433 | * gen6_gt_force_wake_put() at the end of the sequence. | |
434 | */ | |
435 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
436 | { | |
9f1f46a4 | 437 | unsigned long irqflags; |
fcca7926 | 438 | |
9f1f46a4 DV |
439 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
440 | if (dev_priv->forcewake_count++ == 0) | |
8d715f00 | 441 | dev_priv->display.force_wake_get(dev_priv); |
9f1f46a4 | 442 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
443 | } |
444 | ||
ee64cbdb BW |
445 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
446 | { | |
447 | u32 gtfifodbg; | |
448 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); | |
449 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, | |
450 | "MMIO read or write has been dropped %x\n", gtfifodbg)) | |
451 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); | |
452 | } | |
453 | ||
8d715f00 | 454 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
eb43f4af CW |
455 | { |
456 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
ee64cbdb BW |
457 | /* The below doubles as a POSTING_READ */ |
458 | gen6_gt_check_fifodbg(dev_priv); | |
eb43f4af CW |
459 | } |
460 | ||
8d715f00 KP |
461 | void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
462 | { | |
463 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0); | |
ee64cbdb BW |
464 | /* The below doubles as a POSTING_READ */ |
465 | gen6_gt_check_fifodbg(dev_priv); | |
8d715f00 KP |
466 | } |
467 | ||
fcca7926 BW |
468 | /* |
469 | * see gen6_gt_force_wake_get() | |
470 | */ | |
471 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
472 | { | |
9f1f46a4 | 473 | unsigned long irqflags; |
fcca7926 | 474 | |
9f1f46a4 DV |
475 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
476 | if (--dev_priv->forcewake_count == 0) | |
8d715f00 | 477 | dev_priv->display.force_wake_put(dev_priv); |
9f1f46a4 | 478 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
479 | } |
480 | ||
67a3744f | 481 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
91355834 | 482 | { |
67a3744f BW |
483 | int ret = 0; |
484 | ||
0206e353 | 485 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
95736720 CW |
486 | int loop = 500; |
487 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
488 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { | |
489 | udelay(10); | |
490 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
491 | } | |
67a3744f BW |
492 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
493 | ++ret; | |
95736720 | 494 | dev_priv->gt_fifo_count = fifo; |
91355834 | 495 | } |
95736720 | 496 | dev_priv->gt_fifo_count--; |
67a3744f BW |
497 | |
498 | return ret; | |
91355834 CW |
499 | } |
500 | ||
575155a9 JB |
501 | void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
502 | { | |
503 | int count; | |
504 | ||
505 | count = 0; | |
506 | ||
507 | /* Already awake? */ | |
508 | if ((I915_READ(0x130094) & 0xa1) == 0xa1) | |
509 | return; | |
510 | ||
511 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff); | |
512 | POSTING_READ(FORCEWAKE_VLV); | |
513 | ||
514 | count = 0; | |
515 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0) | |
516 | udelay(10); | |
517 | } | |
518 | ||
519 | void vlv_force_wake_put(struct drm_i915_private *dev_priv) | |
520 | { | |
521 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000); | |
522 | /* FIXME: confirm VLV behavior with Punit folks */ | |
523 | POSTING_READ(FORCEWAKE_VLV); | |
524 | } | |
525 | ||
84b79f8d | 526 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 527 | { |
61caf87c RW |
528 | struct drm_i915_private *dev_priv = dev->dev_private; |
529 | ||
5bcf719b DA |
530 | drm_kms_helper_poll_disable(dev); |
531 | ||
ba8bbcf6 | 532 | pci_save_state(dev->pdev); |
ba8bbcf6 | 533 | |
5669fcac | 534 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 535 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
536 | int error = i915_gem_idle(dev); |
537 | if (error) { | |
226485e9 | 538 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
539 | "GEM idle failed, resume might fail\n"); |
540 | return error; | |
541 | } | |
226485e9 | 542 | drm_irq_uninstall(dev); |
5669fcac JB |
543 | } |
544 | ||
9e06dd39 JB |
545 | i915_save_state(dev); |
546 | ||
44834a67 | 547 | intel_opregion_fini(dev); |
8ee1c3db | 548 | |
84b79f8d RW |
549 | /* Modeset on resume, not lid events */ |
550 | dev_priv->modeset_on_lid = 0; | |
61caf87c | 551 | |
3fa016a0 DA |
552 | console_lock(); |
553 | intel_fbdev_set_suspend(dev, 1); | |
554 | console_unlock(); | |
555 | ||
61caf87c | 556 | return 0; |
84b79f8d RW |
557 | } |
558 | ||
6a9ee8af | 559 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
560 | { |
561 | int error; | |
562 | ||
563 | if (!dev || !dev->dev_private) { | |
564 | DRM_ERROR("dev: %p\n", dev); | |
565 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
566 | return -ENODEV; | |
567 | } | |
568 | ||
569 | if (state.event == PM_EVENT_PRETHAW) | |
570 | return 0; | |
571 | ||
5bcf719b DA |
572 | |
573 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
574 | return 0; | |
6eecba33 | 575 | |
84b79f8d RW |
576 | error = i915_drm_freeze(dev); |
577 | if (error) | |
578 | return error; | |
579 | ||
b932ccb5 DA |
580 | if (state.event == PM_EVENT_SUSPEND) { |
581 | /* Shut down the device */ | |
582 | pci_disable_device(dev->pdev); | |
583 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
584 | } | |
ba8bbcf6 JB |
585 | |
586 | return 0; | |
587 | } | |
588 | ||
84b79f8d | 589 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 590 | { |
5669fcac | 591 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 592 | int error = 0; |
8ee1c3db | 593 | |
d1c3b177 CW |
594 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
595 | mutex_lock(&dev->struct_mutex); | |
596 | i915_gem_restore_gtt_mappings(dev); | |
597 | mutex_unlock(&dev->struct_mutex); | |
598 | } | |
599 | ||
61caf87c | 600 | i915_restore_state(dev); |
44834a67 | 601 | intel_opregion_setup(dev); |
61caf87c | 602 | |
5669fcac JB |
603 | /* KMS EnterVT equivalent */ |
604 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
605 | mutex_lock(&dev->struct_mutex); | |
606 | dev_priv->mm.suspended = 0; | |
607 | ||
f691e2f4 | 608 | error = i915_gem_init_hw(dev); |
5669fcac | 609 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 610 | |
9fb526db KP |
611 | if (HAS_PCH_SPLIT(dev)) |
612 | ironlake_init_pch_refclk(dev); | |
613 | ||
500f7147 | 614 | drm_mode_config_reset(dev); |
226485e9 | 615 | drm_irq_install(dev); |
84b79f8d | 616 | |
354ff967 | 617 | /* Resume the modeset for every activated CRTC */ |
927a2f11 | 618 | mutex_lock(&dev->mode_config.mutex); |
354ff967 | 619 | drm_helper_resume_force_mode(dev); |
927a2f11 | 620 | mutex_unlock(&dev->mode_config.mutex); |
5669fcac | 621 | |
ac668088 | 622 | if (IS_IRONLAKE_M(dev)) |
d5bb081b JB |
623 | ironlake_enable_rc6(dev); |
624 | } | |
1daed3fb | 625 | |
44834a67 CW |
626 | intel_opregion_init(dev); |
627 | ||
c9354c85 | 628 | dev_priv->modeset_on_lid = 0; |
06891e27 | 629 | |
3fa016a0 DA |
630 | console_lock(); |
631 | intel_fbdev_set_suspend(dev, 0); | |
632 | console_unlock(); | |
84b79f8d RW |
633 | return error; |
634 | } | |
635 | ||
6a9ee8af | 636 | int i915_resume(struct drm_device *dev) |
84b79f8d | 637 | { |
6eecba33 CW |
638 | int ret; |
639 | ||
5bcf719b DA |
640 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
641 | return 0; | |
642 | ||
84b79f8d RW |
643 | if (pci_enable_device(dev->pdev)) |
644 | return -EIO; | |
645 | ||
646 | pci_set_master(dev->pdev); | |
647 | ||
6eecba33 CW |
648 | ret = i915_drm_thaw(dev); |
649 | if (ret) | |
650 | return ret; | |
651 | ||
652 | drm_kms_helper_poll_enable(dev); | |
653 | return 0; | |
ba8bbcf6 JB |
654 | } |
655 | ||
dc96e9b8 CW |
656 | static int i8xx_do_reset(struct drm_device *dev, u8 flags) |
657 | { | |
658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
659 | ||
660 | if (IS_I85X(dev)) | |
661 | return -ENODEV; | |
662 | ||
663 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
664 | POSTING_READ(D_STATE); | |
665 | ||
666 | if (IS_I830(dev) || IS_845G(dev)) { | |
667 | I915_WRITE(DEBUG_RESET_I830, | |
668 | DEBUG_RESET_DISPLAY | | |
669 | DEBUG_RESET_RENDER | | |
670 | DEBUG_RESET_FULL); | |
671 | POSTING_READ(DEBUG_RESET_I830); | |
672 | msleep(1); | |
673 | ||
674 | I915_WRITE(DEBUG_RESET_I830, 0); | |
675 | POSTING_READ(DEBUG_RESET_I830); | |
676 | } | |
677 | ||
678 | msleep(1); | |
679 | ||
680 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
681 | POSTING_READ(D_STATE); | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
f49f0586 KG |
686 | static int i965_reset_complete(struct drm_device *dev) |
687 | { | |
688 | u8 gdrst; | |
eeccdcac | 689 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
f49f0586 KG |
690 | return gdrst & 0x1; |
691 | } | |
692 | ||
0573ed4a KG |
693 | static int i965_do_reset(struct drm_device *dev, u8 flags) |
694 | { | |
695 | u8 gdrst; | |
696 | ||
ae681d96 CW |
697 | /* |
698 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
699 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
700 | * triggers the reset; when done, the hardware will clear it. | |
701 | */ | |
0573ed4a KG |
702 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
703 | pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1); | |
704 | ||
705 | return wait_for(i965_reset_complete(dev), 500); | |
706 | } | |
707 | ||
708 | static int ironlake_do_reset(struct drm_device *dev, u8 flags) | |
709 | { | |
710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
711 | u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
712 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); | |
713 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
ba8bbcf6 JB |
714 | } |
715 | ||
cff458c2 EA |
716 | static int gen6_do_reset(struct drm_device *dev, u8 flags) |
717 | { | |
718 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b6e45f86 KP |
719 | int ret; |
720 | unsigned long irqflags; | |
cff458c2 | 721 | |
286fed41 KP |
722 | /* Hold gt_lock across reset to prevent any register access |
723 | * with forcewake not set correctly | |
724 | */ | |
b6e45f86 | 725 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
286fed41 KP |
726 | |
727 | /* Reset the chip */ | |
728 | ||
729 | /* GEN6_GDRST is not in the gt power well, no need to check | |
730 | * for fifo space for the write or forcewake the chip for | |
731 | * the read | |
732 | */ | |
733 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
734 | ||
735 | /* Spin waiting for the device to ack the reset request */ | |
736 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
737 | ||
738 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | |
b6e45f86 KP |
739 | if (dev_priv->forcewake_count) |
740 | dev_priv->display.force_wake_get(dev_priv); | |
286fed41 KP |
741 | else |
742 | dev_priv->display.force_wake_put(dev_priv); | |
743 | ||
744 | /* Restore fifo count */ | |
745 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
746 | ||
b6e45f86 KP |
747 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
748 | return ret; | |
cff458c2 EA |
749 | } |
750 | ||
11ed50ec | 751 | /** |
f3953dcb | 752 | * i915_reset - reset chip after a hang |
11ed50ec BG |
753 | * @dev: drm device to reset |
754 | * @flags: reset domains | |
755 | * | |
756 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
757 | * reset or otherwise an error code. | |
758 | * | |
759 | * Procedure is fairly simple: | |
760 | * - reset the chip using the reset reg | |
761 | * - re-init context state | |
762 | * - re-init hardware status page | |
763 | * - re-init ring buffer | |
764 | * - re-init interrupt state | |
765 | * - re-init display | |
766 | */ | |
f803aa55 | 767 | int i915_reset(struct drm_device *dev, u8 flags) |
11ed50ec BG |
768 | { |
769 | drm_i915_private_t *dev_priv = dev->dev_private; | |
11ed50ec BG |
770 | /* |
771 | * We really should only reset the display subsystem if we actually | |
772 | * need to | |
773 | */ | |
774 | bool need_display = true; | |
0573ed4a | 775 | int ret; |
11ed50ec | 776 | |
d78cb50b CW |
777 | if (!i915_try_reset) |
778 | return 0; | |
779 | ||
340479aa CW |
780 | if (!mutex_trylock(&dev->struct_mutex)) |
781 | return -EBUSY; | |
11ed50ec | 782 | |
069efc1d | 783 | i915_gem_reset(dev); |
77f01230 | 784 | |
f803aa55 | 785 | ret = -ENODEV; |
ae681d96 CW |
786 | if (get_seconds() - dev_priv->last_gpu_reset < 5) { |
787 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); | |
788 | } else switch (INTEL_INFO(dev)->gen) { | |
1083694a | 789 | case 7: |
cff458c2 EA |
790 | case 6: |
791 | ret = gen6_do_reset(dev, flags); | |
792 | break; | |
f803aa55 | 793 | case 5: |
0573ed4a | 794 | ret = ironlake_do_reset(dev, flags); |
f803aa55 CW |
795 | break; |
796 | case 4: | |
0573ed4a | 797 | ret = i965_do_reset(dev, flags); |
f803aa55 | 798 | break; |
dc96e9b8 CW |
799 | case 2: |
800 | ret = i8xx_do_reset(dev, flags); | |
801 | break; | |
f803aa55 | 802 | } |
ae681d96 | 803 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 804 | if (ret) { |
f803aa55 | 805 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 806 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 807 | return ret; |
11ed50ec BG |
808 | } |
809 | ||
810 | /* Ok, now get things going again... */ | |
811 | ||
812 | /* | |
813 | * Everything depends on having the GTT running, so we need to start | |
814 | * there. Fortunately we don't need to do this unless we reset the | |
815 | * chip at a PCI level. | |
816 | * | |
817 | * Next we need to restore the context, but we don't use those | |
818 | * yet either... | |
819 | * | |
820 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
821 | * was running at the time of the reset (i.e. we weren't VT | |
822 | * switched away). | |
823 | */ | |
824 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 825 | !dev_priv->mm.suspended) { |
11ed50ec | 826 | dev_priv->mm.suspended = 0; |
75a6898f | 827 | |
f691e2f4 DV |
828 | i915_gem_init_swizzling(dev); |
829 | ||
1ec14ad3 | 830 | dev_priv->ring[RCS].init(&dev_priv->ring[RCS]); |
75a6898f | 831 | if (HAS_BSD(dev)) |
1ec14ad3 | 832 | dev_priv->ring[VCS].init(&dev_priv->ring[VCS]); |
75a6898f | 833 | if (HAS_BLT(dev)) |
1ec14ad3 | 834 | dev_priv->ring[BCS].init(&dev_priv->ring[BCS]); |
75a6898f | 835 | |
e21af88d DV |
836 | i915_gem_init_ppgtt(dev); |
837 | ||
11ed50ec BG |
838 | mutex_unlock(&dev->struct_mutex); |
839 | drm_irq_uninstall(dev); | |
500f7147 | 840 | drm_mode_config_reset(dev); |
11ed50ec BG |
841 | drm_irq_install(dev); |
842 | mutex_lock(&dev->struct_mutex); | |
843 | } | |
844 | ||
9fd98141 CW |
845 | mutex_unlock(&dev->struct_mutex); |
846 | ||
11ed50ec | 847 | /* |
9fd98141 CW |
848 | * Perform a full modeset as on later generations, e.g. Ironlake, we may |
849 | * need to retrain the display link and cannot just restore the register | |
850 | * values. | |
11ed50ec | 851 | */ |
9fd98141 CW |
852 | if (need_display) { |
853 | mutex_lock(&dev->mode_config.mutex); | |
854 | drm_helper_resume_force_mode(dev); | |
855 | mutex_unlock(&dev->mode_config.mutex); | |
856 | } | |
11ed50ec | 857 | |
11ed50ec BG |
858 | return 0; |
859 | } | |
860 | ||
861 | ||
112b715e KH |
862 | static int __devinit |
863 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
864 | { | |
5fe49d86 CW |
865 | /* Only bind to function 0 of the device. Early generations |
866 | * used function 1 as a placeholder for multi-head. This causes | |
867 | * us confusion instead, especially on the systems where both | |
868 | * functions have the same PCI-ID! | |
869 | */ | |
870 | if (PCI_FUNC(pdev->devfn)) | |
871 | return -ENODEV; | |
872 | ||
dcdb1674 | 873 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
874 | } |
875 | ||
876 | static void | |
877 | i915_pci_remove(struct pci_dev *pdev) | |
878 | { | |
879 | struct drm_device *dev = pci_get_drvdata(pdev); | |
880 | ||
881 | drm_put_dev(dev); | |
882 | } | |
883 | ||
84b79f8d | 884 | static int i915_pm_suspend(struct device *dev) |
112b715e | 885 | { |
84b79f8d RW |
886 | struct pci_dev *pdev = to_pci_dev(dev); |
887 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
888 | int error; | |
112b715e | 889 | |
84b79f8d RW |
890 | if (!drm_dev || !drm_dev->dev_private) { |
891 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
892 | return -ENODEV; | |
893 | } | |
112b715e | 894 | |
5bcf719b DA |
895 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
896 | return 0; | |
897 | ||
84b79f8d RW |
898 | error = i915_drm_freeze(drm_dev); |
899 | if (error) | |
900 | return error; | |
112b715e | 901 | |
84b79f8d RW |
902 | pci_disable_device(pdev); |
903 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 904 | |
84b79f8d | 905 | return 0; |
cbda12d7 ZW |
906 | } |
907 | ||
84b79f8d | 908 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 909 | { |
84b79f8d RW |
910 | struct pci_dev *pdev = to_pci_dev(dev); |
911 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
912 | ||
913 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
914 | } |
915 | ||
84b79f8d | 916 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 917 | { |
84b79f8d RW |
918 | struct pci_dev *pdev = to_pci_dev(dev); |
919 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
920 | ||
921 | if (!drm_dev || !drm_dev->dev_private) { | |
922 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
923 | return -ENODEV; | |
924 | } | |
925 | ||
926 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
927 | } |
928 | ||
84b79f8d | 929 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 930 | { |
84b79f8d RW |
931 | struct pci_dev *pdev = to_pci_dev(dev); |
932 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
933 | ||
934 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
935 | } |
936 | ||
84b79f8d | 937 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 938 | { |
84b79f8d RW |
939 | struct pci_dev *pdev = to_pci_dev(dev); |
940 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 941 | |
61caf87c | 942 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
943 | } |
944 | ||
b4b78d12 | 945 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
946 | .suspend = i915_pm_suspend, |
947 | .resume = i915_pm_resume, | |
948 | .freeze = i915_pm_freeze, | |
949 | .thaw = i915_pm_thaw, | |
950 | .poweroff = i915_pm_poweroff, | |
951 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
952 | }; |
953 | ||
de151cf6 JB |
954 | static struct vm_operations_struct i915_gem_vm_ops = { |
955 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
956 | .open = drm_gem_vm_open, |
957 | .close = drm_gem_vm_close, | |
de151cf6 JB |
958 | }; |
959 | ||
e08e96de AV |
960 | static const struct file_operations i915_driver_fops = { |
961 | .owner = THIS_MODULE, | |
962 | .open = drm_open, | |
963 | .release = drm_release, | |
964 | .unlocked_ioctl = drm_ioctl, | |
965 | .mmap = drm_gem_mmap, | |
966 | .poll = drm_poll, | |
967 | .fasync = drm_fasync, | |
968 | .read = drm_read, | |
969 | #ifdef CONFIG_COMPAT | |
970 | .compat_ioctl = i915_compat_ioctl, | |
971 | #endif | |
972 | .llseek = noop_llseek, | |
973 | }; | |
974 | ||
1da177e4 | 975 | static struct drm_driver driver = { |
0c54781b MW |
976 | /* Don't use MTRRs here; the Xserver or userspace app should |
977 | * deal with them for Intel hardware. | |
792d2b9a | 978 | */ |
673a394b EA |
979 | .driver_features = |
980 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
981 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 982 | .load = i915_driver_load, |
ba8bbcf6 | 983 | .unload = i915_driver_unload, |
673a394b | 984 | .open = i915_driver_open, |
22eae947 DA |
985 | .lastclose = i915_driver_lastclose, |
986 | .preclose = i915_driver_preclose, | |
673a394b | 987 | .postclose = i915_driver_postclose, |
d8e29209 RW |
988 | |
989 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
990 | .suspend = i915_suspend, | |
991 | .resume = i915_resume, | |
992 | ||
cda17380 | 993 | .device_is_agp = i915_driver_device_is_agp, |
1da177e4 | 994 | .reclaim_buffers = drm_core_reclaim_buffers, |
7c1c2871 DA |
995 | .master_create = i915_master_create, |
996 | .master_destroy = i915_master_destroy, | |
955b12de | 997 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
998 | .debugfs_init = i915_debugfs_init, |
999 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1000 | #endif |
673a394b EA |
1001 | .gem_init_object = i915_gem_init_object, |
1002 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 1003 | .gem_vm_ops = &i915_gem_vm_ops, |
ff72145b DA |
1004 | .dumb_create = i915_gem_dumb_create, |
1005 | .dumb_map_offset = i915_gem_mmap_gtt, | |
1006 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 | 1007 | .ioctls = i915_ioctls, |
e08e96de | 1008 | .fops = &i915_driver_fops, |
22eae947 DA |
1009 | .name = DRIVER_NAME, |
1010 | .desc = DRIVER_DESC, | |
1011 | .date = DRIVER_DATE, | |
1012 | .major = DRIVER_MAJOR, | |
1013 | .minor = DRIVER_MINOR, | |
1014 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1015 | }; |
1016 | ||
8410ea3b DA |
1017 | static struct pci_driver i915_pci_driver = { |
1018 | .name = DRIVER_NAME, | |
1019 | .id_table = pciidlist, | |
1020 | .probe = i915_pci_probe, | |
1021 | .remove = i915_pci_remove, | |
1022 | .driver.pm = &i915_pm_ops, | |
1023 | }; | |
1024 | ||
1da177e4 LT |
1025 | static int __init i915_init(void) |
1026 | { | |
1f7a6e37 ZW |
1027 | if (!intel_agp_enabled) { |
1028 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
1029 | return -ENODEV; | |
1030 | } | |
1031 | ||
1da177e4 | 1032 | driver.num_ioctls = i915_max_ioctl; |
79e53945 JB |
1033 | |
1034 | /* | |
1035 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1036 | * explicitly disabled with the module pararmeter. | |
1037 | * | |
1038 | * Otherwise, just follow the parameter (defaulting to off). | |
1039 | * | |
1040 | * Allow optional vga_text_mode_force boot option to override | |
1041 | * the default behavior. | |
1042 | */ | |
1043 | #if defined(CONFIG_DRM_I915_KMS) | |
1044 | if (i915_modeset != 0) | |
1045 | driver.driver_features |= DRIVER_MODESET; | |
1046 | #endif | |
1047 | if (i915_modeset == 1) | |
1048 | driver.driver_features |= DRIVER_MODESET; | |
1049 | ||
1050 | #ifdef CONFIG_VGA_CONSOLE | |
1051 | if (vgacon_text_force() && i915_modeset == -1) | |
1052 | driver.driver_features &= ~DRIVER_MODESET; | |
1053 | #endif | |
1054 | ||
3885c6bb CW |
1055 | if (!(driver.driver_features & DRIVER_MODESET)) |
1056 | driver.get_vblank_timestamp = NULL; | |
1057 | ||
8410ea3b | 1058 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1059 | } |
1060 | ||
1061 | static void __exit i915_exit(void) | |
1062 | { | |
8410ea3b | 1063 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1064 | } |
1065 | ||
1066 | module_init(i915_init); | |
1067 | module_exit(i915_exit); | |
1068 | ||
b5e89ed5 DA |
1069 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1070 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1071 | MODULE_LICENSE("GPL and additional rights"); |
f7000883 | 1072 | |
b7d84096 JB |
1073 | /* We give fast paths for the really cool registers */ |
1074 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
1075 | (((dev_priv)->info->gen >= 6) && \ | |
1076 | ((reg) < 0x40000) && \ | |
575155a9 JB |
1077 | ((reg) != FORCEWAKE)) && \ |
1078 | (!IS_VALLEYVIEW((dev_priv)->dev)) | |
b7d84096 | 1079 | |
f7000883 AK |
1080 | #define __i915_read(x, y) \ |
1081 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
1082 | u##x val = 0; \ | |
1083 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
c937504e KP |
1084 | unsigned long irqflags; \ |
1085 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | |
1086 | if (dev_priv->forcewake_count == 0) \ | |
1087 | dev_priv->display.force_wake_get(dev_priv); \ | |
f7000883 | 1088 | val = read##y(dev_priv->regs + reg); \ |
c937504e KP |
1089 | if (dev_priv->forcewake_count == 0) \ |
1090 | dev_priv->display.force_wake_put(dev_priv); \ | |
1091 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | |
f7000883 AK |
1092 | } else { \ |
1093 | val = read##y(dev_priv->regs + reg); \ | |
1094 | } \ | |
1095 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | |
1096 | return val; \ | |
1097 | } | |
1098 | ||
1099 | __i915_read(8, b) | |
1100 | __i915_read(16, w) | |
1101 | __i915_read(32, l) | |
1102 | __i915_read(64, q) | |
1103 | #undef __i915_read | |
1104 | ||
1105 | #define __i915_write(x, y) \ | |
1106 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
67a3744f | 1107 | u32 __fifo_ret = 0; \ |
f7000883 AK |
1108 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1109 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
67a3744f | 1110 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
f7000883 AK |
1111 | } \ |
1112 | write##y(val, dev_priv->regs + reg); \ | |
67a3744f BW |
1113 | if (unlikely(__fifo_ret)) { \ |
1114 | gen6_gt_check_fifodbg(dev_priv); \ | |
1115 | } \ | |
f7000883 AK |
1116 | } |
1117 | __i915_write(8, b) | |
1118 | __i915_write(16, w) | |
1119 | __i915_write(32, l) | |
1120 | __i915_write(64, q) | |
1121 | #undef __i915_write |