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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a726915c | 50 | int i915_panel_ignore_lid __read_mostly = 1; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 | 52 | MODULE_PARM_DESC(panel_ignore_lid, |
a726915c DV |
53 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " |
54 | "-1=force lid closed, -2=force lid open)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
f57f9c16 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
0a3af268 RV |
121 | unsigned int i915_preliminary_hw_support __read_mostly = 0; |
122 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); | |
123 | MODULE_PARM_DESC(preliminary_hw_support, | |
124 | "Enable preliminary hardware support. " | |
125 | "Enable Haswell and ValleyView Support. " | |
126 | "(default: false)"); | |
127 | ||
112b715e | 128 | static struct drm_driver driver; |
1f7a6e37 | 129 | extern int intel_agp_enabled; |
112b715e | 130 | |
cfdf1fa2 | 131 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 132 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 133 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
134 | .vendor = 0x8086, \ |
135 | .device = id, \ | |
136 | .subvendor = PCI_ANY_ID, \ | |
137 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
138 | .driver_data = (unsigned long) info } |
139 | ||
9a7e8492 | 140 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 141 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 142 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
143 | }; |
144 | ||
9a7e8492 | 145 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 146 | .gen = 2, |
31578148 | 147 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
148 | }; |
149 | ||
9a7e8492 | 150 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 151 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 152 | .cursor_needs_physical = 1, |
31578148 | 153 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
154 | }; |
155 | ||
9a7e8492 | 156 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 157 | .gen = 2, |
31578148 | 158 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
159 | }; |
160 | ||
9a7e8492 | 161 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 162 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 163 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 164 | }; |
9a7e8492 | 165 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 166 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 167 | .cursor_needs_physical = 1, |
31578148 | 168 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 169 | .supports_tv = 1, |
cfdf1fa2 | 170 | }; |
9a7e8492 | 171 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 172 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 173 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 174 | }; |
9a7e8492 | 175 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 176 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 177 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 178 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 179 | .supports_tv = 1, |
cfdf1fa2 KH |
180 | }; |
181 | ||
9a7e8492 | 182 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 183 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 184 | .has_hotplug = 1, |
31578148 | 185 | .has_overlay = 1, |
cfdf1fa2 KH |
186 | }; |
187 | ||
9a7e8492 | 188 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 189 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 190 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 191 | .has_overlay = 1, |
a6c45cf0 | 192 | .supports_tv = 1, |
cfdf1fa2 KH |
193 | }; |
194 | ||
9a7e8492 | 195 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 196 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 197 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 198 | .has_overlay = 1, |
cfdf1fa2 KH |
199 | }; |
200 | ||
9a7e8492 | 201 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 202 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 203 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 204 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
205 | }; |
206 | ||
9a7e8492 | 207 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 208 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 209 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 210 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 211 | .supports_tv = 1, |
92f49d9c | 212 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
213 | }; |
214 | ||
9a7e8492 | 215 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 216 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 217 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 218 | .has_overlay = 1, |
cfdf1fa2 KH |
219 | }; |
220 | ||
9a7e8492 | 221 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 222 | .gen = 5, |
5a117db7 | 223 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 224 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
225 | }; |
226 | ||
9a7e8492 | 227 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 228 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 229 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 230 | .has_fbc = 1, |
92f49d9c | 231 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
232 | }; |
233 | ||
9a7e8492 | 234 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 235 | .gen = 6, |
c96c3a8c | 236 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 237 | .has_bsd_ring = 1, |
549f7365 | 238 | .has_blt_ring = 1, |
3d29b842 | 239 | .has_llc = 1, |
b7884eb4 | 240 | .has_force_wake = 1, |
f6e450a6 EA |
241 | }; |
242 | ||
9a7e8492 | 243 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 244 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 245 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 246 | .has_fbc = 1, |
881f47b6 | 247 | .has_bsd_ring = 1, |
549f7365 | 248 | .has_blt_ring = 1, |
3d29b842 | 249 | .has_llc = 1, |
b7884eb4 | 250 | .has_force_wake = 1, |
a13e4093 EA |
251 | }; |
252 | ||
c76b615c JB |
253 | static const struct intel_device_info intel_ivybridge_d_info = { |
254 | .is_ivybridge = 1, .gen = 7, | |
255 | .need_gfx_hws = 1, .has_hotplug = 1, | |
256 | .has_bsd_ring = 1, | |
257 | .has_blt_ring = 1, | |
3d29b842 | 258 | .has_llc = 1, |
b7884eb4 | 259 | .has_force_wake = 1, |
c76b615c JB |
260 | }; |
261 | ||
262 | static const struct intel_device_info intel_ivybridge_m_info = { | |
263 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, | |
264 | .need_gfx_hws = 1, .has_hotplug = 1, | |
265 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ | |
266 | .has_bsd_ring = 1, | |
267 | .has_blt_ring = 1, | |
3d29b842 | 268 | .has_llc = 1, |
b7884eb4 | 269 | .has_force_wake = 1, |
c76b615c JB |
270 | }; |
271 | ||
70a3eb7a JB |
272 | static const struct intel_device_info intel_valleyview_m_info = { |
273 | .gen = 7, .is_mobile = 1, | |
274 | .need_gfx_hws = 1, .has_hotplug = 1, | |
275 | .has_fbc = 0, | |
276 | .has_bsd_ring = 1, | |
277 | .has_blt_ring = 1, | |
278 | .is_valleyview = 1, | |
279 | }; | |
280 | ||
281 | static const struct intel_device_info intel_valleyview_d_info = { | |
282 | .gen = 7, | |
283 | .need_gfx_hws = 1, .has_hotplug = 1, | |
284 | .has_fbc = 0, | |
285 | .has_bsd_ring = 1, | |
286 | .has_blt_ring = 1, | |
287 | .is_valleyview = 1, | |
288 | }; | |
289 | ||
4cae9ae0 ED |
290 | static const struct intel_device_info intel_haswell_d_info = { |
291 | .is_haswell = 1, .gen = 7, | |
292 | .need_gfx_hws = 1, .has_hotplug = 1, | |
293 | .has_bsd_ring = 1, | |
294 | .has_blt_ring = 1, | |
295 | .has_llc = 1, | |
b7884eb4 | 296 | .has_force_wake = 1, |
4cae9ae0 ED |
297 | }; |
298 | ||
299 | static const struct intel_device_info intel_haswell_m_info = { | |
300 | .is_haswell = 1, .gen = 7, .is_mobile = 1, | |
301 | .need_gfx_hws = 1, .has_hotplug = 1, | |
302 | .has_bsd_ring = 1, | |
303 | .has_blt_ring = 1, | |
304 | .has_llc = 1, | |
b7884eb4 | 305 | .has_force_wake = 1, |
c76b615c JB |
306 | }; |
307 | ||
6103da0d CW |
308 | static const struct pci_device_id pciidlist[] = { /* aka */ |
309 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
310 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
311 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 312 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
313 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
314 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
315 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
316 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
317 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
318 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
319 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
320 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
321 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
322 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
323 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
324 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
325 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
326 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
327 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
328 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
329 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
330 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
331 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
332 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
333 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
334 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 335 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
336 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
337 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
338 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
339 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 340 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
341 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
342 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 343 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 344 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 345 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 346 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
347 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
348 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
349 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
350 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
351 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
cc22a938 | 352 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
c14f5286 ED |
353 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
354 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ | |
da612d88 | 355 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ |
c14f5286 ED |
356 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
357 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ | |
da612d88 | 358 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ |
c14f5286 ED |
359 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
360 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ | |
da612d88 PZ |
361 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
362 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ | |
363 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ | |
364 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ | |
365 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ | |
366 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ | |
367 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ | |
368 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ | |
369 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ | |
370 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ | |
371 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ | |
372 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ | |
373 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ | |
374 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ | |
375 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ | |
376 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ | |
377 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ | |
378 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ | |
379 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ | |
380 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */ | |
381 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ | |
382 | INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */ | |
383 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */ | |
384 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ | |
385 | INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */ | |
386 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */ | |
387 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ | |
388 | INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */ | |
ff049b6c JB |
389 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
390 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), | |
391 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), | |
49ae35f2 | 392 | {0, 0, 0} |
1da177e4 LT |
393 | }; |
394 | ||
79e53945 JB |
395 | #if defined(CONFIG_DRM_I915_KMS) |
396 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
397 | #endif | |
398 | ||
0206e353 | 399 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
400 | { |
401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
402 | struct pci_dev *pch; | |
403 | ||
404 | /* | |
405 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
406 | * make graphics device passthrough work easy for VMM, that only | |
407 | * need to expose ISA bridge to let driver know the real hardware | |
408 | * underneath. This is a requirement from virtualization team. | |
409 | */ | |
410 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
411 | if (pch) { | |
412 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
17a303ec | 413 | unsigned short id; |
3bad0781 | 414 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 415 | dev_priv->pch_id = id; |
3bad0781 | 416 | |
90711d50 JB |
417 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
418 | dev_priv->pch_type = PCH_IBX; | |
ee7b9f93 | 419 | dev_priv->num_pch_pll = 2; |
90711d50 | 420 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
7fcb83cd | 421 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 422 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 | 423 | dev_priv->pch_type = PCH_CPT; |
ee7b9f93 | 424 | dev_priv->num_pch_pll = 2; |
3bad0781 | 425 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
7fcb83cd | 426 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
427 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
428 | /* PantherPoint is CPT compatible */ | |
429 | dev_priv->pch_type = PCH_CPT; | |
ee7b9f93 | 430 | dev_priv->num_pch_pll = 2; |
c792513b | 431 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
7fcb83cd | 432 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
433 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
434 | dev_priv->pch_type = PCH_LPT; | |
ee7b9f93 | 435 | dev_priv->num_pch_pll = 0; |
eb877ebf | 436 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
7fcb83cd | 437 | WARN_ON(!IS_HASWELL(dev)); |
ae6935dd WSC |
438 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
439 | dev_priv->pch_type = PCH_LPT; | |
440 | dev_priv->num_pch_pll = 0; | |
441 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
442 | WARN_ON(!IS_HASWELL(dev)); | |
3bad0781 | 443 | } |
ee7b9f93 | 444 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
3bad0781 ZW |
445 | } |
446 | pci_dev_put(pch); | |
447 | } | |
448 | } | |
449 | ||
2911a35b BW |
450 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
451 | { | |
452 | if (INTEL_INFO(dev)->gen < 6) | |
453 | return 0; | |
454 | ||
455 | if (i915_semaphores >= 0) | |
456 | return i915_semaphores; | |
457 | ||
59de3295 | 458 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 459 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
460 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
461 | return false; | |
462 | #endif | |
2911a35b BW |
463 | |
464 | return 1; | |
465 | } | |
466 | ||
84b79f8d | 467 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 468 | { |
61caf87c RW |
469 | struct drm_i915_private *dev_priv = dev->dev_private; |
470 | ||
5bcf719b DA |
471 | drm_kms_helper_poll_disable(dev); |
472 | ||
ba8bbcf6 | 473 | pci_save_state(dev->pdev); |
ba8bbcf6 | 474 | |
5669fcac | 475 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 476 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
477 | int error = i915_gem_idle(dev); |
478 | if (error) { | |
226485e9 | 479 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
480 | "GEM idle failed, resume might fail\n"); |
481 | return error; | |
482 | } | |
a261b246 | 483 | |
1a01ab3b JB |
484 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
485 | ||
a261b246 DV |
486 | intel_modeset_disable(dev); |
487 | ||
226485e9 | 488 | drm_irq_uninstall(dev); |
5669fcac JB |
489 | } |
490 | ||
9e06dd39 JB |
491 | i915_save_state(dev); |
492 | ||
44834a67 | 493 | intel_opregion_fini(dev); |
8ee1c3db | 494 | |
84b79f8d RW |
495 | /* Modeset on resume, not lid events */ |
496 | dev_priv->modeset_on_lid = 0; | |
61caf87c | 497 | |
3fa016a0 DA |
498 | console_lock(); |
499 | intel_fbdev_set_suspend(dev, 1); | |
500 | console_unlock(); | |
501 | ||
61caf87c | 502 | return 0; |
84b79f8d RW |
503 | } |
504 | ||
6a9ee8af | 505 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
506 | { |
507 | int error; | |
508 | ||
509 | if (!dev || !dev->dev_private) { | |
510 | DRM_ERROR("dev: %p\n", dev); | |
511 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
512 | return -ENODEV; | |
513 | } | |
514 | ||
515 | if (state.event == PM_EVENT_PRETHAW) | |
516 | return 0; | |
517 | ||
5bcf719b DA |
518 | |
519 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
520 | return 0; | |
6eecba33 | 521 | |
84b79f8d RW |
522 | error = i915_drm_freeze(dev); |
523 | if (error) | |
524 | return error; | |
525 | ||
b932ccb5 DA |
526 | if (state.event == PM_EVENT_SUSPEND) { |
527 | /* Shut down the device */ | |
528 | pci_disable_device(dev->pdev); | |
529 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
530 | } | |
ba8bbcf6 JB |
531 | |
532 | return 0; | |
533 | } | |
534 | ||
073f34d9 JB |
535 | void intel_console_resume(struct work_struct *work) |
536 | { | |
537 | struct drm_i915_private *dev_priv = | |
538 | container_of(work, struct drm_i915_private, | |
539 | console_resume_work); | |
540 | struct drm_device *dev = dev_priv->dev; | |
541 | ||
542 | console_lock(); | |
543 | intel_fbdev_set_suspend(dev, 0); | |
544 | console_unlock(); | |
545 | } | |
546 | ||
1abd02e2 | 547 | static int __i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 548 | { |
5669fcac | 549 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 550 | int error = 0; |
8ee1c3db | 551 | |
61caf87c | 552 | i915_restore_state(dev); |
44834a67 | 553 | intel_opregion_setup(dev); |
61caf87c | 554 | |
5669fcac JB |
555 | /* KMS EnterVT equivalent */ |
556 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
40579abe | 557 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
1833b134 CW |
558 | ironlake_init_pch_refclk(dev); |
559 | ||
5669fcac JB |
560 | mutex_lock(&dev->struct_mutex); |
561 | dev_priv->mm.suspended = 0; | |
562 | ||
f691e2f4 | 563 | error = i915_gem_init_hw(dev); |
5669fcac | 564 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 565 | |
1833b134 | 566 | intel_modeset_init_hw(dev); |
45e2b5f6 | 567 | intel_modeset_setup_hw_state(dev, false); |
226485e9 | 568 | drm_irq_install(dev); |
d5bb081b | 569 | } |
1daed3fb | 570 | |
44834a67 CW |
571 | intel_opregion_init(dev); |
572 | ||
c9354c85 | 573 | dev_priv->modeset_on_lid = 0; |
06891e27 | 574 | |
073f34d9 JB |
575 | /* |
576 | * The console lock can be pretty contented on resume due | |
577 | * to all the printk activity. Try to keep it out of the hot | |
578 | * path of resume if possible. | |
579 | */ | |
580 | if (console_trylock()) { | |
581 | intel_fbdev_set_suspend(dev, 0); | |
582 | console_unlock(); | |
583 | } else { | |
584 | schedule_work(&dev_priv->console_resume_work); | |
585 | } | |
586 | ||
84b79f8d RW |
587 | return error; |
588 | } | |
589 | ||
1abd02e2 JB |
590 | static int i915_drm_thaw(struct drm_device *dev) |
591 | { | |
592 | int error = 0; | |
593 | ||
594 | intel_gt_reset(dev); | |
595 | ||
596 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
597 | mutex_lock(&dev->struct_mutex); | |
598 | i915_gem_restore_gtt_mappings(dev); | |
599 | mutex_unlock(&dev->struct_mutex); | |
600 | } | |
601 | ||
602 | __i915_drm_thaw(dev); | |
603 | ||
84b79f8d RW |
604 | return error; |
605 | } | |
606 | ||
6a9ee8af | 607 | int i915_resume(struct drm_device *dev) |
84b79f8d | 608 | { |
1abd02e2 | 609 | struct drm_i915_private *dev_priv = dev->dev_private; |
6eecba33 CW |
610 | int ret; |
611 | ||
5bcf719b DA |
612 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
613 | return 0; | |
614 | ||
84b79f8d RW |
615 | if (pci_enable_device(dev->pdev)) |
616 | return -EIO; | |
617 | ||
618 | pci_set_master(dev->pdev); | |
619 | ||
1abd02e2 JB |
620 | intel_gt_reset(dev); |
621 | ||
622 | /* | |
623 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
624 | * earlier) need this since the BIOS might clear all our scratch PTEs. | |
625 | */ | |
626 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
627 | !dev_priv->opregion.header) { | |
628 | mutex_lock(&dev->struct_mutex); | |
629 | i915_gem_restore_gtt_mappings(dev); | |
630 | mutex_unlock(&dev->struct_mutex); | |
631 | } | |
632 | ||
633 | ret = __i915_drm_thaw(dev); | |
6eecba33 CW |
634 | if (ret) |
635 | return ret; | |
636 | ||
637 | drm_kms_helper_poll_enable(dev); | |
638 | return 0; | |
ba8bbcf6 JB |
639 | } |
640 | ||
d4b8bb2a | 641 | static int i8xx_do_reset(struct drm_device *dev) |
dc96e9b8 CW |
642 | { |
643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
644 | ||
645 | if (IS_I85X(dev)) | |
646 | return -ENODEV; | |
647 | ||
648 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
649 | POSTING_READ(D_STATE); | |
650 | ||
651 | if (IS_I830(dev) || IS_845G(dev)) { | |
652 | I915_WRITE(DEBUG_RESET_I830, | |
653 | DEBUG_RESET_DISPLAY | | |
654 | DEBUG_RESET_RENDER | | |
655 | DEBUG_RESET_FULL); | |
656 | POSTING_READ(DEBUG_RESET_I830); | |
657 | msleep(1); | |
658 | ||
659 | I915_WRITE(DEBUG_RESET_I830, 0); | |
660 | POSTING_READ(DEBUG_RESET_I830); | |
661 | } | |
662 | ||
663 | msleep(1); | |
664 | ||
665 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
666 | POSTING_READ(D_STATE); | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
f49f0586 KG |
671 | static int i965_reset_complete(struct drm_device *dev) |
672 | { | |
673 | u8 gdrst; | |
eeccdcac | 674 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
5fe9fe8c | 675 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
f49f0586 KG |
676 | } |
677 | ||
d4b8bb2a | 678 | static int i965_do_reset(struct drm_device *dev) |
0573ed4a | 679 | { |
5ccce180 | 680 | int ret; |
0573ed4a KG |
681 | u8 gdrst; |
682 | ||
ae681d96 CW |
683 | /* |
684 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
685 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
686 | * triggers the reset; when done, the hardware will clear it. | |
687 | */ | |
0573ed4a | 688 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
d4b8bb2a | 689 | pci_write_config_byte(dev->pdev, I965_GDRST, |
5ccce180 DV |
690 | gdrst | GRDOM_RENDER | |
691 | GRDOM_RESET_ENABLE); | |
692 | ret = wait_for(i965_reset_complete(dev), 500); | |
693 | if (ret) | |
694 | return ret; | |
695 | ||
696 | /* We can't reset render&media without also resetting display ... */ | |
697 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | |
698 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
699 | gdrst | GRDOM_MEDIA | | |
700 | GRDOM_RESET_ENABLE); | |
0573ed4a KG |
701 | |
702 | return wait_for(i965_reset_complete(dev), 500); | |
703 | } | |
704 | ||
d4b8bb2a | 705 | static int ironlake_do_reset(struct drm_device *dev) |
0573ed4a KG |
706 | { |
707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5ccce180 DV |
708 | u32 gdrst; |
709 | int ret; | |
710 | ||
711 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
712 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
713 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
714 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
715 | if (ret) | |
716 | return ret; | |
717 | ||
718 | /* We can't reset render&media without also resetting display ... */ | |
719 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
d4b8bb2a | 720 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
5ccce180 | 721 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
0573ed4a | 722 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
ba8bbcf6 JB |
723 | } |
724 | ||
d4b8bb2a | 725 | static int gen6_do_reset(struct drm_device *dev) |
cff458c2 EA |
726 | { |
727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b6e45f86 KP |
728 | int ret; |
729 | unsigned long irqflags; | |
cff458c2 | 730 | |
286fed41 KP |
731 | /* Hold gt_lock across reset to prevent any register access |
732 | * with forcewake not set correctly | |
733 | */ | |
b6e45f86 | 734 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
286fed41 KP |
735 | |
736 | /* Reset the chip */ | |
737 | ||
738 | /* GEN6_GDRST is not in the gt power well, no need to check | |
739 | * for fifo space for the write or forcewake the chip for | |
740 | * the read | |
741 | */ | |
742 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
743 | ||
744 | /* Spin waiting for the device to ack the reset request */ | |
745 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
746 | ||
747 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | |
b6e45f86 | 748 | if (dev_priv->forcewake_count) |
990bbdad | 749 | dev_priv->gt.force_wake_get(dev_priv); |
286fed41 | 750 | else |
990bbdad | 751 | dev_priv->gt.force_wake_put(dev_priv); |
286fed41 KP |
752 | |
753 | /* Restore fifo count */ | |
754 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
755 | ||
b6e45f86 KP |
756 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
757 | return ret; | |
cff458c2 EA |
758 | } |
759 | ||
8e96d9c4 | 760 | int intel_gpu_reset(struct drm_device *dev) |
350d2706 | 761 | { |
2b9dc9a2 | 762 | struct drm_i915_private *dev_priv = dev->dev_private; |
350d2706 DV |
763 | int ret = -ENODEV; |
764 | ||
765 | switch (INTEL_INFO(dev)->gen) { | |
766 | case 7: | |
767 | case 6: | |
d4b8bb2a | 768 | ret = gen6_do_reset(dev); |
350d2706 DV |
769 | break; |
770 | case 5: | |
d4b8bb2a | 771 | ret = ironlake_do_reset(dev); |
350d2706 DV |
772 | break; |
773 | case 4: | |
d4b8bb2a | 774 | ret = i965_do_reset(dev); |
350d2706 DV |
775 | break; |
776 | case 2: | |
d4b8bb2a | 777 | ret = i8xx_do_reset(dev); |
350d2706 DV |
778 | break; |
779 | } | |
780 | ||
2b9dc9a2 DV |
781 | /* Also reset the gpu hangman. */ |
782 | if (dev_priv->stop_rings) { | |
783 | DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); | |
784 | dev_priv->stop_rings = 0; | |
785 | if (ret == -ENODEV) { | |
786 | DRM_ERROR("Reset not implemented, but ignoring " | |
787 | "error for simulated gpu hangs\n"); | |
788 | ret = 0; | |
789 | } | |
790 | } | |
791 | ||
350d2706 DV |
792 | return ret; |
793 | } | |
794 | ||
11ed50ec | 795 | /** |
f3953dcb | 796 | * i915_reset - reset chip after a hang |
11ed50ec | 797 | * @dev: drm device to reset |
11ed50ec BG |
798 | * |
799 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
800 | * reset or otherwise an error code. | |
801 | * | |
802 | * Procedure is fairly simple: | |
803 | * - reset the chip using the reset reg | |
804 | * - re-init context state | |
805 | * - re-init hardware status page | |
806 | * - re-init ring buffer | |
807 | * - re-init interrupt state | |
808 | * - re-init display | |
809 | */ | |
d4b8bb2a | 810 | int i915_reset(struct drm_device *dev) |
11ed50ec BG |
811 | { |
812 | drm_i915_private_t *dev_priv = dev->dev_private; | |
0573ed4a | 813 | int ret; |
11ed50ec | 814 | |
d78cb50b CW |
815 | if (!i915_try_reset) |
816 | return 0; | |
817 | ||
d54a02c0 | 818 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 819 | |
069efc1d | 820 | i915_gem_reset(dev); |
77f01230 | 821 | |
f803aa55 | 822 | ret = -ENODEV; |
350d2706 | 823 | if (get_seconds() - dev_priv->last_gpu_reset < 5) |
ae681d96 | 824 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
350d2706 | 825 | else |
d4b8bb2a | 826 | ret = intel_gpu_reset(dev); |
350d2706 | 827 | |
ae681d96 | 828 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 829 | if (ret) { |
f803aa55 | 830 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 831 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 832 | return ret; |
11ed50ec BG |
833 | } |
834 | ||
835 | /* Ok, now get things going again... */ | |
836 | ||
837 | /* | |
838 | * Everything depends on having the GTT running, so we need to start | |
839 | * there. Fortunately we don't need to do this unless we reset the | |
840 | * chip at a PCI level. | |
841 | * | |
842 | * Next we need to restore the context, but we don't use those | |
843 | * yet either... | |
844 | * | |
845 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
846 | * was running at the time of the reset (i.e. we weren't VT | |
847 | * switched away). | |
848 | */ | |
849 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 850 | !dev_priv->mm.suspended) { |
b4519513 CW |
851 | struct intel_ring_buffer *ring; |
852 | int i; | |
853 | ||
11ed50ec | 854 | dev_priv->mm.suspended = 0; |
75a6898f | 855 | |
f691e2f4 DV |
856 | i915_gem_init_swizzling(dev); |
857 | ||
b4519513 CW |
858 | for_each_ring(ring, dev_priv, i) |
859 | ring->init(ring); | |
75a6898f | 860 | |
254f965c | 861 | i915_gem_context_init(dev); |
e21af88d DV |
862 | i915_gem_init_ppgtt(dev); |
863 | ||
8e88a2bd DV |
864 | /* |
865 | * It would make sense to re-init all the other hw state, at | |
866 | * least the rps/rc6/emon init done within modeset_init_hw. For | |
867 | * some unknown reason, this blows up my ilk, so don't. | |
868 | */ | |
f817586c | 869 | |
8e88a2bd | 870 | mutex_unlock(&dev->struct_mutex); |
f817586c | 871 | |
11ed50ec BG |
872 | drm_irq_uninstall(dev); |
873 | drm_irq_install(dev); | |
bcbc324a DV |
874 | } else { |
875 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
876 | } |
877 | ||
11ed50ec BG |
878 | return 0; |
879 | } | |
880 | ||
112b715e KH |
881 | static int __devinit |
882 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
883 | { | |
01a06850 DV |
884 | struct intel_device_info *intel_info = |
885 | (struct intel_device_info *) ent->driver_data; | |
886 | ||
70b12bb4 | 887 | if (intel_info->is_valleyview) |
0a3af268 RV |
888 | if(!i915_preliminary_hw_support) { |
889 | DRM_ERROR("Preliminary hardware support disabled\n"); | |
890 | return -ENODEV; | |
891 | } | |
892 | ||
5fe49d86 CW |
893 | /* Only bind to function 0 of the device. Early generations |
894 | * used function 1 as a placeholder for multi-head. This causes | |
895 | * us confusion instead, especially on the systems where both | |
896 | * functions have the same PCI-ID! | |
897 | */ | |
898 | if (PCI_FUNC(pdev->devfn)) | |
899 | return -ENODEV; | |
900 | ||
01a06850 DV |
901 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
902 | * implementation for gen3 (and only gen3) that used legacy drm maps | |
903 | * (gasp!) to share buffers between X and the client. Hence we need to | |
904 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ | |
905 | if (intel_info->gen != 3) { | |
906 | driver.driver_features &= | |
907 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); | |
908 | } else if (!intel_agp_enabled) { | |
909 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
910 | return -ENODEV; | |
911 | } | |
912 | ||
dcdb1674 | 913 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
914 | } |
915 | ||
916 | static void | |
917 | i915_pci_remove(struct pci_dev *pdev) | |
918 | { | |
919 | struct drm_device *dev = pci_get_drvdata(pdev); | |
920 | ||
921 | drm_put_dev(dev); | |
922 | } | |
923 | ||
84b79f8d | 924 | static int i915_pm_suspend(struct device *dev) |
112b715e | 925 | { |
84b79f8d RW |
926 | struct pci_dev *pdev = to_pci_dev(dev); |
927 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
928 | int error; | |
112b715e | 929 | |
84b79f8d RW |
930 | if (!drm_dev || !drm_dev->dev_private) { |
931 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
932 | return -ENODEV; | |
933 | } | |
112b715e | 934 | |
5bcf719b DA |
935 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
936 | return 0; | |
937 | ||
84b79f8d RW |
938 | error = i915_drm_freeze(drm_dev); |
939 | if (error) | |
940 | return error; | |
112b715e | 941 | |
84b79f8d RW |
942 | pci_disable_device(pdev); |
943 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 944 | |
84b79f8d | 945 | return 0; |
cbda12d7 ZW |
946 | } |
947 | ||
84b79f8d | 948 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 949 | { |
84b79f8d RW |
950 | struct pci_dev *pdev = to_pci_dev(dev); |
951 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
952 | ||
953 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
954 | } |
955 | ||
84b79f8d | 956 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 957 | { |
84b79f8d RW |
958 | struct pci_dev *pdev = to_pci_dev(dev); |
959 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
960 | ||
961 | if (!drm_dev || !drm_dev->dev_private) { | |
962 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
963 | return -ENODEV; | |
964 | } | |
965 | ||
966 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
967 | } |
968 | ||
84b79f8d | 969 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 970 | { |
84b79f8d RW |
971 | struct pci_dev *pdev = to_pci_dev(dev); |
972 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
973 | ||
974 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
975 | } |
976 | ||
84b79f8d | 977 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 978 | { |
84b79f8d RW |
979 | struct pci_dev *pdev = to_pci_dev(dev); |
980 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 981 | |
61caf87c | 982 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
983 | } |
984 | ||
b4b78d12 | 985 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
986 | .suspend = i915_pm_suspend, |
987 | .resume = i915_pm_resume, | |
988 | .freeze = i915_pm_freeze, | |
989 | .thaw = i915_pm_thaw, | |
990 | .poweroff = i915_pm_poweroff, | |
991 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
992 | }; |
993 | ||
78b68556 | 994 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 995 | .fault = i915_gem_fault, |
ab00b3e5 JB |
996 | .open = drm_gem_vm_open, |
997 | .close = drm_gem_vm_close, | |
de151cf6 JB |
998 | }; |
999 | ||
e08e96de AV |
1000 | static const struct file_operations i915_driver_fops = { |
1001 | .owner = THIS_MODULE, | |
1002 | .open = drm_open, | |
1003 | .release = drm_release, | |
1004 | .unlocked_ioctl = drm_ioctl, | |
1005 | .mmap = drm_gem_mmap, | |
1006 | .poll = drm_poll, | |
1007 | .fasync = drm_fasync, | |
1008 | .read = drm_read, | |
1009 | #ifdef CONFIG_COMPAT | |
1010 | .compat_ioctl = i915_compat_ioctl, | |
1011 | #endif | |
1012 | .llseek = noop_llseek, | |
1013 | }; | |
1014 | ||
1da177e4 | 1015 | static struct drm_driver driver = { |
0c54781b MW |
1016 | /* Don't use MTRRs here; the Xserver or userspace app should |
1017 | * deal with them for Intel hardware. | |
792d2b9a | 1018 | */ |
673a394b EA |
1019 | .driver_features = |
1020 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
1286ff73 | 1021 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME, |
22eae947 | 1022 | .load = i915_driver_load, |
ba8bbcf6 | 1023 | .unload = i915_driver_unload, |
673a394b | 1024 | .open = i915_driver_open, |
22eae947 DA |
1025 | .lastclose = i915_driver_lastclose, |
1026 | .preclose = i915_driver_preclose, | |
673a394b | 1027 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1028 | |
1029 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1030 | .suspend = i915_suspend, | |
1031 | .resume = i915_resume, | |
1032 | ||
cda17380 | 1033 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
1034 | .master_create = i915_master_create, |
1035 | .master_destroy = i915_master_destroy, | |
955b12de | 1036 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1037 | .debugfs_init = i915_debugfs_init, |
1038 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1039 | #endif |
673a394b EA |
1040 | .gem_init_object = i915_gem_init_object, |
1041 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 1042 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1043 | |
1044 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1045 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1046 | .gem_prime_export = i915_gem_prime_export, | |
1047 | .gem_prime_import = i915_gem_prime_import, | |
1048 | ||
ff72145b DA |
1049 | .dumb_create = i915_gem_dumb_create, |
1050 | .dumb_map_offset = i915_gem_mmap_gtt, | |
1051 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 | 1052 | .ioctls = i915_ioctls, |
e08e96de | 1053 | .fops = &i915_driver_fops, |
22eae947 DA |
1054 | .name = DRIVER_NAME, |
1055 | .desc = DRIVER_DESC, | |
1056 | .date = DRIVER_DATE, | |
1057 | .major = DRIVER_MAJOR, | |
1058 | .minor = DRIVER_MINOR, | |
1059 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1060 | }; |
1061 | ||
8410ea3b DA |
1062 | static struct pci_driver i915_pci_driver = { |
1063 | .name = DRIVER_NAME, | |
1064 | .id_table = pciidlist, | |
1065 | .probe = i915_pci_probe, | |
1066 | .remove = i915_pci_remove, | |
1067 | .driver.pm = &i915_pm_ops, | |
1068 | }; | |
1069 | ||
1da177e4 LT |
1070 | static int __init i915_init(void) |
1071 | { | |
1072 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1073 | |
1074 | /* | |
1075 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1076 | * explicitly disabled with the module pararmeter. | |
1077 | * | |
1078 | * Otherwise, just follow the parameter (defaulting to off). | |
1079 | * | |
1080 | * Allow optional vga_text_mode_force boot option to override | |
1081 | * the default behavior. | |
1082 | */ | |
1083 | #if defined(CONFIG_DRM_I915_KMS) | |
1084 | if (i915_modeset != 0) | |
1085 | driver.driver_features |= DRIVER_MODESET; | |
1086 | #endif | |
1087 | if (i915_modeset == 1) | |
1088 | driver.driver_features |= DRIVER_MODESET; | |
1089 | ||
1090 | #ifdef CONFIG_VGA_CONSOLE | |
1091 | if (vgacon_text_force() && i915_modeset == -1) | |
1092 | driver.driver_features &= ~DRIVER_MODESET; | |
1093 | #endif | |
1094 | ||
3885c6bb CW |
1095 | if (!(driver.driver_features & DRIVER_MODESET)) |
1096 | driver.get_vblank_timestamp = NULL; | |
1097 | ||
8410ea3b | 1098 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1099 | } |
1100 | ||
1101 | static void __exit i915_exit(void) | |
1102 | { | |
8410ea3b | 1103 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1104 | } |
1105 | ||
1106 | module_init(i915_init); | |
1107 | module_exit(i915_exit); | |
1108 | ||
b5e89ed5 DA |
1109 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1110 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1111 | MODULE_LICENSE("GPL and additional rights"); |
f7000883 | 1112 | |
b7d84096 JB |
1113 | /* We give fast paths for the really cool registers */ |
1114 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
b7884eb4 DV |
1115 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
1116 | ((reg) < 0x40000) && \ | |
1117 | ((reg) != FORCEWAKE)) | |
b7d84096 | 1118 | |
f7dff0c9 JB |
1119 | static bool IS_DISPLAYREG(u32 reg) |
1120 | { | |
1121 | /* | |
1122 | * This should make it easier to transition modules over to the | |
1123 | * new register block scheme, since we can do it incrementally. | |
1124 | */ | |
a7e806de | 1125 | if (reg >= VLV_DISPLAY_BASE) |
f7dff0c9 JB |
1126 | return false; |
1127 | ||
1128 | if (reg >= RENDER_RING_BASE && | |
1129 | reg < RENDER_RING_BASE + 0xff) | |
1130 | return false; | |
1131 | if (reg >= GEN6_BSD_RING_BASE && | |
1132 | reg < GEN6_BSD_RING_BASE + 0xff) | |
1133 | return false; | |
1134 | if (reg >= BLT_RING_BASE && | |
1135 | reg < BLT_RING_BASE + 0xff) | |
1136 | return false; | |
1137 | ||
1138 | if (reg == PGTBL_ER) | |
1139 | return false; | |
1140 | ||
1141 | if (reg >= IPEIR_I965 && | |
1142 | reg < HWSTAM) | |
1143 | return false; | |
1144 | ||
1145 | if (reg == MI_MODE) | |
1146 | return false; | |
1147 | ||
1148 | if (reg == GFX_MODE_GEN7) | |
1149 | return false; | |
1150 | ||
1151 | if (reg == RENDER_HWS_PGA_GEN7 || | |
1152 | reg == BSD_HWS_PGA_GEN7 || | |
1153 | reg == BLT_HWS_PGA_GEN7) | |
1154 | return false; | |
1155 | ||
1156 | if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || | |
1157 | reg == GEN6_BSD_RNCID) | |
1158 | return false; | |
1159 | ||
1160 | if (reg == GEN6_BLITTER_ECOSKPD) | |
1161 | return false; | |
1162 | ||
1163 | if (reg >= 0x4000c && | |
1164 | reg <= 0x4002c) | |
1165 | return false; | |
1166 | ||
1167 | if (reg >= 0x4f000 && | |
1168 | reg <= 0x4f08f) | |
1169 | return false; | |
1170 | ||
1171 | if (reg >= 0x4f100 && | |
1172 | reg <= 0x4f11f) | |
1173 | return false; | |
1174 | ||
1175 | if (reg >= VLV_MASTER_IER && | |
1176 | reg <= GEN6_PMIER) | |
1177 | return false; | |
1178 | ||
1179 | if (reg >= FENCE_REG_SANDYBRIDGE_0 && | |
1180 | reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) | |
1181 | return false; | |
1182 | ||
1183 | if (reg >= VLV_IIR_RW && | |
1184 | reg <= VLV_ISR) | |
1185 | return false; | |
1186 | ||
1187 | if (reg == FORCEWAKE_VLV || | |
1188 | reg == FORCEWAKE_ACK_VLV) | |
1189 | return false; | |
1190 | ||
1191 | if (reg == GEN6_GDRST) | |
1192 | return false; | |
1193 | ||
8ab43976 | 1194 | switch (reg) { |
310c53a8 JB |
1195 | case _3D_CHICKEN3: |
1196 | case IVB_CHICKEN3: | |
1197 | case GEN7_COMMON_SLICE_CHICKEN1: | |
1198 | case GEN7_L3CNTLREG1: | |
1199 | case GEN7_L3_CHICKEN_MODE_REGISTER: | |
8ab43976 | 1200 | case GEN7_ROW_CHICKEN2: |
310c53a8 JB |
1201 | case GEN7_L3SQCREG4: |
1202 | case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: | |
12f3382b | 1203 | case GEN7_HALF_SLICE_CHICKEN1: |
310c53a8 JB |
1204 | case GEN6_MBCTL: |
1205 | case GEN6_UCGCTL2: | |
8ab43976 JB |
1206 | return false; |
1207 | default: | |
1208 | break; | |
1209 | } | |
1210 | ||
f7dff0c9 JB |
1211 | return true; |
1212 | } | |
1213 | ||
a8b1397d DV |
1214 | static void |
1215 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
1216 | { | |
1217 | /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the | |
1218 | * chip from rc6 before touching it for real. MI_MODE is masked, hence | |
1219 | * harmless to write 0 into. */ | |
1220 | I915_WRITE_NOTRACE(MI_MODE, 0); | |
1221 | } | |
1222 | ||
f7000883 AK |
1223 | #define __i915_read(x, y) \ |
1224 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
1225 | u##x val = 0; \ | |
a8b1397d DV |
1226 | if (IS_GEN5(dev_priv->dev)) \ |
1227 | ilk_dummy_write(dev_priv); \ | |
f7000883 | 1228 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
c937504e KP |
1229 | unsigned long irqflags; \ |
1230 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | |
1231 | if (dev_priv->forcewake_count == 0) \ | |
990bbdad | 1232 | dev_priv->gt.force_wake_get(dev_priv); \ |
f7000883 | 1233 | val = read##y(dev_priv->regs + reg); \ |
c937504e | 1234 | if (dev_priv->forcewake_count == 0) \ |
990bbdad | 1235 | dev_priv->gt.force_wake_put(dev_priv); \ |
c937504e | 1236 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
f7dff0c9 JB |
1237 | } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
1238 | val = read##y(dev_priv->regs + reg + 0x180000); \ | |
f7000883 AK |
1239 | } else { \ |
1240 | val = read##y(dev_priv->regs + reg); \ | |
1241 | } \ | |
1242 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | |
1243 | return val; \ | |
1244 | } | |
1245 | ||
1246 | __i915_read(8, b) | |
1247 | __i915_read(16, w) | |
1248 | __i915_read(32, l) | |
1249 | __i915_read(64, q) | |
1250 | #undef __i915_read | |
1251 | ||
1252 | #define __i915_write(x, y) \ | |
1253 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
67a3744f | 1254 | u32 __fifo_ret = 0; \ |
f7000883 AK |
1255 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1256 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
67a3744f | 1257 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
f7000883 | 1258 | } \ |
a8b1397d DV |
1259 | if (IS_GEN5(dev_priv->dev)) \ |
1260 | ilk_dummy_write(dev_priv); \ | |
c54e5904 PZ |
1261 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
1262 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \ | |
1263 | I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ | |
1264 | } \ | |
f7dff0c9 JB |
1265 | if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
1266 | write##y(val, dev_priv->regs + reg + 0x180000); \ | |
1267 | } else { \ | |
1268 | write##y(val, dev_priv->regs + reg); \ | |
1269 | } \ | |
67a3744f BW |
1270 | if (unlikely(__fifo_ret)) { \ |
1271 | gen6_gt_check_fifodbg(dev_priv); \ | |
1272 | } \ | |
b4c145c1 BW |
1273 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
1274 | DRM_ERROR("Unclaimed write to %x\n", reg); \ | |
1275 | writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \ | |
1276 | } \ | |
f7000883 AK |
1277 | } |
1278 | __i915_write(8, b) | |
1279 | __i915_write(16, w) | |
1280 | __i915_write(32, l) | |
1281 | __i915_write(64, q) | |
1282 | #undef __i915_write | |
c0c7babc BW |
1283 | |
1284 | static const struct register_whitelist { | |
1285 | uint64_t offset; | |
1286 | uint32_t size; | |
1287 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ | |
1288 | } whitelist[] = { | |
1289 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, | |
1290 | }; | |
1291 | ||
1292 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1293 | void *data, struct drm_file *file) | |
1294 | { | |
1295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1296 | struct drm_i915_reg_read *reg = data; | |
1297 | struct register_whitelist const *entry = whitelist; | |
1298 | int i; | |
1299 | ||
1300 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
1301 | if (entry->offset == reg->offset && | |
1302 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | |
1303 | break; | |
1304 | } | |
1305 | ||
1306 | if (i == ARRAY_SIZE(whitelist)) | |
1307 | return -EINVAL; | |
1308 | ||
1309 | switch (entry->size) { | |
1310 | case 8: | |
1311 | reg->val = I915_READ64(reg->offset); | |
1312 | break; | |
1313 | case 4: | |
1314 | reg->val = I915_READ(reg->offset); | |
1315 | break; | |
1316 | case 2: | |
1317 | reg->val = I915_READ16(reg->offset); | |
1318 | break; | |
1319 | case 1: | |
1320 | reg->val = I915_READ8(reg->offset); | |
1321 | break; | |
1322 | default: | |
1323 | WARN_ON(1); | |
1324 | return -EINVAL; | |
1325 | } | |
1326 | ||
1327 | return 0; | |
1328 | } |