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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
35 | ||
79e53945 | 36 | #include <linux/console.h> |
354ff967 | 37 | #include "drm_crtc_helper.h" |
79e53945 | 38 | |
d6073d77 | 39 | static int i915_modeset = -1; |
79e53945 JB |
40 | module_param_named(modeset, i915_modeset, int, 0400); |
41 | ||
42 | unsigned int i915_fbpercrtc = 0; | |
43 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); | |
1da177e4 | 44 | |
652c393a JB |
45 | unsigned int i915_powersave = 1; |
46 | module_param_named(powersave, i915_powersave, int, 0400); | |
47 | ||
33814341 JB |
48 | unsigned int i915_lvds_downclock = 0; |
49 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); | |
50 | ||
112b715e KH |
51 | static struct drm_driver driver; |
52 | ||
cfdf1fa2 | 53 | #define INTEL_VGA_DEVICE(id, info) { \ |
49ae35f2 KH |
54 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ |
55 | .class_mask = 0xffff00, \ | |
56 | .vendor = 0x8086, \ | |
57 | .device = id, \ | |
58 | .subvendor = PCI_ANY_ID, \ | |
59 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
60 | .driver_data = (unsigned long) info } |
61 | ||
62 | const static struct intel_device_info intel_i830_info = { | |
b295d1b6 | 63 | .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1, |
cfdf1fa2 KH |
64 | }; |
65 | ||
66 | const static struct intel_device_info intel_845g_info = { | |
67 | .is_i8xx = 1, | |
68 | }; | |
69 | ||
70 | const static struct intel_device_info intel_i85x_info = { | |
b295d1b6 | 71 | .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1, |
cfdf1fa2 KH |
72 | }; |
73 | ||
74 | const static struct intel_device_info intel_i865g_info = { | |
75 | .is_i8xx = 1, | |
76 | }; | |
77 | ||
78 | const static struct intel_device_info intel_i915g_info = { | |
b295d1b6 | 79 | .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1, |
cfdf1fa2 KH |
80 | }; |
81 | const static struct intel_device_info intel_i915gm_info = { | |
82 | .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1, | |
b295d1b6 | 83 | .cursor_needs_physical = 1, |
cfdf1fa2 KH |
84 | }; |
85 | const static struct intel_device_info intel_i945g_info = { | |
b295d1b6 | 86 | .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1, |
cfdf1fa2 KH |
87 | }; |
88 | const static struct intel_device_info intel_i945gm_info = { | |
89 | .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1, | |
b295d1b6 | 90 | .has_hotplug = 1, .cursor_needs_physical = 1, |
cfdf1fa2 KH |
91 | }; |
92 | ||
93 | const static struct intel_device_info intel_i965g_info = { | |
94 | .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1, | |
95 | }; | |
96 | ||
97 | const static struct intel_device_info intel_i965gm_info = { | |
98 | .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1, | |
99 | .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, | |
100 | .has_hotplug = 1, | |
101 | }; | |
102 | ||
103 | const static struct intel_device_info intel_g33_info = { | |
104 | .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1, | |
105 | .has_hotplug = 1, | |
106 | }; | |
107 | ||
108 | const static struct intel_device_info intel_g45_info = { | |
109 | .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1, | |
110 | .has_pipe_cxsr = 1, | |
111 | .has_hotplug = 1, | |
112 | }; | |
113 | ||
114 | const static struct intel_device_info intel_gm45_info = { | |
115 | .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1, | |
116 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, | |
117 | .has_pipe_cxsr = 1, | |
118 | .has_hotplug = 1, | |
119 | }; | |
120 | ||
121 | const static struct intel_device_info intel_pineview_info = { | |
122 | .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1, | |
8a6c77d6 | 123 | .need_gfx_hws = 1, |
cfdf1fa2 KH |
124 | .has_hotplug = 1, |
125 | }; | |
126 | ||
127 | const static struct intel_device_info intel_ironlake_d_info = { | |
128 | .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, | |
129 | .has_pipe_cxsr = 1, | |
130 | .has_hotplug = 1, | |
131 | }; | |
132 | ||
133 | const static struct intel_device_info intel_ironlake_m_info = { | |
134 | .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1, | |
135 | .need_gfx_hws = 1, .has_rc6 = 1, | |
136 | .has_hotplug = 1, | |
137 | }; | |
138 | ||
139 | const static struct pci_device_id pciidlist[] = { | |
140 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), | |
141 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), | |
142 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), | |
143 | INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info), | |
144 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), | |
145 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), | |
146 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), | |
147 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), | |
148 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), | |
149 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), | |
150 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), | |
151 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), | |
152 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), | |
153 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), | |
154 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), | |
155 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), | |
156 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), | |
157 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), | |
158 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), | |
159 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), | |
160 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), | |
161 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), | |
162 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), | |
163 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), | |
164 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), | |
165 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), | |
166 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), | |
167 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
168 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
169 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
49ae35f2 | 170 | {0, 0, 0} |
1da177e4 LT |
171 | }; |
172 | ||
79e53945 JB |
173 | #if defined(CONFIG_DRM_I915_KMS) |
174 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
175 | #endif | |
176 | ||
84b79f8d | 177 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 178 | { |
61caf87c RW |
179 | struct drm_i915_private *dev_priv = dev->dev_private; |
180 | ||
ba8bbcf6 | 181 | pci_save_state(dev->pdev); |
ba8bbcf6 | 182 | |
5669fcac | 183 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 184 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
185 | int error = i915_gem_idle(dev); |
186 | if (error) { | |
226485e9 | 187 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
188 | "GEM idle failed, resume might fail\n"); |
189 | return error; | |
190 | } | |
226485e9 | 191 | drm_irq_uninstall(dev); |
5669fcac JB |
192 | } |
193 | ||
9e06dd39 JB |
194 | i915_save_state(dev); |
195 | ||
3b1c1c11 | 196 | intel_opregion_free(dev, 1); |
8ee1c3db | 197 | |
84b79f8d RW |
198 | /* Modeset on resume, not lid events */ |
199 | dev_priv->modeset_on_lid = 0; | |
61caf87c RW |
200 | |
201 | return 0; | |
84b79f8d RW |
202 | } |
203 | ||
204 | static int i915_suspend(struct drm_device *dev, pm_message_t state) | |
205 | { | |
206 | int error; | |
207 | ||
208 | if (!dev || !dev->dev_private) { | |
209 | DRM_ERROR("dev: %p\n", dev); | |
210 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
211 | return -ENODEV; | |
212 | } | |
213 | ||
214 | if (state.event == PM_EVENT_PRETHAW) | |
215 | return 0; | |
216 | ||
217 | error = i915_drm_freeze(dev); | |
218 | if (error) | |
219 | return error; | |
220 | ||
b932ccb5 DA |
221 | if (state.event == PM_EVENT_SUSPEND) { |
222 | /* Shut down the device */ | |
223 | pci_disable_device(dev->pdev); | |
224 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
225 | } | |
ba8bbcf6 JB |
226 | |
227 | return 0; | |
228 | } | |
229 | ||
84b79f8d | 230 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 231 | { |
5669fcac | 232 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 233 | int error = 0; |
8ee1c3db | 234 | |
61caf87c RW |
235 | i915_restore_state(dev); |
236 | ||
237 | intel_opregion_init(dev, 1); | |
238 | ||
5669fcac JB |
239 | /* KMS EnterVT equivalent */ |
240 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
241 | mutex_lock(&dev->struct_mutex); | |
242 | dev_priv->mm.suspended = 0; | |
243 | ||
84b79f8d | 244 | error = i915_gem_init_ringbuffer(dev); |
5669fcac | 245 | mutex_unlock(&dev->struct_mutex); |
226485e9 JB |
246 | |
247 | drm_irq_install(dev); | |
84b79f8d | 248 | |
354ff967 ZY |
249 | /* Resume the modeset for every activated CRTC */ |
250 | drm_helper_resume_force_mode(dev); | |
251 | } | |
5669fcac | 252 | |
c9354c85 | 253 | dev_priv->modeset_on_lid = 0; |
06891e27 | 254 | |
84b79f8d RW |
255 | return error; |
256 | } | |
257 | ||
258 | static int i915_resume(struct drm_device *dev) | |
259 | { | |
260 | if (pci_enable_device(dev->pdev)) | |
261 | return -EIO; | |
262 | ||
263 | pci_set_master(dev->pdev); | |
264 | ||
84b79f8d | 265 | return i915_drm_thaw(dev); |
ba8bbcf6 JB |
266 | } |
267 | ||
11ed50ec BG |
268 | /** |
269 | * i965_reset - reset chip after a hang | |
270 | * @dev: drm device to reset | |
271 | * @flags: reset domains | |
272 | * | |
273 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
274 | * reset or otherwise an error code. | |
275 | * | |
276 | * Procedure is fairly simple: | |
277 | * - reset the chip using the reset reg | |
278 | * - re-init context state | |
279 | * - re-init hardware status page | |
280 | * - re-init ring buffer | |
281 | * - re-init interrupt state | |
282 | * - re-init display | |
283 | */ | |
284 | int i965_reset(struct drm_device *dev, u8 flags) | |
285 | { | |
286 | drm_i915_private_t *dev_priv = dev->dev_private; | |
287 | unsigned long timeout; | |
288 | u8 gdrst; | |
289 | /* | |
290 | * We really should only reset the display subsystem if we actually | |
291 | * need to | |
292 | */ | |
293 | bool need_display = true; | |
294 | ||
295 | mutex_lock(&dev->struct_mutex); | |
296 | ||
297 | /* | |
298 | * Clear request list | |
299 | */ | |
300 | i915_gem_retire_requests(dev); | |
301 | ||
302 | if (need_display) | |
303 | i915_save_display(dev); | |
304 | ||
305 | if (IS_I965G(dev) || IS_G4X(dev)) { | |
306 | /* | |
307 | * Set the domains we want to reset, then the reset bit (bit 0). | |
308 | * Clear the reset bit after a while and wait for hardware status | |
309 | * bit (bit 1) to be set | |
310 | */ | |
311 | pci_read_config_byte(dev->pdev, GDRST, &gdrst); | |
312 | pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0)); | |
313 | udelay(50); | |
314 | pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe); | |
315 | ||
316 | /* ...we don't want to loop forever though, 500ms should be plenty */ | |
317 | timeout = jiffies + msecs_to_jiffies(500); | |
318 | do { | |
319 | udelay(100); | |
320 | pci_read_config_byte(dev->pdev, GDRST, &gdrst); | |
321 | } while ((gdrst & 0x1) && time_after(timeout, jiffies)); | |
322 | ||
323 | if (gdrst & 0x1) { | |
324 | WARN(true, "i915: Failed to reset chip\n"); | |
325 | mutex_unlock(&dev->struct_mutex); | |
326 | return -EIO; | |
327 | } | |
328 | } else { | |
329 | DRM_ERROR("Error occurred. Don't know how to reset this chip.\n"); | |
330 | return -ENODEV; | |
331 | } | |
332 | ||
333 | /* Ok, now get things going again... */ | |
334 | ||
335 | /* | |
336 | * Everything depends on having the GTT running, so we need to start | |
337 | * there. Fortunately we don't need to do this unless we reset the | |
338 | * chip at a PCI level. | |
339 | * | |
340 | * Next we need to restore the context, but we don't use those | |
341 | * yet either... | |
342 | * | |
343 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
344 | * was running at the time of the reset (i.e. we weren't VT | |
345 | * switched away). | |
346 | */ | |
347 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
348 | !dev_priv->mm.suspended) { | |
349 | drm_i915_ring_buffer_t *ring = &dev_priv->ring; | |
350 | struct drm_gem_object *obj = ring->ring_obj; | |
351 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
352 | dev_priv->mm.suspended = 0; | |
353 | ||
354 | /* Stop the ring if it's running. */ | |
355 | I915_WRITE(PRB0_CTL, 0); | |
356 | I915_WRITE(PRB0_TAIL, 0); | |
357 | I915_WRITE(PRB0_HEAD, 0); | |
358 | ||
359 | /* Initialize the ring. */ | |
360 | I915_WRITE(PRB0_START, obj_priv->gtt_offset); | |
361 | I915_WRITE(PRB0_CTL, | |
362 | ((obj->size - 4096) & RING_NR_PAGES) | | |
363 | RING_NO_REPORT | | |
364 | RING_VALID); | |
365 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
366 | i915_kernel_lost_context(dev); | |
367 | else { | |
368 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; | |
369 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
370 | ring->space = ring->head - (ring->tail + 8); | |
371 | if (ring->space < 0) | |
372 | ring->space += ring->Size; | |
373 | } | |
374 | ||
375 | mutex_unlock(&dev->struct_mutex); | |
376 | drm_irq_uninstall(dev); | |
377 | drm_irq_install(dev); | |
378 | mutex_lock(&dev->struct_mutex); | |
379 | } | |
380 | ||
381 | /* | |
382 | * Display needs restore too... | |
383 | */ | |
384 | if (need_display) | |
385 | i915_restore_display(dev); | |
386 | ||
387 | mutex_unlock(&dev->struct_mutex); | |
388 | return 0; | |
389 | } | |
390 | ||
391 | ||
112b715e KH |
392 | static int __devinit |
393 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
394 | { | |
395 | return drm_get_dev(pdev, ent, &driver); | |
396 | } | |
397 | ||
398 | static void | |
399 | i915_pci_remove(struct pci_dev *pdev) | |
400 | { | |
401 | struct drm_device *dev = pci_get_drvdata(pdev); | |
402 | ||
403 | drm_put_dev(dev); | |
404 | } | |
405 | ||
84b79f8d | 406 | static int i915_pm_suspend(struct device *dev) |
112b715e | 407 | { |
84b79f8d RW |
408 | struct pci_dev *pdev = to_pci_dev(dev); |
409 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
410 | int error; | |
112b715e | 411 | |
84b79f8d RW |
412 | if (!drm_dev || !drm_dev->dev_private) { |
413 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
414 | return -ENODEV; | |
415 | } | |
112b715e | 416 | |
84b79f8d RW |
417 | error = i915_drm_freeze(drm_dev); |
418 | if (error) | |
419 | return error; | |
112b715e | 420 | |
84b79f8d RW |
421 | pci_disable_device(pdev); |
422 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 423 | |
84b79f8d | 424 | return 0; |
cbda12d7 ZW |
425 | } |
426 | ||
84b79f8d | 427 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 428 | { |
84b79f8d RW |
429 | struct pci_dev *pdev = to_pci_dev(dev); |
430 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
431 | ||
432 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
433 | } |
434 | ||
84b79f8d | 435 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 436 | { |
84b79f8d RW |
437 | struct pci_dev *pdev = to_pci_dev(dev); |
438 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
439 | ||
440 | if (!drm_dev || !drm_dev->dev_private) { | |
441 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
442 | return -ENODEV; | |
443 | } | |
444 | ||
445 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
446 | } |
447 | ||
84b79f8d | 448 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 449 | { |
84b79f8d RW |
450 | struct pci_dev *pdev = to_pci_dev(dev); |
451 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
452 | ||
453 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
454 | } |
455 | ||
84b79f8d | 456 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 457 | { |
84b79f8d RW |
458 | struct pci_dev *pdev = to_pci_dev(dev); |
459 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 460 | |
61caf87c | 461 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
462 | } |
463 | ||
464 | const struct dev_pm_ops i915_pm_ops = { | |
465 | .suspend = i915_pm_suspend, | |
466 | .resume = i915_pm_resume, | |
467 | .freeze = i915_pm_freeze, | |
468 | .thaw = i915_pm_thaw, | |
469 | .poweroff = i915_pm_poweroff, | |
84b79f8d | 470 | .restore = i915_pm_resume, |
cbda12d7 ZW |
471 | }; |
472 | ||
de151cf6 JB |
473 | static struct vm_operations_struct i915_gem_vm_ops = { |
474 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
475 | .open = drm_gem_vm_open, |
476 | .close = drm_gem_vm_close, | |
de151cf6 JB |
477 | }; |
478 | ||
1da177e4 | 479 | static struct drm_driver driver = { |
792d2b9a DA |
480 | /* don't use mtrr's here, the Xserver or user space app should |
481 | * deal with them for intel hardware. | |
482 | */ | |
673a394b EA |
483 | .driver_features = |
484 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
485 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 486 | .load = i915_driver_load, |
ba8bbcf6 | 487 | .unload = i915_driver_unload, |
673a394b | 488 | .open = i915_driver_open, |
22eae947 DA |
489 | .lastclose = i915_driver_lastclose, |
490 | .preclose = i915_driver_preclose, | |
673a394b | 491 | .postclose = i915_driver_postclose, |
d8e29209 RW |
492 | |
493 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
494 | .suspend = i915_suspend, | |
495 | .resume = i915_resume, | |
496 | ||
cda17380 | 497 | .device_is_agp = i915_driver_device_is_agp, |
0a3e67a4 JB |
498 | .enable_vblank = i915_enable_vblank, |
499 | .disable_vblank = i915_disable_vblank, | |
1da177e4 LT |
500 | .irq_preinstall = i915_driver_irq_preinstall, |
501 | .irq_postinstall = i915_driver_irq_postinstall, | |
502 | .irq_uninstall = i915_driver_irq_uninstall, | |
503 | .irq_handler = i915_driver_irq_handler, | |
504 | .reclaim_buffers = drm_core_reclaim_buffers, | |
505 | .get_map_ofs = drm_core_get_map_ofs, | |
506 | .get_reg_ofs = drm_core_get_reg_ofs, | |
7c1c2871 DA |
507 | .master_create = i915_master_create, |
508 | .master_destroy = i915_master_destroy, | |
955b12de | 509 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
510 | .debugfs_init = i915_debugfs_init, |
511 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 512 | #endif |
673a394b EA |
513 | .gem_init_object = i915_gem_init_object, |
514 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 515 | .gem_vm_ops = &i915_gem_vm_ops, |
1da177e4 LT |
516 | .ioctls = i915_ioctls, |
517 | .fops = { | |
b5e89ed5 DA |
518 | .owner = THIS_MODULE, |
519 | .open = drm_open, | |
520 | .release = drm_release, | |
ed8b6704 | 521 | .unlocked_ioctl = drm_ioctl, |
de151cf6 | 522 | .mmap = drm_gem_mmap, |
b5e89ed5 DA |
523 | .poll = drm_poll, |
524 | .fasync = drm_fasync, | |
c9a9c5e0 | 525 | .read = drm_read, |
8ca7c1df | 526 | #ifdef CONFIG_COMPAT |
b5e89ed5 | 527 | .compat_ioctl = i915_compat_ioctl, |
8ca7c1df | 528 | #endif |
22eae947 DA |
529 | }, |
530 | ||
1da177e4 | 531 | .pci_driver = { |
22eae947 DA |
532 | .name = DRIVER_NAME, |
533 | .id_table = pciidlist, | |
112b715e KH |
534 | .probe = i915_pci_probe, |
535 | .remove = i915_pci_remove, | |
cbda12d7 | 536 | .driver.pm = &i915_pm_ops, |
22eae947 | 537 | }, |
bc5f4523 | 538 | |
22eae947 DA |
539 | .name = DRIVER_NAME, |
540 | .desc = DRIVER_DESC, | |
541 | .date = DRIVER_DATE, | |
542 | .major = DRIVER_MAJOR, | |
543 | .minor = DRIVER_MINOR, | |
544 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
545 | }; |
546 | ||
547 | static int __init i915_init(void) | |
548 | { | |
549 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 | 550 | |
31169714 CW |
551 | i915_gem_shrinker_init(); |
552 | ||
79e53945 JB |
553 | /* |
554 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
555 | * explicitly disabled with the module pararmeter. | |
556 | * | |
557 | * Otherwise, just follow the parameter (defaulting to off). | |
558 | * | |
559 | * Allow optional vga_text_mode_force boot option to override | |
560 | * the default behavior. | |
561 | */ | |
562 | #if defined(CONFIG_DRM_I915_KMS) | |
563 | if (i915_modeset != 0) | |
564 | driver.driver_features |= DRIVER_MODESET; | |
565 | #endif | |
566 | if (i915_modeset == 1) | |
567 | driver.driver_features |= DRIVER_MODESET; | |
568 | ||
569 | #ifdef CONFIG_VGA_CONSOLE | |
570 | if (vgacon_text_force() && i915_modeset == -1) | |
571 | driver.driver_features &= ~DRIVER_MODESET; | |
572 | #endif | |
573 | ||
1da177e4 LT |
574 | return drm_init(&driver); |
575 | } | |
576 | ||
577 | static void __exit i915_exit(void) | |
578 | { | |
31169714 | 579 | i915_gem_shrinker_exit(); |
1da177e4 LT |
580 | drm_exit(&driver); |
581 | } | |
582 | ||
583 | module_init(i915_init); | |
584 | module_exit(i915_exit); | |
585 | ||
b5e89ed5 DA |
586 | MODULE_AUTHOR(DRIVER_AUTHOR); |
587 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 588 | MODULE_LICENSE("GPL and additional rights"); |