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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a726915c | 50 | int i915_panel_ignore_lid __read_mostly = 1; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 | 52 | MODULE_PARM_DESC(panel_ignore_lid, |
a726915c DV |
53 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " |
54 | "-1=force lid closed, -2=force lid open)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
f57f9c16 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
105b7c11 RV |
121 | int i915_enable_psr __read_mostly = 0; |
122 | module_param_named(enable_psr, i915_enable_psr, int, 0600); | |
123 | MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)"); | |
124 | ||
99486b8e | 125 | unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT); |
0a3af268 RV |
126 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); |
127 | MODULE_PARM_DESC(preliminary_hw_support, | |
99486b8e | 128 | "Enable preliminary hardware support."); |
0a3af268 | 129 | |
bf51d5e2 | 130 | int i915_disable_power_well __read_mostly = 1; |
2124b72e PZ |
131 | module_param_named(disable_power_well, i915_disable_power_well, int, 0600); |
132 | MODULE_PARM_DESC(disable_power_well, | |
bf51d5e2 | 133 | "Disable the power well when possible (default: true)"); |
2124b72e | 134 | |
3c4ca58c PZ |
135 | int i915_enable_ips __read_mostly = 1; |
136 | module_param_named(enable_ips, i915_enable_ips, int, 0600); | |
137 | MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); | |
138 | ||
2385bdf0 JB |
139 | bool i915_fastboot __read_mostly = 0; |
140 | module_param_named(fastboot, i915_fastboot, bool, 0600); | |
141 | MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time " | |
142 | "(default: false)"); | |
143 | ||
e27e9708 | 144 | int i915_enable_pc8 __read_mostly = 1; |
c67a470b | 145 | module_param_named(enable_pc8, i915_enable_pc8, int, 0600); |
e27e9708 | 146 | MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)"); |
c67a470b | 147 | |
90058745 PZ |
148 | int i915_pc8_timeout __read_mostly = 5000; |
149 | module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600); | |
150 | MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)"); | |
151 | ||
0b74b508 XZ |
152 | bool i915_prefault_disable __read_mostly; |
153 | module_param_named(prefault_disable, i915_prefault_disable, bool, 0600); | |
154 | MODULE_PARM_DESC(prefault_disable, | |
155 | "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); | |
156 | ||
112b715e | 157 | static struct drm_driver driver; |
1f7a6e37 | 158 | extern int intel_agp_enabled; |
112b715e | 159 | |
9a7e8492 | 160 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 161 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 162 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 163 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
164 | }; |
165 | ||
9a7e8492 | 166 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 167 | .gen = 2, .num_pipes = 1, |
31578148 | 168 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 169 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
170 | }; |
171 | ||
9a7e8492 | 172 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 173 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 174 | .cursor_needs_physical = 1, |
31578148 | 175 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 176 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
177 | }; |
178 | ||
9a7e8492 | 179 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 180 | .gen = 2, .num_pipes = 1, |
31578148 | 181 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 182 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
183 | }; |
184 | ||
9a7e8492 | 185 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 186 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 187 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 188 | .ring_mask = RENDER_RING, |
cfdf1fa2 | 189 | }; |
9a7e8492 | 190 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 191 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 192 | .cursor_needs_physical = 1, |
31578148 | 193 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 194 | .supports_tv = 1, |
73ae478c | 195 | .ring_mask = RENDER_RING, |
cfdf1fa2 | 196 | }; |
9a7e8492 | 197 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 198 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 199 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 200 | .ring_mask = RENDER_RING, |
cfdf1fa2 | 201 | }; |
9a7e8492 | 202 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 203 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 204 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 205 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 206 | .supports_tv = 1, |
73ae478c | 207 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
208 | }; |
209 | ||
9a7e8492 | 210 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 211 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 212 | .has_hotplug = 1, |
31578148 | 213 | .has_overlay = 1, |
73ae478c | 214 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
215 | }; |
216 | ||
9a7e8492 | 217 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 218 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 219 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 220 | .has_overlay = 1, |
a6c45cf0 | 221 | .supports_tv = 1, |
73ae478c | 222 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
223 | }; |
224 | ||
9a7e8492 | 225 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 226 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 227 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 228 | .has_overlay = 1, |
73ae478c | 229 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
230 | }; |
231 | ||
9a7e8492 | 232 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 233 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 234 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 235 | .ring_mask = RENDER_RING | BSD_RING, |
cfdf1fa2 KH |
236 | }; |
237 | ||
9a7e8492 | 238 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 239 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 240 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 241 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 242 | .supports_tv = 1, |
73ae478c | 243 | .ring_mask = RENDER_RING | BSD_RING, |
cfdf1fa2 KH |
244 | }; |
245 | ||
9a7e8492 | 246 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 247 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 248 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 249 | .has_overlay = 1, |
cfdf1fa2 KH |
250 | }; |
251 | ||
9a7e8492 | 252 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 253 | .gen = 5, .num_pipes = 2, |
5a117db7 | 254 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 255 | .ring_mask = RENDER_RING | BSD_RING, |
cfdf1fa2 KH |
256 | }; |
257 | ||
9a7e8492 | 258 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 259 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 260 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 261 | .has_fbc = 1, |
73ae478c | 262 | .ring_mask = RENDER_RING | BSD_RING, |
cfdf1fa2 KH |
263 | }; |
264 | ||
9a7e8492 | 265 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 266 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 267 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 268 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 269 | .has_llc = 1, |
f6e450a6 EA |
270 | }; |
271 | ||
9a7e8492 | 272 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 273 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 274 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 275 | .has_fbc = 1, |
73ae478c | 276 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 277 | .has_llc = 1, |
a13e4093 EA |
278 | }; |
279 | ||
219f4fdb BW |
280 | #define GEN7_FEATURES \ |
281 | .gen = 7, .num_pipes = 3, \ | |
282 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
73ae478c | 283 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 284 | .has_llc = 1 |
219f4fdb | 285 | |
c76b615c | 286 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
287 | GEN7_FEATURES, |
288 | .is_ivybridge = 1, | |
c76b615c JB |
289 | }; |
290 | ||
291 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
292 | GEN7_FEATURES, |
293 | .is_ivybridge = 1, | |
294 | .is_mobile = 1, | |
abe959c7 | 295 | .has_fbc = 1, |
c76b615c JB |
296 | }; |
297 | ||
999bcdea BW |
298 | static const struct intel_device_info intel_ivybridge_q_info = { |
299 | GEN7_FEATURES, | |
300 | .is_ivybridge = 1, | |
301 | .num_pipes = 0, /* legal, last one wins */ | |
302 | }; | |
303 | ||
70a3eb7a | 304 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
305 | GEN7_FEATURES, |
306 | .is_mobile = 1, | |
307 | .num_pipes = 2, | |
70a3eb7a | 308 | .is_valleyview = 1, |
fba5d532 | 309 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 310 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
311 | }; |
312 | ||
313 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
314 | GEN7_FEATURES, |
315 | .num_pipes = 2, | |
70a3eb7a | 316 | .is_valleyview = 1, |
fba5d532 | 317 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 318 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
319 | }; |
320 | ||
4cae9ae0 | 321 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
322 | GEN7_FEATURES, |
323 | .is_haswell = 1, | |
dd93be58 | 324 | .has_ddi = 1, |
30568c45 | 325 | .has_fpga_dbg = 1, |
73ae478c | 326 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
4cae9ae0 ED |
327 | }; |
328 | ||
329 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
330 | GEN7_FEATURES, |
331 | .is_haswell = 1, | |
332 | .is_mobile = 1, | |
dd93be58 | 333 | .has_ddi = 1, |
30568c45 | 334 | .has_fpga_dbg = 1, |
891348b2 | 335 | .has_fbc = 1, |
73ae478c | 336 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
c76b615c JB |
337 | }; |
338 | ||
4d4dead6 BW |
339 | static const struct intel_device_info intel_broadwell_d_info = { |
340 | .is_preliminary = 1, | |
4b30553d | 341 | .gen = 8, .num_pipes = 3, |
4d4dead6 BW |
342 | .need_gfx_hws = 1, .has_hotplug = 1, |
343 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
344 | .has_llc = 1, | |
345 | .has_ddi = 1, | |
346 | }; | |
347 | ||
348 | static const struct intel_device_info intel_broadwell_m_info = { | |
349 | .is_preliminary = 1, | |
4b30553d | 350 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
4d4dead6 BW |
351 | .need_gfx_hws = 1, .has_hotplug = 1, |
352 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
353 | .has_llc = 1, | |
354 | .has_ddi = 1, | |
355 | }; | |
356 | ||
a0a18075 JB |
357 | /* |
358 | * Make sure any device matches here are from most specific to most | |
359 | * general. For example, since the Quanta match is based on the subsystem | |
360 | * and subvendor IDs, we need it to come before the more general IVB | |
361 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
362 | */ | |
363 | #define INTEL_PCI_IDS \ | |
364 | INTEL_I830_IDS(&intel_i830_info), \ | |
365 | INTEL_I845G_IDS(&intel_845g_info), \ | |
366 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
367 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
368 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
369 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
370 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
371 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
372 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
373 | INTEL_G33_IDS(&intel_g33_info), \ | |
374 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
375 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
376 | INTEL_G45_IDS(&intel_g45_info), \ | |
377 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
378 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
379 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
380 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
381 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
382 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
383 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
384 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
385 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
386 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
387 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
4d4dead6 BW |
388 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ |
389 | INTEL_BDW_M_IDS(&intel_broadwell_m_info), \ | |
390 | INTEL_BDW_D_IDS(&intel_broadwell_d_info) | |
a0a18075 | 391 | |
6103da0d | 392 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 393 | INTEL_PCI_IDS, |
49ae35f2 | 394 | {0, 0, 0} |
1da177e4 LT |
395 | }; |
396 | ||
79e53945 JB |
397 | #if defined(CONFIG_DRM_I915_KMS) |
398 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
399 | #endif | |
400 | ||
0206e353 | 401 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
402 | { |
403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
404 | struct pci_dev *pch; | |
405 | ||
ce1bb329 BW |
406 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
407 | * (which really amounts to a PCH but no South Display). | |
408 | */ | |
409 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
410 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
411 | return; |
412 | } | |
413 | ||
3bad0781 ZW |
414 | /* |
415 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
416 | * make graphics device passthrough work easy for VMM, that only | |
417 | * need to expose ISA bridge to let driver know the real hardware | |
418 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
419 | * |
420 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
421 | * ISA bridge in the system. To work reliably, we should scan trhough | |
422 | * all the ISA bridge devices and check for the first match, instead | |
423 | * of only checking the first one. | |
3bad0781 ZW |
424 | */ |
425 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
6a9c4b35 RG |
426 | while (pch) { |
427 | struct pci_dev *curr = pch; | |
3bad0781 | 428 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
17a303ec | 429 | unsigned short id; |
3bad0781 | 430 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 431 | dev_priv->pch_id = id; |
3bad0781 | 432 | |
90711d50 JB |
433 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
434 | dev_priv->pch_type = PCH_IBX; | |
435 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 436 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 437 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
438 | dev_priv->pch_type = PCH_CPT; |
439 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 440 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
441 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
442 | /* PantherPoint is CPT compatible */ | |
443 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 444 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 445 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
446 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
447 | dev_priv->pch_type = PCH_LPT; | |
448 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 449 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 450 | WARN_ON(IS_ULT(dev)); |
ae6935dd WSC |
451 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
452 | dev_priv->pch_type = PCH_LPT; | |
ae6935dd WSC |
453 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
454 | WARN_ON(!IS_HASWELL(dev)); | |
08e1413d | 455 | WARN_ON(!IS_ULT(dev)); |
018f52c9 PZ |
456 | } else if (IS_BROADWELL(dev)) { |
457 | dev_priv->pch_type = PCH_LPT; | |
458 | dev_priv->pch_id = | |
459 | INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
460 | DRM_DEBUG_KMS("This is Broadwell, assuming " | |
461 | "LynxPoint LP PCH\n"); | |
6a9c4b35 RG |
462 | } else { |
463 | goto check_next; | |
3bad0781 | 464 | } |
6a9c4b35 RG |
465 | pci_dev_put(pch); |
466 | break; | |
3bad0781 | 467 | } |
6a9c4b35 RG |
468 | check_next: |
469 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr); | |
470 | pci_dev_put(curr); | |
3bad0781 | 471 | } |
6a9c4b35 RG |
472 | if (!pch) |
473 | DRM_DEBUG_KMS("No PCH found?\n"); | |
3bad0781 ZW |
474 | } |
475 | ||
2911a35b BW |
476 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
477 | { | |
478 | if (INTEL_INFO(dev)->gen < 6) | |
479 | return 0; | |
480 | ||
e64c4a1b BW |
481 | /* Until we get further testing... */ |
482 | if (IS_GEN8(dev)) { | |
483 | WARN_ON(!i915_preliminary_hw_support); | |
484 | return 0; | |
485 | } | |
486 | ||
2911a35b BW |
487 | if (i915_semaphores >= 0) |
488 | return i915_semaphores; | |
489 | ||
59de3295 | 490 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 491 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
492 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
493 | return false; | |
494 | #endif | |
2911a35b BW |
495 | |
496 | return 1; | |
497 | } | |
498 | ||
84b79f8d | 499 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 500 | { |
61caf87c | 501 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 502 | struct drm_crtc *crtc; |
61caf87c | 503 | |
b8efb17b ZR |
504 | /* ignore lid events during suspend */ |
505 | mutex_lock(&dev_priv->modeset_restore_lock); | |
506 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
507 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
508 | ||
c67a470b PZ |
509 | /* We do a lot of poking in a lot of registers, make sure they work |
510 | * properly. */ | |
511 | hsw_disable_package_c8(dev_priv); | |
baa70707 | 512 | intel_display_set_init_power(dev, true); |
cb10799c | 513 | |
5bcf719b DA |
514 | drm_kms_helper_poll_disable(dev); |
515 | ||
ba8bbcf6 | 516 | pci_save_state(dev->pdev); |
ba8bbcf6 | 517 | |
5669fcac | 518 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 519 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
520 | int error; |
521 | ||
45c5f202 | 522 | error = i915_gem_suspend(dev); |
84b79f8d | 523 | if (error) { |
226485e9 | 524 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
525 | "GEM idle failed, resume might fail\n"); |
526 | return error; | |
527 | } | |
a261b246 | 528 | |
1a01ab3b JB |
529 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
530 | ||
226485e9 | 531 | drm_irq_uninstall(dev); |
15239099 | 532 | dev_priv->enable_hotplug_processing = false; |
24576d23 JB |
533 | /* |
534 | * Disable CRTCs directly since we want to preserve sw state | |
535 | * for _thaw. | |
536 | */ | |
537 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
538 | dev_priv->display.crtc_disable(crtc); | |
7d708ee4 ID |
539 | |
540 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
541 | } |
542 | ||
828c7908 BW |
543 | i915_gem_suspend_gtt_mappings(dev); |
544 | ||
9e06dd39 JB |
545 | i915_save_state(dev); |
546 | ||
44834a67 | 547 | intel_opregion_fini(dev); |
8ee1c3db | 548 | |
3fa016a0 | 549 | console_lock(); |
b6f3eff7 | 550 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
551 | console_unlock(); |
552 | ||
61caf87c | 553 | return 0; |
84b79f8d RW |
554 | } |
555 | ||
6a9ee8af | 556 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
557 | { |
558 | int error; | |
559 | ||
560 | if (!dev || !dev->dev_private) { | |
561 | DRM_ERROR("dev: %p\n", dev); | |
562 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
563 | return -ENODEV; | |
564 | } | |
565 | ||
566 | if (state.event == PM_EVENT_PRETHAW) | |
567 | return 0; | |
568 | ||
5bcf719b DA |
569 | |
570 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
571 | return 0; | |
6eecba33 | 572 | |
84b79f8d RW |
573 | error = i915_drm_freeze(dev); |
574 | if (error) | |
575 | return error; | |
576 | ||
b932ccb5 DA |
577 | if (state.event == PM_EVENT_SUSPEND) { |
578 | /* Shut down the device */ | |
579 | pci_disable_device(dev->pdev); | |
580 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
581 | } | |
ba8bbcf6 JB |
582 | |
583 | return 0; | |
584 | } | |
585 | ||
073f34d9 JB |
586 | void intel_console_resume(struct work_struct *work) |
587 | { | |
588 | struct drm_i915_private *dev_priv = | |
589 | container_of(work, struct drm_i915_private, | |
590 | console_resume_work); | |
591 | struct drm_device *dev = dev_priv->dev; | |
592 | ||
593 | console_lock(); | |
b6f3eff7 | 594 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
595 | console_unlock(); |
596 | } | |
597 | ||
bb60b969 JB |
598 | static void intel_resume_hotplug(struct drm_device *dev) |
599 | { | |
600 | struct drm_mode_config *mode_config = &dev->mode_config; | |
601 | struct intel_encoder *encoder; | |
602 | ||
603 | mutex_lock(&mode_config->mutex); | |
604 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); | |
605 | ||
606 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
607 | if (encoder->hot_plug) | |
608 | encoder->hot_plug(encoder); | |
609 | ||
610 | mutex_unlock(&mode_config->mutex); | |
611 | ||
612 | /* Just fire off a uevent and let userspace tell us what to do */ | |
613 | drm_helper_hpd_irq_event(dev); | |
614 | } | |
615 | ||
9d49c0ef | 616 | static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) |
ba8bbcf6 | 617 | { |
5669fcac | 618 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 619 | int error = 0; |
8ee1c3db | 620 | |
c9f7fbf9 VS |
621 | intel_uncore_early_sanitize(dev); |
622 | ||
9d49c0ef PZ |
623 | intel_uncore_sanitize(dev); |
624 | ||
625 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
626 | restore_gtt_mappings) { | |
627 | mutex_lock(&dev->struct_mutex); | |
628 | i915_gem_restore_gtt_mappings(dev); | |
629 | mutex_unlock(&dev->struct_mutex); | |
630 | } | |
631 | ||
ddb642fb | 632 | intel_power_domains_init_hw(dev); |
ebdcefc6 | 633 | |
61caf87c | 634 | i915_restore_state(dev); |
44834a67 | 635 | intel_opregion_setup(dev); |
61caf87c | 636 | |
5669fcac JB |
637 | /* KMS EnterVT equivalent */ |
638 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 639 | intel_init_pch_refclk(dev); |
1833b134 | 640 | |
5669fcac | 641 | mutex_lock(&dev->struct_mutex); |
5669fcac | 642 | |
f691e2f4 | 643 | error = i915_gem_init_hw(dev); |
5669fcac | 644 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 645 | |
15239099 DV |
646 | /* We need working interrupts for modeset enabling ... */ |
647 | drm_irq_install(dev); | |
648 | ||
1833b134 | 649 | intel_modeset_init_hw(dev); |
24576d23 JB |
650 | |
651 | drm_modeset_lock_all(dev); | |
652 | intel_modeset_setup_hw_state(dev, true); | |
653 | drm_modeset_unlock_all(dev); | |
15239099 DV |
654 | |
655 | /* | |
656 | * ... but also need to make sure that hotplug processing | |
657 | * doesn't cause havoc. Like in the driver load code we don't | |
658 | * bother with the tiny race here where we might loose hotplug | |
659 | * notifications. | |
660 | * */ | |
20afbda2 | 661 | intel_hpd_init(dev); |
15239099 | 662 | dev_priv->enable_hotplug_processing = true; |
bb60b969 JB |
663 | /* Config may have changed between suspend and resume */ |
664 | intel_resume_hotplug(dev); | |
d5bb081b | 665 | } |
1daed3fb | 666 | |
44834a67 CW |
667 | intel_opregion_init(dev); |
668 | ||
073f34d9 JB |
669 | /* |
670 | * The console lock can be pretty contented on resume due | |
671 | * to all the printk activity. Try to keep it out of the hot | |
672 | * path of resume if possible. | |
673 | */ | |
674 | if (console_trylock()) { | |
b6f3eff7 | 675 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
676 | console_unlock(); |
677 | } else { | |
678 | schedule_work(&dev_priv->console_resume_work); | |
679 | } | |
680 | ||
c67a470b PZ |
681 | /* Undo what we did at i915_drm_freeze so the refcount goes back to the |
682 | * expected level. */ | |
683 | hsw_enable_package_c8(dev_priv); | |
684 | ||
b8efb17b ZR |
685 | mutex_lock(&dev_priv->modeset_restore_lock); |
686 | dev_priv->modeset_restore = MODESET_DONE; | |
687 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
84b79f8d RW |
688 | return error; |
689 | } | |
690 | ||
1abd02e2 JB |
691 | static int i915_drm_thaw(struct drm_device *dev) |
692 | { | |
7f16e5c1 | 693 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
828c7908 | 694 | i915_check_and_clear_faults(dev); |
1abd02e2 | 695 | |
9d49c0ef | 696 | return __i915_drm_thaw(dev, true); |
84b79f8d RW |
697 | } |
698 | ||
6a9ee8af | 699 | int i915_resume(struct drm_device *dev) |
84b79f8d | 700 | { |
1abd02e2 | 701 | struct drm_i915_private *dev_priv = dev->dev_private; |
6eecba33 CW |
702 | int ret; |
703 | ||
5bcf719b DA |
704 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
705 | return 0; | |
706 | ||
84b79f8d RW |
707 | if (pci_enable_device(dev->pdev)) |
708 | return -EIO; | |
709 | ||
710 | pci_set_master(dev->pdev); | |
711 | ||
1abd02e2 JB |
712 | /* |
713 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
9d49c0ef PZ |
714 | * earlier) need to restore the GTT mappings since the BIOS might clear |
715 | * all our scratch PTEs. | |
1abd02e2 | 716 | */ |
9d49c0ef | 717 | ret = __i915_drm_thaw(dev, !dev_priv->opregion.header); |
6eecba33 CW |
718 | if (ret) |
719 | return ret; | |
720 | ||
721 | drm_kms_helper_poll_enable(dev); | |
722 | return 0; | |
ba8bbcf6 JB |
723 | } |
724 | ||
11ed50ec | 725 | /** |
f3953dcb | 726 | * i915_reset - reset chip after a hang |
11ed50ec | 727 | * @dev: drm device to reset |
11ed50ec BG |
728 | * |
729 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
730 | * reset or otherwise an error code. | |
731 | * | |
732 | * Procedure is fairly simple: | |
733 | * - reset the chip using the reset reg | |
734 | * - re-init context state | |
735 | * - re-init hardware status page | |
736 | * - re-init ring buffer | |
737 | * - re-init interrupt state | |
738 | * - re-init display | |
739 | */ | |
d4b8bb2a | 740 | int i915_reset(struct drm_device *dev) |
11ed50ec BG |
741 | { |
742 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2e7c8ee7 | 743 | bool simulated; |
0573ed4a | 744 | int ret; |
11ed50ec | 745 | |
d78cb50b CW |
746 | if (!i915_try_reset) |
747 | return 0; | |
748 | ||
d54a02c0 | 749 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 750 | |
069efc1d | 751 | i915_gem_reset(dev); |
77f01230 | 752 | |
2e7c8ee7 CW |
753 | simulated = dev_priv->gpu_error.stop_rings != 0; |
754 | ||
be62acb4 MK |
755 | ret = intel_gpu_reset(dev); |
756 | ||
757 | /* Also reset the gpu hangman. */ | |
758 | if (simulated) { | |
759 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
760 | dev_priv->gpu_error.stop_rings = 0; | |
761 | if (ret == -ENODEV) { | |
762 | DRM_ERROR("Reset not implemented, but ignoring " | |
763 | "error for simulated gpu hangs\n"); | |
764 | ret = 0; | |
765 | } | |
2e7c8ee7 | 766 | } |
be62acb4 | 767 | |
0573ed4a | 768 | if (ret) { |
f803aa55 | 769 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 770 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 771 | return ret; |
11ed50ec BG |
772 | } |
773 | ||
774 | /* Ok, now get things going again... */ | |
775 | ||
776 | /* | |
777 | * Everything depends on having the GTT running, so we need to start | |
778 | * there. Fortunately we don't need to do this unless we reset the | |
779 | * chip at a PCI level. | |
780 | * | |
781 | * Next we need to restore the context, but we don't use those | |
782 | * yet either... | |
783 | * | |
784 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
785 | * was running at the time of the reset (i.e. we weren't VT | |
786 | * switched away). | |
787 | */ | |
788 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 789 | !dev_priv->ums.mm_suspended) { |
3d57e5bd | 790 | bool hw_contexts_disabled = dev_priv->hw_contexts_disabled; |
db1b76ca | 791 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 792 | |
3d57e5bd BW |
793 | ret = i915_gem_init_hw(dev); |
794 | if (!hw_contexts_disabled && dev_priv->hw_contexts_disabled) | |
795 | DRM_ERROR("HW contexts didn't survive reset\n"); | |
8e88a2bd | 796 | mutex_unlock(&dev->struct_mutex); |
3d57e5bd BW |
797 | if (ret) { |
798 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
799 | return ret; | |
800 | } | |
f817586c | 801 | |
11ed50ec BG |
802 | drm_irq_uninstall(dev); |
803 | drm_irq_install(dev); | |
20afbda2 | 804 | intel_hpd_init(dev); |
bcbc324a DV |
805 | } else { |
806 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
807 | } |
808 | ||
11ed50ec BG |
809 | return 0; |
810 | } | |
811 | ||
56550d94 | 812 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 813 | { |
01a06850 DV |
814 | struct intel_device_info *intel_info = |
815 | (struct intel_device_info *) ent->driver_data; | |
816 | ||
b833d685 BW |
817 | if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) { |
818 | DRM_INFO("This hardware requires preliminary hardware support.\n" | |
819 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
820 | return -ENODEV; | |
821 | } | |
822 | ||
5fe49d86 CW |
823 | /* Only bind to function 0 of the device. Early generations |
824 | * used function 1 as a placeholder for multi-head. This causes | |
825 | * us confusion instead, especially on the systems where both | |
826 | * functions have the same PCI-ID! | |
827 | */ | |
828 | if (PCI_FUNC(pdev->devfn)) | |
829 | return -ENODEV; | |
830 | ||
01a06850 DV |
831 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
832 | * implementation for gen3 (and only gen3) that used legacy drm maps | |
833 | * (gasp!) to share buffers between X and the client. Hence we need to | |
834 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ | |
835 | if (intel_info->gen != 3) { | |
836 | driver.driver_features &= | |
837 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); | |
838 | } else if (!intel_agp_enabled) { | |
839 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
840 | return -ENODEV; | |
841 | } | |
842 | ||
dcdb1674 | 843 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
844 | } |
845 | ||
846 | static void | |
847 | i915_pci_remove(struct pci_dev *pdev) | |
848 | { | |
849 | struct drm_device *dev = pci_get_drvdata(pdev); | |
850 | ||
851 | drm_put_dev(dev); | |
852 | } | |
853 | ||
84b79f8d | 854 | static int i915_pm_suspend(struct device *dev) |
112b715e | 855 | { |
84b79f8d RW |
856 | struct pci_dev *pdev = to_pci_dev(dev); |
857 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
858 | int error; | |
112b715e | 859 | |
84b79f8d RW |
860 | if (!drm_dev || !drm_dev->dev_private) { |
861 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
862 | return -ENODEV; | |
863 | } | |
112b715e | 864 | |
5bcf719b DA |
865 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
866 | return 0; | |
867 | ||
84b79f8d RW |
868 | error = i915_drm_freeze(drm_dev); |
869 | if (error) | |
870 | return error; | |
112b715e | 871 | |
84b79f8d RW |
872 | pci_disable_device(pdev); |
873 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 874 | |
84b79f8d | 875 | return 0; |
cbda12d7 ZW |
876 | } |
877 | ||
84b79f8d | 878 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 879 | { |
84b79f8d RW |
880 | struct pci_dev *pdev = to_pci_dev(dev); |
881 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
882 | ||
883 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
884 | } |
885 | ||
84b79f8d | 886 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 887 | { |
84b79f8d RW |
888 | struct pci_dev *pdev = to_pci_dev(dev); |
889 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
890 | ||
891 | if (!drm_dev || !drm_dev->dev_private) { | |
892 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
893 | return -ENODEV; | |
894 | } | |
895 | ||
896 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
897 | } |
898 | ||
84b79f8d | 899 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 900 | { |
84b79f8d RW |
901 | struct pci_dev *pdev = to_pci_dev(dev); |
902 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
903 | ||
904 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
905 | } |
906 | ||
84b79f8d | 907 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 908 | { |
84b79f8d RW |
909 | struct pci_dev *pdev = to_pci_dev(dev); |
910 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 911 | |
61caf87c | 912 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
913 | } |
914 | ||
b4b78d12 | 915 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
916 | .suspend = i915_pm_suspend, |
917 | .resume = i915_pm_resume, | |
918 | .freeze = i915_pm_freeze, | |
919 | .thaw = i915_pm_thaw, | |
920 | .poweroff = i915_pm_poweroff, | |
921 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
922 | }; |
923 | ||
78b68556 | 924 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 925 | .fault = i915_gem_fault, |
ab00b3e5 JB |
926 | .open = drm_gem_vm_open, |
927 | .close = drm_gem_vm_close, | |
de151cf6 JB |
928 | }; |
929 | ||
e08e96de AV |
930 | static const struct file_operations i915_driver_fops = { |
931 | .owner = THIS_MODULE, | |
932 | .open = drm_open, | |
933 | .release = drm_release, | |
934 | .unlocked_ioctl = drm_ioctl, | |
935 | .mmap = drm_gem_mmap, | |
936 | .poll = drm_poll, | |
e08e96de AV |
937 | .read = drm_read, |
938 | #ifdef CONFIG_COMPAT | |
939 | .compat_ioctl = i915_compat_ioctl, | |
940 | #endif | |
941 | .llseek = noop_llseek, | |
942 | }; | |
943 | ||
1da177e4 | 944 | static struct drm_driver driver = { |
0c54781b MW |
945 | /* Don't use MTRRs here; the Xserver or userspace app should |
946 | * deal with them for Intel hardware. | |
792d2b9a | 947 | */ |
673a394b | 948 | .driver_features = |
28185647 | 949 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | |
10ba5012 KH |
950 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
951 | DRIVER_RENDER, | |
22eae947 | 952 | .load = i915_driver_load, |
ba8bbcf6 | 953 | .unload = i915_driver_unload, |
673a394b | 954 | .open = i915_driver_open, |
22eae947 DA |
955 | .lastclose = i915_driver_lastclose, |
956 | .preclose = i915_driver_preclose, | |
673a394b | 957 | .postclose = i915_driver_postclose, |
d8e29209 RW |
958 | |
959 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
960 | .suspend = i915_suspend, | |
961 | .resume = i915_resume, | |
962 | ||
cda17380 | 963 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
964 | .master_create = i915_master_create, |
965 | .master_destroy = i915_master_destroy, | |
955b12de | 966 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
967 | .debugfs_init = i915_debugfs_init, |
968 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 969 | #endif |
673a394b | 970 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 971 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
972 | |
973 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
974 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
975 | .gem_prime_export = i915_gem_prime_export, | |
976 | .gem_prime_import = i915_gem_prime_import, | |
977 | ||
ff72145b DA |
978 | .dumb_create = i915_gem_dumb_create, |
979 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 980 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 981 | .ioctls = i915_ioctls, |
e08e96de | 982 | .fops = &i915_driver_fops, |
22eae947 DA |
983 | .name = DRIVER_NAME, |
984 | .desc = DRIVER_DESC, | |
985 | .date = DRIVER_DATE, | |
986 | .major = DRIVER_MAJOR, | |
987 | .minor = DRIVER_MINOR, | |
988 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
989 | }; |
990 | ||
8410ea3b DA |
991 | static struct pci_driver i915_pci_driver = { |
992 | .name = DRIVER_NAME, | |
993 | .id_table = pciidlist, | |
994 | .probe = i915_pci_probe, | |
995 | .remove = i915_pci_remove, | |
996 | .driver.pm = &i915_pm_ops, | |
997 | }; | |
998 | ||
1da177e4 LT |
999 | static int __init i915_init(void) |
1000 | { | |
1001 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1002 | |
1003 | /* | |
1004 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1005 | * explicitly disabled with the module pararmeter. | |
1006 | * | |
1007 | * Otherwise, just follow the parameter (defaulting to off). | |
1008 | * | |
1009 | * Allow optional vga_text_mode_force boot option to override | |
1010 | * the default behavior. | |
1011 | */ | |
1012 | #if defined(CONFIG_DRM_I915_KMS) | |
1013 | if (i915_modeset != 0) | |
1014 | driver.driver_features |= DRIVER_MODESET; | |
1015 | #endif | |
1016 | if (i915_modeset == 1) | |
1017 | driver.driver_features |= DRIVER_MODESET; | |
1018 | ||
1019 | #ifdef CONFIG_VGA_CONSOLE | |
1020 | if (vgacon_text_force() && i915_modeset == -1) | |
1021 | driver.driver_features &= ~DRIVER_MODESET; | |
1022 | #endif | |
1023 | ||
3885c6bb CW |
1024 | if (!(driver.driver_features & DRIVER_MODESET)) |
1025 | driver.get_vblank_timestamp = NULL; | |
1026 | ||
8410ea3b | 1027 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1028 | } |
1029 | ||
1030 | static void __exit i915_exit(void) | |
1031 | { | |
8410ea3b | 1032 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1033 | } |
1034 | ||
1035 | module_init(i915_init); | |
1036 | module_exit(i915_exit); | |
1037 | ||
b5e89ed5 DA |
1038 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1039 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1040 | MODULE_LICENSE("GPL and additional rights"); |