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drm/i915: Force RC6 restore after system resume and reset
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
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1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
0673ad47
CW		 46#include <drm/i915_drm.h>
47
48#include "i915_drv.h"
49#include "i915_trace.h"
50#include "i915_vgpu.h"
51#include "intel_drv.h"
79e53945 52
112b715e
KH		 53static struct drm_driver driver;
54
0673ad47
CW		 55static unsigned int i915_load_fail_count;
56
57bool __i915_inject_load_failure(const char *func, int line)
58{
59 if (i915_load_fail_count >= i915.inject_load_failure)
60 return false;
61
62 if (++i915_load_fail_count == i915.inject_load_failure) {
63 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
64 i915.inject_load_failure, func, line);
65 return true;
66 }
67
68 return false;
69}
70
71#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
72#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
73 "providing the dmesg log by booting with drm.debug=0xf"
74
75void
76__i915_printk(struct drm_i915_private *dev_priv, const char *level,
77 const char *fmt, ...)
78{
79 static bool shown_bug_once;
c49d13ee 80 struct device *kdev = dev_priv->drm.dev;
0673ad47
CW		 81 bool is_error = level[1] <= KERN_ERR[1];
82 bool is_debug = level[1] == KERN_DEBUG[1];
83 struct va_format vaf;
84 va_list args;
85
86 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
87 return;
88
89 va_start(args, fmt);
90
91 vaf.fmt = fmt;
92 vaf.va = &args;
93
c49d13ee 94 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
0673ad47
CW		 95 __builtin_return_address(0), &vaf);
96
97 if (is_error && !shown_bug_once) {
c49d13ee 98 dev_notice(kdev, "%s", FDO_BUG_MSG);
0673ad47
CW		 99 shown_bug_once = true;
100 }
101
102 va_end(args);
103}
104
105static bool i915_error_injected(struct drm_i915_private *dev_priv)
106{
107 return i915.inject_load_failure &&
108 i915_load_fail_count == i915.inject_load_failure;
109}
110
111#define i915_load_error(dev_priv, fmt, ...) \
112 __i915_printk(dev_priv, \
113 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
114 fmt, ##__VA_ARGS__)
115
116
117static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
118{
119 enum intel_pch ret = PCH_NOP;
120
121 /*
122 * In a virtualized passthrough environment we can be in a
123 * setup where the ISA bridge is not able to be passed through.
124 * In this case, a south bridge can be emulated and we have to
125 * make an educated guess as to which PCH is really there.
126 */
127
128 if (IS_GEN5(dev)) {
129 ret = PCH_IBX;
130 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
131 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
132 ret = PCH_CPT;
133 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
134 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
135 ret = PCH_LPT;
136 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
137 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
138 ret = PCH_SPT;
139 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
140 }
141
142 return ret;
143}
144
145static void intel_detect_pch(struct drm_device *dev)
146{
fac5e23e 147 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 148 struct pci_dev *pch = NULL;
149
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
152 */
153 if (INTEL_INFO(dev)->num_pipes == 0) {
154 dev_priv->pch_type = PCH_NOP;
155 return;
156 }
157
158 /*
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
163 *
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
168 */
169 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
170 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
171 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
172 dev_priv->pch_id = id;
173
174 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
175 dev_priv->pch_type = PCH_IBX;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
177 WARN_ON(!IS_GEN5(dev));
178 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
179 dev_priv->pch_type = PCH_CPT;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
181 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
182 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
183 /* PantherPoint is CPT compatible */
184 dev_priv->pch_type = PCH_CPT;
185 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
186 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
187 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
188 dev_priv->pch_type = PCH_LPT;
189 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
190 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
191 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
192 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
193 dev_priv->pch_type = PCH_LPT;
194 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
195 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
196 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
197 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
198 dev_priv->pch_type = PCH_SPT;
199 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
200 WARN_ON(!IS_SKYLAKE(dev) &&
201 !IS_KABYLAKE(dev));
202 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
203 dev_priv->pch_type = PCH_SPT;
204 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
205 WARN_ON(!IS_SKYLAKE(dev) &&
206 !IS_KABYLAKE(dev));
22dea0be
RV		 207 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
208 dev_priv->pch_type = PCH_KBP;
209 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
210 WARN_ON(!IS_KABYLAKE(dev));
0673ad47
CW		 211 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
212 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
213 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
214 pch->subsystem_vendor ==
215 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
216 pch->subsystem_device ==
217 PCI_SUBDEVICE_ID_QEMU)) {
218 dev_priv->pch_type = intel_virt_detect_pch(dev);
219 } else
220 continue;
221
222 break;
223 }
224 }
225 if (!pch)
226 DRM_DEBUG_KMS("No PCH found.\n");
227
228 pci_dev_put(pch);
229}
230
0673ad47
CW		 231static int i915_getparam(struct drm_device *dev, void *data,
232 struct drm_file *file_priv)
233{
fac5e23e 234 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 235 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 236 drm_i915_getparam_t *param = data;
237 int value;
238
239 switch (param->param) {
240 case I915_PARAM_IRQ_ACTIVE:
241 case I915_PARAM_ALLOW_BATCHBUFFER:
242 case I915_PARAM_LAST_DISPATCH:
243 /* Reject all old ums/dri params. */
244 return -ENODEV;
245 case I915_PARAM_CHIPSET_ID:
52a05c30 246 value = pdev->device;
0673ad47
CW		 247 break;
248 case I915_PARAM_REVISION:
52a05c30 249 value = pdev->revision;
0673ad47
CW		 250 break;
251 case I915_PARAM_HAS_GEM:
252 value = 1;
253 break;
254 case I915_PARAM_NUM_FENCES_AVAIL:
255 value = dev_priv->num_fence_regs;
256 break;
257 case I915_PARAM_HAS_OVERLAY:
258 value = dev_priv->overlay ? 1 : 0;
259 break;
260 case I915_PARAM_HAS_PAGEFLIPPING:
261 value = 1;
262 break;
263 case I915_PARAM_HAS_EXECBUF2:
264 /* depends on GEM */
265 value = 1;
266 break;
267 case I915_PARAM_HAS_BSD:
268 value = intel_engine_initialized(&dev_priv->engine[VCS]);
269 break;
270 case I915_PARAM_HAS_BLT:
271 value = intel_engine_initialized(&dev_priv->engine[BCS]);
272 break;
273 case I915_PARAM_HAS_VEBOX:
274 value = intel_engine_initialized(&dev_priv->engine[VECS]);
275 break;
276 case I915_PARAM_HAS_BSD2:
277 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
278 break;
279 case I915_PARAM_HAS_RELAXED_FENCING:
280 value = 1;
281 break;
282 case I915_PARAM_HAS_COHERENT_RINGS:
283 value = 1;
284 break;
285 case I915_PARAM_HAS_EXEC_CONSTANTS:
286 value = INTEL_INFO(dev)->gen >= 4;
287 break;
288 case I915_PARAM_HAS_RELAXED_DELTA:
289 value = 1;
290 break;
291 case I915_PARAM_HAS_GEN7_SOL_RESET:
292 value = 1;
293 break;
294 case I915_PARAM_HAS_LLC:
295 value = HAS_LLC(dev);
296 break;
297 case I915_PARAM_HAS_WT:
298 value = HAS_WT(dev);
299 break;
300 case I915_PARAM_HAS_ALIASING_PPGTT:
301 value = USES_PPGTT(dev);
302 break;
303 case I915_PARAM_HAS_WAIT_TIMEOUT:
304 value = 1;
305 break;
306 case I915_PARAM_HAS_SEMAPHORES:
39df9190 307 value = i915.semaphores;
0673ad47
CW		 308 break;
309 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
310 value = 1;
311 break;
312 case I915_PARAM_HAS_SECURE_BATCHES:
313 value = capable(CAP_SYS_ADMIN);
314 break;
315 case I915_PARAM_HAS_PINNED_BATCHES:
316 value = 1;
317 break;
318 case I915_PARAM_HAS_EXEC_NO_RELOC:
319 value = 1;
320 break;
321 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
322 value = 1;
323 break;
324 case I915_PARAM_CMD_PARSER_VERSION:
325 value = i915_cmd_parser_get_version(dev_priv);
326 break;
327 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
328 value = 1;
329 break;
330 case I915_PARAM_MMAP_VERSION:
331 value = 1;
332 break;
333 case I915_PARAM_SUBSLICE_TOTAL:
334 value = INTEL_INFO(dev)->subslice_total;
335 if (!value)
336 return -ENODEV;
337 break;
338 case I915_PARAM_EU_TOTAL:
339 value = INTEL_INFO(dev)->eu_total;
340 if (!value)
341 return -ENODEV;
342 break;
343 case I915_PARAM_HAS_GPU_RESET:
344 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
345 break;
346 case I915_PARAM_HAS_RESOURCE_STREAMER:
347 value = HAS_RESOURCE_STREAMER(dev);
348 break;
349 case I915_PARAM_HAS_EXEC_SOFTPIN:
350 value = 1;
351 break;
37f501af 352 case I915_PARAM_HAS_POOLED_EU:
353 value = HAS_POOLED_EU(dev);
354 break;
355 case I915_PARAM_MIN_EU_IN_POOL:
356 value = INTEL_INFO(dev)->min_eu_in_pool;
357 break;
0673ad47
CW		 358 default:
359 DRM_DEBUG("Unknown parameter %d\n", param->param);
360 return -EINVAL;
361 }
362
dda33009 363 if (put_user(value, param->value))
0673ad47 364 return -EFAULT;
0673ad47
CW		 365
366 return 0;
367}
368
369static int i915_get_bridge_dev(struct drm_device *dev)
370{
fac5e23e 371 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 372
373 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
374 if (!dev_priv->bridge_dev) {
375 DRM_ERROR("bridge device not found\n");
376 return -1;
377 }
378 return 0;
379}
380
381/* Allocate space for the MCH regs if needed, return nonzero on error */
382static int
383intel_alloc_mchbar_resource(struct drm_device *dev)
384{
fac5e23e 385 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 386 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
387 u32 temp_lo, temp_hi = 0;
388 u64 mchbar_addr;
389 int ret;
390
391 if (INTEL_INFO(dev)->gen >= 4)
392 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
393 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
394 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
395
396 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
397#ifdef CONFIG_PNP
398 if (mchbar_addr &&
399 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
400 return 0;
401#endif
402
403 /* Get some space for it */
404 dev_priv->mch_res.name = "i915 MCHBAR";
405 dev_priv->mch_res.flags = IORESOURCE_MEM;
406 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
407 &dev_priv->mch_res,
408 MCHBAR_SIZE, MCHBAR_SIZE,
409 PCIBIOS_MIN_MEM,
410 0, pcibios_align_resource,
411 dev_priv->bridge_dev);
412 if (ret) {
413 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
414 dev_priv->mch_res.start = 0;
415 return ret;
416 }
417
418 if (INTEL_INFO(dev)->gen >= 4)
419 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
420 upper_32_bits(dev_priv->mch_res.start));
421
422 pci_write_config_dword(dev_priv->bridge_dev, reg,
423 lower_32_bits(dev_priv->mch_res.start));
424 return 0;
425}
426
427/* Setup MCHBAR if possible, return true if we should disable it again */
428static void
429intel_setup_mchbar(struct drm_device *dev)
430{
fac5e23e 431 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 432 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
433 u32 temp;
434 bool enabled;
435
436 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
437 return;
438
439 dev_priv->mchbar_need_disable = false;
440
441 if (IS_I915G(dev) || IS_I915GM(dev)) {
442 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
443 enabled = !!(temp & DEVEN_MCHBAR_EN);
444 } else {
445 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
446 enabled = temp & 1;
447 }
448
449 /* If it's already enabled, don't have to do anything */
450 if (enabled)
451 return;
452
453 if (intel_alloc_mchbar_resource(dev))
454 return;
455
456 dev_priv->mchbar_need_disable = true;
457
458 /* Space is allocated or reserved, so enable it. */
459 if (IS_I915G(dev) || IS_I915GM(dev)) {
460 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
461 temp | DEVEN_MCHBAR_EN);
462 } else {
463 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
464 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
465 }
466}
467
468static void
469intel_teardown_mchbar(struct drm_device *dev)
470{
fac5e23e 471 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 472 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
473
474 if (dev_priv->mchbar_need_disable) {
475 if (IS_I915G(dev) || IS_I915GM(dev)) {
476 u32 deven_val;
477
478 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
479 &deven_val);
480 deven_val &= ~DEVEN_MCHBAR_EN;
481 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
482 deven_val);
483 } else {
484 u32 mchbar_val;
485
486 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
487 &mchbar_val);
488 mchbar_val &= ~1;
489 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
490 mchbar_val);
491 }
492 }
493
494 if (dev_priv->mch_res.start)
495 release_resource(&dev_priv->mch_res);
496}
497
498/* true = enable decode, false = disable decoder */
499static unsigned int i915_vga_set_decode(void *cookie, bool state)
500{
501 struct drm_device *dev = cookie;
502
503 intel_modeset_vga_set_state(dev, state);
504 if (state)
505 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
506 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
507 else
508 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
509}
510
511static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
512{
513 struct drm_device *dev = pci_get_drvdata(pdev);
514 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
515
516 if (state == VGA_SWITCHEROO_ON) {
517 pr_info("switched on\n");
518 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
519 /* i915 resume handler doesn't set to D0 */
52a05c30 520 pci_set_power_state(pdev, PCI_D0);
0673ad47
CW		 521 i915_resume_switcheroo(dev);
522 dev->switch_power_state = DRM_SWITCH_POWER_ON;
523 } else {
524 pr_info("switched off\n");
525 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
526 i915_suspend_switcheroo(dev, pmm);
527 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
528 }
529}
530
531static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
532{
533 struct drm_device *dev = pci_get_drvdata(pdev);
534
535 /*
536 * FIXME: open_count is protected by drm_global_mutex but that would lead to
537 * locking inversion with the driver load path. And the access here is
538 * completely racy anyway. So don't bother with locking for now.
539 */
540 return dev->open_count == 0;
541}
542
543static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
544 .set_gpu_state = i915_switcheroo_set_state,
545 .reprobe = NULL,
546 .can_switch = i915_switcheroo_can_switch,
547};
548
549static void i915_gem_fini(struct drm_device *dev)
550{
551 struct drm_i915_private *dev_priv = to_i915(dev);
552
553 /*
554 * Neither the BIOS, ourselves or any other kernel
555 * expects the system to be in execlists mode on startup,
556 * so we need to reset the GPU back to legacy mode. And the only
557 * known way to disable logical contexts is through a GPU reset.
558 *
559 * So in order to leave the system in a known default configuration,
560 * always reset the GPU upon unload. Afterwards we then clean up the
561 * GEM state tracking, flushing off the requests and leaving the
562 * system in a known idle state.
563 *
564 * Note that is of the upmost importance that the GPU is idle and
565 * all stray writes are flushed *before* we dismantle the backing
566 * storage for the pinned objects.
567 *
568 * However, since we are uncertain that reseting the GPU on older
569 * machines is a good idea, we don't - just in case it leaves the
570 * machine in an unusable condition.
571 */
572 if (HAS_HW_CONTEXTS(dev)) {
573 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
574 WARN_ON(reset && reset != -ENODEV);
575 }
576
577 mutex_lock(&dev->struct_mutex);
578 i915_gem_reset(dev);
579 i915_gem_cleanup_engines(dev);
580 i915_gem_context_fini(dev);
581 mutex_unlock(&dev->struct_mutex);
582
583 WARN_ON(!list_empty(&to_i915(dev)->context_list));
584}
585
586static int i915_load_modeset_init(struct drm_device *dev)
587{
fac5e23e 588 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 589 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 590 int ret;
591
592 if (i915_inject_load_failure())
593 return -ENODEV;
594
595 ret = intel_bios_init(dev_priv);
596 if (ret)
597 DRM_INFO("failed to find VBIOS tables\n");
598
599 /* If we have > 1 VGA cards, then we need to arbitrate access
600 * to the common VGA resources.
601 *
602 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
603 * then we do not take part in VGA arbitration and the
604 * vga_client_register() fails with -ENODEV.
605 */
52a05c30 606 ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
0673ad47
CW		 607 if (ret && ret != -ENODEV)
608 goto out;
609
610 intel_register_dsm_handler();
611
52a05c30 612 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
0673ad47
CW		 613 if (ret)
614 goto cleanup_vga_client;
615
616 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
617 intel_update_rawclk(dev_priv);
618
619 intel_power_domains_init_hw(dev_priv, false);
620
621 intel_csr_ucode_init(dev_priv);
622
623 ret = intel_irq_install(dev_priv);
624 if (ret)
625 goto cleanup_csr;
626
627 intel_setup_gmbus(dev);
628
629 /* Important: The output setup functions called by modeset_init need
630 * working irqs for e.g. gmbus and dp aux transfers. */
631 intel_modeset_init(dev);
632
633 intel_guc_init(dev);
634
635 ret = i915_gem_init(dev);
636 if (ret)
637 goto cleanup_irq;
638
639 intel_modeset_gem_init(dev);
640
641 if (INTEL_INFO(dev)->num_pipes == 0)
642 return 0;
643
644 ret = intel_fbdev_init(dev);
645 if (ret)
646 goto cleanup_gem;
647
648 /* Only enable hotplug handling once the fbdev is fully set up. */
649 intel_hpd_init(dev_priv);
650
651 drm_kms_helper_poll_init(dev);
652
653 return 0;
654
655cleanup_gem:
656 i915_gem_fini(dev);
657cleanup_irq:
658 intel_guc_fini(dev);
659 drm_irq_uninstall(dev);
660 intel_teardown_gmbus(dev);
661cleanup_csr:
662 intel_csr_ucode_fini(dev_priv);
663 intel_power_domains_fini(dev_priv);
52a05c30 664 vga_switcheroo_unregister_client(pdev);
0673ad47 665cleanup_vga_client:
52a05c30 666 vga_client_register(pdev, NULL, NULL, NULL);
0673ad47
CW		 667out:
668 return ret;
669}
670
671#if IS_ENABLED(CONFIG_FB)
672static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
673{
674 struct apertures_struct *ap;
91c8a326 675 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 676 struct i915_ggtt *ggtt = &dev_priv->ggtt;
677 bool primary;
678 int ret;
679
680 ap = alloc_apertures(1);
681 if (!ap)
682 return -ENOMEM;
683
684 ap->ranges[0].base = ggtt->mappable_base;
685 ap->ranges[0].size = ggtt->mappable_end;
686
687 primary =
688 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
689
44adece5 690 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
0673ad47
CW		 691
692 kfree(ap);
693
694 return ret;
695}
696#else
697static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
698{
699 return 0;
700}
701#endif
702
703#if !defined(CONFIG_VGA_CONSOLE)
704static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
705{
706 return 0;
707}
708#elif !defined(CONFIG_DUMMY_CONSOLE)
709static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
710{
711 return -ENODEV;
712}
713#else
714static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
715{
716 int ret = 0;
717
718 DRM_INFO("Replacing VGA console driver\n");
719
720 console_lock();
721 if (con_is_bound(&vga_con))
722 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
723 if (ret == 0) {
724 ret = do_unregister_con_driver(&vga_con);
725
726 /* Ignore "already unregistered". */
727 if (ret == -ENODEV)
728 ret = 0;
729 }
730 console_unlock();
731
732 return ret;
733}
734#endif
735
0673ad47
CW		 736static void intel_init_dpio(struct drm_i915_private *dev_priv)
737{
738 /*
739 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
740 * CHV x1 PHY (DP/HDMI D)
741 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
742 */
743 if (IS_CHERRYVIEW(dev_priv)) {
744 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
745 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
746 } else if (IS_VALLEYVIEW(dev_priv)) {
747 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
748 }
749}
750
751static int i915_workqueues_init(struct drm_i915_private *dev_priv)
752{
753 /*
754 * The i915 workqueue is primarily used for batched retirement of
755 * requests (and thus managing bo) once the task has been completed
756 * by the GPU. i915_gem_retire_requests() is called directly when we
757 * need high-priority retirement, such as waiting for an explicit
758 * bo.
759 *
760 * It is also used for periodic low-priority events, such as
761 * idle-timers and recording error state.
762 *
763 * All tasks on the workqueue are expected to acquire the dev mutex
764 * so there is no point in running more than one instance of the
765 * workqueue at any time. Use an ordered one.
766 */
767 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
768 if (dev_priv->wq == NULL)
769 goto out_err;
770
771 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
772 if (dev_priv->hotplug.dp_wq == NULL)
773 goto out_free_wq;
774
0673ad47
CW		 775 return 0;
776
0673ad47
CW		 777out_free_wq:
778 destroy_workqueue(dev_priv->wq);
779out_err:
780 DRM_ERROR("Failed to allocate workqueues.\n");
781
782 return -ENOMEM;
783}
784
785static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
786{
0673ad47
CW		 787 destroy_workqueue(dev_priv->hotplug.dp_wq);
788 destroy_workqueue(dev_priv->wq);
789}
790
791/**
792 * i915_driver_init_early - setup state not requiring device access
793 * @dev_priv: device private
794 *
795 * Initialize everything that is a "SW-only" state, that is state not
796 * requiring accessing the device or exposing the driver via kernel internal
797 * or userspace interfaces. Example steps belonging here: lock initialization,
798 * system memory allocation, setting up device specific attributes and
799 * function hooks not requiring accessing the device.
800 */
801static int i915_driver_init_early(struct drm_i915_private *dev_priv,
802 const struct pci_device_id *ent)
803{
804 const struct intel_device_info *match_info =
805 (struct intel_device_info *)ent->driver_data;
806 struct intel_device_info *device_info;
807 int ret = 0;
808
809 if (i915_inject_load_failure())
810 return -ENODEV;
811
812 /* Setup the write-once "constant" device info */
94b4f3ba 813 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 814 memcpy(device_info, match_info, sizeof(*device_info));
815 device_info->device_id = dev_priv->drm.pdev->device;
816
817 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
818 device_info->gen_mask = BIT(device_info->gen - 1);
819
820 spin_lock_init(&dev_priv->irq_lock);
821 spin_lock_init(&dev_priv->gpu_error.lock);
822 mutex_init(&dev_priv->backlight_lock);
823 spin_lock_init(&dev_priv->uncore.lock);
824 spin_lock_init(&dev_priv->mm.object_stat_lock);
825 spin_lock_init(&dev_priv->mmio_flip_lock);
826 mutex_init(&dev_priv->sb_lock);
827 mutex_init(&dev_priv->modeset_restore_lock);
828 mutex_init(&dev_priv->av_mutex);
829 mutex_init(&dev_priv->wm.wm_mutex);
830 mutex_init(&dev_priv->pps_mutex);
831
0b1de5d5
CW		 832 i915_memcpy_init_early(dev_priv);
833
0673ad47
CW		 834 ret = i915_workqueues_init(dev_priv);
835 if (ret < 0)
836 return ret;
837
838 ret = intel_gvt_init(dev_priv);
839 if (ret < 0)
840 goto err_workqueues;
841
842 /* This must be called before any calls to HAS_PCH_* */
843 intel_detect_pch(&dev_priv->drm);
844
845 intel_pm_setup(&dev_priv->drm);
846 intel_init_dpio(dev_priv);
847 intel_power_domains_init(dev_priv);
848 intel_irq_init(dev_priv);
849 intel_init_display_hooks(dev_priv);
850 intel_init_clock_gating_hooks(dev_priv);
851 intel_init_audio_hooks(dev_priv);
852 i915_gem_load_init(&dev_priv->drm);
853
36cdd013 854 intel_display_crc_init(dev_priv);
0673ad47 855
94b4f3ba 856 intel_device_info_dump(dev_priv);
0673ad47
CW		 857
858 /* Not all pre-production machines fall into this category, only the
859 * very first ones. Almost everything should work, except for maybe
860 * suspend/resume. And we don't implement workarounds that affect only
861 * pre-production machines. */
862 if (IS_HSW_EARLY_SDV(dev_priv))
863 DRM_INFO("This is an early pre-production Haswell machine. "
864 "It may not be fully functional.\n");
865
866 return 0;
867
868err_workqueues:
869 i915_workqueues_cleanup(dev_priv);
870 return ret;
871}
872
873/**
874 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
875 * @dev_priv: device private
876 */
877static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
878{
91c8a326 879 i915_gem_load_cleanup(&dev_priv->drm);
0673ad47
CW		 880 i915_workqueues_cleanup(dev_priv);
881}
882
883static int i915_mmio_setup(struct drm_device *dev)
884{
885 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 886 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 887 int mmio_bar;
888 int mmio_size;
889
890 mmio_bar = IS_GEN2(dev) ? 1 : 0;
891 /*
892 * Before gen4, the registers and the GTT are behind different BARs.
893 * However, from gen4 onwards, the registers and the GTT are shared
894 * in the same BAR, so we want to restrict this ioremap from
895 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
896 * the register BAR remains the same size for all the earlier
897 * generations up to Ironlake.
898 */
899 if (INTEL_INFO(dev)->gen < 5)
900 mmio_size = 512 * 1024;
901 else
902 mmio_size = 2 * 1024 * 1024;
52a05c30 903 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
0673ad47
CW		 904 if (dev_priv->regs == NULL) {
905 DRM_ERROR("failed to map registers\n");
906
907 return -EIO;
908 }
909
910 /* Try to make sure MCHBAR is enabled before poking at it */
911 intel_setup_mchbar(dev);
912
913 return 0;
914}
915
916static void i915_mmio_cleanup(struct drm_device *dev)
917{
918 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 919 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 920
921 intel_teardown_mchbar(dev);
52a05c30 922 pci_iounmap(pdev, dev_priv->regs);
0673ad47
CW		 923}
924
925/**
926 * i915_driver_init_mmio - setup device MMIO
927 * @dev_priv: device private
928 *
929 * Setup minimal device state necessary for MMIO accesses later in the
930 * initialization sequence. The setup here should avoid any other device-wide
931 * side effects or exposing the driver via kernel internal or user space
932 * interfaces.
933 */
934static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
935{
91c8a326 936 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 937 int ret;
938
939 if (i915_inject_load_failure())
940 return -ENODEV;
941
942 if (i915_get_bridge_dev(dev))
943 return -EIO;
944
945 ret = i915_mmio_setup(dev);
946 if (ret < 0)
947 goto put_bridge;
948
949 intel_uncore_init(dev_priv);
950
951 return 0;
952
953put_bridge:
954 pci_dev_put(dev_priv->bridge_dev);
955
956 return ret;
957}
958
959/**
960 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
961 * @dev_priv: device private
962 */
963static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
964{
91c8a326 965 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 966
967 intel_uncore_fini(dev_priv);
968 i915_mmio_cleanup(dev);
969 pci_dev_put(dev_priv->bridge_dev);
970}
971
94b4f3ba
CW		 972static void intel_sanitize_options(struct drm_i915_private *dev_priv)
973{
974 i915.enable_execlists =
975 intel_sanitize_enable_execlists(dev_priv,
976 i915.enable_execlists);
977
978 /*
979 * i915.enable_ppgtt is read-only, so do an early pass to validate the
980 * user's requested state against the hardware/driver capabilities. We
981 * do this now so that we can print out any log messages once rather
982 * than every time we check intel_enable_ppgtt().
983 */
984 i915.enable_ppgtt =
985 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
986 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
39df9190
CW		 987
988 i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
989 DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
94b4f3ba
CW		 990}
991
0673ad47
CW		 992/**
993 * i915_driver_init_hw - setup state requiring device access
994 * @dev_priv: device private
995 *
996 * Setup state that requires accessing the device, but doesn't require
997 * exposing the driver via kernel internal or userspace interfaces.
998 */
999static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1000{
52a05c30 1001 struct pci_dev *pdev = dev_priv->drm.pdev;
91c8a326 1002 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1003 int ret;
1004
1005 if (i915_inject_load_failure())
1006 return -ENODEV;
1007
94b4f3ba
CW		 1008 intel_device_info_runtime_init(dev_priv);
1009
1010 intel_sanitize_options(dev_priv);
0673ad47 1011
97d6d7ab 1012 ret = i915_ggtt_probe_hw(dev_priv);
0673ad47
CW		 1013 if (ret)
1014 return ret;
1015
0673ad47
CW		 1016 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1017 * otherwise the vga fbdev driver falls over. */
1018 ret = i915_kick_out_firmware_fb(dev_priv);
1019 if (ret) {
1020 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1021 goto out_ggtt;
1022 }
1023
1024 ret = i915_kick_out_vgacon(dev_priv);
1025 if (ret) {
1026 DRM_ERROR("failed to remove conflicting VGA console\n");
1027 goto out_ggtt;
1028 }
1029
97d6d7ab 1030 ret = i915_ggtt_init_hw(dev_priv);
0088e522
CW		 1031 if (ret)
1032 return ret;
1033
97d6d7ab 1034 ret = i915_ggtt_enable_hw(dev_priv);
0088e522
CW		 1035 if (ret) {
1036 DRM_ERROR("failed to enable GGTT\n");
1037 goto out_ggtt;
1038 }
1039
52a05c30 1040 pci_set_master(pdev);
0673ad47
CW		 1041
1042 /* overlay on gen2 is broken and can't address above 1G */
1043 if (IS_GEN2(dev)) {
52a05c30 1044 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
0673ad47
CW		 1045 if (ret) {
1046 DRM_ERROR("failed to set DMA mask\n");
1047
1048 goto out_ggtt;
1049 }
1050 }
1051
0673ad47
CW		 1052 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1053 * using 32bit addressing, overwriting memory if HWS is located
1054 * above 4GB.
1055 *
1056 * The documentation also mentions an issue with undefined
1057 * behaviour if any general state is accessed within a page above 4GB,
1058 * which also needs to be handled carefully.
1059 */
1060 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
52a05c30 1061 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0673ad47
CW		 1062
1063 if (ret) {
1064 DRM_ERROR("failed to set DMA mask\n");
1065
1066 goto out_ggtt;
1067 }
1068 }
1069
0673ad47
CW		 1070 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1071 PM_QOS_DEFAULT_VALUE);
1072
1073 intel_uncore_sanitize(dev_priv);
1074
1075 intel_opregion_setup(dev_priv);
1076
1077 i915_gem_load_init_fences(dev_priv);
1078
1079 /* On the 945G/GM, the chipset reports the MSI capability on the
1080 * integrated graphics even though the support isn't actually there
1081 * according to the published specs. It doesn't appear to function
1082 * correctly in testing on 945G.
1083 * This may be a side effect of MSI having been made available for PEG
1084 * and the registers being closely associated.
1085 *
1086 * According to chipset errata, on the 965GM, MSI interrupts may
1087 * be lost or delayed, but we use them anyways to avoid
1088 * stuck interrupts on some machines.
1089 */
1090 if (!IS_I945G(dev) && !IS_I945GM(dev)) {
52a05c30 1091 if (pci_enable_msi(pdev) < 0)
0673ad47
CW		 1092 DRM_DEBUG_DRIVER("can't enable MSI");
1093 }
1094
1095 return 0;
1096
1097out_ggtt:
97d6d7ab 1098 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1099
1100 return ret;
1101}
1102
1103/**
1104 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1105 * @dev_priv: device private
1106 */
1107static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1108{
52a05c30 1109 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 1110
52a05c30
DW		 1111 if (pdev->msi_enabled)
1112 pci_disable_msi(pdev);
0673ad47
CW		 1113
1114 pm_qos_remove_request(&dev_priv->pm_qos);
97d6d7ab 1115 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1116}
1117
1118/**
1119 * i915_driver_register - register the driver with the rest of the system
1120 * @dev_priv: device private
1121 *
1122 * Perform any steps necessary to make the driver available via kernel
1123 * internal or userspace interfaces.
1124 */
1125static void i915_driver_register(struct drm_i915_private *dev_priv)
1126{
91c8a326 1127 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1128
1129 i915_gem_shrinker_init(dev_priv);
1130
1131 /*
1132 * Notify a valid surface after modesetting,
1133 * when running inside a VM.
1134 */
1135 if (intel_vgpu_active(dev_priv))
1136 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1137
1138 /* Reveal our presence to userspace */
1139 if (drm_dev_register(dev, 0) == 0) {
1140 i915_debugfs_register(dev_priv);
694c2828 1141 i915_setup_sysfs(dev_priv);
0673ad47
CW		 1142 } else
1143 DRM_ERROR("Failed to register driver for userspace access!\n");
1144
1145 if (INTEL_INFO(dev_priv)->num_pipes) {
1146 /* Must be done after probing outputs */
1147 intel_opregion_register(dev_priv);
1148 acpi_video_register();
1149 }
1150
1151 if (IS_GEN5(dev_priv))
1152 intel_gpu_ips_init(dev_priv);
1153
1154 i915_audio_component_init(dev_priv);
1155
1156 /*
1157 * Some ports require correctly set-up hpd registers for detection to
1158 * work properly (leading to ghost connected connector status), e.g. VGA
1159 * on gm45. Hence we can only set up the initial fbdev config after hpd
1160 * irqs are fully enabled. We do it last so that the async config
1161 * cannot run before the connectors are registered.
1162 */
1163 intel_fbdev_initial_config_async(dev);
1164}
1165
1166/**
1167 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1168 * @dev_priv: device private
1169 */
1170static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1171{
1172 i915_audio_component_cleanup(dev_priv);
1173
1174 intel_gpu_ips_teardown();
1175 acpi_video_unregister();
1176 intel_opregion_unregister(dev_priv);
1177
694c2828 1178 i915_teardown_sysfs(dev_priv);
0673ad47 1179 i915_debugfs_unregister(dev_priv);
91c8a326 1180 drm_dev_unregister(&dev_priv->drm);
0673ad47
CW		 1181
1182 i915_gem_shrinker_cleanup(dev_priv);
1183}
1184
1185/**
1186 * i915_driver_load - setup chip and create an initial config
1187 * @dev: DRM device
1188 * @flags: startup flags
1189 *
1190 * The driver load routine has to do several things:
1191 * - drive output discovery via intel_modeset_init()
1192 * - initialize the memory manager
1193 * - allocate initial config memory
1194 * - setup the DRM framebuffer with the allocated memory
1195 */
42f5551d 1196int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47
CW		 1197{
1198 struct drm_i915_private *dev_priv;
1199 int ret;
7d87a7f7 1200
a09d0ba1
CW		 1201 if (i915.nuclear_pageflip)
1202 driver.driver_features |= DRIVER_ATOMIC;
1203
0673ad47
CW		 1204 ret = -ENOMEM;
1205 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1206 if (dev_priv)
1207 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1208 if (ret) {
1209 dev_printk(KERN_ERR, &pdev->dev,
1210 "[" DRM_NAME ":%s] allocation failed\n", __func__);
1211 kfree(dev_priv);
1212 return ret;
1213 }
72bbf0af 1214
0673ad47
CW		 1215 dev_priv->drm.pdev = pdev;
1216 dev_priv->drm.dev_private = dev_priv;
719388e1 1217
0673ad47
CW		 1218 ret = pci_enable_device(pdev);
1219 if (ret)
1220 goto out_free_priv;
1347f5b4 1221
0673ad47 1222 pci_set_drvdata(pdev, &dev_priv->drm);
ef11bdb3 1223
0673ad47
CW		 1224 ret = i915_driver_init_early(dev_priv, ent);
1225 if (ret < 0)
1226 goto out_pci_disable;
ef11bdb3 1227
0673ad47 1228 intel_runtime_pm_get(dev_priv);
1da177e4 1229
0673ad47
CW		 1230 ret = i915_driver_init_mmio(dev_priv);
1231 if (ret < 0)
1232 goto out_runtime_pm_put;
79e53945 1233
0673ad47
CW		 1234 ret = i915_driver_init_hw(dev_priv);
1235 if (ret < 0)
1236 goto out_cleanup_mmio;
30c964a6
RB		 1237
1238 /*
0673ad47
CW		 1239 * TODO: move the vblank init and parts of modeset init steps into one
1240 * of the i915_driver_init_/i915_driver_register functions according
1241 * to the role/effect of the given init step.
30c964a6 1242 */
0673ad47 1243 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1244 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1245 INTEL_INFO(dev_priv)->num_pipes);
1246 if (ret)
1247 goto out_cleanup_hw;
30c964a6
RB		 1248 }
1249
91c8a326 1250 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47
CW		 1251 if (ret < 0)
1252 goto out_cleanup_vblank;
1253
1254 i915_driver_register(dev_priv);
1255
1256 intel_runtime_pm_enable(dev_priv);
1257
1258 intel_runtime_pm_put(dev_priv);
1259
1260 return 0;
1261
1262out_cleanup_vblank:
91c8a326 1263 drm_vblank_cleanup(&dev_priv->drm);
0673ad47
CW		 1264out_cleanup_hw:
1265 i915_driver_cleanup_hw(dev_priv);
1266out_cleanup_mmio:
1267 i915_driver_cleanup_mmio(dev_priv);
1268out_runtime_pm_put:
1269 intel_runtime_pm_put(dev_priv);
1270 i915_driver_cleanup_early(dev_priv);
1271out_pci_disable:
1272 pci_disable_device(pdev);
1273out_free_priv:
1274 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1275 drm_dev_unref(&dev_priv->drm);
30c964a6
RB		 1276 return ret;
1277}
1278
42f5551d 1279void i915_driver_unload(struct drm_device *dev)
3bad0781 1280{
fac5e23e 1281 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1282 struct pci_dev *pdev = dev_priv->drm.pdev;
3bad0781 1283
0673ad47
CW		 1284 intel_fbdev_fini(dev);
1285
42f5551d
CW		 1286 if (i915_gem_suspend(dev))
1287 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1288
0673ad47
CW		 1289 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1290
1291 i915_driver_unregister(dev_priv);
1292
1293 drm_vblank_cleanup(dev);
1294
1295 intel_modeset_cleanup(dev);
1296
3bad0781 1297 /*
0673ad47
CW		 1298 * free the memory space allocated for the child device
1299 * config parsed from VBT
3bad0781 1300 */
0673ad47
CW		 1301 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1302 kfree(dev_priv->vbt.child_dev);
1303 dev_priv->vbt.child_dev = NULL;
1304 dev_priv->vbt.child_dev_num = 0;
1305 }
1306 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1307 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1308 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1309 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1310
52a05c30
DW		 1311 vga_switcheroo_unregister_client(pdev);
1312 vga_client_register(pdev, NULL, NULL, NULL);
bcdb72ac 1313
0673ad47 1314 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1315
0673ad47
CW		 1316 /* Free error state after interrupts are fully disabled. */
1317 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1318 i915_destroy_error_state(dev);
1319
1320 /* Flush any outstanding unpin_work. */
b7137e0c 1321 drain_workqueue(dev_priv->wq);
0673ad47
CW		 1322
1323 intel_guc_fini(dev);
1324 i915_gem_fini(dev);
1325 intel_fbc_cleanup_cfb(dev_priv);
1326
1327 intel_power_domains_fini(dev_priv);
1328
1329 i915_driver_cleanup_hw(dev_priv);
1330 i915_driver_cleanup_mmio(dev_priv);
1331
1332 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1333
1334 i915_driver_cleanup_early(dev_priv);
3bad0781
ZW		 1335}
1336
0673ad47 1337static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1338{
0673ad47 1339 int ret;
2911a35b 1340
0673ad47
CW		 1341 ret = i915_gem_open(dev, file);
1342 if (ret)
1343 return ret;
2911a35b 1344
0673ad47
CW		 1345 return 0;
1346}
71386ef9 1347
0673ad47
CW		 1348/**
1349 * i915_driver_lastclose - clean up after all DRM clients have exited
1350 * @dev: DRM device
1351 *
1352 * Take care of cleaning up after all DRM clients have exited. In the
1353 * mode setting case, we want to restore the kernel's initial mode (just
1354 * in case the last client left us in a bad state).
1355 *
1356 * Additionally, in the non-mode setting case, we'll tear down the GTT
1357 * and DMA structures, since the kernel won't be using them, and clea
1358 * up any GEM state.
1359 */
1360static void i915_driver_lastclose(struct drm_device *dev)
1361{
1362 intel_fbdev_restore_mode(dev);
1363 vga_switcheroo_process_delayed_switch();
1364}
2911a35b 1365
0673ad47
CW		 1366static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1367{
1368 mutex_lock(&dev->struct_mutex);
1369 i915_gem_context_close(dev, file);
1370 i915_gem_release(dev, file);
1371 mutex_unlock(&dev->struct_mutex);
1372}
1373
1374static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1375{
1376 struct drm_i915_file_private *file_priv = file->driver_priv;
1377
1378 kfree(file_priv);
2911a35b
BW		 1379}
1380
07f9cd0b
ID		 1381static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1382{
91c8a326 1383 struct drm_device *dev = &dev_priv->drm;
19c8054c 1384 struct intel_encoder *encoder;
07f9cd0b
ID		 1385
1386 drm_modeset_lock_all(dev);
19c8054c
JN		 1387 for_each_intel_encoder(dev, encoder)
1388 if (encoder->suspend)
1389 encoder->suspend(encoder);
07f9cd0b
ID		 1390 drm_modeset_unlock_all(dev);
1391}
1392
1a5df187
PZ		 1393static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1394 bool rpm_resume);
507e126e 1395static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1396
bc87229f
ID		 1397static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1398{
1399#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1400 if (acpi_target_system_state() < ACPI_STATE_S3)
1401 return true;
1402#endif
1403 return false;
1404}
ebc32824 1405
5e365c39 1406static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1407{
fac5e23e 1408 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1409 struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3a 1410 pci_power_t opregion_target_state;
d5818938 1411 int error;
61caf87c 1412
b8efb17b
ZR		 1413 /* ignore lid events during suspend */
1414 mutex_lock(&dev_priv->modeset_restore_lock);
1415 dev_priv->modeset_restore = MODESET_SUSPENDED;
1416 mutex_unlock(&dev_priv->modeset_restore_lock);
1417
1f814dac
ID		 1418 disable_rpm_wakeref_asserts(dev_priv);
1419
c67a470b
PZ		 1420 /* We do a lot of poking in a lot of registers, make sure they work
1421 * properly. */
da7e29bd 1422 intel_display_set_init_power(dev_priv, true);
cb10799c 1423
5bcf719b
DA		 1424 drm_kms_helper_poll_disable(dev);
1425
52a05c30 1426 pci_save_state(pdev);
ba8bbcf6 1427
d5818938
DV		 1428 error = i915_gem_suspend(dev);
1429 if (error) {
52a05c30 1430 dev_err(&pdev->dev,
d5818938 1431 "GEM idle failed, resume might fail\n");
1f814dac 1432 goto out;
d5818938 1433 }
db1b76ca 1434
a1c41994
AD		 1435 intel_guc_suspend(dev);
1436
6b72d486 1437 intel_display_suspend(dev);
2eb5252e 1438
d5818938 1439 intel_dp_mst_suspend(dev);
7d708ee4 1440
d5818938
DV		 1441 intel_runtime_pm_disable_interrupts(dev_priv);
1442 intel_hpd_cancel_work(dev_priv);
09b64267 1443
d5818938 1444 intel_suspend_encoders(dev_priv);
0e32b39c 1445
d5818938 1446 intel_suspend_hw(dev);
5669fcac 1447
828c7908
BW		 1448 i915_gem_suspend_gtt_mappings(dev);
1449
9e06dd39
JB		 1450 i915_save_state(dev);
1451
bc87229f 1452 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1453 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1454
dc97997a 1455 intel_uncore_forcewake_reset(dev_priv, false);
03d92e47 1456 intel_opregion_unregister(dev_priv);
8ee1c3db 1457
82e3b8c1 1458 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1459
62d5d69b
MK		 1460 dev_priv->suspend_count++;
1461
85e90679
KCA		 1462 intel_display_set_init_power(dev_priv, false);
1463
f74ed08d 1464 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1465
1f814dac
ID		 1466out:
1467 enable_rpm_wakeref_asserts(dev_priv);
1468
1469 return error;
84b79f8d
RW		 1470}
1471
c49d13ee 1472static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
c3c09c95 1473{
c49d13ee 1474 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1475 struct pci_dev *pdev = dev_priv->drm.pdev;
bc87229f 1476 bool fw_csr;
c3c09c95
ID		 1477 int ret;
1478
1f814dac
ID		 1479 disable_rpm_wakeref_asserts(dev_priv);
1480
a7c8125f
ID		 1481 fw_csr = !IS_BROXTON(dev_priv) &&
1482 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1483 /*
1484 * In case of firmware assisted context save/restore don't manually
1485 * deinit the power domains. This also means the CSR/DMC firmware will
1486 * stay active, it will power down any HW resources as required and
1487 * also enable deeper system power states that would be blocked if the
1488 * firmware was inactive.
1489 */
1490 if (!fw_csr)
1491 intel_power_domains_suspend(dev_priv);
73dfc227 1492
507e126e 1493 ret = 0;
b8aea3d1 1494 if (IS_BROXTON(dev_priv))
507e126e 1495 bxt_enable_dc9(dev_priv);
b8aea3d1 1496 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1497 hsw_enable_pc8(dev_priv);
1498 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1499 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1500
1501 if (ret) {
1502 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1503 if (!fw_csr)
1504 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1505
1f814dac 1506 goto out;
c3c09c95
ID		 1507 }
1508
52a05c30 1509 pci_disable_device(pdev);
ab3be73f 1510 /*
54875571 1511 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1512 * the device even though it's already in D3 and hang the machine. So
1513 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1514 * power down the device properly. The issue was seen on multiple old
1515 * GENs with different BIOS vendors, so having an explicit blacklist
1516 * is inpractical; apply the workaround on everything pre GEN6. The
1517 * platforms where the issue was seen:
1518 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1519 * Fujitsu FSC S7110
1520 * Acer Aspire 1830T
ab3be73f 1521 */
54875571 1522 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
52a05c30 1523 pci_set_power_state(pdev, PCI_D3hot);
c3c09c95 1524
bc87229f
ID		 1525 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1526
1f814dac
ID		 1527out:
1528 enable_rpm_wakeref_asserts(dev_priv);
1529
1530 return ret;
c3c09c95
ID		 1531}
1532
1751fcf9 1533int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1534{
1535 int error;
1536
ded8b07d 1537 if (!dev) {
84b79f8d
RW		 1538 DRM_ERROR("dev: %p\n", dev);
1539 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1540 return -ENODEV;
1541 }
1542
0b14cbd2
ID		 1543 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1544 state.event != PM_EVENT_FREEZE))
1545 return -EINVAL;
5bcf719b
DA		 1546
1547 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1548 return 0;
6eecba33 1549
5e365c39 1550 error = i915_drm_suspend(dev);
84b79f8d
RW		 1551 if (error)
1552 return error;
1553
ab3be73f 1554 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1555}
1556
5e365c39 1557static int i915_drm_resume(struct drm_device *dev)
76c4b250 1558{
fac5e23e 1559 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1560 int ret;
9d49c0ef 1561
1f814dac 1562 disable_rpm_wakeref_asserts(dev_priv);
abc80abd 1563 intel_sanitize_gt_powersave(dev_priv);
1f814dac 1564
97d6d7ab 1565 ret = i915_ggtt_enable_hw(dev_priv);
ac840ae5
VS		 1566 if (ret)
1567 DRM_ERROR("failed to re-enable GGTT\n");
1568
f74ed08d
ID		 1569 intel_csr_ucode_resume(dev_priv);
1570
5ab57c70 1571 i915_gem_resume(dev);
9d49c0ef 1572
61caf87c 1573 i915_restore_state(dev);
8090ba8c 1574 intel_pps_unlock_regs_wa(dev_priv);
6f9f4b7a 1575 intel_opregion_setup(dev_priv);
61caf87c 1576
d5818938
DV		 1577 intel_init_pch_refclk(dev);
1578 drm_mode_config_reset(dev);
1833b134 1579
364aece0
PA		 1580 /*
1581 * Interrupts have to be enabled before any batches are run. If not the
1582 * GPU will hang. i915_gem_init_hw() will initiate batches to
1583 * update/restore the context.
1584 *
1585 * Modeset enabling in intel_modeset_init_hw() also needs working
1586 * interrupts.
1587 */
1588 intel_runtime_pm_enable_interrupts(dev_priv);
1589
d5818938
DV		 1590 mutex_lock(&dev->struct_mutex);
1591 if (i915_gem_init_hw(dev)) {
1592 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
338d0eea 1593 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
d5818938
DV		 1594 }
1595 mutex_unlock(&dev->struct_mutex);
226485e9 1596
a1c41994
AD		 1597 intel_guc_resume(dev);
1598
d5818938 1599 intel_modeset_init_hw(dev);
24576d23 1600
d5818938
DV		 1601 spin_lock_irq(&dev_priv->irq_lock);
1602 if (dev_priv->display.hpd_irq_setup)
91d14251 1603 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1604 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1605
d5818938 1606 intel_dp_mst_resume(dev);
e7d6f7d7 1607
a16b7658
L		 1608 intel_display_resume(dev);
1609
d5818938
DV		 1610 /*
1611 * ... but also need to make sure that hotplug processing
1612 * doesn't cause havoc. Like in the driver load code we don't
1613 * bother with the tiny race here where we might loose hotplug
1614 * notifications.
1615 * */
1616 intel_hpd_init(dev_priv);
1617 /* Config may have changed between suspend and resume */
1618 drm_helper_hpd_irq_event(dev);
1daed3fb 1619
03d92e47 1620 intel_opregion_register(dev_priv);
44834a67 1621
82e3b8c1 1622 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1623
b8efb17b
ZR		 1624 mutex_lock(&dev_priv->modeset_restore_lock);
1625 dev_priv->modeset_restore = MODESET_DONE;
1626 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1627
6f9f4b7a 1628 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1629
54b4f68f 1630 intel_autoenable_gt_powersave(dev_priv);
ee6f280e
ID		 1631 drm_kms_helper_poll_enable(dev);
1632
1f814dac
ID		 1633 enable_rpm_wakeref_asserts(dev_priv);
1634
074c6ada 1635 return 0;
84b79f8d
RW		 1636}
1637
5e365c39 1638static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1639{
fac5e23e 1640 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1641 struct pci_dev *pdev = dev_priv->drm.pdev;
44410cd0 1642 int ret;
36d61e67 1643
76c4b250
ID		 1644 /*
1645 * We have a resume ordering issue with the snd-hda driver also
1646 * requiring our device to be power up. Due to the lack of a
1647 * parent/child relationship we currently solve this with an early
1648 * resume hook.
1649 *
1650 * FIXME: This should be solved with a special hdmi sink device or
1651 * similar so that power domains can be employed.
1652 */
44410cd0
ID		 1653
1654 /*
1655 * Note that we need to set the power state explicitly, since we
1656 * powered off the device during freeze and the PCI core won't power
1657 * it back up for us during thaw. Powering off the device during
1658 * freeze is not a hard requirement though, and during the
1659 * suspend/resume phases the PCI core makes sure we get here with the
1660 * device powered on. So in case we change our freeze logic and keep
1661 * the device powered we can also remove the following set power state
1662 * call.
1663 */
52a05c30 1664 ret = pci_set_power_state(pdev, PCI_D0);
44410cd0
ID		 1665 if (ret) {
1666 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1667 goto out;
1668 }
1669
1670 /*
1671 * Note that pci_enable_device() first enables any parent bridge
1672 * device and only then sets the power state for this device. The
1673 * bridge enabling is a nop though, since bridge devices are resumed
1674 * first. The order of enabling power and enabling the device is
1675 * imposed by the PCI core as described above, so here we preserve the
1676 * same order for the freeze/thaw phases.
1677 *
1678 * TODO: eventually we should remove pci_disable_device() /
1679 * pci_enable_enable_device() from suspend/resume. Due to how they
1680 * depend on the device enable refcount we can't anyway depend on them
1681 * disabling/enabling the device.
1682 */
52a05c30 1683 if (pci_enable_device(pdev)) {
bc87229f
ID		 1684 ret = -EIO;
1685 goto out;
1686 }
84b79f8d 1687
52a05c30 1688 pci_set_master(pdev);
84b79f8d 1689
1f814dac
ID		 1690 disable_rpm_wakeref_asserts(dev_priv);
1691
666a4537 1692 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1693 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1694 if (ret)
ff0b187f
DL		 1695 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1696 ret);
36d61e67 1697
dc97997a 1698 intel_uncore_early_sanitize(dev_priv, true);
efee833a 1699
dc97997a 1700 if (IS_BROXTON(dev_priv)) {
da2f41d1
ID		 1701 if (!dev_priv->suspended_to_idle)
1702 gen9_sanitize_dc_state(dev_priv);
507e126e 1703 bxt_disable_dc9(dev_priv);
da2f41d1 1704 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1705 hsw_disable_pc8(dev_priv);
da2f41d1 1706 }
efee833a 1707
dc97997a 1708 intel_uncore_sanitize(dev_priv);
bc87229f 1709
a7c8125f
ID		 1710 if (IS_BROXTON(dev_priv) ||
1711 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 1712 intel_power_domains_init_hw(dev_priv, true);
1713
6e35e8ab
ID		 1714 enable_rpm_wakeref_asserts(dev_priv);
1715
bc87229f
ID		 1716out:
1717 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1718
1719 return ret;
76c4b250
ID		 1720}
1721
1751fcf9 1722int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1723{
50a0072f 1724 int ret;
76c4b250 1725
097dd837
ID		 1726 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1727 return 0;
1728
5e365c39 1729 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1730 if (ret)
1731 return ret;
1732
5a17514e
ID		 1733 return i915_drm_resume(dev);
1734}
1735
11ed50ec 1736/**
f3953dcb 1737 * i915_reset - reset chip after a hang
11ed50ec 1738 * @dev: drm device to reset
11ed50ec
BG		 1739 *
1740 * Reset the chip. Useful if a hang is detected. Returns zero on successful
1741 * reset or otherwise an error code.
1742 *
1743 * Procedure is fairly simple:
1744 * - reset the chip using the reset reg
1745 * - re-init context state
1746 * - re-init hardware status page
1747 * - re-init ring buffer
1748 * - re-init interrupt state
1749 * - re-init display
1750 */
c033666a 1751int i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 1752{
91c8a326 1753 struct drm_device *dev = &dev_priv->drm;
d98c52cf
CW		 1754 struct i915_gpu_error *error = &dev_priv->gpu_error;
1755 unsigned reset_counter;
0573ed4a 1756 int ret;
11ed50ec 1757
d54a02c0 1758 mutex_lock(&dev->struct_mutex);
11ed50ec 1759
d98c52cf
CW		 1760 /* Clear any previous failed attempts at recovery. Time to try again. */
1761 atomic_andnot(I915_WEDGED, &error->reset_counter);
77f01230 1762
d98c52cf
CW		 1763 /* Clear the reset-in-progress flag and increment the reset epoch. */
1764 reset_counter = atomic_inc_return(&error->reset_counter);
1765 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
1766 ret = -EIO;
1767 goto error;
1768 }
1769
7b4d3a16
CW		 1770 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1771
d98c52cf 1772 i915_gem_reset(dev);
2e7c8ee7 1773
dc97997a 1774 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
0573ed4a 1775 if (ret) {
804e59a8
CW		 1776 if (ret != -ENODEV)
1777 DRM_ERROR("Failed to reset chip: %i\n", ret);
1778 else
1779 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 1780 goto error;
11ed50ec
BG		 1781 }
1782
1362b776
VS		 1783 intel_overlay_reset(dev_priv);
1784
11ed50ec
BG		 1785 /* Ok, now get things going again... */
1786
1787 /*
1788 * Everything depends on having the GTT running, so we need to start
1789 * there. Fortunately we don't need to do this unless we reset the
1790 * chip at a PCI level.
1791 *
1792 * Next we need to restore the context, but we don't use those
1793 * yet either...
1794 *
1795 * Ring buffer needs to be re-initialized in the KMS case, or if X
1796 * was running at the time of the reset (i.e. we weren't VT
1797 * switched away).
1798 */
33d30a9c 1799 ret = i915_gem_init_hw(dev);
33d30a9c
DV		 1800 if (ret) {
1801 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1802 goto error;
11ed50ec
BG		 1803 }
1804
d98c52cf
CW		 1805 mutex_unlock(&dev->struct_mutex);
1806
33d30a9c
DV		 1807 /*
1808 * rps/rc6 re-init is necessary to restore state lost after the
1809 * reset and the re-install of gt irqs. Skip for ironlake per
1810 * previous concerns that it doesn't respond well to some forms
1811 * of re-init after reset.
1812 */
abc80abd 1813 intel_sanitize_gt_powersave(dev_priv);
54b4f68f 1814 intel_autoenable_gt_powersave(dev_priv);
33d30a9c 1815
11ed50ec 1816 return 0;
d98c52cf
CW		 1817
1818error:
1819 atomic_or(I915_WEDGED, &error->reset_counter);
1820 mutex_unlock(&dev->struct_mutex);
1821 return ret;
11ed50ec
BG		 1822}
1823
c49d13ee 1824static int i915_pm_suspend(struct device *kdev)
112b715e 1825{
c49d13ee
DW		 1826 struct pci_dev *pdev = to_pci_dev(kdev);
1827 struct drm_device *dev = pci_get_drvdata(pdev);
112b715e 1828
c49d13ee
DW		 1829 if (!dev) {
1830 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
84b79f8d
RW		 1831 return -ENODEV;
1832 }
112b715e 1833
c49d13ee 1834 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
5bcf719b
DA		 1835 return 0;
1836
c49d13ee 1837 return i915_drm_suspend(dev);
76c4b250
ID		 1838}
1839
c49d13ee 1840static int i915_pm_suspend_late(struct device *kdev)
76c4b250 1841{
c49d13ee 1842 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250
ID		 1843
1844 /*
c965d995 1845 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 1846 * requiring our device to be power up. Due to the lack of a
1847 * parent/child relationship we currently solve this with an late
1848 * suspend hook.
1849 *
1850 * FIXME: This should be solved with a special hdmi sink device or
1851 * similar so that power domains can be employed.
1852 */
c49d13ee 1853 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
76c4b250 1854 return 0;
112b715e 1855
c49d13ee 1856 return i915_drm_suspend_late(dev, false);
ab3be73f
ID		 1857}
1858
c49d13ee 1859static int i915_pm_poweroff_late(struct device *kdev)
ab3be73f 1860{
c49d13ee 1861 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
ab3be73f 1862
c49d13ee 1863 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
ab3be73f
ID		 1864 return 0;
1865
c49d13ee 1866 return i915_drm_suspend_late(dev, true);
cbda12d7
ZW		 1867}
1868
c49d13ee 1869static int i915_pm_resume_early(struct device *kdev)
76c4b250 1870{
c49d13ee 1871 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250 1872
c49d13ee 1873 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1874 return 0;
1875
c49d13ee 1876 return i915_drm_resume_early(dev);
76c4b250
ID		 1877}
1878
c49d13ee 1879static int i915_pm_resume(struct device *kdev)
cbda12d7 1880{
c49d13ee 1881 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
84b79f8d 1882
c49d13ee 1883 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1884 return 0;
1885
c49d13ee 1886 return i915_drm_resume(dev);
cbda12d7
ZW		 1887}
1888
1f19ac2a 1889/* freeze: before creating the hibernation_image */
c49d13ee 1890static int i915_pm_freeze(struct device *kdev)
1f19ac2a 1891{
c49d13ee 1892 return i915_pm_suspend(kdev);
1f19ac2a
CW		 1893}
1894
c49d13ee 1895static int i915_pm_freeze_late(struct device *kdev)
1f19ac2a 1896{
461fb99c
CW		 1897 int ret;
1898
c49d13ee 1899 ret = i915_pm_suspend_late(kdev);
461fb99c
CW		 1900 if (ret)
1901 return ret;
1902
c49d13ee 1903 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
461fb99c
CW		 1904 if (ret)
1905 return ret;
1906
1907 return 0;
1f19ac2a
CW		 1908}
1909
1910/* thaw: called after creating the hibernation image, but before turning off. */
c49d13ee 1911static int i915_pm_thaw_early(struct device *kdev)
1f19ac2a 1912{
c49d13ee 1913 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1914}
1915
c49d13ee 1916static int i915_pm_thaw(struct device *kdev)
1f19ac2a 1917{
c49d13ee 1918 return i915_pm_resume(kdev);
1f19ac2a
CW		 1919}
1920
1921/* restore: called after loading the hibernation image. */
c49d13ee 1922static int i915_pm_restore_early(struct device *kdev)
1f19ac2a 1923{
c49d13ee 1924 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1925}
1926
c49d13ee 1927static int i915_pm_restore(struct device *kdev)
1f19ac2a 1928{
c49d13ee 1929 return i915_pm_resume(kdev);
1f19ac2a
CW		 1930}
1931
ddeea5b0
ID		 1932/*
1933 * Save all Gunit registers that may be lost after a D3 and a subsequent
1934 * S0i[R123] transition. The list of registers needing a save/restore is
1935 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1936 * registers in the following way:
1937 * - Driver: saved/restored by the driver
1938 * - Punit : saved/restored by the Punit firmware
1939 * - No, w/o marking: no need to save/restore, since the register is R/O or
1940 * used internally by the HW in a way that doesn't depend
1941 * keeping the content across a suspend/resume.
1942 * - Debug : used for debugging
1943 *
1944 * We save/restore all registers marked with 'Driver', with the following
1945 * exceptions:
1946 * - Registers out of use, including also registers marked with 'Debug'.
1947 * These have no effect on the driver's operation, so we don't save/restore
1948 * them to reduce the overhead.
1949 * - Registers that are fully setup by an initialization function called from
1950 * the resume path. For example many clock gating and RPS/RC6 registers.
1951 * - Registers that provide the right functionality with their reset defaults.
1952 *
1953 * TODO: Except for registers that based on the above 3 criteria can be safely
1954 * ignored, we save/restore all others, practically treating the HW context as
1955 * a black-box for the driver. Further investigation is needed to reduce the
1956 * saved/restored registers even further, by following the same 3 criteria.
1957 */
1958static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1959{
1960 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1961 int i;
1962
1963 /* GAM 0x4000-0x4770 */
1964 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1965 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1966 s->arb_mode = I915_READ(ARB_MODE);
1967 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1968 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1969
1970 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 1971 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 1972
1973 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 1974 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 1975
1976 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1977 s->ecochk = I915_READ(GAM_ECOCHK);
1978 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1979 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1980
1981 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1982
1983 /* MBC 0x9024-0x91D0, 0x8500 */
1984 s->g3dctl = I915_READ(VLV_G3DCTL);
1985 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1986 s->mbctl = I915_READ(GEN6_MBCTL);
1987
1988 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1989 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1990 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1991 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1992 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1993 s->rstctl = I915_READ(GEN6_RSTCTL);
1994 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1995
1996 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1997 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1998 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1999 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2000 s->ecobus = I915_READ(ECOBUS);
2001 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2002 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2003 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2004 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2005 s->rcedata = I915_READ(VLV_RCEDATA);
2006 s->spare2gh = I915_READ(VLV_SPAREG2H);
2007
2008 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2009 s->gt_imr = I915_READ(GTIMR);
2010 s->gt_ier = I915_READ(GTIER);
2011 s->pm_imr = I915_READ(GEN6_PMIMR);
2012 s->pm_ier = I915_READ(GEN6_PMIER);
2013
2014 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2015 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2016
2017 /* GT SA CZ domain, 0x100000-0x138124 */
2018 s->tilectl = I915_READ(TILECTL);
2019 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2020 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2021 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2022 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2023
2024 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2025 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2026 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2027 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2028 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2029
2030 /*
2031 * Not saving any of:
2032 * DFT, 0x9800-0x9EC0
2033 * SARB, 0xB000-0xB1FC
2034 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2035 * PCI CFG
2036 */
2037}
2038
2039static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2040{
2041 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2042 u32 val;
2043 int i;
2044
2045 /* GAM 0x4000-0x4770 */
2046 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2047 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2048 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2049 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2050 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2051
2052 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2053 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2054
2055 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2056 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2057
2058 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2059 I915_WRITE(GAM_ECOCHK, s->ecochk);
2060 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2061 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2062
2063 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2064
2065 /* MBC 0x9024-0x91D0, 0x8500 */
2066 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2067 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2068 I915_WRITE(GEN6_MBCTL, s->mbctl);
2069
2070 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2071 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2072 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2073 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2074 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2075 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2076 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2077
2078 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2079 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2080 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2081 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2082 I915_WRITE(ECOBUS, s->ecobus);
2083 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2084 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2085 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2086 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2087 I915_WRITE(VLV_RCEDATA, s->rcedata);
2088 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2089
2090 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2091 I915_WRITE(GTIMR, s->gt_imr);
2092 I915_WRITE(GTIER, s->gt_ier);
2093 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2094 I915_WRITE(GEN6_PMIER, s->pm_ier);
2095
2096 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2097 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2098
2099 /* GT SA CZ domain, 0x100000-0x138124 */
2100 I915_WRITE(TILECTL, s->tilectl);
2101 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2102 /*
2103 * Preserve the GT allow wake and GFX force clock bit, they are not
2104 * be restored, as they are used to control the s0ix suspend/resume
2105 * sequence by the caller.
2106 */
2107 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2108 val &= VLV_GTLC_ALLOWWAKEREQ;
2109 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2110 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2111
2112 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2113 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2114 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2115 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2116
2117 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2118
2119 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2120 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2121 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2122 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2123 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2124}
2125
650ad970
ID		 2126int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2127{
2128 u32 val;
2129 int err;
2130
650ad970
ID		 2131 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2132 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2133 if (force_on)
2134 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2135 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2136
2137 if (!force_on)
2138 return 0;
2139
c6ddc5f3
CW		 2140 err = intel_wait_for_register(dev_priv,
2141 VLV_GTLC_SURVIVABILITY_REG,
2142 VLV_GFX_CLK_STATUS_BIT,
2143 VLV_GFX_CLK_STATUS_BIT,
2144 20);
650ad970
ID		 2145 if (err)
2146 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2147 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2148
2149 return err;
650ad970
ID		 2150}
2151
ddeea5b0
ID		 2152static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2153{
2154 u32 val;
2155 int err = 0;
2156
2157 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2158 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2159 if (allow)
2160 val |= VLV_GTLC_ALLOWWAKEREQ;
2161 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2162 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2163
b2736695
CW		 2164 err = intel_wait_for_register(dev_priv,
2165 VLV_GTLC_PW_STATUS,
2166 VLV_GTLC_ALLOWWAKEACK,
2167 allow,
2168 1);
ddeea5b0
ID		 2169 if (err)
2170 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2171
ddeea5b0 2172 return err;
ddeea5b0
ID		 2173}
2174
2175static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2176 bool wait_for_on)
2177{
2178 u32 mask;
2179 u32 val;
2180 int err;
2181
2182 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2183 val = wait_for_on ? mask : 0;
41ce405e 2184 if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
ddeea5b0
ID		 2185 return 0;
2186
2187 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
87ad3212
JN		 2188 onoff(wait_for_on),
2189 I915_READ(VLV_GTLC_PW_STATUS));
ddeea5b0
ID		 2190
2191 /*
2192 * RC6 transitioning can be delayed up to 2 msec (see
2193 * valleyview_enable_rps), use 3 msec for safety.
2194 */
41ce405e
CW		 2195 err = intel_wait_for_register(dev_priv,
2196 VLV_GTLC_PW_STATUS, mask, val,
2197 3);
ddeea5b0
ID		 2198 if (err)
2199 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2200 onoff(wait_for_on));
ddeea5b0
ID		 2201
2202 return err;
ddeea5b0
ID		 2203}
2204
2205static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2206{
2207 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2208 return;
2209
6fa283b0 2210 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2211 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2212}
2213
ebc32824 2214static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2215{
2216 u32 mask;
2217 int err;
2218
2219 /*
2220 * Bspec defines the following GT well on flags as debug only, so
2221 * don't treat them as hard failures.
2222 */
2223 (void)vlv_wait_for_gt_wells(dev_priv, false);
2224
2225 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2226 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2227
2228 vlv_check_no_gt_access(dev_priv);
2229
2230 err = vlv_force_gfx_clock(dev_priv, true);
2231 if (err)
2232 goto err1;
2233
2234 err = vlv_allow_gt_wake(dev_priv, false);
2235 if (err)
2236 goto err2;
98711167 2237
2d1fe073 2238 if (!IS_CHERRYVIEW(dev_priv))
98711167 2239 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2240
2241 err = vlv_force_gfx_clock(dev_priv, false);
2242 if (err)
2243 goto err2;
2244
2245 return 0;
2246
2247err2:
2248 /* For safety always re-enable waking and disable gfx clock forcing */
2249 vlv_allow_gt_wake(dev_priv, true);
2250err1:
2251 vlv_force_gfx_clock(dev_priv, false);
2252
2253 return err;
2254}
2255
016970be
SK		 2256static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2257 bool rpm_resume)
ddeea5b0 2258{
91c8a326 2259 struct drm_device *dev = &dev_priv->drm;
ddeea5b0
ID		 2260 int err;
2261 int ret;
2262
2263 /*
2264 * If any of the steps fail just try to continue, that's the best we
2265 * can do at this point. Return the first error code (which will also
2266 * leave RPM permanently disabled).
2267 */
2268 ret = vlv_force_gfx_clock(dev_priv, true);
2269
2d1fe073 2270 if (!IS_CHERRYVIEW(dev_priv))
98711167 2271 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2272
2273 err = vlv_allow_gt_wake(dev_priv, true);
2274 if (!ret)
2275 ret = err;
2276
2277 err = vlv_force_gfx_clock(dev_priv, false);
2278 if (!ret)
2279 ret = err;
2280
2281 vlv_check_no_gt_access(dev_priv);
2282
016970be
SK		 2283 if (rpm_resume) {
2284 intel_init_clock_gating(dev);
2285 i915_gem_restore_fences(dev);
2286 }
ddeea5b0
ID		 2287
2288 return ret;
2289}
2290
c49d13ee 2291static int intel_runtime_suspend(struct device *kdev)
8a187455 2292{
c49d13ee 2293 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2294 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2295 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2296 int ret;
8a187455 2297
dc97997a 2298 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2299 return -ENODEV;
2300
604effb7
ID		 2301 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2302 return -ENODEV;
2303
8a187455
PZ		 2304 DRM_DEBUG_KMS("Suspending device\n");
2305
d6102977
ID		 2306 /*
2307 * We could deadlock here in case another thread holding struct_mutex
2308 * calls RPM suspend concurrently, since the RPM suspend will wait
2309 * first for this RPM suspend to finish. In this case the concurrent
2310 * RPM resume will be followed by its RPM suspend counterpart. Still
2311 * for consistency return -EAGAIN, which will reschedule this suspend.
2312 */
2313 if (!mutex_trylock(&dev->struct_mutex)) {
2314 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2315 /*
2316 * Bump the expiration timestamp, otherwise the suspend won't
2317 * be rescheduled.
2318 */
c49d13ee 2319 pm_runtime_mark_last_busy(kdev);
d6102977
ID		 2320
2321 return -EAGAIN;
2322 }
1f814dac
ID		 2323
2324 disable_rpm_wakeref_asserts(dev_priv);
2325
d6102977
ID		 2326 /*
2327 * We are safe here against re-faults, since the fault handler takes
2328 * an RPM reference.
2329 */
2330 i915_gem_release_all_mmaps(dev_priv);
2331 mutex_unlock(&dev->struct_mutex);
2332
a1c41994
AD		 2333 intel_guc_suspend(dev);
2334
2eb5252e 2335 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2336
507e126e
ID		 2337 ret = 0;
2338 if (IS_BROXTON(dev_priv)) {
2339 bxt_display_core_uninit(dev_priv);
2340 bxt_enable_dc9(dev_priv);
2341 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2342 hsw_enable_pc8(dev_priv);
2343 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2344 ret = vlv_suspend_complete(dev_priv);
2345 }
2346
0ab9cfeb
ID		 2347 if (ret) {
2348 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2349 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2350
1f814dac
ID		 2351 enable_rpm_wakeref_asserts(dev_priv);
2352
0ab9cfeb
ID		 2353 return ret;
2354 }
a8a8bd54 2355
dc97997a 2356 intel_uncore_forcewake_reset(dev_priv, false);
1f814dac
ID		 2357
2358 enable_rpm_wakeref_asserts(dev_priv);
2359 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2360
bc3b9346 2361 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2362 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2363
8a187455 2364 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2365
2366 /*
c8a0bd42
PZ		 2367 * FIXME: We really should find a document that references the arguments
2368 * used below!
1fb2362b 2369 */
6f9f4b7a 2370 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2371 /*
2372 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2373 * being detected, and the call we do at intel_runtime_resume()
2374 * won't be able to restore them. Since PCI_D3hot matches the
2375 * actual specification and appears to be working, use it.
2376 */
6f9f4b7a 2377 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2378 } else {
c8a0bd42
PZ		 2379 /*
2380 * current versions of firmware which depend on this opregion
2381 * notification have repurposed the D1 definition to mean
2382 * "runtime suspended" vs. what you would normally expect (D3)
2383 * to distinguish it from notifications that might be sent via
2384 * the suspend path.
2385 */
6f9f4b7a 2386 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2387 }
8a187455 2388
59bad947 2389 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2390
19625e85
L		 2391 if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2392 intel_hpd_poll_init(dev_priv);
2393
a8a8bd54 2394 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2395 return 0;
2396}
2397
c49d13ee 2398static int intel_runtime_resume(struct device *kdev)
8a187455 2399{
c49d13ee 2400 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2401 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2402 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2403 int ret = 0;
8a187455 2404
604effb7
ID		 2405 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2406 return -ENODEV;
8a187455
PZ		 2407
2408 DRM_DEBUG_KMS("Resuming device\n");
2409
1f814dac
ID		 2410 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2411 disable_rpm_wakeref_asserts(dev_priv);
2412
6f9f4b7a 2413 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2414 dev_priv->pm.suspended = false;
55ec45c2
MK		 2415 if (intel_uncore_unclaimed_mmio(dev_priv))
2416 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2417
a1c41994
AD		 2418 intel_guc_resume(dev);
2419
1a5df187
PZ		 2420 if (IS_GEN6(dev_priv))
2421 intel_init_pch_refclk(dev);
31335cec 2422
507e126e
ID		 2423 if (IS_BROXTON(dev)) {
2424 bxt_disable_dc9(dev_priv);
2425 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2426 if (dev_priv->csr.dmc_payload &&
2427 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2428 gen9_enable_dc5(dev_priv);
507e126e 2429 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2430 hsw_disable_pc8(dev_priv);
507e126e 2431 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2432 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2433 }
1a5df187 2434
0ab9cfeb
ID		 2435 /*
2436 * No point of rolling back things in case of an error, as the best
2437 * we can do is to hope that things will still work (and disable RPM).
2438 */
92b806d3 2439 i915_gem_init_swizzling(dev);
92b806d3 2440
b963291c 2441 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2442
2443 /*
2444 * On VLV/CHV display interrupts are part of the display
2445 * power well, so hpd is reinitialized from there. For
2446 * everyone else do it here.
2447 */
666a4537 2448 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2449 intel_hpd_init(dev_priv);
2450
1f814dac
ID		 2451 enable_rpm_wakeref_asserts(dev_priv);
2452
0ab9cfeb
ID		 2453 if (ret)
2454 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2455 else
2456 DRM_DEBUG_KMS("Device resumed\n");
2457
2458 return ret;
8a187455
PZ		 2459}
2460
42f5551d 2461const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2462 /*
2463 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2464 * PMSG_RESUME]
2465 */
0206e353 2466 .suspend = i915_pm_suspend,
76c4b250
ID		 2467 .suspend_late = i915_pm_suspend_late,
2468 .resume_early = i915_pm_resume_early,
0206e353 2469 .resume = i915_pm_resume,
5545dbbf
ID		 2470
2471 /*
2472 * S4 event handlers
2473 * @freeze, @freeze_late : called (1) before creating the
2474 * hibernation image [PMSG_FREEZE] and
2475 * (2) after rebooting, before restoring
2476 * the image [PMSG_QUIESCE]
2477 * @thaw, @thaw_early : called (1) after creating the hibernation
2478 * image, before writing it [PMSG_THAW]
2479 * and (2) after failing to create or
2480 * restore the image [PMSG_RECOVER]
2481 * @poweroff, @poweroff_late: called after writing the hibernation
2482 * image, before rebooting [PMSG_HIBERNATE]
2483 * @restore, @restore_early : called after rebooting and restoring the
2484 * hibernation image [PMSG_RESTORE]
2485 */
1f19ac2a
CW		 2486 .freeze = i915_pm_freeze,
2487 .freeze_late = i915_pm_freeze_late,
2488 .thaw_early = i915_pm_thaw_early,
2489 .thaw = i915_pm_thaw,
36d61e67 2490 .poweroff = i915_pm_suspend,
ab3be73f 2491 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2492 .restore_early = i915_pm_restore_early,
2493 .restore = i915_pm_restore,
5545dbbf
ID		 2494
2495 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2496 .runtime_suspend = intel_runtime_suspend,
2497 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2498};
2499
78b68556 2500static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2501 .fault = i915_gem_fault,
ab00b3e5
JB		 2502 .open = drm_gem_vm_open,
2503 .close = drm_gem_vm_close,
de151cf6
JB		 2504};
2505
e08e96de
AV		 2506static const struct file_operations i915_driver_fops = {
2507 .owner = THIS_MODULE,
2508 .open = drm_open,
2509 .release = drm_release,
2510 .unlocked_ioctl = drm_ioctl,
2511 .mmap = drm_gem_mmap,
2512 .poll = drm_poll,
e08e96de
AV		 2513 .read = drm_read,
2514#ifdef CONFIG_COMPAT
2515 .compat_ioctl = i915_compat_ioctl,
2516#endif
2517 .llseek = noop_llseek,
2518};
2519
0673ad47
CW		 2520static int
2521i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2522 struct drm_file *file)
2523{
2524 return -ENODEV;
2525}
2526
2527static const struct drm_ioctl_desc i915_ioctls[] = {
2528 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2529 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2530 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2531 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2532 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2533 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2534 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2535 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2536 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2537 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2538 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2539 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2540 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2541 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2542 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2543 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2544 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2545 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2546 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2547 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2548 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2549 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2550 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2551 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2552 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2553 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2554 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2555 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2556 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2557 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2558 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2559 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2560 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2561 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2562 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2563 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2564 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2565 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2566 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2567 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2568 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2569 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2570 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2571 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2572 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2573 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2574 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2575 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2576 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2577 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2578 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2579 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2580};
2581
1da177e4 2582static struct drm_driver driver = {
0c54781b
MW		 2583 /* Don't use MTRRs here; the Xserver or userspace app should
2584 * deal with them for Intel hardware.
792d2b9a 2585 */
673a394b 2586 .driver_features =
10ba5012 2587 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1751fcf9 2588 DRIVER_RENDER | DRIVER_MODESET,
673a394b 2589 .open = i915_driver_open,
22eae947
DA		 2590 .lastclose = i915_driver_lastclose,
2591 .preclose = i915_driver_preclose,
673a394b 2592 .postclose = i915_driver_postclose,
915b4d11 2593 .set_busid = drm_pci_set_busid,
d8e29209 2594
b1f788c6 2595 .gem_close_object = i915_gem_close_object,
673a394b 2596 .gem_free_object = i915_gem_free_object,
de151cf6 2597 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2598
2599 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2600 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2601 .gem_prime_export = i915_gem_prime_export,
2602 .gem_prime_import = i915_gem_prime_import,
2603
ff72145b 2604 .dumb_create = i915_gem_dumb_create,
da6b51d0 2605 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 2606 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 2607 .ioctls = i915_ioctls,
0673ad47 2608 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2609 .fops = &i915_driver_fops,
22eae947
DA		 2610 .name = DRIVER_NAME,
2611 .desc = DRIVER_DESC,
2612 .date = DRIVER_DATE,
2613 .major = DRIVER_MAJOR,
2614 .minor = DRIVER_MINOR,
2615 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2616};
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