]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
e5747e3a | 31 | #include <linux/acpi.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/i915_drm.h> | |
1da177e4 | 34 | #include "i915_drv.h" |
990bbdad | 35 | #include "i915_trace.h" |
f49f0586 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
79e53945 | 38 | #include <linux/console.h> |
e0cd3608 | 39 | #include <linux/module.h> |
d6102977 | 40 | #include <linux/pm_runtime.h> |
760285e7 | 41 | #include <drm/drm_crtc_helper.h> |
79e53945 | 42 | |
112b715e KH |
43 | static struct drm_driver driver; |
44 | ||
a57c774a AK |
45 | #define GEN_DEFAULT_PIPEOFFSETS \ |
46 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
47 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
48 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
49 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
a57c774a AK |
50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
51 | ||
84fd4f4e RB |
52 | #define GEN_CHV_PIPEOFFSETS \ |
53 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
54 | CHV_PIPE_C_OFFSET }, \ | |
55 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
56 | CHV_TRANSCODER_C_OFFSET, }, \ | |
84fd4f4e RB |
57 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
58 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 59 | |
5efb3e28 VS |
60 | #define CURSOR_OFFSETS \ |
61 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
62 | ||
63 | #define IVB_CURSOR_OFFSETS \ | |
64 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
65 | ||
9a7e8492 | 66 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 67 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 68 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 69 | .ring_mask = RENDER_RING, |
a57c774a | 70 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 71 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
72 | }; |
73 | ||
9a7e8492 | 74 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 75 | .gen = 2, .num_pipes = 1, |
31578148 | 76 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 77 | .ring_mask = RENDER_RING, |
a57c774a | 78 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 79 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
80 | }; |
81 | ||
9a7e8492 | 82 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 83 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 84 | .cursor_needs_physical = 1, |
31578148 | 85 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 86 | .has_fbc = 1, |
73ae478c | 87 | .ring_mask = RENDER_RING, |
a57c774a | 88 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 89 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
90 | }; |
91 | ||
9a7e8492 | 92 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 93 | .gen = 2, .num_pipes = 1, |
31578148 | 94 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 95 | .ring_mask = RENDER_RING, |
a57c774a | 96 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 97 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
98 | }; |
99 | ||
9a7e8492 | 100 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 101 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 102 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 103 | .ring_mask = RENDER_RING, |
a57c774a | 104 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 105 | CURSOR_OFFSETS, |
cfdf1fa2 | 106 | }; |
9a7e8492 | 107 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 108 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 109 | .cursor_needs_physical = 1, |
31578148 | 110 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 111 | .supports_tv = 1, |
fd70d52a | 112 | .has_fbc = 1, |
73ae478c | 113 | .ring_mask = RENDER_RING, |
a57c774a | 114 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 115 | CURSOR_OFFSETS, |
cfdf1fa2 | 116 | }; |
9a7e8492 | 117 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 118 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 119 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 120 | .ring_mask = RENDER_RING, |
a57c774a | 121 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 122 | CURSOR_OFFSETS, |
cfdf1fa2 | 123 | }; |
9a7e8492 | 124 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 125 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 126 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 127 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 128 | .supports_tv = 1, |
fd70d52a | 129 | .has_fbc = 1, |
73ae478c | 130 | .ring_mask = RENDER_RING, |
a57c774a | 131 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 132 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
133 | }; |
134 | ||
9a7e8492 | 135 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 136 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 137 | .has_hotplug = 1, |
31578148 | 138 | .has_overlay = 1, |
73ae478c | 139 | .ring_mask = RENDER_RING, |
a57c774a | 140 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 141 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
142 | }; |
143 | ||
9a7e8492 | 144 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 145 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 146 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 147 | .has_overlay = 1, |
a6c45cf0 | 148 | .supports_tv = 1, |
73ae478c | 149 | .ring_mask = RENDER_RING, |
a57c774a | 150 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 151 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
152 | }; |
153 | ||
9a7e8492 | 154 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 155 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 156 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 157 | .has_overlay = 1, |
73ae478c | 158 | .ring_mask = RENDER_RING, |
a57c774a | 159 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 160 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
161 | }; |
162 | ||
9a7e8492 | 163 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 164 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 165 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 166 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 167 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 168 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
169 | }; |
170 | ||
9a7e8492 | 171 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 172 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 173 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 174 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 175 | .supports_tv = 1, |
73ae478c | 176 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 177 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 178 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
179 | }; |
180 | ||
9a7e8492 | 181 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 182 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 183 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 184 | .has_overlay = 1, |
a57c774a | 185 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 186 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
187 | }; |
188 | ||
9a7e8492 | 189 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 190 | .gen = 5, .num_pipes = 2, |
5a117db7 | 191 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 192 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 193 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 194 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
195 | }; |
196 | ||
9a7e8492 | 197 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 198 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 199 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 200 | .has_fbc = 1, |
73ae478c | 201 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 202 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 203 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
204 | }; |
205 | ||
9a7e8492 | 206 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 207 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 208 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 209 | .has_fbc = 1, |
73ae478c | 210 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 211 | .has_llc = 1, |
a57c774a | 212 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 213 | CURSOR_OFFSETS, |
f6e450a6 EA |
214 | }; |
215 | ||
9a7e8492 | 216 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 217 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 218 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 219 | .has_fbc = 1, |
73ae478c | 220 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 221 | .has_llc = 1, |
a57c774a | 222 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 223 | CURSOR_OFFSETS, |
a13e4093 EA |
224 | }; |
225 | ||
219f4fdb BW |
226 | #define GEN7_FEATURES \ |
227 | .gen = 7, .num_pipes = 3, \ | |
228 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 229 | .has_fbc = 1, \ |
73ae478c | 230 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
6a8beeff WB |
231 | .has_llc = 1, \ |
232 | GEN_DEFAULT_PIPEOFFSETS, \ | |
233 | IVB_CURSOR_OFFSETS | |
219f4fdb | 234 | |
c76b615c | 235 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
236 | GEN7_FEATURES, |
237 | .is_ivybridge = 1, | |
c76b615c JB |
238 | }; |
239 | ||
240 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
241 | GEN7_FEATURES, |
242 | .is_ivybridge = 1, | |
243 | .is_mobile = 1, | |
c76b615c JB |
244 | }; |
245 | ||
999bcdea BW |
246 | static const struct intel_device_info intel_ivybridge_q_info = { |
247 | GEN7_FEATURES, | |
248 | .is_ivybridge = 1, | |
249 | .num_pipes = 0, /* legal, last one wins */ | |
250 | }; | |
251 | ||
6a8beeff WB |
252 | #define VLV_FEATURES \ |
253 | .gen = 7, .num_pipes = 2, \ | |
254 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
255 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
256 | .display_mmio_offset = VLV_DISPLAY_BASE, \ | |
257 | GEN_DEFAULT_PIPEOFFSETS, \ | |
258 | CURSOR_OFFSETS | |
259 | ||
70a3eb7a | 260 | static const struct intel_device_info intel_valleyview_m_info = { |
6a8beeff | 261 | VLV_FEATURES, |
70a3eb7a | 262 | .is_valleyview = 1, |
6a8beeff | 263 | .is_mobile = 1, |
70a3eb7a JB |
264 | }; |
265 | ||
266 | static const struct intel_device_info intel_valleyview_d_info = { | |
6a8beeff | 267 | VLV_FEATURES, |
70a3eb7a JB |
268 | .is_valleyview = 1, |
269 | }; | |
270 | ||
6a8beeff WB |
271 | #define HSW_FEATURES \ |
272 | GEN7_FEATURES, \ | |
273 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
274 | .has_ddi = 1, \ | |
275 | .has_fpga_dbg = 1 | |
276 | ||
4cae9ae0 | 277 | static const struct intel_device_info intel_haswell_d_info = { |
6a8beeff | 278 | HSW_FEATURES, |
219f4fdb | 279 | .is_haswell = 1, |
4cae9ae0 ED |
280 | }; |
281 | ||
282 | static const struct intel_device_info intel_haswell_m_info = { | |
6a8beeff | 283 | HSW_FEATURES, |
219f4fdb BW |
284 | .is_haswell = 1, |
285 | .is_mobile = 1, | |
c76b615c JB |
286 | }; |
287 | ||
4d4dead6 | 288 | static const struct intel_device_info intel_broadwell_d_info = { |
6a8beeff WB |
289 | HSW_FEATURES, |
290 | .gen = 8, | |
4d4dead6 BW |
291 | }; |
292 | ||
293 | static const struct intel_device_info intel_broadwell_m_info = { | |
6a8beeff WB |
294 | HSW_FEATURES, |
295 | .gen = 8, .is_mobile = 1, | |
4d4dead6 BW |
296 | }; |
297 | ||
fd3c269f | 298 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
6a8beeff WB |
299 | HSW_FEATURES, |
300 | .gen = 8, | |
845f74a7 | 301 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
302 | }; |
303 | ||
304 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
6a8beeff WB |
305 | HSW_FEATURES, |
306 | .gen = 8, .is_mobile = 1, | |
845f74a7 | 307 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
308 | }; |
309 | ||
7d87a7f7 | 310 | static const struct intel_device_info intel_cherryview_info = { |
07fddb14 | 311 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
312 | .need_gfx_hws = 1, .has_hotplug = 1, |
313 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
666a4537 | 314 | .is_cherryview = 1, |
7d87a7f7 | 315 | .display_mmio_offset = VLV_DISPLAY_BASE, |
84fd4f4e | 316 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 317 | CURSOR_OFFSETS, |
7d87a7f7 VS |
318 | }; |
319 | ||
72bbf0af | 320 | static const struct intel_device_info intel_skylake_info = { |
6a8beeff | 321 | HSW_FEATURES, |
7201c0b3 | 322 | .is_skylake = 1, |
6a8beeff | 323 | .gen = 9, |
72bbf0af DL |
324 | }; |
325 | ||
719388e1 | 326 | static const struct intel_device_info intel_skylake_gt3_info = { |
a9287dbc | 327 | HSW_FEATURES, |
719388e1 | 328 | .is_skylake = 1, |
6a8beeff | 329 | .gen = 9, |
719388e1 | 330 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
719388e1 DL |
331 | }; |
332 | ||
1347f5b4 DL |
333 | static const struct intel_device_info intel_broxton_info = { |
334 | .is_preliminary = 1, | |
7526ac19 | 335 | .is_broxton = 1, |
1347f5b4 DL |
336 | .gen = 9, |
337 | .need_gfx_hws = 1, .has_hotplug = 1, | |
338 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
339 | .num_pipes = 3, | |
340 | .has_ddi = 1, | |
6c908bf4 | 341 | .has_fpga_dbg = 1, |
ce89db2e | 342 | .has_fbc = 1, |
1347f5b4 DL |
343 | GEN_DEFAULT_PIPEOFFSETS, |
344 | IVB_CURSOR_OFFSETS, | |
345 | }; | |
346 | ||
ef11bdb3 | 347 | static const struct intel_device_info intel_kabylake_info = { |
6a8beeff | 348 | HSW_FEATURES, |
ef11bdb3 RV |
349 | .is_preliminary = 1, |
350 | .is_kabylake = 1, | |
351 | .gen = 9, | |
ef11bdb3 RV |
352 | }; |
353 | ||
354 | static const struct intel_device_info intel_kabylake_gt3_info = { | |
6a8beeff | 355 | HSW_FEATURES, |
ef11bdb3 RV |
356 | .is_preliminary = 1, |
357 | .is_kabylake = 1, | |
358 | .gen = 9, | |
ef11bdb3 | 359 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
ef11bdb3 RV |
360 | }; |
361 | ||
a0a18075 JB |
362 | /* |
363 | * Make sure any device matches here are from most specific to most | |
364 | * general. For example, since the Quanta match is based on the subsystem | |
365 | * and subvendor IDs, we need it to come before the more general IVB | |
366 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
367 | */ | |
3cb27f38 JN |
368 | static const struct pci_device_id pciidlist[] = { |
369 | INTEL_I830_IDS(&intel_i830_info), | |
370 | INTEL_I845G_IDS(&intel_845g_info), | |
371 | INTEL_I85X_IDS(&intel_i85x_info), | |
372 | INTEL_I865G_IDS(&intel_i865g_info), | |
373 | INTEL_I915G_IDS(&intel_i915g_info), | |
374 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
375 | INTEL_I945G_IDS(&intel_i945g_info), | |
376 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
377 | INTEL_I965G_IDS(&intel_i965g_info), | |
378 | INTEL_G33_IDS(&intel_g33_info), | |
379 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
380 | INTEL_GM45_IDS(&intel_gm45_info), | |
381 | INTEL_G45_IDS(&intel_g45_info), | |
382 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
383 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
384 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
385 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), | |
386 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), | |
387 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ | |
388 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), | |
389 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), | |
390 | INTEL_HSW_D_IDS(&intel_haswell_d_info), | |
391 | INTEL_HSW_M_IDS(&intel_haswell_m_info), | |
392 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), | |
393 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), | |
394 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), | |
395 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), | |
396 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), | |
397 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), | |
398 | INTEL_CHV_IDS(&intel_cherryview_info), | |
399 | INTEL_SKL_GT1_IDS(&intel_skylake_info), | |
400 | INTEL_SKL_GT2_IDS(&intel_skylake_info), | |
401 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), | |
15620206 | 402 | INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), |
3cb27f38 | 403 | INTEL_BXT_IDS(&intel_broxton_info), |
d97044b6 D |
404 | INTEL_KBL_GT1_IDS(&intel_kabylake_info), |
405 | INTEL_KBL_GT2_IDS(&intel_kabylake_info), | |
406 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), | |
8b10c0cf | 407 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), |
49ae35f2 | 408 | {0, 0, 0} |
1da177e4 LT |
409 | }; |
410 | ||
79e53945 | 411 | MODULE_DEVICE_TABLE(pci, pciidlist); |
79e53945 | 412 | |
30c964a6 RB |
413 | static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) |
414 | { | |
415 | enum intel_pch ret = PCH_NOP; | |
416 | ||
417 | /* | |
418 | * In a virtualized passthrough environment we can be in a | |
419 | * setup where the ISA bridge is not able to be passed through. | |
420 | * In this case, a south bridge can be emulated and we have to | |
421 | * make an educated guess as to which PCH is really there. | |
422 | */ | |
423 | ||
424 | if (IS_GEN5(dev)) { | |
425 | ret = PCH_IBX; | |
426 | DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); | |
427 | } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { | |
428 | ret = PCH_CPT; | |
429 | DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); | |
430 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
431 | ret = PCH_LPT; | |
432 | DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); | |
ef11bdb3 | 433 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
30c964a6 RB |
434 | ret = PCH_SPT; |
435 | DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); | |
436 | } | |
437 | ||
438 | return ret; | |
439 | } | |
440 | ||
0206e353 | 441 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
442 | { |
443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 444 | struct pci_dev *pch = NULL; |
3bad0781 | 445 | |
ce1bb329 BW |
446 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
447 | * (which really amounts to a PCH but no South Display). | |
448 | */ | |
449 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
450 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
451 | return; |
452 | } | |
453 | ||
3bad0781 ZW |
454 | /* |
455 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
456 | * make graphics device passthrough work easy for VMM, that only | |
457 | * need to expose ISA bridge to let driver know the real hardware | |
458 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
459 | * |
460 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
461 | * ISA bridge in the system. To work reliably, we should scan trhough | |
462 | * all the ISA bridge devices and check for the first match, instead | |
463 | * of only checking the first one. | |
3bad0781 | 464 | */ |
bcdb72ac | 465 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 466 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 467 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 468 | dev_priv->pch_id = id; |
3bad0781 | 469 | |
90711d50 JB |
470 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
471 | dev_priv->pch_type = PCH_IBX; | |
472 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 473 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 474 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
475 | dev_priv->pch_type = PCH_CPT; |
476 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 477 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
478 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
479 | /* PantherPoint is CPT compatible */ | |
480 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 481 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 482 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
483 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
484 | dev_priv->pch_type = PCH_LPT; | |
485 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
a35cc9d0 RV |
486 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
487 | WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); | |
e76e0634 BW |
488 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
489 | dev_priv->pch_type = PCH_LPT; | |
490 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
a35cc9d0 RV |
491 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
492 | WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); | |
e7e7ea20 S |
493 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
494 | dev_priv->pch_type = PCH_SPT; | |
495 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
ef11bdb3 RV |
496 | WARN_ON(!IS_SKYLAKE(dev) && |
497 | !IS_KABYLAKE(dev)); | |
e7e7ea20 S |
498 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
499 | dev_priv->pch_type = PCH_SPT; | |
500 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
ef11bdb3 RV |
501 | WARN_ON(!IS_SKYLAKE(dev) && |
502 | !IS_KABYLAKE(dev)); | |
39bfcd52 GH |
503 | } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) || |
504 | (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)) { | |
30c964a6 | 505 | dev_priv->pch_type = intel_virt_detect_pch(dev); |
bcdb72ac ID |
506 | } else |
507 | continue; | |
508 | ||
6a9c4b35 | 509 | break; |
3bad0781 | 510 | } |
3bad0781 | 511 | } |
6a9c4b35 | 512 | if (!pch) |
bcdb72ac ID |
513 | DRM_DEBUG_KMS("No PCH found.\n"); |
514 | ||
515 | pci_dev_put(pch); | |
3bad0781 ZW |
516 | } |
517 | ||
2911a35b BW |
518 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
519 | { | |
520 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 521 | return false; |
2911a35b | 522 | |
d330a953 JN |
523 | if (i915.semaphores >= 0) |
524 | return i915.semaphores; | |
2911a35b | 525 | |
71386ef9 OM |
526 | /* TODO: make semaphores and Execlists play nicely together */ |
527 | if (i915.enable_execlists) | |
528 | return false; | |
529 | ||
be71eabe RV |
530 | /* Until we get further testing... */ |
531 | if (IS_GEN8(dev)) | |
532 | return false; | |
533 | ||
59de3295 | 534 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 535 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
536 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
537 | return false; | |
538 | #endif | |
2911a35b | 539 | |
a08acaf2 | 540 | return true; |
2911a35b BW |
541 | } |
542 | ||
07f9cd0b ID |
543 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
544 | { | |
545 | struct drm_device *dev = dev_priv->dev; | |
546 | struct drm_encoder *encoder; | |
547 | ||
548 | drm_modeset_lock_all(dev); | |
549 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
550 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
551 | ||
552 | if (intel_encoder->suspend) | |
553 | intel_encoder->suspend(intel_encoder); | |
554 | } | |
555 | drm_modeset_unlock_all(dev); | |
556 | } | |
557 | ||
ebc32824 | 558 | static int intel_suspend_complete(struct drm_i915_private *dev_priv); |
1a5df187 PZ |
559 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
560 | bool rpm_resume); | |
a9a6b73a | 561 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv); |
f75a1985 | 562 | |
bc87229f ID |
563 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
564 | { | |
565 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
566 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
567 | return true; | |
568 | #endif | |
569 | return false; | |
570 | } | |
ebc32824 | 571 | |
5e365c39 | 572 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 573 | { |
61caf87c | 574 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5747e3a | 575 | pci_power_t opregion_target_state; |
d5818938 | 576 | int error; |
61caf87c | 577 | |
b8efb17b ZR |
578 | /* ignore lid events during suspend */ |
579 | mutex_lock(&dev_priv->modeset_restore_lock); | |
580 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
581 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
582 | ||
c67a470b PZ |
583 | /* We do a lot of poking in a lot of registers, make sure they work |
584 | * properly. */ | |
da7e29bd | 585 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 586 | |
5bcf719b DA |
587 | drm_kms_helper_poll_disable(dev); |
588 | ||
ba8bbcf6 | 589 | pci_save_state(dev->pdev); |
ba8bbcf6 | 590 | |
d5818938 DV |
591 | error = i915_gem_suspend(dev); |
592 | if (error) { | |
593 | dev_err(&dev->pdev->dev, | |
594 | "GEM idle failed, resume might fail\n"); | |
595 | return error; | |
596 | } | |
db1b76ca | 597 | |
a1c41994 AD |
598 | intel_guc_suspend(dev); |
599 | ||
d5818938 | 600 | intel_suspend_gt_powersave(dev); |
a261b246 | 601 | |
d5818938 DV |
602 | /* |
603 | * Disable CRTCs directly since we want to preserve sw state | |
604 | * for _thaw. Also, power gate the CRTC power wells. | |
605 | */ | |
606 | drm_modeset_lock_all(dev); | |
6b72d486 | 607 | intel_display_suspend(dev); |
d5818938 | 608 | drm_modeset_unlock_all(dev); |
2eb5252e | 609 | |
d5818938 | 610 | intel_dp_mst_suspend(dev); |
7d708ee4 | 611 | |
d5818938 DV |
612 | intel_runtime_pm_disable_interrupts(dev_priv); |
613 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 614 | |
d5818938 | 615 | intel_suspend_encoders(dev_priv); |
0e32b39c | 616 | |
d5818938 | 617 | intel_suspend_hw(dev); |
5669fcac | 618 | |
828c7908 BW |
619 | i915_gem_suspend_gtt_mappings(dev); |
620 | ||
9e06dd39 JB |
621 | i915_save_state(dev); |
622 | ||
bc87229f | 623 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
e5747e3a JB |
624 | intel_opregion_notify_adapter(dev, opregion_target_state); |
625 | ||
156c7ca0 | 626 | intel_uncore_forcewake_reset(dev, false); |
44834a67 | 627 | intel_opregion_fini(dev); |
8ee1c3db | 628 | |
82e3b8c1 | 629 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 630 | |
62d5d69b MK |
631 | dev_priv->suspend_count++; |
632 | ||
85e90679 KCA |
633 | intel_display_set_init_power(dev_priv, false); |
634 | ||
f514c2d8 ID |
635 | if (HAS_CSR(dev_priv)) |
636 | flush_work(&dev_priv->csr.work); | |
637 | ||
61caf87c | 638 | return 0; |
84b79f8d RW |
639 | } |
640 | ||
ab3be73f | 641 | static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) |
c3c09c95 ID |
642 | { |
643 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
bc87229f | 644 | bool fw_csr; |
c3c09c95 ID |
645 | int ret; |
646 | ||
bc87229f ID |
647 | fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; |
648 | /* | |
649 | * In case of firmware assisted context save/restore don't manually | |
650 | * deinit the power domains. This also means the CSR/DMC firmware will | |
651 | * stay active, it will power down any HW resources as required and | |
652 | * also enable deeper system power states that would be blocked if the | |
653 | * firmware was inactive. | |
654 | */ | |
655 | if (!fw_csr) | |
656 | intel_power_domains_suspend(dev_priv); | |
73dfc227 | 657 | |
c3c09c95 ID |
658 | ret = intel_suspend_complete(dev_priv); |
659 | ||
660 | if (ret) { | |
661 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
bc87229f ID |
662 | if (!fw_csr) |
663 | intel_power_domains_init_hw(dev_priv, true); | |
c3c09c95 ID |
664 | |
665 | return ret; | |
666 | } | |
667 | ||
668 | pci_disable_device(drm_dev->pdev); | |
ab3be73f | 669 | /* |
54875571 | 670 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
671 | * the device even though it's already in D3 and hang the machine. So |
672 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
673 | * power down the device properly. The issue was seen on multiple old |
674 | * GENs with different BIOS vendors, so having an explicit blacklist | |
675 | * is inpractical; apply the workaround on everything pre GEN6. The | |
676 | * platforms where the issue was seen: | |
677 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
678 | * Fujitsu FSC S7110 | |
679 | * Acer Aspire 1830T | |
ab3be73f | 680 | */ |
54875571 | 681 | if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) |
ab3be73f | 682 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); |
c3c09c95 | 683 | |
bc87229f ID |
684 | dev_priv->suspended_to_idle = suspend_to_idle(dev_priv); |
685 | ||
c3c09c95 ID |
686 | return 0; |
687 | } | |
688 | ||
1751fcf9 | 689 | int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
690 | { |
691 | int error; | |
692 | ||
693 | if (!dev || !dev->dev_private) { | |
694 | DRM_ERROR("dev: %p\n", dev); | |
695 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
696 | return -ENODEV; | |
697 | } | |
698 | ||
0b14cbd2 ID |
699 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
700 | state.event != PM_EVENT_FREEZE)) | |
701 | return -EINVAL; | |
5bcf719b DA |
702 | |
703 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
704 | return 0; | |
6eecba33 | 705 | |
5e365c39 | 706 | error = i915_drm_suspend(dev); |
84b79f8d RW |
707 | if (error) |
708 | return error; | |
709 | ||
ab3be73f | 710 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
711 | } |
712 | ||
5e365c39 | 713 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 ID |
714 | { |
715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9d49c0ef | 716 | |
d5818938 DV |
717 | mutex_lock(&dev->struct_mutex); |
718 | i915_gem_restore_gtt_mappings(dev); | |
719 | mutex_unlock(&dev->struct_mutex); | |
9d49c0ef | 720 | |
61caf87c | 721 | i915_restore_state(dev); |
44834a67 | 722 | intel_opregion_setup(dev); |
61caf87c | 723 | |
d5818938 DV |
724 | intel_init_pch_refclk(dev); |
725 | drm_mode_config_reset(dev); | |
1833b134 | 726 | |
364aece0 PA |
727 | /* |
728 | * Interrupts have to be enabled before any batches are run. If not the | |
729 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
730 | * update/restore the context. | |
731 | * | |
732 | * Modeset enabling in intel_modeset_init_hw() also needs working | |
733 | * interrupts. | |
734 | */ | |
735 | intel_runtime_pm_enable_interrupts(dev_priv); | |
736 | ||
d5818938 DV |
737 | mutex_lock(&dev->struct_mutex); |
738 | if (i915_gem_init_hw(dev)) { | |
739 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
805de8f4 | 740 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
d5818938 DV |
741 | } |
742 | mutex_unlock(&dev->struct_mutex); | |
226485e9 | 743 | |
a1c41994 AD |
744 | intel_guc_resume(dev); |
745 | ||
d5818938 | 746 | intel_modeset_init_hw(dev); |
24576d23 | 747 | |
d5818938 DV |
748 | spin_lock_irq(&dev_priv->irq_lock); |
749 | if (dev_priv->display.hpd_irq_setup) | |
750 | dev_priv->display.hpd_irq_setup(dev); | |
751 | spin_unlock_irq(&dev_priv->irq_lock); | |
0e32b39c | 752 | |
d5818938 | 753 | drm_modeset_lock_all(dev); |
043e9bda | 754 | intel_display_resume(dev); |
d5818938 | 755 | drm_modeset_unlock_all(dev); |
15239099 | 756 | |
d5818938 | 757 | intel_dp_mst_resume(dev); |
e7d6f7d7 | 758 | |
d5818938 DV |
759 | /* |
760 | * ... but also need to make sure that hotplug processing | |
761 | * doesn't cause havoc. Like in the driver load code we don't | |
762 | * bother with the tiny race here where we might loose hotplug | |
763 | * notifications. | |
764 | * */ | |
765 | intel_hpd_init(dev_priv); | |
766 | /* Config may have changed between suspend and resume */ | |
767 | drm_helper_hpd_irq_event(dev); | |
1daed3fb | 768 | |
44834a67 CW |
769 | intel_opregion_init(dev); |
770 | ||
82e3b8c1 | 771 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 772 | |
b8efb17b ZR |
773 | mutex_lock(&dev_priv->modeset_restore_lock); |
774 | dev_priv->modeset_restore = MODESET_DONE; | |
775 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 776 | |
e5747e3a JB |
777 | intel_opregion_notify_adapter(dev, PCI_D0); |
778 | ||
ee6f280e ID |
779 | drm_kms_helper_poll_enable(dev); |
780 | ||
074c6ada | 781 | return 0; |
84b79f8d RW |
782 | } |
783 | ||
5e365c39 | 784 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 785 | { |
36d61e67 | 786 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a5df187 | 787 | int ret = 0; |
36d61e67 | 788 | |
76c4b250 ID |
789 | /* |
790 | * We have a resume ordering issue with the snd-hda driver also | |
791 | * requiring our device to be power up. Due to the lack of a | |
792 | * parent/child relationship we currently solve this with an early | |
793 | * resume hook. | |
794 | * | |
795 | * FIXME: This should be solved with a special hdmi sink device or | |
796 | * similar so that power domains can be employed. | |
797 | */ | |
bc87229f ID |
798 | if (pci_enable_device(dev->pdev)) { |
799 | ret = -EIO; | |
800 | goto out; | |
801 | } | |
84b79f8d RW |
802 | |
803 | pci_set_master(dev->pdev); | |
804 | ||
666a4537 | 805 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 | 806 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 807 | if (ret) |
ff0b187f DL |
808 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
809 | ret); | |
36d61e67 ID |
810 | |
811 | intel_uncore_early_sanitize(dev, true); | |
efee833a | 812 | |
a9a6b73a DL |
813 | if (IS_BROXTON(dev)) |
814 | ret = bxt_resume_prepare(dev_priv); | |
a9a6b73a DL |
815 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
816 | hsw_disable_pc8(dev_priv); | |
efee833a | 817 | |
36d61e67 | 818 | intel_uncore_sanitize(dev); |
bc87229f ID |
819 | |
820 | if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) | |
821 | intel_power_domains_init_hw(dev_priv, true); | |
822 | ||
823 | out: | |
824 | dev_priv->suspended_to_idle = false; | |
36d61e67 ID |
825 | |
826 | return ret; | |
76c4b250 ID |
827 | } |
828 | ||
1751fcf9 | 829 | int i915_resume_switcheroo(struct drm_device *dev) |
76c4b250 | 830 | { |
50a0072f | 831 | int ret; |
76c4b250 | 832 | |
097dd837 ID |
833 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
834 | return 0; | |
835 | ||
5e365c39 | 836 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
837 | if (ret) |
838 | return ret; | |
839 | ||
5a17514e ID |
840 | return i915_drm_resume(dev); |
841 | } | |
842 | ||
11ed50ec | 843 | /** |
f3953dcb | 844 | * i915_reset - reset chip after a hang |
11ed50ec | 845 | * @dev: drm device to reset |
11ed50ec BG |
846 | * |
847 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
848 | * reset or otherwise an error code. | |
849 | * | |
850 | * Procedure is fairly simple: | |
851 | * - reset the chip using the reset reg | |
852 | * - re-init context state | |
853 | * - re-init hardware status page | |
854 | * - re-init ring buffer | |
855 | * - re-init interrupt state | |
856 | * - re-init display | |
857 | */ | |
d4b8bb2a | 858 | int i915_reset(struct drm_device *dev) |
11ed50ec | 859 | { |
50227e1c | 860 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 861 | bool simulated; |
0573ed4a | 862 | int ret; |
11ed50ec | 863 | |
dbea3cea ID |
864 | intel_reset_gt_powersave(dev); |
865 | ||
d54a02c0 | 866 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 867 | |
069efc1d | 868 | i915_gem_reset(dev); |
77f01230 | 869 | |
2e7c8ee7 CW |
870 | simulated = dev_priv->gpu_error.stop_rings != 0; |
871 | ||
be62acb4 MK |
872 | ret = intel_gpu_reset(dev); |
873 | ||
874 | /* Also reset the gpu hangman. */ | |
875 | if (simulated) { | |
876 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
877 | dev_priv->gpu_error.stop_rings = 0; | |
878 | if (ret == -ENODEV) { | |
f2d91a2c DV |
879 | DRM_INFO("Reset not implemented, but ignoring " |
880 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
881 | ret = 0; |
882 | } | |
2e7c8ee7 | 883 | } |
be62acb4 | 884 | |
d8f2716a DV |
885 | if (i915_stop_ring_allow_warn(dev_priv)) |
886 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); | |
887 | ||
0573ed4a | 888 | if (ret) { |
f2d91a2c | 889 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 890 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 891 | return ret; |
11ed50ec BG |
892 | } |
893 | ||
1362b776 VS |
894 | intel_overlay_reset(dev_priv); |
895 | ||
11ed50ec BG |
896 | /* Ok, now get things going again... */ |
897 | ||
898 | /* | |
899 | * Everything depends on having the GTT running, so we need to start | |
900 | * there. Fortunately we don't need to do this unless we reset the | |
901 | * chip at a PCI level. | |
902 | * | |
903 | * Next we need to restore the context, but we don't use those | |
904 | * yet either... | |
905 | * | |
906 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
907 | * was running at the time of the reset (i.e. we weren't VT | |
908 | * switched away). | |
909 | */ | |
6689c167 | 910 | |
33d30a9c DV |
911 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
912 | dev_priv->gpu_error.reload_in_reset = true; | |
6689c167 | 913 | |
33d30a9c | 914 | ret = i915_gem_init_hw(dev); |
6689c167 | 915 | |
33d30a9c | 916 | dev_priv->gpu_error.reload_in_reset = false; |
f817586c | 917 | |
33d30a9c DV |
918 | mutex_unlock(&dev->struct_mutex); |
919 | if (ret) { | |
920 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
921 | return ret; | |
11ed50ec BG |
922 | } |
923 | ||
33d30a9c DV |
924 | /* |
925 | * rps/rc6 re-init is necessary to restore state lost after the | |
926 | * reset and the re-install of gt irqs. Skip for ironlake per | |
927 | * previous concerns that it doesn't respond well to some forms | |
928 | * of re-init after reset. | |
929 | */ | |
930 | if (INTEL_INFO(dev)->gen > 5) | |
931 | intel_enable_gt_powersave(dev); | |
932 | ||
11ed50ec BG |
933 | return 0; |
934 | } | |
935 | ||
56550d94 | 936 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 937 | { |
01a06850 DV |
938 | struct intel_device_info *intel_info = |
939 | (struct intel_device_info *) ent->driver_data; | |
940 | ||
d330a953 | 941 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
942 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
943 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
944 | return -ENODEV; | |
945 | } | |
946 | ||
5fe49d86 CW |
947 | /* Only bind to function 0 of the device. Early generations |
948 | * used function 1 as a placeholder for multi-head. This causes | |
949 | * us confusion instead, especially on the systems where both | |
950 | * functions have the same PCI-ID! | |
951 | */ | |
952 | if (PCI_FUNC(pdev->devfn)) | |
953 | return -ENODEV; | |
954 | ||
dcdb1674 | 955 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
956 | } |
957 | ||
958 | static void | |
959 | i915_pci_remove(struct pci_dev *pdev) | |
960 | { | |
961 | struct drm_device *dev = pci_get_drvdata(pdev); | |
962 | ||
963 | drm_put_dev(dev); | |
964 | } | |
965 | ||
84b79f8d | 966 | static int i915_pm_suspend(struct device *dev) |
112b715e | 967 | { |
84b79f8d RW |
968 | struct pci_dev *pdev = to_pci_dev(dev); |
969 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 970 | |
84b79f8d RW |
971 | if (!drm_dev || !drm_dev->dev_private) { |
972 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
973 | return -ENODEV; | |
974 | } | |
112b715e | 975 | |
5bcf719b DA |
976 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
977 | return 0; | |
978 | ||
5e365c39 | 979 | return i915_drm_suspend(drm_dev); |
76c4b250 ID |
980 | } |
981 | ||
982 | static int i915_pm_suspend_late(struct device *dev) | |
983 | { | |
888d0d42 | 984 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 ID |
985 | |
986 | /* | |
c965d995 | 987 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
988 | * requiring our device to be power up. Due to the lack of a |
989 | * parent/child relationship we currently solve this with an late | |
990 | * suspend hook. | |
991 | * | |
992 | * FIXME: This should be solved with a special hdmi sink device or | |
993 | * similar so that power domains can be employed. | |
994 | */ | |
995 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
996 | return 0; | |
112b715e | 997 | |
ab3be73f ID |
998 | return i915_drm_suspend_late(drm_dev, false); |
999 | } | |
1000 | ||
1001 | static int i915_pm_poweroff_late(struct device *dev) | |
1002 | { | |
1003 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; | |
1004 | ||
1005 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1006 | return 0; | |
1007 | ||
1008 | return i915_drm_suspend_late(drm_dev, true); | |
cbda12d7 ZW |
1009 | } |
1010 | ||
76c4b250 ID |
1011 | static int i915_pm_resume_early(struct device *dev) |
1012 | { | |
888d0d42 | 1013 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 | 1014 | |
097dd837 ID |
1015 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1016 | return 0; | |
1017 | ||
5e365c39 | 1018 | return i915_drm_resume_early(drm_dev); |
76c4b250 ID |
1019 | } |
1020 | ||
84b79f8d | 1021 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 1022 | { |
888d0d42 | 1023 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
84b79f8d | 1024 | |
097dd837 ID |
1025 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1026 | return 0; | |
1027 | ||
5a17514e | 1028 | return i915_drm_resume(drm_dev); |
cbda12d7 ZW |
1029 | } |
1030 | ||
ebc32824 | 1031 | static int hsw_suspend_complete(struct drm_i915_private *dev_priv) |
97bea207 | 1032 | { |
414de7a0 | 1033 | hsw_enable_pc8(dev_priv); |
0ab9cfeb ID |
1034 | |
1035 | return 0; | |
97bea207 PZ |
1036 | } |
1037 | ||
31335cec SS |
1038 | static int bxt_suspend_complete(struct drm_i915_private *dev_priv) |
1039 | { | |
1040 | struct drm_device *dev = dev_priv->dev; | |
1041 | ||
1042 | /* TODO: when DC5 support is added disable DC5 here. */ | |
1043 | ||
1044 | broxton_ddi_phy_uninit(dev); | |
1045 | broxton_uninit_cdclk(dev); | |
1046 | bxt_enable_dc9(dev_priv); | |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv) | |
1052 | { | |
1053 | struct drm_device *dev = dev_priv->dev; | |
1054 | ||
1055 | /* TODO: when CSR FW support is added make sure the FW is loaded */ | |
1056 | ||
1057 | bxt_disable_dc9(dev_priv); | |
1058 | ||
1059 | /* | |
1060 | * TODO: when DC5 support is added enable DC5 here if the CSR FW | |
1061 | * is available. | |
1062 | */ | |
1063 | broxton_init_cdclk(dev); | |
1064 | broxton_ddi_phy_init(dev); | |
1065 | intel_prepare_ddi(dev); | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
ddeea5b0 ID |
1070 | /* |
1071 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
1072 | * S0i[R123] transition. The list of registers needing a save/restore is | |
1073 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
1074 | * registers in the following way: | |
1075 | * - Driver: saved/restored by the driver | |
1076 | * - Punit : saved/restored by the Punit firmware | |
1077 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
1078 | * used internally by the HW in a way that doesn't depend | |
1079 | * keeping the content across a suspend/resume. | |
1080 | * - Debug : used for debugging | |
1081 | * | |
1082 | * We save/restore all registers marked with 'Driver', with the following | |
1083 | * exceptions: | |
1084 | * - Registers out of use, including also registers marked with 'Debug'. | |
1085 | * These have no effect on the driver's operation, so we don't save/restore | |
1086 | * them to reduce the overhead. | |
1087 | * - Registers that are fully setup by an initialization function called from | |
1088 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1089 | * - Registers that provide the right functionality with their reset defaults. | |
1090 | * | |
1091 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1092 | * ignored, we save/restore all others, practically treating the HW context as | |
1093 | * a black-box for the driver. Further investigation is needed to reduce the | |
1094 | * saved/restored registers even further, by following the same 3 criteria. | |
1095 | */ | |
1096 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1097 | { | |
1098 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1099 | int i; | |
1100 | ||
1101 | /* GAM 0x4000-0x4770 */ | |
1102 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1103 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1104 | s->arb_mode = I915_READ(ARB_MODE); | |
1105 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1106 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1107 | ||
1108 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1109 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
1110 | |
1111 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 1112 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
1113 | |
1114 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1115 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1116 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1117 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1118 | ||
1119 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1120 | ||
1121 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1122 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1123 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1124 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1125 | ||
1126 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1127 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1128 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1129 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1130 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1131 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1132 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1133 | ||
1134 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1135 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1136 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1137 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1138 | s->ecobus = I915_READ(ECOBUS); | |
1139 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1140 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1141 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1142 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1143 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1144 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1145 | ||
1146 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1147 | s->gt_imr = I915_READ(GTIMR); | |
1148 | s->gt_ier = I915_READ(GTIER); | |
1149 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1150 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1151 | ||
1152 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1153 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
1154 | |
1155 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1156 | s->tilectl = I915_READ(TILECTL); | |
1157 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1158 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1159 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1160 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1161 | ||
1162 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1163 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1164 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 1165 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
1166 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
1167 | ||
1168 | /* | |
1169 | * Not saving any of: | |
1170 | * DFT, 0x9800-0x9EC0 | |
1171 | * SARB, 0xB000-0xB1FC | |
1172 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1173 | * PCI CFG | |
1174 | */ | |
1175 | } | |
1176 | ||
1177 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1178 | { | |
1179 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1180 | u32 val; | |
1181 | int i; | |
1182 | ||
1183 | /* GAM 0x4000-0x4770 */ | |
1184 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1185 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1186 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1187 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1188 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1189 | ||
1190 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1191 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
1192 | |
1193 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 1194 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
1195 | |
1196 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1197 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1198 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1199 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1200 | ||
1201 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1202 | ||
1203 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1204 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1205 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1206 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1207 | ||
1208 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1209 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1210 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1211 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1212 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1213 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1214 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1215 | ||
1216 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1217 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1218 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1219 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1220 | I915_WRITE(ECOBUS, s->ecobus); | |
1221 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1222 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1223 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1224 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1225 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1226 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1227 | ||
1228 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1229 | I915_WRITE(GTIMR, s->gt_imr); | |
1230 | I915_WRITE(GTIER, s->gt_ier); | |
1231 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1232 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1233 | ||
1234 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1235 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
1236 | |
1237 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1238 | I915_WRITE(TILECTL, s->tilectl); | |
1239 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1240 | /* | |
1241 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1242 | * be restored, as they are used to control the s0ix suspend/resume | |
1243 | * sequence by the caller. | |
1244 | */ | |
1245 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1246 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1247 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1248 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1249 | ||
1250 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1251 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1252 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1253 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1254 | ||
1255 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1256 | ||
1257 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1258 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1259 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 1260 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
1261 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
1262 | } | |
1263 | ||
650ad970 ID |
1264 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1265 | { | |
1266 | u32 val; | |
1267 | int err; | |
1268 | ||
650ad970 | 1269 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) |
650ad970 ID |
1270 | |
1271 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1272 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1273 | if (force_on) | |
1274 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1275 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1276 | ||
1277 | if (!force_on) | |
1278 | return 0; | |
1279 | ||
8d4eee9c | 1280 | err = wait_for(COND, 20); |
650ad970 ID |
1281 | if (err) |
1282 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1283 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1284 | ||
1285 | return err; | |
1286 | #undef COND | |
1287 | } | |
1288 | ||
ddeea5b0 ID |
1289 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1290 | { | |
1291 | u32 val; | |
1292 | int err = 0; | |
1293 | ||
1294 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1295 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1296 | if (allow) | |
1297 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1298 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1299 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1300 | ||
1301 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1302 | allow) | |
1303 | err = wait_for(COND, 1); | |
1304 | if (err) | |
1305 | DRM_ERROR("timeout disabling GT waking\n"); | |
1306 | return err; | |
1307 | #undef COND | |
1308 | } | |
1309 | ||
1310 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1311 | bool wait_for_on) | |
1312 | { | |
1313 | u32 mask; | |
1314 | u32 val; | |
1315 | int err; | |
1316 | ||
1317 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1318 | val = wait_for_on ? mask : 0; | |
1319 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1320 | if (COND) | |
1321 | return 0; | |
1322 | ||
1323 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
1324 | wait_for_on ? "on" : "off", | |
1325 | I915_READ(VLV_GTLC_PW_STATUS)); | |
1326 | ||
1327 | /* | |
1328 | * RC6 transitioning can be delayed up to 2 msec (see | |
1329 | * valleyview_enable_rps), use 3 msec for safety. | |
1330 | */ | |
1331 | err = wait_for(COND, 3); | |
1332 | if (err) | |
1333 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
1334 | wait_for_on ? "on" : "off"); | |
1335 | ||
1336 | return err; | |
1337 | #undef COND | |
1338 | } | |
1339 | ||
1340 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1341 | { | |
1342 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1343 | return; | |
1344 | ||
1345 | DRM_ERROR("GT register access while GT waking disabled\n"); | |
1346 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); | |
1347 | } | |
1348 | ||
ebc32824 | 1349 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
1350 | { |
1351 | u32 mask; | |
1352 | int err; | |
1353 | ||
1354 | /* | |
1355 | * Bspec defines the following GT well on flags as debug only, so | |
1356 | * don't treat them as hard failures. | |
1357 | */ | |
1358 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1359 | ||
1360 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1361 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1362 | ||
1363 | vlv_check_no_gt_access(dev_priv); | |
1364 | ||
1365 | err = vlv_force_gfx_clock(dev_priv, true); | |
1366 | if (err) | |
1367 | goto err1; | |
1368 | ||
1369 | err = vlv_allow_gt_wake(dev_priv, false); | |
1370 | if (err) | |
1371 | goto err2; | |
98711167 D |
1372 | |
1373 | if (!IS_CHERRYVIEW(dev_priv->dev)) | |
1374 | vlv_save_gunit_s0ix_state(dev_priv); | |
ddeea5b0 ID |
1375 | |
1376 | err = vlv_force_gfx_clock(dev_priv, false); | |
1377 | if (err) | |
1378 | goto err2; | |
1379 | ||
1380 | return 0; | |
1381 | ||
1382 | err2: | |
1383 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1384 | vlv_allow_gt_wake(dev_priv, true); | |
1385 | err1: | |
1386 | vlv_force_gfx_clock(dev_priv, false); | |
1387 | ||
1388 | return err; | |
1389 | } | |
1390 | ||
016970be SK |
1391 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1392 | bool rpm_resume) | |
ddeea5b0 ID |
1393 | { |
1394 | struct drm_device *dev = dev_priv->dev; | |
1395 | int err; | |
1396 | int ret; | |
1397 | ||
1398 | /* | |
1399 | * If any of the steps fail just try to continue, that's the best we | |
1400 | * can do at this point. Return the first error code (which will also | |
1401 | * leave RPM permanently disabled). | |
1402 | */ | |
1403 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1404 | ||
98711167 D |
1405 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
1406 | vlv_restore_gunit_s0ix_state(dev_priv); | |
ddeea5b0 ID |
1407 | |
1408 | err = vlv_allow_gt_wake(dev_priv, true); | |
1409 | if (!ret) | |
1410 | ret = err; | |
1411 | ||
1412 | err = vlv_force_gfx_clock(dev_priv, false); | |
1413 | if (!ret) | |
1414 | ret = err; | |
1415 | ||
1416 | vlv_check_no_gt_access(dev_priv); | |
1417 | ||
016970be SK |
1418 | if (rpm_resume) { |
1419 | intel_init_clock_gating(dev); | |
1420 | i915_gem_restore_fences(dev); | |
1421 | } | |
ddeea5b0 ID |
1422 | |
1423 | return ret; | |
1424 | } | |
1425 | ||
97bea207 | 1426 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1427 | { |
1428 | struct pci_dev *pdev = to_pci_dev(device); | |
1429 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1431 | int ret; |
8a187455 | 1432 | |
aeab0b5a | 1433 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1434 | return -ENODEV; |
1435 | ||
604effb7 ID |
1436 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1437 | return -ENODEV; | |
1438 | ||
8a187455 PZ |
1439 | DRM_DEBUG_KMS("Suspending device\n"); |
1440 | ||
d6102977 ID |
1441 | /* |
1442 | * We could deadlock here in case another thread holding struct_mutex | |
1443 | * calls RPM suspend concurrently, since the RPM suspend will wait | |
1444 | * first for this RPM suspend to finish. In this case the concurrent | |
1445 | * RPM resume will be followed by its RPM suspend counterpart. Still | |
1446 | * for consistency return -EAGAIN, which will reschedule this suspend. | |
1447 | */ | |
1448 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1449 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); | |
1450 | /* | |
1451 | * Bump the expiration timestamp, otherwise the suspend won't | |
1452 | * be rescheduled. | |
1453 | */ | |
1454 | pm_runtime_mark_last_busy(device); | |
1455 | ||
1456 | return -EAGAIN; | |
1457 | } | |
1458 | /* | |
1459 | * We are safe here against re-faults, since the fault handler takes | |
1460 | * an RPM reference. | |
1461 | */ | |
1462 | i915_gem_release_all_mmaps(dev_priv); | |
1463 | mutex_unlock(&dev->struct_mutex); | |
1464 | ||
825f2728 JL |
1465 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
1466 | ||
a1c41994 AD |
1467 | intel_guc_suspend(dev); |
1468 | ||
fac6adb0 | 1469 | intel_suspend_gt_powersave(dev); |
2eb5252e | 1470 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 1471 | |
ebc32824 | 1472 | ret = intel_suspend_complete(dev_priv); |
0ab9cfeb ID |
1473 | if (ret) { |
1474 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
b963291c | 1475 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb ID |
1476 | |
1477 | return ret; | |
1478 | } | |
a8a8bd54 | 1479 | |
dc9fb09c | 1480 | intel_uncore_forcewake_reset(dev, false); |
8a187455 | 1481 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1482 | |
1483 | /* | |
c8a0bd42 PZ |
1484 | * FIXME: We really should find a document that references the arguments |
1485 | * used below! | |
1fb2362b | 1486 | */ |
d37ae19a PZ |
1487 | if (IS_BROADWELL(dev)) { |
1488 | /* | |
1489 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
1490 | * being detected, and the call we do at intel_runtime_resume() | |
1491 | * won't be able to restore them. Since PCI_D3hot matches the | |
1492 | * actual specification and appears to be working, use it. | |
1493 | */ | |
1494 | intel_opregion_notify_adapter(dev, PCI_D3hot); | |
1495 | } else { | |
c8a0bd42 PZ |
1496 | /* |
1497 | * current versions of firmware which depend on this opregion | |
1498 | * notification have repurposed the D1 definition to mean | |
1499 | * "runtime suspended" vs. what you would normally expect (D3) | |
1500 | * to distinguish it from notifications that might be sent via | |
1501 | * the suspend path. | |
1502 | */ | |
1503 | intel_opregion_notify_adapter(dev, PCI_D1); | |
c8a0bd42 | 1504 | } |
8a187455 | 1505 | |
59bad947 | 1506 | assert_forcewakes_inactive(dev_priv); |
dc9fb09c | 1507 | |
a8a8bd54 | 1508 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1509 | return 0; |
1510 | } | |
1511 | ||
97bea207 | 1512 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1513 | { |
1514 | struct pci_dev *pdev = to_pci_dev(device); | |
1515 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1a5df187 | 1517 | int ret = 0; |
8a187455 | 1518 | |
604effb7 ID |
1519 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1520 | return -ENODEV; | |
8a187455 PZ |
1521 | |
1522 | DRM_DEBUG_KMS("Resuming device\n"); | |
1523 | ||
cd2e9e90 | 1524 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 PZ |
1525 | dev_priv->pm.suspended = false; |
1526 | ||
a1c41994 AD |
1527 | intel_guc_resume(dev); |
1528 | ||
1a5df187 PZ |
1529 | if (IS_GEN6(dev_priv)) |
1530 | intel_init_pch_refclk(dev); | |
31335cec SS |
1531 | |
1532 | if (IS_BROXTON(dev)) | |
1533 | ret = bxt_resume_prepare(dev_priv); | |
1a5df187 PZ |
1534 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
1535 | hsw_disable_pc8(dev_priv); | |
666a4537 | 1536 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 PZ |
1537 | ret = vlv_resume_prepare(dev_priv, true); |
1538 | ||
0ab9cfeb ID |
1539 | /* |
1540 | * No point of rolling back things in case of an error, as the best | |
1541 | * we can do is to hope that things will still work (and disable RPM). | |
1542 | */ | |
92b806d3 ID |
1543 | i915_gem_init_swizzling(dev); |
1544 | gen6_update_ring_freq(dev); | |
1545 | ||
b963291c | 1546 | intel_runtime_pm_enable_interrupts(dev_priv); |
08d8a232 VS |
1547 | |
1548 | /* | |
1549 | * On VLV/CHV display interrupts are part of the display | |
1550 | * power well, so hpd is reinitialized from there. For | |
1551 | * everyone else do it here. | |
1552 | */ | |
666a4537 | 1553 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
08d8a232 VS |
1554 | intel_hpd_init(dev_priv); |
1555 | ||
fac6adb0 | 1556 | intel_enable_gt_powersave(dev); |
b5478bcd | 1557 | |
0ab9cfeb ID |
1558 | if (ret) |
1559 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1560 | else | |
1561 | DRM_DEBUG_KMS("Device resumed\n"); | |
1562 | ||
1563 | return ret; | |
8a187455 PZ |
1564 | } |
1565 | ||
016970be SK |
1566 | /* |
1567 | * This function implements common functionality of runtime and system | |
1568 | * suspend sequence. | |
1569 | */ | |
ebc32824 SK |
1570 | static int intel_suspend_complete(struct drm_i915_private *dev_priv) |
1571 | { | |
ebc32824 SK |
1572 | int ret; |
1573 | ||
16e44e3e | 1574 | if (IS_BROXTON(dev_priv)) |
31335cec | 1575 | ret = bxt_suspend_complete(dev_priv); |
16e44e3e | 1576 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ebc32824 | 1577 | ret = hsw_suspend_complete(dev_priv); |
666a4537 | 1578 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
ebc32824 | 1579 | ret = vlv_suspend_complete(dev_priv); |
604effb7 ID |
1580 | else |
1581 | ret = 0; | |
ebc32824 SK |
1582 | |
1583 | return ret; | |
1584 | } | |
1585 | ||
b4b78d12 | 1586 | static const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
1587 | /* |
1588 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
1589 | * PMSG_RESUME] | |
1590 | */ | |
0206e353 | 1591 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1592 | .suspend_late = i915_pm_suspend_late, |
1593 | .resume_early = i915_pm_resume_early, | |
0206e353 | 1594 | .resume = i915_pm_resume, |
5545dbbf ID |
1595 | |
1596 | /* | |
1597 | * S4 event handlers | |
1598 | * @freeze, @freeze_late : called (1) before creating the | |
1599 | * hibernation image [PMSG_FREEZE] and | |
1600 | * (2) after rebooting, before restoring | |
1601 | * the image [PMSG_QUIESCE] | |
1602 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
1603 | * image, before writing it [PMSG_THAW] | |
1604 | * and (2) after failing to create or | |
1605 | * restore the image [PMSG_RECOVER] | |
1606 | * @poweroff, @poweroff_late: called after writing the hibernation | |
1607 | * image, before rebooting [PMSG_HIBERNATE] | |
1608 | * @restore, @restore_early : called after rebooting and restoring the | |
1609 | * hibernation image [PMSG_RESTORE] | |
1610 | */ | |
36d61e67 ID |
1611 | .freeze = i915_pm_suspend, |
1612 | .freeze_late = i915_pm_suspend_late, | |
1613 | .thaw_early = i915_pm_resume_early, | |
1614 | .thaw = i915_pm_resume, | |
1615 | .poweroff = i915_pm_suspend, | |
ab3be73f | 1616 | .poweroff_late = i915_pm_poweroff_late, |
76c4b250 | 1617 | .restore_early = i915_pm_resume_early, |
0206e353 | 1618 | .restore = i915_pm_resume, |
5545dbbf ID |
1619 | |
1620 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
1621 | .runtime_suspend = intel_runtime_suspend, |
1622 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1623 | }; |
1624 | ||
78b68556 | 1625 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1626 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1627 | .open = drm_gem_vm_open, |
1628 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1629 | }; |
1630 | ||
e08e96de AV |
1631 | static const struct file_operations i915_driver_fops = { |
1632 | .owner = THIS_MODULE, | |
1633 | .open = drm_open, | |
1634 | .release = drm_release, | |
1635 | .unlocked_ioctl = drm_ioctl, | |
1636 | .mmap = drm_gem_mmap, | |
1637 | .poll = drm_poll, | |
e08e96de AV |
1638 | .read = drm_read, |
1639 | #ifdef CONFIG_COMPAT | |
1640 | .compat_ioctl = i915_compat_ioctl, | |
1641 | #endif | |
1642 | .llseek = noop_llseek, | |
1643 | }; | |
1644 | ||
1da177e4 | 1645 | static struct drm_driver driver = { |
0c54781b MW |
1646 | /* Don't use MTRRs here; the Xserver or userspace app should |
1647 | * deal with them for Intel hardware. | |
792d2b9a | 1648 | */ |
673a394b | 1649 | .driver_features = |
10ba5012 | 1650 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1751fcf9 | 1651 | DRIVER_RENDER | DRIVER_MODESET, |
22eae947 | 1652 | .load = i915_driver_load, |
ba8bbcf6 | 1653 | .unload = i915_driver_unload, |
673a394b | 1654 | .open = i915_driver_open, |
22eae947 DA |
1655 | .lastclose = i915_driver_lastclose, |
1656 | .preclose = i915_driver_preclose, | |
673a394b | 1657 | .postclose = i915_driver_postclose, |
915b4d11 | 1658 | .set_busid = drm_pci_set_busid, |
d8e29209 | 1659 | |
955b12de | 1660 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1661 | .debugfs_init = i915_debugfs_init, |
1662 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1663 | #endif |
673a394b | 1664 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1665 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1666 | |
1667 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1668 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1669 | .gem_prime_export = i915_gem_prime_export, | |
1670 | .gem_prime_import = i915_gem_prime_import, | |
1671 | ||
ff72145b | 1672 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 1673 | .dumb_map_offset = i915_gem_mmap_gtt, |
43387b37 | 1674 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1675 | .ioctls = i915_ioctls, |
e08e96de | 1676 | .fops = &i915_driver_fops, |
22eae947 DA |
1677 | .name = DRIVER_NAME, |
1678 | .desc = DRIVER_DESC, | |
1679 | .date = DRIVER_DATE, | |
1680 | .major = DRIVER_MAJOR, | |
1681 | .minor = DRIVER_MINOR, | |
1682 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1683 | }; |
1684 | ||
8410ea3b DA |
1685 | static struct pci_driver i915_pci_driver = { |
1686 | .name = DRIVER_NAME, | |
1687 | .id_table = pciidlist, | |
1688 | .probe = i915_pci_probe, | |
1689 | .remove = i915_pci_remove, | |
1690 | .driver.pm = &i915_pm_ops, | |
1691 | }; | |
1692 | ||
1da177e4 LT |
1693 | static int __init i915_init(void) |
1694 | { | |
1695 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1696 | |
1697 | /* | |
fd930478 CW |
1698 | * Enable KMS by default, unless explicitly overriden by |
1699 | * either the i915.modeset prarameter or by the | |
1700 | * vga_text_mode_force boot option. | |
79e53945 | 1701 | */ |
fd930478 CW |
1702 | |
1703 | if (i915.modeset == 0) | |
1704 | driver.driver_features &= ~DRIVER_MODESET; | |
79e53945 JB |
1705 | |
1706 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 1707 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
1708 | driver.driver_features &= ~DRIVER_MODESET; |
1709 | #endif | |
1710 | ||
b30324ad | 1711 | if (!(driver.driver_features & DRIVER_MODESET)) { |
b30324ad | 1712 | /* Silently fail loading to not upset userspace. */ |
c9cd7b65 | 1713 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
b30324ad | 1714 | return 0; |
b30324ad | 1715 | } |
3885c6bb | 1716 | |
c5b852f3 | 1717 | if (i915.nuclear_pageflip) |
b2e7723b MR |
1718 | driver.driver_features |= DRIVER_ATOMIC; |
1719 | ||
8410ea3b | 1720 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1721 | } |
1722 | ||
1723 | static void __exit i915_exit(void) | |
1724 | { | |
b33ecdd1 DV |
1725 | if (!(driver.driver_features & DRIVER_MODESET)) |
1726 | return; /* Never loaded a driver. */ | |
b33ecdd1 | 1727 | |
8410ea3b | 1728 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1729 | } |
1730 | ||
1731 | module_init(i915_init); | |
1732 | module_exit(i915_exit); | |
1733 | ||
0a6d1631 | 1734 | MODULE_AUTHOR("Tungsten Graphics, Inc."); |
1eab9234 | 1735 | MODULE_AUTHOR("Intel Corporation"); |
0a6d1631 | 1736 | |
b5e89ed5 | 1737 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 | 1738 | MODULE_LICENSE("GPL and additional rights"); |