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drm/i915: Restore nonblocking awaits for modesetting
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
0673ad47
CW		 46#include <drm/i915_drm.h>
47
48#include "i915_drv.h"
49#include "i915_trace.h"
50#include "i915_vgpu.h"
51#include "intel_drv.h"
79e53945 52
112b715e
KH		 53static struct drm_driver driver;
54
0673ad47
CW		 55static unsigned int i915_load_fail_count;
56
57bool __i915_inject_load_failure(const char *func, int line)
58{
59 if (i915_load_fail_count >= i915.inject_load_failure)
60 return false;
61
62 if (++i915_load_fail_count == i915.inject_load_failure) {
63 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
64 i915.inject_load_failure, func, line);
65 return true;
66 }
67
68 return false;
69}
70
71#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
72#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
73 "providing the dmesg log by booting with drm.debug=0xf"
74
75void
76__i915_printk(struct drm_i915_private *dev_priv, const char *level,
77 const char *fmt, ...)
78{
79 static bool shown_bug_once;
c49d13ee 80 struct device *kdev = dev_priv->drm.dev;
0673ad47
CW		 81 bool is_error = level[1] <= KERN_ERR[1];
82 bool is_debug = level[1] == KERN_DEBUG[1];
83 struct va_format vaf;
84 va_list args;
85
86 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
87 return;
88
89 va_start(args, fmt);
90
91 vaf.fmt = fmt;
92 vaf.va = &args;
93
c49d13ee 94 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
0673ad47
CW		 95 __builtin_return_address(0), &vaf);
96
97 if (is_error && !shown_bug_once) {
c49d13ee 98 dev_notice(kdev, "%s", FDO_BUG_MSG);
0673ad47
CW		 99 shown_bug_once = true;
100 }
101
102 va_end(args);
103}
104
105static bool i915_error_injected(struct drm_i915_private *dev_priv)
106{
107 return i915.inject_load_failure &&
108 i915_load_fail_count == i915.inject_load_failure;
109}
110
111#define i915_load_error(dev_priv, fmt, ...) \
112 __i915_printk(dev_priv, \
113 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
114 fmt, ##__VA_ARGS__)
115
116
fd6b8f43 117static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
0673ad47
CW		 118{
119 enum intel_pch ret = PCH_NOP;
120
121 /*
122 * In a virtualized passthrough environment we can be in a
123 * setup where the ISA bridge is not able to be passed through.
124 * In this case, a south bridge can be emulated and we have to
125 * make an educated guess as to which PCH is really there.
126 */
127
fd6b8f43 128 if (IS_GEN5(dev_priv)) {
0673ad47
CW		 129 ret = PCH_IBX;
130 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
fd6b8f43 131 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
0673ad47
CW		 132 ret = PCH_CPT;
133 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
fd6b8f43 134 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0673ad47
CW		 135 ret = PCH_LPT;
136 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
fd6b8f43 137 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
0673ad47
CW		 138 ret = PCH_SPT;
139 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
140 }
141
142 return ret;
143}
144
145static void intel_detect_pch(struct drm_device *dev)
146{
fac5e23e 147 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 148 struct pci_dev *pch = NULL;
149
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
152 */
153 if (INTEL_INFO(dev)->num_pipes == 0) {
154 dev_priv->pch_type = PCH_NOP;
155 return;
156 }
157
158 /*
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
163 *
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
168 */
169 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
170 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
171 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
172 dev_priv->pch_id = id;
173
174 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
175 dev_priv->pch_type = PCH_IBX;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
5db94019 177 WARN_ON(!IS_GEN5(dev_priv));
0673ad47
CW		 178 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
179 dev_priv->pch_type = PCH_CPT;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
fd6b8f43
TU		 181 WARN_ON(!(IS_GEN6(dev_priv) ||
182 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 183 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
184 /* PantherPoint is CPT compatible */
185 dev_priv->pch_type = PCH_CPT;
186 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
fd6b8f43
TU		 187 WARN_ON(!(IS_GEN6(dev_priv) ||
188 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 189 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
190 dev_priv->pch_type = PCH_LPT;
191 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
8652744b
TU		 192 WARN_ON(!IS_HASWELL(dev_priv) &&
193 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 194 WARN_ON(IS_HSW_ULT(dev_priv) ||
195 IS_BDW_ULT(dev_priv));
0673ad47
CW		 196 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
197 dev_priv->pch_type = PCH_LPT;
198 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
8652744b
TU		 199 WARN_ON(!IS_HASWELL(dev_priv) &&
200 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 201 WARN_ON(!IS_HSW_ULT(dev_priv) &&
202 !IS_BDW_ULT(dev_priv));
0673ad47
CW		 203 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
204 dev_priv->pch_type = PCH_SPT;
205 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
0853723b
TU		 206 WARN_ON(!IS_SKYLAKE(dev_priv) &&
207 !IS_KABYLAKE(dev_priv));
0673ad47
CW		 208 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
209 dev_priv->pch_type = PCH_SPT;
210 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
0853723b
TU		 211 WARN_ON(!IS_SKYLAKE(dev_priv) &&
212 !IS_KABYLAKE(dev_priv));
22dea0be
RV		 213 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
214 dev_priv->pch_type = PCH_KBP;
215 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
0853723b 216 WARN_ON(!IS_KABYLAKE(dev_priv));
0673ad47
CW		 217 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
218 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
219 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
220 pch->subsystem_vendor ==
221 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
222 pch->subsystem_device ==
223 PCI_SUBDEVICE_ID_QEMU)) {
fd6b8f43
TU		 224 dev_priv->pch_type =
225 intel_virt_detect_pch(dev_priv);
0673ad47
CW		 226 } else
227 continue;
228
229 break;
230 }
231 }
232 if (!pch)
233 DRM_DEBUG_KMS("No PCH found.\n");
234
235 pci_dev_put(pch);
236}
237
0673ad47
CW		 238static int i915_getparam(struct drm_device *dev, void *data,
239 struct drm_file *file_priv)
240{
fac5e23e 241 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 242 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 243 drm_i915_getparam_t *param = data;
244 int value;
245
246 switch (param->param) {
247 case I915_PARAM_IRQ_ACTIVE:
248 case I915_PARAM_ALLOW_BATCHBUFFER:
249 case I915_PARAM_LAST_DISPATCH:
250 /* Reject all old ums/dri params. */
251 return -ENODEV;
252 case I915_PARAM_CHIPSET_ID:
52a05c30 253 value = pdev->device;
0673ad47
CW		 254 break;
255 case I915_PARAM_REVISION:
52a05c30 256 value = pdev->revision;
0673ad47 257 break;
0673ad47
CW		 258 case I915_PARAM_NUM_FENCES_AVAIL:
259 value = dev_priv->num_fence_regs;
260 break;
261 case I915_PARAM_HAS_OVERLAY:
262 value = dev_priv->overlay ? 1 : 0;
263 break;
0673ad47 264 case I915_PARAM_HAS_BSD:
3b3f1650 265 value = !!dev_priv->engine[VCS];
0673ad47
CW		 266 break;
267 case I915_PARAM_HAS_BLT:
3b3f1650 268 value = !!dev_priv->engine[BCS];
0673ad47
CW		 269 break;
270 case I915_PARAM_HAS_VEBOX:
3b3f1650 271 value = !!dev_priv->engine[VECS];
0673ad47
CW		 272 break;
273 case I915_PARAM_HAS_BSD2:
3b3f1650 274 value = !!dev_priv->engine[VCS2];
0673ad47 275 break;
0673ad47 276 case I915_PARAM_HAS_EXEC_CONSTANTS:
16162470 277 value = INTEL_GEN(dev_priv) >= 4;
0673ad47
CW		 278 break;
279 case I915_PARAM_HAS_LLC:
16162470 280 value = HAS_LLC(dev_priv);
0673ad47
CW		 281 break;
282 case I915_PARAM_HAS_WT:
16162470 283 value = HAS_WT(dev_priv);
0673ad47
CW		 284 break;
285 case I915_PARAM_HAS_ALIASING_PPGTT:
16162470 286 value = USES_PPGTT(dev_priv);
0673ad47
CW		 287 break;
288 case I915_PARAM_HAS_SEMAPHORES:
39df9190 289 value = i915.semaphores;
0673ad47 290 break;
0673ad47
CW		 291 case I915_PARAM_HAS_SECURE_BATCHES:
292 value = capable(CAP_SYS_ADMIN);
293 break;
0673ad47
CW		 294 case I915_PARAM_CMD_PARSER_VERSION:
295 value = i915_cmd_parser_get_version(dev_priv);
296 break;
0673ad47 297 case I915_PARAM_SUBSLICE_TOTAL:
57ec171e 298 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
0673ad47
CW		 299 if (!value)
300 return -ENODEV;
301 break;
302 case I915_PARAM_EU_TOTAL:
43b67998 303 value = INTEL_INFO(dev_priv)->sseu.eu_total;
0673ad47
CW		 304 if (!value)
305 return -ENODEV;
306 break;
307 case I915_PARAM_HAS_GPU_RESET:
308 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
309 break;
310 case I915_PARAM_HAS_RESOURCE_STREAMER:
16162470 311 value = HAS_RESOURCE_STREAMER(dev_priv);
0673ad47 312 break;
37f501af 313 case I915_PARAM_HAS_POOLED_EU:
16162470 314 value = HAS_POOLED_EU(dev_priv);
37f501af 315 break;
316 case I915_PARAM_MIN_EU_IN_POOL:
43b67998 317 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
37f501af 318 break;
4cc69075
CW		 319 case I915_PARAM_MMAP_GTT_VERSION:
320 /* Though we've started our numbering from 1, and so class all
321 * earlier versions as 0, in effect their value is undefined as
322 * the ioctl will report EINVAL for the unknown param!
323 */
324 value = i915_gem_mmap_gtt_version();
325 break;
16162470
DW		 326 case I915_PARAM_MMAP_VERSION:
327 /* Remember to bump this if the version changes! */
328 case I915_PARAM_HAS_GEM:
329 case I915_PARAM_HAS_PAGEFLIPPING:
330 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
331 case I915_PARAM_HAS_RELAXED_FENCING:
332 case I915_PARAM_HAS_COHERENT_RINGS:
333 case I915_PARAM_HAS_RELAXED_DELTA:
334 case I915_PARAM_HAS_GEN7_SOL_RESET:
335 case I915_PARAM_HAS_WAIT_TIMEOUT:
336 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
337 case I915_PARAM_HAS_PINNED_BATCHES:
338 case I915_PARAM_HAS_EXEC_NO_RELOC:
339 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
340 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
341 case I915_PARAM_HAS_EXEC_SOFTPIN:
342 /* For the time being all of these are always true;
343 * if some supported hardware does not have one of these
344 * features this value needs to be provided from
345 * INTEL_INFO(), a feature macro, or similar.
346 */
347 value = 1;
348 break;
0673ad47
CW		 349 default:
350 DRM_DEBUG("Unknown parameter %d\n", param->param);
351 return -EINVAL;
352 }
353
dda33009 354 if (put_user(value, param->value))
0673ad47 355 return -EFAULT;
0673ad47
CW		 356
357 return 0;
358}
359
360static int i915_get_bridge_dev(struct drm_device *dev)
361{
fac5e23e 362 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 363
364 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
365 if (!dev_priv->bridge_dev) {
366 DRM_ERROR("bridge device not found\n");
367 return -1;
368 }
369 return 0;
370}
371
372/* Allocate space for the MCH regs if needed, return nonzero on error */
373static int
374intel_alloc_mchbar_resource(struct drm_device *dev)
375{
fac5e23e 376 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 377 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
378 u32 temp_lo, temp_hi = 0;
379 u64 mchbar_addr;
380 int ret;
381
382 if (INTEL_INFO(dev)->gen >= 4)
383 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
384 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
385 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
386
387 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
388#ifdef CONFIG_PNP
389 if (mchbar_addr &&
390 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
391 return 0;
392#endif
393
394 /* Get some space for it */
395 dev_priv->mch_res.name = "i915 MCHBAR";
396 dev_priv->mch_res.flags = IORESOURCE_MEM;
397 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
398 &dev_priv->mch_res,
399 MCHBAR_SIZE, MCHBAR_SIZE,
400 PCIBIOS_MIN_MEM,
401 0, pcibios_align_resource,
402 dev_priv->bridge_dev);
403 if (ret) {
404 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
405 dev_priv->mch_res.start = 0;
406 return ret;
407 }
408
409 if (INTEL_INFO(dev)->gen >= 4)
410 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
411 upper_32_bits(dev_priv->mch_res.start));
412
413 pci_write_config_dword(dev_priv->bridge_dev, reg,
414 lower_32_bits(dev_priv->mch_res.start));
415 return 0;
416}
417
418/* Setup MCHBAR if possible, return true if we should disable it again */
419static void
420intel_setup_mchbar(struct drm_device *dev)
421{
fac5e23e 422 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 423 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
424 u32 temp;
425 bool enabled;
426
920a14b2 427 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0673ad47
CW		 428 return;
429
430 dev_priv->mchbar_need_disable = false;
431
50a0bc90 432 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 433 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
434 enabled = !!(temp & DEVEN_MCHBAR_EN);
435 } else {
436 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
437 enabled = temp & 1;
438 }
439
440 /* If it's already enabled, don't have to do anything */
441 if (enabled)
442 return;
443
444 if (intel_alloc_mchbar_resource(dev))
445 return;
446
447 dev_priv->mchbar_need_disable = true;
448
449 /* Space is allocated or reserved, so enable it. */
50a0bc90 450 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 451 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
452 temp | DEVEN_MCHBAR_EN);
453 } else {
454 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
455 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
456 }
457}
458
459static void
460intel_teardown_mchbar(struct drm_device *dev)
461{
fac5e23e 462 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 463 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
464
465 if (dev_priv->mchbar_need_disable) {
50a0bc90 466 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 467 u32 deven_val;
468
469 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
470 &deven_val);
471 deven_val &= ~DEVEN_MCHBAR_EN;
472 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
473 deven_val);
474 } else {
475 u32 mchbar_val;
476
477 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
478 &mchbar_val);
479 mchbar_val &= ~1;
480 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
481 mchbar_val);
482 }
483 }
484
485 if (dev_priv->mch_res.start)
486 release_resource(&dev_priv->mch_res);
487}
488
489/* true = enable decode, false = disable decoder */
490static unsigned int i915_vga_set_decode(void *cookie, bool state)
491{
492 struct drm_device *dev = cookie;
493
494 intel_modeset_vga_set_state(dev, state);
495 if (state)
496 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
497 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
498 else
499 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
500}
501
502static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
503{
504 struct drm_device *dev = pci_get_drvdata(pdev);
505 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
506
507 if (state == VGA_SWITCHEROO_ON) {
508 pr_info("switched on\n");
509 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
510 /* i915 resume handler doesn't set to D0 */
52a05c30 511 pci_set_power_state(pdev, PCI_D0);
0673ad47
CW		 512 i915_resume_switcheroo(dev);
513 dev->switch_power_state = DRM_SWITCH_POWER_ON;
514 } else {
515 pr_info("switched off\n");
516 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
517 i915_suspend_switcheroo(dev, pmm);
518 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
519 }
520}
521
522static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
523{
524 struct drm_device *dev = pci_get_drvdata(pdev);
525
526 /*
527 * FIXME: open_count is protected by drm_global_mutex but that would lead to
528 * locking inversion with the driver load path. And the access here is
529 * completely racy anyway. So don't bother with locking for now.
530 */
531 return dev->open_count == 0;
532}
533
534static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
535 .set_gpu_state = i915_switcheroo_set_state,
536 .reprobe = NULL,
537 .can_switch = i915_switcheroo_can_switch,
538};
539
fbbd37b3 540static void i915_gem_fini(struct drm_i915_private *dev_priv)
0673ad47 541{
fbbd37b3
CW		 542 mutex_lock(&dev_priv->drm.struct_mutex);
543 i915_gem_cleanup_engines(&dev_priv->drm);
544 i915_gem_context_fini(&dev_priv->drm);
545 mutex_unlock(&dev_priv->drm.struct_mutex);
0673ad47 546
fbbd37b3
CW		 547 synchronize_rcu();
548 flush_work(&dev_priv->mm.free_work);
549
550 WARN_ON(!list_empty(&dev_priv->context_list));
0673ad47
CW		 551}
552
553static int i915_load_modeset_init(struct drm_device *dev)
554{
fac5e23e 555 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 556 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 557 int ret;
558
559 if (i915_inject_load_failure())
560 return -ENODEV;
561
562 ret = intel_bios_init(dev_priv);
563 if (ret)
564 DRM_INFO("failed to find VBIOS tables\n");
565
566 /* If we have > 1 VGA cards, then we need to arbitrate access
567 * to the common VGA resources.
568 *
569 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
570 * then we do not take part in VGA arbitration and the
571 * vga_client_register() fails with -ENODEV.
572 */
52a05c30 573 ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
0673ad47
CW		 574 if (ret && ret != -ENODEV)
575 goto out;
576
577 intel_register_dsm_handler();
578
52a05c30 579 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
0673ad47
CW		 580 if (ret)
581 goto cleanup_vga_client;
582
583 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
584 intel_update_rawclk(dev_priv);
585
586 intel_power_domains_init_hw(dev_priv, false);
587
588 intel_csr_ucode_init(dev_priv);
589
590 ret = intel_irq_install(dev_priv);
591 if (ret)
592 goto cleanup_csr;
593
594 intel_setup_gmbus(dev);
595
596 /* Important: The output setup functions called by modeset_init need
597 * working irqs for e.g. gmbus and dp aux transfers. */
598 intel_modeset_init(dev);
599
600 intel_guc_init(dev);
601
602 ret = i915_gem_init(dev);
603 if (ret)
604 goto cleanup_irq;
605
606 intel_modeset_gem_init(dev);
607
608 if (INTEL_INFO(dev)->num_pipes == 0)
609 return 0;
610
611 ret = intel_fbdev_init(dev);
612 if (ret)
613 goto cleanup_gem;
614
615 /* Only enable hotplug handling once the fbdev is fully set up. */
616 intel_hpd_init(dev_priv);
617
618 drm_kms_helper_poll_init(dev);
619
620 return 0;
621
622cleanup_gem:
1c777c5d
ID		 623 if (i915_gem_suspend(dev))
624 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
fbbd37b3 625 i915_gem_fini(dev_priv);
0673ad47
CW		 626cleanup_irq:
627 intel_guc_fini(dev);
628 drm_irq_uninstall(dev);
629 intel_teardown_gmbus(dev);
630cleanup_csr:
631 intel_csr_ucode_fini(dev_priv);
632 intel_power_domains_fini(dev_priv);
52a05c30 633 vga_switcheroo_unregister_client(pdev);
0673ad47 634cleanup_vga_client:
52a05c30 635 vga_client_register(pdev, NULL, NULL, NULL);
0673ad47
CW		 636out:
637 return ret;
638}
639
640#if IS_ENABLED(CONFIG_FB)
641static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
642{
643 struct apertures_struct *ap;
91c8a326 644 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 645 struct i915_ggtt *ggtt = &dev_priv->ggtt;
646 bool primary;
647 int ret;
648
649 ap = alloc_apertures(1);
650 if (!ap)
651 return -ENOMEM;
652
653 ap->ranges[0].base = ggtt->mappable_base;
654 ap->ranges[0].size = ggtt->mappable_end;
655
656 primary =
657 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
658
44adece5 659 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
0673ad47
CW		 660
661 kfree(ap);
662
663 return ret;
664}
665#else
666static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
667{
668 return 0;
669}
670#endif
671
672#if !defined(CONFIG_VGA_CONSOLE)
673static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
674{
675 return 0;
676}
677#elif !defined(CONFIG_DUMMY_CONSOLE)
678static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
679{
680 return -ENODEV;
681}
682#else
683static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
684{
685 int ret = 0;
686
687 DRM_INFO("Replacing VGA console driver\n");
688
689 console_lock();
690 if (con_is_bound(&vga_con))
691 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
692 if (ret == 0) {
693 ret = do_unregister_con_driver(&vga_con);
694
695 /* Ignore "already unregistered". */
696 if (ret == -ENODEV)
697 ret = 0;
698 }
699 console_unlock();
700
701 return ret;
702}
703#endif
704
0673ad47
CW		 705static void intel_init_dpio(struct drm_i915_private *dev_priv)
706{
707 /*
708 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
709 * CHV x1 PHY (DP/HDMI D)
710 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
711 */
712 if (IS_CHERRYVIEW(dev_priv)) {
713 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
714 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
715 } else if (IS_VALLEYVIEW(dev_priv)) {
716 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
717 }
718}
719
720static int i915_workqueues_init(struct drm_i915_private *dev_priv)
721{
722 /*
723 * The i915 workqueue is primarily used for batched retirement of
724 * requests (and thus managing bo) once the task has been completed
725 * by the GPU. i915_gem_retire_requests() is called directly when we
726 * need high-priority retirement, such as waiting for an explicit
727 * bo.
728 *
729 * It is also used for periodic low-priority events, such as
730 * idle-timers and recording error state.
731 *
732 * All tasks on the workqueue are expected to acquire the dev mutex
733 * so there is no point in running more than one instance of the
734 * workqueue at any time. Use an ordered one.
735 */
736 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
737 if (dev_priv->wq == NULL)
738 goto out_err;
739
740 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
741 if (dev_priv->hotplug.dp_wq == NULL)
742 goto out_free_wq;
743
0673ad47
CW		 744 return 0;
745
0673ad47
CW		 746out_free_wq:
747 destroy_workqueue(dev_priv->wq);
748out_err:
749 DRM_ERROR("Failed to allocate workqueues.\n");
750
751 return -ENOMEM;
752}
753
754static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
755{
0673ad47
CW		 756 destroy_workqueue(dev_priv->hotplug.dp_wq);
757 destroy_workqueue(dev_priv->wq);
758}
759
4fc7e845
PZ		 760/*
761 * We don't keep the workarounds for pre-production hardware, so we expect our
762 * driver to fail on these machines in one way or another. A little warning on
763 * dmesg may help both the user and the bug triagers.
764 */
765static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
766{
767 if (IS_HSW_EARLY_SDV(dev_priv) ||
768 IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
769 DRM_ERROR("This is a pre-production stepping. "
770 "It may not be fully functional.\n");
771}
772
0673ad47
CW		 773/**
774 * i915_driver_init_early - setup state not requiring device access
775 * @dev_priv: device private
776 *
777 * Initialize everything that is a "SW-only" state, that is state not
778 * requiring accessing the device or exposing the driver via kernel internal
779 * or userspace interfaces. Example steps belonging here: lock initialization,
780 * system memory allocation, setting up device specific attributes and
781 * function hooks not requiring accessing the device.
782 */
783static int i915_driver_init_early(struct drm_i915_private *dev_priv,
784 const struct pci_device_id *ent)
785{
786 const struct intel_device_info *match_info =
787 (struct intel_device_info *)ent->driver_data;
788 struct intel_device_info *device_info;
789 int ret = 0;
790
791 if (i915_inject_load_failure())
792 return -ENODEV;
793
794 /* Setup the write-once "constant" device info */
94b4f3ba 795 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 796 memcpy(device_info, match_info, sizeof(*device_info));
797 device_info->device_id = dev_priv->drm.pdev->device;
798
799 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
800 device_info->gen_mask = BIT(device_info->gen - 1);
801
802 spin_lock_init(&dev_priv->irq_lock);
803 spin_lock_init(&dev_priv->gpu_error.lock);
804 mutex_init(&dev_priv->backlight_lock);
805 spin_lock_init(&dev_priv->uncore.lock);
806 spin_lock_init(&dev_priv->mm.object_stat_lock);
807 spin_lock_init(&dev_priv->mmio_flip_lock);
808 mutex_init(&dev_priv->sb_lock);
809 mutex_init(&dev_priv->modeset_restore_lock);
810 mutex_init(&dev_priv->av_mutex);
811 mutex_init(&dev_priv->wm.wm_mutex);
812 mutex_init(&dev_priv->pps_mutex);
813
0b1de5d5
CW		 814 i915_memcpy_init_early(dev_priv);
815
0673ad47
CW		 816 ret = i915_workqueues_init(dev_priv);
817 if (ret < 0)
818 return ret;
819
820 ret = intel_gvt_init(dev_priv);
821 if (ret < 0)
822 goto err_workqueues;
823
824 /* This must be called before any calls to HAS_PCH_* */
825 intel_detect_pch(&dev_priv->drm);
826
827 intel_pm_setup(&dev_priv->drm);
828 intel_init_dpio(dev_priv);
829 intel_power_domains_init(dev_priv);
830 intel_irq_init(dev_priv);
831 intel_init_display_hooks(dev_priv);
832 intel_init_clock_gating_hooks(dev_priv);
833 intel_init_audio_hooks(dev_priv);
834 i915_gem_load_init(&dev_priv->drm);
835
36cdd013 836 intel_display_crc_init(dev_priv);
0673ad47 837
94b4f3ba 838 intel_device_info_dump(dev_priv);
0673ad47 839
4fc7e845 840 intel_detect_preproduction_hw(dev_priv);
0673ad47
CW		 841
842 return 0;
843
844err_workqueues:
845 i915_workqueues_cleanup(dev_priv);
846 return ret;
847}
848
849/**
850 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
851 * @dev_priv: device private
852 */
853static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
854{
91c8a326 855 i915_gem_load_cleanup(&dev_priv->drm);
0673ad47
CW		 856 i915_workqueues_cleanup(dev_priv);
857}
858
859static int i915_mmio_setup(struct drm_device *dev)
860{
861 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 862 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 863 int mmio_bar;
864 int mmio_size;
865
5db94019 866 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
0673ad47
CW		 867 /*
868 * Before gen4, the registers and the GTT are behind different BARs.
869 * However, from gen4 onwards, the registers and the GTT are shared
870 * in the same BAR, so we want to restrict this ioremap from
871 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
872 * the register BAR remains the same size for all the earlier
873 * generations up to Ironlake.
874 */
875 if (INTEL_INFO(dev)->gen < 5)
876 mmio_size = 512 * 1024;
877 else
878 mmio_size = 2 * 1024 * 1024;
52a05c30 879 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
0673ad47
CW		 880 if (dev_priv->regs == NULL) {
881 DRM_ERROR("failed to map registers\n");
882
883 return -EIO;
884 }
885
886 /* Try to make sure MCHBAR is enabled before poking at it */
887 intel_setup_mchbar(dev);
888
889 return 0;
890}
891
892static void i915_mmio_cleanup(struct drm_device *dev)
893{
894 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 895 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 896
897 intel_teardown_mchbar(dev);
52a05c30 898 pci_iounmap(pdev, dev_priv->regs);
0673ad47
CW		 899}
900
901/**
902 * i915_driver_init_mmio - setup device MMIO
903 * @dev_priv: device private
904 *
905 * Setup minimal device state necessary for MMIO accesses later in the
906 * initialization sequence. The setup here should avoid any other device-wide
907 * side effects or exposing the driver via kernel internal or user space
908 * interfaces.
909 */
910static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
911{
91c8a326 912 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 913 int ret;
914
915 if (i915_inject_load_failure())
916 return -ENODEV;
917
918 if (i915_get_bridge_dev(dev))
919 return -EIO;
920
921 ret = i915_mmio_setup(dev);
922 if (ret < 0)
923 goto put_bridge;
924
925 intel_uncore_init(dev_priv);
926
927 return 0;
928
929put_bridge:
930 pci_dev_put(dev_priv->bridge_dev);
931
932 return ret;
933}
934
935/**
936 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
937 * @dev_priv: device private
938 */
939static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
940{
91c8a326 941 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 942
943 intel_uncore_fini(dev_priv);
944 i915_mmio_cleanup(dev);
945 pci_dev_put(dev_priv->bridge_dev);
946}
947
94b4f3ba
CW		 948static void intel_sanitize_options(struct drm_i915_private *dev_priv)
949{
950 i915.enable_execlists =
951 intel_sanitize_enable_execlists(dev_priv,
952 i915.enable_execlists);
953
954 /*
955 * i915.enable_ppgtt is read-only, so do an early pass to validate the
956 * user's requested state against the hardware/driver capabilities. We
957 * do this now so that we can print out any log messages once rather
958 * than every time we check intel_enable_ppgtt().
959 */
960 i915.enable_ppgtt =
961 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
962 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
39df9190
CW		 963
964 i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
965 DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
94b4f3ba
CW		 966}
967
0673ad47
CW		 968/**
969 * i915_driver_init_hw - setup state requiring device access
970 * @dev_priv: device private
971 *
972 * Setup state that requires accessing the device, but doesn't require
973 * exposing the driver via kernel internal or userspace interfaces.
974 */
975static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
976{
52a05c30 977 struct pci_dev *pdev = dev_priv->drm.pdev;
91c8a326 978 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 979 int ret;
980
981 if (i915_inject_load_failure())
982 return -ENODEV;
983
94b4f3ba
CW		 984 intel_device_info_runtime_init(dev_priv);
985
986 intel_sanitize_options(dev_priv);
0673ad47 987
97d6d7ab 988 ret = i915_ggtt_probe_hw(dev_priv);
0673ad47
CW		 989 if (ret)
990 return ret;
991
0673ad47
CW		 992 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
993 * otherwise the vga fbdev driver falls over. */
994 ret = i915_kick_out_firmware_fb(dev_priv);
995 if (ret) {
996 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
997 goto out_ggtt;
998 }
999
1000 ret = i915_kick_out_vgacon(dev_priv);
1001 if (ret) {
1002 DRM_ERROR("failed to remove conflicting VGA console\n");
1003 goto out_ggtt;
1004 }
1005
97d6d7ab 1006 ret = i915_ggtt_init_hw(dev_priv);
0088e522
CW		 1007 if (ret)
1008 return ret;
1009
97d6d7ab 1010 ret = i915_ggtt_enable_hw(dev_priv);
0088e522
CW		 1011 if (ret) {
1012 DRM_ERROR("failed to enable GGTT\n");
1013 goto out_ggtt;
1014 }
1015
52a05c30 1016 pci_set_master(pdev);
0673ad47
CW		 1017
1018 /* overlay on gen2 is broken and can't address above 1G */
5db94019 1019 if (IS_GEN2(dev_priv)) {
52a05c30 1020 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
0673ad47
CW		 1021 if (ret) {
1022 DRM_ERROR("failed to set DMA mask\n");
1023
1024 goto out_ggtt;
1025 }
1026 }
1027
0673ad47
CW		 1028 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1029 * using 32bit addressing, overwriting memory if HWS is located
1030 * above 4GB.
1031 *
1032 * The documentation also mentions an issue with undefined
1033 * behaviour if any general state is accessed within a page above 4GB,
1034 * which also needs to be handled carefully.
1035 */
1036 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
52a05c30 1037 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0673ad47
CW		 1038
1039 if (ret) {
1040 DRM_ERROR("failed to set DMA mask\n");
1041
1042 goto out_ggtt;
1043 }
1044 }
1045
0673ad47
CW		 1046 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1047 PM_QOS_DEFAULT_VALUE);
1048
1049 intel_uncore_sanitize(dev_priv);
1050
1051 intel_opregion_setup(dev_priv);
1052
1053 i915_gem_load_init_fences(dev_priv);
1054
1055 /* On the 945G/GM, the chipset reports the MSI capability on the
1056 * integrated graphics even though the support isn't actually there
1057 * according to the published specs. It doesn't appear to function
1058 * correctly in testing on 945G.
1059 * This may be a side effect of MSI having been made available for PEG
1060 * and the registers being closely associated.
1061 *
1062 * According to chipset errata, on the 965GM, MSI interrupts may
1063 * be lost or delayed, but we use them anyways to avoid
1064 * stuck interrupts on some machines.
1065 */
50a0bc90 1066 if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
52a05c30 1067 if (pci_enable_msi(pdev) < 0)
0673ad47
CW		 1068 DRM_DEBUG_DRIVER("can't enable MSI");
1069 }
1070
1071 return 0;
1072
1073out_ggtt:
97d6d7ab 1074 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1075
1076 return ret;
1077}
1078
1079/**
1080 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1081 * @dev_priv: device private
1082 */
1083static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1084{
52a05c30 1085 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 1086
52a05c30
DW		 1087 if (pdev->msi_enabled)
1088 pci_disable_msi(pdev);
0673ad47
CW		 1089
1090 pm_qos_remove_request(&dev_priv->pm_qos);
97d6d7ab 1091 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1092}
1093
1094/**
1095 * i915_driver_register - register the driver with the rest of the system
1096 * @dev_priv: device private
1097 *
1098 * Perform any steps necessary to make the driver available via kernel
1099 * internal or userspace interfaces.
1100 */
1101static void i915_driver_register(struct drm_i915_private *dev_priv)
1102{
91c8a326 1103 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1104
1105 i915_gem_shrinker_init(dev_priv);
1106
1107 /*
1108 * Notify a valid surface after modesetting,
1109 * when running inside a VM.
1110 */
1111 if (intel_vgpu_active(dev_priv))
1112 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1113
1114 /* Reveal our presence to userspace */
1115 if (drm_dev_register(dev, 0) == 0) {
1116 i915_debugfs_register(dev_priv);
f8240835 1117 i915_guc_register(dev_priv);
694c2828 1118 i915_setup_sysfs(dev_priv);
0673ad47
CW		 1119 } else
1120 DRM_ERROR("Failed to register driver for userspace access!\n");
1121
1122 if (INTEL_INFO(dev_priv)->num_pipes) {
1123 /* Must be done after probing outputs */
1124 intel_opregion_register(dev_priv);
1125 acpi_video_register();
1126 }
1127
1128 if (IS_GEN5(dev_priv))
1129 intel_gpu_ips_init(dev_priv);
1130
1131 i915_audio_component_init(dev_priv);
1132
1133 /*
1134 * Some ports require correctly set-up hpd registers for detection to
1135 * work properly (leading to ghost connected connector status), e.g. VGA
1136 * on gm45. Hence we can only set up the initial fbdev config after hpd
1137 * irqs are fully enabled. We do it last so that the async config
1138 * cannot run before the connectors are registered.
1139 */
1140 intel_fbdev_initial_config_async(dev);
1141}
1142
1143/**
1144 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1145 * @dev_priv: device private
1146 */
1147static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1148{
1149 i915_audio_component_cleanup(dev_priv);
1150
1151 intel_gpu_ips_teardown();
1152 acpi_video_unregister();
1153 intel_opregion_unregister(dev_priv);
1154
694c2828 1155 i915_teardown_sysfs(dev_priv);
f8240835 1156 i915_guc_unregister(dev_priv);
0673ad47 1157 i915_debugfs_unregister(dev_priv);
91c8a326 1158 drm_dev_unregister(&dev_priv->drm);
0673ad47
CW		 1159
1160 i915_gem_shrinker_cleanup(dev_priv);
1161}
1162
1163/**
1164 * i915_driver_load - setup chip and create an initial config
1165 * @dev: DRM device
1166 * @flags: startup flags
1167 *
1168 * The driver load routine has to do several things:
1169 * - drive output discovery via intel_modeset_init()
1170 * - initialize the memory manager
1171 * - allocate initial config memory
1172 * - setup the DRM framebuffer with the allocated memory
1173 */
42f5551d 1174int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47
CW		 1175{
1176 struct drm_i915_private *dev_priv;
1177 int ret;
7d87a7f7 1178
a09d0ba1
CW		 1179 if (i915.nuclear_pageflip)
1180 driver.driver_features |= DRIVER_ATOMIC;
1181
0673ad47
CW		 1182 ret = -ENOMEM;
1183 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1184 if (dev_priv)
1185 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1186 if (ret) {
1187 dev_printk(KERN_ERR, &pdev->dev,
1188 "[" DRM_NAME ":%s] allocation failed\n", __func__);
1189 kfree(dev_priv);
1190 return ret;
1191 }
72bbf0af 1192
0673ad47
CW		 1193 dev_priv->drm.pdev = pdev;
1194 dev_priv->drm.dev_private = dev_priv;
719388e1 1195
0673ad47
CW		 1196 ret = pci_enable_device(pdev);
1197 if (ret)
1198 goto out_free_priv;
1347f5b4 1199
0673ad47 1200 pci_set_drvdata(pdev, &dev_priv->drm);
ef11bdb3 1201
0673ad47
CW		 1202 ret = i915_driver_init_early(dev_priv, ent);
1203 if (ret < 0)
1204 goto out_pci_disable;
ef11bdb3 1205
0673ad47 1206 intel_runtime_pm_get(dev_priv);
1da177e4 1207
0673ad47
CW		 1208 ret = i915_driver_init_mmio(dev_priv);
1209 if (ret < 0)
1210 goto out_runtime_pm_put;
79e53945 1211
0673ad47
CW		 1212 ret = i915_driver_init_hw(dev_priv);
1213 if (ret < 0)
1214 goto out_cleanup_mmio;
30c964a6
RB		 1215
1216 /*
0673ad47
CW		 1217 * TODO: move the vblank init and parts of modeset init steps into one
1218 * of the i915_driver_init_/i915_driver_register functions according
1219 * to the role/effect of the given init step.
30c964a6 1220 */
0673ad47 1221 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1222 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1223 INTEL_INFO(dev_priv)->num_pipes);
1224 if (ret)
1225 goto out_cleanup_hw;
30c964a6
RB		 1226 }
1227
91c8a326 1228 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47
CW		 1229 if (ret < 0)
1230 goto out_cleanup_vblank;
1231
1232 i915_driver_register(dev_priv);
1233
1234 intel_runtime_pm_enable(dev_priv);
1235
bc5ca47c
CW		 1236 /* Everything is in place, we can now relax! */
1237 DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1238 driver.name, driver.major, driver.minor, driver.patchlevel,
1239 driver.date, pci_name(pdev), dev_priv->drm.primary->index);
0525a062
CW		 1240 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1241 DRM_INFO("DRM_I915_DEBUG enabled\n");
1242 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1243 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
bc5ca47c 1244
0673ad47
CW		 1245 intel_runtime_pm_put(dev_priv);
1246
1247 return 0;
1248
1249out_cleanup_vblank:
91c8a326 1250 drm_vblank_cleanup(&dev_priv->drm);
0673ad47
CW		 1251out_cleanup_hw:
1252 i915_driver_cleanup_hw(dev_priv);
1253out_cleanup_mmio:
1254 i915_driver_cleanup_mmio(dev_priv);
1255out_runtime_pm_put:
1256 intel_runtime_pm_put(dev_priv);
1257 i915_driver_cleanup_early(dev_priv);
1258out_pci_disable:
1259 pci_disable_device(pdev);
1260out_free_priv:
1261 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1262 drm_dev_unref(&dev_priv->drm);
30c964a6
RB		 1263 return ret;
1264}
1265
42f5551d 1266void i915_driver_unload(struct drm_device *dev)
3bad0781 1267{
fac5e23e 1268 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1269 struct pci_dev *pdev = dev_priv->drm.pdev;
3bad0781 1270
0673ad47
CW		 1271 intel_fbdev_fini(dev);
1272
42f5551d
CW		 1273 if (i915_gem_suspend(dev))
1274 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1275
0673ad47
CW		 1276 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1277
1278 i915_driver_unregister(dev_priv);
1279
1280 drm_vblank_cleanup(dev);
1281
1282 intel_modeset_cleanup(dev);
1283
3bad0781 1284 /*
0673ad47
CW		 1285 * free the memory space allocated for the child device
1286 * config parsed from VBT
3bad0781 1287 */
0673ad47
CW		 1288 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1289 kfree(dev_priv->vbt.child_dev);
1290 dev_priv->vbt.child_dev = NULL;
1291 dev_priv->vbt.child_dev_num = 0;
1292 }
1293 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1294 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1295 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1296 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1297
52a05c30
DW		 1298 vga_switcheroo_unregister_client(pdev);
1299 vga_client_register(pdev, NULL, NULL, NULL);
bcdb72ac 1300
0673ad47 1301 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1302
0673ad47
CW		 1303 /* Free error state after interrupts are fully disabled. */
1304 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1305 i915_destroy_error_state(dev);
1306
1307 /* Flush any outstanding unpin_work. */
b7137e0c 1308 drain_workqueue(dev_priv->wq);
0673ad47
CW		 1309
1310 intel_guc_fini(dev);
fbbd37b3 1311 i915_gem_fini(dev_priv);
0673ad47
CW		 1312 intel_fbc_cleanup_cfb(dev_priv);
1313
1314 intel_power_domains_fini(dev_priv);
1315
1316 i915_driver_cleanup_hw(dev_priv);
1317 i915_driver_cleanup_mmio(dev_priv);
1318
1319 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1320
1321 i915_driver_cleanup_early(dev_priv);
3bad0781
ZW		 1322}
1323
0673ad47 1324static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1325{
0673ad47 1326 int ret;
2911a35b 1327
0673ad47
CW		 1328 ret = i915_gem_open(dev, file);
1329 if (ret)
1330 return ret;
2911a35b 1331
0673ad47
CW		 1332 return 0;
1333}
71386ef9 1334
0673ad47
CW		 1335/**
1336 * i915_driver_lastclose - clean up after all DRM clients have exited
1337 * @dev: DRM device
1338 *
1339 * Take care of cleaning up after all DRM clients have exited. In the
1340 * mode setting case, we want to restore the kernel's initial mode (just
1341 * in case the last client left us in a bad state).
1342 *
1343 * Additionally, in the non-mode setting case, we'll tear down the GTT
1344 * and DMA structures, since the kernel won't be using them, and clea
1345 * up any GEM state.
1346 */
1347static void i915_driver_lastclose(struct drm_device *dev)
1348{
1349 intel_fbdev_restore_mode(dev);
1350 vga_switcheroo_process_delayed_switch();
1351}
2911a35b 1352
0673ad47
CW		 1353static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1354{
1355 mutex_lock(&dev->struct_mutex);
1356 i915_gem_context_close(dev, file);
1357 i915_gem_release(dev, file);
1358 mutex_unlock(&dev->struct_mutex);
1359}
1360
1361static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1362{
1363 struct drm_i915_file_private *file_priv = file->driver_priv;
1364
1365 kfree(file_priv);
2911a35b
BW		 1366}
1367
07f9cd0b
ID		 1368static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1369{
91c8a326 1370 struct drm_device *dev = &dev_priv->drm;
19c8054c 1371 struct intel_encoder *encoder;
07f9cd0b
ID		 1372
1373 drm_modeset_lock_all(dev);
19c8054c
JN		 1374 for_each_intel_encoder(dev, encoder)
1375 if (encoder->suspend)
1376 encoder->suspend(encoder);
07f9cd0b
ID		 1377 drm_modeset_unlock_all(dev);
1378}
1379
1a5df187
PZ		 1380static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1381 bool rpm_resume);
507e126e 1382static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1383
bc87229f
ID		 1384static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1385{
1386#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1387 if (acpi_target_system_state() < ACPI_STATE_S3)
1388 return true;
1389#endif
1390 return false;
1391}
ebc32824 1392
5e365c39 1393static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1394{
fac5e23e 1395 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1396 struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3a 1397 pci_power_t opregion_target_state;
d5818938 1398 int error;
61caf87c 1399
b8efb17b
ZR		 1400 /* ignore lid events during suspend */
1401 mutex_lock(&dev_priv->modeset_restore_lock);
1402 dev_priv->modeset_restore = MODESET_SUSPENDED;
1403 mutex_unlock(&dev_priv->modeset_restore_lock);
1404
1f814dac
ID		 1405 disable_rpm_wakeref_asserts(dev_priv);
1406
c67a470b
PZ		 1407 /* We do a lot of poking in a lot of registers, make sure they work
1408 * properly. */
da7e29bd 1409 intel_display_set_init_power(dev_priv, true);
cb10799c 1410
5bcf719b
DA		 1411 drm_kms_helper_poll_disable(dev);
1412
52a05c30 1413 pci_save_state(pdev);
ba8bbcf6 1414
d5818938
DV		 1415 error = i915_gem_suspend(dev);
1416 if (error) {
52a05c30 1417 dev_err(&pdev->dev,
d5818938 1418 "GEM idle failed, resume might fail\n");
1f814dac 1419 goto out;
d5818938 1420 }
db1b76ca 1421
a1c41994
AD		 1422 intel_guc_suspend(dev);
1423
6b72d486 1424 intel_display_suspend(dev);
2eb5252e 1425
d5818938 1426 intel_dp_mst_suspend(dev);
7d708ee4 1427
d5818938
DV		 1428 intel_runtime_pm_disable_interrupts(dev_priv);
1429 intel_hpd_cancel_work(dev_priv);
09b64267 1430
d5818938 1431 intel_suspend_encoders(dev_priv);
0e32b39c 1432
d5818938 1433 intel_suspend_hw(dev);
5669fcac 1434
828c7908
BW		 1435 i915_gem_suspend_gtt_mappings(dev);
1436
9e06dd39
JB		 1437 i915_save_state(dev);
1438
bc87229f 1439 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1440 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1441
dc97997a 1442 intel_uncore_forcewake_reset(dev_priv, false);
03d92e47 1443 intel_opregion_unregister(dev_priv);
8ee1c3db 1444
82e3b8c1 1445 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1446
62d5d69b
MK		 1447 dev_priv->suspend_count++;
1448
f74ed08d 1449 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1450
1f814dac
ID		 1451out:
1452 enable_rpm_wakeref_asserts(dev_priv);
1453
1454 return error;
84b79f8d
RW		 1455}
1456
c49d13ee 1457static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
c3c09c95 1458{
c49d13ee 1459 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1460 struct pci_dev *pdev = dev_priv->drm.pdev;
bc87229f 1461 bool fw_csr;
c3c09c95
ID		 1462 int ret;
1463
1f814dac
ID		 1464 disable_rpm_wakeref_asserts(dev_priv);
1465
4c494a57
ID		 1466 intel_display_set_init_power(dev_priv, false);
1467
a7c8125f
ID		 1468 fw_csr = !IS_BROXTON(dev_priv) &&
1469 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1470 /*
1471 * In case of firmware assisted context save/restore don't manually
1472 * deinit the power domains. This also means the CSR/DMC firmware will
1473 * stay active, it will power down any HW resources as required and
1474 * also enable deeper system power states that would be blocked if the
1475 * firmware was inactive.
1476 */
1477 if (!fw_csr)
1478 intel_power_domains_suspend(dev_priv);
73dfc227 1479
507e126e 1480 ret = 0;
b8aea3d1 1481 if (IS_BROXTON(dev_priv))
507e126e 1482 bxt_enable_dc9(dev_priv);
b8aea3d1 1483 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1484 hsw_enable_pc8(dev_priv);
1485 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1486 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1487
1488 if (ret) {
1489 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1490 if (!fw_csr)
1491 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1492
1f814dac 1493 goto out;
c3c09c95
ID		 1494 }
1495
52a05c30 1496 pci_disable_device(pdev);
ab3be73f 1497 /*
54875571 1498 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1499 * the device even though it's already in D3 and hang the machine. So
1500 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1501 * power down the device properly. The issue was seen on multiple old
1502 * GENs with different BIOS vendors, so having an explicit blacklist
1503 * is inpractical; apply the workaround on everything pre GEN6. The
1504 * platforms where the issue was seen:
1505 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1506 * Fujitsu FSC S7110
1507 * Acer Aspire 1830T
ab3be73f 1508 */
54875571 1509 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
52a05c30 1510 pci_set_power_state(pdev, PCI_D3hot);
c3c09c95 1511
bc87229f
ID		 1512 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1513
1f814dac
ID		 1514out:
1515 enable_rpm_wakeref_asserts(dev_priv);
1516
1517 return ret;
c3c09c95
ID		 1518}
1519
1751fcf9 1520int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1521{
1522 int error;
1523
ded8b07d 1524 if (!dev) {
84b79f8d
RW		 1525 DRM_ERROR("dev: %p\n", dev);
1526 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1527 return -ENODEV;
1528 }
1529
0b14cbd2
ID		 1530 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1531 state.event != PM_EVENT_FREEZE))
1532 return -EINVAL;
5bcf719b
DA		 1533
1534 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1535 return 0;
6eecba33 1536
5e365c39 1537 error = i915_drm_suspend(dev);
84b79f8d
RW		 1538 if (error)
1539 return error;
1540
ab3be73f 1541 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1542}
1543
5e365c39 1544static int i915_drm_resume(struct drm_device *dev)
76c4b250 1545{
fac5e23e 1546 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1547 int ret;
9d49c0ef 1548
1f814dac 1549 disable_rpm_wakeref_asserts(dev_priv);
abc80abd 1550 intel_sanitize_gt_powersave(dev_priv);
1f814dac 1551
97d6d7ab 1552 ret = i915_ggtt_enable_hw(dev_priv);
ac840ae5
VS		 1553 if (ret)
1554 DRM_ERROR("failed to re-enable GGTT\n");
1555
f74ed08d
ID		 1556 intel_csr_ucode_resume(dev_priv);
1557
5ab57c70 1558 i915_gem_resume(dev);
9d49c0ef 1559
61caf87c 1560 i915_restore_state(dev);
8090ba8c 1561 intel_pps_unlock_regs_wa(dev_priv);
6f9f4b7a 1562 intel_opregion_setup(dev_priv);
61caf87c 1563
d5818938
DV		 1564 intel_init_pch_refclk(dev);
1565 drm_mode_config_reset(dev);
1833b134 1566
364aece0
PA		 1567 /*
1568 * Interrupts have to be enabled before any batches are run. If not the
1569 * GPU will hang. i915_gem_init_hw() will initiate batches to
1570 * update/restore the context.
1571 *
1572 * Modeset enabling in intel_modeset_init_hw() also needs working
1573 * interrupts.
1574 */
1575 intel_runtime_pm_enable_interrupts(dev_priv);
1576
d5818938
DV		 1577 mutex_lock(&dev->struct_mutex);
1578 if (i915_gem_init_hw(dev)) {
1579 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
821ed7df 1580 i915_gem_set_wedged(dev_priv);
d5818938
DV		 1581 }
1582 mutex_unlock(&dev->struct_mutex);
226485e9 1583
a1c41994
AD		 1584 intel_guc_resume(dev);
1585
d5818938 1586 intel_modeset_init_hw(dev);
24576d23 1587
d5818938
DV		 1588 spin_lock_irq(&dev_priv->irq_lock);
1589 if (dev_priv->display.hpd_irq_setup)
91d14251 1590 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1591 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1592
d5818938 1593 intel_dp_mst_resume(dev);
e7d6f7d7 1594
a16b7658
L		 1595 intel_display_resume(dev);
1596
d5818938
DV		 1597 /*
1598 * ... but also need to make sure that hotplug processing
1599 * doesn't cause havoc. Like in the driver load code we don't
1600 * bother with the tiny race here where we might loose hotplug
1601 * notifications.
1602 * */
1603 intel_hpd_init(dev_priv);
1604 /* Config may have changed between suspend and resume */
1605 drm_helper_hpd_irq_event(dev);
1daed3fb 1606
03d92e47 1607 intel_opregion_register(dev_priv);
44834a67 1608
82e3b8c1 1609 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1610
b8efb17b
ZR		 1611 mutex_lock(&dev_priv->modeset_restore_lock);
1612 dev_priv->modeset_restore = MODESET_DONE;
1613 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1614
6f9f4b7a 1615 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1616
54b4f68f 1617 intel_autoenable_gt_powersave(dev_priv);
ee6f280e
ID		 1618 drm_kms_helper_poll_enable(dev);
1619
1f814dac
ID		 1620 enable_rpm_wakeref_asserts(dev_priv);
1621
074c6ada 1622 return 0;
84b79f8d
RW		 1623}
1624
5e365c39 1625static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1626{
fac5e23e 1627 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1628 struct pci_dev *pdev = dev_priv->drm.pdev;
44410cd0 1629 int ret;
36d61e67 1630
76c4b250
ID		 1631 /*
1632 * We have a resume ordering issue with the snd-hda driver also
1633 * requiring our device to be power up. Due to the lack of a
1634 * parent/child relationship we currently solve this with an early
1635 * resume hook.
1636 *
1637 * FIXME: This should be solved with a special hdmi sink device or
1638 * similar so that power domains can be employed.
1639 */
44410cd0
ID		 1640
1641 /*
1642 * Note that we need to set the power state explicitly, since we
1643 * powered off the device during freeze and the PCI core won't power
1644 * it back up for us during thaw. Powering off the device during
1645 * freeze is not a hard requirement though, and during the
1646 * suspend/resume phases the PCI core makes sure we get here with the
1647 * device powered on. So in case we change our freeze logic and keep
1648 * the device powered we can also remove the following set power state
1649 * call.
1650 */
52a05c30 1651 ret = pci_set_power_state(pdev, PCI_D0);
44410cd0
ID		 1652 if (ret) {
1653 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1654 goto out;
1655 }
1656
1657 /*
1658 * Note that pci_enable_device() first enables any parent bridge
1659 * device and only then sets the power state for this device. The
1660 * bridge enabling is a nop though, since bridge devices are resumed
1661 * first. The order of enabling power and enabling the device is
1662 * imposed by the PCI core as described above, so here we preserve the
1663 * same order for the freeze/thaw phases.
1664 *
1665 * TODO: eventually we should remove pci_disable_device() /
1666 * pci_enable_enable_device() from suspend/resume. Due to how they
1667 * depend on the device enable refcount we can't anyway depend on them
1668 * disabling/enabling the device.
1669 */
52a05c30 1670 if (pci_enable_device(pdev)) {
bc87229f
ID		 1671 ret = -EIO;
1672 goto out;
1673 }
84b79f8d 1674
52a05c30 1675 pci_set_master(pdev);
84b79f8d 1676
1f814dac
ID		 1677 disable_rpm_wakeref_asserts(dev_priv);
1678
666a4537 1679 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1680 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1681 if (ret)
ff0b187f
DL		 1682 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1683 ret);
36d61e67 1684
dc97997a 1685 intel_uncore_early_sanitize(dev_priv, true);
efee833a 1686
dc97997a 1687 if (IS_BROXTON(dev_priv)) {
da2f41d1
ID		 1688 if (!dev_priv->suspended_to_idle)
1689 gen9_sanitize_dc_state(dev_priv);
507e126e 1690 bxt_disable_dc9(dev_priv);
da2f41d1 1691 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1692 hsw_disable_pc8(dev_priv);
da2f41d1 1693 }
efee833a 1694
dc97997a 1695 intel_uncore_sanitize(dev_priv);
bc87229f 1696
a7c8125f
ID		 1697 if (IS_BROXTON(dev_priv) ||
1698 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 1699 intel_power_domains_init_hw(dev_priv, true);
1700
6e35e8ab
ID		 1701 enable_rpm_wakeref_asserts(dev_priv);
1702
bc87229f
ID		 1703out:
1704 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1705
1706 return ret;
76c4b250
ID		 1707}
1708
1751fcf9 1709int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1710{
50a0072f 1711 int ret;
76c4b250 1712
097dd837
ID		 1713 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1714 return 0;
1715
5e365c39 1716 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1717 if (ret)
1718 return ret;
1719
5a17514e
ID		 1720 return i915_drm_resume(dev);
1721}
1722
9e60ab03
CW		 1723static void disable_engines_irq(struct drm_i915_private *dev_priv)
1724{
1725 struct intel_engine_cs *engine;
3b3f1650 1726 enum intel_engine_id id;
9e60ab03
CW		 1727
1728 /* Ensure irq handler finishes, and not run again. */
1729 disable_irq(dev_priv->drm.irq);
3b3f1650 1730 for_each_engine(engine, dev_priv, id)
9e60ab03
CW		 1731 tasklet_kill(&engine->irq_tasklet);
1732}
1733
1734static void enable_engines_irq(struct drm_i915_private *dev_priv)
1735{
1736 enable_irq(dev_priv->drm.irq);
1737}
1738
11ed50ec 1739/**
f3953dcb 1740 * i915_reset - reset chip after a hang
11ed50ec 1741 * @dev: drm device to reset
11ed50ec 1742 *
780f262a
CW		 1743 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1744 * on failure.
11ed50ec 1745 *
221fe799
CW		 1746 * Caller must hold the struct_mutex.
1747 *
11ed50ec
BG		 1748 * Procedure is fairly simple:
1749 * - reset the chip using the reset reg
1750 * - re-init context state
1751 * - re-init hardware status page
1752 * - re-init ring buffer
1753 * - re-init interrupt state
1754 * - re-init display
1755 */
780f262a 1756void i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 1757{
91c8a326 1758 struct drm_device *dev = &dev_priv->drm;
d98c52cf 1759 struct i915_gpu_error *error = &dev_priv->gpu_error;
0573ed4a 1760 int ret;
11ed50ec 1761
221fe799
CW		 1762 lockdep_assert_held(&dev->struct_mutex);
1763
1764 if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
780f262a 1765 return;
11ed50ec 1766
d98c52cf 1767 /* Clear any previous failed attempts at recovery. Time to try again. */
8af29b0c
CW		 1768 __clear_bit(I915_WEDGED, &error->flags);
1769 error->reset_count++;
d98c52cf 1770
7b4d3a16 1771 pr_notice("drm/i915: Resetting chip after gpu hang\n");
9e60ab03
CW		 1772
1773 disable_engines_irq(dev_priv);
dc97997a 1774 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
9e60ab03
CW		 1775 enable_engines_irq(dev_priv);
1776
0573ed4a 1777 if (ret) {
804e59a8
CW		 1778 if (ret != -ENODEV)
1779 DRM_ERROR("Failed to reset chip: %i\n", ret);
1780 else
1781 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 1782 goto error;
11ed50ec
BG		 1783 }
1784
821ed7df 1785 i915_gem_reset(dev_priv);
1362b776
VS		 1786 intel_overlay_reset(dev_priv);
1787
11ed50ec
BG		 1788 /* Ok, now get things going again... */
1789
1790 /*
1791 * Everything depends on having the GTT running, so we need to start
1792 * there. Fortunately we don't need to do this unless we reset the
1793 * chip at a PCI level.
1794 *
1795 * Next we need to restore the context, but we don't use those
1796 * yet either...
1797 *
1798 * Ring buffer needs to be re-initialized in the KMS case, or if X
1799 * was running at the time of the reset (i.e. we weren't VT
1800 * switched away).
1801 */
33d30a9c 1802 ret = i915_gem_init_hw(dev);
33d30a9c
DV		 1803 if (ret) {
1804 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1805 goto error;
11ed50ec
BG		 1806 }
1807
780f262a
CW		 1808wakeup:
1809 wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1810 return;
d98c52cf
CW		 1811
1812error:
821ed7df 1813 i915_gem_set_wedged(dev_priv);
780f262a 1814 goto wakeup;
11ed50ec
BG		 1815}
1816
c49d13ee 1817static int i915_pm_suspend(struct device *kdev)
112b715e 1818{
c49d13ee
DW		 1819 struct pci_dev *pdev = to_pci_dev(kdev);
1820 struct drm_device *dev = pci_get_drvdata(pdev);
112b715e 1821
c49d13ee
DW		 1822 if (!dev) {
1823 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
84b79f8d
RW		 1824 return -ENODEV;
1825 }
112b715e 1826
c49d13ee 1827 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
5bcf719b
DA		 1828 return 0;
1829
c49d13ee 1830 return i915_drm_suspend(dev);
76c4b250
ID		 1831}
1832
c49d13ee 1833static int i915_pm_suspend_late(struct device *kdev)
76c4b250 1834{
c49d13ee 1835 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250
ID		 1836
1837 /*
c965d995 1838 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 1839 * requiring our device to be power up. Due to the lack of a
1840 * parent/child relationship we currently solve this with an late
1841 * suspend hook.
1842 *
1843 * FIXME: This should be solved with a special hdmi sink device or
1844 * similar so that power domains can be employed.
1845 */
c49d13ee 1846 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
76c4b250 1847 return 0;
112b715e 1848
c49d13ee 1849 return i915_drm_suspend_late(dev, false);
ab3be73f
ID		 1850}
1851
c49d13ee 1852static int i915_pm_poweroff_late(struct device *kdev)
ab3be73f 1853{
c49d13ee 1854 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
ab3be73f 1855
c49d13ee 1856 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
ab3be73f
ID		 1857 return 0;
1858
c49d13ee 1859 return i915_drm_suspend_late(dev, true);
cbda12d7
ZW		 1860}
1861
c49d13ee 1862static int i915_pm_resume_early(struct device *kdev)
76c4b250 1863{
c49d13ee 1864 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250 1865
c49d13ee 1866 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1867 return 0;
1868
c49d13ee 1869 return i915_drm_resume_early(dev);
76c4b250
ID		 1870}
1871
c49d13ee 1872static int i915_pm_resume(struct device *kdev)
cbda12d7 1873{
c49d13ee 1874 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
84b79f8d 1875
c49d13ee 1876 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1877 return 0;
1878
c49d13ee 1879 return i915_drm_resume(dev);
cbda12d7
ZW		 1880}
1881
1f19ac2a 1882/* freeze: before creating the hibernation_image */
c49d13ee 1883static int i915_pm_freeze(struct device *kdev)
1f19ac2a 1884{
6a800eab
CW		 1885 int ret;
1886
1887 ret = i915_pm_suspend(kdev);
1888 if (ret)
1889 return ret;
1890
1891 ret = i915_gem_freeze(kdev_to_i915(kdev));
1892 if (ret)
1893 return ret;
1894
1895 return 0;
1f19ac2a
CW		 1896}
1897
c49d13ee 1898static int i915_pm_freeze_late(struct device *kdev)
1f19ac2a 1899{
461fb99c
CW		 1900 int ret;
1901
c49d13ee 1902 ret = i915_pm_suspend_late(kdev);
461fb99c
CW		 1903 if (ret)
1904 return ret;
1905
c49d13ee 1906 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
461fb99c
CW		 1907 if (ret)
1908 return ret;
1909
1910 return 0;
1f19ac2a
CW		 1911}
1912
1913/* thaw: called after creating the hibernation image, but before turning off. */
c49d13ee 1914static int i915_pm_thaw_early(struct device *kdev)
1f19ac2a 1915{
c49d13ee 1916 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1917}
1918
c49d13ee 1919static int i915_pm_thaw(struct device *kdev)
1f19ac2a 1920{
c49d13ee 1921 return i915_pm_resume(kdev);
1f19ac2a
CW		 1922}
1923
1924/* restore: called after loading the hibernation image. */
c49d13ee 1925static int i915_pm_restore_early(struct device *kdev)
1f19ac2a 1926{
c49d13ee 1927 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1928}
1929
c49d13ee 1930static int i915_pm_restore(struct device *kdev)
1f19ac2a 1931{
c49d13ee 1932 return i915_pm_resume(kdev);
1f19ac2a
CW		 1933}
1934
ddeea5b0
ID		 1935/*
1936 * Save all Gunit registers that may be lost after a D3 and a subsequent
1937 * S0i[R123] transition. The list of registers needing a save/restore is
1938 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1939 * registers in the following way:
1940 * - Driver: saved/restored by the driver
1941 * - Punit : saved/restored by the Punit firmware
1942 * - No, w/o marking: no need to save/restore, since the register is R/O or
1943 * used internally by the HW in a way that doesn't depend
1944 * keeping the content across a suspend/resume.
1945 * - Debug : used for debugging
1946 *
1947 * We save/restore all registers marked with 'Driver', with the following
1948 * exceptions:
1949 * - Registers out of use, including also registers marked with 'Debug'.
1950 * These have no effect on the driver's operation, so we don't save/restore
1951 * them to reduce the overhead.
1952 * - Registers that are fully setup by an initialization function called from
1953 * the resume path. For example many clock gating and RPS/RC6 registers.
1954 * - Registers that provide the right functionality with their reset defaults.
1955 *
1956 * TODO: Except for registers that based on the above 3 criteria can be safely
1957 * ignored, we save/restore all others, practically treating the HW context as
1958 * a black-box for the driver. Further investigation is needed to reduce the
1959 * saved/restored registers even further, by following the same 3 criteria.
1960 */
1961static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1962{
1963 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1964 int i;
1965
1966 /* GAM 0x4000-0x4770 */
1967 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1968 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1969 s->arb_mode = I915_READ(ARB_MODE);
1970 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1971 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1972
1973 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 1974 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 1975
1976 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 1977 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 1978
1979 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1980 s->ecochk = I915_READ(GAM_ECOCHK);
1981 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1982 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1983
1984 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1985
1986 /* MBC 0x9024-0x91D0, 0x8500 */
1987 s->g3dctl = I915_READ(VLV_G3DCTL);
1988 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1989 s->mbctl = I915_READ(GEN6_MBCTL);
1990
1991 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1992 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1993 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1994 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1995 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1996 s->rstctl = I915_READ(GEN6_RSTCTL);
1997 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1998
1999 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2000 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2001 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2002 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2003 s->ecobus = I915_READ(ECOBUS);
2004 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2005 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2006 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2007 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2008 s->rcedata = I915_READ(VLV_RCEDATA);
2009 s->spare2gh = I915_READ(VLV_SPAREG2H);
2010
2011 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2012 s->gt_imr = I915_READ(GTIMR);
2013 s->gt_ier = I915_READ(GTIER);
2014 s->pm_imr = I915_READ(GEN6_PMIMR);
2015 s->pm_ier = I915_READ(GEN6_PMIER);
2016
2017 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2018 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2019
2020 /* GT SA CZ domain, 0x100000-0x138124 */
2021 s->tilectl = I915_READ(TILECTL);
2022 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2023 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2024 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2025 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2026
2027 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2028 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2029 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2030 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2031 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2032
2033 /*
2034 * Not saving any of:
2035 * DFT, 0x9800-0x9EC0
2036 * SARB, 0xB000-0xB1FC
2037 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2038 * PCI CFG
2039 */
2040}
2041
2042static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2043{
2044 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2045 u32 val;
2046 int i;
2047
2048 /* GAM 0x4000-0x4770 */
2049 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2050 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2051 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2052 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2053 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2054
2055 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2056 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2057
2058 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2059 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2060
2061 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2062 I915_WRITE(GAM_ECOCHK, s->ecochk);
2063 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2064 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2065
2066 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2067
2068 /* MBC 0x9024-0x91D0, 0x8500 */
2069 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2070 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2071 I915_WRITE(GEN6_MBCTL, s->mbctl);
2072
2073 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2074 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2075 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2076 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2077 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2078 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2079 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2080
2081 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2082 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2083 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2084 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2085 I915_WRITE(ECOBUS, s->ecobus);
2086 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2087 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2088 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2089 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2090 I915_WRITE(VLV_RCEDATA, s->rcedata);
2091 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2092
2093 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2094 I915_WRITE(GTIMR, s->gt_imr);
2095 I915_WRITE(GTIER, s->gt_ier);
2096 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2097 I915_WRITE(GEN6_PMIER, s->pm_ier);
2098
2099 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2100 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2101
2102 /* GT SA CZ domain, 0x100000-0x138124 */
2103 I915_WRITE(TILECTL, s->tilectl);
2104 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2105 /*
2106 * Preserve the GT allow wake and GFX force clock bit, they are not
2107 * be restored, as they are used to control the s0ix suspend/resume
2108 * sequence by the caller.
2109 */
2110 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2111 val &= VLV_GTLC_ALLOWWAKEREQ;
2112 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2113 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2114
2115 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2116 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2117 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2118 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2119
2120 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2121
2122 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2123 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2124 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2125 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2126 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2127}
2128
650ad970
ID		 2129int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2130{
2131 u32 val;
2132 int err;
2133
650ad970
ID		 2134 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2135 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2136 if (force_on)
2137 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2138 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2139
2140 if (!force_on)
2141 return 0;
2142
c6ddc5f3
CW		 2143 err = intel_wait_for_register(dev_priv,
2144 VLV_GTLC_SURVIVABILITY_REG,
2145 VLV_GFX_CLK_STATUS_BIT,
2146 VLV_GFX_CLK_STATUS_BIT,
2147 20);
650ad970
ID		 2148 if (err)
2149 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2150 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2151
2152 return err;
650ad970
ID		 2153}
2154
ddeea5b0
ID		 2155static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2156{
2157 u32 val;
2158 int err = 0;
2159
2160 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2161 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2162 if (allow)
2163 val |= VLV_GTLC_ALLOWWAKEREQ;
2164 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2165 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2166
b2736695
CW		 2167 err = intel_wait_for_register(dev_priv,
2168 VLV_GTLC_PW_STATUS,
2169 VLV_GTLC_ALLOWWAKEACK,
2170 allow,
2171 1);
ddeea5b0
ID		 2172 if (err)
2173 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2174
ddeea5b0 2175 return err;
ddeea5b0
ID		 2176}
2177
2178static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2179 bool wait_for_on)
2180{
2181 u32 mask;
2182 u32 val;
2183 int err;
2184
2185 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2186 val = wait_for_on ? mask : 0;
41ce405e 2187 if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
ddeea5b0
ID		 2188 return 0;
2189
2190 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
87ad3212
JN		 2191 onoff(wait_for_on),
2192 I915_READ(VLV_GTLC_PW_STATUS));
ddeea5b0
ID		 2193
2194 /*
2195 * RC6 transitioning can be delayed up to 2 msec (see
2196 * valleyview_enable_rps), use 3 msec for safety.
2197 */
41ce405e
CW		 2198 err = intel_wait_for_register(dev_priv,
2199 VLV_GTLC_PW_STATUS, mask, val,
2200 3);
ddeea5b0
ID		 2201 if (err)
2202 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2203 onoff(wait_for_on));
ddeea5b0
ID		 2204
2205 return err;
ddeea5b0
ID		 2206}
2207
2208static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2209{
2210 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2211 return;
2212
6fa283b0 2213 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2214 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2215}
2216
ebc32824 2217static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2218{
2219 u32 mask;
2220 int err;
2221
2222 /*
2223 * Bspec defines the following GT well on flags as debug only, so
2224 * don't treat them as hard failures.
2225 */
2226 (void)vlv_wait_for_gt_wells(dev_priv, false);
2227
2228 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2229 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2230
2231 vlv_check_no_gt_access(dev_priv);
2232
2233 err = vlv_force_gfx_clock(dev_priv, true);
2234 if (err)
2235 goto err1;
2236
2237 err = vlv_allow_gt_wake(dev_priv, false);
2238 if (err)
2239 goto err2;
98711167 2240
2d1fe073 2241 if (!IS_CHERRYVIEW(dev_priv))
98711167 2242 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2243
2244 err = vlv_force_gfx_clock(dev_priv, false);
2245 if (err)
2246 goto err2;
2247
2248 return 0;
2249
2250err2:
2251 /* For safety always re-enable waking and disable gfx clock forcing */
2252 vlv_allow_gt_wake(dev_priv, true);
2253err1:
2254 vlv_force_gfx_clock(dev_priv, false);
2255
2256 return err;
2257}
2258
016970be
SK		 2259static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2260 bool rpm_resume)
ddeea5b0 2261{
91c8a326 2262 struct drm_device *dev = &dev_priv->drm;
ddeea5b0
ID		 2263 int err;
2264 int ret;
2265
2266 /*
2267 * If any of the steps fail just try to continue, that's the best we
2268 * can do at this point. Return the first error code (which will also
2269 * leave RPM permanently disabled).
2270 */
2271 ret = vlv_force_gfx_clock(dev_priv, true);
2272
2d1fe073 2273 if (!IS_CHERRYVIEW(dev_priv))
98711167 2274 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2275
2276 err = vlv_allow_gt_wake(dev_priv, true);
2277 if (!ret)
2278 ret = err;
2279
2280 err = vlv_force_gfx_clock(dev_priv, false);
2281 if (!ret)
2282 ret = err;
2283
2284 vlv_check_no_gt_access(dev_priv);
2285
7c108fd8 2286 if (rpm_resume)
016970be 2287 intel_init_clock_gating(dev);
ddeea5b0
ID		 2288
2289 return ret;
2290}
2291
c49d13ee 2292static int intel_runtime_suspend(struct device *kdev)
8a187455 2293{
c49d13ee 2294 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2295 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2296 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2297 int ret;
8a187455 2298
dc97997a 2299 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2300 return -ENODEV;
2301
6772ffe0 2302 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7
ID		 2303 return -ENODEV;
2304
8a187455
PZ		 2305 DRM_DEBUG_KMS("Suspending device\n");
2306
1f814dac
ID		 2307 disable_rpm_wakeref_asserts(dev_priv);
2308
d6102977
ID		 2309 /*
2310 * We are safe here against re-faults, since the fault handler takes
2311 * an RPM reference.
2312 */
7c108fd8 2313 i915_gem_runtime_suspend(dev_priv);
d6102977 2314
a1c41994
AD		 2315 intel_guc_suspend(dev);
2316
2eb5252e 2317 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2318
507e126e
ID		 2319 ret = 0;
2320 if (IS_BROXTON(dev_priv)) {
2321 bxt_display_core_uninit(dev_priv);
2322 bxt_enable_dc9(dev_priv);
2323 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2324 hsw_enable_pc8(dev_priv);
2325 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2326 ret = vlv_suspend_complete(dev_priv);
2327 }
2328
0ab9cfeb
ID		 2329 if (ret) {
2330 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2331 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2332
1f814dac
ID		 2333 enable_rpm_wakeref_asserts(dev_priv);
2334
0ab9cfeb
ID		 2335 return ret;
2336 }
a8a8bd54 2337
dc97997a 2338 intel_uncore_forcewake_reset(dev_priv, false);
1f814dac
ID		 2339
2340 enable_rpm_wakeref_asserts(dev_priv);
2341 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2342
bc3b9346 2343 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2344 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2345
8a187455 2346 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2347
2348 /*
c8a0bd42
PZ		 2349 * FIXME: We really should find a document that references the arguments
2350 * used below!
1fb2362b 2351 */
6f9f4b7a 2352 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2353 /*
2354 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2355 * being detected, and the call we do at intel_runtime_resume()
2356 * won't be able to restore them. Since PCI_D3hot matches the
2357 * actual specification and appears to be working, use it.
2358 */
6f9f4b7a 2359 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2360 } else {
c8a0bd42
PZ		 2361 /*
2362 * current versions of firmware which depend on this opregion
2363 * notification have repurposed the D1 definition to mean
2364 * "runtime suspended" vs. what you would normally expect (D3)
2365 * to distinguish it from notifications that might be sent via
2366 * the suspend path.
2367 */
6f9f4b7a 2368 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2369 }
8a187455 2370
59bad947 2371 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2372
19625e85
L		 2373 if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2374 intel_hpd_poll_init(dev_priv);
2375
a8a8bd54 2376 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2377 return 0;
2378}
2379
c49d13ee 2380static int intel_runtime_resume(struct device *kdev)
8a187455 2381{
c49d13ee 2382 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2383 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2384 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2385 int ret = 0;
8a187455 2386
6772ffe0 2387 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7 2388 return -ENODEV;
8a187455
PZ		 2389
2390 DRM_DEBUG_KMS("Resuming device\n");
2391
1f814dac
ID		 2392 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2393 disable_rpm_wakeref_asserts(dev_priv);
2394
6f9f4b7a 2395 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2396 dev_priv->pm.suspended = false;
55ec45c2
MK		 2397 if (intel_uncore_unclaimed_mmio(dev_priv))
2398 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2399
a1c41994
AD		 2400 intel_guc_resume(dev);
2401
1a5df187
PZ		 2402 if (IS_GEN6(dev_priv))
2403 intel_init_pch_refclk(dev);
31335cec 2404
e2d214ae 2405 if (IS_BROXTON(dev_priv)) {
507e126e
ID		 2406 bxt_disable_dc9(dev_priv);
2407 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2408 if (dev_priv->csr.dmc_payload &&
2409 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2410 gen9_enable_dc5(dev_priv);
507e126e 2411 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2412 hsw_disable_pc8(dev_priv);
507e126e 2413 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2414 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2415 }
1a5df187 2416
0ab9cfeb
ID		 2417 /*
2418 * No point of rolling back things in case of an error, as the best
2419 * we can do is to hope that things will still work (and disable RPM).
2420 */
92b806d3 2421 i915_gem_init_swizzling(dev);
92b806d3 2422
b963291c 2423 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2424
2425 /*
2426 * On VLV/CHV display interrupts are part of the display
2427 * power well, so hpd is reinitialized from there. For
2428 * everyone else do it here.
2429 */
666a4537 2430 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2431 intel_hpd_init(dev_priv);
2432
1f814dac
ID		 2433 enable_rpm_wakeref_asserts(dev_priv);
2434
0ab9cfeb
ID		 2435 if (ret)
2436 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2437 else
2438 DRM_DEBUG_KMS("Device resumed\n");
2439
2440 return ret;
8a187455
PZ		 2441}
2442
42f5551d 2443const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2444 /*
2445 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2446 * PMSG_RESUME]
2447 */
0206e353 2448 .suspend = i915_pm_suspend,
76c4b250
ID		 2449 .suspend_late = i915_pm_suspend_late,
2450 .resume_early = i915_pm_resume_early,
0206e353 2451 .resume = i915_pm_resume,
5545dbbf
ID		 2452
2453 /*
2454 * S4 event handlers
2455 * @freeze, @freeze_late : called (1) before creating the
2456 * hibernation image [PMSG_FREEZE] and
2457 * (2) after rebooting, before restoring
2458 * the image [PMSG_QUIESCE]
2459 * @thaw, @thaw_early : called (1) after creating the hibernation
2460 * image, before writing it [PMSG_THAW]
2461 * and (2) after failing to create or
2462 * restore the image [PMSG_RECOVER]
2463 * @poweroff, @poweroff_late: called after writing the hibernation
2464 * image, before rebooting [PMSG_HIBERNATE]
2465 * @restore, @restore_early : called after rebooting and restoring the
2466 * hibernation image [PMSG_RESTORE]
2467 */
1f19ac2a
CW		 2468 .freeze = i915_pm_freeze,
2469 .freeze_late = i915_pm_freeze_late,
2470 .thaw_early = i915_pm_thaw_early,
2471 .thaw = i915_pm_thaw,
36d61e67 2472 .poweroff = i915_pm_suspend,
ab3be73f 2473 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2474 .restore_early = i915_pm_restore_early,
2475 .restore = i915_pm_restore,
5545dbbf
ID		 2476
2477 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2478 .runtime_suspend = intel_runtime_suspend,
2479 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2480};
2481
78b68556 2482static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2483 .fault = i915_gem_fault,
ab00b3e5
JB		 2484 .open = drm_gem_vm_open,
2485 .close = drm_gem_vm_close,
de151cf6
JB		 2486};
2487
e08e96de
AV		 2488static const struct file_operations i915_driver_fops = {
2489 .owner = THIS_MODULE,
2490 .open = drm_open,
2491 .release = drm_release,
2492 .unlocked_ioctl = drm_ioctl,
2493 .mmap = drm_gem_mmap,
2494 .poll = drm_poll,
e08e96de
AV		 2495 .read = drm_read,
2496#ifdef CONFIG_COMPAT
2497 .compat_ioctl = i915_compat_ioctl,
2498#endif
2499 .llseek = noop_llseek,
2500};
2501
0673ad47
CW		 2502static int
2503i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2504 struct drm_file *file)
2505{
2506 return -ENODEV;
2507}
2508
2509static const struct drm_ioctl_desc i915_ioctls[] = {
2510 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2511 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2512 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2513 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2514 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2515 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2516 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2517 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2518 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2519 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2520 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2521 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2522 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2523 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2524 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2525 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2526 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2527 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2528 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2529 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2530 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2531 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2532 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2533 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2534 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2535 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2536 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2537 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2538 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2539 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2540 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2541 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2542 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2543 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2544 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2545 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2546 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2547 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2548 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2549 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2550 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2551 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2552 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2553 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2554 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2555 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2556 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2557 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2558 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2559 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2560 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2561 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2562};
2563
1da177e4 2564static struct drm_driver driver = {
0c54781b
MW		 2565 /* Don't use MTRRs here; the Xserver or userspace app should
2566 * deal with them for Intel hardware.
792d2b9a 2567 */
673a394b 2568 .driver_features =
10ba5012 2569 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1751fcf9 2570 DRIVER_RENDER | DRIVER_MODESET,
673a394b 2571 .open = i915_driver_open,
22eae947
DA		 2572 .lastclose = i915_driver_lastclose,
2573 .preclose = i915_driver_preclose,
673a394b 2574 .postclose = i915_driver_postclose,
915b4d11 2575 .set_busid = drm_pci_set_busid,
d8e29209 2576
b1f788c6 2577 .gem_close_object = i915_gem_close_object,
f0cd5182 2578 .gem_free_object_unlocked = i915_gem_free_object,
de151cf6 2579 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2580
2581 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2582 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2583 .gem_prime_export = i915_gem_prime_export,
2584 .gem_prime_import = i915_gem_prime_import,
2585
ff72145b 2586 .dumb_create = i915_gem_dumb_create,
da6b51d0 2587 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 2588 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 2589 .ioctls = i915_ioctls,
0673ad47 2590 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2591 .fops = &i915_driver_fops,
22eae947
DA		 2592 .name = DRIVER_NAME,
2593 .desc = DRIVER_DESC,
2594 .date = DRIVER_DATE,
2595 .major = DRIVER_MAJOR,
2596 .minor = DRIVER_MINOR,
2597 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2598};
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