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drm/i915: get a runtime PM ref for the deferred GT powersave enabling
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT
1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
760285e7
DH
31#include <drm/drmP.h>
32#include <drm/i915_drm.h>
1da177e4 33#include "i915_drv.h"
990bbdad 34#include "i915_trace.h"
f49f0586 35#include "intel_drv.h"
1da177e4 36
79e53945 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
760285e7 39#include <drm/drm_crtc_helper.h>
79e53945 40
112b715e
KH
41static struct drm_driver driver;
42
a57c774a
AK
43#define GEN_DEFAULT_PIPEOFFSETS \
44 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
45 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
46 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
47 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
48 .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
49 .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51
52
9a7e8492 53static const struct intel_device_info intel_i830_info = {
7eb552ae 54 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
31578148 55 .has_overlay = 1, .overlay_needs_physical = 1,
73ae478c 56 .ring_mask = RENDER_RING,
a57c774a 57 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
58};
59
9a7e8492 60static const struct intel_device_info intel_845g_info = {
7eb552ae 61 .gen = 2, .num_pipes = 1,
31578148 62 .has_overlay = 1, .overlay_needs_physical = 1,
73ae478c 63 .ring_mask = RENDER_RING,
a57c774a 64 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
65};
66
9a7e8492 67static const struct intel_device_info intel_i85x_info = {
7eb552ae 68 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
5ce8ba7c 69 .cursor_needs_physical = 1,
31578148 70 .has_overlay = 1, .overlay_needs_physical = 1,
fd70d52a 71 .has_fbc = 1,
73ae478c 72 .ring_mask = RENDER_RING,
a57c774a 73 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
74};
75
9a7e8492 76static const struct intel_device_info intel_i865g_info = {
7eb552ae 77 .gen = 2, .num_pipes = 1,
31578148 78 .has_overlay = 1, .overlay_needs_physical = 1,
73ae478c 79 .ring_mask = RENDER_RING,
a57c774a 80 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
81};
82
9a7e8492 83static const struct intel_device_info intel_i915g_info = {
7eb552ae 84 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
31578148 85 .has_overlay = 1, .overlay_needs_physical = 1,
73ae478c 86 .ring_mask = RENDER_RING,
a57c774a 87 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2 88};
9a7e8492 89static const struct intel_device_info intel_i915gm_info = {
7eb552ae 90 .gen = 3, .is_mobile = 1, .num_pipes = 2,
b295d1b6 91 .cursor_needs_physical = 1,
31578148 92 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 93 .supports_tv = 1,
fd70d52a 94 .has_fbc = 1,
73ae478c 95 .ring_mask = RENDER_RING,
a57c774a 96 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2 97};
9a7e8492 98static const struct intel_device_info intel_i945g_info = {
7eb552ae 99 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
31578148 100 .has_overlay = 1, .overlay_needs_physical = 1,
73ae478c 101 .ring_mask = RENDER_RING,
a57c774a 102 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2 103};
9a7e8492 104static const struct intel_device_info intel_i945gm_info = {
7eb552ae 105 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
b295d1b6 106 .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 107 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 108 .supports_tv = 1,
fd70d52a 109 .has_fbc = 1,
73ae478c 110 .ring_mask = RENDER_RING,
a57c774a 111 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
112};
113
9a7e8492 114static const struct intel_device_info intel_i965g_info = {
7eb552ae 115 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
c96c3a8c 116 .has_hotplug = 1,
31578148 117 .has_overlay = 1,
73ae478c 118 .ring_mask = RENDER_RING,
a57c774a 119 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
120};
121
9a7e8492 122static const struct intel_device_info intel_i965gm_info = {
7eb552ae 123 .gen = 4, .is_crestline = 1, .num_pipes = 2,
e3c4e5dd 124 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
31578148 125 .has_overlay = 1,
a6c45cf0 126 .supports_tv = 1,
73ae478c 127 .ring_mask = RENDER_RING,
a57c774a 128 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
129};
130
9a7e8492 131static const struct intel_device_info intel_g33_info = {
7eb552ae 132 .gen = 3, .is_g33 = 1, .num_pipes = 2,
c96c3a8c 133 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 134 .has_overlay = 1,
73ae478c 135 .ring_mask = RENDER_RING,
a57c774a 136 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
137};
138
9a7e8492 139static const struct intel_device_info intel_g45_info = {
7eb552ae 140 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
c96c3a8c 141 .has_pipe_cxsr = 1, .has_hotplug = 1,
73ae478c 142 .ring_mask = RENDER_RING | BSD_RING,
a57c774a 143 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
144};
145
9a7e8492 146static const struct intel_device_info intel_gm45_info = {
7eb552ae 147 .gen = 4, .is_g4x = 1, .num_pipes = 2,
e3c4e5dd 148 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
c96c3a8c 149 .has_pipe_cxsr = 1, .has_hotplug = 1,
a6c45cf0 150 .supports_tv = 1,
73ae478c 151 .ring_mask = RENDER_RING | BSD_RING,
a57c774a 152 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
153};
154
9a7e8492 155static const struct intel_device_info intel_pineview_info = {
7eb552ae 156 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
c96c3a8c 157 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 158 .has_overlay = 1,
a57c774a 159 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
160};
161
9a7e8492 162static const struct intel_device_info intel_ironlake_d_info = {
7eb552ae 163 .gen = 5, .num_pipes = 2,
5a117db7 164 .need_gfx_hws = 1, .has_hotplug = 1,
73ae478c 165 .ring_mask = RENDER_RING | BSD_RING,
a57c774a 166 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
167};
168
9a7e8492 169static const struct intel_device_info intel_ironlake_m_info = {
7eb552ae 170 .gen = 5, .is_mobile = 1, .num_pipes = 2,
e3c4e5dd 171 .need_gfx_hws = 1, .has_hotplug = 1,
c1a9f047 172 .has_fbc = 1,
73ae478c 173 .ring_mask = RENDER_RING | BSD_RING,
a57c774a 174 GEN_DEFAULT_PIPEOFFSETS,
cfdf1fa2
KH
175};
176
9a7e8492 177static const struct intel_device_info intel_sandybridge_d_info = {
7eb552ae 178 .gen = 6, .num_pipes = 2,
c96c3a8c 179 .need_gfx_hws = 1, .has_hotplug = 1,
cbaef0f1 180 .has_fbc = 1,
73ae478c 181 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
3d29b842 182 .has_llc = 1,
a57c774a 183 GEN_DEFAULT_PIPEOFFSETS,
f6e450a6
EA
184};
185
9a7e8492 186static const struct intel_device_info intel_sandybridge_m_info = {
7eb552ae 187 .gen = 6, .is_mobile = 1, .num_pipes = 2,
c96c3a8c 188 .need_gfx_hws = 1, .has_hotplug = 1,
9c04f015 189 .has_fbc = 1,
73ae478c 190 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
3d29b842 191 .has_llc = 1,
a57c774a 192 GEN_DEFAULT_PIPEOFFSETS,
a13e4093
EA
193};
194
219f4fdb
BW
195#define GEN7_FEATURES \
196 .gen = 7, .num_pipes = 3, \
197 .need_gfx_hws = 1, .has_hotplug = 1, \
cbaef0f1 198 .has_fbc = 1, \
73ae478c 199 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
ab484f8f 200 .has_llc = 1
219f4fdb 201
c76b615c 202static const struct intel_device_info intel_ivybridge_d_info = {
219f4fdb
BW
203 GEN7_FEATURES,
204 .is_ivybridge = 1,
a57c774a 205 GEN_DEFAULT_PIPEOFFSETS,
c76b615c
JB
206};
207
208static const struct intel_device_info intel_ivybridge_m_info = {
219f4fdb
BW
209 GEN7_FEATURES,
210 .is_ivybridge = 1,
211 .is_mobile = 1,
a57c774a 212 GEN_DEFAULT_PIPEOFFSETS,
c76b615c
JB
213};
214
999bcdea
BW
215static const struct intel_device_info intel_ivybridge_q_info = {
216 GEN7_FEATURES,
217 .is_ivybridge = 1,
218 .num_pipes = 0, /* legal, last one wins */
a57c774a 219 GEN_DEFAULT_PIPEOFFSETS,
999bcdea
BW
220};
221
70a3eb7a 222static const struct intel_device_info intel_valleyview_m_info = {
219f4fdb
BW
223 GEN7_FEATURES,
224 .is_mobile = 1,
225 .num_pipes = 2,
70a3eb7a 226 .is_valleyview = 1,
fba5d532 227 .display_mmio_offset = VLV_DISPLAY_BASE,
cbaef0f1 228 .has_fbc = 0, /* legal, last one wins */
30ccd964 229 .has_llc = 0, /* legal, last one wins */
a57c774a 230 GEN_DEFAULT_PIPEOFFSETS,
70a3eb7a
JB
231};
232
233static const struct intel_device_info intel_valleyview_d_info = {
219f4fdb
BW
234 GEN7_FEATURES,
235 .num_pipes = 2,
70a3eb7a 236 .is_valleyview = 1,
fba5d532 237 .display_mmio_offset = VLV_DISPLAY_BASE,
cbaef0f1 238 .has_fbc = 0, /* legal, last one wins */
30ccd964 239 .has_llc = 0, /* legal, last one wins */
a57c774a 240 GEN_DEFAULT_PIPEOFFSETS,
70a3eb7a
JB
241};
242
4cae9ae0 243static const struct intel_device_info intel_haswell_d_info = {
219f4fdb
BW
244 GEN7_FEATURES,
245 .is_haswell = 1,
dd93be58 246 .has_ddi = 1,
30568c45 247 .has_fpga_dbg = 1,
73ae478c 248 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
a57c774a 249 GEN_DEFAULT_PIPEOFFSETS,
4cae9ae0
ED
250};
251
252static const struct intel_device_info intel_haswell_m_info = {
219f4fdb
BW
253 GEN7_FEATURES,
254 .is_haswell = 1,
255 .is_mobile = 1,
dd93be58 256 .has_ddi = 1,
30568c45 257 .has_fpga_dbg = 1,
73ae478c 258 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
a57c774a 259 GEN_DEFAULT_PIPEOFFSETS,
c76b615c
JB
260};
261
4d4dead6 262static const struct intel_device_info intel_broadwell_d_info = {
4b30553d 263 .gen = 8, .num_pipes = 3,
4d4dead6
BW
264 .need_gfx_hws = 1, .has_hotplug = 1,
265 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
266 .has_llc = 1,
267 .has_ddi = 1,
8f94d24b 268 .has_fbc = 1,
a57c774a 269 GEN_DEFAULT_PIPEOFFSETS,
4d4dead6
BW
270};
271
272static const struct intel_device_info intel_broadwell_m_info = {
4b30553d 273 .gen = 8, .is_mobile = 1, .num_pipes = 3,
4d4dead6
BW
274 .need_gfx_hws = 1, .has_hotplug = 1,
275 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
276 .has_llc = 1,
277 .has_ddi = 1,
8f94d24b 278 .has_fbc = 1,
a57c774a 279 GEN_DEFAULT_PIPEOFFSETS,
4d4dead6
BW
280};
281
fd3c269f
ZY
282static const struct intel_device_info intel_broadwell_gt3d_info = {
283 .gen = 8, .num_pipes = 3,
284 .need_gfx_hws = 1, .has_hotplug = 1,
845f74a7 285 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
fd3c269f
ZY
286 .has_llc = 1,
287 .has_ddi = 1,
288 .has_fbc = 1,
289 GEN_DEFAULT_PIPEOFFSETS,
290};
291
292static const struct intel_device_info intel_broadwell_gt3m_info = {
293 .gen = 8, .is_mobile = 1, .num_pipes = 3,
294 .need_gfx_hws = 1, .has_hotplug = 1,
845f74a7 295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
fd3c269f
ZY
296 .has_llc = 1,
297 .has_ddi = 1,
298 .has_fbc = 1,
299 GEN_DEFAULT_PIPEOFFSETS,
300};
301
a0a18075
JB
302/*
303 * Make sure any device matches here are from most specific to most
304 * general. For example, since the Quanta match is based on the subsystem
305 * and subvendor IDs, we need it to come before the more general IVB
306 * PCI ID matches, otherwise we'll use the wrong info struct above.
307 */
308#define INTEL_PCI_IDS \
309 INTEL_I830_IDS(&intel_i830_info), \
310 INTEL_I845G_IDS(&intel_845g_info), \
311 INTEL_I85X_IDS(&intel_i85x_info), \
312 INTEL_I865G_IDS(&intel_i865g_info), \
313 INTEL_I915G_IDS(&intel_i915g_info), \
314 INTEL_I915GM_IDS(&intel_i915gm_info), \
315 INTEL_I945G_IDS(&intel_i945g_info), \
316 INTEL_I945GM_IDS(&intel_i945gm_info), \
317 INTEL_I965G_IDS(&intel_i965g_info), \
318 INTEL_G33_IDS(&intel_g33_info), \
319 INTEL_I965GM_IDS(&intel_i965gm_info), \
320 INTEL_GM45_IDS(&intel_gm45_info), \
321 INTEL_G45_IDS(&intel_g45_info), \
322 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
323 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
324 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
325 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
326 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
327 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
328 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
329 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
330 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
331 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
332 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
4d4dead6 333 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
fd3c269f
ZY
334 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
335 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
336 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
337 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info)
a0a18075 338
6103da0d 339static const struct pci_device_id pciidlist[] = { /* aka */
a0a18075 340 INTEL_PCI_IDS,
49ae35f2 341 {0, 0, 0}
1da177e4
LT
342};
343
79e53945
JB
344#if defined(CONFIG_DRM_I915_KMS)
345MODULE_DEVICE_TABLE(pci, pciidlist);
346#endif
347
0206e353 348void intel_detect_pch(struct drm_device *dev)
3bad0781
ZW
349{
350 struct drm_i915_private *dev_priv = dev->dev_private;
bcdb72ac 351 struct pci_dev *pch = NULL;
3bad0781 352
ce1bb329
BW
353 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
354 * (which really amounts to a PCH but no South Display).
355 */
356 if (INTEL_INFO(dev)->num_pipes == 0) {
357 dev_priv->pch_type = PCH_NOP;
ce1bb329
BW
358 return;
359 }
360
3bad0781
ZW
361 /*
362 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
363 * make graphics device passthrough work easy for VMM, that only
364 * need to expose ISA bridge to let driver know the real hardware
365 * underneath. This is a requirement from virtualization team.
6a9c4b35
RG
366 *
367 * In some virtualized environments (e.g. XEN), there is irrelevant
368 * ISA bridge in the system. To work reliably, we should scan trhough
369 * all the ISA bridge devices and check for the first match, instead
370 * of only checking the first one.
3bad0781 371 */
bcdb72ac 372 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
3bad0781 373 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
bcdb72ac 374 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
17a303ec 375 dev_priv->pch_id = id;
3bad0781 376
90711d50
JB
377 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
378 dev_priv->pch_type = PCH_IBX;
379 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
7fcb83cd 380 WARN_ON(!IS_GEN5(dev));
90711d50 381 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
3bad0781
ZW
382 dev_priv->pch_type = PCH_CPT;
383 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
7fcb83cd 384 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
c792513b
JB
385 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
386 /* PantherPoint is CPT compatible */
387 dev_priv->pch_type = PCH_CPT;
492ab669 388 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
7fcb83cd 389 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
eb877ebf
ED
390 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
391 dev_priv->pch_type = PCH_LPT;
392 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
7fcb83cd 393 WARN_ON(!IS_HASWELL(dev));
08e1413d 394 WARN_ON(IS_ULT(dev));
018f52c9
PZ
395 } else if (IS_BROADWELL(dev)) {
396 dev_priv->pch_type = PCH_LPT;
397 dev_priv->pch_id =
398 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
399 DRM_DEBUG_KMS("This is Broadwell, assuming "
400 "LynxPoint LP PCH\n");
e76e0634
BW
401 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
402 dev_priv->pch_type = PCH_LPT;
403 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
404 WARN_ON(!IS_HASWELL(dev));
405 WARN_ON(!IS_ULT(dev));
bcdb72ac
ID
406 } else
407 continue;
408
6a9c4b35 409 break;
3bad0781 410 }
3bad0781 411 }
6a9c4b35 412 if (!pch)
bcdb72ac
ID
413 DRM_DEBUG_KMS("No PCH found.\n");
414
415 pci_dev_put(pch);
3bad0781
ZW
416}
417
2911a35b
BW
418bool i915_semaphore_is_enabled(struct drm_device *dev)
419{
420 if (INTEL_INFO(dev)->gen < 6)
a08acaf2 421 return false;
2911a35b 422
d330a953
JN
423 if (i915.semaphores >= 0)
424 return i915.semaphores;
2911a35b 425
c923facd
JN
426 /* Until we get further testing... */
427 if (IS_GEN8(dev))
428 return false;
429
59de3295 430#ifdef CONFIG_INTEL_IOMMU
2911a35b 431 /* Enable semaphores on SNB when IO remapping is off */
59de3295
DV
432 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
433 return false;
434#endif
2911a35b 435
a08acaf2 436 return true;
2911a35b
BW
437}
438
84b79f8d 439static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 440{
61caf87c 441 struct drm_i915_private *dev_priv = dev->dev_private;
24576d23 442 struct drm_crtc *crtc;
61caf87c 443
8a187455
PZ
444 intel_runtime_pm_get(dev_priv);
445
b8efb17b
ZR
446 /* ignore lid events during suspend */
447 mutex_lock(&dev_priv->modeset_restore_lock);
448 dev_priv->modeset_restore = MODESET_SUSPENDED;
449 mutex_unlock(&dev_priv->modeset_restore_lock);
450
c67a470b
PZ
451 /* We do a lot of poking in a lot of registers, make sure they work
452 * properly. */
da7e29bd 453 intel_display_set_init_power(dev_priv, true);
cb10799c 454
5bcf719b
DA
455 drm_kms_helper_poll_disable(dev);
456
ba8bbcf6 457 pci_save_state(dev->pdev);
ba8bbcf6 458
5669fcac 459 /* If KMS is active, we do the leavevt stuff here */
226485e9 460 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
db1b76ca
DV
461 int error;
462
45c5f202 463 error = i915_gem_suspend(dev);
84b79f8d 464 if (error) {
226485e9 465 dev_err(&dev->pdev->dev,
84b79f8d
RW
466 "GEM idle failed, resume might fail\n");
467 return error;
468 }
a261b246 469
1a01ab3b
JB
470 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
471
226485e9 472 drm_irq_uninstall(dev);
15239099 473 dev_priv->enable_hotplug_processing = false;
24576d23
JB
474 /*
475 * Disable CRTCs directly since we want to preserve sw state
476 * for _thaw.
477 */
7c063c72 478 mutex_lock(&dev->mode_config.mutex);
24576d23
JB
479 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
480 dev_priv->display.crtc_disable(crtc);
7c063c72 481 mutex_unlock(&dev->mode_config.mutex);
7d708ee4
ID
482
483 intel_modeset_suspend_hw(dev);
5669fcac
JB
484 }
485
828c7908
BW
486 i915_gem_suspend_gtt_mappings(dev);
487
9e06dd39
JB
488 i915_save_state(dev);
489
44834a67 490 intel_opregion_fini(dev);
28d85cd3 491 intel_uncore_fini(dev);
8ee1c3db 492
3fa016a0 493 console_lock();
b6f3eff7 494 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
3fa016a0
DA
495 console_unlock();
496
62d5d69b
MK
497 dev_priv->suspend_count++;
498
61caf87c 499 return 0;
84b79f8d
RW
500}
501
6a9ee8af 502int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW
503{
504 int error;
505
506 if (!dev || !dev->dev_private) {
507 DRM_ERROR("dev: %p\n", dev);
508 DRM_ERROR("DRM not initialized, aborting suspend.\n");
509 return -ENODEV;
510 }
511
512 if (state.event == PM_EVENT_PRETHAW)
513 return 0;
514
5bcf719b
DA
515
516 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
517 return 0;
6eecba33 518
84b79f8d
RW
519 error = i915_drm_freeze(dev);
520 if (error)
521 return error;
522
b932ccb5
DA
523 if (state.event == PM_EVENT_SUSPEND) {
524 /* Shut down the device */
525 pci_disable_device(dev->pdev);
526 pci_set_power_state(dev->pdev, PCI_D3hot);
527 }
ba8bbcf6
JB
528
529 return 0;
530}
531
073f34d9
JB
532void intel_console_resume(struct work_struct *work)
533{
534 struct drm_i915_private *dev_priv =
535 container_of(work, struct drm_i915_private,
536 console_resume_work);
537 struct drm_device *dev = dev_priv->dev;
538
539 console_lock();
b6f3eff7 540 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
073f34d9
JB
541 console_unlock();
542}
543
bb60b969
JB
544static void intel_resume_hotplug(struct drm_device *dev)
545{
546 struct drm_mode_config *mode_config = &dev->mode_config;
547 struct intel_encoder *encoder;
548
549 mutex_lock(&mode_config->mutex);
550 DRM_DEBUG_KMS("running encoder hotplug functions\n");
551
552 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
553 if (encoder->hot_plug)
554 encoder->hot_plug(encoder);
555
556 mutex_unlock(&mode_config->mutex);
557
558 /* Just fire off a uevent and let userspace tell us what to do */
559 drm_helper_hpd_irq_event(dev);
560}
561
76c4b250 562static int i915_drm_thaw_early(struct drm_device *dev)
ba8bbcf6 563{
5669fcac 564 struct drm_i915_private *dev_priv = dev->dev_private;
8ee1c3db 565
c9f7fbf9 566 intel_uncore_early_sanitize(dev);
9d49c0ef 567 intel_uncore_sanitize(dev);
76c4b250
ID
568 intel_power_domains_init_hw(dev_priv);
569
570 return 0;
571}
572
573static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
574{
575 struct drm_i915_private *dev_priv = dev->dev_private;
9d49c0ef
PZ
576
577 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
578 restore_gtt_mappings) {
579 mutex_lock(&dev->struct_mutex);
580 i915_gem_restore_gtt_mappings(dev);
581 mutex_unlock(&dev->struct_mutex);
582 }
583
61caf87c 584 i915_restore_state(dev);
44834a67 585 intel_opregion_setup(dev);
61caf87c 586
5669fcac
JB
587 /* KMS EnterVT equivalent */
588 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
dde86e2d 589 intel_init_pch_refclk(dev);
754970ee 590 drm_mode_config_reset(dev);
1833b134 591
5669fcac 592 mutex_lock(&dev->struct_mutex);
074c6ada
CW
593 if (i915_gem_init_hw(dev)) {
594 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
595 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
596 }
5669fcac 597 mutex_unlock(&dev->struct_mutex);
226485e9 598
15239099 599 /* We need working interrupts for modeset enabling ... */
bb0f1b5c 600 drm_irq_install(dev, dev->pdev->irq);
15239099 601
1833b134 602 intel_modeset_init_hw(dev);
24576d23
JB
603
604 drm_modeset_lock_all(dev);
605 intel_modeset_setup_hw_state(dev, true);
606 drm_modeset_unlock_all(dev);
15239099
DV
607
608 /*
609 * ... but also need to make sure that hotplug processing
610 * doesn't cause havoc. Like in the driver load code we don't
611 * bother with the tiny race here where we might loose hotplug
612 * notifications.
613 * */
20afbda2 614 intel_hpd_init(dev);
15239099 615 dev_priv->enable_hotplug_processing = true;
bb60b969
JB
616 /* Config may have changed between suspend and resume */
617 intel_resume_hotplug(dev);
d5bb081b 618 }
1daed3fb 619
44834a67
CW
620 intel_opregion_init(dev);
621
073f34d9
JB
622 /*
623 * The console lock can be pretty contented on resume due
624 * to all the printk activity. Try to keep it out of the hot
625 * path of resume if possible.
626 */
627 if (console_trylock()) {
b6f3eff7 628 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
073f34d9
JB
629 console_unlock();
630 } else {
631 schedule_work(&dev_priv->console_resume_work);
632 }
633
b8efb17b
ZR
634 mutex_lock(&dev_priv->modeset_restore_lock);
635 dev_priv->modeset_restore = MODESET_DONE;
636 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455
PZ
637
638 intel_runtime_pm_put(dev_priv);
074c6ada 639 return 0;
84b79f8d
RW
640}
641
1abd02e2
JB
642static int i915_drm_thaw(struct drm_device *dev)
643{
7f16e5c1 644 if (drm_core_check_feature(dev, DRIVER_MODESET))
828c7908 645 i915_check_and_clear_faults(dev);
1abd02e2 646
9d49c0ef 647 return __i915_drm_thaw(dev, true);
84b79f8d
RW
648}
649
76c4b250 650static int i915_resume_early(struct drm_device *dev)
84b79f8d 651{
5bcf719b
DA
652 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
653 return 0;
654
76c4b250
ID
655 /*
656 * We have a resume ordering issue with the snd-hda driver also
657 * requiring our device to be power up. Due to the lack of a
658 * parent/child relationship we currently solve this with an early
659 * resume hook.
660 *
661 * FIXME: This should be solved with a special hdmi sink device or
662 * similar so that power domains can be employed.
663 */
84b79f8d
RW
664 if (pci_enable_device(dev->pdev))
665 return -EIO;
666
667 pci_set_master(dev->pdev);
668
76c4b250
ID
669 return i915_drm_thaw_early(dev);
670}
671
672int i915_resume(struct drm_device *dev)
673{
674 struct drm_i915_private *dev_priv = dev->dev_private;
675 int ret;
676
1abd02e2
JB
677 /*
678 * Platforms with opregion should have sane BIOS, older ones (gen3 and
9d49c0ef
PZ
679 * earlier) need to restore the GTT mappings since the BIOS might clear
680 * all our scratch PTEs.
1abd02e2 681 */
9d49c0ef 682 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
6eecba33
CW
683 if (ret)
684 return ret;
685
686 drm_kms_helper_poll_enable(dev);
687 return 0;
ba8bbcf6
JB
688}
689
76c4b250
ID
690static int i915_resume_legacy(struct drm_device *dev)
691{
692 i915_resume_early(dev);
693 i915_resume(dev);
694
695 return 0;
696}
697
11ed50ec 698/**
f3953dcb 699 * i915_reset - reset chip after a hang
11ed50ec 700 * @dev: drm device to reset
11ed50ec
BG
701 *
702 * Reset the chip. Useful if a hang is detected. Returns zero on successful
703 * reset or otherwise an error code.
704 *
705 * Procedure is fairly simple:
706 * - reset the chip using the reset reg
707 * - re-init context state
708 * - re-init hardware status page
709 * - re-init ring buffer
710 * - re-init interrupt state
711 * - re-init display
712 */
d4b8bb2a 713int i915_reset(struct drm_device *dev)
11ed50ec 714{
50227e1c 715 struct drm_i915_private *dev_priv = dev->dev_private;
2e7c8ee7 716 bool simulated;
0573ed4a 717 int ret;
11ed50ec 718
d330a953 719 if (!i915.reset)
d78cb50b
CW
720 return 0;
721
d54a02c0 722 mutex_lock(&dev->struct_mutex);
11ed50ec 723
069efc1d 724 i915_gem_reset(dev);
77f01230 725
2e7c8ee7
CW
726 simulated = dev_priv->gpu_error.stop_rings != 0;
727
be62acb4
MK
728 ret = intel_gpu_reset(dev);
729
730 /* Also reset the gpu hangman. */
731 if (simulated) {
732 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
733 dev_priv->gpu_error.stop_rings = 0;
734 if (ret == -ENODEV) {
f2d91a2c
DV
735 DRM_INFO("Reset not implemented, but ignoring "
736 "error for simulated gpu hangs\n");
be62acb4
MK
737 ret = 0;
738 }
2e7c8ee7 739 }
be62acb4 740
0573ed4a 741 if (ret) {
f2d91a2c 742 DRM_ERROR("Failed to reset chip: %i\n", ret);
f953c935 743 mutex_unlock(&dev->struct_mutex);
f803aa55 744 return ret;
11ed50ec
BG
745 }
746
747 /* Ok, now get things going again... */
748
749 /*
750 * Everything depends on having the GTT running, so we need to start
751 * there. Fortunately we don't need to do this unless we reset the
752 * chip at a PCI level.
753 *
754 * Next we need to restore the context, but we don't use those
755 * yet either...
756 *
757 * Ring buffer needs to be re-initialized in the KMS case, or if X
758 * was running at the time of the reset (i.e. we weren't VT
759 * switched away).
760 */
761 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
db1b76ca 762 !dev_priv->ums.mm_suspended) {
db1b76ca 763 dev_priv->ums.mm_suspended = 0;
75a6898f 764
3d57e5bd 765 ret = i915_gem_init_hw(dev);
8e88a2bd 766 mutex_unlock(&dev->struct_mutex);
3d57e5bd
BW
767 if (ret) {
768 DRM_ERROR("Failed hw init on reset %d\n", ret);
769 return ret;
770 }
f817586c 771
e090c53b
DV
772 /*
773 * FIXME: This is horribly race against concurrent pageflip and
774 * vblank wait ioctls since they can observe dev->irqs_disabled
775 * being false when they shouldn't be able to.
776 */
11ed50ec 777 drm_irq_uninstall(dev);
bb0f1b5c 778 drm_irq_install(dev, dev->pdev->irq);
dd0a1aa1
JM
779
780 /* rps/rc6 re-init is necessary to restore state lost after the
781 * reset and the re-install of drm irq. Skip for ironlake per
782 * previous concerns that it doesn't respond well to some forms
783 * of re-init after reset. */
dc1d0136 784 if (INTEL_INFO(dev)->gen > 5)
c6df39b5 785 intel_reset_gt_powersave(dev);
dd0a1aa1 786
20afbda2 787 intel_hpd_init(dev);
bcbc324a
DV
788 } else {
789 mutex_unlock(&dev->struct_mutex);
11ed50ec
BG
790 }
791
11ed50ec
BG
792 return 0;
793}
794
56550d94 795static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
112b715e 796{
01a06850
DV
797 struct intel_device_info *intel_info =
798 (struct intel_device_info *) ent->driver_data;
799
d330a953 800 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
b833d685
BW
801 DRM_INFO("This hardware requires preliminary hardware support.\n"
802 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
803 return -ENODEV;
804 }
805
5fe49d86
CW
806 /* Only bind to function 0 of the device. Early generations
807 * used function 1 as a placeholder for multi-head. This causes
808 * us confusion instead, especially on the systems where both
809 * functions have the same PCI-ID!
810 */
811 if (PCI_FUNC(pdev->devfn))
812 return -ENODEV;
813
24986ee0 814 driver.driver_features &= ~(DRIVER_USE_AGP);
01a06850 815
dcdb1674 816 return drm_get_pci_dev(pdev, ent, &driver);
112b715e
KH
817}
818
819static void
820i915_pci_remove(struct pci_dev *pdev)
821{
822 struct drm_device *dev = pci_get_drvdata(pdev);
823
824 drm_put_dev(dev);
825}
826
84b79f8d 827static int i915_pm_suspend(struct device *dev)
112b715e 828{
84b79f8d
RW
829 struct pci_dev *pdev = to_pci_dev(dev);
830 struct drm_device *drm_dev = pci_get_drvdata(pdev);
112b715e 831
84b79f8d
RW
832 if (!drm_dev || !drm_dev->dev_private) {
833 dev_err(dev, "DRM not initialized, aborting suspend.\n");
834 return -ENODEV;
835 }
112b715e 836
5bcf719b
DA
837 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
838 return 0;
839
76c4b250
ID
840 return i915_drm_freeze(drm_dev);
841}
842
843static int i915_pm_suspend_late(struct device *dev)
844{
845 struct pci_dev *pdev = to_pci_dev(dev);
846 struct drm_device *drm_dev = pci_get_drvdata(pdev);
847
848 /*
849 * We have a suspedn ordering issue with the snd-hda driver also
850 * requiring our device to be power up. Due to the lack of a
851 * parent/child relationship we currently solve this with an late
852 * suspend hook.
853 *
854 * FIXME: This should be solved with a special hdmi sink device or
855 * similar so that power domains can be employed.
856 */
857 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
858 return 0;
112b715e 859
84b79f8d
RW
860 pci_disable_device(pdev);
861 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 862
84b79f8d 863 return 0;
cbda12d7
ZW
864}
865
76c4b250
ID
866static int i915_pm_resume_early(struct device *dev)
867{
868 struct pci_dev *pdev = to_pci_dev(dev);
869 struct drm_device *drm_dev = pci_get_drvdata(pdev);
870
871 return i915_resume_early(drm_dev);
872}
873
84b79f8d 874static int i915_pm_resume(struct device *dev)
cbda12d7 875{
84b79f8d
RW
876 struct pci_dev *pdev = to_pci_dev(dev);
877 struct drm_device *drm_dev = pci_get_drvdata(pdev);
878
879 return i915_resume(drm_dev);
cbda12d7
ZW
880}
881
84b79f8d 882static int i915_pm_freeze(struct device *dev)
cbda12d7 883{
84b79f8d
RW
884 struct pci_dev *pdev = to_pci_dev(dev);
885 struct drm_device *drm_dev = pci_get_drvdata(pdev);
886
887 if (!drm_dev || !drm_dev->dev_private) {
888 dev_err(dev, "DRM not initialized, aborting suspend.\n");
889 return -ENODEV;
890 }
891
892 return i915_drm_freeze(drm_dev);
cbda12d7
ZW
893}
894
76c4b250
ID
895static int i915_pm_thaw_early(struct device *dev)
896{
897 struct pci_dev *pdev = to_pci_dev(dev);
898 struct drm_device *drm_dev = pci_get_drvdata(pdev);
899
900 return i915_drm_thaw_early(drm_dev);
901}
902
84b79f8d 903static int i915_pm_thaw(struct device *dev)
cbda12d7 904{
84b79f8d
RW
905 struct pci_dev *pdev = to_pci_dev(dev);
906 struct drm_device *drm_dev = pci_get_drvdata(pdev);
907
908 return i915_drm_thaw(drm_dev);
cbda12d7
ZW
909}
910
84b79f8d 911static int i915_pm_poweroff(struct device *dev)
cbda12d7 912{
84b79f8d
RW
913 struct pci_dev *pdev = to_pci_dev(dev);
914 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 915
61caf87c 916 return i915_drm_freeze(drm_dev);
cbda12d7
ZW
917}
918
9a952a0d
PZ
919static void snb_runtime_suspend(struct drm_i915_private *dev_priv)
920{
921 struct drm_device *dev = dev_priv->dev;
922
923 intel_runtime_pm_disable_interrupts(dev);
924}
925
97bea207
PZ
926static void hsw_runtime_suspend(struct drm_i915_private *dev_priv)
927{
414de7a0 928 hsw_enable_pc8(dev_priv);
97bea207
PZ
929}
930
9a952a0d
PZ
931static void snb_runtime_resume(struct drm_i915_private *dev_priv)
932{
933 struct drm_device *dev = dev_priv->dev;
934
935 intel_runtime_pm_restore_interrupts(dev);
936 intel_init_pch_refclk(dev);
937 i915_gem_init_swizzling(dev);
938 mutex_lock(&dev_priv->rps.hw_lock);
939 gen6_update_ring_freq(dev);
940 mutex_unlock(&dev_priv->rps.hw_lock);
941}
942
97bea207
PZ
943static void hsw_runtime_resume(struct drm_i915_private *dev_priv)
944{
414de7a0 945 hsw_disable_pc8(dev_priv);
97bea207
PZ
946}
947
948static int intel_runtime_suspend(struct device *device)
8a187455
PZ
949{
950 struct pci_dev *pdev = to_pci_dev(device);
951 struct drm_device *dev = pci_get_drvdata(pdev);
952 struct drm_i915_private *dev_priv = dev->dev_private;
953
c6df39b5
ID
954 if (WARN_ON_ONCE(!dev_priv->rps.enabled))
955 return -ENODEV;
956
8a187455 957 WARN_ON(!HAS_RUNTIME_PM(dev));
e998c40f 958 assert_force_wake_inactive(dev_priv);
8a187455
PZ
959
960 DRM_DEBUG_KMS("Suspending device\n");
961
9a952a0d
PZ
962 if (IS_GEN6(dev))
963 snb_runtime_suspend(dev_priv);
6157d3c8 964 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
97bea207 965 hsw_runtime_suspend(dev_priv);
6157d3c8
PZ
966 else
967 WARN_ON(1);
a8a8bd54 968
48018a57
PZ
969 i915_gem_release_all_mmaps(dev_priv);
970
16a3d6ef 971 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
8a187455 972 dev_priv->pm.suspended = true;
1fb2362b
KCA
973
974 /*
975 * current versions of firmware which depend on this opregion
976 * notification have repurposed the D1 definition to mean
977 * "runtime suspended" vs. what you would normally expect (D3)
978 * to distinguish it from notifications that might be sent
979 * via the suspend path.
980 */
981 intel_opregion_notify_adapter(dev, PCI_D1);
8a187455 982
a8a8bd54 983 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ
984 return 0;
985}
986
97bea207 987static int intel_runtime_resume(struct device *device)
8a187455
PZ
988{
989 struct pci_dev *pdev = to_pci_dev(device);
990 struct drm_device *dev = pci_get_drvdata(pdev);
991 struct drm_i915_private *dev_priv = dev->dev_private;
992
993 WARN_ON(!HAS_RUNTIME_PM(dev));
994
995 DRM_DEBUG_KMS("Resuming device\n");
996
cd2e9e90 997 intel_opregion_notify_adapter(dev, PCI_D0);
8a187455
PZ
998 dev_priv->pm.suspended = false;
999
9a952a0d
PZ
1000 if (IS_GEN6(dev))
1001 snb_runtime_resume(dev_priv);
6157d3c8 1002 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
97bea207 1003 hsw_runtime_resume(dev_priv);
6157d3c8
PZ
1004 else
1005 WARN_ON(1);
a8a8bd54
PZ
1006
1007 DRM_DEBUG_KMS("Device resumed\n");
8a187455
PZ
1008 return 0;
1009}
1010
b4b78d12 1011static const struct dev_pm_ops i915_pm_ops = {
0206e353 1012 .suspend = i915_pm_suspend,
76c4b250
ID
1013 .suspend_late = i915_pm_suspend_late,
1014 .resume_early = i915_pm_resume_early,
0206e353
AJ
1015 .resume = i915_pm_resume,
1016 .freeze = i915_pm_freeze,
76c4b250 1017 .thaw_early = i915_pm_thaw_early,
0206e353
AJ
1018 .thaw = i915_pm_thaw,
1019 .poweroff = i915_pm_poweroff,
76c4b250 1020 .restore_early = i915_pm_resume_early,
0206e353 1021 .restore = i915_pm_resume,
97bea207
PZ
1022 .runtime_suspend = intel_runtime_suspend,
1023 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW
1024};
1025
78b68556 1026static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 1027 .fault = i915_gem_fault,
ab00b3e5
JB
1028 .open = drm_gem_vm_open,
1029 .close = drm_gem_vm_close,
de151cf6
JB
1030};
1031
e08e96de
AV
1032static const struct file_operations i915_driver_fops = {
1033 .owner = THIS_MODULE,
1034 .open = drm_open,
1035 .release = drm_release,
1036 .unlocked_ioctl = drm_ioctl,
1037 .mmap = drm_gem_mmap,
1038 .poll = drm_poll,
e08e96de
AV
1039 .read = drm_read,
1040#ifdef CONFIG_COMPAT
1041 .compat_ioctl = i915_compat_ioctl,
1042#endif
1043 .llseek = noop_llseek,
1044};
1045
1da177e4 1046static struct drm_driver driver = {
0c54781b
MW
1047 /* Don't use MTRRs here; the Xserver or userspace app should
1048 * deal with them for Intel hardware.
792d2b9a 1049 */
673a394b 1050 .driver_features =
24986ee0 1051 DRIVER_USE_AGP |
10ba5012
KH
1052 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1053 DRIVER_RENDER,
22eae947 1054 .load = i915_driver_load,
ba8bbcf6 1055 .unload = i915_driver_unload,
673a394b 1056 .open = i915_driver_open,
22eae947
DA
1057 .lastclose = i915_driver_lastclose,
1058 .preclose = i915_driver_preclose,
673a394b 1059 .postclose = i915_driver_postclose,
d8e29209
RW
1060
1061 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1062 .suspend = i915_suspend,
76c4b250 1063 .resume = i915_resume_legacy,
d8e29209 1064
cda17380 1065 .device_is_agp = i915_driver_device_is_agp,
7c1c2871
DA
1066 .master_create = i915_master_create,
1067 .master_destroy = i915_master_destroy,
955b12de 1068#if defined(CONFIG_DEBUG_FS)
27c202ad
BG
1069 .debugfs_init = i915_debugfs_init,
1070 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 1071#endif
673a394b 1072 .gem_free_object = i915_gem_free_object,
de151cf6 1073 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV
1074
1075 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1076 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1077 .gem_prime_export = i915_gem_prime_export,
1078 .gem_prime_import = i915_gem_prime_import,
1079
ff72145b
DA
1080 .dumb_create = i915_gem_dumb_create,
1081 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 1082 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 1083 .ioctls = i915_ioctls,
e08e96de 1084 .fops = &i915_driver_fops,
22eae947
DA
1085 .name = DRIVER_NAME,
1086 .desc = DRIVER_DESC,
1087 .date = DRIVER_DATE,
1088 .major = DRIVER_MAJOR,
1089 .minor = DRIVER_MINOR,
1090 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT
1091};
1092
8410ea3b
DA
1093static struct pci_driver i915_pci_driver = {
1094 .name = DRIVER_NAME,
1095 .id_table = pciidlist,
1096 .probe = i915_pci_probe,
1097 .remove = i915_pci_remove,
1098 .driver.pm = &i915_pm_ops,
1099};
1100
1da177e4
LT
1101static int __init i915_init(void)
1102{
1103 driver.num_ioctls = i915_max_ioctl;
79e53945
JB
1104
1105 /*
1106 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1107 * explicitly disabled with the module pararmeter.
1108 *
1109 * Otherwise, just follow the parameter (defaulting to off).
1110 *
1111 * Allow optional vga_text_mode_force boot option to override
1112 * the default behavior.
1113 */
1114#if defined(CONFIG_DRM_I915_KMS)
d330a953 1115 if (i915.modeset != 0)
79e53945
JB
1116 driver.driver_features |= DRIVER_MODESET;
1117#endif
d330a953 1118 if (i915.modeset == 1)
79e53945
JB
1119 driver.driver_features |= DRIVER_MODESET;
1120
1121#ifdef CONFIG_VGA_CONSOLE
d330a953 1122 if (vgacon_text_force() && i915.modeset == -1)
79e53945
JB
1123 driver.driver_features &= ~DRIVER_MODESET;
1124#endif
1125
b30324ad 1126 if (!(driver.driver_features & DRIVER_MODESET)) {
3885c6bb 1127 driver.get_vblank_timestamp = NULL;
b30324ad
DV
1128#ifndef CONFIG_DRM_I915_UMS
1129 /* Silently fail loading to not upset userspace. */
1130 return 0;
1131#endif
1132 }
3885c6bb 1133
8410ea3b 1134 return drm_pci_init(&driver, &i915_pci_driver);
1da177e4
LT
1135}
1136
1137static void __exit i915_exit(void)
1138{
b33ecdd1
DV
1139#ifndef CONFIG_DRM_I915_UMS
1140 if (!(driver.driver_features & DRIVER_MODESET))
1141 return; /* Never loaded a driver. */
1142#endif
1143
8410ea3b 1144 drm_pci_exit(&driver, &i915_pci_driver);
1da177e4
LT
1145}
1146
1147module_init(i915_init);
1148module_exit(i915_exit);
1149
b5e89ed5
DA
1150MODULE_AUTHOR(DRIVER_AUTHOR);
1151MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 1152MODULE_LICENSE("GPL and additional rights");