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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
e5747e3a | 31 | #include <linux/acpi.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/i915_drm.h> | |
1da177e4 | 34 | #include "i915_drv.h" |
990bbdad | 35 | #include "i915_trace.h" |
f49f0586 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
704ab614 | 38 | #include <linux/apple-gmux.h> |
79e53945 | 39 | #include <linux/console.h> |
e0cd3608 | 40 | #include <linux/module.h> |
d6102977 | 41 | #include <linux/pm_runtime.h> |
704ab614 LW |
42 | #include <linux/vgaarb.h> |
43 | #include <linux/vga_switcheroo.h> | |
760285e7 | 44 | #include <drm/drm_crtc_helper.h> |
79e53945 | 45 | |
112b715e KH |
46 | static struct drm_driver driver; |
47 | ||
a57c774a AK |
48 | #define GEN_DEFAULT_PIPEOFFSETS \ |
49 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
50 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
51 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
52 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
a57c774a AK |
53 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
54 | ||
84fd4f4e RB |
55 | #define GEN_CHV_PIPEOFFSETS \ |
56 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
57 | CHV_PIPE_C_OFFSET }, \ | |
58 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
59 | CHV_TRANSCODER_C_OFFSET, }, \ | |
84fd4f4e RB |
60 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
61 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 62 | |
5efb3e28 VS |
63 | #define CURSOR_OFFSETS \ |
64 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
65 | ||
66 | #define IVB_CURSOR_OFFSETS \ | |
67 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
68 | ||
82cf435b LL |
69 | #define BDW_COLORS \ |
70 | .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } | |
29dc3739 LL |
71 | #define CHV_COLORS \ |
72 | .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } | |
82cf435b | 73 | |
9a7e8492 | 74 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 75 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 76 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 77 | .ring_mask = RENDER_RING, |
a57c774a | 78 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 79 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
80 | }; |
81 | ||
9a7e8492 | 82 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 83 | .gen = 2, .num_pipes = 1, |
31578148 | 84 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 85 | .ring_mask = RENDER_RING, |
a57c774a | 86 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 87 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
88 | }; |
89 | ||
9a7e8492 | 90 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 91 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 92 | .cursor_needs_physical = 1, |
31578148 | 93 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 94 | .has_fbc = 1, |
73ae478c | 95 | .ring_mask = RENDER_RING, |
a57c774a | 96 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 97 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
98 | }; |
99 | ||
9a7e8492 | 100 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 101 | .gen = 2, .num_pipes = 1, |
31578148 | 102 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 103 | .ring_mask = RENDER_RING, |
a57c774a | 104 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 105 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
106 | }; |
107 | ||
9a7e8492 | 108 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 109 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 110 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 111 | .ring_mask = RENDER_RING, |
a57c774a | 112 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 113 | CURSOR_OFFSETS, |
cfdf1fa2 | 114 | }; |
9a7e8492 | 115 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 116 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 117 | .cursor_needs_physical = 1, |
31578148 | 118 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 119 | .supports_tv = 1, |
fd70d52a | 120 | .has_fbc = 1, |
73ae478c | 121 | .ring_mask = RENDER_RING, |
a57c774a | 122 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 123 | CURSOR_OFFSETS, |
cfdf1fa2 | 124 | }; |
9a7e8492 | 125 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 126 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 127 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 128 | .ring_mask = RENDER_RING, |
a57c774a | 129 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 130 | CURSOR_OFFSETS, |
cfdf1fa2 | 131 | }; |
9a7e8492 | 132 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 133 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 134 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 135 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 136 | .supports_tv = 1, |
fd70d52a | 137 | .has_fbc = 1, |
73ae478c | 138 | .ring_mask = RENDER_RING, |
a57c774a | 139 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 140 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
141 | }; |
142 | ||
9a7e8492 | 143 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 144 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 145 | .has_hotplug = 1, |
31578148 | 146 | .has_overlay = 1, |
73ae478c | 147 | .ring_mask = RENDER_RING, |
a57c774a | 148 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 149 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
150 | }; |
151 | ||
9a7e8492 | 152 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 153 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 154 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 155 | .has_overlay = 1, |
a6c45cf0 | 156 | .supports_tv = 1, |
73ae478c | 157 | .ring_mask = RENDER_RING, |
a57c774a | 158 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 159 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
160 | }; |
161 | ||
9a7e8492 | 162 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 163 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 164 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 165 | .has_overlay = 1, |
73ae478c | 166 | .ring_mask = RENDER_RING, |
a57c774a | 167 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 168 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
169 | }; |
170 | ||
9a7e8492 | 171 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 172 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 173 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 174 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 175 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 176 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
177 | }; |
178 | ||
9a7e8492 | 179 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 180 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 181 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 182 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 183 | .supports_tv = 1, |
73ae478c | 184 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 185 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 186 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
187 | }; |
188 | ||
9a7e8492 | 189 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 190 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 191 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 192 | .has_overlay = 1, |
a57c774a | 193 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 194 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
195 | }; |
196 | ||
9a7e8492 | 197 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 198 | .gen = 5, .num_pipes = 2, |
5a117db7 | 199 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 200 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 201 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 202 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
203 | }; |
204 | ||
9a7e8492 | 205 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 206 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 207 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 208 | .has_fbc = 1, |
73ae478c | 209 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 210 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 211 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
212 | }; |
213 | ||
9a7e8492 | 214 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 215 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 216 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 217 | .has_fbc = 1, |
73ae478c | 218 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 219 | .has_llc = 1, |
a57c774a | 220 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 221 | CURSOR_OFFSETS, |
f6e450a6 EA |
222 | }; |
223 | ||
9a7e8492 | 224 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 225 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 226 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 227 | .has_fbc = 1, |
73ae478c | 228 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 229 | .has_llc = 1, |
a57c774a | 230 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 231 | CURSOR_OFFSETS, |
a13e4093 EA |
232 | }; |
233 | ||
219f4fdb BW |
234 | #define GEN7_FEATURES \ |
235 | .gen = 7, .num_pipes = 3, \ | |
236 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 237 | .has_fbc = 1, \ |
73ae478c | 238 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
6a8beeff WB |
239 | .has_llc = 1, \ |
240 | GEN_DEFAULT_PIPEOFFSETS, \ | |
241 | IVB_CURSOR_OFFSETS | |
219f4fdb | 242 | |
c76b615c | 243 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
244 | GEN7_FEATURES, |
245 | .is_ivybridge = 1, | |
c76b615c JB |
246 | }; |
247 | ||
248 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
249 | GEN7_FEATURES, |
250 | .is_ivybridge = 1, | |
251 | .is_mobile = 1, | |
c76b615c JB |
252 | }; |
253 | ||
999bcdea BW |
254 | static const struct intel_device_info intel_ivybridge_q_info = { |
255 | GEN7_FEATURES, | |
256 | .is_ivybridge = 1, | |
257 | .num_pipes = 0, /* legal, last one wins */ | |
258 | }; | |
259 | ||
6a8beeff WB |
260 | #define VLV_FEATURES \ |
261 | .gen = 7, .num_pipes = 2, \ | |
262 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
263 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
264 | .display_mmio_offset = VLV_DISPLAY_BASE, \ | |
265 | GEN_DEFAULT_PIPEOFFSETS, \ | |
266 | CURSOR_OFFSETS | |
267 | ||
70a3eb7a | 268 | static const struct intel_device_info intel_valleyview_m_info = { |
6a8beeff | 269 | VLV_FEATURES, |
70a3eb7a | 270 | .is_valleyview = 1, |
6a8beeff | 271 | .is_mobile = 1, |
70a3eb7a JB |
272 | }; |
273 | ||
274 | static const struct intel_device_info intel_valleyview_d_info = { | |
6a8beeff | 275 | VLV_FEATURES, |
70a3eb7a JB |
276 | .is_valleyview = 1, |
277 | }; | |
278 | ||
6a8beeff WB |
279 | #define HSW_FEATURES \ |
280 | GEN7_FEATURES, \ | |
281 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
282 | .has_ddi = 1, \ | |
283 | .has_fpga_dbg = 1 | |
284 | ||
4cae9ae0 | 285 | static const struct intel_device_info intel_haswell_d_info = { |
6a8beeff | 286 | HSW_FEATURES, |
219f4fdb | 287 | .is_haswell = 1, |
4cae9ae0 ED |
288 | }; |
289 | ||
290 | static const struct intel_device_info intel_haswell_m_info = { | |
6a8beeff | 291 | HSW_FEATURES, |
219f4fdb BW |
292 | .is_haswell = 1, |
293 | .is_mobile = 1, | |
c76b615c JB |
294 | }; |
295 | ||
82cf435b LL |
296 | #define BDW_FEATURES \ |
297 | HSW_FEATURES, \ | |
298 | BDW_COLORS | |
299 | ||
4d4dead6 | 300 | static const struct intel_device_info intel_broadwell_d_info = { |
82cf435b | 301 | BDW_FEATURES, |
6a8beeff | 302 | .gen = 8, |
4d4dead6 BW |
303 | }; |
304 | ||
305 | static const struct intel_device_info intel_broadwell_m_info = { | |
82cf435b | 306 | BDW_FEATURES, |
6a8beeff | 307 | .gen = 8, .is_mobile = 1, |
4d4dead6 BW |
308 | }; |
309 | ||
fd3c269f | 310 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
82cf435b | 311 | BDW_FEATURES, |
6a8beeff | 312 | .gen = 8, |
845f74a7 | 313 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
314 | }; |
315 | ||
316 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
82cf435b | 317 | BDW_FEATURES, |
6a8beeff | 318 | .gen = 8, .is_mobile = 1, |
845f74a7 | 319 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
320 | }; |
321 | ||
7d87a7f7 | 322 | static const struct intel_device_info intel_cherryview_info = { |
07fddb14 | 323 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
324 | .need_gfx_hws = 1, .has_hotplug = 1, |
325 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
666a4537 | 326 | .is_cherryview = 1, |
7d87a7f7 | 327 | .display_mmio_offset = VLV_DISPLAY_BASE, |
84fd4f4e | 328 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 329 | CURSOR_OFFSETS, |
29dc3739 | 330 | CHV_COLORS, |
7d87a7f7 VS |
331 | }; |
332 | ||
72bbf0af | 333 | static const struct intel_device_info intel_skylake_info = { |
82cf435b | 334 | BDW_FEATURES, |
7201c0b3 | 335 | .is_skylake = 1, |
6a8beeff | 336 | .gen = 9, |
72bbf0af DL |
337 | }; |
338 | ||
719388e1 | 339 | static const struct intel_device_info intel_skylake_gt3_info = { |
82cf435b | 340 | BDW_FEATURES, |
719388e1 | 341 | .is_skylake = 1, |
6a8beeff | 342 | .gen = 9, |
719388e1 | 343 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
719388e1 DL |
344 | }; |
345 | ||
1347f5b4 DL |
346 | static const struct intel_device_info intel_broxton_info = { |
347 | .is_preliminary = 1, | |
7526ac19 | 348 | .is_broxton = 1, |
1347f5b4 DL |
349 | .gen = 9, |
350 | .need_gfx_hws = 1, .has_hotplug = 1, | |
351 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
352 | .num_pipes = 3, | |
353 | .has_ddi = 1, | |
6c908bf4 | 354 | .has_fpga_dbg = 1, |
ce89db2e | 355 | .has_fbc = 1, |
1347f5b4 DL |
356 | GEN_DEFAULT_PIPEOFFSETS, |
357 | IVB_CURSOR_OFFSETS, | |
82cf435b | 358 | BDW_COLORS, |
1347f5b4 DL |
359 | }; |
360 | ||
ef11bdb3 | 361 | static const struct intel_device_info intel_kabylake_info = { |
82cf435b | 362 | BDW_FEATURES, |
ef11bdb3 RV |
363 | .is_kabylake = 1, |
364 | .gen = 9, | |
ef11bdb3 RV |
365 | }; |
366 | ||
367 | static const struct intel_device_info intel_kabylake_gt3_info = { | |
82cf435b | 368 | BDW_FEATURES, |
ef11bdb3 RV |
369 | .is_kabylake = 1, |
370 | .gen = 9, | |
ef11bdb3 | 371 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
ef11bdb3 RV |
372 | }; |
373 | ||
a0a18075 JB |
374 | /* |
375 | * Make sure any device matches here are from most specific to most | |
376 | * general. For example, since the Quanta match is based on the subsystem | |
377 | * and subvendor IDs, we need it to come before the more general IVB | |
378 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
379 | */ | |
3cb27f38 JN |
380 | static const struct pci_device_id pciidlist[] = { |
381 | INTEL_I830_IDS(&intel_i830_info), | |
382 | INTEL_I845G_IDS(&intel_845g_info), | |
383 | INTEL_I85X_IDS(&intel_i85x_info), | |
384 | INTEL_I865G_IDS(&intel_i865g_info), | |
385 | INTEL_I915G_IDS(&intel_i915g_info), | |
386 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
387 | INTEL_I945G_IDS(&intel_i945g_info), | |
388 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
389 | INTEL_I965G_IDS(&intel_i965g_info), | |
390 | INTEL_G33_IDS(&intel_g33_info), | |
391 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
392 | INTEL_GM45_IDS(&intel_gm45_info), | |
393 | INTEL_G45_IDS(&intel_g45_info), | |
394 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
395 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
396 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
397 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), | |
398 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), | |
399 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ | |
400 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), | |
401 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), | |
402 | INTEL_HSW_D_IDS(&intel_haswell_d_info), | |
403 | INTEL_HSW_M_IDS(&intel_haswell_m_info), | |
404 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), | |
405 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), | |
406 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), | |
407 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), | |
408 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), | |
409 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), | |
410 | INTEL_CHV_IDS(&intel_cherryview_info), | |
411 | INTEL_SKL_GT1_IDS(&intel_skylake_info), | |
412 | INTEL_SKL_GT2_IDS(&intel_skylake_info), | |
413 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), | |
15620206 | 414 | INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), |
3cb27f38 | 415 | INTEL_BXT_IDS(&intel_broxton_info), |
d97044b6 D |
416 | INTEL_KBL_GT1_IDS(&intel_kabylake_info), |
417 | INTEL_KBL_GT2_IDS(&intel_kabylake_info), | |
418 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), | |
8b10c0cf | 419 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), |
49ae35f2 | 420 | {0, 0, 0} |
1da177e4 LT |
421 | }; |
422 | ||
79e53945 | 423 | MODULE_DEVICE_TABLE(pci, pciidlist); |
79e53945 | 424 | |
30c964a6 RB |
425 | static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) |
426 | { | |
427 | enum intel_pch ret = PCH_NOP; | |
428 | ||
429 | /* | |
430 | * In a virtualized passthrough environment we can be in a | |
431 | * setup where the ISA bridge is not able to be passed through. | |
432 | * In this case, a south bridge can be emulated and we have to | |
433 | * make an educated guess as to which PCH is really there. | |
434 | */ | |
435 | ||
436 | if (IS_GEN5(dev)) { | |
437 | ret = PCH_IBX; | |
438 | DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); | |
439 | } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { | |
440 | ret = PCH_CPT; | |
441 | DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); | |
442 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
443 | ret = PCH_LPT; | |
444 | DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); | |
ef11bdb3 | 445 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
30c964a6 RB |
446 | ret = PCH_SPT; |
447 | DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); | |
448 | } | |
449 | ||
450 | return ret; | |
451 | } | |
452 | ||
0206e353 | 453 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
454 | { |
455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 456 | struct pci_dev *pch = NULL; |
3bad0781 | 457 | |
ce1bb329 BW |
458 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
459 | * (which really amounts to a PCH but no South Display). | |
460 | */ | |
461 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
462 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
463 | return; |
464 | } | |
465 | ||
3bad0781 ZW |
466 | /* |
467 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
468 | * make graphics device passthrough work easy for VMM, that only | |
469 | * need to expose ISA bridge to let driver know the real hardware | |
470 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
471 | * |
472 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
473 | * ISA bridge in the system. To work reliably, we should scan trhough | |
474 | * all the ISA bridge devices and check for the first match, instead | |
475 | * of only checking the first one. | |
3bad0781 | 476 | */ |
bcdb72ac | 477 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 478 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 479 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 480 | dev_priv->pch_id = id; |
3bad0781 | 481 | |
90711d50 JB |
482 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
483 | dev_priv->pch_type = PCH_IBX; | |
484 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 485 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 486 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
487 | dev_priv->pch_type = PCH_CPT; |
488 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 489 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
490 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
491 | /* PantherPoint is CPT compatible */ | |
492 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 493 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 494 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
495 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
496 | dev_priv->pch_type = PCH_LPT; | |
497 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
a35cc9d0 RV |
498 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
499 | WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); | |
e76e0634 BW |
500 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
501 | dev_priv->pch_type = PCH_LPT; | |
502 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
a35cc9d0 RV |
503 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
504 | WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); | |
e7e7ea20 S |
505 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
506 | dev_priv->pch_type = PCH_SPT; | |
507 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
ef11bdb3 RV |
508 | WARN_ON(!IS_SKYLAKE(dev) && |
509 | !IS_KABYLAKE(dev)); | |
e7e7ea20 S |
510 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
511 | dev_priv->pch_type = PCH_SPT; | |
512 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
ef11bdb3 RV |
513 | WARN_ON(!IS_SKYLAKE(dev) && |
514 | !IS_KABYLAKE(dev)); | |
bc7135b9 RV |
515 | } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) { |
516 | dev_priv->pch_type = PCH_KBP; | |
517 | DRM_DEBUG_KMS("Found KabyPoint PCH\n"); | |
518 | WARN_ON(!IS_KABYLAKE(dev)); | |
39bfcd52 | 519 | } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) || |
1844a66b | 520 | (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) || |
f2e30510 GH |
521 | ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) && |
522 | pch->subsystem_vendor == 0x1af4 && | |
523 | pch->subsystem_device == 0x1100)) { | |
30c964a6 | 524 | dev_priv->pch_type = intel_virt_detect_pch(dev); |
bcdb72ac ID |
525 | } else |
526 | continue; | |
527 | ||
6a9c4b35 | 528 | break; |
3bad0781 | 529 | } |
3bad0781 | 530 | } |
6a9c4b35 | 531 | if (!pch) |
bcdb72ac ID |
532 | DRM_DEBUG_KMS("No PCH found.\n"); |
533 | ||
534 | pci_dev_put(pch); | |
3bad0781 ZW |
535 | } |
536 | ||
2911a35b BW |
537 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
538 | { | |
539 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 540 | return false; |
2911a35b | 541 | |
d330a953 JN |
542 | if (i915.semaphores >= 0) |
543 | return i915.semaphores; | |
2911a35b | 544 | |
71386ef9 OM |
545 | /* TODO: make semaphores and Execlists play nicely together */ |
546 | if (i915.enable_execlists) | |
547 | return false; | |
548 | ||
be71eabe RV |
549 | /* Until we get further testing... */ |
550 | if (IS_GEN8(dev)) | |
551 | return false; | |
552 | ||
59de3295 | 553 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 554 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
555 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
556 | return false; | |
557 | #endif | |
2911a35b | 558 | |
a08acaf2 | 559 | return true; |
2911a35b BW |
560 | } |
561 | ||
07f9cd0b ID |
562 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
563 | { | |
564 | struct drm_device *dev = dev_priv->dev; | |
19c8054c | 565 | struct intel_encoder *encoder; |
07f9cd0b ID |
566 | |
567 | drm_modeset_lock_all(dev); | |
19c8054c JN |
568 | for_each_intel_encoder(dev, encoder) |
569 | if (encoder->suspend) | |
570 | encoder->suspend(encoder); | |
07f9cd0b ID |
571 | drm_modeset_unlock_all(dev); |
572 | } | |
573 | ||
1a5df187 PZ |
574 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
575 | bool rpm_resume); | |
507e126e | 576 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv); |
f75a1985 | 577 | |
bc87229f ID |
578 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
579 | { | |
580 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
581 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
582 | return true; | |
583 | #endif | |
584 | return false; | |
585 | } | |
ebc32824 | 586 | |
5e365c39 | 587 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 588 | { |
61caf87c | 589 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5747e3a | 590 | pci_power_t opregion_target_state; |
d5818938 | 591 | int error; |
61caf87c | 592 | |
b8efb17b ZR |
593 | /* ignore lid events during suspend */ |
594 | mutex_lock(&dev_priv->modeset_restore_lock); | |
595 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
596 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
597 | ||
1f814dac ID |
598 | disable_rpm_wakeref_asserts(dev_priv); |
599 | ||
c67a470b PZ |
600 | /* We do a lot of poking in a lot of registers, make sure they work |
601 | * properly. */ | |
da7e29bd | 602 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 603 | |
5bcf719b DA |
604 | drm_kms_helper_poll_disable(dev); |
605 | ||
ba8bbcf6 | 606 | pci_save_state(dev->pdev); |
ba8bbcf6 | 607 | |
d5818938 DV |
608 | error = i915_gem_suspend(dev); |
609 | if (error) { | |
610 | dev_err(&dev->pdev->dev, | |
611 | "GEM idle failed, resume might fail\n"); | |
1f814dac | 612 | goto out; |
d5818938 | 613 | } |
db1b76ca | 614 | |
a1c41994 AD |
615 | intel_guc_suspend(dev); |
616 | ||
d5818938 | 617 | intel_suspend_gt_powersave(dev); |
a261b246 | 618 | |
6b72d486 | 619 | intel_display_suspend(dev); |
2eb5252e | 620 | |
d5818938 | 621 | intel_dp_mst_suspend(dev); |
7d708ee4 | 622 | |
d5818938 DV |
623 | intel_runtime_pm_disable_interrupts(dev_priv); |
624 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 625 | |
d5818938 | 626 | intel_suspend_encoders(dev_priv); |
0e32b39c | 627 | |
d5818938 | 628 | intel_suspend_hw(dev); |
5669fcac | 629 | |
828c7908 BW |
630 | i915_gem_suspend_gtt_mappings(dev); |
631 | ||
9e06dd39 JB |
632 | i915_save_state(dev); |
633 | ||
bc87229f | 634 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
e5747e3a JB |
635 | intel_opregion_notify_adapter(dev, opregion_target_state); |
636 | ||
156c7ca0 | 637 | intel_uncore_forcewake_reset(dev, false); |
44834a67 | 638 | intel_opregion_fini(dev); |
8ee1c3db | 639 | |
82e3b8c1 | 640 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 641 | |
62d5d69b MK |
642 | dev_priv->suspend_count++; |
643 | ||
85e90679 KCA |
644 | intel_display_set_init_power(dev_priv, false); |
645 | ||
f74ed08d | 646 | intel_csr_ucode_suspend(dev_priv); |
f514c2d8 | 647 | |
1f814dac ID |
648 | out: |
649 | enable_rpm_wakeref_asserts(dev_priv); | |
650 | ||
651 | return error; | |
84b79f8d RW |
652 | } |
653 | ||
ab3be73f | 654 | static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) |
c3c09c95 ID |
655 | { |
656 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
bc87229f | 657 | bool fw_csr; |
c3c09c95 ID |
658 | int ret; |
659 | ||
1f814dac ID |
660 | disable_rpm_wakeref_asserts(dev_priv); |
661 | ||
a7c8125f ID |
662 | fw_csr = !IS_BROXTON(dev_priv) && |
663 | suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; | |
bc87229f ID |
664 | /* |
665 | * In case of firmware assisted context save/restore don't manually | |
666 | * deinit the power domains. This also means the CSR/DMC firmware will | |
667 | * stay active, it will power down any HW resources as required and | |
668 | * also enable deeper system power states that would be blocked if the | |
669 | * firmware was inactive. | |
670 | */ | |
671 | if (!fw_csr) | |
672 | intel_power_domains_suspend(dev_priv); | |
73dfc227 | 673 | |
507e126e | 674 | ret = 0; |
b8aea3d1 | 675 | if (IS_BROXTON(dev_priv)) |
507e126e | 676 | bxt_enable_dc9(dev_priv); |
b8aea3d1 | 677 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
507e126e ID |
678 | hsw_enable_pc8(dev_priv); |
679 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
680 | ret = vlv_suspend_complete(dev_priv); | |
c3c09c95 ID |
681 | |
682 | if (ret) { | |
683 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
bc87229f ID |
684 | if (!fw_csr) |
685 | intel_power_domains_init_hw(dev_priv, true); | |
c3c09c95 | 686 | |
1f814dac | 687 | goto out; |
c3c09c95 ID |
688 | } |
689 | ||
690 | pci_disable_device(drm_dev->pdev); | |
ab3be73f | 691 | /* |
54875571 | 692 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
693 | * the device even though it's already in D3 and hang the machine. So |
694 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
695 | * power down the device properly. The issue was seen on multiple old |
696 | * GENs with different BIOS vendors, so having an explicit blacklist | |
697 | * is inpractical; apply the workaround on everything pre GEN6. The | |
698 | * platforms where the issue was seen: | |
699 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
700 | * Fujitsu FSC S7110 | |
701 | * Acer Aspire 1830T | |
ab3be73f | 702 | */ |
54875571 | 703 | if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) |
ab3be73f | 704 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); |
c3c09c95 | 705 | |
bc87229f ID |
706 | dev_priv->suspended_to_idle = suspend_to_idle(dev_priv); |
707 | ||
1f814dac ID |
708 | out: |
709 | enable_rpm_wakeref_asserts(dev_priv); | |
710 | ||
711 | return ret; | |
c3c09c95 ID |
712 | } |
713 | ||
1751fcf9 | 714 | int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
715 | { |
716 | int error; | |
717 | ||
718 | if (!dev || !dev->dev_private) { | |
719 | DRM_ERROR("dev: %p\n", dev); | |
720 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
721 | return -ENODEV; | |
722 | } | |
723 | ||
0b14cbd2 ID |
724 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
725 | state.event != PM_EVENT_FREEZE)) | |
726 | return -EINVAL; | |
5bcf719b DA |
727 | |
728 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
729 | return 0; | |
6eecba33 | 730 | |
5e365c39 | 731 | error = i915_drm_suspend(dev); |
84b79f8d RW |
732 | if (error) |
733 | return error; | |
734 | ||
ab3be73f | 735 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
736 | } |
737 | ||
5e365c39 | 738 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 ID |
739 | { |
740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5fbd0418 | 741 | int ret; |
9d49c0ef | 742 | |
1f814dac ID |
743 | disable_rpm_wakeref_asserts(dev_priv); |
744 | ||
5fbd0418 VS |
745 | ret = i915_ggtt_enable_hw(dev); |
746 | if (ret) | |
747 | DRM_ERROR("failed to re-enable GGTT\n"); | |
748 | ||
f74ed08d ID |
749 | intel_csr_ucode_resume(dev_priv); |
750 | ||
d5818938 DV |
751 | mutex_lock(&dev->struct_mutex); |
752 | i915_gem_restore_gtt_mappings(dev); | |
753 | mutex_unlock(&dev->struct_mutex); | |
9d49c0ef | 754 | |
61caf87c | 755 | i915_restore_state(dev); |
44834a67 | 756 | intel_opregion_setup(dev); |
61caf87c | 757 | |
d5818938 DV |
758 | intel_init_pch_refclk(dev); |
759 | drm_mode_config_reset(dev); | |
1833b134 | 760 | |
364aece0 PA |
761 | /* |
762 | * Interrupts have to be enabled before any batches are run. If not the | |
763 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
764 | * update/restore the context. | |
765 | * | |
766 | * Modeset enabling in intel_modeset_init_hw() also needs working | |
767 | * interrupts. | |
768 | */ | |
769 | intel_runtime_pm_enable_interrupts(dev_priv); | |
770 | ||
d5818938 DV |
771 | mutex_lock(&dev->struct_mutex); |
772 | if (i915_gem_init_hw(dev)) { | |
773 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
805de8f4 | 774 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
d5818938 DV |
775 | } |
776 | mutex_unlock(&dev->struct_mutex); | |
226485e9 | 777 | |
a1c41994 AD |
778 | intel_guc_resume(dev); |
779 | ||
d5818938 | 780 | intel_modeset_init_hw(dev); |
24576d23 | 781 | |
d5818938 DV |
782 | spin_lock_irq(&dev_priv->irq_lock); |
783 | if (dev_priv->display.hpd_irq_setup) | |
784 | dev_priv->display.hpd_irq_setup(dev); | |
785 | spin_unlock_irq(&dev_priv->irq_lock); | |
0e32b39c | 786 | |
d5818938 | 787 | intel_dp_mst_resume(dev); |
e7d6f7d7 | 788 | |
a16b7658 L |
789 | intel_display_resume(dev); |
790 | ||
d5818938 DV |
791 | /* |
792 | * ... but also need to make sure that hotplug processing | |
793 | * doesn't cause havoc. Like in the driver load code we don't | |
794 | * bother with the tiny race here where we might loose hotplug | |
795 | * notifications. | |
796 | * */ | |
797 | intel_hpd_init(dev_priv); | |
798 | /* Config may have changed between suspend and resume */ | |
799 | drm_helper_hpd_irq_event(dev); | |
1daed3fb | 800 | |
44834a67 CW |
801 | intel_opregion_init(dev); |
802 | ||
82e3b8c1 | 803 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 804 | |
b8efb17b ZR |
805 | mutex_lock(&dev_priv->modeset_restore_lock); |
806 | dev_priv->modeset_restore = MODESET_DONE; | |
807 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 808 | |
e5747e3a JB |
809 | intel_opregion_notify_adapter(dev, PCI_D0); |
810 | ||
ee6f280e ID |
811 | drm_kms_helper_poll_enable(dev); |
812 | ||
1f814dac ID |
813 | enable_rpm_wakeref_asserts(dev_priv); |
814 | ||
074c6ada | 815 | return 0; |
84b79f8d RW |
816 | } |
817 | ||
5e365c39 | 818 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 819 | { |
36d61e67 | 820 | struct drm_i915_private *dev_priv = dev->dev_private; |
44410cd0 | 821 | int ret; |
36d61e67 | 822 | |
76c4b250 ID |
823 | /* |
824 | * We have a resume ordering issue with the snd-hda driver also | |
825 | * requiring our device to be power up. Due to the lack of a | |
826 | * parent/child relationship we currently solve this with an early | |
827 | * resume hook. | |
828 | * | |
829 | * FIXME: This should be solved with a special hdmi sink device or | |
830 | * similar so that power domains can be employed. | |
831 | */ | |
44410cd0 ID |
832 | |
833 | /* | |
834 | * Note that we need to set the power state explicitly, since we | |
835 | * powered off the device during freeze and the PCI core won't power | |
836 | * it back up for us during thaw. Powering off the device during | |
837 | * freeze is not a hard requirement though, and during the | |
838 | * suspend/resume phases the PCI core makes sure we get here with the | |
839 | * device powered on. So in case we change our freeze logic and keep | |
840 | * the device powered we can also remove the following set power state | |
841 | * call. | |
842 | */ | |
843 | ret = pci_set_power_state(dev->pdev, PCI_D0); | |
844 | if (ret) { | |
845 | DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret); | |
846 | goto out; | |
847 | } | |
848 | ||
849 | /* | |
850 | * Note that pci_enable_device() first enables any parent bridge | |
851 | * device and only then sets the power state for this device. The | |
852 | * bridge enabling is a nop though, since bridge devices are resumed | |
853 | * first. The order of enabling power and enabling the device is | |
854 | * imposed by the PCI core as described above, so here we preserve the | |
855 | * same order for the freeze/thaw phases. | |
856 | * | |
857 | * TODO: eventually we should remove pci_disable_device() / | |
858 | * pci_enable_enable_device() from suspend/resume. Due to how they | |
859 | * depend on the device enable refcount we can't anyway depend on them | |
860 | * disabling/enabling the device. | |
861 | */ | |
bc87229f ID |
862 | if (pci_enable_device(dev->pdev)) { |
863 | ret = -EIO; | |
864 | goto out; | |
865 | } | |
84b79f8d RW |
866 | |
867 | pci_set_master(dev->pdev); | |
868 | ||
1f814dac ID |
869 | disable_rpm_wakeref_asserts(dev_priv); |
870 | ||
666a4537 | 871 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 | 872 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 873 | if (ret) |
ff0b187f DL |
874 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
875 | ret); | |
36d61e67 ID |
876 | |
877 | intel_uncore_early_sanitize(dev, true); | |
efee833a | 878 | |
da2f41d1 ID |
879 | if (IS_BROXTON(dev)) { |
880 | if (!dev_priv->suspended_to_idle) | |
881 | gen9_sanitize_dc_state(dev_priv); | |
507e126e | 882 | bxt_disable_dc9(dev_priv); |
da2f41d1 | 883 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
a9a6b73a | 884 | hsw_disable_pc8(dev_priv); |
da2f41d1 | 885 | } |
efee833a | 886 | |
36d61e67 | 887 | intel_uncore_sanitize(dev); |
bc87229f | 888 | |
a7c8125f ID |
889 | if (IS_BROXTON(dev_priv) || |
890 | !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) | |
bc87229f ID |
891 | intel_power_domains_init_hw(dev_priv, true); |
892 | ||
6e35e8ab ID |
893 | enable_rpm_wakeref_asserts(dev_priv); |
894 | ||
bc87229f ID |
895 | out: |
896 | dev_priv->suspended_to_idle = false; | |
36d61e67 ID |
897 | |
898 | return ret; | |
76c4b250 ID |
899 | } |
900 | ||
1751fcf9 | 901 | int i915_resume_switcheroo(struct drm_device *dev) |
76c4b250 | 902 | { |
50a0072f | 903 | int ret; |
76c4b250 | 904 | |
097dd837 ID |
905 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
906 | return 0; | |
907 | ||
5e365c39 | 908 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
909 | if (ret) |
910 | return ret; | |
911 | ||
5a17514e ID |
912 | return i915_drm_resume(dev); |
913 | } | |
914 | ||
11ed50ec | 915 | /** |
f3953dcb | 916 | * i915_reset - reset chip after a hang |
11ed50ec | 917 | * @dev: drm device to reset |
11ed50ec BG |
918 | * |
919 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
920 | * reset or otherwise an error code. | |
921 | * | |
922 | * Procedure is fairly simple: | |
923 | * - reset the chip using the reset reg | |
924 | * - re-init context state | |
925 | * - re-init hardware status page | |
926 | * - re-init ring buffer | |
927 | * - re-init interrupt state | |
928 | * - re-init display | |
929 | */ | |
d4b8bb2a | 930 | int i915_reset(struct drm_device *dev) |
11ed50ec | 931 | { |
50227e1c | 932 | struct drm_i915_private *dev_priv = dev->dev_private; |
d98c52cf CW |
933 | struct i915_gpu_error *error = &dev_priv->gpu_error; |
934 | unsigned reset_counter; | |
0573ed4a | 935 | int ret; |
11ed50ec | 936 | |
dbea3cea ID |
937 | intel_reset_gt_powersave(dev); |
938 | ||
d54a02c0 | 939 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 940 | |
d98c52cf CW |
941 | /* Clear any previous failed attempts at recovery. Time to try again. */ |
942 | atomic_andnot(I915_WEDGED, &error->reset_counter); | |
77f01230 | 943 | |
d98c52cf CW |
944 | /* Clear the reset-in-progress flag and increment the reset epoch. */ |
945 | reset_counter = atomic_inc_return(&error->reset_counter); | |
946 | if (WARN_ON(__i915_reset_in_progress(reset_counter))) { | |
947 | ret = -EIO; | |
948 | goto error; | |
949 | } | |
950 | ||
951 | i915_gem_reset(dev); | |
2e7c8ee7 | 952 | |
ee4b6faf | 953 | ret = intel_gpu_reset(dev, ALL_ENGINES); |
be62acb4 MK |
954 | |
955 | /* Also reset the gpu hangman. */ | |
d98c52cf | 956 | if (error->stop_rings != 0) { |
be62acb4 | 957 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); |
d98c52cf | 958 | error->stop_rings = 0; |
be62acb4 | 959 | if (ret == -ENODEV) { |
f2d91a2c DV |
960 | DRM_INFO("Reset not implemented, but ignoring " |
961 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
962 | ret = 0; |
963 | } | |
2e7c8ee7 | 964 | } |
be62acb4 | 965 | |
d8f2716a DV |
966 | if (i915_stop_ring_allow_warn(dev_priv)) |
967 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); | |
968 | ||
0573ed4a | 969 | if (ret) { |
804e59a8 CW |
970 | if (ret != -ENODEV) |
971 | DRM_ERROR("Failed to reset chip: %i\n", ret); | |
972 | else | |
973 | DRM_DEBUG_DRIVER("GPU reset disabled\n"); | |
d98c52cf | 974 | goto error; |
11ed50ec BG |
975 | } |
976 | ||
1362b776 VS |
977 | intel_overlay_reset(dev_priv); |
978 | ||
11ed50ec BG |
979 | /* Ok, now get things going again... */ |
980 | ||
981 | /* | |
982 | * Everything depends on having the GTT running, so we need to start | |
983 | * there. Fortunately we don't need to do this unless we reset the | |
984 | * chip at a PCI level. | |
985 | * | |
986 | * Next we need to restore the context, but we don't use those | |
987 | * yet either... | |
988 | * | |
989 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
990 | * was running at the time of the reset (i.e. we weren't VT | |
991 | * switched away). | |
992 | */ | |
33d30a9c | 993 | ret = i915_gem_init_hw(dev); |
33d30a9c DV |
994 | if (ret) { |
995 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
d98c52cf | 996 | goto error; |
11ed50ec BG |
997 | } |
998 | ||
d98c52cf CW |
999 | mutex_unlock(&dev->struct_mutex); |
1000 | ||
33d30a9c DV |
1001 | /* |
1002 | * rps/rc6 re-init is necessary to restore state lost after the | |
1003 | * reset and the re-install of gt irqs. Skip for ironlake per | |
1004 | * previous concerns that it doesn't respond well to some forms | |
1005 | * of re-init after reset. | |
1006 | */ | |
1007 | if (INTEL_INFO(dev)->gen > 5) | |
1008 | intel_enable_gt_powersave(dev); | |
1009 | ||
11ed50ec | 1010 | return 0; |
d98c52cf CW |
1011 | |
1012 | error: | |
1013 | atomic_or(I915_WEDGED, &error->reset_counter); | |
1014 | mutex_unlock(&dev->struct_mutex); | |
1015 | return ret; | |
11ed50ec BG |
1016 | } |
1017 | ||
56550d94 | 1018 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 1019 | { |
01a06850 DV |
1020 | struct intel_device_info *intel_info = |
1021 | (struct intel_device_info *) ent->driver_data; | |
1022 | ||
d330a953 | 1023 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
1024 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
1025 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
1026 | return -ENODEV; | |
1027 | } | |
1028 | ||
5fe49d86 CW |
1029 | /* Only bind to function 0 of the device. Early generations |
1030 | * used function 1 as a placeholder for multi-head. This causes | |
1031 | * us confusion instead, especially on the systems where both | |
1032 | * functions have the same PCI-ID! | |
1033 | */ | |
1034 | if (PCI_FUNC(pdev->devfn)) | |
1035 | return -ENODEV; | |
1036 | ||
704ab614 LW |
1037 | /* |
1038 | * apple-gmux is needed on dual GPU MacBook Pro | |
1039 | * to probe the panel if we're the inactive GPU. | |
1040 | */ | |
1041 | if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) && | |
1042 | apple_gmux_present() && pdev != vga_default_device() && | |
1043 | !vga_switcheroo_handler_flags()) | |
1044 | return -EPROBE_DEFER; | |
1045 | ||
dcdb1674 | 1046 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
1047 | } |
1048 | ||
1049 | static void | |
1050 | i915_pci_remove(struct pci_dev *pdev) | |
1051 | { | |
1052 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1053 | ||
1054 | drm_put_dev(dev); | |
1055 | } | |
1056 | ||
84b79f8d | 1057 | static int i915_pm_suspend(struct device *dev) |
112b715e | 1058 | { |
84b79f8d RW |
1059 | struct pci_dev *pdev = to_pci_dev(dev); |
1060 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 1061 | |
84b79f8d RW |
1062 | if (!drm_dev || !drm_dev->dev_private) { |
1063 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
1064 | return -ENODEV; | |
1065 | } | |
112b715e | 1066 | |
5bcf719b DA |
1067 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1068 | return 0; | |
1069 | ||
5e365c39 | 1070 | return i915_drm_suspend(drm_dev); |
76c4b250 ID |
1071 | } |
1072 | ||
1073 | static int i915_pm_suspend_late(struct device *dev) | |
1074 | { | |
888d0d42 | 1075 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 ID |
1076 | |
1077 | /* | |
c965d995 | 1078 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
1079 | * requiring our device to be power up. Due to the lack of a |
1080 | * parent/child relationship we currently solve this with an late | |
1081 | * suspend hook. | |
1082 | * | |
1083 | * FIXME: This should be solved with a special hdmi sink device or | |
1084 | * similar so that power domains can be employed. | |
1085 | */ | |
1086 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1087 | return 0; | |
112b715e | 1088 | |
ab3be73f ID |
1089 | return i915_drm_suspend_late(drm_dev, false); |
1090 | } | |
1091 | ||
1092 | static int i915_pm_poweroff_late(struct device *dev) | |
1093 | { | |
1094 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; | |
1095 | ||
1096 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1097 | return 0; | |
1098 | ||
1099 | return i915_drm_suspend_late(drm_dev, true); | |
cbda12d7 ZW |
1100 | } |
1101 | ||
76c4b250 ID |
1102 | static int i915_pm_resume_early(struct device *dev) |
1103 | { | |
888d0d42 | 1104 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 | 1105 | |
097dd837 ID |
1106 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1107 | return 0; | |
1108 | ||
5e365c39 | 1109 | return i915_drm_resume_early(drm_dev); |
76c4b250 ID |
1110 | } |
1111 | ||
84b79f8d | 1112 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 1113 | { |
888d0d42 | 1114 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
84b79f8d | 1115 | |
097dd837 ID |
1116 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1117 | return 0; | |
1118 | ||
5a17514e | 1119 | return i915_drm_resume(drm_dev); |
cbda12d7 ZW |
1120 | } |
1121 | ||
ddeea5b0 ID |
1122 | /* |
1123 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
1124 | * S0i[R123] transition. The list of registers needing a save/restore is | |
1125 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
1126 | * registers in the following way: | |
1127 | * - Driver: saved/restored by the driver | |
1128 | * - Punit : saved/restored by the Punit firmware | |
1129 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
1130 | * used internally by the HW in a way that doesn't depend | |
1131 | * keeping the content across a suspend/resume. | |
1132 | * - Debug : used for debugging | |
1133 | * | |
1134 | * We save/restore all registers marked with 'Driver', with the following | |
1135 | * exceptions: | |
1136 | * - Registers out of use, including also registers marked with 'Debug'. | |
1137 | * These have no effect on the driver's operation, so we don't save/restore | |
1138 | * them to reduce the overhead. | |
1139 | * - Registers that are fully setup by an initialization function called from | |
1140 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1141 | * - Registers that provide the right functionality with their reset defaults. | |
1142 | * | |
1143 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1144 | * ignored, we save/restore all others, practically treating the HW context as | |
1145 | * a black-box for the driver. Further investigation is needed to reduce the | |
1146 | * saved/restored registers even further, by following the same 3 criteria. | |
1147 | */ | |
1148 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1149 | { | |
1150 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1151 | int i; | |
1152 | ||
1153 | /* GAM 0x4000-0x4770 */ | |
1154 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1155 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1156 | s->arb_mode = I915_READ(ARB_MODE); | |
1157 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1158 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1159 | ||
1160 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1161 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
1162 | |
1163 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 1164 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
1165 | |
1166 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1167 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1168 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1169 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1170 | ||
1171 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1172 | ||
1173 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1174 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1175 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1176 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1177 | ||
1178 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1179 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1180 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1181 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1182 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1183 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1184 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1185 | ||
1186 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1187 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1188 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1189 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1190 | s->ecobus = I915_READ(ECOBUS); | |
1191 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1192 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1193 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1194 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1195 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1196 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1197 | ||
1198 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1199 | s->gt_imr = I915_READ(GTIMR); | |
1200 | s->gt_ier = I915_READ(GTIER); | |
1201 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1202 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1203 | ||
1204 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1205 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
1206 | |
1207 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1208 | s->tilectl = I915_READ(TILECTL); | |
1209 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1210 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1211 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1212 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1213 | ||
1214 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1215 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1216 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 1217 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
1218 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
1219 | ||
1220 | /* | |
1221 | * Not saving any of: | |
1222 | * DFT, 0x9800-0x9EC0 | |
1223 | * SARB, 0xB000-0xB1FC | |
1224 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1225 | * PCI CFG | |
1226 | */ | |
1227 | } | |
1228 | ||
1229 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1230 | { | |
1231 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1232 | u32 val; | |
1233 | int i; | |
1234 | ||
1235 | /* GAM 0x4000-0x4770 */ | |
1236 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1237 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1238 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1239 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1240 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1241 | ||
1242 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1243 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
1244 | |
1245 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 1246 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
1247 | |
1248 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1249 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1250 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1251 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1252 | ||
1253 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1254 | ||
1255 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1256 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1257 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1258 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1259 | ||
1260 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1261 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1262 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1263 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1264 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1265 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1266 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1267 | ||
1268 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1269 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1270 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1271 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1272 | I915_WRITE(ECOBUS, s->ecobus); | |
1273 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1274 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1275 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1276 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1277 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1278 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1279 | ||
1280 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1281 | I915_WRITE(GTIMR, s->gt_imr); | |
1282 | I915_WRITE(GTIER, s->gt_ier); | |
1283 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1284 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1285 | ||
1286 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1287 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
1288 | |
1289 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1290 | I915_WRITE(TILECTL, s->tilectl); | |
1291 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1292 | /* | |
1293 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1294 | * be restored, as they are used to control the s0ix suspend/resume | |
1295 | * sequence by the caller. | |
1296 | */ | |
1297 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1298 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1299 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1300 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1301 | ||
1302 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1303 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1304 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1305 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1306 | ||
1307 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1308 | ||
1309 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1310 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1311 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 1312 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
1313 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
1314 | } | |
1315 | ||
650ad970 ID |
1316 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1317 | { | |
1318 | u32 val; | |
1319 | int err; | |
1320 | ||
650ad970 | 1321 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) |
650ad970 ID |
1322 | |
1323 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1324 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1325 | if (force_on) | |
1326 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1327 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1328 | ||
1329 | if (!force_on) | |
1330 | return 0; | |
1331 | ||
8d4eee9c | 1332 | err = wait_for(COND, 20); |
650ad970 ID |
1333 | if (err) |
1334 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1335 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1336 | ||
1337 | return err; | |
1338 | #undef COND | |
1339 | } | |
1340 | ||
ddeea5b0 ID |
1341 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1342 | { | |
1343 | u32 val; | |
1344 | int err = 0; | |
1345 | ||
1346 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1347 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1348 | if (allow) | |
1349 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1350 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1351 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1352 | ||
1353 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1354 | allow) | |
1355 | err = wait_for(COND, 1); | |
1356 | if (err) | |
1357 | DRM_ERROR("timeout disabling GT waking\n"); | |
1358 | return err; | |
1359 | #undef COND | |
1360 | } | |
1361 | ||
1362 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1363 | bool wait_for_on) | |
1364 | { | |
1365 | u32 mask; | |
1366 | u32 val; | |
1367 | int err; | |
1368 | ||
1369 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1370 | val = wait_for_on ? mask : 0; | |
1371 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1372 | if (COND) | |
1373 | return 0; | |
1374 | ||
1375 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
87ad3212 JN |
1376 | onoff(wait_for_on), |
1377 | I915_READ(VLV_GTLC_PW_STATUS)); | |
ddeea5b0 ID |
1378 | |
1379 | /* | |
1380 | * RC6 transitioning can be delayed up to 2 msec (see | |
1381 | * valleyview_enable_rps), use 3 msec for safety. | |
1382 | */ | |
1383 | err = wait_for(COND, 3); | |
1384 | if (err) | |
1385 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
87ad3212 | 1386 | onoff(wait_for_on)); |
ddeea5b0 ID |
1387 | |
1388 | return err; | |
1389 | #undef COND | |
1390 | } | |
1391 | ||
1392 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1393 | { | |
1394 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1395 | return; | |
1396 | ||
6fa283b0 | 1397 | DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); |
ddeea5b0 ID |
1398 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
1399 | } | |
1400 | ||
ebc32824 | 1401 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
1402 | { |
1403 | u32 mask; | |
1404 | int err; | |
1405 | ||
1406 | /* | |
1407 | * Bspec defines the following GT well on flags as debug only, so | |
1408 | * don't treat them as hard failures. | |
1409 | */ | |
1410 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1411 | ||
1412 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1413 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1414 | ||
1415 | vlv_check_no_gt_access(dev_priv); | |
1416 | ||
1417 | err = vlv_force_gfx_clock(dev_priv, true); | |
1418 | if (err) | |
1419 | goto err1; | |
1420 | ||
1421 | err = vlv_allow_gt_wake(dev_priv, false); | |
1422 | if (err) | |
1423 | goto err2; | |
98711167 | 1424 | |
2d1fe073 | 1425 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 1426 | vlv_save_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
1427 | |
1428 | err = vlv_force_gfx_clock(dev_priv, false); | |
1429 | if (err) | |
1430 | goto err2; | |
1431 | ||
1432 | return 0; | |
1433 | ||
1434 | err2: | |
1435 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1436 | vlv_allow_gt_wake(dev_priv, true); | |
1437 | err1: | |
1438 | vlv_force_gfx_clock(dev_priv, false); | |
1439 | ||
1440 | return err; | |
1441 | } | |
1442 | ||
016970be SK |
1443 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1444 | bool rpm_resume) | |
ddeea5b0 ID |
1445 | { |
1446 | struct drm_device *dev = dev_priv->dev; | |
1447 | int err; | |
1448 | int ret; | |
1449 | ||
1450 | /* | |
1451 | * If any of the steps fail just try to continue, that's the best we | |
1452 | * can do at this point. Return the first error code (which will also | |
1453 | * leave RPM permanently disabled). | |
1454 | */ | |
1455 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1456 | ||
2d1fe073 | 1457 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 1458 | vlv_restore_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
1459 | |
1460 | err = vlv_allow_gt_wake(dev_priv, true); | |
1461 | if (!ret) | |
1462 | ret = err; | |
1463 | ||
1464 | err = vlv_force_gfx_clock(dev_priv, false); | |
1465 | if (!ret) | |
1466 | ret = err; | |
1467 | ||
1468 | vlv_check_no_gt_access(dev_priv); | |
1469 | ||
016970be SK |
1470 | if (rpm_resume) { |
1471 | intel_init_clock_gating(dev); | |
1472 | i915_gem_restore_fences(dev); | |
1473 | } | |
ddeea5b0 ID |
1474 | |
1475 | return ret; | |
1476 | } | |
1477 | ||
97bea207 | 1478 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1479 | { |
1480 | struct pci_dev *pdev = to_pci_dev(device); | |
1481 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1483 | int ret; |
8a187455 | 1484 | |
aeab0b5a | 1485 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1486 | return -ENODEV; |
1487 | ||
604effb7 ID |
1488 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1489 | return -ENODEV; | |
1490 | ||
8a187455 PZ |
1491 | DRM_DEBUG_KMS("Suspending device\n"); |
1492 | ||
d6102977 ID |
1493 | /* |
1494 | * We could deadlock here in case another thread holding struct_mutex | |
1495 | * calls RPM suspend concurrently, since the RPM suspend will wait | |
1496 | * first for this RPM suspend to finish. In this case the concurrent | |
1497 | * RPM resume will be followed by its RPM suspend counterpart. Still | |
1498 | * for consistency return -EAGAIN, which will reschedule this suspend. | |
1499 | */ | |
1500 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1501 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); | |
1502 | /* | |
1503 | * Bump the expiration timestamp, otherwise the suspend won't | |
1504 | * be rescheduled. | |
1505 | */ | |
1506 | pm_runtime_mark_last_busy(device); | |
1507 | ||
1508 | return -EAGAIN; | |
1509 | } | |
1f814dac ID |
1510 | |
1511 | disable_rpm_wakeref_asserts(dev_priv); | |
1512 | ||
d6102977 ID |
1513 | /* |
1514 | * We are safe here against re-faults, since the fault handler takes | |
1515 | * an RPM reference. | |
1516 | */ | |
1517 | i915_gem_release_all_mmaps(dev_priv); | |
1518 | mutex_unlock(&dev->struct_mutex); | |
1519 | ||
825f2728 JL |
1520 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
1521 | ||
a1c41994 AD |
1522 | intel_guc_suspend(dev); |
1523 | ||
fac6adb0 | 1524 | intel_suspend_gt_powersave(dev); |
2eb5252e | 1525 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 1526 | |
507e126e ID |
1527 | ret = 0; |
1528 | if (IS_BROXTON(dev_priv)) { | |
1529 | bxt_display_core_uninit(dev_priv); | |
1530 | bxt_enable_dc9(dev_priv); | |
1531 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { | |
1532 | hsw_enable_pc8(dev_priv); | |
1533 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
1534 | ret = vlv_suspend_complete(dev_priv); | |
1535 | } | |
1536 | ||
0ab9cfeb ID |
1537 | if (ret) { |
1538 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
b963291c | 1539 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb | 1540 | |
1f814dac ID |
1541 | enable_rpm_wakeref_asserts(dev_priv); |
1542 | ||
0ab9cfeb ID |
1543 | return ret; |
1544 | } | |
a8a8bd54 | 1545 | |
dc9fb09c | 1546 | intel_uncore_forcewake_reset(dev, false); |
1f814dac ID |
1547 | |
1548 | enable_rpm_wakeref_asserts(dev_priv); | |
1549 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); | |
55ec45c2 | 1550 | |
bc3b9346 | 1551 | if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) |
55ec45c2 MK |
1552 | DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
1553 | ||
8a187455 | 1554 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1555 | |
1556 | /* | |
c8a0bd42 PZ |
1557 | * FIXME: We really should find a document that references the arguments |
1558 | * used below! | |
1fb2362b | 1559 | */ |
d37ae19a PZ |
1560 | if (IS_BROADWELL(dev)) { |
1561 | /* | |
1562 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
1563 | * being detected, and the call we do at intel_runtime_resume() | |
1564 | * won't be able to restore them. Since PCI_D3hot matches the | |
1565 | * actual specification and appears to be working, use it. | |
1566 | */ | |
1567 | intel_opregion_notify_adapter(dev, PCI_D3hot); | |
1568 | } else { | |
c8a0bd42 PZ |
1569 | /* |
1570 | * current versions of firmware which depend on this opregion | |
1571 | * notification have repurposed the D1 definition to mean | |
1572 | * "runtime suspended" vs. what you would normally expect (D3) | |
1573 | * to distinguish it from notifications that might be sent via | |
1574 | * the suspend path. | |
1575 | */ | |
1576 | intel_opregion_notify_adapter(dev, PCI_D1); | |
c8a0bd42 | 1577 | } |
8a187455 | 1578 | |
59bad947 | 1579 | assert_forcewakes_inactive(dev_priv); |
dc9fb09c | 1580 | |
a8a8bd54 | 1581 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1582 | return 0; |
1583 | } | |
1584 | ||
97bea207 | 1585 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1586 | { |
1587 | struct pci_dev *pdev = to_pci_dev(device); | |
1588 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1a5df187 | 1590 | int ret = 0; |
8a187455 | 1591 | |
604effb7 ID |
1592 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1593 | return -ENODEV; | |
8a187455 PZ |
1594 | |
1595 | DRM_DEBUG_KMS("Resuming device\n"); | |
1596 | ||
1f814dac ID |
1597 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); |
1598 | disable_rpm_wakeref_asserts(dev_priv); | |
1599 | ||
cd2e9e90 | 1600 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 | 1601 | dev_priv->pm.suspended = false; |
55ec45c2 MK |
1602 | if (intel_uncore_unclaimed_mmio(dev_priv)) |
1603 | DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); | |
8a187455 | 1604 | |
a1c41994 AD |
1605 | intel_guc_resume(dev); |
1606 | ||
1a5df187 PZ |
1607 | if (IS_GEN6(dev_priv)) |
1608 | intel_init_pch_refclk(dev); | |
31335cec | 1609 | |
507e126e ID |
1610 | if (IS_BROXTON(dev)) { |
1611 | bxt_disable_dc9(dev_priv); | |
1612 | bxt_display_core_init(dev_priv, true); | |
f62c79b3 ID |
1613 | if (dev_priv->csr.dmc_payload && |
1614 | (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) | |
1615 | gen9_enable_dc5(dev_priv); | |
507e126e | 1616 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1a5df187 | 1617 | hsw_disable_pc8(dev_priv); |
507e126e | 1618 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
1a5df187 | 1619 | ret = vlv_resume_prepare(dev_priv, true); |
507e126e | 1620 | } |
1a5df187 | 1621 | |
0ab9cfeb ID |
1622 | /* |
1623 | * No point of rolling back things in case of an error, as the best | |
1624 | * we can do is to hope that things will still work (and disable RPM). | |
1625 | */ | |
92b806d3 ID |
1626 | i915_gem_init_swizzling(dev); |
1627 | gen6_update_ring_freq(dev); | |
1628 | ||
b963291c | 1629 | intel_runtime_pm_enable_interrupts(dev_priv); |
08d8a232 VS |
1630 | |
1631 | /* | |
1632 | * On VLV/CHV display interrupts are part of the display | |
1633 | * power well, so hpd is reinitialized from there. For | |
1634 | * everyone else do it here. | |
1635 | */ | |
666a4537 | 1636 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
08d8a232 VS |
1637 | intel_hpd_init(dev_priv); |
1638 | ||
fac6adb0 | 1639 | intel_enable_gt_powersave(dev); |
b5478bcd | 1640 | |
1f814dac ID |
1641 | enable_rpm_wakeref_asserts(dev_priv); |
1642 | ||
0ab9cfeb ID |
1643 | if (ret) |
1644 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1645 | else | |
1646 | DRM_DEBUG_KMS("Device resumed\n"); | |
1647 | ||
1648 | return ret; | |
8a187455 PZ |
1649 | } |
1650 | ||
b4b78d12 | 1651 | static const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
1652 | /* |
1653 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
1654 | * PMSG_RESUME] | |
1655 | */ | |
0206e353 | 1656 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1657 | .suspend_late = i915_pm_suspend_late, |
1658 | .resume_early = i915_pm_resume_early, | |
0206e353 | 1659 | .resume = i915_pm_resume, |
5545dbbf ID |
1660 | |
1661 | /* | |
1662 | * S4 event handlers | |
1663 | * @freeze, @freeze_late : called (1) before creating the | |
1664 | * hibernation image [PMSG_FREEZE] and | |
1665 | * (2) after rebooting, before restoring | |
1666 | * the image [PMSG_QUIESCE] | |
1667 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
1668 | * image, before writing it [PMSG_THAW] | |
1669 | * and (2) after failing to create or | |
1670 | * restore the image [PMSG_RECOVER] | |
1671 | * @poweroff, @poweroff_late: called after writing the hibernation | |
1672 | * image, before rebooting [PMSG_HIBERNATE] | |
1673 | * @restore, @restore_early : called after rebooting and restoring the | |
1674 | * hibernation image [PMSG_RESTORE] | |
1675 | */ | |
36d61e67 ID |
1676 | .freeze = i915_pm_suspend, |
1677 | .freeze_late = i915_pm_suspend_late, | |
1678 | .thaw_early = i915_pm_resume_early, | |
1679 | .thaw = i915_pm_resume, | |
1680 | .poweroff = i915_pm_suspend, | |
ab3be73f | 1681 | .poweroff_late = i915_pm_poweroff_late, |
76c4b250 | 1682 | .restore_early = i915_pm_resume_early, |
0206e353 | 1683 | .restore = i915_pm_resume, |
5545dbbf ID |
1684 | |
1685 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
1686 | .runtime_suspend = intel_runtime_suspend, |
1687 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1688 | }; |
1689 | ||
78b68556 | 1690 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1691 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1692 | .open = drm_gem_vm_open, |
1693 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1694 | }; |
1695 | ||
e08e96de AV |
1696 | static const struct file_operations i915_driver_fops = { |
1697 | .owner = THIS_MODULE, | |
1698 | .open = drm_open, | |
1699 | .release = drm_release, | |
1700 | .unlocked_ioctl = drm_ioctl, | |
1701 | .mmap = drm_gem_mmap, | |
1702 | .poll = drm_poll, | |
e08e96de AV |
1703 | .read = drm_read, |
1704 | #ifdef CONFIG_COMPAT | |
1705 | .compat_ioctl = i915_compat_ioctl, | |
1706 | #endif | |
1707 | .llseek = noop_llseek, | |
1708 | }; | |
1709 | ||
1da177e4 | 1710 | static struct drm_driver driver = { |
0c54781b MW |
1711 | /* Don't use MTRRs here; the Xserver or userspace app should |
1712 | * deal with them for Intel hardware. | |
792d2b9a | 1713 | */ |
673a394b | 1714 | .driver_features = |
10ba5012 | 1715 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1751fcf9 | 1716 | DRIVER_RENDER | DRIVER_MODESET, |
22eae947 | 1717 | .load = i915_driver_load, |
ba8bbcf6 | 1718 | .unload = i915_driver_unload, |
673a394b | 1719 | .open = i915_driver_open, |
22eae947 DA |
1720 | .lastclose = i915_driver_lastclose, |
1721 | .preclose = i915_driver_preclose, | |
673a394b | 1722 | .postclose = i915_driver_postclose, |
915b4d11 | 1723 | .set_busid = drm_pci_set_busid, |
d8e29209 | 1724 | |
955b12de | 1725 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1726 | .debugfs_init = i915_debugfs_init, |
1727 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1728 | #endif |
673a394b | 1729 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1730 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1731 | |
1732 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1733 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1734 | .gem_prime_export = i915_gem_prime_export, | |
1735 | .gem_prime_import = i915_gem_prime_import, | |
1736 | ||
ff72145b | 1737 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 1738 | .dumb_map_offset = i915_gem_mmap_gtt, |
43387b37 | 1739 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1740 | .ioctls = i915_ioctls, |
e08e96de | 1741 | .fops = &i915_driver_fops, |
22eae947 DA |
1742 | .name = DRIVER_NAME, |
1743 | .desc = DRIVER_DESC, | |
1744 | .date = DRIVER_DATE, | |
1745 | .major = DRIVER_MAJOR, | |
1746 | .minor = DRIVER_MINOR, | |
1747 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1748 | }; |
1749 | ||
8410ea3b DA |
1750 | static struct pci_driver i915_pci_driver = { |
1751 | .name = DRIVER_NAME, | |
1752 | .id_table = pciidlist, | |
1753 | .probe = i915_pci_probe, | |
1754 | .remove = i915_pci_remove, | |
1755 | .driver.pm = &i915_pm_ops, | |
1756 | }; | |
1757 | ||
1da177e4 LT |
1758 | static int __init i915_init(void) |
1759 | { | |
1760 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1761 | |
1762 | /* | |
fd930478 CW |
1763 | * Enable KMS by default, unless explicitly overriden by |
1764 | * either the i915.modeset prarameter or by the | |
1765 | * vga_text_mode_force boot option. | |
79e53945 | 1766 | */ |
fd930478 CW |
1767 | |
1768 | if (i915.modeset == 0) | |
1769 | driver.driver_features &= ~DRIVER_MODESET; | |
79e53945 | 1770 | |
d330a953 | 1771 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 | 1772 | driver.driver_features &= ~DRIVER_MODESET; |
79e53945 | 1773 | |
b30324ad | 1774 | if (!(driver.driver_features & DRIVER_MODESET)) { |
b30324ad | 1775 | /* Silently fail loading to not upset userspace. */ |
c9cd7b65 | 1776 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
b30324ad | 1777 | return 0; |
b30324ad | 1778 | } |
3885c6bb | 1779 | |
c5b852f3 | 1780 | if (i915.nuclear_pageflip) |
b2e7723b MR |
1781 | driver.driver_features |= DRIVER_ATOMIC; |
1782 | ||
8410ea3b | 1783 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1784 | } |
1785 | ||
1786 | static void __exit i915_exit(void) | |
1787 | { | |
b33ecdd1 DV |
1788 | if (!(driver.driver_features & DRIVER_MODESET)) |
1789 | return; /* Never loaded a driver. */ | |
b33ecdd1 | 1790 | |
8410ea3b | 1791 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1792 | } |
1793 | ||
1794 | module_init(i915_init); | |
1795 | module_exit(i915_exit); | |
1796 | ||
0a6d1631 | 1797 | MODULE_AUTHOR("Tungsten Graphics, Inc."); |
1eab9234 | 1798 | MODULE_AUTHOR("Intel Corporation"); |
0a6d1631 | 1799 | |
b5e89ed5 | 1800 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 | 1801 | MODULE_LICENSE("GPL and additional rights"); |