]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/gpu/drm/i915/i915_drv.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Set PCH_NOP
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/i915_drm.h>
1da177e4 33#include "i915_drv.h"
990bbdad 34#include "i915_trace.h"
f49f0586 35#include "intel_drv.h"
1da177e4 36
79e53945 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
760285e7 39#include <drm/drm_crtc_helper.h>
79e53945 40
a35d9d3c 41static int i915_modeset __read_mostly = -1;
79e53945 42module_param_named(modeset, i915_modeset, int, 0400);
6e96e775
BW		 43MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
79e53945 46
a35d9d3c 47unsigned int i915_fbpercrtc __always_unused = 0;
79e53945 48module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 49
a726915c 50int i915_panel_ignore_lid __read_mostly = 1;
fca87409 51module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
6e96e775 52MODULE_PARM_DESC(panel_ignore_lid,
a726915c
DV		 53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
fca87409 55
a35d9d3c 56unsigned int i915_powersave __read_mostly = 1;
0aa99277 57module_param_named(powersave, i915_powersave, int, 0600);
6e96e775
BW		 58MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
652c393a 60
f45b5557 61int i915_semaphores __read_mostly = -1;
a1656b90 62module_param_named(semaphores, i915_semaphores, int, 0600);
6e96e775 63MODULE_PARM_DESC(semaphores,
f45b5557 64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
a1656b90 65
c0f372b3 66int i915_enable_rc6 __read_mostly = -1;
f57f9c16 67module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
6e96e775 68MODULE_PARM_DESC(i915_enable_rc6,
83b7f9ac
ED		 69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
ac668088 74
4415e63b 75int i915_enable_fbc __read_mostly = -1;
c1a9f047 76module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
6e96e775
BW		 77MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
cd0de039 79 "(default: -1 (use per-chip default))");
c1a9f047 80
a35d9d3c 81unsigned int i915_lvds_downclock __read_mostly = 0;
33814341 82module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
6e96e775
BW		 83MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
33814341 86
121d527a
TI		 87int i915_lvds_channel_mode __read_mostly;
88module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
4415e63b 93int i915_panel_use_ssc __read_mostly = -1;
a7615030 94module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
6e96e775
BW		 95MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
72bbe58c 97 "(default: auto from VBT)");
a7615030 98
a35d9d3c 99int i915_vbt_sdvo_panel_type __read_mostly = -1;
5a1e5b6c 100module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
6e96e775 101MODULE_PARM_DESC(vbt_sdvo_panel_type,
c10e408a
MF		 102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
5a1e5b6c 104
a35d9d3c 105static bool i915_try_reset __read_mostly = true;
d78cb50b 106module_param_named(reset, i915_try_reset, bool, 0600);
6e96e775 107MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
d78cb50b 108
a35d9d3c 109bool i915_enable_hangcheck __read_mostly = true;
3e0dc6b0 110module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
6e96e775
BW		 111MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
3e0dc6b0 115
650dc07e
DV		 116int i915_enable_ppgtt __read_mostly = -1;
117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
e21af88d
DV		 118MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
0a3af268
RV		 121unsigned int i915_preliminary_hw_support __read_mostly = 0;
122module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123MODULE_PARM_DESC(preliminary_hw_support,
c4aaf350 124 "Enable preliminary hardware support. (default: false)");
0a3af268 125
2124b72e
PZ		 126int i915_disable_power_well __read_mostly = 0;
127module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
128MODULE_PARM_DESC(disable_power_well,
129 "Disable the power well when possible (default: false)");
130
112b715e 131static struct drm_driver driver;
1f7a6e37 132extern int intel_agp_enabled;
112b715e 133
cfdf1fa2 134#define INTEL_VGA_DEVICE(id, info) { \
80a2901d 135 .class = PCI_BASE_CLASS_DISPLAY << 16, \
934f992c 136 .class_mask = 0xff0000, \
49ae35f2
KH		 137 .vendor = 0x8086, \
138 .device = id, \
139 .subvendor = PCI_ANY_ID, \
140 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH		 141 .driver_data = (unsigned long) info }
142
9a7e8492 143static const struct intel_device_info intel_i830_info = {
7eb552ae 144 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
31578148 145 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 146};
147
9a7e8492 148static const struct intel_device_info intel_845g_info = {
7eb552ae 149 .gen = 2, .num_pipes = 1,
31578148 150 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 151};
152
9a7e8492 153static const struct intel_device_info intel_i85x_info = {
7eb552ae 154 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
5ce8ba7c 155 .cursor_needs_physical = 1,
31578148 156 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 157};
158
9a7e8492 159static const struct intel_device_info intel_i865g_info = {
7eb552ae 160 .gen = 2, .num_pipes = 1,
31578148 161 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 162};
163
9a7e8492 164static const struct intel_device_info intel_i915g_info = {
7eb552ae 165 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
31578148 166 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 167};
9a7e8492 168static const struct intel_device_info intel_i915gm_info = {
7eb552ae 169 .gen = 3, .is_mobile = 1, .num_pipes = 2,
b295d1b6 170 .cursor_needs_physical = 1,
31578148 171 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 172 .supports_tv = 1,
cfdf1fa2 173};
9a7e8492 174static const struct intel_device_info intel_i945g_info = {
7eb552ae 175 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
31578148 176 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 177};
9a7e8492 178static const struct intel_device_info intel_i945gm_info = {
7eb552ae 179 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
b295d1b6 180 .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 181 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 182 .supports_tv = 1,
cfdf1fa2
KH		 183};
184
9a7e8492 185static const struct intel_device_info intel_i965g_info = {
7eb552ae 186 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
c96c3a8c 187 .has_hotplug = 1,
31578148 188 .has_overlay = 1,
cfdf1fa2
KH		 189};
190
9a7e8492 191static const struct intel_device_info intel_i965gm_info = {
7eb552ae 192 .gen = 4, .is_crestline = 1, .num_pipes = 2,
e3c4e5dd 193 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
31578148 194 .has_overlay = 1,
a6c45cf0 195 .supports_tv = 1,
cfdf1fa2
KH		 196};
197
9a7e8492 198static const struct intel_device_info intel_g33_info = {
7eb552ae 199 .gen = 3, .is_g33 = 1, .num_pipes = 2,
c96c3a8c 200 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 201 .has_overlay = 1,
cfdf1fa2
KH		 202};
203
9a7e8492 204static const struct intel_device_info intel_g45_info = {
7eb552ae 205 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
c96c3a8c 206 .has_pipe_cxsr = 1, .has_hotplug = 1,
92f49d9c 207 .has_bsd_ring = 1,
cfdf1fa2
KH		 208};
209
9a7e8492 210static const struct intel_device_info intel_gm45_info = {
7eb552ae 211 .gen = 4, .is_g4x = 1, .num_pipes = 2,
e3c4e5dd 212 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
c96c3a8c 213 .has_pipe_cxsr = 1, .has_hotplug = 1,
a6c45cf0 214 .supports_tv = 1,
92f49d9c 215 .has_bsd_ring = 1,
cfdf1fa2
KH		 216};
217
9a7e8492 218static const struct intel_device_info intel_pineview_info = {
7eb552ae 219 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
c96c3a8c 220 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 221 .has_overlay = 1,
cfdf1fa2
KH		 222};
223
9a7e8492 224static const struct intel_device_info intel_ironlake_d_info = {
7eb552ae 225 .gen = 5, .num_pipes = 2,
5a117db7 226 .need_gfx_hws = 1, .has_hotplug = 1,
92f49d9c 227 .has_bsd_ring = 1,
cfdf1fa2
KH		 228};
229
9a7e8492 230static const struct intel_device_info intel_ironlake_m_info = {
7eb552ae 231 .gen = 5, .is_mobile = 1, .num_pipes = 2,
e3c4e5dd 232 .need_gfx_hws = 1, .has_hotplug = 1,
c1a9f047 233 .has_fbc = 1,
92f49d9c 234 .has_bsd_ring = 1,
cfdf1fa2
KH		 235};
236
9a7e8492 237static const struct intel_device_info intel_sandybridge_d_info = {
7eb552ae 238 .gen = 6, .num_pipes = 2,
c96c3a8c 239 .need_gfx_hws = 1, .has_hotplug = 1,
881f47b6 240 .has_bsd_ring = 1,
549f7365 241 .has_blt_ring = 1,
3d29b842 242 .has_llc = 1,
b7884eb4 243 .has_force_wake = 1,
f6e450a6
EA		 244};
245
9a7e8492 246static const struct intel_device_info intel_sandybridge_m_info = {
7eb552ae 247 .gen = 6, .is_mobile = 1, .num_pipes = 2,
c96c3a8c 248 .need_gfx_hws = 1, .has_hotplug = 1,
9c04f015 249 .has_fbc = 1,
881f47b6 250 .has_bsd_ring = 1,
549f7365 251 .has_blt_ring = 1,
3d29b842 252 .has_llc = 1,
b7884eb4 253 .has_force_wake = 1,
a13e4093
EA		 254};
255
219f4fdb
BW		 256#define GEN7_FEATURES \
257 .gen = 7, .num_pipes = 3, \
258 .need_gfx_hws = 1, .has_hotplug = 1, \
259 .has_bsd_ring = 1, \
260 .has_blt_ring = 1, \
261 .has_llc = 1, \
262 .has_force_wake = 1
263
c76b615c 264static const struct intel_device_info intel_ivybridge_d_info = {
219f4fdb
BW		 265 GEN7_FEATURES,
266 .is_ivybridge = 1,
c76b615c
JB		 267};
268
269static const struct intel_device_info intel_ivybridge_m_info = {
219f4fdb
BW		 270 GEN7_FEATURES,
271 .is_ivybridge = 1,
272 .is_mobile = 1,
c76b615c
JB		 273};
274
70a3eb7a 275static const struct intel_device_info intel_valleyview_m_info = {
219f4fdb
BW		 276 GEN7_FEATURES,
277 .is_mobile = 1,
278 .num_pipes = 2,
70a3eb7a 279 .is_valleyview = 1,
fba5d532 280 .display_mmio_offset = VLV_DISPLAY_BASE,
70a3eb7a
JB		 281};
282
283static const struct intel_device_info intel_valleyview_d_info = {
219f4fdb
BW		 284 GEN7_FEATURES,
285 .num_pipes = 2,
70a3eb7a 286 .is_valleyview = 1,
fba5d532 287 .display_mmio_offset = VLV_DISPLAY_BASE,
70a3eb7a
JB		 288};
289
4cae9ae0 290static const struct intel_device_info intel_haswell_d_info = {
219f4fdb
BW		 291 GEN7_FEATURES,
292 .is_haswell = 1,
4cae9ae0
ED		 293};
294
295static const struct intel_device_info intel_haswell_m_info = {
219f4fdb
BW		 296 GEN7_FEATURES,
297 .is_haswell = 1,
298 .is_mobile = 1,
c76b615c
JB		 299};
300
6103da0d
CW		 301static const struct pci_device_id pciidlist[] = { /* aka */
302 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
303 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
304 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
5ce8ba7c 305 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
6103da0d
CW		 306 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
307 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
308 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
309 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
310 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
311 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
312 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
313 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
314 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
315 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
316 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
317 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
318 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
319 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
320 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
321 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
322 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
323 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
324 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
325 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
326 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
327 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
41a51428 328 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
cfdf1fa2
KH		 329 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
330 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
331 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
332 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
f6e450a6 333 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
85540480
ZW		 334 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
335 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
a13e4093 336 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
85540480 337 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
4fefe435 338 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
85540480 339 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
c76b615c
JB		 340 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
341 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
342 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
343 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
344 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
cc22a938 345 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
c14f5286
ED		 346 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
347 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
da612d88 348 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
c14f5286
ED		 349 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
350 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
da612d88 351 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
c14f5286
ED		 352 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
353 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
da612d88
PZ		 354 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
355 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
356 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
357 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
358 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
359 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
360 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
361 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
362 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
363 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
364 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
365 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
366 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
367 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
368 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
369 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
370 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
371 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
372 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
86c268ed
KG		 373 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
374 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
da612d88 375 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
86c268ed
KG		 376 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
377 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
da612d88 378 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
86c268ed
KG		 379 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
380 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
da612d88 381 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
ff049b6c 382 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
d7fee5f6
JB		 383 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
384 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
385 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
ff049b6c
JB		 386 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
387 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
49ae35f2 388 {0, 0, 0}
1da177e4
LT		 389};
390
79e53945
JB		 391#if defined(CONFIG_DRM_I915_KMS)
392MODULE_DEVICE_TABLE(pci, pciidlist);
393#endif
394
0206e353 395void intel_detect_pch(struct drm_device *dev)
3bad0781
ZW		 396{
397 struct drm_i915_private *dev_priv = dev->dev_private;
398 struct pci_dev *pch;
399
ce1bb329
BW		 400 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
401 * (which really amounts to a PCH but no South Display).
402 */
403 if (INTEL_INFO(dev)->num_pipes == 0) {
404 dev_priv->pch_type = PCH_NOP;
405 dev_priv->num_pch_pll = 0;
406 return;
407 }
408
3bad0781
ZW		 409 /*
410 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
411 * make graphics device passthrough work easy for VMM, that only
412 * need to expose ISA bridge to let driver know the real hardware
413 * underneath. This is a requirement from virtualization team.
414 */
415 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
416 if (pch) {
417 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
17a303ec 418 unsigned short id;
3bad0781 419 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
17a303ec 420 dev_priv->pch_id = id;
3bad0781 421
90711d50
JB		 422 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
423 dev_priv->pch_type = PCH_IBX;
ee7b9f93 424 dev_priv->num_pch_pll = 2;
90711d50 425 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
7fcb83cd 426 WARN_ON(!IS_GEN5(dev));
90711d50 427 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
3bad0781 428 dev_priv->pch_type = PCH_CPT;
ee7b9f93 429 dev_priv->num_pch_pll = 2;
3bad0781 430 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
7fcb83cd 431 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
c792513b
JB		 432 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
433 /* PantherPoint is CPT compatible */
434 dev_priv->pch_type = PCH_CPT;
ee7b9f93 435 dev_priv->num_pch_pll = 2;
c792513b 436 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
7fcb83cd 437 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
eb877ebf
ED		 438 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
439 dev_priv->pch_type = PCH_LPT;
ee7b9f93 440 dev_priv->num_pch_pll = 0;
eb877ebf 441 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
7fcb83cd 442 WARN_ON(!IS_HASWELL(dev));
ae6935dd
WSC		 443 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
444 dev_priv->pch_type = PCH_LPT;
445 dev_priv->num_pch_pll = 0;
446 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
447 WARN_ON(!IS_HASWELL(dev));
3bad0781 448 }
ee7b9f93 449 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
3bad0781
ZW		 450 }
451 pci_dev_put(pch);
452 }
453}
454
2911a35b
BW		 455bool i915_semaphore_is_enabled(struct drm_device *dev)
456{
457 if (INTEL_INFO(dev)->gen < 6)
458 return 0;
459
460 if (i915_semaphores >= 0)
461 return i915_semaphores;
462
59de3295 463#ifdef CONFIG_INTEL_IOMMU
2911a35b 464 /* Enable semaphores on SNB when IO remapping is off */
59de3295
DV		 465 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
466 return false;
467#endif
2911a35b
BW		 468
469 return 1;
470}
471
84b79f8d 472static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 473{
61caf87c 474 struct drm_i915_private *dev_priv = dev->dev_private;
24576d23 475 struct drm_crtc *crtc;
61caf87c 476
b8efb17b
ZR		 477 /* ignore lid events during suspend */
478 mutex_lock(&dev_priv->modeset_restore_lock);
479 dev_priv->modeset_restore = MODESET_SUSPENDED;
480 mutex_unlock(&dev_priv->modeset_restore_lock);
481
cb10799c
PZ		 482 intel_set_power_well(dev, true);
483
5bcf719b
DA		 484 drm_kms_helper_poll_disable(dev);
485
ba8bbcf6 486 pci_save_state(dev->pdev);
ba8bbcf6 487
5669fcac 488 /* If KMS is active, we do the leavevt stuff here */
226485e9 489 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW		 490 int error = i915_gem_idle(dev);
491 if (error) {
226485e9 492 dev_err(&dev->pdev->dev,
84b79f8d
RW		 493 "GEM idle failed, resume might fail\n");
494 return error;
495 }
a261b246 496
1a01ab3b
JB		 497 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
498
226485e9 499 drm_irq_uninstall(dev);
15239099 500 dev_priv->enable_hotplug_processing = false;
24576d23
JB		 501 /*
502 * Disable CRTCs directly since we want to preserve sw state
503 * for _thaw.
504 */
505 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
506 dev_priv->display.crtc_disable(crtc);
5669fcac
JB		 507 }
508
9e06dd39
JB		 509 i915_save_state(dev);
510
44834a67 511 intel_opregion_fini(dev);
8ee1c3db 512
3fa016a0
DA		 513 console_lock();
514 intel_fbdev_set_suspend(dev, 1);
515 console_unlock();
516
61caf87c 517 return 0;
84b79f8d
RW		 518}
519
6a9ee8af 520int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 521{
522 int error;
523
524 if (!dev || !dev->dev_private) {
525 DRM_ERROR("dev: %p\n", dev);
526 DRM_ERROR("DRM not initialized, aborting suspend.\n");
527 return -ENODEV;
528 }
529
530 if (state.event == PM_EVENT_PRETHAW)
531 return 0;
532
5bcf719b
DA		 533
534 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
535 return 0;
6eecba33 536
84b79f8d
RW		 537 error = i915_drm_freeze(dev);
538 if (error)
539 return error;
540
b932ccb5
DA		 541 if (state.event == PM_EVENT_SUSPEND) {
542 /* Shut down the device */
543 pci_disable_device(dev->pdev);
544 pci_set_power_state(dev->pdev, PCI_D3hot);
545 }
ba8bbcf6
JB		 546
547 return 0;
548}
549
073f34d9
JB		 550void intel_console_resume(struct work_struct *work)
551{
552 struct drm_i915_private *dev_priv =
553 container_of(work, struct drm_i915_private,
554 console_resume_work);
555 struct drm_device *dev = dev_priv->dev;
556
557 console_lock();
558 intel_fbdev_set_suspend(dev, 0);
559 console_unlock();
560}
561
bb60b969
JB		 562static void intel_resume_hotplug(struct drm_device *dev)
563{
564 struct drm_mode_config *mode_config = &dev->mode_config;
565 struct intel_encoder *encoder;
566
567 mutex_lock(&mode_config->mutex);
568 DRM_DEBUG_KMS("running encoder hotplug functions\n");
569
570 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
571 if (encoder->hot_plug)
572 encoder->hot_plug(encoder);
573
574 mutex_unlock(&mode_config->mutex);
575
576 /* Just fire off a uevent and let userspace tell us what to do */
577 drm_helper_hpd_irq_event(dev);
578}
579
1abd02e2 580static int __i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 581{
5669fcac 582 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 583 int error = 0;
8ee1c3db 584
61caf87c 585 i915_restore_state(dev);
44834a67 586 intel_opregion_setup(dev);
61caf87c 587
5669fcac
JB		 588 /* KMS EnterVT equivalent */
589 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
dde86e2d 590 intel_init_pch_refclk(dev);
1833b134 591
5669fcac
JB		 592 mutex_lock(&dev->struct_mutex);
593 dev_priv->mm.suspended = 0;
594
f691e2f4 595 error = i915_gem_init_hw(dev);
5669fcac 596 mutex_unlock(&dev->struct_mutex);
226485e9 597
15239099
DV		 598 /* We need working interrupts for modeset enabling ... */
599 drm_irq_install(dev);
600
1833b134 601 intel_modeset_init_hw(dev);
24576d23
JB		 602
603 drm_modeset_lock_all(dev);
604 intel_modeset_setup_hw_state(dev, true);
605 drm_modeset_unlock_all(dev);
15239099
DV		 606
607 /*
608 * ... but also need to make sure that hotplug processing
609 * doesn't cause havoc. Like in the driver load code we don't
610 * bother with the tiny race here where we might loose hotplug
611 * notifications.
612 * */
20afbda2 613 intel_hpd_init(dev);
15239099 614 dev_priv->enable_hotplug_processing = true;
bb60b969
JB		 615 /* Config may have changed between suspend and resume */
616 intel_resume_hotplug(dev);
d5bb081b 617 }
1daed3fb 618
44834a67
CW		 619 intel_opregion_init(dev);
620
073f34d9
JB		 621 /*
622 * The console lock can be pretty contented on resume due
623 * to all the printk activity. Try to keep it out of the hot
624 * path of resume if possible.
625 */
626 if (console_trylock()) {
627 intel_fbdev_set_suspend(dev, 0);
628 console_unlock();
629 } else {
630 schedule_work(&dev_priv->console_resume_work);
631 }
632
b8efb17b
ZR		 633 mutex_lock(&dev_priv->modeset_restore_lock);
634 dev_priv->modeset_restore = MODESET_DONE;
635 mutex_unlock(&dev_priv->modeset_restore_lock);
84b79f8d
RW		 636 return error;
637}
638
1abd02e2
JB		 639static int i915_drm_thaw(struct drm_device *dev)
640{
641 int error = 0;
642
643 intel_gt_reset(dev);
644
645 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
646 mutex_lock(&dev->struct_mutex);
647 i915_gem_restore_gtt_mappings(dev);
648 mutex_unlock(&dev->struct_mutex);
649 }
650
651 __i915_drm_thaw(dev);
652
84b79f8d
RW		 653 return error;
654}
655
6a9ee8af 656int i915_resume(struct drm_device *dev)
84b79f8d 657{
1abd02e2 658 struct drm_i915_private *dev_priv = dev->dev_private;
6eecba33
CW		 659 int ret;
660
5bcf719b
DA		 661 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
662 return 0;
663
84b79f8d
RW		 664 if (pci_enable_device(dev->pdev))
665 return -EIO;
666
667 pci_set_master(dev->pdev);
668
1abd02e2
JB		 669 intel_gt_reset(dev);
670
671 /*
672 * Platforms with opregion should have sane BIOS, older ones (gen3 and
673 * earlier) need this since the BIOS might clear all our scratch PTEs.
674 */
675 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
676 !dev_priv->opregion.header) {
677 mutex_lock(&dev->struct_mutex);
678 i915_gem_restore_gtt_mappings(dev);
679 mutex_unlock(&dev->struct_mutex);
680 }
681
682 ret = __i915_drm_thaw(dev);
6eecba33
CW		 683 if (ret)
684 return ret;
685
686 drm_kms_helper_poll_enable(dev);
687 return 0;
ba8bbcf6
JB		 688}
689
d4b8bb2a 690static int i8xx_do_reset(struct drm_device *dev)
dc96e9b8
CW		 691{
692 struct drm_i915_private *dev_priv = dev->dev_private;
693
694 if (IS_I85X(dev))
695 return -ENODEV;
696
697 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
698 POSTING_READ(D_STATE);
699
700 if (IS_I830(dev) || IS_845G(dev)) {
701 I915_WRITE(DEBUG_RESET_I830,
702 DEBUG_RESET_DISPLAY |
703 DEBUG_RESET_RENDER |
704 DEBUG_RESET_FULL);
705 POSTING_READ(DEBUG_RESET_I830);
706 msleep(1);
707
708 I915_WRITE(DEBUG_RESET_I830, 0);
709 POSTING_READ(DEBUG_RESET_I830);
710 }
711
712 msleep(1);
713
714 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
715 POSTING_READ(D_STATE);
716
717 return 0;
718}
719
f49f0586
KG		 720static int i965_reset_complete(struct drm_device *dev)
721{
722 u8 gdrst;
eeccdcac 723 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
5fe9fe8c 724 return (gdrst & GRDOM_RESET_ENABLE) == 0;
f49f0586
KG		 725}
726
d4b8bb2a 727static int i965_do_reset(struct drm_device *dev)
0573ed4a 728{
5ccce180 729 int ret;
0573ed4a
KG		 730 u8 gdrst;
731
ae681d96
CW		 732 /*
733 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
734 * well as the reset bit (GR/bit 0). Setting the GR bit
735 * triggers the reset; when done, the hardware will clear it.
736 */
0573ed4a 737 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
d4b8bb2a 738 pci_write_config_byte(dev->pdev, I965_GDRST,
5ccce180
DV		 739 gdrst | GRDOM_RENDER |
740 GRDOM_RESET_ENABLE);
741 ret = wait_for(i965_reset_complete(dev), 500);
742 if (ret)
743 return ret;
744
745 /* We can't reset render&media without also resetting display ... */
746 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
747 pci_write_config_byte(dev->pdev, I965_GDRST,
748 gdrst | GRDOM_MEDIA |
749 GRDOM_RESET_ENABLE);
0573ed4a
KG		 750
751 return wait_for(i965_reset_complete(dev), 500);
752}
753
d4b8bb2a 754static int ironlake_do_reset(struct drm_device *dev)
0573ed4a
KG		 755{
756 struct drm_i915_private *dev_priv = dev->dev_private;
5ccce180
DV		 757 u32 gdrst;
758 int ret;
759
760 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
8a5c2ae7 761 gdrst &= ~GRDOM_MASK;
5ccce180
DV		 762 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
763 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
764 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
765 if (ret)
766 return ret;
767
768 /* We can't reset render&media without also resetting display ... */
769 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
8a5c2ae7 770 gdrst &= ~GRDOM_MASK;
d4b8bb2a 771 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
5ccce180 772 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
0573ed4a 773 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
ba8bbcf6
JB		 774}
775
d4b8bb2a 776static int gen6_do_reset(struct drm_device *dev)
cff458c2
EA		 777{
778 struct drm_i915_private *dev_priv = dev->dev_private;
b6e45f86
KP		 779 int ret;
780 unsigned long irqflags;
cff458c2 781
286fed41
KP		 782 /* Hold gt_lock across reset to prevent any register access
783 * with forcewake not set correctly
784 */
b6e45f86 785 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
286fed41
KP		 786
787 /* Reset the chip */
788
789 /* GEN6_GDRST is not in the gt power well, no need to check
790 * for fifo space for the write or forcewake the chip for
791 * the read
792 */
793 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
794
795 /* Spin waiting for the device to ack the reset request */
796 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
797
798 /* If reset with a user forcewake, try to restore, otherwise turn it off */
b6e45f86 799 if (dev_priv->forcewake_count)
990bbdad 800 dev_priv->gt.force_wake_get(dev_priv);
286fed41 801 else
990bbdad 802 dev_priv->gt.force_wake_put(dev_priv);
286fed41
KP		 803
804 /* Restore fifo count */
805 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
806
b6e45f86
KP		 807 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
808 return ret;
cff458c2
EA		 809}
810
8e96d9c4 811int intel_gpu_reset(struct drm_device *dev)
350d2706 812{
2b9dc9a2 813 struct drm_i915_private *dev_priv = dev->dev_private;
350d2706
DV		 814 int ret = -ENODEV;
815
816 switch (INTEL_INFO(dev)->gen) {
817 case 7:
818 case 6:
d4b8bb2a 819 ret = gen6_do_reset(dev);
350d2706
DV		 820 break;
821 case 5:
d4b8bb2a 822 ret = ironlake_do_reset(dev);
350d2706
DV		 823 break;
824 case 4:
d4b8bb2a 825 ret = i965_do_reset(dev);
350d2706
DV		 826 break;
827 case 2:
d4b8bb2a 828 ret = i8xx_do_reset(dev);
350d2706
DV		 829 break;
830 }
831
2b9dc9a2 832 /* Also reset the gpu hangman. */
99584db3 833 if (dev_priv->gpu_error.stop_rings) {
bae36991 834 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
99584db3 835 dev_priv->gpu_error.stop_rings = 0;
2b9dc9a2
DV		 836 if (ret == -ENODEV) {
837 DRM_ERROR("Reset not implemented, but ignoring "
838 "error for simulated gpu hangs\n");
839 ret = 0;
840 }
841 }
842
350d2706
DV		 843 return ret;
844}
845
11ed50ec 846/**
f3953dcb 847 * i915_reset - reset chip after a hang
11ed50ec 848 * @dev: drm device to reset
11ed50ec
BG		 849 *
850 * Reset the chip. Useful if a hang is detected. Returns zero on successful
851 * reset or otherwise an error code.
852 *
853 * Procedure is fairly simple:
854 * - reset the chip using the reset reg
855 * - re-init context state
856 * - re-init hardware status page
857 * - re-init ring buffer
858 * - re-init interrupt state
859 * - re-init display
860 */
d4b8bb2a 861int i915_reset(struct drm_device *dev)
11ed50ec
BG		 862{
863 drm_i915_private_t *dev_priv = dev->dev_private;
0573ed4a 864 int ret;
11ed50ec 865
d78cb50b
CW		 866 if (!i915_try_reset)
867 return 0;
868
d54a02c0 869 mutex_lock(&dev->struct_mutex);
11ed50ec 870
069efc1d 871 i915_gem_reset(dev);
77f01230 872
f803aa55 873 ret = -ENODEV;
99584db3 874 if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
ae681d96 875 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
350d2706 876 else
d4b8bb2a 877 ret = intel_gpu_reset(dev);
350d2706 878
99584db3 879 dev_priv->gpu_error.last_reset = get_seconds();
0573ed4a 880 if (ret) {
f803aa55 881 DRM_ERROR("Failed to reset chip.\n");
f953c935 882 mutex_unlock(&dev->struct_mutex);
f803aa55 883 return ret;
11ed50ec
BG		 884 }
885
886 /* Ok, now get things going again... */
887
888 /*
889 * Everything depends on having the GTT running, so we need to start
890 * there. Fortunately we don't need to do this unless we reset the
891 * chip at a PCI level.
892 *
893 * Next we need to restore the context, but we don't use those
894 * yet either...
895 *
896 * Ring buffer needs to be re-initialized in the KMS case, or if X
897 * was running at the time of the reset (i.e. we weren't VT
898 * switched away).
899 */
900 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
8187a2b7 901 !dev_priv->mm.suspended) {
b4519513
CW		 902 struct intel_ring_buffer *ring;
903 int i;
904
11ed50ec 905 dev_priv->mm.suspended = 0;
75a6898f 906
f691e2f4
DV		 907 i915_gem_init_swizzling(dev);
908
b4519513
CW		 909 for_each_ring(ring, dev_priv, i)
910 ring->init(ring);
75a6898f 911
254f965c 912 i915_gem_context_init(dev);
e21af88d
DV		 913 i915_gem_init_ppgtt(dev);
914
8e88a2bd
DV		 915 /*
916 * It would make sense to re-init all the other hw state, at
917 * least the rps/rc6/emon init done within modeset_init_hw. For
918 * some unknown reason, this blows up my ilk, so don't.
919 */
f817586c 920
8e88a2bd 921 mutex_unlock(&dev->struct_mutex);
f817586c 922
11ed50ec
BG		 923 drm_irq_uninstall(dev);
924 drm_irq_install(dev);
20afbda2 925 intel_hpd_init(dev);
bcbc324a
DV		 926 } else {
927 mutex_unlock(&dev->struct_mutex);
11ed50ec
BG		 928 }
929
11ed50ec
BG		 930 return 0;
931}
932
56550d94 933static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
112b715e 934{
01a06850
DV		 935 struct intel_device_info *intel_info =
936 (struct intel_device_info *) ent->driver_data;
937
70b12bb4 938 if (intel_info->is_valleyview)
0a3af268
RV		 939 if(!i915_preliminary_hw_support) {
940 DRM_ERROR("Preliminary hardware support disabled\n");
941 return -ENODEV;
942 }
943
5fe49d86
CW		 944 /* Only bind to function 0 of the device. Early generations
945 * used function 1 as a placeholder for multi-head. This causes
946 * us confusion instead, especially on the systems where both
947 * functions have the same PCI-ID!
948 */
949 if (PCI_FUNC(pdev->devfn))
950 return -ENODEV;
951
01a06850
DV		 952 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
953 * implementation for gen3 (and only gen3) that used legacy drm maps
954 * (gasp!) to share buffers between X and the client. Hence we need to
955 * keep around the fake agp stuff for gen3, even when kms is enabled. */
956 if (intel_info->gen != 3) {
957 driver.driver_features &=
958 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
959 } else if (!intel_agp_enabled) {
960 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
961 return -ENODEV;
962 }
963
dcdb1674 964 return drm_get_pci_dev(pdev, ent, &driver);
112b715e
KH		 965}
966
967static void
968i915_pci_remove(struct pci_dev *pdev)
969{
970 struct drm_device *dev = pci_get_drvdata(pdev);
971
972 drm_put_dev(dev);
973}
974
84b79f8d 975static int i915_pm_suspend(struct device *dev)
112b715e 976{
84b79f8d
RW		 977 struct pci_dev *pdev = to_pci_dev(dev);
978 struct drm_device *drm_dev = pci_get_drvdata(pdev);
979 int error;
112b715e 980
84b79f8d
RW		 981 if (!drm_dev || !drm_dev->dev_private) {
982 dev_err(dev, "DRM not initialized, aborting suspend.\n");
983 return -ENODEV;
984 }
112b715e 985
5bcf719b
DA		 986 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
987 return 0;
988
84b79f8d
RW		 989 error = i915_drm_freeze(drm_dev);
990 if (error)
991 return error;
112b715e 992
84b79f8d
RW		 993 pci_disable_device(pdev);
994 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 995
84b79f8d 996 return 0;
cbda12d7
ZW		 997}
998
84b79f8d 999static int i915_pm_resume(struct device *dev)
cbda12d7 1000{
84b79f8d
RW		 1001 struct pci_dev *pdev = to_pci_dev(dev);
1002 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1003
1004 return i915_resume(drm_dev);
cbda12d7
ZW		 1005}
1006
84b79f8d 1007static int i915_pm_freeze(struct device *dev)
cbda12d7 1008{
84b79f8d
RW		 1009 struct pci_dev *pdev = to_pci_dev(dev);
1010 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1011
1012 if (!drm_dev || !drm_dev->dev_private) {
1013 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1014 return -ENODEV;
1015 }
1016
1017 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 1018}
1019
84b79f8d 1020static int i915_pm_thaw(struct device *dev)
cbda12d7 1021{
84b79f8d
RW		 1022 struct pci_dev *pdev = to_pci_dev(dev);
1023 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1024
1025 return i915_drm_thaw(drm_dev);
cbda12d7
ZW		 1026}
1027
84b79f8d 1028static int i915_pm_poweroff(struct device *dev)
cbda12d7 1029{
84b79f8d
RW		 1030 struct pci_dev *pdev = to_pci_dev(dev);
1031 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 1032
61caf87c 1033 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 1034}
1035
b4b78d12 1036static const struct dev_pm_ops i915_pm_ops = {
0206e353
AJ		 1037 .suspend = i915_pm_suspend,
1038 .resume = i915_pm_resume,
1039 .freeze = i915_pm_freeze,
1040 .thaw = i915_pm_thaw,
1041 .poweroff = i915_pm_poweroff,
1042 .restore = i915_pm_resume,
cbda12d7
ZW		 1043};
1044
78b68556 1045static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 1046 .fault = i915_gem_fault,
ab00b3e5
JB		 1047 .open = drm_gem_vm_open,
1048 .close = drm_gem_vm_close,
de151cf6
JB		 1049};
1050
e08e96de
AV		 1051static const struct file_operations i915_driver_fops = {
1052 .owner = THIS_MODULE,
1053 .open = drm_open,
1054 .release = drm_release,
1055 .unlocked_ioctl = drm_ioctl,
1056 .mmap = drm_gem_mmap,
1057 .poll = drm_poll,
1058 .fasync = drm_fasync,
1059 .read = drm_read,
1060#ifdef CONFIG_COMPAT
1061 .compat_ioctl = i915_compat_ioctl,
1062#endif
1063 .llseek = noop_llseek,
1064};
1065
1da177e4 1066static struct drm_driver driver = {
0c54781b
MW		 1067 /* Don't use MTRRs here; the Xserver or userspace app should
1068 * deal with them for Intel hardware.
792d2b9a 1069 */
673a394b
EA		 1070 .driver_features =
1071 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1286ff73 1072 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
22eae947 1073 .load = i915_driver_load,
ba8bbcf6 1074 .unload = i915_driver_unload,
673a394b 1075 .open = i915_driver_open,
22eae947
DA		 1076 .lastclose = i915_driver_lastclose,
1077 .preclose = i915_driver_preclose,
673a394b 1078 .postclose = i915_driver_postclose,
d8e29209
RW		 1079
1080 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1081 .suspend = i915_suspend,
1082 .resume = i915_resume,
1083
cda17380 1084 .device_is_agp = i915_driver_device_is_agp,
7c1c2871
DA		 1085 .master_create = i915_master_create,
1086 .master_destroy = i915_master_destroy,
955b12de 1087#if defined(CONFIG_DEBUG_FS)
27c202ad
BG		 1088 .debugfs_init = i915_debugfs_init,
1089 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 1090#endif
673a394b
EA		 1091 .gem_init_object = i915_gem_init_object,
1092 .gem_free_object = i915_gem_free_object,
de151cf6 1093 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 1094
1095 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1096 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1097 .gem_prime_export = i915_gem_prime_export,
1098 .gem_prime_import = i915_gem_prime_import,
1099
ff72145b
DA		 1100 .dumb_create = i915_gem_dumb_create,
1101 .dumb_map_offset = i915_gem_mmap_gtt,
1102 .dumb_destroy = i915_gem_dumb_destroy,
1da177e4 1103 .ioctls = i915_ioctls,
e08e96de 1104 .fops = &i915_driver_fops,
22eae947
DA		 1105 .name = DRIVER_NAME,
1106 .desc = DRIVER_DESC,
1107 .date = DRIVER_DATE,
1108 .major = DRIVER_MAJOR,
1109 .minor = DRIVER_MINOR,
1110 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 1111};
1112
8410ea3b
DA		 1113static struct pci_driver i915_pci_driver = {
1114 .name = DRIVER_NAME,
1115 .id_table = pciidlist,
1116 .probe = i915_pci_probe,
1117 .remove = i915_pci_remove,
1118 .driver.pm = &i915_pm_ops,
1119};
1120
1da177e4
LT		 1121static int __init i915_init(void)
1122{
1123 driver.num_ioctls = i915_max_ioctl;
79e53945
JB		 1124
1125 /*
1126 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1127 * explicitly disabled with the module pararmeter.
1128 *
1129 * Otherwise, just follow the parameter (defaulting to off).
1130 *
1131 * Allow optional vga_text_mode_force boot option to override
1132 * the default behavior.
1133 */
1134#if defined(CONFIG_DRM_I915_KMS)
1135 if (i915_modeset != 0)
1136 driver.driver_features |= DRIVER_MODESET;
1137#endif
1138 if (i915_modeset == 1)
1139 driver.driver_features |= DRIVER_MODESET;
1140
1141#ifdef CONFIG_VGA_CONSOLE
1142 if (vgacon_text_force() && i915_modeset == -1)
1143 driver.driver_features &= ~DRIVER_MODESET;
1144#endif
1145
3885c6bb
CW		 1146 if (!(driver.driver_features & DRIVER_MODESET))
1147 driver.get_vblank_timestamp = NULL;
1148
8410ea3b 1149 return drm_pci_init(&driver, &i915_pci_driver);
1da177e4
LT		 1150}
1151
1152static void __exit i915_exit(void)
1153{
8410ea3b 1154 drm_pci_exit(&driver, &i915_pci_driver);
1da177e4
LT		 1155}
1156
1157module_init(i915_init);
1158module_exit(i915_exit);
1159
b5e89ed5
DA		 1160MODULE_AUTHOR(DRIVER_AUTHOR);
1161MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 1162MODULE_LICENSE("GPL and additional rights");
f7000883 1163
b7d84096
JB		 1164/* We give fast paths for the really cool registers */
1165#define NEEDS_FORCE_WAKE(dev_priv, reg) \
b7884eb4
DV		 1166 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1167 ((reg) < 0x40000) && \
1168 ((reg) != FORCEWAKE))
a8b1397d
DV		 1169static void
1170ilk_dummy_write(struct drm_i915_private *dev_priv)
1171{
1172 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1173 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1174 * harmless to write 0 into. */
1175 I915_WRITE_NOTRACE(MI_MODE, 0);
1176}
1177
115bc2de
PZ		 1178static void
1179hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1180{
1181 if (IS_HASWELL(dev_priv->dev) &&
3f1e109a 1182 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
115bc2de
PZ		 1183 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1184 reg);
3f1e109a 1185 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
115bc2de
PZ		 1186 }
1187}
1188
1189static void
1190hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1191{
1192 if (IS_HASWELL(dev_priv->dev) &&
3f1e109a 1193 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
115bc2de 1194 DRM_ERROR("Unclaimed write to %x\n", reg);
3f1e109a 1195 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
115bc2de
PZ		 1196 }
1197}
1198
f7000883
AK		 1199#define __i915_read(x, y) \
1200u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1201 u##x val = 0; \
a8b1397d
DV		 1202 if (IS_GEN5(dev_priv->dev)) \
1203 ilk_dummy_write(dev_priv); \
f7000883 1204 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
c937504e
KP		 1205 unsigned long irqflags; \
1206 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1207 if (dev_priv->forcewake_count == 0) \
990bbdad 1208 dev_priv->gt.force_wake_get(dev_priv); \
f7000883 1209 val = read##y(dev_priv->regs + reg); \
c937504e 1210 if (dev_priv->forcewake_count == 0) \
990bbdad 1211 dev_priv->gt.force_wake_put(dev_priv); \
c937504e 1212 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
f7000883
AK		 1213 } else { \
1214 val = read##y(dev_priv->regs + reg); \
1215 } \
1216 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1217 return val; \
1218}
1219
1220__i915_read(8, b)
1221__i915_read(16, w)
1222__i915_read(32, l)
1223__i915_read(64, q)
1224#undef __i915_read
1225
1226#define __i915_write(x, y) \
1227void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
67a3744f 1228 u32 __fifo_ret = 0; \
f7000883
AK		 1229 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1230 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
67a3744f 1231 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
f7000883 1232 } \
a8b1397d
DV		 1233 if (IS_GEN5(dev_priv->dev)) \
1234 ilk_dummy_write(dev_priv); \
115bc2de 1235 hsw_unclaimed_reg_clear(dev_priv, reg); \
fe31b574 1236 write##y(val, dev_priv->regs + reg); \
67a3744f
BW		 1237 if (unlikely(__fifo_ret)) { \
1238 gen6_gt_check_fifodbg(dev_priv); \
1239 } \
115bc2de 1240 hsw_unclaimed_reg_check(dev_priv, reg); \
f7000883
AK		 1241}
1242__i915_write(8, b)
1243__i915_write(16, w)
1244__i915_write(32, l)
1245__i915_write(64, q)
1246#undef __i915_write
c0c7babc
BW		 1247
1248static const struct register_whitelist {
1249 uint64_t offset;
1250 uint32_t size;
1251 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1252} whitelist[] = {
1253 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1254};
1255
1256int i915_reg_read_ioctl(struct drm_device *dev,
1257 void *data, struct drm_file *file)
1258{
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 struct drm_i915_reg_read *reg = data;
1261 struct register_whitelist const *entry = whitelist;
1262 int i;
1263
1264 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1265 if (entry->offset == reg->offset &&
1266 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1267 break;
1268 }
1269
1270 if (i == ARRAY_SIZE(whitelist))
1271 return -EINVAL;
1272
1273 switch (entry->size) {
1274 case 8:
1275 reg->val = I915_READ64(reg->offset);
1276 break;
1277 case 4:
1278 reg->val = I915_READ(reg->offset);
1279 break;
1280 case 2:
1281 reg->val = I915_READ16(reg->offset);
1282 break;
1283 case 1:
1284 reg->val = I915_READ8(reg->offset);
1285 break;
1286 default:
1287 WARN_ON(1);
1288 return -EINVAL;
1289 }
1290
1291 return 0;
1292}
ubuntu-zesty-kernel mirror