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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
e5747e3a | 30 | #include <linux/acpi.h> |
0673ad47 CW |
31 | #include <linux/device.h> |
32 | #include <linux/oom.h> | |
e0cd3608 | 33 | #include <linux/module.h> |
0673ad47 CW |
34 | #include <linux/pci.h> |
35 | #include <linux/pm.h> | |
d6102977 | 36 | #include <linux/pm_runtime.h> |
0673ad47 CW |
37 | #include <linux/pnp.h> |
38 | #include <linux/slab.h> | |
39 | #include <linux/vgaarb.h> | |
704ab614 | 40 | #include <linux/vga_switcheroo.h> |
0673ad47 CW |
41 | #include <linux/vt.h> |
42 | #include <acpi/video.h> | |
43 | ||
44 | #include <drm/drmP.h> | |
760285e7 | 45 | #include <drm/drm_crtc_helper.h> |
a667fb40 | 46 | #include <drm/drm_atomic_helper.h> |
0673ad47 CW |
47 | #include <drm/i915_drm.h> |
48 | ||
49 | #include "i915_drv.h" | |
50 | #include "i915_trace.h" | |
51 | #include "i915_vgpu.h" | |
52 | #include "intel_drv.h" | |
5464cd65 | 53 | #include "intel_uc.h" |
79e53945 | 54 | |
112b715e KH |
55 | static struct drm_driver driver; |
56 | ||
0673ad47 CW |
57 | static unsigned int i915_load_fail_count; |
58 | ||
59 | bool __i915_inject_load_failure(const char *func, int line) | |
60 | { | |
4f044a88 | 61 | if (i915_load_fail_count >= i915_modparams.inject_load_failure) |
0673ad47 CW |
62 | return false; |
63 | ||
4f044a88 | 64 | if (++i915_load_fail_count == i915_modparams.inject_load_failure) { |
0673ad47 | 65 | DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n", |
4f044a88 | 66 | i915_modparams.inject_load_failure, func, line); |
0673ad47 CW |
67 | return true; |
68 | } | |
69 | ||
70 | return false; | |
71 | } | |
72 | ||
73 | #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI" | |
74 | #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \ | |
75 | "providing the dmesg log by booting with drm.debug=0xf" | |
76 | ||
77 | void | |
78 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
79 | const char *fmt, ...) | |
80 | { | |
81 | static bool shown_bug_once; | |
c49d13ee | 82 | struct device *kdev = dev_priv->drm.dev; |
0673ad47 CW |
83 | bool is_error = level[1] <= KERN_ERR[1]; |
84 | bool is_debug = level[1] == KERN_DEBUG[1]; | |
85 | struct va_format vaf; | |
86 | va_list args; | |
87 | ||
88 | if (is_debug && !(drm_debug & DRM_UT_DRIVER)) | |
89 | return; | |
90 | ||
91 | va_start(args, fmt); | |
92 | ||
93 | vaf.fmt = fmt; | |
94 | vaf.va = &args; | |
95 | ||
c49d13ee | 96 | dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV", |
0673ad47 CW |
97 | __builtin_return_address(0), &vaf); |
98 | ||
99 | if (is_error && !shown_bug_once) { | |
c49d13ee | 100 | dev_notice(kdev, "%s", FDO_BUG_MSG); |
0673ad47 CW |
101 | shown_bug_once = true; |
102 | } | |
103 | ||
104 | va_end(args); | |
105 | } | |
106 | ||
107 | static bool i915_error_injected(struct drm_i915_private *dev_priv) | |
108 | { | |
4f044a88 MW |
109 | return i915_modparams.inject_load_failure && |
110 | i915_load_fail_count == i915_modparams.inject_load_failure; | |
0673ad47 CW |
111 | } |
112 | ||
113 | #define i915_load_error(dev_priv, fmt, ...) \ | |
114 | __i915_printk(dev_priv, \ | |
115 | i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \ | |
116 | fmt, ##__VA_ARGS__) | |
117 | ||
118 | ||
fd6b8f43 | 119 | static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv) |
0673ad47 CW |
120 | { |
121 | enum intel_pch ret = PCH_NOP; | |
122 | ||
123 | /* | |
124 | * In a virtualized passthrough environment we can be in a | |
125 | * setup where the ISA bridge is not able to be passed through. | |
126 | * In this case, a south bridge can be emulated and we have to | |
127 | * make an educated guess as to which PCH is really there. | |
128 | */ | |
129 | ||
fd6b8f43 | 130 | if (IS_GEN5(dev_priv)) { |
0673ad47 CW |
131 | ret = PCH_IBX; |
132 | DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); | |
fd6b8f43 | 133 | } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) { |
0673ad47 | 134 | ret = PCH_CPT; |
aa032130 | 135 | DRM_DEBUG_KMS("Assuming CougarPoint PCH\n"); |
fd6b8f43 | 136 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
0673ad47 | 137 | ret = PCH_LPT; |
817aef5d XZ |
138 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
139 | dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
140 | else | |
141 | dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE; | |
0673ad47 | 142 | DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); |
fd6b8f43 | 143 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
0673ad47 CW |
144 | ret = PCH_SPT; |
145 | DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); | |
80937819 | 146 | } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
acf1dba6 | 147 | ret = PCH_CNP; |
80937819 | 148 | DRM_DEBUG_KMS("Assuming CannonPoint PCH\n"); |
0673ad47 CW |
149 | } |
150 | ||
151 | return ret; | |
152 | } | |
153 | ||
da5f53bf | 154 | static void intel_detect_pch(struct drm_i915_private *dev_priv) |
0673ad47 | 155 | { |
0673ad47 CW |
156 | struct pci_dev *pch = NULL; |
157 | ||
158 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting | |
159 | * (which really amounts to a PCH but no South Display). | |
160 | */ | |
b7f05d4a | 161 | if (INTEL_INFO(dev_priv)->num_pipes == 0) { |
0673ad47 CW |
162 | dev_priv->pch_type = PCH_NOP; |
163 | return; | |
164 | } | |
165 | ||
166 | /* | |
167 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
168 | * make graphics device passthrough work easy for VMM, that only | |
169 | * need to expose ISA bridge to let driver know the real hardware | |
170 | * underneath. This is a requirement from virtualization team. | |
171 | * | |
172 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
173 | * ISA bridge in the system. To work reliably, we should scan trhough | |
174 | * all the ISA bridge devices and check for the first match, instead | |
175 | * of only checking the first one. | |
176 | */ | |
177 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { | |
178 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
179 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
c5e855d0 VS |
180 | |
181 | dev_priv->pch_id = id; | |
ec7e0bb3 | 182 | |
0673ad47 CW |
183 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
184 | dev_priv->pch_type = PCH_IBX; | |
185 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
5db94019 | 186 | WARN_ON(!IS_GEN5(dev_priv)); |
0673ad47 CW |
187 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
188 | dev_priv->pch_type = PCH_CPT; | |
189 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
d4cdbf03 VS |
190 | WARN_ON(!IS_GEN6(dev_priv) && |
191 | !IS_IVYBRIDGE(dev_priv)); | |
0673ad47 CW |
192 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
193 | /* PantherPoint is CPT compatible */ | |
194 | dev_priv->pch_type = PCH_CPT; | |
195 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); | |
d4cdbf03 VS |
196 | WARN_ON(!IS_GEN6(dev_priv) && |
197 | !IS_IVYBRIDGE(dev_priv)); | |
0673ad47 CW |
198 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
199 | dev_priv->pch_type = PCH_LPT; | |
200 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
8652744b TU |
201 | WARN_ON(!IS_HASWELL(dev_priv) && |
202 | !IS_BROADWELL(dev_priv)); | |
50a0bc90 TU |
203 | WARN_ON(IS_HSW_ULT(dev_priv) || |
204 | IS_BDW_ULT(dev_priv)); | |
0673ad47 CW |
205 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
206 | dev_priv->pch_type = PCH_LPT; | |
207 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
8652744b TU |
208 | WARN_ON(!IS_HASWELL(dev_priv) && |
209 | !IS_BROADWELL(dev_priv)); | |
50a0bc90 TU |
210 | WARN_ON(!IS_HSW_ULT(dev_priv) && |
211 | !IS_BDW_ULT(dev_priv)); | |
c5e855d0 VS |
212 | } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) { |
213 | /* WildcatPoint is LPT compatible */ | |
214 | dev_priv->pch_type = PCH_LPT; | |
215 | DRM_DEBUG_KMS("Found WildcatPoint PCH\n"); | |
216 | WARN_ON(!IS_HASWELL(dev_priv) && | |
217 | !IS_BROADWELL(dev_priv)); | |
218 | WARN_ON(IS_HSW_ULT(dev_priv) || | |
219 | IS_BDW_ULT(dev_priv)); | |
220 | } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) { | |
221 | /* WildcatPoint is LPT compatible */ | |
222 | dev_priv->pch_type = PCH_LPT; | |
223 | DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n"); | |
224 | WARN_ON(!IS_HASWELL(dev_priv) && | |
225 | !IS_BROADWELL(dev_priv)); | |
226 | WARN_ON(!IS_HSW_ULT(dev_priv) && | |
227 | !IS_BDW_ULT(dev_priv)); | |
0673ad47 CW |
228 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
229 | dev_priv->pch_type = PCH_SPT; | |
230 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
0853723b TU |
231 | WARN_ON(!IS_SKYLAKE(dev_priv) && |
232 | !IS_KABYLAKE(dev_priv)); | |
c5e855d0 | 233 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
0673ad47 CW |
234 | dev_priv->pch_type = PCH_SPT; |
235 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
0853723b TU |
236 | WARN_ON(!IS_SKYLAKE(dev_priv) && |
237 | !IS_KABYLAKE(dev_priv)); | |
22dea0be RV |
238 | } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) { |
239 | dev_priv->pch_type = PCH_KBP; | |
23247d71 | 240 | DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n"); |
85327748 | 241 | WARN_ON(!IS_SKYLAKE(dev_priv) && |
eb371933 RV |
242 | !IS_KABYLAKE(dev_priv) && |
243 | !IS_COFFEELAKE(dev_priv)); | |
7b22b8c4 RV |
244 | } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) { |
245 | dev_priv->pch_type = PCH_CNP; | |
23247d71 | 246 | DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n"); |
80937819 RV |
247 | WARN_ON(!IS_CANNONLAKE(dev_priv) && |
248 | !IS_COFFEELAKE(dev_priv)); | |
c5e855d0 | 249 | } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) { |
ec7e0bb3 | 250 | dev_priv->pch_type = PCH_CNP; |
23247d71 | 251 | DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n"); |
80937819 RV |
252 | WARN_ON(!IS_CANNONLAKE(dev_priv) && |
253 | !IS_COFFEELAKE(dev_priv)); | |
d4cdbf03 VS |
254 | } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE || |
255 | id == INTEL_PCH_P3X_DEVICE_ID_TYPE || | |
256 | (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE && | |
0673ad47 CW |
257 | pch->subsystem_vendor == |
258 | PCI_SUBVENDOR_ID_REDHAT_QUMRANET && | |
259 | pch->subsystem_device == | |
260 | PCI_SUBDEVICE_ID_QEMU)) { | |
fd6b8f43 TU |
261 | dev_priv->pch_type = |
262 | intel_virt_detect_pch(dev_priv); | |
0673ad47 CW |
263 | } else |
264 | continue; | |
265 | ||
266 | break; | |
267 | } | |
268 | } | |
269 | if (!pch) | |
270 | DRM_DEBUG_KMS("No PCH found.\n"); | |
271 | ||
272 | pci_dev_put(pch); | |
273 | } | |
274 | ||
0673ad47 CW |
275 | static int i915_getparam(struct drm_device *dev, void *data, |
276 | struct drm_file *file_priv) | |
277 | { | |
fac5e23e | 278 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 279 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
280 | drm_i915_getparam_t *param = data; |
281 | int value; | |
282 | ||
283 | switch (param->param) { | |
284 | case I915_PARAM_IRQ_ACTIVE: | |
285 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
286 | case I915_PARAM_LAST_DISPATCH: | |
ef0f411f | 287 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
0673ad47 CW |
288 | /* Reject all old ums/dri params. */ |
289 | return -ENODEV; | |
290 | case I915_PARAM_CHIPSET_ID: | |
52a05c30 | 291 | value = pdev->device; |
0673ad47 CW |
292 | break; |
293 | case I915_PARAM_REVISION: | |
52a05c30 | 294 | value = pdev->revision; |
0673ad47 | 295 | break; |
0673ad47 CW |
296 | case I915_PARAM_NUM_FENCES_AVAIL: |
297 | value = dev_priv->num_fence_regs; | |
298 | break; | |
299 | case I915_PARAM_HAS_OVERLAY: | |
300 | value = dev_priv->overlay ? 1 : 0; | |
301 | break; | |
0673ad47 | 302 | case I915_PARAM_HAS_BSD: |
3b3f1650 | 303 | value = !!dev_priv->engine[VCS]; |
0673ad47 CW |
304 | break; |
305 | case I915_PARAM_HAS_BLT: | |
3b3f1650 | 306 | value = !!dev_priv->engine[BCS]; |
0673ad47 CW |
307 | break; |
308 | case I915_PARAM_HAS_VEBOX: | |
3b3f1650 | 309 | value = !!dev_priv->engine[VECS]; |
0673ad47 CW |
310 | break; |
311 | case I915_PARAM_HAS_BSD2: | |
3b3f1650 | 312 | value = !!dev_priv->engine[VCS2]; |
0673ad47 | 313 | break; |
0673ad47 | 314 | case I915_PARAM_HAS_LLC: |
16162470 | 315 | value = HAS_LLC(dev_priv); |
0673ad47 CW |
316 | break; |
317 | case I915_PARAM_HAS_WT: | |
16162470 | 318 | value = HAS_WT(dev_priv); |
0673ad47 CW |
319 | break; |
320 | case I915_PARAM_HAS_ALIASING_PPGTT: | |
16162470 | 321 | value = USES_PPGTT(dev_priv); |
0673ad47 CW |
322 | break; |
323 | case I915_PARAM_HAS_SEMAPHORES: | |
4f044a88 | 324 | value = i915_modparams.semaphores; |
0673ad47 | 325 | break; |
0673ad47 CW |
326 | case I915_PARAM_HAS_SECURE_BATCHES: |
327 | value = capable(CAP_SYS_ADMIN); | |
328 | break; | |
0673ad47 CW |
329 | case I915_PARAM_CMD_PARSER_VERSION: |
330 | value = i915_cmd_parser_get_version(dev_priv); | |
331 | break; | |
0673ad47 | 332 | case I915_PARAM_SUBSLICE_TOTAL: |
57ec171e | 333 | value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu); |
0673ad47 CW |
334 | if (!value) |
335 | return -ENODEV; | |
336 | break; | |
337 | case I915_PARAM_EU_TOTAL: | |
43b67998 | 338 | value = INTEL_INFO(dev_priv)->sseu.eu_total; |
0673ad47 CW |
339 | if (!value) |
340 | return -ENODEV; | |
341 | break; | |
342 | case I915_PARAM_HAS_GPU_RESET: | |
4f044a88 MW |
343 | value = i915_modparams.enable_hangcheck && |
344 | intel_has_gpu_reset(dev_priv); | |
142bc7d9 MT |
345 | if (value && intel_has_reset_engine(dev_priv)) |
346 | value = 2; | |
0673ad47 CW |
347 | break; |
348 | case I915_PARAM_HAS_RESOURCE_STREAMER: | |
16162470 | 349 | value = HAS_RESOURCE_STREAMER(dev_priv); |
0673ad47 | 350 | break; |
37f501af | 351 | case I915_PARAM_HAS_POOLED_EU: |
16162470 | 352 | value = HAS_POOLED_EU(dev_priv); |
37f501af | 353 | break; |
354 | case I915_PARAM_MIN_EU_IN_POOL: | |
43b67998 | 355 | value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool; |
37f501af | 356 | break; |
5464cd65 | 357 | case I915_PARAM_HUC_STATUS: |
3582ad13 | 358 | intel_runtime_pm_get(dev_priv); |
5464cd65 | 359 | value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED; |
3582ad13 | 360 | intel_runtime_pm_put(dev_priv); |
5464cd65 | 361 | break; |
4cc69075 CW |
362 | case I915_PARAM_MMAP_GTT_VERSION: |
363 | /* Though we've started our numbering from 1, and so class all | |
364 | * earlier versions as 0, in effect their value is undefined as | |
365 | * the ioctl will report EINVAL for the unknown param! | |
366 | */ | |
367 | value = i915_gem_mmap_gtt_version(); | |
368 | break; | |
0de9136d | 369 | case I915_PARAM_HAS_SCHEDULER: |
bf64e0b0 | 370 | value = 0; |
beecec90 | 371 | if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) { |
bf64e0b0 | 372 | value |= I915_SCHEDULER_CAP_ENABLED; |
ac14fbd4 | 373 | value |= I915_SCHEDULER_CAP_PRIORITY; |
beecec90 | 374 | |
a4598d17 | 375 | if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) && |
c41937fd | 376 | i915_modparams.enable_execlists) |
beecec90 CW |
377 | value |= I915_SCHEDULER_CAP_PREEMPTION; |
378 | } | |
0de9136d | 379 | break; |
beecec90 | 380 | |
16162470 DW |
381 | case I915_PARAM_MMAP_VERSION: |
382 | /* Remember to bump this if the version changes! */ | |
383 | case I915_PARAM_HAS_GEM: | |
384 | case I915_PARAM_HAS_PAGEFLIPPING: | |
385 | case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */ | |
386 | case I915_PARAM_HAS_RELAXED_FENCING: | |
387 | case I915_PARAM_HAS_COHERENT_RINGS: | |
388 | case I915_PARAM_HAS_RELAXED_DELTA: | |
389 | case I915_PARAM_HAS_GEN7_SOL_RESET: | |
390 | case I915_PARAM_HAS_WAIT_TIMEOUT: | |
391 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: | |
392 | case I915_PARAM_HAS_PINNED_BATCHES: | |
393 | case I915_PARAM_HAS_EXEC_NO_RELOC: | |
394 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: | |
395 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: | |
396 | case I915_PARAM_HAS_EXEC_SOFTPIN: | |
77ae9957 | 397 | case I915_PARAM_HAS_EXEC_ASYNC: |
fec0445c | 398 | case I915_PARAM_HAS_EXEC_FENCE: |
b0fd47ad | 399 | case I915_PARAM_HAS_EXEC_CAPTURE: |
1a71cf2f | 400 | case I915_PARAM_HAS_EXEC_BATCH_FIRST: |
cf6e7bac | 401 | case I915_PARAM_HAS_EXEC_FENCE_ARRAY: |
16162470 DW |
402 | /* For the time being all of these are always true; |
403 | * if some supported hardware does not have one of these | |
404 | * features this value needs to be provided from | |
405 | * INTEL_INFO(), a feature macro, or similar. | |
406 | */ | |
407 | value = 1; | |
408 | break; | |
d2b4b979 CW |
409 | case I915_PARAM_HAS_CONTEXT_ISOLATION: |
410 | value = intel_engines_has_context_isolation(dev_priv); | |
411 | break; | |
7fed555c RB |
412 | case I915_PARAM_SLICE_MASK: |
413 | value = INTEL_INFO(dev_priv)->sseu.slice_mask; | |
414 | if (!value) | |
415 | return -ENODEV; | |
416 | break; | |
f5320233 RB |
417 | case I915_PARAM_SUBSLICE_MASK: |
418 | value = INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
419 | if (!value) | |
420 | return -ENODEV; | |
421 | break; | |
dab91783 | 422 | case I915_PARAM_CS_TIMESTAMP_FREQUENCY: |
f577a03b | 423 | value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz; |
dab91783 | 424 | break; |
0673ad47 CW |
425 | default: |
426 | DRM_DEBUG("Unknown parameter %d\n", param->param); | |
427 | return -EINVAL; | |
428 | } | |
429 | ||
dda33009 | 430 | if (put_user(value, param->value)) |
0673ad47 | 431 | return -EFAULT; |
0673ad47 CW |
432 | |
433 | return 0; | |
434 | } | |
435 | ||
da5f53bf | 436 | static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) |
0673ad47 | 437 | { |
0673ad47 CW |
438 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
439 | if (!dev_priv->bridge_dev) { | |
440 | DRM_ERROR("bridge device not found\n"); | |
441 | return -1; | |
442 | } | |
443 | return 0; | |
444 | } | |
445 | ||
446 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
447 | static int | |
da5f53bf | 448 | intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) |
0673ad47 | 449 | { |
514e1d64 | 450 | int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
451 | u32 temp_lo, temp_hi = 0; |
452 | u64 mchbar_addr; | |
453 | int ret; | |
454 | ||
514e1d64 | 455 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
456 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
457 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
458 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
459 | ||
460 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
461 | #ifdef CONFIG_PNP | |
462 | if (mchbar_addr && | |
463 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) | |
464 | return 0; | |
465 | #endif | |
466 | ||
467 | /* Get some space for it */ | |
468 | dev_priv->mch_res.name = "i915 MCHBAR"; | |
469 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
470 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
471 | &dev_priv->mch_res, | |
472 | MCHBAR_SIZE, MCHBAR_SIZE, | |
473 | PCIBIOS_MIN_MEM, | |
474 | 0, pcibios_align_resource, | |
475 | dev_priv->bridge_dev); | |
476 | if (ret) { | |
477 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
478 | dev_priv->mch_res.start = 0; | |
479 | return ret; | |
480 | } | |
481 | ||
514e1d64 | 482 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
483 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
484 | upper_32_bits(dev_priv->mch_res.start)); | |
485 | ||
486 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
487 | lower_32_bits(dev_priv->mch_res.start)); | |
488 | return 0; | |
489 | } | |
490 | ||
491 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
492 | static void | |
da5f53bf | 493 | intel_setup_mchbar(struct drm_i915_private *dev_priv) |
0673ad47 | 494 | { |
514e1d64 | 495 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
496 | u32 temp; |
497 | bool enabled; | |
498 | ||
920a14b2 | 499 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
0673ad47 CW |
500 | return; |
501 | ||
502 | dev_priv->mchbar_need_disable = false; | |
503 | ||
50a0bc90 | 504 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
505 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); |
506 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
507 | } else { | |
508 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
509 | enabled = temp & 1; | |
510 | } | |
511 | ||
512 | /* If it's already enabled, don't have to do anything */ | |
513 | if (enabled) | |
514 | return; | |
515 | ||
da5f53bf | 516 | if (intel_alloc_mchbar_resource(dev_priv)) |
0673ad47 CW |
517 | return; |
518 | ||
519 | dev_priv->mchbar_need_disable = true; | |
520 | ||
521 | /* Space is allocated or reserved, so enable it. */ | |
50a0bc90 | 522 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
523 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, |
524 | temp | DEVEN_MCHBAR_EN); | |
525 | } else { | |
526 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
527 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
528 | } | |
529 | } | |
530 | ||
531 | static void | |
da5f53bf | 532 | intel_teardown_mchbar(struct drm_i915_private *dev_priv) |
0673ad47 | 533 | { |
514e1d64 | 534 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
535 | |
536 | if (dev_priv->mchbar_need_disable) { | |
50a0bc90 | 537 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
538 | u32 deven_val; |
539 | ||
540 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, | |
541 | &deven_val); | |
542 | deven_val &= ~DEVEN_MCHBAR_EN; | |
543 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, | |
544 | deven_val); | |
545 | } else { | |
546 | u32 mchbar_val; | |
547 | ||
548 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
549 | &mchbar_val); | |
550 | mchbar_val &= ~1; | |
551 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
552 | mchbar_val); | |
553 | } | |
554 | } | |
555 | ||
556 | if (dev_priv->mch_res.start) | |
557 | release_resource(&dev_priv->mch_res); | |
558 | } | |
559 | ||
560 | /* true = enable decode, false = disable decoder */ | |
561 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
562 | { | |
da5f53bf | 563 | struct drm_i915_private *dev_priv = cookie; |
0673ad47 | 564 | |
da5f53bf | 565 | intel_modeset_vga_set_state(dev_priv, state); |
0673ad47 CW |
566 | if (state) |
567 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
568 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
569 | else | |
570 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
571 | } | |
572 | ||
7f26cb88 TU |
573 | static int i915_resume_switcheroo(struct drm_device *dev); |
574 | static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); | |
575 | ||
0673ad47 CW |
576 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
577 | { | |
578 | struct drm_device *dev = pci_get_drvdata(pdev); | |
579 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
580 | ||
581 | if (state == VGA_SWITCHEROO_ON) { | |
582 | pr_info("switched on\n"); | |
583 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
584 | /* i915 resume handler doesn't set to D0 */ | |
52a05c30 | 585 | pci_set_power_state(pdev, PCI_D0); |
0673ad47 CW |
586 | i915_resume_switcheroo(dev); |
587 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
588 | } else { | |
589 | pr_info("switched off\n"); | |
590 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
591 | i915_suspend_switcheroo(dev, pmm); | |
592 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; | |
593 | } | |
594 | } | |
595 | ||
596 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
597 | { | |
598 | struct drm_device *dev = pci_get_drvdata(pdev); | |
599 | ||
600 | /* | |
601 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
602 | * locking inversion with the driver load path. And the access here is | |
603 | * completely racy anyway. So don't bother with locking for now. | |
604 | */ | |
605 | return dev->open_count == 0; | |
606 | } | |
607 | ||
608 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { | |
609 | .set_gpu_state = i915_switcheroo_set_state, | |
610 | .reprobe = NULL, | |
611 | .can_switch = i915_switcheroo_can_switch, | |
612 | }; | |
613 | ||
fbbd37b3 | 614 | static void i915_gem_fini(struct drm_i915_private *dev_priv) |
0673ad47 | 615 | { |
3b19f16a CW |
616 | /* Flush any outstanding unpin_work. */ |
617 | i915_gem_drain_workqueue(dev_priv); | |
5f09a9c8 | 618 | |
fbbd37b3 | 619 | mutex_lock(&dev_priv->drm.struct_mutex); |
b8991403 | 620 | intel_uc_fini_hw(dev_priv); |
cb15d9f8 | 621 | i915_gem_cleanup_engines(dev_priv); |
829a0af2 | 622 | i915_gem_contexts_fini(dev_priv); |
fbbd37b3 | 623 | mutex_unlock(&dev_priv->drm.struct_mutex); |
0673ad47 | 624 | |
7c781423 CW |
625 | i915_gem_cleanup_userptr(dev_priv); |
626 | ||
bdeb9785 | 627 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 | 628 | |
829a0af2 | 629 | WARN_ON(!list_empty(&dev_priv->contexts.list)); |
0673ad47 CW |
630 | } |
631 | ||
632 | static int i915_load_modeset_init(struct drm_device *dev) | |
633 | { | |
fac5e23e | 634 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 635 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
636 | int ret; |
637 | ||
638 | if (i915_inject_load_failure()) | |
639 | return -ENODEV; | |
640 | ||
66578857 | 641 | intel_bios_init(dev_priv); |
0673ad47 CW |
642 | |
643 | /* If we have > 1 VGA cards, then we need to arbitrate access | |
644 | * to the common VGA resources. | |
645 | * | |
646 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
647 | * then we do not take part in VGA arbitration and the | |
648 | * vga_client_register() fails with -ENODEV. | |
649 | */ | |
da5f53bf | 650 | ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode); |
0673ad47 CW |
651 | if (ret && ret != -ENODEV) |
652 | goto out; | |
653 | ||
654 | intel_register_dsm_handler(); | |
655 | ||
52a05c30 | 656 | ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false); |
0673ad47 CW |
657 | if (ret) |
658 | goto cleanup_vga_client; | |
659 | ||
660 | /* must happen before intel_power_domains_init_hw() on VLV/CHV */ | |
661 | intel_update_rawclk(dev_priv); | |
662 | ||
663 | intel_power_domains_init_hw(dev_priv, false); | |
664 | ||
665 | intel_csr_ucode_init(dev_priv); | |
666 | ||
667 | ret = intel_irq_install(dev_priv); | |
668 | if (ret) | |
669 | goto cleanup_csr; | |
670 | ||
40196446 | 671 | intel_setup_gmbus(dev_priv); |
0673ad47 CW |
672 | |
673 | /* Important: The output setup functions called by modeset_init need | |
674 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b079bd17 VS |
675 | ret = intel_modeset_init(dev); |
676 | if (ret) | |
677 | goto cleanup_irq; | |
0673ad47 | 678 | |
29ad6a30 | 679 | intel_uc_init_fw(dev_priv); |
0673ad47 | 680 | |
bf9e8429 | 681 | ret = i915_gem_init(dev_priv); |
0673ad47 | 682 | if (ret) |
3950bf3d | 683 | goto cleanup_uc; |
0673ad47 | 684 | |
d378a3ef | 685 | intel_setup_overlay(dev_priv); |
0673ad47 | 686 | |
b7f05d4a | 687 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
0673ad47 CW |
688 | return 0; |
689 | ||
690 | ret = intel_fbdev_init(dev); | |
691 | if (ret) | |
692 | goto cleanup_gem; | |
693 | ||
694 | /* Only enable hotplug handling once the fbdev is fully set up. */ | |
695 | intel_hpd_init(dev_priv); | |
696 | ||
697 | drm_kms_helper_poll_init(dev); | |
698 | ||
699 | return 0; | |
700 | ||
701 | cleanup_gem: | |
bf9e8429 | 702 | if (i915_gem_suspend(dev_priv)) |
1c777c5d | 703 | DRM_ERROR("failed to idle hardware; continuing to unload!\n"); |
fbbd37b3 | 704 | i915_gem_fini(dev_priv); |
3950bf3d OM |
705 | cleanup_uc: |
706 | intel_uc_fini_fw(dev_priv); | |
0673ad47 | 707 | cleanup_irq: |
0673ad47 | 708 | drm_irq_uninstall(dev); |
40196446 | 709 | intel_teardown_gmbus(dev_priv); |
0673ad47 CW |
710 | cleanup_csr: |
711 | intel_csr_ucode_fini(dev_priv); | |
712 | intel_power_domains_fini(dev_priv); | |
52a05c30 | 713 | vga_switcheroo_unregister_client(pdev); |
0673ad47 | 714 | cleanup_vga_client: |
52a05c30 | 715 | vga_client_register(pdev, NULL, NULL, NULL); |
0673ad47 CW |
716 | out: |
717 | return ret; | |
718 | } | |
719 | ||
0673ad47 CW |
720 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
721 | { | |
722 | struct apertures_struct *ap; | |
91c8a326 | 723 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
724 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
725 | bool primary; | |
726 | int ret; | |
727 | ||
728 | ap = alloc_apertures(1); | |
729 | if (!ap) | |
730 | return -ENOMEM; | |
731 | ||
732 | ap->ranges[0].base = ggtt->mappable_base; | |
733 | ap->ranges[0].size = ggtt->mappable_end; | |
734 | ||
735 | primary = | |
736 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
737 | ||
44adece5 | 738 | ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
0673ad47 CW |
739 | |
740 | kfree(ap); | |
741 | ||
742 | return ret; | |
743 | } | |
0673ad47 CW |
744 | |
745 | #if !defined(CONFIG_VGA_CONSOLE) | |
746 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
747 | { | |
748 | return 0; | |
749 | } | |
750 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
751 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
752 | { | |
753 | return -ENODEV; | |
754 | } | |
755 | #else | |
756 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
757 | { | |
758 | int ret = 0; | |
759 | ||
760 | DRM_INFO("Replacing VGA console driver\n"); | |
761 | ||
762 | console_lock(); | |
763 | if (con_is_bound(&vga_con)) | |
764 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
765 | if (ret == 0) { | |
766 | ret = do_unregister_con_driver(&vga_con); | |
767 | ||
768 | /* Ignore "already unregistered". */ | |
769 | if (ret == -ENODEV) | |
770 | ret = 0; | |
771 | } | |
772 | console_unlock(); | |
773 | ||
774 | return ret; | |
775 | } | |
776 | #endif | |
777 | ||
0673ad47 CW |
778 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
779 | { | |
780 | /* | |
781 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
782 | * CHV x1 PHY (DP/HDMI D) | |
783 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
784 | */ | |
785 | if (IS_CHERRYVIEW(dev_priv)) { | |
786 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
787 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
788 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
789 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
790 | } | |
791 | } | |
792 | ||
793 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) | |
794 | { | |
795 | /* | |
796 | * The i915 workqueue is primarily used for batched retirement of | |
797 | * requests (and thus managing bo) once the task has been completed | |
798 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
799 | * need high-priority retirement, such as waiting for an explicit | |
800 | * bo. | |
801 | * | |
802 | * It is also used for periodic low-priority events, such as | |
803 | * idle-timers and recording error state. | |
804 | * | |
805 | * All tasks on the workqueue are expected to acquire the dev mutex | |
806 | * so there is no point in running more than one instance of the | |
807 | * workqueue at any time. Use an ordered one. | |
808 | */ | |
809 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); | |
810 | if (dev_priv->wq == NULL) | |
811 | goto out_err; | |
812 | ||
813 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); | |
814 | if (dev_priv->hotplug.dp_wq == NULL) | |
815 | goto out_free_wq; | |
816 | ||
0673ad47 CW |
817 | return 0; |
818 | ||
0673ad47 CW |
819 | out_free_wq: |
820 | destroy_workqueue(dev_priv->wq); | |
821 | out_err: | |
822 | DRM_ERROR("Failed to allocate workqueues.\n"); | |
823 | ||
824 | return -ENOMEM; | |
825 | } | |
826 | ||
bb8f0f5a CW |
827 | static void i915_engines_cleanup(struct drm_i915_private *i915) |
828 | { | |
829 | struct intel_engine_cs *engine; | |
830 | enum intel_engine_id id; | |
831 | ||
832 | for_each_engine(engine, i915, id) | |
833 | kfree(engine); | |
834 | } | |
835 | ||
0673ad47 CW |
836 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) |
837 | { | |
0673ad47 CW |
838 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
839 | destroy_workqueue(dev_priv->wq); | |
840 | } | |
841 | ||
4fc7e845 PZ |
842 | /* |
843 | * We don't keep the workarounds for pre-production hardware, so we expect our | |
844 | * driver to fail on these machines in one way or another. A little warning on | |
845 | * dmesg may help both the user and the bug triagers. | |
846 | */ | |
847 | static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) | |
848 | { | |
248a124d CW |
849 | bool pre = false; |
850 | ||
851 | pre |= IS_HSW_EARLY_SDV(dev_priv); | |
852 | pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0); | |
0102ba1f | 853 | pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST); |
248a124d | 854 | |
7c5ff4a2 | 855 | if (pre) { |
4fc7e845 PZ |
856 | DRM_ERROR("This is a pre-production stepping. " |
857 | "It may not be fully functional.\n"); | |
7c5ff4a2 CW |
858 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); |
859 | } | |
4fc7e845 PZ |
860 | } |
861 | ||
0673ad47 CW |
862 | /** |
863 | * i915_driver_init_early - setup state not requiring device access | |
864 | * @dev_priv: device private | |
865 | * | |
866 | * Initialize everything that is a "SW-only" state, that is state not | |
867 | * requiring accessing the device or exposing the driver via kernel internal | |
868 | * or userspace interfaces. Example steps belonging here: lock initialization, | |
869 | * system memory allocation, setting up device specific attributes and | |
870 | * function hooks not requiring accessing the device. | |
871 | */ | |
872 | static int i915_driver_init_early(struct drm_i915_private *dev_priv, | |
873 | const struct pci_device_id *ent) | |
874 | { | |
875 | const struct intel_device_info *match_info = | |
876 | (struct intel_device_info *)ent->driver_data; | |
877 | struct intel_device_info *device_info; | |
878 | int ret = 0; | |
879 | ||
880 | if (i915_inject_load_failure()) | |
881 | return -ENODEV; | |
882 | ||
883 | /* Setup the write-once "constant" device info */ | |
94b4f3ba | 884 | device_info = mkwrite_device_info(dev_priv); |
0673ad47 CW |
885 | memcpy(device_info, match_info, sizeof(*device_info)); |
886 | device_info->device_id = dev_priv->drm.pdev->device; | |
887 | ||
ae7617f0 TU |
888 | BUILD_BUG_ON(INTEL_MAX_PLATFORMS > |
889 | sizeof(device_info->platform_mask) * BITS_PER_BYTE); | |
890 | device_info->platform_mask = BIT(device_info->platform); | |
891 | ||
0673ad47 CW |
892 | BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE); |
893 | device_info->gen_mask = BIT(device_info->gen - 1); | |
894 | ||
895 | spin_lock_init(&dev_priv->irq_lock); | |
896 | spin_lock_init(&dev_priv->gpu_error.lock); | |
897 | mutex_init(&dev_priv->backlight_lock); | |
898 | spin_lock_init(&dev_priv->uncore.lock); | |
317eaa95 | 899 | |
0673ad47 CW |
900 | mutex_init(&dev_priv->sb_lock); |
901 | mutex_init(&dev_priv->modeset_restore_lock); | |
902 | mutex_init(&dev_priv->av_mutex); | |
903 | mutex_init(&dev_priv->wm.wm_mutex); | |
904 | mutex_init(&dev_priv->pps_mutex); | |
905 | ||
413e8fdb | 906 | intel_uc_init_early(dev_priv); |
0b1de5d5 CW |
907 | i915_memcpy_init_early(dev_priv); |
908 | ||
0673ad47 CW |
909 | ret = i915_workqueues_init(dev_priv); |
910 | if (ret < 0) | |
bb8f0f5a | 911 | goto err_engines; |
0673ad47 | 912 | |
0673ad47 | 913 | /* This must be called before any calls to HAS_PCH_* */ |
da5f53bf | 914 | intel_detect_pch(dev_priv); |
0673ad47 | 915 | |
192aa181 | 916 | intel_pm_setup(dev_priv); |
0673ad47 CW |
917 | intel_init_dpio(dev_priv); |
918 | intel_power_domains_init(dev_priv); | |
919 | intel_irq_init(dev_priv); | |
3ac168a7 | 920 | intel_hangcheck_init(dev_priv); |
0673ad47 CW |
921 | intel_init_display_hooks(dev_priv); |
922 | intel_init_clock_gating_hooks(dev_priv); | |
923 | intel_init_audio_hooks(dev_priv); | |
cb15d9f8 | 924 | ret = i915_gem_load_init(dev_priv); |
73cb9701 | 925 | if (ret < 0) |
cefcff8f | 926 | goto err_irq; |
0673ad47 | 927 | |
36cdd013 | 928 | intel_display_crc_init(dev_priv); |
0673ad47 | 929 | |
94b4f3ba | 930 | intel_device_info_dump(dev_priv); |
0673ad47 | 931 | |
4fc7e845 | 932 | intel_detect_preproduction_hw(dev_priv); |
0673ad47 | 933 | |
eec688e1 RB |
934 | i915_perf_init(dev_priv); |
935 | ||
0673ad47 CW |
936 | return 0; |
937 | ||
cefcff8f JL |
938 | err_irq: |
939 | intel_irq_fini(dev_priv); | |
0673ad47 | 940 | i915_workqueues_cleanup(dev_priv); |
bb8f0f5a CW |
941 | err_engines: |
942 | i915_engines_cleanup(dev_priv); | |
0673ad47 CW |
943 | return ret; |
944 | } | |
945 | ||
946 | /** | |
947 | * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early() | |
948 | * @dev_priv: device private | |
949 | */ | |
950 | static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv) | |
951 | { | |
eec688e1 | 952 | i915_perf_fini(dev_priv); |
cb15d9f8 | 953 | i915_gem_load_cleanup(dev_priv); |
cefcff8f | 954 | intel_irq_fini(dev_priv); |
0673ad47 | 955 | i915_workqueues_cleanup(dev_priv); |
bb8f0f5a | 956 | i915_engines_cleanup(dev_priv); |
0673ad47 CW |
957 | } |
958 | ||
da5f53bf | 959 | static int i915_mmio_setup(struct drm_i915_private *dev_priv) |
0673ad47 | 960 | { |
52a05c30 | 961 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
962 | int mmio_bar; |
963 | int mmio_size; | |
964 | ||
5db94019 | 965 | mmio_bar = IS_GEN2(dev_priv) ? 1 : 0; |
0673ad47 CW |
966 | /* |
967 | * Before gen4, the registers and the GTT are behind different BARs. | |
968 | * However, from gen4 onwards, the registers and the GTT are shared | |
969 | * in the same BAR, so we want to restrict this ioremap from | |
970 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
971 | * the register BAR remains the same size for all the earlier | |
972 | * generations up to Ironlake. | |
973 | */ | |
514e1d64 | 974 | if (INTEL_GEN(dev_priv) < 5) |
0673ad47 CW |
975 | mmio_size = 512 * 1024; |
976 | else | |
977 | mmio_size = 2 * 1024 * 1024; | |
52a05c30 | 978 | dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size); |
0673ad47 CW |
979 | if (dev_priv->regs == NULL) { |
980 | DRM_ERROR("failed to map registers\n"); | |
981 | ||
982 | return -EIO; | |
983 | } | |
984 | ||
985 | /* Try to make sure MCHBAR is enabled before poking at it */ | |
da5f53bf | 986 | intel_setup_mchbar(dev_priv); |
0673ad47 CW |
987 | |
988 | return 0; | |
989 | } | |
990 | ||
da5f53bf | 991 | static void i915_mmio_cleanup(struct drm_i915_private *dev_priv) |
0673ad47 | 992 | { |
52a05c30 | 993 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 | 994 | |
da5f53bf | 995 | intel_teardown_mchbar(dev_priv); |
52a05c30 | 996 | pci_iounmap(pdev, dev_priv->regs); |
0673ad47 CW |
997 | } |
998 | ||
999 | /** | |
1000 | * i915_driver_init_mmio - setup device MMIO | |
1001 | * @dev_priv: device private | |
1002 | * | |
1003 | * Setup minimal device state necessary for MMIO accesses later in the | |
1004 | * initialization sequence. The setup here should avoid any other device-wide | |
1005 | * side effects or exposing the driver via kernel internal or user space | |
1006 | * interfaces. | |
1007 | */ | |
1008 | static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) | |
1009 | { | |
0673ad47 CW |
1010 | int ret; |
1011 | ||
1012 | if (i915_inject_load_failure()) | |
1013 | return -ENODEV; | |
1014 | ||
da5f53bf | 1015 | if (i915_get_bridge_dev(dev_priv)) |
0673ad47 CW |
1016 | return -EIO; |
1017 | ||
da5f53bf | 1018 | ret = i915_mmio_setup(dev_priv); |
0673ad47 | 1019 | if (ret < 0) |
63ffbcda | 1020 | goto err_bridge; |
0673ad47 CW |
1021 | |
1022 | intel_uncore_init(dev_priv); | |
63ffbcda | 1023 | |
1fc556fa SAK |
1024 | intel_uc_init_mmio(dev_priv); |
1025 | ||
63ffbcda JL |
1026 | ret = intel_engines_init_mmio(dev_priv); |
1027 | if (ret) | |
1028 | goto err_uncore; | |
1029 | ||
24145517 | 1030 | i915_gem_init_mmio(dev_priv); |
0673ad47 CW |
1031 | |
1032 | return 0; | |
1033 | ||
63ffbcda JL |
1034 | err_uncore: |
1035 | intel_uncore_fini(dev_priv); | |
1036 | err_bridge: | |
0673ad47 CW |
1037 | pci_dev_put(dev_priv->bridge_dev); |
1038 | ||
1039 | return ret; | |
1040 | } | |
1041 | ||
1042 | /** | |
1043 | * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio() | |
1044 | * @dev_priv: device private | |
1045 | */ | |
1046 | static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) | |
1047 | { | |
0673ad47 | 1048 | intel_uncore_fini(dev_priv); |
da5f53bf | 1049 | i915_mmio_cleanup(dev_priv); |
0673ad47 CW |
1050 | pci_dev_put(dev_priv->bridge_dev); |
1051 | } | |
1052 | ||
94b4f3ba CW |
1053 | static void intel_sanitize_options(struct drm_i915_private *dev_priv) |
1054 | { | |
4f044a88 | 1055 | i915_modparams.enable_execlists = |
94b4f3ba | 1056 | intel_sanitize_enable_execlists(dev_priv, |
4f044a88 | 1057 | i915_modparams.enable_execlists); |
94b4f3ba CW |
1058 | |
1059 | /* | |
1060 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
1061 | * user's requested state against the hardware/driver capabilities. We | |
1062 | * do this now so that we can print out any log messages once rather | |
1063 | * than every time we check intel_enable_ppgtt(). | |
1064 | */ | |
4f044a88 MW |
1065 | i915_modparams.enable_ppgtt = |
1066 | intel_sanitize_enable_ppgtt(dev_priv, | |
1067 | i915_modparams.enable_ppgtt); | |
1068 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt); | |
39df9190 | 1069 | |
4f044a88 MW |
1070 | i915_modparams.semaphores = |
1071 | intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores); | |
1072 | DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", | |
1073 | yesno(i915_modparams.semaphores)); | |
d2be9f2f AH |
1074 | |
1075 | intel_uc_sanitize_options(dev_priv); | |
67b7f33e CD |
1076 | |
1077 | intel_gvt_sanitize_options(dev_priv); | |
94b4f3ba CW |
1078 | } |
1079 | ||
0673ad47 CW |
1080 | /** |
1081 | * i915_driver_init_hw - setup state requiring device access | |
1082 | * @dev_priv: device private | |
1083 | * | |
1084 | * Setup state that requires accessing the device, but doesn't require | |
1085 | * exposing the driver via kernel internal or userspace interfaces. | |
1086 | */ | |
1087 | static int i915_driver_init_hw(struct drm_i915_private *dev_priv) | |
1088 | { | |
52a05c30 | 1089 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
1090 | int ret; |
1091 | ||
1092 | if (i915_inject_load_failure()) | |
1093 | return -ENODEV; | |
1094 | ||
94b4f3ba CW |
1095 | intel_device_info_runtime_init(dev_priv); |
1096 | ||
1097 | intel_sanitize_options(dev_priv); | |
0673ad47 | 1098 | |
97d6d7ab | 1099 | ret = i915_ggtt_probe_hw(dev_priv); |
0673ad47 CW |
1100 | if (ret) |
1101 | return ret; | |
1102 | ||
0673ad47 CW |
1103 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, |
1104 | * otherwise the vga fbdev driver falls over. */ | |
1105 | ret = i915_kick_out_firmware_fb(dev_priv); | |
1106 | if (ret) { | |
1107 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
1108 | goto out_ggtt; | |
1109 | } | |
1110 | ||
1111 | ret = i915_kick_out_vgacon(dev_priv); | |
1112 | if (ret) { | |
1113 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
1114 | goto out_ggtt; | |
1115 | } | |
1116 | ||
97d6d7ab | 1117 | ret = i915_ggtt_init_hw(dev_priv); |
0088e522 CW |
1118 | if (ret) |
1119 | return ret; | |
1120 | ||
97d6d7ab | 1121 | ret = i915_ggtt_enable_hw(dev_priv); |
0088e522 CW |
1122 | if (ret) { |
1123 | DRM_ERROR("failed to enable GGTT\n"); | |
1124 | goto out_ggtt; | |
1125 | } | |
1126 | ||
52a05c30 | 1127 | pci_set_master(pdev); |
0673ad47 CW |
1128 | |
1129 | /* overlay on gen2 is broken and can't address above 1G */ | |
5db94019 | 1130 | if (IS_GEN2(dev_priv)) { |
52a05c30 | 1131 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); |
0673ad47 CW |
1132 | if (ret) { |
1133 | DRM_ERROR("failed to set DMA mask\n"); | |
1134 | ||
1135 | goto out_ggtt; | |
1136 | } | |
1137 | } | |
1138 | ||
0673ad47 CW |
1139 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1140 | * using 32bit addressing, overwriting memory if HWS is located | |
1141 | * above 4GB. | |
1142 | * | |
1143 | * The documentation also mentions an issue with undefined | |
1144 | * behaviour if any general state is accessed within a page above 4GB, | |
1145 | * which also needs to be handled carefully. | |
1146 | */ | |
c0f86832 | 1147 | if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) { |
52a05c30 | 1148 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
0673ad47 CW |
1149 | |
1150 | if (ret) { | |
1151 | DRM_ERROR("failed to set DMA mask\n"); | |
1152 | ||
1153 | goto out_ggtt; | |
1154 | } | |
1155 | } | |
1156 | ||
0673ad47 CW |
1157 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, |
1158 | PM_QOS_DEFAULT_VALUE); | |
1159 | ||
1160 | intel_uncore_sanitize(dev_priv); | |
1161 | ||
1162 | intel_opregion_setup(dev_priv); | |
1163 | ||
1164 | i915_gem_load_init_fences(dev_priv); | |
1165 | ||
1166 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
1167 | * integrated graphics even though the support isn't actually there | |
1168 | * according to the published specs. It doesn't appear to function | |
1169 | * correctly in testing on 945G. | |
1170 | * This may be a side effect of MSI having been made available for PEG | |
1171 | * and the registers being closely associated. | |
1172 | * | |
1173 | * According to chipset errata, on the 965GM, MSI interrupts may | |
e38c2da0 VS |
1174 | * be lost or delayed, and was defeatured. MSI interrupts seem to |
1175 | * get lost on g4x as well, and interrupt delivery seems to stay | |
1176 | * properly dead afterwards. So we'll just disable them for all | |
1177 | * pre-gen5 chipsets. | |
0673ad47 | 1178 | */ |
e38c2da0 | 1179 | if (INTEL_GEN(dev_priv) >= 5) { |
52a05c30 | 1180 | if (pci_enable_msi(pdev) < 0) |
0673ad47 CW |
1181 | DRM_DEBUG_DRIVER("can't enable MSI"); |
1182 | } | |
1183 | ||
26f837e8 ZW |
1184 | ret = intel_gvt_init(dev_priv); |
1185 | if (ret) | |
1186 | goto out_ggtt; | |
1187 | ||
0673ad47 CW |
1188 | return 0; |
1189 | ||
1190 | out_ggtt: | |
97d6d7ab | 1191 | i915_ggtt_cleanup_hw(dev_priv); |
0673ad47 CW |
1192 | |
1193 | return ret; | |
1194 | } | |
1195 | ||
1196 | /** | |
1197 | * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw() | |
1198 | * @dev_priv: device private | |
1199 | */ | |
1200 | static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv) | |
1201 | { | |
52a05c30 | 1202 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 | 1203 | |
52a05c30 DW |
1204 | if (pdev->msi_enabled) |
1205 | pci_disable_msi(pdev); | |
0673ad47 CW |
1206 | |
1207 | pm_qos_remove_request(&dev_priv->pm_qos); | |
97d6d7ab | 1208 | i915_ggtt_cleanup_hw(dev_priv); |
0673ad47 CW |
1209 | } |
1210 | ||
1211 | /** | |
1212 | * i915_driver_register - register the driver with the rest of the system | |
1213 | * @dev_priv: device private | |
1214 | * | |
1215 | * Perform any steps necessary to make the driver available via kernel | |
1216 | * internal or userspace interfaces. | |
1217 | */ | |
1218 | static void i915_driver_register(struct drm_i915_private *dev_priv) | |
1219 | { | |
91c8a326 | 1220 | struct drm_device *dev = &dev_priv->drm; |
0673ad47 CW |
1221 | |
1222 | i915_gem_shrinker_init(dev_priv); | |
1223 | ||
1224 | /* | |
1225 | * Notify a valid surface after modesetting, | |
1226 | * when running inside a VM. | |
1227 | */ | |
1228 | if (intel_vgpu_active(dev_priv)) | |
1229 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); | |
1230 | ||
1231 | /* Reveal our presence to userspace */ | |
1232 | if (drm_dev_register(dev, 0) == 0) { | |
1233 | i915_debugfs_register(dev_priv); | |
f9cda048 | 1234 | i915_guc_log_register(dev_priv); |
694c2828 | 1235 | i915_setup_sysfs(dev_priv); |
442b8c06 RB |
1236 | |
1237 | /* Depends on sysfs having been initialized */ | |
1238 | i915_perf_register(dev_priv); | |
0673ad47 CW |
1239 | } else |
1240 | DRM_ERROR("Failed to register driver for userspace access!\n"); | |
1241 | ||
1242 | if (INTEL_INFO(dev_priv)->num_pipes) { | |
1243 | /* Must be done after probing outputs */ | |
1244 | intel_opregion_register(dev_priv); | |
1245 | acpi_video_register(); | |
1246 | } | |
1247 | ||
1248 | if (IS_GEN5(dev_priv)) | |
1249 | intel_gpu_ips_init(dev_priv); | |
1250 | ||
eef57324 | 1251 | intel_audio_init(dev_priv); |
0673ad47 CW |
1252 | |
1253 | /* | |
1254 | * Some ports require correctly set-up hpd registers for detection to | |
1255 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1256 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1257 | * irqs are fully enabled. We do it last so that the async config | |
1258 | * cannot run before the connectors are registered. | |
1259 | */ | |
1260 | intel_fbdev_initial_config_async(dev); | |
1261 | } | |
1262 | ||
1263 | /** | |
1264 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() | |
1265 | * @dev_priv: device private | |
1266 | */ | |
1267 | static void i915_driver_unregister(struct drm_i915_private *dev_priv) | |
1268 | { | |
4f256d82 | 1269 | intel_fbdev_unregister(dev_priv); |
eef57324 | 1270 | intel_audio_deinit(dev_priv); |
0673ad47 CW |
1271 | |
1272 | intel_gpu_ips_teardown(); | |
1273 | acpi_video_unregister(); | |
1274 | intel_opregion_unregister(dev_priv); | |
1275 | ||
442b8c06 RB |
1276 | i915_perf_unregister(dev_priv); |
1277 | ||
694c2828 | 1278 | i915_teardown_sysfs(dev_priv); |
f9cda048 | 1279 | i915_guc_log_unregister(dev_priv); |
91c8a326 | 1280 | drm_dev_unregister(&dev_priv->drm); |
0673ad47 CW |
1281 | |
1282 | i915_gem_shrinker_cleanup(dev_priv); | |
1283 | } | |
1284 | ||
1285 | /** | |
1286 | * i915_driver_load - setup chip and create an initial config | |
d2ad3ae4 JL |
1287 | * @pdev: PCI device |
1288 | * @ent: matching PCI ID entry | |
0673ad47 CW |
1289 | * |
1290 | * The driver load routine has to do several things: | |
1291 | * - drive output discovery via intel_modeset_init() | |
1292 | * - initialize the memory manager | |
1293 | * - allocate initial config memory | |
1294 | * - setup the DRM framebuffer with the allocated memory | |
1295 | */ | |
42f5551d | 1296 | int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) |
0673ad47 | 1297 | { |
8d2b47dd ML |
1298 | const struct intel_device_info *match_info = |
1299 | (struct intel_device_info *)ent->driver_data; | |
0673ad47 CW |
1300 | struct drm_i915_private *dev_priv; |
1301 | int ret; | |
7d87a7f7 | 1302 | |
ff4c3b76 | 1303 | /* Enable nuclear pageflip on ILK+ */ |
4f044a88 | 1304 | if (!i915_modparams.nuclear_pageflip && match_info->gen < 5) |
8d2b47dd | 1305 | driver.driver_features &= ~DRIVER_ATOMIC; |
a09d0ba1 | 1306 | |
0673ad47 CW |
1307 | ret = -ENOMEM; |
1308 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
1309 | if (dev_priv) | |
1310 | ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev); | |
1311 | if (ret) { | |
87a6752c | 1312 | DRM_DEV_ERROR(&pdev->dev, "allocation failed\n"); |
cad3688f | 1313 | goto out_free; |
0673ad47 | 1314 | } |
72bbf0af | 1315 | |
0673ad47 CW |
1316 | dev_priv->drm.pdev = pdev; |
1317 | dev_priv->drm.dev_private = dev_priv; | |
719388e1 | 1318 | |
0673ad47 CW |
1319 | ret = pci_enable_device(pdev); |
1320 | if (ret) | |
cad3688f | 1321 | goto out_fini; |
1347f5b4 | 1322 | |
0673ad47 | 1323 | pci_set_drvdata(pdev, &dev_priv->drm); |
adfdf85d ID |
1324 | /* |
1325 | * Disable the system suspend direct complete optimization, which can | |
1326 | * leave the device suspended skipping the driver's suspend handlers | |
1327 | * if the device was already runtime suspended. This is needed due to | |
1328 | * the difference in our runtime and system suspend sequence and | |
1329 | * becaue the HDA driver may require us to enable the audio power | |
1330 | * domain during system suspend. | |
1331 | */ | |
1332 | pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME; | |
ef11bdb3 | 1333 | |
0673ad47 CW |
1334 | ret = i915_driver_init_early(dev_priv, ent); |
1335 | if (ret < 0) | |
1336 | goto out_pci_disable; | |
ef11bdb3 | 1337 | |
0673ad47 | 1338 | intel_runtime_pm_get(dev_priv); |
1da177e4 | 1339 | |
0673ad47 CW |
1340 | ret = i915_driver_init_mmio(dev_priv); |
1341 | if (ret < 0) | |
1342 | goto out_runtime_pm_put; | |
79e53945 | 1343 | |
0673ad47 CW |
1344 | ret = i915_driver_init_hw(dev_priv); |
1345 | if (ret < 0) | |
1346 | goto out_cleanup_mmio; | |
30c964a6 RB |
1347 | |
1348 | /* | |
0673ad47 CW |
1349 | * TODO: move the vblank init and parts of modeset init steps into one |
1350 | * of the i915_driver_init_/i915_driver_register functions according | |
1351 | * to the role/effect of the given init step. | |
30c964a6 | 1352 | */ |
0673ad47 | 1353 | if (INTEL_INFO(dev_priv)->num_pipes) { |
91c8a326 | 1354 | ret = drm_vblank_init(&dev_priv->drm, |
0673ad47 CW |
1355 | INTEL_INFO(dev_priv)->num_pipes); |
1356 | if (ret) | |
1357 | goto out_cleanup_hw; | |
30c964a6 RB |
1358 | } |
1359 | ||
91c8a326 | 1360 | ret = i915_load_modeset_init(&dev_priv->drm); |
0673ad47 | 1361 | if (ret < 0) |
baf54385 | 1362 | goto out_cleanup_hw; |
0673ad47 CW |
1363 | |
1364 | i915_driver_register(dev_priv); | |
1365 | ||
1366 | intel_runtime_pm_enable(dev_priv); | |
1367 | ||
2503a0fe | 1368 | intel_init_ipc(dev_priv); |
a3a8986c | 1369 | |
0525a062 CW |
1370 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) |
1371 | DRM_INFO("DRM_I915_DEBUG enabled\n"); | |
1372 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) | |
1373 | DRM_INFO("DRM_I915_DEBUG_GEM enabled\n"); | |
bc5ca47c | 1374 | |
0673ad47 CW |
1375 | intel_runtime_pm_put(dev_priv); |
1376 | ||
1377 | return 0; | |
1378 | ||
0673ad47 CW |
1379 | out_cleanup_hw: |
1380 | i915_driver_cleanup_hw(dev_priv); | |
1381 | out_cleanup_mmio: | |
1382 | i915_driver_cleanup_mmio(dev_priv); | |
1383 | out_runtime_pm_put: | |
1384 | intel_runtime_pm_put(dev_priv); | |
1385 | i915_driver_cleanup_early(dev_priv); | |
1386 | out_pci_disable: | |
1387 | pci_disable_device(pdev); | |
cad3688f | 1388 | out_fini: |
0673ad47 | 1389 | i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret); |
cad3688f CW |
1390 | drm_dev_fini(&dev_priv->drm); |
1391 | out_free: | |
1392 | kfree(dev_priv); | |
30c964a6 RB |
1393 | return ret; |
1394 | } | |
1395 | ||
42f5551d | 1396 | void i915_driver_unload(struct drm_device *dev) |
3bad0781 | 1397 | { |
fac5e23e | 1398 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1399 | struct pci_dev *pdev = dev_priv->drm.pdev; |
3bad0781 | 1400 | |
99c539be DV |
1401 | i915_driver_unregister(dev_priv); |
1402 | ||
bf9e8429 | 1403 | if (i915_gem_suspend(dev_priv)) |
42f5551d | 1404 | DRM_ERROR("failed to idle hardware; continuing to unload!\n"); |
ce1bb329 | 1405 | |
0673ad47 CW |
1406 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
1407 | ||
18dddadc | 1408 | drm_atomic_helper_shutdown(dev); |
a667fb40 | 1409 | |
26f837e8 ZW |
1410 | intel_gvt_cleanup(dev_priv); |
1411 | ||
0673ad47 CW |
1412 | intel_modeset_cleanup(dev); |
1413 | ||
3bad0781 | 1414 | /* |
0673ad47 CW |
1415 | * free the memory space allocated for the child device |
1416 | * config parsed from VBT | |
3bad0781 | 1417 | */ |
0673ad47 CW |
1418 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
1419 | kfree(dev_priv->vbt.child_dev); | |
1420 | dev_priv->vbt.child_dev = NULL; | |
1421 | dev_priv->vbt.child_dev_num = 0; | |
1422 | } | |
1423 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); | |
1424 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; | |
1425 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); | |
1426 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; | |
3bad0781 | 1427 | |
52a05c30 DW |
1428 | vga_switcheroo_unregister_client(pdev); |
1429 | vga_client_register(pdev, NULL, NULL, NULL); | |
bcdb72ac | 1430 | |
0673ad47 | 1431 | intel_csr_ucode_fini(dev_priv); |
bcdb72ac | 1432 | |
0673ad47 CW |
1433 | /* Free error state after interrupts are fully disabled. */ |
1434 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
5a4c6f1b | 1435 | i915_reset_error_state(dev_priv); |
0673ad47 | 1436 | |
fbbd37b3 | 1437 | i915_gem_fini(dev_priv); |
3950bf3d | 1438 | intel_uc_fini_fw(dev_priv); |
0673ad47 CW |
1439 | intel_fbc_cleanup_cfb(dev_priv); |
1440 | ||
1441 | intel_power_domains_fini(dev_priv); | |
1442 | ||
1443 | i915_driver_cleanup_hw(dev_priv); | |
1444 | i915_driver_cleanup_mmio(dev_priv); | |
1445 | ||
1446 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
cad3688f CW |
1447 | } |
1448 | ||
1449 | static void i915_driver_release(struct drm_device *dev) | |
1450 | { | |
1451 | struct drm_i915_private *dev_priv = to_i915(dev); | |
0673ad47 CW |
1452 | |
1453 | i915_driver_cleanup_early(dev_priv); | |
cad3688f CW |
1454 | drm_dev_fini(&dev_priv->drm); |
1455 | ||
1456 | kfree(dev_priv); | |
3bad0781 ZW |
1457 | } |
1458 | ||
0673ad47 | 1459 | static int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
2911a35b | 1460 | { |
829a0af2 | 1461 | struct drm_i915_private *i915 = to_i915(dev); |
0673ad47 | 1462 | int ret; |
2911a35b | 1463 | |
829a0af2 | 1464 | ret = i915_gem_open(i915, file); |
0673ad47 CW |
1465 | if (ret) |
1466 | return ret; | |
2911a35b | 1467 | |
0673ad47 CW |
1468 | return 0; |
1469 | } | |
71386ef9 | 1470 | |
0673ad47 CW |
1471 | /** |
1472 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1473 | * @dev: DRM device | |
1474 | * | |
1475 | * Take care of cleaning up after all DRM clients have exited. In the | |
1476 | * mode setting case, we want to restore the kernel's initial mode (just | |
1477 | * in case the last client left us in a bad state). | |
1478 | * | |
1479 | * Additionally, in the non-mode setting case, we'll tear down the GTT | |
1480 | * and DMA structures, since the kernel won't be using them, and clea | |
1481 | * up any GEM state. | |
1482 | */ | |
1483 | static void i915_driver_lastclose(struct drm_device *dev) | |
1484 | { | |
1485 | intel_fbdev_restore_mode(dev); | |
1486 | vga_switcheroo_process_delayed_switch(); | |
1487 | } | |
2911a35b | 1488 | |
7d2ec881 | 1489 | static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
0673ad47 | 1490 | { |
7d2ec881 DV |
1491 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1492 | ||
0673ad47 | 1493 | mutex_lock(&dev->struct_mutex); |
829a0af2 | 1494 | i915_gem_context_close(file); |
0673ad47 CW |
1495 | i915_gem_release(dev, file); |
1496 | mutex_unlock(&dev->struct_mutex); | |
0673ad47 CW |
1497 | |
1498 | kfree(file_priv); | |
2911a35b BW |
1499 | } |
1500 | ||
07f9cd0b ID |
1501 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
1502 | { | |
91c8a326 | 1503 | struct drm_device *dev = &dev_priv->drm; |
19c8054c | 1504 | struct intel_encoder *encoder; |
07f9cd0b ID |
1505 | |
1506 | drm_modeset_lock_all(dev); | |
19c8054c JN |
1507 | for_each_intel_encoder(dev, encoder) |
1508 | if (encoder->suspend) | |
1509 | encoder->suspend(encoder); | |
07f9cd0b ID |
1510 | drm_modeset_unlock_all(dev); |
1511 | } | |
1512 | ||
1a5df187 PZ |
1513 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1514 | bool rpm_resume); | |
507e126e | 1515 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv); |
f75a1985 | 1516 | |
bc87229f ID |
1517 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
1518 | { | |
1519 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
1520 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
1521 | return true; | |
1522 | #endif | |
1523 | return false; | |
1524 | } | |
ebc32824 | 1525 | |
5e365c39 | 1526 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 1527 | { |
fac5e23e | 1528 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1529 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e5747e3a | 1530 | pci_power_t opregion_target_state; |
d5818938 | 1531 | int error; |
61caf87c | 1532 | |
b8efb17b ZR |
1533 | /* ignore lid events during suspend */ |
1534 | mutex_lock(&dev_priv->modeset_restore_lock); | |
1535 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
1536 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
1537 | ||
1f814dac ID |
1538 | disable_rpm_wakeref_asserts(dev_priv); |
1539 | ||
c67a470b PZ |
1540 | /* We do a lot of poking in a lot of registers, make sure they work |
1541 | * properly. */ | |
da7e29bd | 1542 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 1543 | |
5bcf719b DA |
1544 | drm_kms_helper_poll_disable(dev); |
1545 | ||
52a05c30 | 1546 | pci_save_state(pdev); |
ba8bbcf6 | 1547 | |
bf9e8429 | 1548 | error = i915_gem_suspend(dev_priv); |
d5818938 | 1549 | if (error) { |
52a05c30 | 1550 | dev_err(&pdev->dev, |
d5818938 | 1551 | "GEM idle failed, resume might fail\n"); |
1f814dac | 1552 | goto out; |
d5818938 | 1553 | } |
db1b76ca | 1554 | |
6b72d486 | 1555 | intel_display_suspend(dev); |
2eb5252e | 1556 | |
d5818938 | 1557 | intel_dp_mst_suspend(dev); |
7d708ee4 | 1558 | |
d5818938 DV |
1559 | intel_runtime_pm_disable_interrupts(dev_priv); |
1560 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 1561 | |
d5818938 | 1562 | intel_suspend_encoders(dev_priv); |
0e32b39c | 1563 | |
712bf364 | 1564 | intel_suspend_hw(dev_priv); |
5669fcac | 1565 | |
275a991c | 1566 | i915_gem_suspend_gtt_mappings(dev_priv); |
828c7908 | 1567 | |
af6dc742 | 1568 | i915_save_state(dev_priv); |
9e06dd39 | 1569 | |
bc87229f | 1570 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
6f9f4b7a | 1571 | intel_opregion_notify_adapter(dev_priv, opregion_target_state); |
e5747e3a | 1572 | |
68f60946 | 1573 | intel_uncore_suspend(dev_priv); |
03d92e47 | 1574 | intel_opregion_unregister(dev_priv); |
8ee1c3db | 1575 | |
82e3b8c1 | 1576 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 1577 | |
62d5d69b MK |
1578 | dev_priv->suspend_count++; |
1579 | ||
f74ed08d | 1580 | intel_csr_ucode_suspend(dev_priv); |
f514c2d8 | 1581 | |
1f814dac ID |
1582 | out: |
1583 | enable_rpm_wakeref_asserts(dev_priv); | |
1584 | ||
1585 | return error; | |
84b79f8d RW |
1586 | } |
1587 | ||
c49d13ee | 1588 | static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) |
c3c09c95 | 1589 | { |
c49d13ee | 1590 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1591 | struct pci_dev *pdev = dev_priv->drm.pdev; |
bc87229f | 1592 | bool fw_csr; |
c3c09c95 ID |
1593 | int ret; |
1594 | ||
1f814dac ID |
1595 | disable_rpm_wakeref_asserts(dev_priv); |
1596 | ||
4c494a57 ID |
1597 | intel_display_set_init_power(dev_priv, false); |
1598 | ||
dd9f31c7 | 1599 | fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation && |
a7c8125f | 1600 | suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; |
bc87229f ID |
1601 | /* |
1602 | * In case of firmware assisted context save/restore don't manually | |
1603 | * deinit the power domains. This also means the CSR/DMC firmware will | |
1604 | * stay active, it will power down any HW resources as required and | |
1605 | * also enable deeper system power states that would be blocked if the | |
1606 | * firmware was inactive. | |
1607 | */ | |
1608 | if (!fw_csr) | |
1609 | intel_power_domains_suspend(dev_priv); | |
73dfc227 | 1610 | |
507e126e | 1611 | ret = 0; |
b9fd799e | 1612 | if (IS_GEN9_LP(dev_priv)) |
507e126e | 1613 | bxt_enable_dc9(dev_priv); |
b8aea3d1 | 1614 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
507e126e ID |
1615 | hsw_enable_pc8(dev_priv); |
1616 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1617 | ret = vlv_suspend_complete(dev_priv); | |
c3c09c95 ID |
1618 | |
1619 | if (ret) { | |
1620 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
bc87229f ID |
1621 | if (!fw_csr) |
1622 | intel_power_domains_init_hw(dev_priv, true); | |
c3c09c95 | 1623 | |
1f814dac | 1624 | goto out; |
c3c09c95 ID |
1625 | } |
1626 | ||
52a05c30 | 1627 | pci_disable_device(pdev); |
ab3be73f | 1628 | /* |
54875571 | 1629 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
1630 | * the device even though it's already in D3 and hang the machine. So |
1631 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
1632 | * power down the device properly. The issue was seen on multiple old |
1633 | * GENs with different BIOS vendors, so having an explicit blacklist | |
1634 | * is inpractical; apply the workaround on everything pre GEN6. The | |
1635 | * platforms where the issue was seen: | |
1636 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
1637 | * Fujitsu FSC S7110 | |
1638 | * Acer Aspire 1830T | |
ab3be73f | 1639 | */ |
514e1d64 | 1640 | if (!(hibernation && INTEL_GEN(dev_priv) < 6)) |
52a05c30 | 1641 | pci_set_power_state(pdev, PCI_D3hot); |
c3c09c95 | 1642 | |
bc87229f ID |
1643 | dev_priv->suspended_to_idle = suspend_to_idle(dev_priv); |
1644 | ||
1f814dac ID |
1645 | out: |
1646 | enable_rpm_wakeref_asserts(dev_priv); | |
1647 | ||
1648 | return ret; | |
c3c09c95 ID |
1649 | } |
1650 | ||
a9a251c2 | 1651 | static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
1652 | { |
1653 | int error; | |
1654 | ||
ded8b07d | 1655 | if (!dev) { |
84b79f8d RW |
1656 | DRM_ERROR("dev: %p\n", dev); |
1657 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
1658 | return -ENODEV; | |
1659 | } | |
1660 | ||
0b14cbd2 ID |
1661 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
1662 | state.event != PM_EVENT_FREEZE)) | |
1663 | return -EINVAL; | |
5bcf719b DA |
1664 | |
1665 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1666 | return 0; | |
6eecba33 | 1667 | |
5e365c39 | 1668 | error = i915_drm_suspend(dev); |
84b79f8d RW |
1669 | if (error) |
1670 | return error; | |
1671 | ||
ab3be73f | 1672 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
1673 | } |
1674 | ||
5e365c39 | 1675 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 | 1676 | { |
fac5e23e | 1677 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac840ae5 | 1678 | int ret; |
9d49c0ef | 1679 | |
1f814dac | 1680 | disable_rpm_wakeref_asserts(dev_priv); |
abc80abd | 1681 | intel_sanitize_gt_powersave(dev_priv); |
1f814dac | 1682 | |
97d6d7ab | 1683 | ret = i915_ggtt_enable_hw(dev_priv); |
ac840ae5 VS |
1684 | if (ret) |
1685 | DRM_ERROR("failed to re-enable GGTT\n"); | |
1686 | ||
f74ed08d ID |
1687 | intel_csr_ucode_resume(dev_priv); |
1688 | ||
af6dc742 | 1689 | i915_restore_state(dev_priv); |
8090ba8c | 1690 | intel_pps_unlock_regs_wa(dev_priv); |
6f9f4b7a | 1691 | intel_opregion_setup(dev_priv); |
61caf87c | 1692 | |
c39055b0 | 1693 | intel_init_pch_refclk(dev_priv); |
1833b134 | 1694 | |
364aece0 PA |
1695 | /* |
1696 | * Interrupts have to be enabled before any batches are run. If not the | |
1697 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
1698 | * update/restore the context. | |
1699 | * | |
908764f6 ID |
1700 | * drm_mode_config_reset() needs AUX interrupts. |
1701 | * | |
364aece0 PA |
1702 | * Modeset enabling in intel_modeset_init_hw() also needs working |
1703 | * interrupts. | |
1704 | */ | |
1705 | intel_runtime_pm_enable_interrupts(dev_priv); | |
1706 | ||
908764f6 ID |
1707 | drm_mode_config_reset(dev); |
1708 | ||
37cd3300 | 1709 | i915_gem_resume(dev_priv); |
226485e9 | 1710 | |
d5818938 | 1711 | intel_modeset_init_hw(dev); |
24576d23 | 1712 | |
d5818938 DV |
1713 | spin_lock_irq(&dev_priv->irq_lock); |
1714 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 1715 | dev_priv->display.hpd_irq_setup(dev_priv); |
d5818938 | 1716 | spin_unlock_irq(&dev_priv->irq_lock); |
0e32b39c | 1717 | |
d5818938 | 1718 | intel_dp_mst_resume(dev); |
e7d6f7d7 | 1719 | |
a16b7658 L |
1720 | intel_display_resume(dev); |
1721 | ||
e0b70061 L |
1722 | drm_kms_helper_poll_enable(dev); |
1723 | ||
d5818938 DV |
1724 | /* |
1725 | * ... but also need to make sure that hotplug processing | |
1726 | * doesn't cause havoc. Like in the driver load code we don't | |
1727 | * bother with the tiny race here where we might loose hotplug | |
1728 | * notifications. | |
1729 | * */ | |
1730 | intel_hpd_init(dev_priv); | |
1daed3fb | 1731 | |
03d92e47 | 1732 | intel_opregion_register(dev_priv); |
44834a67 | 1733 | |
82e3b8c1 | 1734 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 1735 | |
b8efb17b ZR |
1736 | mutex_lock(&dev_priv->modeset_restore_lock); |
1737 | dev_priv->modeset_restore = MODESET_DONE; | |
1738 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 1739 | |
6f9f4b7a | 1740 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
e5747e3a | 1741 | |
1f814dac ID |
1742 | enable_rpm_wakeref_asserts(dev_priv); |
1743 | ||
074c6ada | 1744 | return 0; |
84b79f8d RW |
1745 | } |
1746 | ||
5e365c39 | 1747 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 1748 | { |
fac5e23e | 1749 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1750 | struct pci_dev *pdev = dev_priv->drm.pdev; |
44410cd0 | 1751 | int ret; |
36d61e67 | 1752 | |
76c4b250 ID |
1753 | /* |
1754 | * We have a resume ordering issue with the snd-hda driver also | |
1755 | * requiring our device to be power up. Due to the lack of a | |
1756 | * parent/child relationship we currently solve this with an early | |
1757 | * resume hook. | |
1758 | * | |
1759 | * FIXME: This should be solved with a special hdmi sink device or | |
1760 | * similar so that power domains can be employed. | |
1761 | */ | |
44410cd0 ID |
1762 | |
1763 | /* | |
1764 | * Note that we need to set the power state explicitly, since we | |
1765 | * powered off the device during freeze and the PCI core won't power | |
1766 | * it back up for us during thaw. Powering off the device during | |
1767 | * freeze is not a hard requirement though, and during the | |
1768 | * suspend/resume phases the PCI core makes sure we get here with the | |
1769 | * device powered on. So in case we change our freeze logic and keep | |
1770 | * the device powered we can also remove the following set power state | |
1771 | * call. | |
1772 | */ | |
52a05c30 | 1773 | ret = pci_set_power_state(pdev, PCI_D0); |
44410cd0 ID |
1774 | if (ret) { |
1775 | DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret); | |
1776 | goto out; | |
1777 | } | |
1778 | ||
1779 | /* | |
1780 | * Note that pci_enable_device() first enables any parent bridge | |
1781 | * device and only then sets the power state for this device. The | |
1782 | * bridge enabling is a nop though, since bridge devices are resumed | |
1783 | * first. The order of enabling power and enabling the device is | |
1784 | * imposed by the PCI core as described above, so here we preserve the | |
1785 | * same order for the freeze/thaw phases. | |
1786 | * | |
1787 | * TODO: eventually we should remove pci_disable_device() / | |
1788 | * pci_enable_enable_device() from suspend/resume. Due to how they | |
1789 | * depend on the device enable refcount we can't anyway depend on them | |
1790 | * disabling/enabling the device. | |
1791 | */ | |
52a05c30 | 1792 | if (pci_enable_device(pdev)) { |
bc87229f ID |
1793 | ret = -EIO; |
1794 | goto out; | |
1795 | } | |
84b79f8d | 1796 | |
52a05c30 | 1797 | pci_set_master(pdev); |
84b79f8d | 1798 | |
1f814dac ID |
1799 | disable_rpm_wakeref_asserts(dev_priv); |
1800 | ||
666a4537 | 1801 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 | 1802 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 1803 | if (ret) |
ff0b187f DL |
1804 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
1805 | ret); | |
36d61e67 | 1806 | |
68f60946 | 1807 | intel_uncore_resume_early(dev_priv); |
efee833a | 1808 | |
b9fd799e | 1809 | if (IS_GEN9_LP(dev_priv)) { |
da2f41d1 ID |
1810 | if (!dev_priv->suspended_to_idle) |
1811 | gen9_sanitize_dc_state(dev_priv); | |
507e126e | 1812 | bxt_disable_dc9(dev_priv); |
da2f41d1 | 1813 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
a9a6b73a | 1814 | hsw_disable_pc8(dev_priv); |
da2f41d1 | 1815 | } |
efee833a | 1816 | |
dc97997a | 1817 | intel_uncore_sanitize(dev_priv); |
bc87229f | 1818 | |
b9fd799e | 1819 | if (IS_GEN9_LP(dev_priv) || |
a7c8125f | 1820 | !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) |
bc87229f ID |
1821 | intel_power_domains_init_hw(dev_priv, true); |
1822 | ||
24145517 CW |
1823 | i915_gem_sanitize(dev_priv); |
1824 | ||
6e35e8ab ID |
1825 | enable_rpm_wakeref_asserts(dev_priv); |
1826 | ||
bc87229f ID |
1827 | out: |
1828 | dev_priv->suspended_to_idle = false; | |
36d61e67 ID |
1829 | |
1830 | return ret; | |
76c4b250 ID |
1831 | } |
1832 | ||
7f26cb88 | 1833 | static int i915_resume_switcheroo(struct drm_device *dev) |
76c4b250 | 1834 | { |
50a0072f | 1835 | int ret; |
76c4b250 | 1836 | |
097dd837 ID |
1837 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1838 | return 0; | |
1839 | ||
5e365c39 | 1840 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
1841 | if (ret) |
1842 | return ret; | |
1843 | ||
5a17514e ID |
1844 | return i915_drm_resume(dev); |
1845 | } | |
1846 | ||
11ed50ec | 1847 | /** |
f3953dcb | 1848 | * i915_reset - reset chip after a hang |
535275d3 CW |
1849 | * @i915: #drm_i915_private to reset |
1850 | * @flags: Instructions | |
11ed50ec | 1851 | * |
780f262a CW |
1852 | * Reset the chip. Useful if a hang is detected. Marks the device as wedged |
1853 | * on failure. | |
11ed50ec | 1854 | * |
221fe799 CW |
1855 | * Caller must hold the struct_mutex. |
1856 | * | |
11ed50ec BG |
1857 | * Procedure is fairly simple: |
1858 | * - reset the chip using the reset reg | |
1859 | * - re-init context state | |
1860 | * - re-init hardware status page | |
1861 | * - re-init ring buffer | |
1862 | * - re-init interrupt state | |
1863 | * - re-init display | |
1864 | */ | |
535275d3 | 1865 | void i915_reset(struct drm_i915_private *i915, unsigned int flags) |
11ed50ec | 1866 | { |
535275d3 | 1867 | struct i915_gpu_error *error = &i915->gpu_error; |
0573ed4a | 1868 | int ret; |
11ed50ec | 1869 | |
535275d3 | 1870 | lockdep_assert_held(&i915->drm.struct_mutex); |
8c185eca | 1871 | GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags)); |
221fe799 | 1872 | |
8c185eca | 1873 | if (!test_bit(I915_RESET_HANDOFF, &error->flags)) |
780f262a | 1874 | return; |
11ed50ec | 1875 | |
d98c52cf | 1876 | /* Clear any previous failed attempts at recovery. Time to try again. */ |
535275d3 | 1877 | if (!i915_gem_unset_wedged(i915)) |
2e8f9d32 CW |
1878 | goto wakeup; |
1879 | ||
535275d3 CW |
1880 | if (!(flags & I915_RESET_QUIET)) |
1881 | dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n"); | |
8af29b0c | 1882 | error->reset_count++; |
d98c52cf | 1883 | |
535275d3 CW |
1884 | disable_irq(i915->drm.irq); |
1885 | ret = i915_gem_reset_prepare(i915); | |
0e178aef CW |
1886 | if (ret) { |
1887 | DRM_ERROR("GPU recovery failed\n"); | |
535275d3 | 1888 | intel_gpu_reset(i915, ALL_ENGINES); |
0e178aef CW |
1889 | goto error; |
1890 | } | |
9e60ab03 | 1891 | |
535275d3 | 1892 | ret = intel_gpu_reset(i915, ALL_ENGINES); |
0573ed4a | 1893 | if (ret) { |
804e59a8 CW |
1894 | if (ret != -ENODEV) |
1895 | DRM_ERROR("Failed to reset chip: %i\n", ret); | |
1896 | else | |
1897 | DRM_DEBUG_DRIVER("GPU reset disabled\n"); | |
d98c52cf | 1898 | goto error; |
11ed50ec BG |
1899 | } |
1900 | ||
535275d3 CW |
1901 | i915_gem_reset(i915); |
1902 | intel_overlay_reset(i915); | |
1362b776 | 1903 | |
11ed50ec BG |
1904 | /* Ok, now get things going again... */ |
1905 | ||
1906 | /* | |
1907 | * Everything depends on having the GTT running, so we need to start | |
0db8c961 CW |
1908 | * there. |
1909 | */ | |
1910 | ret = i915_ggtt_enable_hw(i915); | |
1911 | if (ret) { | |
1912 | DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret); | |
1913 | goto error; | |
1914 | } | |
1915 | ||
1916 | /* | |
11ed50ec BG |
1917 | * Next we need to restore the context, but we don't use those |
1918 | * yet either... | |
1919 | * | |
1920 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
1921 | * was running at the time of the reset (i.e. we weren't VT | |
1922 | * switched away). | |
1923 | */ | |
535275d3 | 1924 | ret = i915_gem_init_hw(i915); |
33d30a9c DV |
1925 | if (ret) { |
1926 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
d98c52cf | 1927 | goto error; |
11ed50ec BG |
1928 | } |
1929 | ||
535275d3 | 1930 | i915_queue_hangcheck(i915); |
c2a126a4 | 1931 | |
2e8f9d32 | 1932 | finish: |
535275d3 CW |
1933 | i915_gem_reset_finish(i915); |
1934 | enable_irq(i915->drm.irq); | |
8c185eca | 1935 | |
2e8f9d32 | 1936 | wakeup: |
8c185eca CW |
1937 | clear_bit(I915_RESET_HANDOFF, &error->flags); |
1938 | wake_up_bit(&error->flags, I915_RESET_HANDOFF); | |
780f262a | 1939 | return; |
d98c52cf CW |
1940 | |
1941 | error: | |
535275d3 CW |
1942 | i915_gem_set_wedged(i915); |
1943 | i915_gem_retire_requests(i915); | |
2e8f9d32 | 1944 | goto finish; |
11ed50ec BG |
1945 | } |
1946 | ||
6acbea89 MT |
1947 | static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv, |
1948 | struct intel_engine_cs *engine) | |
1949 | { | |
1950 | return intel_gpu_reset(dev_priv, intel_engine_flag(engine)); | |
1951 | } | |
1952 | ||
142bc7d9 MT |
1953 | /** |
1954 | * i915_reset_engine - reset GPU engine to recover from a hang | |
1955 | * @engine: engine to reset | |
535275d3 | 1956 | * @flags: options |
142bc7d9 MT |
1957 | * |
1958 | * Reset a specific GPU engine. Useful if a hang is detected. | |
1959 | * Returns zero on successful reset or otherwise an error code. | |
a1ef70e1 MT |
1960 | * |
1961 | * Procedure is: | |
1962 | * - identifies the request that caused the hang and it is dropped | |
1963 | * - reset engine (which will force the engine to idle) | |
1964 | * - re-init/configure engine | |
142bc7d9 | 1965 | */ |
535275d3 | 1966 | int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags) |
142bc7d9 | 1967 | { |
a1ef70e1 MT |
1968 | struct i915_gpu_error *error = &engine->i915->gpu_error; |
1969 | struct drm_i915_gem_request *active_request; | |
1970 | int ret; | |
1971 | ||
1972 | GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags)); | |
1973 | ||
535275d3 CW |
1974 | if (!(flags & I915_RESET_QUIET)) { |
1975 | dev_notice(engine->i915->drm.dev, | |
1976 | "Resetting %s after gpu hang\n", engine->name); | |
1977 | } | |
7367612f | 1978 | error->reset_engine_count[engine->id]++; |
a1ef70e1 MT |
1979 | |
1980 | active_request = i915_gem_reset_prepare_engine(engine); | |
1981 | if (IS_ERR(active_request)) { | |
1982 | DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n"); | |
1983 | ret = PTR_ERR(active_request); | |
1984 | goto out; | |
1985 | } | |
1986 | ||
6acbea89 MT |
1987 | if (!engine->i915->guc.execbuf_client) |
1988 | ret = intel_gt_reset_engine(engine->i915, engine); | |
1989 | else | |
1990 | ret = intel_guc_reset_engine(&engine->i915->guc, engine); | |
0364cd19 CW |
1991 | if (ret) { |
1992 | /* If we fail here, we expect to fallback to a global reset */ | |
6acbea89 MT |
1993 | DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n", |
1994 | engine->i915->guc.execbuf_client ? "GuC " : "", | |
0364cd19 CW |
1995 | engine->name, ret); |
1996 | goto out; | |
1997 | } | |
b4f3e163 | 1998 | |
a1ef70e1 MT |
1999 | /* |
2000 | * The request that caused the hang is stuck on elsp, we know the | |
2001 | * active request and can drop it, adjust head to skip the offending | |
2002 | * request to resume executing remaining requests in the queue. | |
2003 | */ | |
2004 | i915_gem_reset_engine(engine, active_request); | |
2005 | ||
a1ef70e1 MT |
2006 | /* |
2007 | * The engine and its registers (and workarounds in case of render) | |
2008 | * have been reset to their default values. Follow the init_ring | |
2009 | * process to program RING_MODE, HWSP and re-enable submission. | |
2010 | */ | |
2011 | ret = engine->init_hw(engine); | |
702c8f8e MT |
2012 | if (ret) |
2013 | goto out; | |
a1ef70e1 MT |
2014 | |
2015 | out: | |
0364cd19 | 2016 | i915_gem_reset_finish_engine(engine); |
a1ef70e1 | 2017 | return ret; |
142bc7d9 MT |
2018 | } |
2019 | ||
c49d13ee | 2020 | static int i915_pm_suspend(struct device *kdev) |
112b715e | 2021 | { |
c49d13ee DW |
2022 | struct pci_dev *pdev = to_pci_dev(kdev); |
2023 | struct drm_device *dev = pci_get_drvdata(pdev); | |
112b715e | 2024 | |
c49d13ee DW |
2025 | if (!dev) { |
2026 | dev_err(kdev, "DRM not initialized, aborting suspend.\n"); | |
84b79f8d RW |
2027 | return -ENODEV; |
2028 | } | |
112b715e | 2029 | |
c49d13ee | 2030 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
5bcf719b DA |
2031 | return 0; |
2032 | ||
c49d13ee | 2033 | return i915_drm_suspend(dev); |
76c4b250 ID |
2034 | } |
2035 | ||
c49d13ee | 2036 | static int i915_pm_suspend_late(struct device *kdev) |
76c4b250 | 2037 | { |
c49d13ee | 2038 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
76c4b250 ID |
2039 | |
2040 | /* | |
c965d995 | 2041 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
2042 | * requiring our device to be power up. Due to the lack of a |
2043 | * parent/child relationship we currently solve this with an late | |
2044 | * suspend hook. | |
2045 | * | |
2046 | * FIXME: This should be solved with a special hdmi sink device or | |
2047 | * similar so that power domains can be employed. | |
2048 | */ | |
c49d13ee | 2049 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
76c4b250 | 2050 | return 0; |
112b715e | 2051 | |
c49d13ee | 2052 | return i915_drm_suspend_late(dev, false); |
ab3be73f ID |
2053 | } |
2054 | ||
c49d13ee | 2055 | static int i915_pm_poweroff_late(struct device *kdev) |
ab3be73f | 2056 | { |
c49d13ee | 2057 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
ab3be73f | 2058 | |
c49d13ee | 2059 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
ab3be73f ID |
2060 | return 0; |
2061 | ||
c49d13ee | 2062 | return i915_drm_suspend_late(dev, true); |
cbda12d7 ZW |
2063 | } |
2064 | ||
c49d13ee | 2065 | static int i915_pm_resume_early(struct device *kdev) |
76c4b250 | 2066 | { |
c49d13ee | 2067 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
76c4b250 | 2068 | |
c49d13ee | 2069 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
2070 | return 0; |
2071 | ||
c49d13ee | 2072 | return i915_drm_resume_early(dev); |
76c4b250 ID |
2073 | } |
2074 | ||
c49d13ee | 2075 | static int i915_pm_resume(struct device *kdev) |
cbda12d7 | 2076 | { |
c49d13ee | 2077 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
84b79f8d | 2078 | |
c49d13ee | 2079 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
2080 | return 0; |
2081 | ||
c49d13ee | 2082 | return i915_drm_resume(dev); |
cbda12d7 ZW |
2083 | } |
2084 | ||
1f19ac2a | 2085 | /* freeze: before creating the hibernation_image */ |
c49d13ee | 2086 | static int i915_pm_freeze(struct device *kdev) |
1f19ac2a | 2087 | { |
dd9f31c7 | 2088 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
6a800eab CW |
2089 | int ret; |
2090 | ||
dd9f31c7 ID |
2091 | if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) { |
2092 | ret = i915_drm_suspend(dev); | |
2093 | if (ret) | |
2094 | return ret; | |
2095 | } | |
6a800eab CW |
2096 | |
2097 | ret = i915_gem_freeze(kdev_to_i915(kdev)); | |
2098 | if (ret) | |
2099 | return ret; | |
2100 | ||
2101 | return 0; | |
1f19ac2a CW |
2102 | } |
2103 | ||
c49d13ee | 2104 | static int i915_pm_freeze_late(struct device *kdev) |
1f19ac2a | 2105 | { |
dd9f31c7 | 2106 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
461fb99c CW |
2107 | int ret; |
2108 | ||
dd9f31c7 ID |
2109 | if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) { |
2110 | ret = i915_drm_suspend_late(dev, true); | |
2111 | if (ret) | |
2112 | return ret; | |
2113 | } | |
461fb99c | 2114 | |
c49d13ee | 2115 | ret = i915_gem_freeze_late(kdev_to_i915(kdev)); |
461fb99c CW |
2116 | if (ret) |
2117 | return ret; | |
2118 | ||
2119 | return 0; | |
1f19ac2a CW |
2120 | } |
2121 | ||
2122 | /* thaw: called after creating the hibernation image, but before turning off. */ | |
c49d13ee | 2123 | static int i915_pm_thaw_early(struct device *kdev) |
1f19ac2a | 2124 | { |
c49d13ee | 2125 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
2126 | } |
2127 | ||
c49d13ee | 2128 | static int i915_pm_thaw(struct device *kdev) |
1f19ac2a | 2129 | { |
c49d13ee | 2130 | return i915_pm_resume(kdev); |
1f19ac2a CW |
2131 | } |
2132 | ||
2133 | /* restore: called after loading the hibernation image. */ | |
c49d13ee | 2134 | static int i915_pm_restore_early(struct device *kdev) |
1f19ac2a | 2135 | { |
c49d13ee | 2136 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
2137 | } |
2138 | ||
c49d13ee | 2139 | static int i915_pm_restore(struct device *kdev) |
1f19ac2a | 2140 | { |
c49d13ee | 2141 | return i915_pm_resume(kdev); |
1f19ac2a CW |
2142 | } |
2143 | ||
ddeea5b0 ID |
2144 | /* |
2145 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
2146 | * S0i[R123] transition. The list of registers needing a save/restore is | |
2147 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
2148 | * registers in the following way: | |
2149 | * - Driver: saved/restored by the driver | |
2150 | * - Punit : saved/restored by the Punit firmware | |
2151 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
2152 | * used internally by the HW in a way that doesn't depend | |
2153 | * keeping the content across a suspend/resume. | |
2154 | * - Debug : used for debugging | |
2155 | * | |
2156 | * We save/restore all registers marked with 'Driver', with the following | |
2157 | * exceptions: | |
2158 | * - Registers out of use, including also registers marked with 'Debug'. | |
2159 | * These have no effect on the driver's operation, so we don't save/restore | |
2160 | * them to reduce the overhead. | |
2161 | * - Registers that are fully setup by an initialization function called from | |
2162 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
2163 | * - Registers that provide the right functionality with their reset defaults. | |
2164 | * | |
2165 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
2166 | * ignored, we save/restore all others, practically treating the HW context as | |
2167 | * a black-box for the driver. Further investigation is needed to reduce the | |
2168 | * saved/restored registers even further, by following the same 3 criteria. | |
2169 | */ | |
2170 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
2171 | { | |
2172 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
2173 | int i; | |
2174 | ||
2175 | /* GAM 0x4000-0x4770 */ | |
2176 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
2177 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
2178 | s->arb_mode = I915_READ(ARB_MODE); | |
2179 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
2180 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
2181 | ||
2182 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 2183 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
2184 | |
2185 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 2186 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
2187 | |
2188 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
2189 | s->ecochk = I915_READ(GAM_ECOCHK); | |
2190 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
2191 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
2192 | ||
2193 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
2194 | ||
2195 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
2196 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
2197 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
2198 | s->mbctl = I915_READ(GEN6_MBCTL); | |
2199 | ||
2200 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2201 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
2202 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
2203 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
2204 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
2205 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
2206 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
2207 | ||
2208 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2209 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
2210 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
2211 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
2212 | s->ecobus = I915_READ(ECOBUS); | |
2213 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
2214 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
2215 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
2216 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
2217 | s->rcedata = I915_READ(VLV_RCEDATA); | |
2218 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
2219 | ||
2220 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2221 | s->gt_imr = I915_READ(GTIMR); | |
2222 | s->gt_ier = I915_READ(GTIER); | |
2223 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
2224 | s->pm_ier = I915_READ(GEN6_PMIER); | |
2225 | ||
2226 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2227 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
2228 | |
2229 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2230 | s->tilectl = I915_READ(TILECTL); | |
2231 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
2232 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2233 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2234 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
2235 | ||
2236 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2237 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
2238 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 2239 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
2240 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
2241 | ||
2242 | /* | |
2243 | * Not saving any of: | |
2244 | * DFT, 0x9800-0x9EC0 | |
2245 | * SARB, 0xB000-0xB1FC | |
2246 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
2247 | * PCI CFG | |
2248 | */ | |
2249 | } | |
2250 | ||
2251 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
2252 | { | |
2253 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
2254 | u32 val; | |
2255 | int i; | |
2256 | ||
2257 | /* GAM 0x4000-0x4770 */ | |
2258 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
2259 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
2260 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
2261 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
2262 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
2263 | ||
2264 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 2265 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
2266 | |
2267 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 2268 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
2269 | |
2270 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
2271 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
2272 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
2273 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
2274 | ||
2275 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
2276 | ||
2277 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
2278 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
2279 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
2280 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
2281 | ||
2282 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2283 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
2284 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
2285 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
2286 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
2287 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
2288 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
2289 | ||
2290 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2291 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
2292 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
2293 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
2294 | I915_WRITE(ECOBUS, s->ecobus); | |
2295 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
2296 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
2297 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
2298 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
2299 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
2300 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
2301 | ||
2302 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2303 | I915_WRITE(GTIMR, s->gt_imr); | |
2304 | I915_WRITE(GTIER, s->gt_ier); | |
2305 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
2306 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
2307 | ||
2308 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2309 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
2310 | |
2311 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2312 | I915_WRITE(TILECTL, s->tilectl); | |
2313 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
2314 | /* | |
2315 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
2316 | * be restored, as they are used to control the s0ix suspend/resume | |
2317 | * sequence by the caller. | |
2318 | */ | |
2319 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2320 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
2321 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
2322 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2323 | ||
2324 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2325 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
2326 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2327 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2328 | ||
2329 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
2330 | ||
2331 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2332 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
2333 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 2334 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
2335 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
2336 | } | |
2337 | ||
3dd14c04 CW |
2338 | static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv, |
2339 | u32 mask, u32 val) | |
2340 | { | |
2341 | /* The HW does not like us polling for PW_STATUS frequently, so | |
2342 | * use the sleeping loop rather than risk the busy spin within | |
2343 | * intel_wait_for_register(). | |
2344 | * | |
2345 | * Transitioning between RC6 states should be at most 2ms (see | |
2346 | * valleyview_enable_rps) so use a 3ms timeout. | |
2347 | */ | |
2348 | return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val, | |
2349 | 3); | |
2350 | } | |
2351 | ||
650ad970 ID |
2352 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
2353 | { | |
2354 | u32 val; | |
2355 | int err; | |
2356 | ||
650ad970 ID |
2357 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
2358 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2359 | if (force_on) | |
2360 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
2361 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2362 | ||
2363 | if (!force_on) | |
2364 | return 0; | |
2365 | ||
c6ddc5f3 CW |
2366 | err = intel_wait_for_register(dev_priv, |
2367 | VLV_GTLC_SURVIVABILITY_REG, | |
2368 | VLV_GFX_CLK_STATUS_BIT, | |
2369 | VLV_GFX_CLK_STATUS_BIT, | |
2370 | 20); | |
650ad970 ID |
2371 | if (err) |
2372 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
2373 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
2374 | ||
2375 | return err; | |
650ad970 ID |
2376 | } |
2377 | ||
ddeea5b0 ID |
2378 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
2379 | { | |
3dd14c04 | 2380 | u32 mask; |
ddeea5b0 | 2381 | u32 val; |
3dd14c04 | 2382 | int err; |
ddeea5b0 ID |
2383 | |
2384 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2385 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
2386 | if (allow) | |
2387 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
2388 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2389 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
2390 | ||
3dd14c04 CW |
2391 | mask = VLV_GTLC_ALLOWWAKEACK; |
2392 | val = allow ? mask : 0; | |
2393 | ||
2394 | err = vlv_wait_for_pw_status(dev_priv, mask, val); | |
ddeea5b0 ID |
2395 | if (err) |
2396 | DRM_ERROR("timeout disabling GT waking\n"); | |
b2736695 | 2397 | |
ddeea5b0 | 2398 | return err; |
ddeea5b0 ID |
2399 | } |
2400 | ||
3dd14c04 CW |
2401 | static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, |
2402 | bool wait_for_on) | |
ddeea5b0 ID |
2403 | { |
2404 | u32 mask; | |
2405 | u32 val; | |
ddeea5b0 ID |
2406 | |
2407 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
2408 | val = wait_for_on ? mask : 0; | |
ddeea5b0 ID |
2409 | |
2410 | /* | |
2411 | * RC6 transitioning can be delayed up to 2 msec (see | |
2412 | * valleyview_enable_rps), use 3 msec for safety. | |
2413 | */ | |
3dd14c04 | 2414 | if (vlv_wait_for_pw_status(dev_priv, mask, val)) |
ddeea5b0 | 2415 | DRM_ERROR("timeout waiting for GT wells to go %s\n", |
87ad3212 | 2416 | onoff(wait_for_on)); |
ddeea5b0 ID |
2417 | } |
2418 | ||
2419 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
2420 | { | |
2421 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
2422 | return; | |
2423 | ||
6fa283b0 | 2424 | DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); |
ddeea5b0 ID |
2425 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
2426 | } | |
2427 | ||
ebc32824 | 2428 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
2429 | { |
2430 | u32 mask; | |
2431 | int err; | |
2432 | ||
2433 | /* | |
2434 | * Bspec defines the following GT well on flags as debug only, so | |
2435 | * don't treat them as hard failures. | |
2436 | */ | |
3dd14c04 | 2437 | vlv_wait_for_gt_wells(dev_priv, false); |
ddeea5b0 ID |
2438 | |
2439 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
2440 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
2441 | ||
2442 | vlv_check_no_gt_access(dev_priv); | |
2443 | ||
2444 | err = vlv_force_gfx_clock(dev_priv, true); | |
2445 | if (err) | |
2446 | goto err1; | |
2447 | ||
2448 | err = vlv_allow_gt_wake(dev_priv, false); | |
2449 | if (err) | |
2450 | goto err2; | |
98711167 | 2451 | |
2d1fe073 | 2452 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 2453 | vlv_save_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2454 | |
2455 | err = vlv_force_gfx_clock(dev_priv, false); | |
2456 | if (err) | |
2457 | goto err2; | |
2458 | ||
2459 | return 0; | |
2460 | ||
2461 | err2: | |
2462 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
2463 | vlv_allow_gt_wake(dev_priv, true); | |
2464 | err1: | |
2465 | vlv_force_gfx_clock(dev_priv, false); | |
2466 | ||
2467 | return err; | |
2468 | } | |
2469 | ||
016970be SK |
2470 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
2471 | bool rpm_resume) | |
ddeea5b0 | 2472 | { |
ddeea5b0 ID |
2473 | int err; |
2474 | int ret; | |
2475 | ||
2476 | /* | |
2477 | * If any of the steps fail just try to continue, that's the best we | |
2478 | * can do at this point. Return the first error code (which will also | |
2479 | * leave RPM permanently disabled). | |
2480 | */ | |
2481 | ret = vlv_force_gfx_clock(dev_priv, true); | |
2482 | ||
2d1fe073 | 2483 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 2484 | vlv_restore_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2485 | |
2486 | err = vlv_allow_gt_wake(dev_priv, true); | |
2487 | if (!ret) | |
2488 | ret = err; | |
2489 | ||
2490 | err = vlv_force_gfx_clock(dev_priv, false); | |
2491 | if (!ret) | |
2492 | ret = err; | |
2493 | ||
2494 | vlv_check_no_gt_access(dev_priv); | |
2495 | ||
7c108fd8 | 2496 | if (rpm_resume) |
46f16e63 | 2497 | intel_init_clock_gating(dev_priv); |
ddeea5b0 ID |
2498 | |
2499 | return ret; | |
2500 | } | |
2501 | ||
c49d13ee | 2502 | static int intel_runtime_suspend(struct device *kdev) |
8a187455 | 2503 | { |
c49d13ee | 2504 | struct pci_dev *pdev = to_pci_dev(kdev); |
8a187455 | 2505 | struct drm_device *dev = pci_get_drvdata(pdev); |
fac5e23e | 2506 | struct drm_i915_private *dev_priv = to_i915(dev); |
0ab9cfeb | 2507 | int ret; |
8a187455 | 2508 | |
37d933fc | 2509 | if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled()))) |
c6df39b5 ID |
2510 | return -ENODEV; |
2511 | ||
6772ffe0 | 2512 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 ID |
2513 | return -ENODEV; |
2514 | ||
8a187455 PZ |
2515 | DRM_DEBUG_KMS("Suspending device\n"); |
2516 | ||
1f814dac ID |
2517 | disable_rpm_wakeref_asserts(dev_priv); |
2518 | ||
d6102977 ID |
2519 | /* |
2520 | * We are safe here against re-faults, since the fault handler takes | |
2521 | * an RPM reference. | |
2522 | */ | |
7c108fd8 | 2523 | i915_gem_runtime_suspend(dev_priv); |
d6102977 | 2524 | |
bf9e8429 | 2525 | intel_guc_suspend(dev_priv); |
a1c41994 | 2526 | |
2eb5252e | 2527 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 2528 | |
507e126e | 2529 | ret = 0; |
b9fd799e | 2530 | if (IS_GEN9_LP(dev_priv)) { |
507e126e ID |
2531 | bxt_display_core_uninit(dev_priv); |
2532 | bxt_enable_dc9(dev_priv); | |
2533 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { | |
2534 | hsw_enable_pc8(dev_priv); | |
2535 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
2536 | ret = vlv_suspend_complete(dev_priv); | |
2537 | } | |
2538 | ||
0ab9cfeb ID |
2539 | if (ret) { |
2540 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
b963291c | 2541 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb | 2542 | |
1f814dac ID |
2543 | enable_rpm_wakeref_asserts(dev_priv); |
2544 | ||
0ab9cfeb ID |
2545 | return ret; |
2546 | } | |
a8a8bd54 | 2547 | |
68f60946 | 2548 | intel_uncore_suspend(dev_priv); |
1f814dac ID |
2549 | |
2550 | enable_rpm_wakeref_asserts(dev_priv); | |
ad1443f0 | 2551 | WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count)); |
55ec45c2 | 2552 | |
bc3b9346 | 2553 | if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) |
55ec45c2 MK |
2554 | DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
2555 | ||
ad1443f0 | 2556 | dev_priv->runtime_pm.suspended = true; |
1fb2362b KCA |
2557 | |
2558 | /* | |
c8a0bd42 PZ |
2559 | * FIXME: We really should find a document that references the arguments |
2560 | * used below! | |
1fb2362b | 2561 | */ |
6f9f4b7a | 2562 | if (IS_BROADWELL(dev_priv)) { |
d37ae19a PZ |
2563 | /* |
2564 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
2565 | * being detected, and the call we do at intel_runtime_resume() | |
2566 | * won't be able to restore them. Since PCI_D3hot matches the | |
2567 | * actual specification and appears to be working, use it. | |
2568 | */ | |
6f9f4b7a | 2569 | intel_opregion_notify_adapter(dev_priv, PCI_D3hot); |
d37ae19a | 2570 | } else { |
c8a0bd42 PZ |
2571 | /* |
2572 | * current versions of firmware which depend on this opregion | |
2573 | * notification have repurposed the D1 definition to mean | |
2574 | * "runtime suspended" vs. what you would normally expect (D3) | |
2575 | * to distinguish it from notifications that might be sent via | |
2576 | * the suspend path. | |
2577 | */ | |
6f9f4b7a | 2578 | intel_opregion_notify_adapter(dev_priv, PCI_D1); |
c8a0bd42 | 2579 | } |
8a187455 | 2580 | |
59bad947 | 2581 | assert_forcewakes_inactive(dev_priv); |
dc9fb09c | 2582 | |
21d6e0bd | 2583 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
19625e85 L |
2584 | intel_hpd_poll_init(dev_priv); |
2585 | ||
a8a8bd54 | 2586 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
2587 | return 0; |
2588 | } | |
2589 | ||
c49d13ee | 2590 | static int intel_runtime_resume(struct device *kdev) |
8a187455 | 2591 | { |
c49d13ee | 2592 | struct pci_dev *pdev = to_pci_dev(kdev); |
8a187455 | 2593 | struct drm_device *dev = pci_get_drvdata(pdev); |
fac5e23e | 2594 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a5df187 | 2595 | int ret = 0; |
8a187455 | 2596 | |
6772ffe0 | 2597 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 | 2598 | return -ENODEV; |
8a187455 PZ |
2599 | |
2600 | DRM_DEBUG_KMS("Resuming device\n"); | |
2601 | ||
ad1443f0 | 2602 | WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count)); |
1f814dac ID |
2603 | disable_rpm_wakeref_asserts(dev_priv); |
2604 | ||
6f9f4b7a | 2605 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
ad1443f0 | 2606 | dev_priv->runtime_pm.suspended = false; |
55ec45c2 MK |
2607 | if (intel_uncore_unclaimed_mmio(dev_priv)) |
2608 | DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); | |
8a187455 | 2609 | |
bf9e8429 | 2610 | intel_guc_resume(dev_priv); |
a1c41994 | 2611 | |
b9fd799e | 2612 | if (IS_GEN9_LP(dev_priv)) { |
507e126e ID |
2613 | bxt_disable_dc9(dev_priv); |
2614 | bxt_display_core_init(dev_priv, true); | |
f62c79b3 ID |
2615 | if (dev_priv->csr.dmc_payload && |
2616 | (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) | |
2617 | gen9_enable_dc5(dev_priv); | |
507e126e | 2618 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1a5df187 | 2619 | hsw_disable_pc8(dev_priv); |
507e126e | 2620 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
1a5df187 | 2621 | ret = vlv_resume_prepare(dev_priv, true); |
507e126e | 2622 | } |
1a5df187 | 2623 | |
0ab9cfeb ID |
2624 | /* |
2625 | * No point of rolling back things in case of an error, as the best | |
2626 | * we can do is to hope that things will still work (and disable RPM). | |
2627 | */ | |
c6be607a | 2628 | i915_gem_init_swizzling(dev_priv); |
83bf6d55 | 2629 | i915_gem_restore_fences(dev_priv); |
92b806d3 | 2630 | |
b963291c | 2631 | intel_runtime_pm_enable_interrupts(dev_priv); |
08d8a232 VS |
2632 | |
2633 | /* | |
2634 | * On VLV/CHV display interrupts are part of the display | |
2635 | * power well, so hpd is reinitialized from there. For | |
2636 | * everyone else do it here. | |
2637 | */ | |
666a4537 | 2638 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
08d8a232 VS |
2639 | intel_hpd_init(dev_priv); |
2640 | ||
2503a0fe KM |
2641 | intel_enable_ipc(dev_priv); |
2642 | ||
1f814dac ID |
2643 | enable_rpm_wakeref_asserts(dev_priv); |
2644 | ||
0ab9cfeb ID |
2645 | if (ret) |
2646 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
2647 | else | |
2648 | DRM_DEBUG_KMS("Device resumed\n"); | |
2649 | ||
2650 | return ret; | |
8a187455 PZ |
2651 | } |
2652 | ||
42f5551d | 2653 | const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
2654 | /* |
2655 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
2656 | * PMSG_RESUME] | |
2657 | */ | |
0206e353 | 2658 | .suspend = i915_pm_suspend, |
76c4b250 ID |
2659 | .suspend_late = i915_pm_suspend_late, |
2660 | .resume_early = i915_pm_resume_early, | |
0206e353 | 2661 | .resume = i915_pm_resume, |
5545dbbf ID |
2662 | |
2663 | /* | |
2664 | * S4 event handlers | |
2665 | * @freeze, @freeze_late : called (1) before creating the | |
2666 | * hibernation image [PMSG_FREEZE] and | |
2667 | * (2) after rebooting, before restoring | |
2668 | * the image [PMSG_QUIESCE] | |
2669 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
2670 | * image, before writing it [PMSG_THAW] | |
2671 | * and (2) after failing to create or | |
2672 | * restore the image [PMSG_RECOVER] | |
2673 | * @poweroff, @poweroff_late: called after writing the hibernation | |
2674 | * image, before rebooting [PMSG_HIBERNATE] | |
2675 | * @restore, @restore_early : called after rebooting and restoring the | |
2676 | * hibernation image [PMSG_RESTORE] | |
2677 | */ | |
1f19ac2a CW |
2678 | .freeze = i915_pm_freeze, |
2679 | .freeze_late = i915_pm_freeze_late, | |
2680 | .thaw_early = i915_pm_thaw_early, | |
2681 | .thaw = i915_pm_thaw, | |
36d61e67 | 2682 | .poweroff = i915_pm_suspend, |
ab3be73f | 2683 | .poweroff_late = i915_pm_poweroff_late, |
1f19ac2a CW |
2684 | .restore_early = i915_pm_restore_early, |
2685 | .restore = i915_pm_restore, | |
5545dbbf ID |
2686 | |
2687 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
2688 | .runtime_suspend = intel_runtime_suspend, |
2689 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
2690 | }; |
2691 | ||
78b68556 | 2692 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 2693 | .fault = i915_gem_fault, |
ab00b3e5 JB |
2694 | .open = drm_gem_vm_open, |
2695 | .close = drm_gem_vm_close, | |
de151cf6 JB |
2696 | }; |
2697 | ||
e08e96de AV |
2698 | static const struct file_operations i915_driver_fops = { |
2699 | .owner = THIS_MODULE, | |
2700 | .open = drm_open, | |
2701 | .release = drm_release, | |
2702 | .unlocked_ioctl = drm_ioctl, | |
2703 | .mmap = drm_gem_mmap, | |
2704 | .poll = drm_poll, | |
e08e96de | 2705 | .read = drm_read, |
e08e96de | 2706 | .compat_ioctl = i915_compat_ioctl, |
e08e96de AV |
2707 | .llseek = noop_llseek, |
2708 | }; | |
2709 | ||
0673ad47 CW |
2710 | static int |
2711 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
2712 | struct drm_file *file) | |
2713 | { | |
2714 | return -ENODEV; | |
2715 | } | |
2716 | ||
2717 | static const struct drm_ioctl_desc i915_ioctls[] = { | |
2718 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2719 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
2720 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
2721 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
2722 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
2723 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
2724 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), | |
2725 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2726 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), | |
2727 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
2728 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2729 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), | |
2730 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2731 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2732 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), | |
2733 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
2734 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2735 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2736 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), | |
fec0445c | 2737 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW), |
0673ad47 CW |
2738 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), |
2739 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
2740 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
2741 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), | |
2742 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), | |
2743 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
2744 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2745 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2746 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), | |
2747 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), | |
2748 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), | |
2749 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), | |
2750 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW), | |
2751 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), | |
2752 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), | |
111dbcab CW |
2753 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), |
2754 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), | |
0673ad47 CW |
2755 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), |
2756 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), | |
2757 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), | |
2758 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), | |
2759 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), | |
2760 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW), | |
2761 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW), | |
2762 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
2763 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), | |
2764 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), | |
2765 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), | |
2766 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), | |
2767 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), | |
2768 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), | |
2769 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), | |
eec688e1 | 2770 | DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), |
f89823c2 LL |
2771 | DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
2772 | DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
0673ad47 CW |
2773 | }; |
2774 | ||
1da177e4 | 2775 | static struct drm_driver driver = { |
0c54781b MW |
2776 | /* Don't use MTRRs here; the Xserver or userspace app should |
2777 | * deal with them for Intel hardware. | |
792d2b9a | 2778 | */ |
673a394b | 2779 | .driver_features = |
10ba5012 | 2780 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
cf6e7bac | 2781 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ, |
cad3688f | 2782 | .release = i915_driver_release, |
673a394b | 2783 | .open = i915_driver_open, |
22eae947 | 2784 | .lastclose = i915_driver_lastclose, |
673a394b | 2785 | .postclose = i915_driver_postclose, |
d8e29209 | 2786 | |
b1f788c6 | 2787 | .gem_close_object = i915_gem_close_object, |
f0cd5182 | 2788 | .gem_free_object_unlocked = i915_gem_free_object, |
de151cf6 | 2789 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
2790 | |
2791 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
2792 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
2793 | .gem_prime_export = i915_gem_prime_export, | |
2794 | .gem_prime_import = i915_gem_prime_import, | |
2795 | ||
ff72145b | 2796 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 2797 | .dumb_map_offset = i915_gem_mmap_gtt, |
1da177e4 | 2798 | .ioctls = i915_ioctls, |
0673ad47 | 2799 | .num_ioctls = ARRAY_SIZE(i915_ioctls), |
e08e96de | 2800 | .fops = &i915_driver_fops, |
22eae947 DA |
2801 | .name = DRIVER_NAME, |
2802 | .desc = DRIVER_DESC, | |
2803 | .date = DRIVER_DATE, | |
2804 | .major = DRIVER_MAJOR, | |
2805 | .minor = DRIVER_MINOR, | |
2806 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 | 2807 | }; |
66d9cb5d CW |
2808 | |
2809 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
2810 | #include "selftests/mock_drm.c" | |
2811 | #endif |