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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
e5747e3a | 30 | #include <linux/acpi.h> |
0673ad47 CW |
31 | #include <linux/device.h> |
32 | #include <linux/oom.h> | |
e0cd3608 | 33 | #include <linux/module.h> |
0673ad47 CW |
34 | #include <linux/pci.h> |
35 | #include <linux/pm.h> | |
d6102977 | 36 | #include <linux/pm_runtime.h> |
0673ad47 CW |
37 | #include <linux/pnp.h> |
38 | #include <linux/slab.h> | |
704ab614 | 39 | #include <linux/vga_switcheroo.h> |
0673ad47 CW |
40 | #include <linux/vt.h> |
41 | #include <acpi/video.h> | |
42 | ||
a667fb40 | 43 | #include <drm/drm_atomic_helper.h> |
d0e93599 SR |
44 | #include <drm/drm_ioctl.h> |
45 | #include <drm/drm_irq.h> | |
46 | #include <drm/drm_probe_helper.h> | |
0673ad47 CW |
47 | #include <drm/i915_drm.h> |
48 | ||
df0566a6 JN |
49 | #include "display/intel_acpi.h" |
50 | #include "display/intel_audio.h" | |
51 | #include "display/intel_bw.h" | |
52 | #include "display/intel_cdclk.h" | |
1d455f8d | 53 | #include "display/intel_display_types.h" |
379bc100 | 54 | #include "display/intel_dp.h" |
df0566a6 | 55 | #include "display/intel_fbdev.h" |
df0566a6 JN |
56 | #include "display/intel_hotplug.h" |
57 | #include "display/intel_overlay.h" | |
58 | #include "display/intel_pipe_crc.h" | |
33e059a2 | 59 | #include "display/intel_psr.h" |
df0566a6 | 60 | #include "display/intel_sprite.h" |
4fb87831 | 61 | #include "display/intel_vga.h" |
379bc100 | 62 | |
10be98a7 | 63 | #include "gem/i915_gem_context.h" |
afa13085 | 64 | #include "gem/i915_gem_ioctls.h" |
cc662126 | 65 | #include "gem/i915_gem_mman.h" |
24635c51 | 66 | #include "gt/intel_gt.h" |
79ffac85 | 67 | #include "gt/intel_gt_pm.h" |
2248a283 | 68 | #include "gt/intel_rc6.h" |
112ed2d3 | 69 | |
2126d3e9 | 70 | #include "i915_debugfs.h" |
0673ad47 | 71 | #include "i915_drv.h" |
440e2b3d | 72 | #include "i915_irq.h" |
9c9082b9 | 73 | #include "i915_memcpy.h" |
db94e9f1 | 74 | #include "i915_perf.h" |
a446ae2c | 75 | #include "i915_query.h" |
bdd1510c | 76 | #include "i915_suspend.h" |
63bf8301 | 77 | #include "i915_switcheroo.h" |
be68261d | 78 | #include "i915_sysfs.h" |
331c201a | 79 | #include "i915_trace.h" |
0673ad47 | 80 | #include "i915_vgpu.h" |
174594db | 81 | #include "intel_csr.h" |
3fc794f2 | 82 | #include "intel_memory_region.h" |
696173b0 | 83 | #include "intel_pm.h" |
79e53945 | 84 | |
112b715e KH |
85 | static struct drm_driver driver; |
86 | ||
1bcd8688 DCS |
87 | struct vlv_s0ix_state { |
88 | /* GAM */ | |
89 | u32 wr_watermark; | |
90 | u32 gfx_prio_ctrl; | |
91 | u32 arb_mode; | |
92 | u32 gfx_pend_tlb0; | |
93 | u32 gfx_pend_tlb1; | |
94 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
95 | u32 media_max_req_count; | |
96 | u32 gfx_max_req_count; | |
97 | u32 render_hwsp; | |
98 | u32 ecochk; | |
99 | u32 bsd_hwsp; | |
100 | u32 blt_hwsp; | |
101 | u32 tlb_rd_addr; | |
102 | ||
103 | /* MBC */ | |
104 | u32 g3dctl; | |
105 | u32 gsckgctl; | |
106 | u32 mbctl; | |
107 | ||
108 | /* GCP */ | |
109 | u32 ucgctl1; | |
110 | u32 ucgctl3; | |
111 | u32 rcgctl1; | |
112 | u32 rcgctl2; | |
113 | u32 rstctl; | |
114 | u32 misccpctl; | |
115 | ||
116 | /* GPM */ | |
117 | u32 gfxpause; | |
118 | u32 rpdeuhwtc; | |
119 | u32 rpdeuc; | |
120 | u32 ecobus; | |
121 | u32 pwrdwnupctl; | |
122 | u32 rp_down_timeout; | |
123 | u32 rp_deucsw; | |
124 | u32 rcubmabdtmr; | |
125 | u32 rcedata; | |
126 | u32 spare2gh; | |
127 | ||
128 | /* Display 1 CZ domain */ | |
129 | u32 gt_imr; | |
130 | u32 gt_ier; | |
131 | u32 pm_imr; | |
132 | u32 pm_ier; | |
133 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
134 | ||
135 | /* GT SA CZ domain */ | |
136 | u32 tilectl; | |
137 | u32 gt_fifoctl; | |
138 | u32 gtlc_wake_ctrl; | |
139 | u32 gtlc_survive; | |
140 | u32 pmwgicz; | |
141 | ||
142 | /* Display 2 CZ domain */ | |
143 | u32 gu_ctl0; | |
144 | u32 gu_ctl1; | |
145 | u32 pcbr; | |
146 | u32 clock_gate_dis2; | |
147 | }; | |
148 | ||
da5f53bf | 149 | static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) |
0673ad47 | 150 | { |
57b29646 SK |
151 | int domain = pci_domain_nr(dev_priv->drm.pdev->bus); |
152 | ||
153 | dev_priv->bridge_dev = | |
154 | pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); | |
0673ad47 CW |
155 | if (!dev_priv->bridge_dev) { |
156 | DRM_ERROR("bridge device not found\n"); | |
157 | return -1; | |
158 | } | |
159 | return 0; | |
160 | } | |
161 | ||
162 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
163 | static int | |
da5f53bf | 164 | intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) |
0673ad47 | 165 | { |
514e1d64 | 166 | int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
167 | u32 temp_lo, temp_hi = 0; |
168 | u64 mchbar_addr; | |
169 | int ret; | |
170 | ||
514e1d64 | 171 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
172 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
173 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
174 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
175 | ||
176 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
177 | #ifdef CONFIG_PNP | |
178 | if (mchbar_addr && | |
179 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) | |
180 | return 0; | |
181 | #endif | |
182 | ||
183 | /* Get some space for it */ | |
184 | dev_priv->mch_res.name = "i915 MCHBAR"; | |
185 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
186 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
187 | &dev_priv->mch_res, | |
188 | MCHBAR_SIZE, MCHBAR_SIZE, | |
189 | PCIBIOS_MIN_MEM, | |
190 | 0, pcibios_align_resource, | |
191 | dev_priv->bridge_dev); | |
192 | if (ret) { | |
193 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
194 | dev_priv->mch_res.start = 0; | |
195 | return ret; | |
196 | } | |
197 | ||
514e1d64 | 198 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
199 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
200 | upper_32_bits(dev_priv->mch_res.start)); | |
201 | ||
202 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
203 | lower_32_bits(dev_priv->mch_res.start)); | |
204 | return 0; | |
205 | } | |
206 | ||
207 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
208 | static void | |
da5f53bf | 209 | intel_setup_mchbar(struct drm_i915_private *dev_priv) |
0673ad47 | 210 | { |
514e1d64 | 211 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
212 | u32 temp; |
213 | bool enabled; | |
214 | ||
920a14b2 | 215 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
0673ad47 CW |
216 | return; |
217 | ||
218 | dev_priv->mchbar_need_disable = false; | |
219 | ||
50a0bc90 | 220 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
221 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); |
222 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
223 | } else { | |
224 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
225 | enabled = temp & 1; | |
226 | } | |
227 | ||
228 | /* If it's already enabled, don't have to do anything */ | |
229 | if (enabled) | |
230 | return; | |
231 | ||
da5f53bf | 232 | if (intel_alloc_mchbar_resource(dev_priv)) |
0673ad47 CW |
233 | return; |
234 | ||
235 | dev_priv->mchbar_need_disable = true; | |
236 | ||
237 | /* Space is allocated or reserved, so enable it. */ | |
50a0bc90 | 238 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
239 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, |
240 | temp | DEVEN_MCHBAR_EN); | |
241 | } else { | |
242 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
243 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
244 | } | |
245 | } | |
246 | ||
247 | static void | |
da5f53bf | 248 | intel_teardown_mchbar(struct drm_i915_private *dev_priv) |
0673ad47 | 249 | { |
514e1d64 | 250 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
251 | |
252 | if (dev_priv->mchbar_need_disable) { | |
50a0bc90 | 253 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
254 | u32 deven_val; |
255 | ||
256 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, | |
257 | &deven_val); | |
258 | deven_val &= ~DEVEN_MCHBAR_EN; | |
259 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, | |
260 | deven_val); | |
261 | } else { | |
262 | u32 mchbar_val; | |
263 | ||
264 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
265 | &mchbar_val); | |
266 | mchbar_val &= ~1; | |
267 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
268 | mchbar_val); | |
269 | } | |
270 | } | |
271 | ||
272 | if (dev_priv->mch_res.start) | |
273 | release_resource(&dev_priv->mch_res); | |
274 | } | |
275 | ||
5bcd53aa | 276 | static int i915_driver_modeset_probe(struct drm_i915_private *i915) |
0673ad47 | 277 | { |
0673ad47 CW |
278 | int ret; |
279 | ||
5bcd53aa | 280 | if (i915_inject_probe_failure(i915)) |
0673ad47 CW |
281 | return -ENODEV; |
282 | ||
5bcd53aa JN |
283 | if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) { |
284 | ret = drm_vblank_init(&i915->drm, | |
285 | INTEL_NUM_PIPES(i915)); | |
8d3bf1a3 JRS |
286 | if (ret) |
287 | goto out; | |
288 | } | |
289 | ||
5bcd53aa | 290 | intel_bios_init(i915); |
0673ad47 | 291 | |
4fb87831 JN |
292 | ret = intel_vga_register(i915); |
293 | if (ret) | |
0673ad47 CW |
294 | goto out; |
295 | ||
296 | intel_register_dsm_handler(); | |
297 | ||
63bf8301 | 298 | ret = i915_switcheroo_register(i915); |
0673ad47 CW |
299 | if (ret) |
300 | goto cleanup_vga_client; | |
301 | ||
5bcd53aa | 302 | intel_power_domains_init_hw(i915, false); |
0673ad47 | 303 | |
5bcd53aa | 304 | intel_csr_ucode_init(i915); |
0673ad47 | 305 | |
5bcd53aa | 306 | ret = intel_irq_install(i915); |
0673ad47 CW |
307 | if (ret) |
308 | goto cleanup_csr; | |
309 | ||
0673ad47 CW |
310 | /* Important: The output setup functions called by modeset_init need |
311 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
6cd02e77 | 312 | ret = intel_modeset_init(i915); |
b079bd17 VS |
313 | if (ret) |
314 | goto cleanup_irq; | |
0673ad47 | 315 | |
5bcd53aa | 316 | ret = i915_gem_init(i915); |
0673ad47 | 317 | if (ret) |
73bad7ca | 318 | goto cleanup_modeset; |
0673ad47 | 319 | |
5bcd53aa | 320 | intel_overlay_setup(i915); |
0673ad47 | 321 | |
5bcd53aa | 322 | if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915)) |
0673ad47 CW |
323 | return 0; |
324 | ||
5bcd53aa | 325 | ret = intel_fbdev_init(&i915->drm); |
0673ad47 CW |
326 | if (ret) |
327 | goto cleanup_gem; | |
328 | ||
329 | /* Only enable hotplug handling once the fbdev is fully set up. */ | |
5bcd53aa | 330 | intel_hpd_init(i915); |
0673ad47 | 331 | |
5bcd53aa | 332 | intel_init_ipc(i915); |
a8147d0c | 333 | |
33e059a2 JRS |
334 | intel_psr_set_force_mode_changed(i915->psr.dp); |
335 | ||
0673ad47 CW |
336 | return 0; |
337 | ||
338 | cleanup_gem: | |
5bcd53aa JN |
339 | i915_gem_suspend(i915); |
340 | i915_gem_driver_remove(i915); | |
341 | i915_gem_driver_release(i915); | |
73bad7ca | 342 | cleanup_modeset: |
9980c3c1 | 343 | intel_modeset_driver_remove(i915); |
0673ad47 | 344 | cleanup_irq: |
5bcd53aa | 345 | intel_irq_uninstall(i915); |
0673ad47 | 346 | cleanup_csr: |
5bcd53aa JN |
347 | intel_csr_ucode_fini(i915); |
348 | intel_power_domains_driver_remove(i915); | |
63bf8301 | 349 | i915_switcheroo_unregister(i915); |
0673ad47 | 350 | cleanup_vga_client: |
4fb87831 | 351 | intel_vga_unregister(i915); |
0673ad47 CW |
352 | out: |
353 | return ret; | |
354 | } | |
355 | ||
2d6f6f35 JN |
356 | static void i915_driver_modeset_remove(struct drm_i915_private *i915) |
357 | { | |
9980c3c1 | 358 | intel_modeset_driver_remove(i915); |
2d6f6f35 | 359 | |
789fa874 JK |
360 | intel_irq_uninstall(i915); |
361 | ||
2d6f6f35 JN |
362 | intel_bios_driver_remove(i915); |
363 | ||
63bf8301 JN |
364 | i915_switcheroo_unregister(i915); |
365 | ||
4fb87831 | 366 | intel_vga_unregister(i915); |
2d6f6f35 JN |
367 | |
368 | intel_csr_ucode_fini(i915); | |
369 | } | |
370 | ||
0673ad47 CW |
371 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
372 | { | |
373 | /* | |
374 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
375 | * CHV x1 PHY (DP/HDMI D) | |
376 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
377 | */ | |
378 | if (IS_CHERRYVIEW(dev_priv)) { | |
379 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
380 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
381 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
382 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
383 | } | |
384 | } | |
385 | ||
386 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) | |
387 | { | |
388 | /* | |
389 | * The i915 workqueue is primarily used for batched retirement of | |
390 | * requests (and thus managing bo) once the task has been completed | |
e61e0f51 | 391 | * by the GPU. i915_retire_requests() is called directly when we |
0673ad47 CW |
392 | * need high-priority retirement, such as waiting for an explicit |
393 | * bo. | |
394 | * | |
395 | * It is also used for periodic low-priority events, such as | |
396 | * idle-timers and recording error state. | |
397 | * | |
398 | * All tasks on the workqueue are expected to acquire the dev mutex | |
399 | * so there is no point in running more than one instance of the | |
400 | * workqueue at any time. Use an ordered one. | |
401 | */ | |
402 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); | |
403 | if (dev_priv->wq == NULL) | |
404 | goto out_err; | |
405 | ||
406 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); | |
407 | if (dev_priv->hotplug.dp_wq == NULL) | |
408 | goto out_free_wq; | |
409 | ||
0673ad47 CW |
410 | return 0; |
411 | ||
0673ad47 CW |
412 | out_free_wq: |
413 | destroy_workqueue(dev_priv->wq); | |
414 | out_err: | |
415 | DRM_ERROR("Failed to allocate workqueues.\n"); | |
416 | ||
417 | return -ENOMEM; | |
418 | } | |
419 | ||
420 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) | |
421 | { | |
0673ad47 CW |
422 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
423 | destroy_workqueue(dev_priv->wq); | |
424 | } | |
425 | ||
4fc7e845 PZ |
426 | /* |
427 | * We don't keep the workarounds for pre-production hardware, so we expect our | |
428 | * driver to fail on these machines in one way or another. A little warning on | |
429 | * dmesg may help both the user and the bug triagers. | |
6a7a6a98 CW |
430 | * |
431 | * Our policy for removing pre-production workarounds is to keep the | |
432 | * current gen workarounds as a guide to the bring-up of the next gen | |
433 | * (workarounds have a habit of persisting!). Anything older than that | |
434 | * should be removed along with the complications they introduce. | |
4fc7e845 PZ |
435 | */ |
436 | static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) | |
437 | { | |
248a124d CW |
438 | bool pre = false; |
439 | ||
440 | pre |= IS_HSW_EARLY_SDV(dev_priv); | |
441 | pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0); | |
0102ba1f | 442 | pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST); |
1aca96cc | 443 | pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0); |
248a124d | 444 | |
7c5ff4a2 | 445 | if (pre) { |
4fc7e845 PZ |
446 | DRM_ERROR("This is a pre-production stepping. " |
447 | "It may not be fully functional.\n"); | |
7c5ff4a2 CW |
448 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); |
449 | } | |
4fc7e845 PZ |
450 | } |
451 | ||
1bcd8688 DCS |
452 | static int vlv_alloc_s0ix_state(struct drm_i915_private *i915) |
453 | { | |
454 | if (!IS_VALLEYVIEW(i915)) | |
455 | return 0; | |
456 | ||
457 | /* we write all the values in the struct, so no need to zero it out */ | |
458 | i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state), | |
459 | GFP_KERNEL); | |
460 | if (!i915->vlv_s0ix_state) | |
461 | return -ENOMEM; | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static void vlv_free_s0ix_state(struct drm_i915_private *i915) | |
467 | { | |
468 | if (!i915->vlv_s0ix_state) | |
469 | return; | |
470 | ||
471 | kfree(i915->vlv_s0ix_state); | |
472 | i915->vlv_s0ix_state = NULL; | |
473 | } | |
474 | ||
640b50fa CW |
475 | static void sanitize_gpu(struct drm_i915_private *i915) |
476 | { | |
477 | if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) | |
478 | __intel_gt_reset(&i915->gt, ALL_ENGINES); | |
479 | } | |
480 | ||
0673ad47 | 481 | /** |
0b61b8b0 | 482 | * i915_driver_early_probe - setup state not requiring device access |
0673ad47 CW |
483 | * @dev_priv: device private |
484 | * | |
485 | * Initialize everything that is a "SW-only" state, that is state not | |
486 | * requiring accessing the device or exposing the driver via kernel internal | |
487 | * or userspace interfaces. Example steps belonging here: lock initialization, | |
488 | * system memory allocation, setting up device specific attributes and | |
489 | * function hooks not requiring accessing the device. | |
490 | */ | |
0b61b8b0 | 491 | static int i915_driver_early_probe(struct drm_i915_private *dev_priv) |
0673ad47 | 492 | { |
0673ad47 CW |
493 | int ret = 0; |
494 | ||
50d84418 | 495 | if (i915_inject_probe_failure(dev_priv)) |
0673ad47 CW |
496 | return -ENODEV; |
497 | ||
805446c8 TU |
498 | intel_device_info_subplatform_init(dev_priv); |
499 | ||
0a9b2630 | 500 | intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); |
01385758 | 501 | intel_uncore_init_early(&dev_priv->uncore, dev_priv); |
6cbe8830 | 502 | |
0673ad47 CW |
503 | spin_lock_init(&dev_priv->irq_lock); |
504 | spin_lock_init(&dev_priv->gpu_error.lock); | |
505 | mutex_init(&dev_priv->backlight_lock); | |
317eaa95 | 506 | |
0673ad47 | 507 | mutex_init(&dev_priv->sb_lock); |
a75d035f CW |
508 | pm_qos_add_request(&dev_priv->sb_qos, |
509 | PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); | |
510 | ||
0673ad47 CW |
511 | mutex_init(&dev_priv->av_mutex); |
512 | mutex_init(&dev_priv->wm.wm_mutex); | |
513 | mutex_init(&dev_priv->pps_mutex); | |
9055aac7 | 514 | mutex_init(&dev_priv->hdcp_comp_mutex); |
0673ad47 | 515 | |
0b1de5d5 | 516 | i915_memcpy_init_early(dev_priv); |
69c66355 | 517 | intel_runtime_pm_init_early(&dev_priv->runtime_pm); |
0b1de5d5 | 518 | |
0673ad47 CW |
519 | ret = i915_workqueues_init(dev_priv); |
520 | if (ret < 0) | |
f3bcb0cc | 521 | return ret; |
0673ad47 | 522 | |
1bcd8688 DCS |
523 | ret = vlv_alloc_s0ix_state(dev_priv); |
524 | if (ret < 0) | |
525 | goto err_workqueues; | |
526 | ||
6f76098f DCS |
527 | intel_wopcm_init_early(&dev_priv->wopcm); |
528 | ||
724e9564 | 529 | intel_gt_init_early(&dev_priv->gt, dev_priv); |
24635c51 | 530 | |
a3f356b2 | 531 | i915_gem_init_early(dev_priv); |
a0de908d | 532 | |
0673ad47 | 533 | /* This must be called before any calls to HAS_PCH_* */ |
da5f53bf | 534 | intel_detect_pch(dev_priv); |
0673ad47 | 535 | |
192aa181 | 536 | intel_pm_setup(dev_priv); |
0673ad47 | 537 | intel_init_dpio(dev_priv); |
f28ec6f4 ID |
538 | ret = intel_power_domains_init(dev_priv); |
539 | if (ret < 0) | |
6f76098f | 540 | goto err_gem; |
0673ad47 CW |
541 | intel_irq_init(dev_priv); |
542 | intel_init_display_hooks(dev_priv); | |
543 | intel_init_clock_gating_hooks(dev_priv); | |
544 | intel_init_audio_hooks(dev_priv); | |
36cdd013 | 545 | intel_display_crc_init(dev_priv); |
0673ad47 | 546 | |
4fc7e845 | 547 | intel_detect_preproduction_hw(dev_priv); |
0673ad47 CW |
548 | |
549 | return 0; | |
550 | ||
6f76098f | 551 | err_gem: |
f28ec6f4 | 552 | i915_gem_cleanup_early(dev_priv); |
6cf72db6 | 553 | intel_gt_driver_late_release(&dev_priv->gt); |
1bcd8688 DCS |
554 | vlv_free_s0ix_state(dev_priv); |
555 | err_workqueues: | |
0673ad47 CW |
556 | i915_workqueues_cleanup(dev_priv); |
557 | return ret; | |
558 | } | |
559 | ||
560 | /** | |
3b58a945 | 561 | * i915_driver_late_release - cleanup the setup done in |
0b61b8b0 | 562 | * i915_driver_early_probe() |
0673ad47 CW |
563 | * @dev_priv: device private |
564 | */ | |
3b58a945 | 565 | static void i915_driver_late_release(struct drm_i915_private *dev_priv) |
0673ad47 | 566 | { |
cefcff8f | 567 | intel_irq_fini(dev_priv); |
f28ec6f4 | 568 | intel_power_domains_cleanup(dev_priv); |
a0de908d | 569 | i915_gem_cleanup_early(dev_priv); |
6cf72db6 | 570 | intel_gt_driver_late_release(&dev_priv->gt); |
1bcd8688 | 571 | vlv_free_s0ix_state(dev_priv); |
0673ad47 | 572 | i915_workqueues_cleanup(dev_priv); |
a75d035f CW |
573 | |
574 | pm_qos_remove_request(&dev_priv->sb_qos); | |
575 | mutex_destroy(&dev_priv->sb_lock); | |
0673ad47 CW |
576 | } |
577 | ||
0673ad47 | 578 | /** |
0b61b8b0 | 579 | * i915_driver_mmio_probe - setup device MMIO |
0673ad47 CW |
580 | * @dev_priv: device private |
581 | * | |
582 | * Setup minimal device state necessary for MMIO accesses later in the | |
583 | * initialization sequence. The setup here should avoid any other device-wide | |
584 | * side effects or exposing the driver via kernel internal or user space | |
585 | * interfaces. | |
586 | */ | |
0b61b8b0 | 587 | static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) |
0673ad47 | 588 | { |
0673ad47 CW |
589 | int ret; |
590 | ||
50d84418 | 591 | if (i915_inject_probe_failure(dev_priv)) |
0673ad47 CW |
592 | return -ENODEV; |
593 | ||
da5f53bf | 594 | if (i915_get_bridge_dev(dev_priv)) |
0673ad47 CW |
595 | return -EIO; |
596 | ||
3de6f852 | 597 | ret = intel_uncore_init_mmio(&dev_priv->uncore); |
0673ad47 | 598 | if (ret < 0) |
63ffbcda | 599 | goto err_bridge; |
0673ad47 | 600 | |
25286aac DCS |
601 | /* Try to make sure MCHBAR is enabled before poking at it */ |
602 | intel_setup_mchbar(dev_priv); | |
63ffbcda | 603 | |
26376a7e OM |
604 | intel_device_info_init_mmio(dev_priv); |
605 | ||
3de6f852 | 606 | intel_uncore_prune_mmio_domains(&dev_priv->uncore); |
26376a7e | 607 | |
ca7b2c1b | 608 | intel_uc_init_mmio(&dev_priv->gt.uc); |
1fc556fa | 609 | |
adcb5264 | 610 | ret = intel_engines_init_mmio(&dev_priv->gt); |
63ffbcda JL |
611 | if (ret) |
612 | goto err_uncore; | |
613 | ||
640b50fa CW |
614 | /* As early as possible, scrub existing GPU state before clobbering */ |
615 | sanitize_gpu(dev_priv); | |
616 | ||
0673ad47 CW |
617 | return 0; |
618 | ||
63ffbcda | 619 | err_uncore: |
25286aac | 620 | intel_teardown_mchbar(dev_priv); |
3de6f852 | 621 | intel_uncore_fini_mmio(&dev_priv->uncore); |
63ffbcda | 622 | err_bridge: |
0673ad47 CW |
623 | pci_dev_put(dev_priv->bridge_dev); |
624 | ||
625 | return ret; | |
626 | } | |
627 | ||
628 | /** | |
0b61b8b0 | 629 | * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() |
0673ad47 CW |
630 | * @dev_priv: device private |
631 | */ | |
3b58a945 | 632 | static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) |
0673ad47 | 633 | { |
25286aac | 634 | intel_teardown_mchbar(dev_priv); |
3de6f852 | 635 | intel_uncore_fini_mmio(&dev_priv->uncore); |
0673ad47 CW |
636 | pci_dev_put(dev_priv->bridge_dev); |
637 | } | |
638 | ||
94b4f3ba CW |
639 | static void intel_sanitize_options(struct drm_i915_private *dev_priv) |
640 | { | |
67b7f33e | 641 | intel_gvt_sanitize_options(dev_priv); |
94b4f3ba CW |
642 | } |
643 | ||
b185a352 VS |
644 | #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type |
645 | ||
646 | static const char *intel_dram_type_str(enum intel_dram_type type) | |
647 | { | |
648 | static const char * const str[] = { | |
649 | DRAM_TYPE_STR(UNKNOWN), | |
650 | DRAM_TYPE_STR(DDR3), | |
651 | DRAM_TYPE_STR(DDR4), | |
652 | DRAM_TYPE_STR(LPDDR3), | |
653 | DRAM_TYPE_STR(LPDDR4), | |
654 | }; | |
655 | ||
656 | if (type >= ARRAY_SIZE(str)) | |
657 | type = INTEL_DRAM_UNKNOWN; | |
658 | ||
659 | return str[type]; | |
660 | } | |
661 | ||
662 | #undef DRAM_TYPE_STR | |
663 | ||
54561b23 VS |
664 | static int intel_dimm_num_devices(const struct dram_dimm_info *dimm) |
665 | { | |
666 | return dimm->ranks * 64 / (dimm->width ?: 1); | |
667 | } | |
668 | ||
ea411e6b VS |
669 | /* Returns total GB for the whole DIMM */ |
670 | static int skl_get_dimm_size(u16 val) | |
5771caf8 | 671 | { |
ea411e6b VS |
672 | return val & SKL_DRAM_SIZE_MASK; |
673 | } | |
674 | ||
675 | static int skl_get_dimm_width(u16 val) | |
676 | { | |
677 | if (skl_get_dimm_size(val) == 0) | |
80373fb6 | 678 | return 0; |
5771caf8 | 679 | |
ea411e6b VS |
680 | switch (val & SKL_DRAM_WIDTH_MASK) { |
681 | case SKL_DRAM_WIDTH_X8: | |
682 | case SKL_DRAM_WIDTH_X16: | |
683 | case SKL_DRAM_WIDTH_X32: | |
684 | val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT; | |
685 | return 8 << val; | |
686 | default: | |
687 | MISSING_CASE(val); | |
688 | return 0; | |
689 | } | |
690 | } | |
691 | ||
692 | static int skl_get_dimm_ranks(u16 val) | |
693 | { | |
694 | if (skl_get_dimm_size(val) == 0) | |
695 | return 0; | |
696 | ||
697 | val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT; | |
698 | ||
699 | return val + 1; | |
5771caf8 MK |
700 | } |
701 | ||
6d9c1e92 VS |
702 | /* Returns total GB for the whole DIMM */ |
703 | static int cnl_get_dimm_size(u16 val) | |
704 | { | |
705 | return (val & CNL_DRAM_SIZE_MASK) / 2; | |
706 | } | |
707 | ||
708 | static int cnl_get_dimm_width(u16 val) | |
709 | { | |
710 | if (cnl_get_dimm_size(val) == 0) | |
711 | return 0; | |
712 | ||
713 | switch (val & CNL_DRAM_WIDTH_MASK) { | |
714 | case CNL_DRAM_WIDTH_X8: | |
715 | case CNL_DRAM_WIDTH_X16: | |
716 | case CNL_DRAM_WIDTH_X32: | |
717 | val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT; | |
718 | return 8 << val; | |
719 | default: | |
720 | MISSING_CASE(val); | |
721 | return 0; | |
722 | } | |
723 | } | |
724 | ||
725 | static int cnl_get_dimm_ranks(u16 val) | |
726 | { | |
727 | if (cnl_get_dimm_size(val) == 0) | |
728 | return 0; | |
729 | ||
730 | val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT; | |
731 | ||
732 | return val + 1; | |
733 | } | |
734 | ||
86b59287 | 735 | static bool |
54561b23 | 736 | skl_is_16gb_dimm(const struct dram_dimm_info *dimm) |
86b59287 | 737 | { |
54561b23 VS |
738 | /* Convert total GB to Gb per DRAM device */ |
739 | return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16; | |
86b59287 MK |
740 | } |
741 | ||
198b8dd9 | 742 | static void |
6d9c1e92 VS |
743 | skl_dram_get_dimm_info(struct drm_i915_private *dev_priv, |
744 | struct dram_dimm_info *dimm, | |
198b8dd9 | 745 | int channel, char dimm_name, u16 val) |
5771caf8 | 746 | { |
6d9c1e92 VS |
747 | if (INTEL_GEN(dev_priv) >= 10) { |
748 | dimm->size = cnl_get_dimm_size(val); | |
749 | dimm->width = cnl_get_dimm_width(val); | |
750 | dimm->ranks = cnl_get_dimm_ranks(val); | |
751 | } else { | |
752 | dimm->size = skl_get_dimm_size(val); | |
753 | dimm->width = skl_get_dimm_width(val); | |
754 | dimm->ranks = skl_get_dimm_ranks(val); | |
755 | } | |
5771caf8 | 756 | |
198b8dd9 VS |
757 | DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n", |
758 | channel, dimm_name, dimm->size, dimm->width, dimm->ranks, | |
759 | yesno(skl_is_16gb_dimm(dimm))); | |
760 | } | |
5771caf8 | 761 | |
198b8dd9 | 762 | static int |
6d9c1e92 VS |
763 | skl_dram_get_channel_info(struct drm_i915_private *dev_priv, |
764 | struct dram_channel_info *ch, | |
198b8dd9 VS |
765 | int channel, u32 val) |
766 | { | |
6d9c1e92 VS |
767 | skl_dram_get_dimm_info(dev_priv, &ch->dimm_l, |
768 | channel, 'L', val & 0xffff); | |
769 | skl_dram_get_dimm_info(dev_priv, &ch->dimm_s, | |
770 | channel, 'S', val >> 16); | |
5771caf8 | 771 | |
1d55967d | 772 | if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) { |
198b8dd9 | 773 | DRM_DEBUG_KMS("CH%u not populated\n", channel); |
5771caf8 | 774 | return -EINVAL; |
198b8dd9 | 775 | } |
80373fb6 | 776 | |
1d55967d | 777 | if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2) |
80373fb6 | 778 | ch->ranks = 2; |
1d55967d | 779 | else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1) |
80373fb6 | 780 | ch->ranks = 2; |
5771caf8 | 781 | else |
80373fb6 | 782 | ch->ranks = 1; |
5771caf8 | 783 | |
54561b23 | 784 | ch->is_16gb_dimm = |
1d55967d VS |
785 | skl_is_16gb_dimm(&ch->dimm_l) || |
786 | skl_is_16gb_dimm(&ch->dimm_s); | |
86b59287 | 787 | |
198b8dd9 VS |
788 | DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n", |
789 | channel, ch->ranks, yesno(ch->is_16gb_dimm)); | |
5771caf8 MK |
790 | |
791 | return 0; | |
792 | } | |
793 | ||
8a6c5447 | 794 | static bool |
d75434bc VS |
795 | intel_is_dram_symmetric(const struct dram_channel_info *ch0, |
796 | const struct dram_channel_info *ch1) | |
8a6c5447 | 797 | { |
d75434bc | 798 | return !memcmp(ch0, ch1, sizeof(*ch0)) && |
1d55967d VS |
799 | (ch0->dimm_s.size == 0 || |
800 | !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l))); | |
8a6c5447 MK |
801 | } |
802 | ||
5771caf8 MK |
803 | static int |
804 | skl_dram_get_channels_info(struct drm_i915_private *dev_priv) | |
805 | { | |
806 | struct dram_info *dram_info = &dev_priv->dram_info; | |
198b8dd9 | 807 | struct dram_channel_info ch0 = {}, ch1 = {}; |
d75434bc | 808 | u32 val; |
5771caf8 MK |
809 | int ret; |
810 | ||
d75434bc | 811 | val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); |
6d9c1e92 | 812 | ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val); |
5771caf8 MK |
813 | if (ret == 0) |
814 | dram_info->num_channels++; | |
815 | ||
d75434bc | 816 | val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); |
6d9c1e92 | 817 | ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val); |
5771caf8 MK |
818 | if (ret == 0) |
819 | dram_info->num_channels++; | |
820 | ||
821 | if (dram_info->num_channels == 0) { | |
822 | DRM_INFO("Number of memory channels is zero\n"); | |
823 | return -EINVAL; | |
824 | } | |
825 | ||
826 | /* | |
827 | * If any of the channel is single rank channel, worst case output | |
828 | * will be same as if single rank memory, so consider single rank | |
829 | * memory. | |
830 | */ | |
80373fb6 VS |
831 | if (ch0.ranks == 1 || ch1.ranks == 1) |
832 | dram_info->ranks = 1; | |
5771caf8 | 833 | else |
80373fb6 | 834 | dram_info->ranks = max(ch0.ranks, ch1.ranks); |
5771caf8 | 835 | |
80373fb6 | 836 | if (dram_info->ranks == 0) { |
5771caf8 MK |
837 | DRM_INFO("couldn't get memory rank information\n"); |
838 | return -EINVAL; | |
839 | } | |
86b59287 | 840 | |
5d6f36b2 | 841 | dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm; |
86b59287 | 842 | |
d75434bc | 843 | dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1); |
8a6c5447 | 844 | |
d75434bc VS |
845 | DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n", |
846 | yesno(dram_info->symmetric_memory)); | |
5771caf8 MK |
847 | return 0; |
848 | } | |
849 | ||
b185a352 VS |
850 | static enum intel_dram_type |
851 | skl_get_dram_type(struct drm_i915_private *dev_priv) | |
852 | { | |
853 | u32 val; | |
854 | ||
855 | val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); | |
856 | ||
857 | switch (val & SKL_DRAM_DDR_TYPE_MASK) { | |
858 | case SKL_DRAM_DDR_TYPE_DDR3: | |
859 | return INTEL_DRAM_DDR3; | |
860 | case SKL_DRAM_DDR_TYPE_DDR4: | |
861 | return INTEL_DRAM_DDR4; | |
862 | case SKL_DRAM_DDR_TYPE_LPDDR3: | |
863 | return INTEL_DRAM_LPDDR3; | |
864 | case SKL_DRAM_DDR_TYPE_LPDDR4: | |
865 | return INTEL_DRAM_LPDDR4; | |
866 | default: | |
867 | MISSING_CASE(val); | |
868 | return INTEL_DRAM_UNKNOWN; | |
869 | } | |
870 | } | |
871 | ||
5771caf8 MK |
872 | static int |
873 | skl_get_dram_info(struct drm_i915_private *dev_priv) | |
874 | { | |
875 | struct dram_info *dram_info = &dev_priv->dram_info; | |
876 | u32 mem_freq_khz, val; | |
877 | int ret; | |
878 | ||
b185a352 VS |
879 | dram_info->type = skl_get_dram_type(dev_priv); |
880 | DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type)); | |
881 | ||
5771caf8 MK |
882 | ret = skl_dram_get_channels_info(dev_priv); |
883 | if (ret) | |
884 | return ret; | |
885 | ||
886 | val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); | |
887 | mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) * | |
888 | SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000); | |
889 | ||
890 | dram_info->bandwidth_kbps = dram_info->num_channels * | |
891 | mem_freq_khz * 8; | |
892 | ||
893 | if (dram_info->bandwidth_kbps == 0) { | |
894 | DRM_INFO("Couldn't get system memory bandwidth\n"); | |
895 | return -EINVAL; | |
896 | } | |
897 | ||
898 | dram_info->valid = true; | |
899 | return 0; | |
900 | } | |
901 | ||
a62819a3 VS |
902 | /* Returns Gb per DRAM device */ |
903 | static int bxt_get_dimm_size(u32 val) | |
904 | { | |
905 | switch (val & BXT_DRAM_SIZE_MASK) { | |
8860343c | 906 | case BXT_DRAM_SIZE_4GBIT: |
a62819a3 | 907 | return 4; |
8860343c | 908 | case BXT_DRAM_SIZE_6GBIT: |
a62819a3 | 909 | return 6; |
8860343c | 910 | case BXT_DRAM_SIZE_8GBIT: |
a62819a3 | 911 | return 8; |
8860343c | 912 | case BXT_DRAM_SIZE_12GBIT: |
a62819a3 | 913 | return 12; |
8860343c | 914 | case BXT_DRAM_SIZE_16GBIT: |
a62819a3 VS |
915 | return 16; |
916 | default: | |
917 | MISSING_CASE(val); | |
918 | return 0; | |
919 | } | |
920 | } | |
921 | ||
922 | static int bxt_get_dimm_width(u32 val) | |
923 | { | |
924 | if (!bxt_get_dimm_size(val)) | |
925 | return 0; | |
926 | ||
927 | val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT; | |
928 | ||
929 | return 8 << val; | |
930 | } | |
931 | ||
932 | static int bxt_get_dimm_ranks(u32 val) | |
933 | { | |
934 | if (!bxt_get_dimm_size(val)) | |
935 | return 0; | |
936 | ||
937 | switch (val & BXT_DRAM_RANK_MASK) { | |
938 | case BXT_DRAM_RANK_SINGLE: | |
939 | return 1; | |
940 | case BXT_DRAM_RANK_DUAL: | |
941 | return 2; | |
942 | default: | |
943 | MISSING_CASE(val); | |
944 | return 0; | |
945 | } | |
946 | } | |
947 | ||
b185a352 VS |
948 | static enum intel_dram_type bxt_get_dimm_type(u32 val) |
949 | { | |
950 | if (!bxt_get_dimm_size(val)) | |
951 | return INTEL_DRAM_UNKNOWN; | |
952 | ||
953 | switch (val & BXT_DRAM_TYPE_MASK) { | |
954 | case BXT_DRAM_TYPE_DDR3: | |
955 | return INTEL_DRAM_DDR3; | |
956 | case BXT_DRAM_TYPE_LPDDR3: | |
957 | return INTEL_DRAM_LPDDR3; | |
958 | case BXT_DRAM_TYPE_DDR4: | |
959 | return INTEL_DRAM_DDR4; | |
960 | case BXT_DRAM_TYPE_LPDDR4: | |
961 | return INTEL_DRAM_LPDDR4; | |
962 | default: | |
963 | MISSING_CASE(val); | |
964 | return INTEL_DRAM_UNKNOWN; | |
965 | } | |
966 | } | |
967 | ||
a62819a3 VS |
968 | static void bxt_get_dimm_info(struct dram_dimm_info *dimm, |
969 | u32 val) | |
970 | { | |
a62819a3 VS |
971 | dimm->width = bxt_get_dimm_width(val); |
972 | dimm->ranks = bxt_get_dimm_ranks(val); | |
8860343c VS |
973 | |
974 | /* | |
975 | * Size in register is Gb per DRAM device. Convert to total | |
976 | * GB to match the way we report this for non-LP platforms. | |
977 | */ | |
978 | dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8; | |
a62819a3 VS |
979 | } |
980 | ||
cbfa59d4 MK |
981 | static int |
982 | bxt_get_dram_info(struct drm_i915_private *dev_priv) | |
983 | { | |
984 | struct dram_info *dram_info = &dev_priv->dram_info; | |
985 | u32 dram_channels; | |
986 | u32 mem_freq_khz, val; | |
987 | u8 num_active_channels; | |
988 | int i; | |
989 | ||
990 | val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0); | |
991 | mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) * | |
992 | BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000); | |
993 | ||
994 | dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK; | |
995 | num_active_channels = hweight32(dram_channels); | |
996 | ||
997 | /* Each active bit represents 4-byte channel */ | |
998 | dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4); | |
999 | ||
1000 | if (dram_info->bandwidth_kbps == 0) { | |
1001 | DRM_INFO("Couldn't get system memory bandwidth\n"); | |
1002 | return -EINVAL; | |
1003 | } | |
1004 | ||
1005 | /* | |
1006 | * Now read each DUNIT8/9/10/11 to check the rank of each dimms. | |
1007 | */ | |
1008 | for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) { | |
a62819a3 | 1009 | struct dram_dimm_info dimm; |
b185a352 | 1010 | enum intel_dram_type type; |
cbfa59d4 MK |
1011 | |
1012 | val = I915_READ(BXT_D_CR_DRP0_DUNIT(i)); | |
1013 | if (val == 0xFFFFFFFF) | |
1014 | continue; | |
1015 | ||
1016 | dram_info->num_channels++; | |
a62819a3 VS |
1017 | |
1018 | bxt_get_dimm_info(&dimm, val); | |
b185a352 VS |
1019 | type = bxt_get_dimm_type(val); |
1020 | ||
1021 | WARN_ON(type != INTEL_DRAM_UNKNOWN && | |
1022 | dram_info->type != INTEL_DRAM_UNKNOWN && | |
1023 | dram_info->type != type); | |
a62819a3 | 1024 | |
b185a352 | 1025 | DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n", |
a62819a3 | 1026 | i - BXT_D_CR_DRP0_DUNIT_START, |
b185a352 VS |
1027 | dimm.size, dimm.width, dimm.ranks, |
1028 | intel_dram_type_str(type)); | |
cbfa59d4 MK |
1029 | |
1030 | /* | |
1031 | * If any of the channel is single rank channel, | |
1032 | * worst case output will be same as if single rank | |
1033 | * memory, so consider single rank memory. | |
1034 | */ | |
80373fb6 | 1035 | if (dram_info->ranks == 0) |
a62819a3 VS |
1036 | dram_info->ranks = dimm.ranks; |
1037 | else if (dimm.ranks == 1) | |
80373fb6 | 1038 | dram_info->ranks = 1; |
b185a352 VS |
1039 | |
1040 | if (type != INTEL_DRAM_UNKNOWN) | |
1041 | dram_info->type = type; | |
cbfa59d4 MK |
1042 | } |
1043 | ||
b185a352 VS |
1044 | if (dram_info->type == INTEL_DRAM_UNKNOWN || |
1045 | dram_info->ranks == 0) { | |
1046 | DRM_INFO("couldn't get memory information\n"); | |
cbfa59d4 MK |
1047 | return -EINVAL; |
1048 | } | |
1049 | ||
1050 | dram_info->valid = true; | |
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | static void | |
1055 | intel_get_dram_info(struct drm_i915_private *dev_priv) | |
1056 | { | |
1057 | struct dram_info *dram_info = &dev_priv->dram_info; | |
1058 | int ret; | |
1059 | ||
5d6f36b2 VS |
1060 | /* |
1061 | * Assume 16Gb DIMMs are present until proven otherwise. | |
1062 | * This is only used for the level 0 watermark latency | |
1063 | * w/a which does not apply to bxt/glk. | |
1064 | */ | |
1065 | dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv); | |
1066 | ||
e7862f47 | 1067 | if (INTEL_GEN(dev_priv) < 9 || !HAS_DISPLAY(dev_priv)) |
cbfa59d4 MK |
1068 | return; |
1069 | ||
331ecded | 1070 | if (IS_GEN9_LP(dev_priv)) |
5771caf8 | 1071 | ret = bxt_get_dram_info(dev_priv); |
5771caf8 | 1072 | else |
6d9c1e92 | 1073 | ret = skl_get_dram_info(dev_priv); |
cbfa59d4 MK |
1074 | if (ret) |
1075 | return; | |
1076 | ||
30a533e5 VS |
1077 | DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n", |
1078 | dram_info->bandwidth_kbps, | |
1079 | dram_info->num_channels); | |
1080 | ||
54561b23 | 1081 | DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n", |
80373fb6 | 1082 | dram_info->ranks, yesno(dram_info->is_16gb_dimm)); |
cbfa59d4 MK |
1083 | } |
1084 | ||
f6ac993f DCS |
1085 | static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap) |
1086 | { | |
2edb3de9 VS |
1087 | static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; |
1088 | static const u8 sets[4] = { 1, 1, 2, 2 }; | |
f6ac993f DCS |
1089 | |
1090 | return EDRAM_NUM_BANKS(cap) * | |
1091 | ways[EDRAM_WAYS_IDX(cap)] * | |
1092 | sets[EDRAM_SETS_IDX(cap)]; | |
1093 | } | |
1094 | ||
1095 | static void edram_detect(struct drm_i915_private *dev_priv) | |
1096 | { | |
1097 | u32 edram_cap = 0; | |
1098 | ||
1099 | if (!(IS_HASWELL(dev_priv) || | |
1100 | IS_BROADWELL(dev_priv) || | |
1101 | INTEL_GEN(dev_priv) >= 9)) | |
1102 | return; | |
1103 | ||
1104 | edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP); | |
1105 | ||
1106 | /* NB: We can't write IDICR yet because we don't have gt funcs set up */ | |
1107 | ||
1108 | if (!(edram_cap & EDRAM_ENABLED)) | |
1109 | return; | |
1110 | ||
1111 | /* | |
1112 | * The needed capability bits for size calculation are not there with | |
1113 | * pre gen9 so return 128MB always. | |
1114 | */ | |
1115 | if (INTEL_GEN(dev_priv) < 9) | |
1116 | dev_priv->edram_size_mb = 128; | |
1117 | else | |
1118 | dev_priv->edram_size_mb = | |
1119 | gen9_edram_size_mb(dev_priv, edram_cap); | |
1120 | ||
88f8065c CW |
1121 | dev_info(dev_priv->drm.dev, |
1122 | "Found %uMB of eDRAM\n", dev_priv->edram_size_mb); | |
f6ac993f DCS |
1123 | } |
1124 | ||
0673ad47 | 1125 | /** |
0b61b8b0 | 1126 | * i915_driver_hw_probe - setup state requiring device access |
0673ad47 CW |
1127 | * @dev_priv: device private |
1128 | * | |
1129 | * Setup state that requires accessing the device, but doesn't require | |
1130 | * exposing the driver via kernel internal or userspace interfaces. | |
1131 | */ | |
0b61b8b0 | 1132 | static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) |
0673ad47 | 1133 | { |
52a05c30 | 1134 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
1135 | int ret; |
1136 | ||
50d84418 | 1137 | if (i915_inject_probe_failure(dev_priv)) |
0673ad47 CW |
1138 | return -ENODEV; |
1139 | ||
1400cc7e | 1140 | intel_device_info_runtime_init(dev_priv); |
94b4f3ba | 1141 | |
4bdafb9d CW |
1142 | if (HAS_PPGTT(dev_priv)) { |
1143 | if (intel_vgpu_active(dev_priv) && | |
ca6ac684 | 1144 | !intel_vgpu_has_full_ppgtt(dev_priv)) { |
4bdafb9d CW |
1145 | i915_report_error(dev_priv, |
1146 | "incompatible vGPU found, support for isolated ppGTT required\n"); | |
1147 | return -ENXIO; | |
1148 | } | |
1149 | } | |
1150 | ||
46592892 CW |
1151 | if (HAS_EXECLISTS(dev_priv)) { |
1152 | /* | |
1153 | * Older GVT emulation depends upon intercepting CSB mmio, | |
1154 | * which we no longer use, preferring to use the HWSP cache | |
1155 | * instead. | |
1156 | */ | |
1157 | if (intel_vgpu_active(dev_priv) && | |
1158 | !intel_vgpu_has_hwsp_emulation(dev_priv)) { | |
1159 | i915_report_error(dev_priv, | |
1160 | "old vGPU host found, support for HWSP emulation required\n"); | |
1161 | return -ENXIO; | |
1162 | } | |
1163 | } | |
1164 | ||
94b4f3ba | 1165 | intel_sanitize_options(dev_priv); |
0673ad47 | 1166 | |
f6ac993f DCS |
1167 | /* needs to be done before ggtt probe */ |
1168 | edram_detect(dev_priv); | |
1169 | ||
9f9b2792 LL |
1170 | i915_perf_init(dev_priv); |
1171 | ||
97d6d7ab | 1172 | ret = i915_ggtt_probe_hw(dev_priv); |
0673ad47 | 1173 | if (ret) |
9f172f6f | 1174 | goto err_perf; |
0673ad47 | 1175 | |
f2521f77 GH |
1176 | ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb"); |
1177 | if (ret) | |
9f172f6f | 1178 | goto err_ggtt; |
0673ad47 | 1179 | |
97d6d7ab | 1180 | ret = i915_ggtt_init_hw(dev_priv); |
0088e522 | 1181 | if (ret) |
9f172f6f | 1182 | goto err_ggtt; |
0088e522 | 1183 | |
3fc794f2 CW |
1184 | ret = intel_memory_regions_hw_probe(dev_priv); |
1185 | if (ret) | |
1186 | goto err_ggtt; | |
1187 | ||
797a6153 | 1188 | intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt); |
d8a44248 | 1189 | |
97d6d7ab | 1190 | ret = i915_ggtt_enable_hw(dev_priv); |
0088e522 CW |
1191 | if (ret) { |
1192 | DRM_ERROR("failed to enable GGTT\n"); | |
3fc794f2 | 1193 | goto err_mem_regions; |
0088e522 CW |
1194 | } |
1195 | ||
52a05c30 | 1196 | pci_set_master(pdev); |
0673ad47 | 1197 | |
acd674af LP |
1198 | /* |
1199 | * We don't have a max segment size, so set it to the max so sg's | |
1200 | * debugging layer doesn't complain | |
1201 | */ | |
1202 | dma_set_max_seg_size(&pdev->dev, UINT_MAX); | |
1203 | ||
0673ad47 | 1204 | /* overlay on gen2 is broken and can't address above 1G */ |
cf819eff | 1205 | if (IS_GEN(dev_priv, 2)) { |
52a05c30 | 1206 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); |
0673ad47 CW |
1207 | if (ret) { |
1208 | DRM_ERROR("failed to set DMA mask\n"); | |
1209 | ||
3fc794f2 | 1210 | goto err_mem_regions; |
0673ad47 CW |
1211 | } |
1212 | } | |
1213 | ||
0673ad47 CW |
1214 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1215 | * using 32bit addressing, overwriting memory if HWS is located | |
1216 | * above 4GB. | |
1217 | * | |
1218 | * The documentation also mentions an issue with undefined | |
1219 | * behaviour if any general state is accessed within a page above 4GB, | |
1220 | * which also needs to be handled carefully. | |
1221 | */ | |
c0f86832 | 1222 | if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) { |
52a05c30 | 1223 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
0673ad47 CW |
1224 | |
1225 | if (ret) { | |
1226 | DRM_ERROR("failed to set DMA mask\n"); | |
1227 | ||
3fc794f2 | 1228 | goto err_mem_regions; |
0673ad47 CW |
1229 | } |
1230 | } | |
1231 | ||
0673ad47 CW |
1232 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, |
1233 | PM_QOS_DEFAULT_VALUE); | |
1234 | ||
25d140fa | 1235 | intel_gt_init_workarounds(dev_priv); |
0673ad47 CW |
1236 | |
1237 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
1238 | * integrated graphics even though the support isn't actually there | |
1239 | * according to the published specs. It doesn't appear to function | |
1240 | * correctly in testing on 945G. | |
1241 | * This may be a side effect of MSI having been made available for PEG | |
1242 | * and the registers being closely associated. | |
1243 | * | |
1244 | * According to chipset errata, on the 965GM, MSI interrupts may | |
e38c2da0 VS |
1245 | * be lost or delayed, and was defeatured. MSI interrupts seem to |
1246 | * get lost on g4x as well, and interrupt delivery seems to stay | |
1247 | * properly dead afterwards. So we'll just disable them for all | |
1248 | * pre-gen5 chipsets. | |
8a29c778 LDM |
1249 | * |
1250 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy | |
1251 | * interrupts even when in MSI mode. This results in spurious | |
1252 | * interrupt warnings if the legacy irq no. is shared with another | |
1253 | * device. The kernel then disables that interrupt source and so | |
1254 | * prevents the other device from working properly. | |
0673ad47 | 1255 | */ |
e38c2da0 | 1256 | if (INTEL_GEN(dev_priv) >= 5) { |
52a05c30 | 1257 | if (pci_enable_msi(pdev) < 0) |
0673ad47 CW |
1258 | DRM_DEBUG_DRIVER("can't enable MSI"); |
1259 | } | |
1260 | ||
26f837e8 ZW |
1261 | ret = intel_gvt_init(dev_priv); |
1262 | if (ret) | |
7ab87ede CW |
1263 | goto err_msi; |
1264 | ||
1265 | intel_opregion_setup(dev_priv); | |
cbfa59d4 MK |
1266 | /* |
1267 | * Fill the dram structure to get the system raw bandwidth and | |
1268 | * dram info. This will be used for memory latency calculation. | |
1269 | */ | |
1270 | intel_get_dram_info(dev_priv); | |
1271 | ||
c457d9cf | 1272 | intel_bw_init_hw(dev_priv); |
26f837e8 | 1273 | |
0673ad47 CW |
1274 | return 0; |
1275 | ||
7ab87ede CW |
1276 | err_msi: |
1277 | if (pdev->msi_enabled) | |
1278 | pci_disable_msi(pdev); | |
1279 | pm_qos_remove_request(&dev_priv->pm_qos); | |
3fc794f2 CW |
1280 | err_mem_regions: |
1281 | intel_memory_regions_driver_release(dev_priv); | |
9f172f6f | 1282 | err_ggtt: |
3b58a945 | 1283 | i915_ggtt_driver_release(dev_priv); |
9f172f6f CW |
1284 | err_perf: |
1285 | i915_perf_fini(dev_priv); | |
0673ad47 CW |
1286 | return ret; |
1287 | } | |
1288 | ||
1289 | /** | |
78dae1ac | 1290 | * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() |
0673ad47 CW |
1291 | * @dev_priv: device private |
1292 | */ | |
78dae1ac | 1293 | static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) |
0673ad47 | 1294 | { |
52a05c30 | 1295 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 | 1296 | |
9f9b2792 LL |
1297 | i915_perf_fini(dev_priv); |
1298 | ||
52a05c30 DW |
1299 | if (pdev->msi_enabled) |
1300 | pci_disable_msi(pdev); | |
0673ad47 CW |
1301 | |
1302 | pm_qos_remove_request(&dev_priv->pm_qos); | |
0673ad47 CW |
1303 | } |
1304 | ||
1305 | /** | |
1306 | * i915_driver_register - register the driver with the rest of the system | |
1307 | * @dev_priv: device private | |
1308 | * | |
1309 | * Perform any steps necessary to make the driver available via kernel | |
1310 | * internal or userspace interfaces. | |
1311 | */ | |
1312 | static void i915_driver_register(struct drm_i915_private *dev_priv) | |
1313 | { | |
91c8a326 | 1314 | struct drm_device *dev = &dev_priv->drm; |
0673ad47 | 1315 | |
c29579d2 | 1316 | i915_gem_driver_register(dev_priv); |
b46a33e2 | 1317 | i915_pmu_register(dev_priv); |
0673ad47 CW |
1318 | |
1319 | /* | |
1320 | * Notify a valid surface after modesetting, | |
1321 | * when running inside a VM. | |
1322 | */ | |
1323 | if (intel_vgpu_active(dev_priv)) | |
1324 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); | |
1325 | ||
1326 | /* Reveal our presence to userspace */ | |
1327 | if (drm_dev_register(dev, 0) == 0) { | |
1328 | i915_debugfs_register(dev_priv); | |
694c2828 | 1329 | i915_setup_sysfs(dev_priv); |
442b8c06 RB |
1330 | |
1331 | /* Depends on sysfs having been initialized */ | |
1332 | i915_perf_register(dev_priv); | |
0673ad47 CW |
1333 | } else |
1334 | DRM_ERROR("Failed to register driver for userspace access!\n"); | |
1335 | ||
a2b69ea4 | 1336 | if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) { |
0673ad47 CW |
1337 | /* Must be done after probing outputs */ |
1338 | intel_opregion_register(dev_priv); | |
1339 | acpi_video_register(); | |
1340 | } | |
1341 | ||
42014f69 | 1342 | intel_gt_driver_register(&dev_priv->gt); |
0673ad47 | 1343 | |
eef57324 | 1344 | intel_audio_init(dev_priv); |
0673ad47 CW |
1345 | |
1346 | /* | |
1347 | * Some ports require correctly set-up hpd registers for detection to | |
1348 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1349 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1350 | * irqs are fully enabled. We do it last so that the async config | |
1351 | * cannot run before the connectors are registered. | |
1352 | */ | |
1353 | intel_fbdev_initial_config_async(dev); | |
448aa911 CW |
1354 | |
1355 | /* | |
1356 | * We need to coordinate the hotplugs with the asynchronous fbdev | |
1357 | * configuration, for which we use the fbdev->async_cookie. | |
1358 | */ | |
a2b69ea4 | 1359 | if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) |
448aa911 | 1360 | drm_kms_helper_poll_init(dev); |
07d80572 | 1361 | |
2cd9a689 | 1362 | intel_power_domains_enable(dev_priv); |
69c66355 | 1363 | intel_runtime_pm_enable(&dev_priv->runtime_pm); |
0673ad47 CW |
1364 | } |
1365 | ||
1366 | /** | |
1367 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() | |
1368 | * @dev_priv: device private | |
1369 | */ | |
1370 | static void i915_driver_unregister(struct drm_i915_private *dev_priv) | |
1371 | { | |
69c66355 | 1372 | intel_runtime_pm_disable(&dev_priv->runtime_pm); |
2cd9a689 | 1373 | intel_power_domains_disable(dev_priv); |
07d80572 | 1374 | |
4f256d82 | 1375 | intel_fbdev_unregister(dev_priv); |
eef57324 | 1376 | intel_audio_deinit(dev_priv); |
0673ad47 | 1377 | |
448aa911 CW |
1378 | /* |
1379 | * After flushing the fbdev (incl. a late async config which will | |
1380 | * have delayed queuing of a hotplug event), then flush the hotplug | |
1381 | * events. | |
1382 | */ | |
1383 | drm_kms_helper_poll_fini(&dev_priv->drm); | |
1384 | ||
42014f69 | 1385 | intel_gt_driver_unregister(&dev_priv->gt); |
0673ad47 CW |
1386 | acpi_video_unregister(); |
1387 | intel_opregion_unregister(dev_priv); | |
1388 | ||
442b8c06 | 1389 | i915_perf_unregister(dev_priv); |
b46a33e2 | 1390 | i915_pmu_unregister(dev_priv); |
442b8c06 | 1391 | |
694c2828 | 1392 | i915_teardown_sysfs(dev_priv); |
d69990e0 | 1393 | drm_dev_unplug(&dev_priv->drm); |
0673ad47 | 1394 | |
c29579d2 | 1395 | i915_gem_driver_unregister(dev_priv); |
0673ad47 CW |
1396 | } |
1397 | ||
27d558a1 MW |
1398 | static void i915_welcome_messages(struct drm_i915_private *dev_priv) |
1399 | { | |
bdbf43d7 | 1400 | if (drm_debug_enabled(DRM_UT_DRIVER)) { |
27d558a1 MW |
1401 | struct drm_printer p = drm_debug_printer("i915 device info:"); |
1402 | ||
805446c8 | 1403 | drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", |
1787a984 JN |
1404 | INTEL_DEVID(dev_priv), |
1405 | INTEL_REVID(dev_priv), | |
1406 | intel_platform_name(INTEL_INFO(dev_priv)->platform), | |
805446c8 TU |
1407 | intel_subplatform(RUNTIME_INFO(dev_priv), |
1408 | INTEL_INFO(dev_priv)->platform), | |
1787a984 JN |
1409 | INTEL_GEN(dev_priv)); |
1410 | ||
72404978 CW |
1411 | intel_device_info_print_static(INTEL_INFO(dev_priv), &p); |
1412 | intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p); | |
27d558a1 MW |
1413 | } |
1414 | ||
1415 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) | |
1416 | DRM_INFO("DRM_I915_DEBUG enabled\n"); | |
1417 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) | |
1418 | DRM_INFO("DRM_I915_DEBUG_GEM enabled\n"); | |
6dfc4a8f ID |
1419 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) |
1420 | DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n"); | |
27d558a1 MW |
1421 | } |
1422 | ||
55ac5a16 CW |
1423 | static struct drm_i915_private * |
1424 | i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1425 | { | |
1426 | const struct intel_device_info *match_info = | |
1427 | (struct intel_device_info *)ent->driver_data; | |
1428 | struct intel_device_info *device_info; | |
1429 | struct drm_i915_private *i915; | |
2ddcc982 | 1430 | int err; |
55ac5a16 CW |
1431 | |
1432 | i915 = kzalloc(sizeof(*i915), GFP_KERNEL); | |
1433 | if (!i915) | |
2ddcc982 | 1434 | return ERR_PTR(-ENOMEM); |
55ac5a16 | 1435 | |
2ddcc982 AS |
1436 | err = drm_dev_init(&i915->drm, &driver, &pdev->dev); |
1437 | if (err) { | |
55ac5a16 | 1438 | kfree(i915); |
2ddcc982 | 1439 | return ERR_PTR(err); |
55ac5a16 CW |
1440 | } |
1441 | ||
55ac5a16 | 1442 | i915->drm.dev_private = i915; |
361f9dc2 CW |
1443 | |
1444 | i915->drm.pdev = pdev; | |
1445 | pci_set_drvdata(pdev, i915); | |
55ac5a16 CW |
1446 | |
1447 | /* Setup the write-once "constant" device info */ | |
1448 | device_info = mkwrite_device_info(i915); | |
1449 | memcpy(device_info, match_info, sizeof(*device_info)); | |
0258404f | 1450 | RUNTIME_INFO(i915)->device_id = pdev->device; |
55ac5a16 | 1451 | |
74f6e183 | 1452 | BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask)); |
55ac5a16 CW |
1453 | |
1454 | return i915; | |
1455 | } | |
1456 | ||
31962ca6 CW |
1457 | static void i915_driver_destroy(struct drm_i915_private *i915) |
1458 | { | |
1459 | struct pci_dev *pdev = i915->drm.pdev; | |
1460 | ||
1461 | drm_dev_fini(&i915->drm); | |
1462 | kfree(i915); | |
1463 | ||
1464 | /* And make sure we never chase our dangling pointer from pci_dev */ | |
1465 | pci_set_drvdata(pdev, NULL); | |
1466 | } | |
1467 | ||
0673ad47 | 1468 | /** |
b01558e5 | 1469 | * i915_driver_probe - setup chip and create an initial config |
d2ad3ae4 JL |
1470 | * @pdev: PCI device |
1471 | * @ent: matching PCI ID entry | |
0673ad47 | 1472 | * |
b01558e5 | 1473 | * The driver probe routine has to do several things: |
0673ad47 CW |
1474 | * - drive output discovery via intel_modeset_init() |
1475 | * - initialize the memory manager | |
1476 | * - allocate initial config memory | |
1477 | * - setup the DRM framebuffer with the allocated memory | |
1478 | */ | |
b01558e5 | 1479 | int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
0673ad47 | 1480 | { |
8d2b47dd ML |
1481 | const struct intel_device_info *match_info = |
1482 | (struct intel_device_info *)ent->driver_data; | |
0673ad47 CW |
1483 | struct drm_i915_private *dev_priv; |
1484 | int ret; | |
7d87a7f7 | 1485 | |
55ac5a16 | 1486 | dev_priv = i915_driver_create(pdev, ent); |
2ddcc982 AS |
1487 | if (IS_ERR(dev_priv)) |
1488 | return PTR_ERR(dev_priv); | |
719388e1 | 1489 | |
1feb64c4 VS |
1490 | /* Disable nuclear pageflip by default on pre-ILK */ |
1491 | if (!i915_modparams.nuclear_pageflip && match_info->gen < 5) | |
1492 | dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; | |
1493 | ||
16292243 MA |
1494 | /* |
1495 | * Check if we support fake LMEM -- for now we only unleash this for | |
1496 | * the live selftests(test-and-exit). | |
1497 | */ | |
292a27b0 | 1498 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
16292243 MA |
1499 | if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) { |
1500 | if (INTEL_GEN(dev_priv) >= 9 && i915_selftest.live < 0 && | |
1501 | i915_modparams.fake_lmem_start) { | |
1502 | mkwrite_device_info(dev_priv)->memory_regions = | |
1503 | REGION_SMEM | REGION_LMEM | REGION_STOLEN; | |
1504 | mkwrite_device_info(dev_priv)->is_dgfx = true; | |
1505 | GEM_BUG_ON(!HAS_LMEM(dev_priv)); | |
1506 | GEM_BUG_ON(!IS_DGFX(dev_priv)); | |
1507 | } | |
1508 | } | |
292a27b0 | 1509 | #endif |
16292243 | 1510 | |
0673ad47 CW |
1511 | ret = pci_enable_device(pdev); |
1512 | if (ret) | |
cad3688f | 1513 | goto out_fini; |
1347f5b4 | 1514 | |
0b61b8b0 | 1515 | ret = i915_driver_early_probe(dev_priv); |
0673ad47 CW |
1516 | if (ret < 0) |
1517 | goto out_pci_disable; | |
ef11bdb3 | 1518 | |
9102650f | 1519 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1da177e4 | 1520 | |
9e138ea1 DCS |
1521 | i915_detect_vgpu(dev_priv); |
1522 | ||
0b61b8b0 | 1523 | ret = i915_driver_mmio_probe(dev_priv); |
0673ad47 CW |
1524 | if (ret < 0) |
1525 | goto out_runtime_pm_put; | |
79e53945 | 1526 | |
0b61b8b0 | 1527 | ret = i915_driver_hw_probe(dev_priv); |
0673ad47 CW |
1528 | if (ret < 0) |
1529 | goto out_cleanup_mmio; | |
30c964a6 | 1530 | |
5bcd53aa | 1531 | ret = i915_driver_modeset_probe(dev_priv); |
0673ad47 | 1532 | if (ret < 0) |
baf54385 | 1533 | goto out_cleanup_hw; |
0673ad47 CW |
1534 | |
1535 | i915_driver_register(dev_priv); | |
1536 | ||
9102650f | 1537 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
0673ad47 | 1538 | |
27d558a1 MW |
1539 | i915_welcome_messages(dev_priv); |
1540 | ||
0673ad47 CW |
1541 | return 0; |
1542 | ||
0673ad47 | 1543 | out_cleanup_hw: |
78dae1ac | 1544 | i915_driver_hw_remove(dev_priv); |
3fc794f2 | 1545 | intel_memory_regions_driver_release(dev_priv); |
3b58a945 | 1546 | i915_ggtt_driver_release(dev_priv); |
0673ad47 | 1547 | out_cleanup_mmio: |
3b58a945 | 1548 | i915_driver_mmio_release(dev_priv); |
0673ad47 | 1549 | out_runtime_pm_put: |
9102650f | 1550 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
3b58a945 | 1551 | i915_driver_late_release(dev_priv); |
0673ad47 CW |
1552 | out_pci_disable: |
1553 | pci_disable_device(pdev); | |
cad3688f | 1554 | out_fini: |
f2db53f1 | 1555 | i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret); |
31962ca6 | 1556 | i915_driver_destroy(dev_priv); |
30c964a6 RB |
1557 | return ret; |
1558 | } | |
1559 | ||
361f9dc2 | 1560 | void i915_driver_remove(struct drm_i915_private *i915) |
3bad0781 | 1561 | { |
361f9dc2 | 1562 | disable_rpm_wakeref_asserts(&i915->runtime_pm); |
07d80572 | 1563 | |
361f9dc2 | 1564 | i915_driver_unregister(i915); |
99c539be | 1565 | |
141f3767 JK |
1566 | /* |
1567 | * After unregistering the device to prevent any new users, cancel | |
1568 | * all in-flight requests so that we can quickly unbind the active | |
1569 | * resources. | |
1570 | */ | |
361f9dc2 | 1571 | intel_gt_set_wedged(&i915->gt); |
141f3767 | 1572 | |
4a8ab5ea CW |
1573 | /* Flush any external code that still may be under the RCU lock */ |
1574 | synchronize_rcu(); | |
1575 | ||
361f9dc2 | 1576 | i915_gem_suspend(i915); |
ce1bb329 | 1577 | |
361f9dc2 | 1578 | drm_atomic_helper_shutdown(&i915->drm); |
a667fb40 | 1579 | |
361f9dc2 | 1580 | intel_gvt_driver_remove(i915); |
26f837e8 | 1581 | |
2d6f6f35 | 1582 | i915_driver_modeset_remove(i915); |
bcdb72ac | 1583 | |
361f9dc2 | 1584 | i915_reset_error_state(i915); |
361f9dc2 | 1585 | i915_gem_driver_remove(i915); |
0673ad47 | 1586 | |
361f9dc2 | 1587 | intel_power_domains_driver_remove(i915); |
0673ad47 | 1588 | |
361f9dc2 | 1589 | i915_driver_hw_remove(i915); |
0673ad47 | 1590 | |
361f9dc2 | 1591 | enable_rpm_wakeref_asserts(&i915->runtime_pm); |
cad3688f CW |
1592 | } |
1593 | ||
1594 | static void i915_driver_release(struct drm_device *dev) | |
1595 | { | |
1596 | struct drm_i915_private *dev_priv = to_i915(dev); | |
69c66355 | 1597 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
0673ad47 | 1598 | |
69c66355 | 1599 | disable_rpm_wakeref_asserts(rpm); |
47bc28d7 | 1600 | |
3b58a945 | 1601 | i915_gem_driver_release(dev_priv); |
47bc28d7 | 1602 | |
3fc794f2 | 1603 | intel_memory_regions_driver_release(dev_priv); |
3b58a945 | 1604 | i915_ggtt_driver_release(dev_priv); |
19e0a8d4 | 1605 | |
3b58a945 | 1606 | i915_driver_mmio_release(dev_priv); |
47bc28d7 | 1607 | |
69c66355 | 1608 | enable_rpm_wakeref_asserts(rpm); |
3b58a945 | 1609 | intel_runtime_pm_driver_release(rpm); |
47bc28d7 | 1610 | |
3b58a945 | 1611 | i915_driver_late_release(dev_priv); |
31962ca6 | 1612 | i915_driver_destroy(dev_priv); |
3bad0781 ZW |
1613 | } |
1614 | ||
0673ad47 | 1615 | static int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
2911a35b | 1616 | { |
829a0af2 | 1617 | struct drm_i915_private *i915 = to_i915(dev); |
0673ad47 | 1618 | int ret; |
2911a35b | 1619 | |
829a0af2 | 1620 | ret = i915_gem_open(i915, file); |
0673ad47 CW |
1621 | if (ret) |
1622 | return ret; | |
2911a35b | 1623 | |
0673ad47 CW |
1624 | return 0; |
1625 | } | |
71386ef9 | 1626 | |
0673ad47 CW |
1627 | /** |
1628 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1629 | * @dev: DRM device | |
1630 | * | |
1631 | * Take care of cleaning up after all DRM clients have exited. In the | |
1632 | * mode setting case, we want to restore the kernel's initial mode (just | |
1633 | * in case the last client left us in a bad state). | |
1634 | * | |
1635 | * Additionally, in the non-mode setting case, we'll tear down the GTT | |
1636 | * and DMA structures, since the kernel won't be using them, and clea | |
1637 | * up any GEM state. | |
1638 | */ | |
1639 | static void i915_driver_lastclose(struct drm_device *dev) | |
1640 | { | |
1641 | intel_fbdev_restore_mode(dev); | |
1642 | vga_switcheroo_process_delayed_switch(); | |
1643 | } | |
2911a35b | 1644 | |
7d2ec881 | 1645 | static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
0673ad47 | 1646 | { |
7d2ec881 DV |
1647 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1648 | ||
829a0af2 | 1649 | i915_gem_context_close(file); |
0673ad47 | 1650 | i915_gem_release(dev, file); |
0673ad47 | 1651 | |
77715906 | 1652 | kfree_rcu(file_priv, rcu); |
515b8b7e CW |
1653 | |
1654 | /* Catch up with all the deferred frees from "this" client */ | |
1655 | i915_gem_flush_free_objects(to_i915(dev)); | |
2911a35b BW |
1656 | } |
1657 | ||
07f9cd0b ID |
1658 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
1659 | { | |
91c8a326 | 1660 | struct drm_device *dev = &dev_priv->drm; |
19c8054c | 1661 | struct intel_encoder *encoder; |
07f9cd0b ID |
1662 | |
1663 | drm_modeset_lock_all(dev); | |
19c8054c JN |
1664 | for_each_intel_encoder(dev, encoder) |
1665 | if (encoder->suspend) | |
1666 | encoder->suspend(encoder); | |
07f9cd0b ID |
1667 | drm_modeset_unlock_all(dev); |
1668 | } | |
1669 | ||
1a5df187 PZ |
1670 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1671 | bool rpm_resume); | |
507e126e | 1672 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv); |
f75a1985 | 1673 | |
bc87229f ID |
1674 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
1675 | { | |
1676 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
1677 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
1678 | return true; | |
1679 | #endif | |
1680 | return false; | |
1681 | } | |
ebc32824 | 1682 | |
73b66f87 CW |
1683 | static int i915_drm_prepare(struct drm_device *dev) |
1684 | { | |
1685 | struct drm_i915_private *i915 = to_i915(dev); | |
73b66f87 CW |
1686 | |
1687 | /* | |
1688 | * NB intel_display_suspend() may issue new requests after we've | |
1689 | * ostensibly marked the GPU as ready-to-sleep here. We need to | |
1690 | * split out that work and pull it forward so that after point, | |
1691 | * the GPU is not woken again. | |
1692 | */ | |
5861b013 | 1693 | i915_gem_suspend(i915); |
73b66f87 | 1694 | |
5861b013 | 1695 | return 0; |
73b66f87 CW |
1696 | } |
1697 | ||
5e365c39 | 1698 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 1699 | { |
fac5e23e | 1700 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1701 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e5747e3a | 1702 | pci_power_t opregion_target_state; |
61caf87c | 1703 | |
9102650f | 1704 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1f814dac | 1705 | |
c67a470b PZ |
1706 | /* We do a lot of poking in a lot of registers, make sure they work |
1707 | * properly. */ | |
2cd9a689 | 1708 | intel_power_domains_disable(dev_priv); |
cb10799c | 1709 | |
5bcf719b DA |
1710 | drm_kms_helper_poll_disable(dev); |
1711 | ||
52a05c30 | 1712 | pci_save_state(pdev); |
ba8bbcf6 | 1713 | |
6b72d486 | 1714 | intel_display_suspend(dev); |
2eb5252e | 1715 | |
1a4313d1 | 1716 | intel_dp_mst_suspend(dev_priv); |
7d708ee4 | 1717 | |
d5818938 DV |
1718 | intel_runtime_pm_disable_interrupts(dev_priv); |
1719 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 1720 | |
d5818938 | 1721 | intel_suspend_encoders(dev_priv); |
0e32b39c | 1722 | |
712bf364 | 1723 | intel_suspend_hw(dev_priv); |
5669fcac | 1724 | |
275a991c | 1725 | i915_gem_suspend_gtt_mappings(dev_priv); |
828c7908 | 1726 | |
af6dc742 | 1727 | i915_save_state(dev_priv); |
9e06dd39 | 1728 | |
bc87229f | 1729 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
a950adc6 | 1730 | intel_opregion_suspend(dev_priv, opregion_target_state); |
8ee1c3db | 1731 | |
82e3b8c1 | 1732 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 1733 | |
62d5d69b MK |
1734 | dev_priv->suspend_count++; |
1735 | ||
f74ed08d | 1736 | intel_csr_ucode_suspend(dev_priv); |
f514c2d8 | 1737 | |
9102650f | 1738 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1f814dac | 1739 | |
73b66f87 | 1740 | return 0; |
84b79f8d RW |
1741 | } |
1742 | ||
2cd9a689 ID |
1743 | static enum i915_drm_suspend_mode |
1744 | get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) | |
1745 | { | |
1746 | if (hibernate) | |
1747 | return I915_DRM_SUSPEND_HIBERNATE; | |
1748 | ||
1749 | if (suspend_to_idle(dev_priv)) | |
1750 | return I915_DRM_SUSPEND_IDLE; | |
1751 | ||
1752 | return I915_DRM_SUSPEND_MEM; | |
1753 | } | |
1754 | ||
c49d13ee | 1755 | static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) |
c3c09c95 | 1756 | { |
c49d13ee | 1757 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1758 | struct pci_dev *pdev = dev_priv->drm.pdev; |
69c66355 | 1759 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
071b68cc | 1760 | int ret = 0; |
c3c09c95 | 1761 | |
69c66355 | 1762 | disable_rpm_wakeref_asserts(rpm); |
1f814dac | 1763 | |
ec92ad00 CW |
1764 | i915_gem_suspend_late(dev_priv); |
1765 | ||
f7de5027 | 1766 | intel_uncore_suspend(&dev_priv->uncore); |
4c494a57 | 1767 | |
2cd9a689 ID |
1768 | intel_power_domains_suspend(dev_priv, |
1769 | get_suspend_mode(dev_priv, hibernation)); | |
73dfc227 | 1770 | |
071b68cc RV |
1771 | intel_display_power_suspend_late(dev_priv); |
1772 | ||
1773 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
507e126e | 1774 | ret = vlv_suspend_complete(dev_priv); |
c3c09c95 ID |
1775 | |
1776 | if (ret) { | |
1777 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
2cd9a689 | 1778 | intel_power_domains_resume(dev_priv); |
c3c09c95 | 1779 | |
1f814dac | 1780 | goto out; |
c3c09c95 ID |
1781 | } |
1782 | ||
52a05c30 | 1783 | pci_disable_device(pdev); |
ab3be73f | 1784 | /* |
54875571 | 1785 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
1786 | * the device even though it's already in D3 and hang the machine. So |
1787 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
1788 | * power down the device properly. The issue was seen on multiple old |
1789 | * GENs with different BIOS vendors, so having an explicit blacklist | |
1790 | * is inpractical; apply the workaround on everything pre GEN6. The | |
1791 | * platforms where the issue was seen: | |
1792 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
1793 | * Fujitsu FSC S7110 | |
1794 | * Acer Aspire 1830T | |
ab3be73f | 1795 | */ |
514e1d64 | 1796 | if (!(hibernation && INTEL_GEN(dev_priv) < 6)) |
52a05c30 | 1797 | pci_set_power_state(pdev, PCI_D3hot); |
c3c09c95 | 1798 | |
1f814dac | 1799 | out: |
69c66355 | 1800 | enable_rpm_wakeref_asserts(rpm); |
0a9b2630 | 1801 | if (!dev_priv->uncore.user_forcewake_count) |
3b58a945 | 1802 | intel_runtime_pm_driver_release(rpm); |
1f814dac ID |
1803 | |
1804 | return ret; | |
c3c09c95 ID |
1805 | } |
1806 | ||
63bf8301 | 1807 | int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state) |
84b79f8d RW |
1808 | { |
1809 | int error; | |
1810 | ||
0b14cbd2 ID |
1811 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
1812 | state.event != PM_EVENT_FREEZE)) | |
1813 | return -EINVAL; | |
5bcf719b | 1814 | |
361f9dc2 | 1815 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
5bcf719b | 1816 | return 0; |
6eecba33 | 1817 | |
361f9dc2 | 1818 | error = i915_drm_suspend(&i915->drm); |
84b79f8d RW |
1819 | if (error) |
1820 | return error; | |
1821 | ||
361f9dc2 | 1822 | return i915_drm_suspend_late(&i915->drm, false); |
ba8bbcf6 JB |
1823 | } |
1824 | ||
5e365c39 | 1825 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 | 1826 | { |
fac5e23e | 1827 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac840ae5 | 1828 | int ret; |
9d49c0ef | 1829 | |
9102650f | 1830 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1f814dac | 1831 | |
640b50fa CW |
1832 | sanitize_gpu(dev_priv); |
1833 | ||
97d6d7ab | 1834 | ret = i915_ggtt_enable_hw(dev_priv); |
ac840ae5 VS |
1835 | if (ret) |
1836 | DRM_ERROR("failed to re-enable GGTT\n"); | |
1837 | ||
cec5ca08 | 1838 | i915_gem_restore_gtt_mappings(dev_priv); |
e9d4c924 | 1839 | i915_gem_restore_fences(&dev_priv->ggtt); |
cec5ca08 | 1840 | |
f74ed08d ID |
1841 | intel_csr_ucode_resume(dev_priv); |
1842 | ||
af6dc742 | 1843 | i915_restore_state(dev_priv); |
8090ba8c | 1844 | intel_pps_unlock_regs_wa(dev_priv); |
61caf87c | 1845 | |
c39055b0 | 1846 | intel_init_pch_refclk(dev_priv); |
1833b134 | 1847 | |
364aece0 PA |
1848 | /* |
1849 | * Interrupts have to be enabled before any batches are run. If not the | |
1850 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
1851 | * update/restore the context. | |
1852 | * | |
908764f6 ID |
1853 | * drm_mode_config_reset() needs AUX interrupts. |
1854 | * | |
364aece0 PA |
1855 | * Modeset enabling in intel_modeset_init_hw() also needs working |
1856 | * interrupts. | |
1857 | */ | |
1858 | intel_runtime_pm_enable_interrupts(dev_priv); | |
1859 | ||
908764f6 ID |
1860 | drm_mode_config_reset(dev); |
1861 | ||
37cd3300 | 1862 | i915_gem_resume(dev_priv); |
226485e9 | 1863 | |
6cd02e77 | 1864 | intel_modeset_init_hw(dev_priv); |
675f7ff3 | 1865 | intel_init_clock_gating(dev_priv); |
24576d23 | 1866 | |
d5818938 DV |
1867 | spin_lock_irq(&dev_priv->irq_lock); |
1868 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 1869 | dev_priv->display.hpd_irq_setup(dev_priv); |
d5818938 | 1870 | spin_unlock_irq(&dev_priv->irq_lock); |
0e32b39c | 1871 | |
1a4313d1 | 1872 | intel_dp_mst_resume(dev_priv); |
e7d6f7d7 | 1873 | |
a16b7658 L |
1874 | intel_display_resume(dev); |
1875 | ||
e0b70061 L |
1876 | drm_kms_helper_poll_enable(dev); |
1877 | ||
d5818938 DV |
1878 | /* |
1879 | * ... but also need to make sure that hotplug processing | |
1880 | * doesn't cause havoc. Like in the driver load code we don't | |
c444ad79 | 1881 | * bother with the tiny race here where we might lose hotplug |
d5818938 DV |
1882 | * notifications. |
1883 | * */ | |
1884 | intel_hpd_init(dev_priv); | |
1daed3fb | 1885 | |
a950adc6 | 1886 | intel_opregion_resume(dev_priv); |
44834a67 | 1887 | |
82e3b8c1 | 1888 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 1889 | |
2cd9a689 ID |
1890 | intel_power_domains_enable(dev_priv); |
1891 | ||
9102650f | 1892 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1f814dac | 1893 | |
074c6ada | 1894 | return 0; |
84b79f8d RW |
1895 | } |
1896 | ||
5e365c39 | 1897 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 1898 | { |
fac5e23e | 1899 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1900 | struct pci_dev *pdev = dev_priv->drm.pdev; |
44410cd0 | 1901 | int ret; |
36d61e67 | 1902 | |
76c4b250 ID |
1903 | /* |
1904 | * We have a resume ordering issue with the snd-hda driver also | |
1905 | * requiring our device to be power up. Due to the lack of a | |
1906 | * parent/child relationship we currently solve this with an early | |
1907 | * resume hook. | |
1908 | * | |
1909 | * FIXME: This should be solved with a special hdmi sink device or | |
1910 | * similar so that power domains can be employed. | |
1911 | */ | |
44410cd0 ID |
1912 | |
1913 | /* | |
1914 | * Note that we need to set the power state explicitly, since we | |
1915 | * powered off the device during freeze and the PCI core won't power | |
1916 | * it back up for us during thaw. Powering off the device during | |
1917 | * freeze is not a hard requirement though, and during the | |
1918 | * suspend/resume phases the PCI core makes sure we get here with the | |
1919 | * device powered on. So in case we change our freeze logic and keep | |
1920 | * the device powered we can also remove the following set power state | |
1921 | * call. | |
1922 | */ | |
52a05c30 | 1923 | ret = pci_set_power_state(pdev, PCI_D0); |
44410cd0 ID |
1924 | if (ret) { |
1925 | DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret); | |
2cd9a689 | 1926 | return ret; |
44410cd0 ID |
1927 | } |
1928 | ||
1929 | /* | |
1930 | * Note that pci_enable_device() first enables any parent bridge | |
1931 | * device and only then sets the power state for this device. The | |
1932 | * bridge enabling is a nop though, since bridge devices are resumed | |
1933 | * first. The order of enabling power and enabling the device is | |
1934 | * imposed by the PCI core as described above, so here we preserve the | |
1935 | * same order for the freeze/thaw phases. | |
1936 | * | |
1937 | * TODO: eventually we should remove pci_disable_device() / | |
1938 | * pci_enable_enable_device() from suspend/resume. Due to how they | |
1939 | * depend on the device enable refcount we can't anyway depend on them | |
1940 | * disabling/enabling the device. | |
1941 | */ | |
2cd9a689 ID |
1942 | if (pci_enable_device(pdev)) |
1943 | return -EIO; | |
84b79f8d | 1944 | |
52a05c30 | 1945 | pci_set_master(pdev); |
84b79f8d | 1946 | |
9102650f | 1947 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1f814dac | 1948 | |
666a4537 | 1949 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 | 1950 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 1951 | if (ret) |
ff0b187f DL |
1952 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
1953 | ret); | |
36d61e67 | 1954 | |
f7de5027 DCS |
1955 | intel_uncore_resume_early(&dev_priv->uncore); |
1956 | ||
eaf522f6 | 1957 | intel_gt_check_and_clear_faults(&dev_priv->gt); |
efee833a | 1958 | |
071b68cc | 1959 | intel_display_power_resume_early(dev_priv); |
efee833a | 1960 | |
2cd9a689 | 1961 | intel_power_domains_resume(dev_priv); |
bc87229f | 1962 | |
9102650f | 1963 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
6e35e8ab | 1964 | |
36d61e67 | 1965 | return ret; |
76c4b250 ID |
1966 | } |
1967 | ||
63bf8301 | 1968 | int i915_resume_switcheroo(struct drm_i915_private *i915) |
76c4b250 | 1969 | { |
50a0072f | 1970 | int ret; |
76c4b250 | 1971 | |
361f9dc2 | 1972 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
1973 | return 0; |
1974 | ||
361f9dc2 | 1975 | ret = i915_drm_resume_early(&i915->drm); |
50a0072f ID |
1976 | if (ret) |
1977 | return ret; | |
1978 | ||
361f9dc2 | 1979 | return i915_drm_resume(&i915->drm); |
5a17514e ID |
1980 | } |
1981 | ||
73b66f87 CW |
1982 | static int i915_pm_prepare(struct device *kdev) |
1983 | { | |
361f9dc2 | 1984 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
73b66f87 | 1985 | |
361f9dc2 | 1986 | if (!i915) { |
73b66f87 CW |
1987 | dev_err(kdev, "DRM not initialized, aborting suspend.\n"); |
1988 | return -ENODEV; | |
1989 | } | |
1990 | ||
361f9dc2 | 1991 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
73b66f87 CW |
1992 | return 0; |
1993 | ||
361f9dc2 | 1994 | return i915_drm_prepare(&i915->drm); |
73b66f87 CW |
1995 | } |
1996 | ||
c49d13ee | 1997 | static int i915_pm_suspend(struct device *kdev) |
112b715e | 1998 | { |
361f9dc2 | 1999 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
112b715e | 2000 | |
361f9dc2 | 2001 | if (!i915) { |
c49d13ee | 2002 | dev_err(kdev, "DRM not initialized, aborting suspend.\n"); |
84b79f8d RW |
2003 | return -ENODEV; |
2004 | } | |
112b715e | 2005 | |
361f9dc2 | 2006 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
5bcf719b DA |
2007 | return 0; |
2008 | ||
361f9dc2 | 2009 | return i915_drm_suspend(&i915->drm); |
76c4b250 ID |
2010 | } |
2011 | ||
c49d13ee | 2012 | static int i915_pm_suspend_late(struct device *kdev) |
76c4b250 | 2013 | { |
361f9dc2 | 2014 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
76c4b250 ID |
2015 | |
2016 | /* | |
c965d995 | 2017 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
2018 | * requiring our device to be power up. Due to the lack of a |
2019 | * parent/child relationship we currently solve this with an late | |
2020 | * suspend hook. | |
2021 | * | |
2022 | * FIXME: This should be solved with a special hdmi sink device or | |
2023 | * similar so that power domains can be employed. | |
2024 | */ | |
361f9dc2 | 2025 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
76c4b250 | 2026 | return 0; |
112b715e | 2027 | |
361f9dc2 | 2028 | return i915_drm_suspend_late(&i915->drm, false); |
ab3be73f ID |
2029 | } |
2030 | ||
c49d13ee | 2031 | static int i915_pm_poweroff_late(struct device *kdev) |
ab3be73f | 2032 | { |
361f9dc2 | 2033 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
ab3be73f | 2034 | |
361f9dc2 | 2035 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
ab3be73f ID |
2036 | return 0; |
2037 | ||
361f9dc2 | 2038 | return i915_drm_suspend_late(&i915->drm, true); |
cbda12d7 ZW |
2039 | } |
2040 | ||
c49d13ee | 2041 | static int i915_pm_resume_early(struct device *kdev) |
76c4b250 | 2042 | { |
361f9dc2 | 2043 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
76c4b250 | 2044 | |
361f9dc2 | 2045 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
2046 | return 0; |
2047 | ||
361f9dc2 | 2048 | return i915_drm_resume_early(&i915->drm); |
76c4b250 ID |
2049 | } |
2050 | ||
c49d13ee | 2051 | static int i915_pm_resume(struct device *kdev) |
cbda12d7 | 2052 | { |
361f9dc2 | 2053 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
84b79f8d | 2054 | |
361f9dc2 | 2055 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
2056 | return 0; |
2057 | ||
361f9dc2 | 2058 | return i915_drm_resume(&i915->drm); |
cbda12d7 ZW |
2059 | } |
2060 | ||
1f19ac2a | 2061 | /* freeze: before creating the hibernation_image */ |
c49d13ee | 2062 | static int i915_pm_freeze(struct device *kdev) |
1f19ac2a | 2063 | { |
361f9dc2 | 2064 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
6a800eab CW |
2065 | int ret; |
2066 | ||
361f9dc2 CW |
2067 | if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { |
2068 | ret = i915_drm_suspend(&i915->drm); | |
dd9f31c7 ID |
2069 | if (ret) |
2070 | return ret; | |
2071 | } | |
6a800eab | 2072 | |
361f9dc2 | 2073 | ret = i915_gem_freeze(i915); |
6a800eab CW |
2074 | if (ret) |
2075 | return ret; | |
2076 | ||
2077 | return 0; | |
1f19ac2a CW |
2078 | } |
2079 | ||
c49d13ee | 2080 | static int i915_pm_freeze_late(struct device *kdev) |
1f19ac2a | 2081 | { |
361f9dc2 | 2082 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
461fb99c CW |
2083 | int ret; |
2084 | ||
361f9dc2 CW |
2085 | if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { |
2086 | ret = i915_drm_suspend_late(&i915->drm, true); | |
dd9f31c7 ID |
2087 | if (ret) |
2088 | return ret; | |
2089 | } | |
461fb99c | 2090 | |
361f9dc2 | 2091 | ret = i915_gem_freeze_late(i915); |
461fb99c CW |
2092 | if (ret) |
2093 | return ret; | |
2094 | ||
2095 | return 0; | |
1f19ac2a CW |
2096 | } |
2097 | ||
2098 | /* thaw: called after creating the hibernation image, but before turning off. */ | |
c49d13ee | 2099 | static int i915_pm_thaw_early(struct device *kdev) |
1f19ac2a | 2100 | { |
c49d13ee | 2101 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
2102 | } |
2103 | ||
c49d13ee | 2104 | static int i915_pm_thaw(struct device *kdev) |
1f19ac2a | 2105 | { |
c49d13ee | 2106 | return i915_pm_resume(kdev); |
1f19ac2a CW |
2107 | } |
2108 | ||
2109 | /* restore: called after loading the hibernation image. */ | |
c49d13ee | 2110 | static int i915_pm_restore_early(struct device *kdev) |
1f19ac2a | 2111 | { |
c49d13ee | 2112 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
2113 | } |
2114 | ||
c49d13ee | 2115 | static int i915_pm_restore(struct device *kdev) |
1f19ac2a | 2116 | { |
c49d13ee | 2117 | return i915_pm_resume(kdev); |
1f19ac2a CW |
2118 | } |
2119 | ||
ddeea5b0 ID |
2120 | /* |
2121 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
2122 | * S0i[R123] transition. The list of registers needing a save/restore is | |
2123 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
2124 | * registers in the following way: | |
2125 | * - Driver: saved/restored by the driver | |
2126 | * - Punit : saved/restored by the Punit firmware | |
2127 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
2128 | * used internally by the HW in a way that doesn't depend | |
2129 | * keeping the content across a suspend/resume. | |
2130 | * - Debug : used for debugging | |
2131 | * | |
2132 | * We save/restore all registers marked with 'Driver', with the following | |
2133 | * exceptions: | |
2134 | * - Registers out of use, including also registers marked with 'Debug'. | |
2135 | * These have no effect on the driver's operation, so we don't save/restore | |
2136 | * them to reduce the overhead. | |
2137 | * - Registers that are fully setup by an initialization function called from | |
2138 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
2139 | * - Registers that provide the right functionality with their reset defaults. | |
2140 | * | |
2141 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
2142 | * ignored, we save/restore all others, practically treating the HW context as | |
2143 | * a black-box for the driver. Further investigation is needed to reduce the | |
2144 | * saved/restored registers even further, by following the same 3 criteria. | |
2145 | */ | |
2146 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
2147 | { | |
1bcd8688 | 2148 | struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state; |
ddeea5b0 ID |
2149 | int i; |
2150 | ||
1bcd8688 DCS |
2151 | if (!s) |
2152 | return; | |
2153 | ||
ddeea5b0 ID |
2154 | /* GAM 0x4000-0x4770 */ |
2155 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
2156 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
2157 | s->arb_mode = I915_READ(ARB_MODE); | |
2158 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
2159 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
2160 | ||
2161 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 2162 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
2163 | |
2164 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 2165 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
2166 | |
2167 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
2168 | s->ecochk = I915_READ(GAM_ECOCHK); | |
2169 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
2170 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
2171 | ||
2172 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
2173 | ||
2174 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
2175 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
2176 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
2177 | s->mbctl = I915_READ(GEN6_MBCTL); | |
2178 | ||
2179 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2180 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
2181 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
2182 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
2183 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
2184 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
2185 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
2186 | ||
2187 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2188 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
2189 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
2190 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
2191 | s->ecobus = I915_READ(ECOBUS); | |
2192 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
2193 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
2194 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
2195 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
2196 | s->rcedata = I915_READ(VLV_RCEDATA); | |
2197 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
2198 | ||
2199 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2200 | s->gt_imr = I915_READ(GTIMR); | |
2201 | s->gt_ier = I915_READ(GTIER); | |
2202 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
2203 | s->pm_ier = I915_READ(GEN6_PMIER); | |
2204 | ||
2205 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2206 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
2207 | |
2208 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2209 | s->tilectl = I915_READ(TILECTL); | |
2210 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
2211 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2212 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2213 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
2214 | ||
2215 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2216 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
2217 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 2218 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
2219 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
2220 | ||
2221 | /* | |
2222 | * Not saving any of: | |
2223 | * DFT, 0x9800-0x9EC0 | |
2224 | * SARB, 0xB000-0xB1FC | |
2225 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
2226 | * PCI CFG | |
2227 | */ | |
2228 | } | |
2229 | ||
2230 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
2231 | { | |
1bcd8688 | 2232 | struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state; |
ddeea5b0 ID |
2233 | u32 val; |
2234 | int i; | |
2235 | ||
1bcd8688 DCS |
2236 | if (!s) |
2237 | return; | |
2238 | ||
ddeea5b0 ID |
2239 | /* GAM 0x4000-0x4770 */ |
2240 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
2241 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
2242 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
2243 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
2244 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
2245 | ||
2246 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 2247 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
2248 | |
2249 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 2250 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
2251 | |
2252 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
2253 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
2254 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
2255 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
2256 | ||
2257 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
2258 | ||
2259 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
2260 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
2261 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
2262 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
2263 | ||
2264 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2265 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
2266 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
2267 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
2268 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
2269 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
2270 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
2271 | ||
2272 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2273 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
2274 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
2275 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
2276 | I915_WRITE(ECOBUS, s->ecobus); | |
2277 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
2278 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
2279 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
2280 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
2281 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
2282 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
2283 | ||
2284 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2285 | I915_WRITE(GTIMR, s->gt_imr); | |
2286 | I915_WRITE(GTIER, s->gt_ier); | |
2287 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
2288 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
2289 | ||
2290 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2291 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
2292 | |
2293 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2294 | I915_WRITE(TILECTL, s->tilectl); | |
2295 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
2296 | /* | |
2297 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
2298 | * be restored, as they are used to control the s0ix suspend/resume | |
2299 | * sequence by the caller. | |
2300 | */ | |
2301 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2302 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
2303 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
2304 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2305 | ||
2306 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2307 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
2308 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2309 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2310 | ||
2311 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
2312 | ||
2313 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2314 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
2315 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 2316 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
2317 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
2318 | } | |
2319 | ||
5a31d30b | 2320 | static int vlv_wait_for_pw_status(struct drm_i915_private *i915, |
3dd14c04 CW |
2321 | u32 mask, u32 val) |
2322 | { | |
39806c3f VS |
2323 | i915_reg_t reg = VLV_GTLC_PW_STATUS; |
2324 | u32 reg_value; | |
2325 | int ret; | |
2326 | ||
3dd14c04 CW |
2327 | /* The HW does not like us polling for PW_STATUS frequently, so |
2328 | * use the sleeping loop rather than risk the busy spin within | |
2329 | * intel_wait_for_register(). | |
2330 | * | |
2331 | * Transitioning between RC6 states should be at most 2ms (see | |
2332 | * valleyview_enable_rps) so use a 3ms timeout. | |
2333 | */ | |
5a31d30b TU |
2334 | ret = wait_for(((reg_value = |
2335 | intel_uncore_read_notrace(&i915->uncore, reg)) & mask) | |
2336 | == val, 3); | |
39806c3f VS |
2337 | |
2338 | /* just trace the final value */ | |
2339 | trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); | |
2340 | ||
2341 | return ret; | |
3dd14c04 CW |
2342 | } |
2343 | ||
650ad970 ID |
2344 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
2345 | { | |
2346 | u32 val; | |
2347 | int err; | |
2348 | ||
650ad970 ID |
2349 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
2350 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2351 | if (force_on) | |
2352 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
2353 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2354 | ||
2355 | if (!force_on) | |
2356 | return 0; | |
2357 | ||
97a04e0d | 2358 | err = intel_wait_for_register(&dev_priv->uncore, |
c6ddc5f3 CW |
2359 | VLV_GTLC_SURVIVABILITY_REG, |
2360 | VLV_GFX_CLK_STATUS_BIT, | |
2361 | VLV_GFX_CLK_STATUS_BIT, | |
2362 | 20); | |
650ad970 ID |
2363 | if (err) |
2364 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
2365 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
2366 | ||
2367 | return err; | |
650ad970 ID |
2368 | } |
2369 | ||
ddeea5b0 ID |
2370 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
2371 | { | |
3dd14c04 | 2372 | u32 mask; |
ddeea5b0 | 2373 | u32 val; |
3dd14c04 | 2374 | int err; |
ddeea5b0 ID |
2375 | |
2376 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2377 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
2378 | if (allow) | |
2379 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
2380 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2381 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
2382 | ||
3dd14c04 CW |
2383 | mask = VLV_GTLC_ALLOWWAKEACK; |
2384 | val = allow ? mask : 0; | |
2385 | ||
2386 | err = vlv_wait_for_pw_status(dev_priv, mask, val); | |
ddeea5b0 ID |
2387 | if (err) |
2388 | DRM_ERROR("timeout disabling GT waking\n"); | |
b2736695 | 2389 | |
ddeea5b0 | 2390 | return err; |
ddeea5b0 ID |
2391 | } |
2392 | ||
3dd14c04 CW |
2393 | static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, |
2394 | bool wait_for_on) | |
ddeea5b0 ID |
2395 | { |
2396 | u32 mask; | |
2397 | u32 val; | |
ddeea5b0 ID |
2398 | |
2399 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
2400 | val = wait_for_on ? mask : 0; | |
ddeea5b0 ID |
2401 | |
2402 | /* | |
2403 | * RC6 transitioning can be delayed up to 2 msec (see | |
2404 | * valleyview_enable_rps), use 3 msec for safety. | |
e01569ab CW |
2405 | * |
2406 | * This can fail to turn off the rc6 if the GPU is stuck after a failed | |
2407 | * reset and we are trying to force the machine to sleep. | |
ddeea5b0 | 2408 | */ |
3dd14c04 | 2409 | if (vlv_wait_for_pw_status(dev_priv, mask, val)) |
e01569ab CW |
2410 | DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n", |
2411 | onoff(wait_for_on)); | |
ddeea5b0 ID |
2412 | } |
2413 | ||
2414 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
2415 | { | |
2416 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
2417 | return; | |
2418 | ||
6fa283b0 | 2419 | DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); |
ddeea5b0 ID |
2420 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
2421 | } | |
2422 | ||
ebc32824 | 2423 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
2424 | { |
2425 | u32 mask; | |
2426 | int err; | |
2427 | ||
2428 | /* | |
2429 | * Bspec defines the following GT well on flags as debug only, so | |
2430 | * don't treat them as hard failures. | |
2431 | */ | |
3dd14c04 | 2432 | vlv_wait_for_gt_wells(dev_priv, false); |
ddeea5b0 ID |
2433 | |
2434 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
2435 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
2436 | ||
2437 | vlv_check_no_gt_access(dev_priv); | |
2438 | ||
2439 | err = vlv_force_gfx_clock(dev_priv, true); | |
2440 | if (err) | |
2441 | goto err1; | |
2442 | ||
2443 | err = vlv_allow_gt_wake(dev_priv, false); | |
2444 | if (err) | |
2445 | goto err2; | |
98711167 | 2446 | |
1bcd8688 | 2447 | vlv_save_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2448 | |
2449 | err = vlv_force_gfx_clock(dev_priv, false); | |
2450 | if (err) | |
2451 | goto err2; | |
2452 | ||
2453 | return 0; | |
2454 | ||
2455 | err2: | |
2456 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
2457 | vlv_allow_gt_wake(dev_priv, true); | |
2458 | err1: | |
2459 | vlv_force_gfx_clock(dev_priv, false); | |
2460 | ||
2461 | return err; | |
2462 | } | |
2463 | ||
016970be SK |
2464 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
2465 | bool rpm_resume) | |
ddeea5b0 | 2466 | { |
ddeea5b0 ID |
2467 | int err; |
2468 | int ret; | |
2469 | ||
2470 | /* | |
2471 | * If any of the steps fail just try to continue, that's the best we | |
2472 | * can do at this point. Return the first error code (which will also | |
2473 | * leave RPM permanently disabled). | |
2474 | */ | |
2475 | ret = vlv_force_gfx_clock(dev_priv, true); | |
2476 | ||
1bcd8688 | 2477 | vlv_restore_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2478 | |
2479 | err = vlv_allow_gt_wake(dev_priv, true); | |
2480 | if (!ret) | |
2481 | ret = err; | |
2482 | ||
2483 | err = vlv_force_gfx_clock(dev_priv, false); | |
2484 | if (!ret) | |
2485 | ret = err; | |
2486 | ||
2487 | vlv_check_no_gt_access(dev_priv); | |
2488 | ||
7c108fd8 | 2489 | if (rpm_resume) |
46f16e63 | 2490 | intel_init_clock_gating(dev_priv); |
ddeea5b0 ID |
2491 | |
2492 | return ret; | |
2493 | } | |
2494 | ||
c49d13ee | 2495 | static int intel_runtime_suspend(struct device *kdev) |
8a187455 | 2496 | { |
361f9dc2 | 2497 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
1bf676cc | 2498 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
071b68cc | 2499 | int ret = 0; |
8a187455 | 2500 | |
6772ffe0 | 2501 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 ID |
2502 | return -ENODEV; |
2503 | ||
8a187455 PZ |
2504 | DRM_DEBUG_KMS("Suspending device\n"); |
2505 | ||
9102650f | 2506 | disable_rpm_wakeref_asserts(rpm); |
1f814dac | 2507 | |
d6102977 ID |
2508 | /* |
2509 | * We are safe here against re-faults, since the fault handler takes | |
2510 | * an RPM reference. | |
2511 | */ | |
7c108fd8 | 2512 | i915_gem_runtime_suspend(dev_priv); |
d6102977 | 2513 | |
9dfe3459 | 2514 | intel_gt_runtime_suspend(&dev_priv->gt); |
a1c41994 | 2515 | |
2eb5252e | 2516 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 2517 | |
f7de5027 | 2518 | intel_uncore_suspend(&dev_priv->uncore); |
01c799c9 | 2519 | |
071b68cc RV |
2520 | intel_display_power_suspend(dev_priv); |
2521 | ||
2522 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
507e126e | 2523 | ret = vlv_suspend_complete(dev_priv); |
507e126e | 2524 | |
0ab9cfeb ID |
2525 | if (ret) { |
2526 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
f7de5027 | 2527 | intel_uncore_runtime_resume(&dev_priv->uncore); |
01c799c9 | 2528 | |
b963291c | 2529 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb | 2530 | |
9dfe3459 | 2531 | intel_gt_runtime_resume(&dev_priv->gt); |
1ed21cb4 | 2532 | |
e9d4c924 | 2533 | i915_gem_restore_fences(&dev_priv->ggtt); |
1ed21cb4 | 2534 | |
9102650f | 2535 | enable_rpm_wakeref_asserts(rpm); |
1f814dac | 2536 | |
0ab9cfeb ID |
2537 | return ret; |
2538 | } | |
a8a8bd54 | 2539 | |
9102650f | 2540 | enable_rpm_wakeref_asserts(rpm); |
3b58a945 | 2541 | intel_runtime_pm_driver_release(rpm); |
55ec45c2 | 2542 | |
2cf7bf6f | 2543 | if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) |
55ec45c2 MK |
2544 | DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
2545 | ||
9102650f | 2546 | rpm->suspended = true; |
1fb2362b KCA |
2547 | |
2548 | /* | |
c8a0bd42 PZ |
2549 | * FIXME: We really should find a document that references the arguments |
2550 | * used below! | |
1fb2362b | 2551 | */ |
6f9f4b7a | 2552 | if (IS_BROADWELL(dev_priv)) { |
d37ae19a PZ |
2553 | /* |
2554 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
2555 | * being detected, and the call we do at intel_runtime_resume() | |
2556 | * won't be able to restore them. Since PCI_D3hot matches the | |
2557 | * actual specification and appears to be working, use it. | |
2558 | */ | |
6f9f4b7a | 2559 | intel_opregion_notify_adapter(dev_priv, PCI_D3hot); |
d37ae19a | 2560 | } else { |
c8a0bd42 PZ |
2561 | /* |
2562 | * current versions of firmware which depend on this opregion | |
2563 | * notification have repurposed the D1 definition to mean | |
2564 | * "runtime suspended" vs. what you would normally expect (D3) | |
2565 | * to distinguish it from notifications that might be sent via | |
2566 | * the suspend path. | |
2567 | */ | |
6f9f4b7a | 2568 | intel_opregion_notify_adapter(dev_priv, PCI_D1); |
c8a0bd42 | 2569 | } |
8a187455 | 2570 | |
f568eeee | 2571 | assert_forcewakes_inactive(&dev_priv->uncore); |
dc9fb09c | 2572 | |
21d6e0bd | 2573 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
19625e85 L |
2574 | intel_hpd_poll_init(dev_priv); |
2575 | ||
a8a8bd54 | 2576 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
2577 | return 0; |
2578 | } | |
2579 | ||
c49d13ee | 2580 | static int intel_runtime_resume(struct device *kdev) |
8a187455 | 2581 | { |
361f9dc2 | 2582 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
1bf676cc | 2583 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
1a5df187 | 2584 | int ret = 0; |
8a187455 | 2585 | |
6772ffe0 | 2586 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 | 2587 | return -ENODEV; |
8a187455 PZ |
2588 | |
2589 | DRM_DEBUG_KMS("Resuming device\n"); | |
2590 | ||
9102650f DCS |
2591 | WARN_ON_ONCE(atomic_read(&rpm->wakeref_count)); |
2592 | disable_rpm_wakeref_asserts(rpm); | |
1f814dac | 2593 | |
6f9f4b7a | 2594 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
9102650f | 2595 | rpm->suspended = false; |
2cf7bf6f | 2596 | if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) |
55ec45c2 | 2597 | DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); |
8a187455 | 2598 | |
071b68cc RV |
2599 | intel_display_power_resume(dev_priv); |
2600 | ||
2601 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1a5df187 PZ |
2602 | ret = vlv_resume_prepare(dev_priv, true); |
2603 | ||
f7de5027 | 2604 | intel_uncore_runtime_resume(&dev_priv->uncore); |
bedf4d79 | 2605 | |
1ed21cb4 SAK |
2606 | intel_runtime_pm_enable_interrupts(dev_priv); |
2607 | ||
0ab9cfeb ID |
2608 | /* |
2609 | * No point of rolling back things in case of an error, as the best | |
2610 | * we can do is to hope that things will still work (and disable RPM). | |
2611 | */ | |
9dfe3459 | 2612 | intel_gt_runtime_resume(&dev_priv->gt); |
e9d4c924 | 2613 | i915_gem_restore_fences(&dev_priv->ggtt); |
92b806d3 | 2614 | |
08d8a232 VS |
2615 | /* |
2616 | * On VLV/CHV display interrupts are part of the display | |
2617 | * power well, so hpd is reinitialized from there. For | |
2618 | * everyone else do it here. | |
2619 | */ | |
666a4537 | 2620 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
08d8a232 VS |
2621 | intel_hpd_init(dev_priv); |
2622 | ||
2503a0fe KM |
2623 | intel_enable_ipc(dev_priv); |
2624 | ||
9102650f | 2625 | enable_rpm_wakeref_asserts(rpm); |
1f814dac | 2626 | |
0ab9cfeb ID |
2627 | if (ret) |
2628 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
2629 | else | |
2630 | DRM_DEBUG_KMS("Device resumed\n"); | |
2631 | ||
2632 | return ret; | |
8a187455 PZ |
2633 | } |
2634 | ||
42f5551d | 2635 | const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
2636 | /* |
2637 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
2638 | * PMSG_RESUME] | |
2639 | */ | |
73b66f87 | 2640 | .prepare = i915_pm_prepare, |
0206e353 | 2641 | .suspend = i915_pm_suspend, |
76c4b250 ID |
2642 | .suspend_late = i915_pm_suspend_late, |
2643 | .resume_early = i915_pm_resume_early, | |
0206e353 | 2644 | .resume = i915_pm_resume, |
5545dbbf ID |
2645 | |
2646 | /* | |
2647 | * S4 event handlers | |
2648 | * @freeze, @freeze_late : called (1) before creating the | |
2649 | * hibernation image [PMSG_FREEZE] and | |
2650 | * (2) after rebooting, before restoring | |
2651 | * the image [PMSG_QUIESCE] | |
2652 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
2653 | * image, before writing it [PMSG_THAW] | |
2654 | * and (2) after failing to create or | |
2655 | * restore the image [PMSG_RECOVER] | |
2656 | * @poweroff, @poweroff_late: called after writing the hibernation | |
2657 | * image, before rebooting [PMSG_HIBERNATE] | |
2658 | * @restore, @restore_early : called after rebooting and restoring the | |
2659 | * hibernation image [PMSG_RESTORE] | |
2660 | */ | |
1f19ac2a CW |
2661 | .freeze = i915_pm_freeze, |
2662 | .freeze_late = i915_pm_freeze_late, | |
2663 | .thaw_early = i915_pm_thaw_early, | |
2664 | .thaw = i915_pm_thaw, | |
36d61e67 | 2665 | .poweroff = i915_pm_suspend, |
ab3be73f | 2666 | .poweroff_late = i915_pm_poweroff_late, |
1f19ac2a CW |
2667 | .restore_early = i915_pm_restore_early, |
2668 | .restore = i915_pm_restore, | |
5545dbbf ID |
2669 | |
2670 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
2671 | .runtime_suspend = intel_runtime_suspend, |
2672 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
2673 | }; |
2674 | ||
e08e96de AV |
2675 | static const struct file_operations i915_driver_fops = { |
2676 | .owner = THIS_MODULE, | |
2677 | .open = drm_open, | |
2678 | .release = drm_release, | |
2679 | .unlocked_ioctl = drm_ioctl, | |
cc662126 | 2680 | .mmap = i915_gem_mmap, |
e08e96de | 2681 | .poll = drm_poll, |
e08e96de | 2682 | .read = drm_read, |
e08e96de | 2683 | .compat_ioctl = i915_compat_ioctl, |
e08e96de AV |
2684 | .llseek = noop_llseek, |
2685 | }; | |
2686 | ||
0673ad47 CW |
2687 | static int |
2688 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
2689 | struct drm_file *file) | |
2690 | { | |
2691 | return -ENODEV; | |
2692 | } | |
2693 | ||
2694 | static const struct drm_ioctl_desc i915_ioctls[] = { | |
2695 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2696 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
2697 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
2698 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
2699 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
2700 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
b972fffa | 2701 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
2702 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2703 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), | |
2704 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
2705 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2706 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), | |
2707 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2708 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2709 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), | |
2710 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
2711 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2712 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
6a20fe7b | 2713 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH), |
b972fffa | 2714 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
2715 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), |
2716 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
b972fffa | 2717 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
2718 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), |
2719 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), | |
b972fffa | 2720 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
2721 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2722 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2723 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), | |
2724 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), | |
2725 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), | |
2726 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), | |
cc662126 | 2727 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
2728 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), |
2729 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), | |
111dbcab CW |
2730 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), |
2731 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), | |
0673ad47 | 2732 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), |
6a20fe7b | 2733 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), |
0673ad47 | 2734 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), |
0cd54b03 DV |
2735 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), |
2736 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), | |
2737 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), | |
2738 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), | |
b972fffa | 2739 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), |
b9171541 | 2740 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
2741 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), |
2742 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), | |
2743 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), | |
2744 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), | |
2745 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), | |
2746 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), | |
eec688e1 | 2747 | DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), |
b4023756 EV |
2748 | DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), |
2749 | DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), | |
2750 | DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), | |
7f3f317a CW |
2751 | DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), |
2752 | DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), | |
0673ad47 CW |
2753 | }; |
2754 | ||
1da177e4 | 2755 | static struct drm_driver driver = { |
0c54781b MW |
2756 | /* Don't use MTRRs here; the Xserver or userspace app should |
2757 | * deal with them for Intel hardware. | |
792d2b9a | 2758 | */ |
673a394b | 2759 | .driver_features = |
0424fdaf | 2760 | DRIVER_GEM | |
cf6e7bac | 2761 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ, |
cad3688f | 2762 | .release = i915_driver_release, |
673a394b | 2763 | .open = i915_driver_open, |
22eae947 | 2764 | .lastclose = i915_driver_lastclose, |
673a394b | 2765 | .postclose = i915_driver_postclose, |
d8e29209 | 2766 | |
b1f788c6 | 2767 | .gem_close_object = i915_gem_close_object, |
f0cd5182 | 2768 | .gem_free_object_unlocked = i915_gem_free_object, |
1286ff73 DV |
2769 | |
2770 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
2771 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
2772 | .gem_prime_export = i915_gem_prime_export, | |
2773 | .gem_prime_import = i915_gem_prime_import, | |
2774 | ||
7d23e593 VS |
2775 | .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, |
2776 | .get_scanout_position = i915_get_crtc_scanoutpos, | |
2777 | ||
ff72145b | 2778 | .dumb_create = i915_gem_dumb_create, |
cc662126 AJ |
2779 | .dumb_map_offset = i915_gem_dumb_mmap_offset, |
2780 | ||
1da177e4 | 2781 | .ioctls = i915_ioctls, |
0673ad47 | 2782 | .num_ioctls = ARRAY_SIZE(i915_ioctls), |
e08e96de | 2783 | .fops = &i915_driver_fops, |
22eae947 DA |
2784 | .name = DRIVER_NAME, |
2785 | .desc = DRIVER_DESC, | |
2786 | .date = DRIVER_DATE, | |
2787 | .major = DRIVER_MAJOR, | |
2788 | .minor = DRIVER_MINOR, | |
2789 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 | 2790 | }; |