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drm/i915: Split GEM resetting into 3 phases
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
0673ad47
CW		 46#include <drm/i915_drm.h>
47
48#include "i915_drv.h"
49#include "i915_trace.h"
50#include "i915_vgpu.h"
51#include "intel_drv.h"
5464cd65 52#include "intel_uc.h"
79e53945 53
112b715e
KH		 54static struct drm_driver driver;
55
0673ad47
CW		 56static unsigned int i915_load_fail_count;
57
58bool __i915_inject_load_failure(const char *func, int line)
59{
60 if (i915_load_fail_count >= i915.inject_load_failure)
61 return false;
62
63 if (++i915_load_fail_count == i915.inject_load_failure) {
64 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
65 i915.inject_load_failure, func, line);
66 return true;
67 }
68
69 return false;
70}
71
72#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
73#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
74 "providing the dmesg log by booting with drm.debug=0xf"
75
76void
77__i915_printk(struct drm_i915_private *dev_priv, const char *level,
78 const char *fmt, ...)
79{
80 static bool shown_bug_once;
c49d13ee 81 struct device *kdev = dev_priv->drm.dev;
0673ad47
CW		 82 bool is_error = level[1] <= KERN_ERR[1];
83 bool is_debug = level[1] == KERN_DEBUG[1];
84 struct va_format vaf;
85 va_list args;
86
87 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
88 return;
89
90 va_start(args, fmt);
91
92 vaf.fmt = fmt;
93 vaf.va = &args;
94
c49d13ee 95 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
0673ad47
CW		 96 __builtin_return_address(0), &vaf);
97
98 if (is_error && !shown_bug_once) {
c49d13ee 99 dev_notice(kdev, "%s", FDO_BUG_MSG);
0673ad47
CW		 100 shown_bug_once = true;
101 }
102
103 va_end(args);
104}
105
106static bool i915_error_injected(struct drm_i915_private *dev_priv)
107{
108 return i915.inject_load_failure &&
109 i915_load_fail_count == i915.inject_load_failure;
110}
111
112#define i915_load_error(dev_priv, fmt, ...) \
113 __i915_printk(dev_priv, \
114 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
115 fmt, ##__VA_ARGS__)
116
117
fd6b8f43 118static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
0673ad47
CW		 119{
120 enum intel_pch ret = PCH_NOP;
121
122 /*
123 * In a virtualized passthrough environment we can be in a
124 * setup where the ISA bridge is not able to be passed through.
125 * In this case, a south bridge can be emulated and we have to
126 * make an educated guess as to which PCH is really there.
127 */
128
fd6b8f43 129 if (IS_GEN5(dev_priv)) {
0673ad47
CW		 130 ret = PCH_IBX;
131 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
fd6b8f43 132 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
0673ad47
CW		 133 ret = PCH_CPT;
134 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
fd6b8f43 135 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0673ad47
CW		 136 ret = PCH_LPT;
137 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
fd6b8f43 138 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
0673ad47
CW		 139 ret = PCH_SPT;
140 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
141 }
142
143 return ret;
144}
145
da5f53bf 146static void intel_detect_pch(struct drm_i915_private *dev_priv)
0673ad47 147{
0673ad47
CW		 148 struct pci_dev *pch = NULL;
149
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
152 */
b7f05d4a 153 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
0673ad47
CW		 154 dev_priv->pch_type = PCH_NOP;
155 return;
156 }
157
158 /*
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
163 *
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
168 */
169 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
170 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
171 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
172 dev_priv->pch_id = id;
173
174 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
175 dev_priv->pch_type = PCH_IBX;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
5db94019 177 WARN_ON(!IS_GEN5(dev_priv));
0673ad47
CW		 178 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
179 dev_priv->pch_type = PCH_CPT;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
fd6b8f43
TU		 181 WARN_ON(!(IS_GEN6(dev_priv) ||
182 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 183 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
184 /* PantherPoint is CPT compatible */
185 dev_priv->pch_type = PCH_CPT;
186 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
fd6b8f43
TU		 187 WARN_ON(!(IS_GEN6(dev_priv) ||
188 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 189 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
190 dev_priv->pch_type = PCH_LPT;
191 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
8652744b
TU		 192 WARN_ON(!IS_HASWELL(dev_priv) &&
193 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 194 WARN_ON(IS_HSW_ULT(dev_priv) ||
195 IS_BDW_ULT(dev_priv));
0673ad47
CW		 196 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
197 dev_priv->pch_type = PCH_LPT;
198 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
8652744b
TU		 199 WARN_ON(!IS_HASWELL(dev_priv) &&
200 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 201 WARN_ON(!IS_HSW_ULT(dev_priv) &&
202 !IS_BDW_ULT(dev_priv));
0673ad47
CW		 203 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
204 dev_priv->pch_type = PCH_SPT;
205 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
0853723b
TU		 206 WARN_ON(!IS_SKYLAKE(dev_priv) &&
207 !IS_KABYLAKE(dev_priv));
0673ad47
CW		 208 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
209 dev_priv->pch_type = PCH_SPT;
210 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
0853723b
TU		 211 WARN_ON(!IS_SKYLAKE(dev_priv) &&
212 !IS_KABYLAKE(dev_priv));
22dea0be
RV		 213 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
214 dev_priv->pch_type = PCH_KBP;
215 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
85327748
JN		 216 WARN_ON(!IS_SKYLAKE(dev_priv) &&
217 !IS_KABYLAKE(dev_priv));
0673ad47
CW		 218 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
219 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
220 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
221 pch->subsystem_vendor ==
222 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
223 pch->subsystem_device ==
224 PCI_SUBDEVICE_ID_QEMU)) {
fd6b8f43
TU		 225 dev_priv->pch_type =
226 intel_virt_detect_pch(dev_priv);
0673ad47
CW		 227 } else
228 continue;
229
230 break;
231 }
232 }
233 if (!pch)
234 DRM_DEBUG_KMS("No PCH found.\n");
235
236 pci_dev_put(pch);
237}
238
0673ad47
CW		 239static int i915_getparam(struct drm_device *dev, void *data,
240 struct drm_file *file_priv)
241{
fac5e23e 242 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 243 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 244 drm_i915_getparam_t *param = data;
245 int value;
246
247 switch (param->param) {
248 case I915_PARAM_IRQ_ACTIVE:
249 case I915_PARAM_ALLOW_BATCHBUFFER:
250 case I915_PARAM_LAST_DISPATCH:
251 /* Reject all old ums/dri params. */
252 return -ENODEV;
253 case I915_PARAM_CHIPSET_ID:
52a05c30 254 value = pdev->device;
0673ad47
CW		 255 break;
256 case I915_PARAM_REVISION:
52a05c30 257 value = pdev->revision;
0673ad47 258 break;
0673ad47
CW		 259 case I915_PARAM_NUM_FENCES_AVAIL:
260 value = dev_priv->num_fence_regs;
261 break;
262 case I915_PARAM_HAS_OVERLAY:
263 value = dev_priv->overlay ? 1 : 0;
264 break;
0673ad47 265 case I915_PARAM_HAS_BSD:
3b3f1650 266 value = !!dev_priv->engine[VCS];
0673ad47
CW		 267 break;
268 case I915_PARAM_HAS_BLT:
3b3f1650 269 value = !!dev_priv->engine[BCS];
0673ad47
CW		 270 break;
271 case I915_PARAM_HAS_VEBOX:
3b3f1650 272 value = !!dev_priv->engine[VECS];
0673ad47
CW		 273 break;
274 case I915_PARAM_HAS_BSD2:
3b3f1650 275 value = !!dev_priv->engine[VCS2];
0673ad47 276 break;
0673ad47 277 case I915_PARAM_HAS_EXEC_CONSTANTS:
16162470 278 value = INTEL_GEN(dev_priv) >= 4;
0673ad47
CW		 279 break;
280 case I915_PARAM_HAS_LLC:
16162470 281 value = HAS_LLC(dev_priv);
0673ad47
CW		 282 break;
283 case I915_PARAM_HAS_WT:
16162470 284 value = HAS_WT(dev_priv);
0673ad47
CW		 285 break;
286 case I915_PARAM_HAS_ALIASING_PPGTT:
16162470 287 value = USES_PPGTT(dev_priv);
0673ad47
CW		 288 break;
289 case I915_PARAM_HAS_SEMAPHORES:
39df9190 290 value = i915.semaphores;
0673ad47 291 break;
0673ad47
CW		 292 case I915_PARAM_HAS_SECURE_BATCHES:
293 value = capable(CAP_SYS_ADMIN);
294 break;
0673ad47
CW		 295 case I915_PARAM_CMD_PARSER_VERSION:
296 value = i915_cmd_parser_get_version(dev_priv);
297 break;
0673ad47 298 case I915_PARAM_SUBSLICE_TOTAL:
57ec171e 299 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
0673ad47
CW		 300 if (!value)
301 return -ENODEV;
302 break;
303 case I915_PARAM_EU_TOTAL:
43b67998 304 value = INTEL_INFO(dev_priv)->sseu.eu_total;
0673ad47
CW		 305 if (!value)
306 return -ENODEV;
307 break;
308 case I915_PARAM_HAS_GPU_RESET:
309 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
310 break;
311 case I915_PARAM_HAS_RESOURCE_STREAMER:
16162470 312 value = HAS_RESOURCE_STREAMER(dev_priv);
0673ad47 313 break;
37f501af 314 case I915_PARAM_HAS_POOLED_EU:
16162470 315 value = HAS_POOLED_EU(dev_priv);
37f501af 316 break;
317 case I915_PARAM_MIN_EU_IN_POOL:
43b67998 318 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
37f501af 319 break;
5464cd65
AS		 320 case I915_PARAM_HUC_STATUS:
321 /* The register is already force-woken. We dont need
322 * any rpm here
323 */
324 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
325 break;
4cc69075
CW		 326 case I915_PARAM_MMAP_GTT_VERSION:
327 /* Though we've started our numbering from 1, and so class all
328 * earlier versions as 0, in effect their value is undefined as
329 * the ioctl will report EINVAL for the unknown param!
330 */
331 value = i915_gem_mmap_gtt_version();
332 break;
0de9136d
CW		 333 case I915_PARAM_HAS_SCHEDULER:
334 value = dev_priv->engine[RCS] &&
335 dev_priv->engine[RCS]->schedule;
336 break;
16162470
DW		 337 case I915_PARAM_MMAP_VERSION:
338 /* Remember to bump this if the version changes! */
339 case I915_PARAM_HAS_GEM:
340 case I915_PARAM_HAS_PAGEFLIPPING:
341 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
342 case I915_PARAM_HAS_RELAXED_FENCING:
343 case I915_PARAM_HAS_COHERENT_RINGS:
344 case I915_PARAM_HAS_RELAXED_DELTA:
345 case I915_PARAM_HAS_GEN7_SOL_RESET:
346 case I915_PARAM_HAS_WAIT_TIMEOUT:
347 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
348 case I915_PARAM_HAS_PINNED_BATCHES:
349 case I915_PARAM_HAS_EXEC_NO_RELOC:
350 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
351 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
352 case I915_PARAM_HAS_EXEC_SOFTPIN:
353 /* For the time being all of these are always true;
354 * if some supported hardware does not have one of these
355 * features this value needs to be provided from
356 * INTEL_INFO(), a feature macro, or similar.
357 */
358 value = 1;
359 break;
0673ad47
CW		 360 default:
361 DRM_DEBUG("Unknown parameter %d\n", param->param);
362 return -EINVAL;
363 }
364
dda33009 365 if (put_user(value, param->value))
0673ad47 366 return -EFAULT;
0673ad47
CW		 367
368 return 0;
369}
370
da5f53bf 371static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
0673ad47 372{
0673ad47
CW		 373 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
374 if (!dev_priv->bridge_dev) {
375 DRM_ERROR("bridge device not found\n");
376 return -1;
377 }
378 return 0;
379}
380
381/* Allocate space for the MCH regs if needed, return nonzero on error */
382static int
da5f53bf 383intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
0673ad47 384{
514e1d64 385 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 386 u32 temp_lo, temp_hi = 0;
387 u64 mchbar_addr;
388 int ret;
389
514e1d64 390 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 391 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
392 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
393 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
394
395 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
396#ifdef CONFIG_PNP
397 if (mchbar_addr &&
398 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
399 return 0;
400#endif
401
402 /* Get some space for it */
403 dev_priv->mch_res.name = "i915 MCHBAR";
404 dev_priv->mch_res.flags = IORESOURCE_MEM;
405 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
406 &dev_priv->mch_res,
407 MCHBAR_SIZE, MCHBAR_SIZE,
408 PCIBIOS_MIN_MEM,
409 0, pcibios_align_resource,
410 dev_priv->bridge_dev);
411 if (ret) {
412 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
413 dev_priv->mch_res.start = 0;
414 return ret;
415 }
416
514e1d64 417 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 418 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
419 upper_32_bits(dev_priv->mch_res.start));
420
421 pci_write_config_dword(dev_priv->bridge_dev, reg,
422 lower_32_bits(dev_priv->mch_res.start));
423 return 0;
424}
425
426/* Setup MCHBAR if possible, return true if we should disable it again */
427static void
da5f53bf 428intel_setup_mchbar(struct drm_i915_private *dev_priv)
0673ad47 429{
514e1d64 430 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 431 u32 temp;
432 bool enabled;
433
920a14b2 434 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0673ad47
CW		 435 return;
436
437 dev_priv->mchbar_need_disable = false;
438
50a0bc90 439 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 440 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
441 enabled = !!(temp & DEVEN_MCHBAR_EN);
442 } else {
443 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
444 enabled = temp & 1;
445 }
446
447 /* If it's already enabled, don't have to do anything */
448 if (enabled)
449 return;
450
da5f53bf 451 if (intel_alloc_mchbar_resource(dev_priv))
0673ad47
CW		 452 return;
453
454 dev_priv->mchbar_need_disable = true;
455
456 /* Space is allocated or reserved, so enable it. */
50a0bc90 457 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 458 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
459 temp | DEVEN_MCHBAR_EN);
460 } else {
461 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
462 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
463 }
464}
465
466static void
da5f53bf 467intel_teardown_mchbar(struct drm_i915_private *dev_priv)
0673ad47 468{
514e1d64 469 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 470
471 if (dev_priv->mchbar_need_disable) {
50a0bc90 472 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 473 u32 deven_val;
474
475 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
476 &deven_val);
477 deven_val &= ~DEVEN_MCHBAR_EN;
478 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
479 deven_val);
480 } else {
481 u32 mchbar_val;
482
483 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
484 &mchbar_val);
485 mchbar_val &= ~1;
486 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
487 mchbar_val);
488 }
489 }
490
491 if (dev_priv->mch_res.start)
492 release_resource(&dev_priv->mch_res);
493}
494
495/* true = enable decode, false = disable decoder */
496static unsigned int i915_vga_set_decode(void *cookie, bool state)
497{
da5f53bf 498 struct drm_i915_private *dev_priv = cookie;
0673ad47 499
da5f53bf 500 intel_modeset_vga_set_state(dev_priv, state);
0673ad47
CW		 501 if (state)
502 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
503 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
504 else
505 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
506}
507
7f26cb88
TU		 508static int i915_resume_switcheroo(struct drm_device *dev);
509static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
510
0673ad47
CW		 511static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
512{
513 struct drm_device *dev = pci_get_drvdata(pdev);
514 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
515
516 if (state == VGA_SWITCHEROO_ON) {
517 pr_info("switched on\n");
518 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
519 /* i915 resume handler doesn't set to D0 */
52a05c30 520 pci_set_power_state(pdev, PCI_D0);
0673ad47
CW		 521 i915_resume_switcheroo(dev);
522 dev->switch_power_state = DRM_SWITCH_POWER_ON;
523 } else {
524 pr_info("switched off\n");
525 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
526 i915_suspend_switcheroo(dev, pmm);
527 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
528 }
529}
530
531static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
532{
533 struct drm_device *dev = pci_get_drvdata(pdev);
534
535 /*
536 * FIXME: open_count is protected by drm_global_mutex but that would lead to
537 * locking inversion with the driver load path. And the access here is
538 * completely racy anyway. So don't bother with locking for now.
539 */
540 return dev->open_count == 0;
541}
542
543static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
544 .set_gpu_state = i915_switcheroo_set_state,
545 .reprobe = NULL,
546 .can_switch = i915_switcheroo_can_switch,
547};
548
fbbd37b3 549static void i915_gem_fini(struct drm_i915_private *dev_priv)
0673ad47 550{
fbbd37b3 551 mutex_lock(&dev_priv->drm.struct_mutex);
cb15d9f8
TU		 552 i915_gem_cleanup_engines(dev_priv);
553 i915_gem_context_fini(dev_priv);
fbbd37b3 554 mutex_unlock(&dev_priv->drm.struct_mutex);
0673ad47 555
bdeb9785 556 i915_gem_drain_freed_objects(dev_priv);
fbbd37b3
CW		 557
558 WARN_ON(!list_empty(&dev_priv->context_list));
0673ad47
CW		 559}
560
561static int i915_load_modeset_init(struct drm_device *dev)
562{
fac5e23e 563 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 564 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 565 int ret;
566
567 if (i915_inject_load_failure())
568 return -ENODEV;
569
570 ret = intel_bios_init(dev_priv);
571 if (ret)
572 DRM_INFO("failed to find VBIOS tables\n");
573
574 /* If we have > 1 VGA cards, then we need to arbitrate access
575 * to the common VGA resources.
576 *
577 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
578 * then we do not take part in VGA arbitration and the
579 * vga_client_register() fails with -ENODEV.
580 */
da5f53bf 581 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
0673ad47
CW		 582 if (ret && ret != -ENODEV)
583 goto out;
584
585 intel_register_dsm_handler();
586
52a05c30 587 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
0673ad47
CW		 588 if (ret)
589 goto cleanup_vga_client;
590
591 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
592 intel_update_rawclk(dev_priv);
593
594 intel_power_domains_init_hw(dev_priv, false);
595
596 intel_csr_ucode_init(dev_priv);
597
598 ret = intel_irq_install(dev_priv);
599 if (ret)
600 goto cleanup_csr;
601
40196446 602 intel_setup_gmbus(dev_priv);
0673ad47
CW		 603
604 /* Important: The output setup functions called by modeset_init need
605 * working irqs for e.g. gmbus and dp aux transfers. */
b079bd17
VS		 606 ret = intel_modeset_init(dev);
607 if (ret)
608 goto cleanup_irq;
0673ad47 609
bd132858 610 intel_huc_init(dev_priv);
bf9e8429 611 intel_guc_init(dev_priv);
0673ad47 612
bf9e8429 613 ret = i915_gem_init(dev_priv);
0673ad47
CW		 614 if (ret)
615 goto cleanup_irq;
616
617 intel_modeset_gem_init(dev);
618
b7f05d4a 619 if (INTEL_INFO(dev_priv)->num_pipes == 0)
0673ad47
CW		 620 return 0;
621
622 ret = intel_fbdev_init(dev);
623 if (ret)
624 goto cleanup_gem;
625
626 /* Only enable hotplug handling once the fbdev is fully set up. */
627 intel_hpd_init(dev_priv);
628
629 drm_kms_helper_poll_init(dev);
630
631 return 0;
632
633cleanup_gem:
bf9e8429 634 if (i915_gem_suspend(dev_priv))
1c777c5d 635 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
fbbd37b3 636 i915_gem_fini(dev_priv);
0673ad47 637cleanup_irq:
bf9e8429 638 intel_guc_fini(dev_priv);
bd132858 639 intel_huc_fini(dev_priv);
0673ad47 640 drm_irq_uninstall(dev);
40196446 641 intel_teardown_gmbus(dev_priv);
0673ad47
CW		 642cleanup_csr:
643 intel_csr_ucode_fini(dev_priv);
644 intel_power_domains_fini(dev_priv);
52a05c30 645 vga_switcheroo_unregister_client(pdev);
0673ad47 646cleanup_vga_client:
52a05c30 647 vga_client_register(pdev, NULL, NULL, NULL);
0673ad47
CW		 648out:
649 return ret;
650}
651
0673ad47
CW		 652static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
653{
654 struct apertures_struct *ap;
91c8a326 655 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 656 struct i915_ggtt *ggtt = &dev_priv->ggtt;
657 bool primary;
658 int ret;
659
660 ap = alloc_apertures(1);
661 if (!ap)
662 return -ENOMEM;
663
664 ap->ranges[0].base = ggtt->mappable_base;
665 ap->ranges[0].size = ggtt->mappable_end;
666
667 primary =
668 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
669
44adece5 670 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
0673ad47
CW		 671
672 kfree(ap);
673
674 return ret;
675}
0673ad47
CW		 676
677#if !defined(CONFIG_VGA_CONSOLE)
678static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
679{
680 return 0;
681}
682#elif !defined(CONFIG_DUMMY_CONSOLE)
683static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
684{
685 return -ENODEV;
686}
687#else
688static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
689{
690 int ret = 0;
691
692 DRM_INFO("Replacing VGA console driver\n");
693
694 console_lock();
695 if (con_is_bound(&vga_con))
696 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
697 if (ret == 0) {
698 ret = do_unregister_con_driver(&vga_con);
699
700 /* Ignore "already unregistered". */
701 if (ret == -ENODEV)
702 ret = 0;
703 }
704 console_unlock();
705
706 return ret;
707}
708#endif
709
0673ad47
CW		 710static void intel_init_dpio(struct drm_i915_private *dev_priv)
711{
712 /*
713 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
714 * CHV x1 PHY (DP/HDMI D)
715 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
716 */
717 if (IS_CHERRYVIEW(dev_priv)) {
718 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
719 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
720 } else if (IS_VALLEYVIEW(dev_priv)) {
721 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
722 }
723}
724
725static int i915_workqueues_init(struct drm_i915_private *dev_priv)
726{
727 /*
728 * The i915 workqueue is primarily used for batched retirement of
729 * requests (and thus managing bo) once the task has been completed
730 * by the GPU. i915_gem_retire_requests() is called directly when we
731 * need high-priority retirement, such as waiting for an explicit
732 * bo.
733 *
734 * It is also used for periodic low-priority events, such as
735 * idle-timers and recording error state.
736 *
737 * All tasks on the workqueue are expected to acquire the dev mutex
738 * so there is no point in running more than one instance of the
739 * workqueue at any time. Use an ordered one.
740 */
741 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
742 if (dev_priv->wq == NULL)
743 goto out_err;
744
745 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
746 if (dev_priv->hotplug.dp_wq == NULL)
747 goto out_free_wq;
748
0673ad47
CW		 749 return 0;
750
0673ad47
CW		 751out_free_wq:
752 destroy_workqueue(dev_priv->wq);
753out_err:
754 DRM_ERROR("Failed to allocate workqueues.\n");
755
756 return -ENOMEM;
757}
758
759static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
760{
0673ad47
CW		 761 destroy_workqueue(dev_priv->hotplug.dp_wq);
762 destroy_workqueue(dev_priv->wq);
763}
764
4fc7e845
PZ		 765/*
766 * We don't keep the workarounds for pre-production hardware, so we expect our
767 * driver to fail on these machines in one way or another. A little warning on
768 * dmesg may help both the user and the bug triagers.
769 */
770static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
771{
772 if (IS_HSW_EARLY_SDV(dev_priv) ||
773 IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
774 DRM_ERROR("This is a pre-production stepping. "
775 "It may not be fully functional.\n");
776}
777
0673ad47
CW		 778/**
779 * i915_driver_init_early - setup state not requiring device access
780 * @dev_priv: device private
781 *
782 * Initialize everything that is a "SW-only" state, that is state not
783 * requiring accessing the device or exposing the driver via kernel internal
784 * or userspace interfaces. Example steps belonging here: lock initialization,
785 * system memory allocation, setting up device specific attributes and
786 * function hooks not requiring accessing the device.
787 */
788static int i915_driver_init_early(struct drm_i915_private *dev_priv,
789 const struct pci_device_id *ent)
790{
791 const struct intel_device_info *match_info =
792 (struct intel_device_info *)ent->driver_data;
793 struct intel_device_info *device_info;
794 int ret = 0;
795
796 if (i915_inject_load_failure())
797 return -ENODEV;
798
799 /* Setup the write-once "constant" device info */
94b4f3ba 800 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 801 memcpy(device_info, match_info, sizeof(*device_info));
802 device_info->device_id = dev_priv->drm.pdev->device;
803
804 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
805 device_info->gen_mask = BIT(device_info->gen - 1);
806
807 spin_lock_init(&dev_priv->irq_lock);
808 spin_lock_init(&dev_priv->gpu_error.lock);
809 mutex_init(&dev_priv->backlight_lock);
810 spin_lock_init(&dev_priv->uncore.lock);
811 spin_lock_init(&dev_priv->mm.object_stat_lock);
812 spin_lock_init(&dev_priv->mmio_flip_lock);
467a14d9 813 spin_lock_init(&dev_priv->wm.dsparb_lock);
0673ad47
CW		 814 mutex_init(&dev_priv->sb_lock);
815 mutex_init(&dev_priv->modeset_restore_lock);
816 mutex_init(&dev_priv->av_mutex);
817 mutex_init(&dev_priv->wm.wm_mutex);
818 mutex_init(&dev_priv->pps_mutex);
819
413e8fdb
AH		 820 intel_uc_init_early(dev_priv);
821
0b1de5d5
CW		 822 i915_memcpy_init_early(dev_priv);
823
0673ad47
CW		 824 ret = i915_workqueues_init(dev_priv);
825 if (ret < 0)
826 return ret;
827
0673ad47 828 /* This must be called before any calls to HAS_PCH_* */
da5f53bf 829 intel_detect_pch(dev_priv);
0673ad47 830
192aa181 831 intel_pm_setup(dev_priv);
0673ad47
CW		 832 intel_init_dpio(dev_priv);
833 intel_power_domains_init(dev_priv);
834 intel_irq_init(dev_priv);
3ac168a7 835 intel_hangcheck_init(dev_priv);
0673ad47
CW		 836 intel_init_display_hooks(dev_priv);
837 intel_init_clock_gating_hooks(dev_priv);
838 intel_init_audio_hooks(dev_priv);
cb15d9f8 839 ret = i915_gem_load_init(dev_priv);
73cb9701 840 if (ret < 0)
26f837e8 841 goto err_workqueues;
0673ad47 842
36cdd013 843 intel_display_crc_init(dev_priv);
0673ad47 844
94b4f3ba 845 intel_device_info_dump(dev_priv);
0673ad47 846
4fc7e845 847 intel_detect_preproduction_hw(dev_priv);
0673ad47 848
eec688e1
RB		 849 i915_perf_init(dev_priv);
850
0673ad47
CW		 851 return 0;
852
853err_workqueues:
854 i915_workqueues_cleanup(dev_priv);
855 return ret;
856}
857
858/**
859 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
860 * @dev_priv: device private
861 */
862static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
863{
eec688e1 864 i915_perf_fini(dev_priv);
cb15d9f8 865 i915_gem_load_cleanup(dev_priv);
0673ad47
CW		 866 i915_workqueues_cleanup(dev_priv);
867}
868
da5f53bf 869static int i915_mmio_setup(struct drm_i915_private *dev_priv)
0673ad47 870{
52a05c30 871 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 872 int mmio_bar;
873 int mmio_size;
874
5db94019 875 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
0673ad47
CW		 876 /*
877 * Before gen4, the registers and the GTT are behind different BARs.
878 * However, from gen4 onwards, the registers and the GTT are shared
879 * in the same BAR, so we want to restrict this ioremap from
880 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
881 * the register BAR remains the same size for all the earlier
882 * generations up to Ironlake.
883 */
514e1d64 884 if (INTEL_GEN(dev_priv) < 5)
0673ad47
CW		 885 mmio_size = 512 * 1024;
886 else
887 mmio_size = 2 * 1024 * 1024;
52a05c30 888 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
0673ad47
CW		 889 if (dev_priv->regs == NULL) {
890 DRM_ERROR("failed to map registers\n");
891
892 return -EIO;
893 }
894
895 /* Try to make sure MCHBAR is enabled before poking at it */
da5f53bf 896 intel_setup_mchbar(dev_priv);
0673ad47
CW		 897
898 return 0;
899}
900
da5f53bf 901static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
0673ad47 902{
52a05c30 903 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 904
da5f53bf 905 intel_teardown_mchbar(dev_priv);
52a05c30 906 pci_iounmap(pdev, dev_priv->regs);
0673ad47
CW		 907}
908
909/**
910 * i915_driver_init_mmio - setup device MMIO
911 * @dev_priv: device private
912 *
913 * Setup minimal device state necessary for MMIO accesses later in the
914 * initialization sequence. The setup here should avoid any other device-wide
915 * side effects or exposing the driver via kernel internal or user space
916 * interfaces.
917 */
918static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
919{
0673ad47
CW		 920 int ret;
921
922 if (i915_inject_load_failure())
923 return -ENODEV;
924
da5f53bf 925 if (i915_get_bridge_dev(dev_priv))
0673ad47
CW		 926 return -EIO;
927
da5f53bf 928 ret = i915_mmio_setup(dev_priv);
0673ad47
CW		 929 if (ret < 0)
930 goto put_bridge;
931
932 intel_uncore_init(dev_priv);
933
934 return 0;
935
936put_bridge:
937 pci_dev_put(dev_priv->bridge_dev);
938
939 return ret;
940}
941
942/**
943 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
944 * @dev_priv: device private
945 */
946static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
947{
0673ad47 948 intel_uncore_fini(dev_priv);
da5f53bf 949 i915_mmio_cleanup(dev_priv);
0673ad47
CW		 950 pci_dev_put(dev_priv->bridge_dev);
951}
952
94b4f3ba
CW		 953static void intel_sanitize_options(struct drm_i915_private *dev_priv)
954{
955 i915.enable_execlists =
956 intel_sanitize_enable_execlists(dev_priv,
957 i915.enable_execlists);
958
959 /*
960 * i915.enable_ppgtt is read-only, so do an early pass to validate the
961 * user's requested state against the hardware/driver capabilities. We
962 * do this now so that we can print out any log messages once rather
963 * than every time we check intel_enable_ppgtt().
964 */
965 i915.enable_ppgtt =
966 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
967 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
39df9190
CW		 968
969 i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
970 DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
94b4f3ba
CW		 971}
972
0673ad47
CW		 973/**
974 * i915_driver_init_hw - setup state requiring device access
975 * @dev_priv: device private
976 *
977 * Setup state that requires accessing the device, but doesn't require
978 * exposing the driver via kernel internal or userspace interfaces.
979 */
980static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
981{
52a05c30 982 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 983 int ret;
984
985 if (i915_inject_load_failure())
986 return -ENODEV;
987
94b4f3ba
CW		 988 intel_device_info_runtime_init(dev_priv);
989
990 intel_sanitize_options(dev_priv);
0673ad47 991
97d6d7ab 992 ret = i915_ggtt_probe_hw(dev_priv);
0673ad47
CW		 993 if (ret)
994 return ret;
995
0673ad47
CW		 996 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
997 * otherwise the vga fbdev driver falls over. */
998 ret = i915_kick_out_firmware_fb(dev_priv);
999 if (ret) {
1000 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1001 goto out_ggtt;
1002 }
1003
1004 ret = i915_kick_out_vgacon(dev_priv);
1005 if (ret) {
1006 DRM_ERROR("failed to remove conflicting VGA console\n");
1007 goto out_ggtt;
1008 }
1009
97d6d7ab 1010 ret = i915_ggtt_init_hw(dev_priv);
0088e522
CW		 1011 if (ret)
1012 return ret;
1013
97d6d7ab 1014 ret = i915_ggtt_enable_hw(dev_priv);
0088e522
CW		 1015 if (ret) {
1016 DRM_ERROR("failed to enable GGTT\n");
1017 goto out_ggtt;
1018 }
1019
52a05c30 1020 pci_set_master(pdev);
0673ad47
CW		 1021
1022 /* overlay on gen2 is broken and can't address above 1G */
5db94019 1023 if (IS_GEN2(dev_priv)) {
52a05c30 1024 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
0673ad47
CW		 1025 if (ret) {
1026 DRM_ERROR("failed to set DMA mask\n");
1027
1028 goto out_ggtt;
1029 }
1030 }
1031
0673ad47
CW		 1032 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1033 * using 32bit addressing, overwriting memory if HWS is located
1034 * above 4GB.
1035 *
1036 * The documentation also mentions an issue with undefined
1037 * behaviour if any general state is accessed within a page above 4GB,
1038 * which also needs to be handled carefully.
1039 */
c0f86832 1040 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
52a05c30 1041 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0673ad47
CW		 1042
1043 if (ret) {
1044 DRM_ERROR("failed to set DMA mask\n");
1045
1046 goto out_ggtt;
1047 }
1048 }
1049
0673ad47
CW		 1050 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1051 PM_QOS_DEFAULT_VALUE);
1052
1053 intel_uncore_sanitize(dev_priv);
1054
1055 intel_opregion_setup(dev_priv);
1056
1057 i915_gem_load_init_fences(dev_priv);
1058
1059 /* On the 945G/GM, the chipset reports the MSI capability on the
1060 * integrated graphics even though the support isn't actually there
1061 * according to the published specs. It doesn't appear to function
1062 * correctly in testing on 945G.
1063 * This may be a side effect of MSI having been made available for PEG
1064 * and the registers being closely associated.
1065 *
1066 * According to chipset errata, on the 965GM, MSI interrupts may
1067 * be lost or delayed, but we use them anyways to avoid
1068 * stuck interrupts on some machines.
1069 */
50a0bc90 1070 if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
52a05c30 1071 if (pci_enable_msi(pdev) < 0)
0673ad47
CW		 1072 DRM_DEBUG_DRIVER("can't enable MSI");
1073 }
1074
26f837e8
ZW		 1075 ret = intel_gvt_init(dev_priv);
1076 if (ret)
1077 goto out_ggtt;
1078
0673ad47
CW		 1079 return 0;
1080
1081out_ggtt:
97d6d7ab 1082 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1083
1084 return ret;
1085}
1086
1087/**
1088 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1089 * @dev_priv: device private
1090 */
1091static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1092{
52a05c30 1093 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 1094
52a05c30
DW		 1095 if (pdev->msi_enabled)
1096 pci_disable_msi(pdev);
0673ad47
CW		 1097
1098 pm_qos_remove_request(&dev_priv->pm_qos);
97d6d7ab 1099 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1100}
1101
1102/**
1103 * i915_driver_register - register the driver with the rest of the system
1104 * @dev_priv: device private
1105 *
1106 * Perform any steps necessary to make the driver available via kernel
1107 * internal or userspace interfaces.
1108 */
1109static void i915_driver_register(struct drm_i915_private *dev_priv)
1110{
91c8a326 1111 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1112
1113 i915_gem_shrinker_init(dev_priv);
1114
1115 /*
1116 * Notify a valid surface after modesetting,
1117 * when running inside a VM.
1118 */
1119 if (intel_vgpu_active(dev_priv))
1120 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1121
1122 /* Reveal our presence to userspace */
1123 if (drm_dev_register(dev, 0) == 0) {
1124 i915_debugfs_register(dev_priv);
f9cda048 1125 i915_guc_log_register(dev_priv);
694c2828 1126 i915_setup_sysfs(dev_priv);
442b8c06
RB		 1127
1128 /* Depends on sysfs having been initialized */
1129 i915_perf_register(dev_priv);
0673ad47
CW		 1130 } else
1131 DRM_ERROR("Failed to register driver for userspace access!\n");
1132
1133 if (INTEL_INFO(dev_priv)->num_pipes) {
1134 /* Must be done after probing outputs */
1135 intel_opregion_register(dev_priv);
1136 acpi_video_register();
1137 }
1138
1139 if (IS_GEN5(dev_priv))
1140 intel_gpu_ips_init(dev_priv);
1141
eef57324 1142 intel_audio_init(dev_priv);
0673ad47
CW		 1143
1144 /*
1145 * Some ports require correctly set-up hpd registers for detection to
1146 * work properly (leading to ghost connected connector status), e.g. VGA
1147 * on gm45. Hence we can only set up the initial fbdev config after hpd
1148 * irqs are fully enabled. We do it last so that the async config
1149 * cannot run before the connectors are registered.
1150 */
1151 intel_fbdev_initial_config_async(dev);
1152}
1153
1154/**
1155 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1156 * @dev_priv: device private
1157 */
1158static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1159{
eef57324 1160 intel_audio_deinit(dev_priv);
0673ad47
CW		 1161
1162 intel_gpu_ips_teardown();
1163 acpi_video_unregister();
1164 intel_opregion_unregister(dev_priv);
1165
442b8c06
RB		 1166 i915_perf_unregister(dev_priv);
1167
694c2828 1168 i915_teardown_sysfs(dev_priv);
f9cda048 1169 i915_guc_log_unregister(dev_priv);
0673ad47 1170 i915_debugfs_unregister(dev_priv);
91c8a326 1171 drm_dev_unregister(&dev_priv->drm);
0673ad47
CW		 1172
1173 i915_gem_shrinker_cleanup(dev_priv);
1174}
1175
1176/**
1177 * i915_driver_load - setup chip and create an initial config
d2ad3ae4
JL		 1178 * @pdev: PCI device
1179 * @ent: matching PCI ID entry
0673ad47
CW		 1180 *
1181 * The driver load routine has to do several things:
1182 * - drive output discovery via intel_modeset_init()
1183 * - initialize the memory manager
1184 * - allocate initial config memory
1185 * - setup the DRM framebuffer with the allocated memory
1186 */
42f5551d 1187int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47
CW		 1188{
1189 struct drm_i915_private *dev_priv;
1190 int ret;
7d87a7f7 1191
a09d0ba1
CW		 1192 if (i915.nuclear_pageflip)
1193 driver.driver_features |= DRIVER_ATOMIC;
1194
0673ad47
CW		 1195 ret = -ENOMEM;
1196 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1197 if (dev_priv)
1198 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1199 if (ret) {
87a6752c 1200 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
0673ad47
CW		 1201 kfree(dev_priv);
1202 return ret;
1203 }
72bbf0af 1204
0673ad47
CW		 1205 dev_priv->drm.pdev = pdev;
1206 dev_priv->drm.dev_private = dev_priv;
719388e1 1207
0673ad47
CW		 1208 ret = pci_enable_device(pdev);
1209 if (ret)
1210 goto out_free_priv;
1347f5b4 1211
0673ad47 1212 pci_set_drvdata(pdev, &dev_priv->drm);
ef11bdb3 1213
0673ad47
CW		 1214 ret = i915_driver_init_early(dev_priv, ent);
1215 if (ret < 0)
1216 goto out_pci_disable;
ef11bdb3 1217
0673ad47 1218 intel_runtime_pm_get(dev_priv);
1da177e4 1219
0673ad47
CW		 1220 ret = i915_driver_init_mmio(dev_priv);
1221 if (ret < 0)
1222 goto out_runtime_pm_put;
79e53945 1223
0673ad47
CW		 1224 ret = i915_driver_init_hw(dev_priv);
1225 if (ret < 0)
1226 goto out_cleanup_mmio;
30c964a6
RB		 1227
1228 /*
0673ad47
CW		 1229 * TODO: move the vblank init and parts of modeset init steps into one
1230 * of the i915_driver_init_/i915_driver_register functions according
1231 * to the role/effect of the given init step.
30c964a6 1232 */
0673ad47 1233 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1234 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1235 INTEL_INFO(dev_priv)->num_pipes);
1236 if (ret)
1237 goto out_cleanup_hw;
30c964a6
RB		 1238 }
1239
91c8a326 1240 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47
CW		 1241 if (ret < 0)
1242 goto out_cleanup_vblank;
1243
1244 i915_driver_register(dev_priv);
1245
1246 intel_runtime_pm_enable(dev_priv);
1247
a3a8986c
MK		 1248 dev_priv->ipc_enabled = false;
1249
bc5ca47c
CW		 1250 /* Everything is in place, we can now relax! */
1251 DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1252 driver.name, driver.major, driver.minor, driver.patchlevel,
1253 driver.date, pci_name(pdev), dev_priv->drm.primary->index);
0525a062
CW		 1254 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1255 DRM_INFO("DRM_I915_DEBUG enabled\n");
1256 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1257 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
bc5ca47c 1258
0673ad47
CW		 1259 intel_runtime_pm_put(dev_priv);
1260
1261 return 0;
1262
1263out_cleanup_vblank:
91c8a326 1264 drm_vblank_cleanup(&dev_priv->drm);
0673ad47
CW		 1265out_cleanup_hw:
1266 i915_driver_cleanup_hw(dev_priv);
1267out_cleanup_mmio:
1268 i915_driver_cleanup_mmio(dev_priv);
1269out_runtime_pm_put:
1270 intel_runtime_pm_put(dev_priv);
1271 i915_driver_cleanup_early(dev_priv);
1272out_pci_disable:
1273 pci_disable_device(pdev);
1274out_free_priv:
1275 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1276 drm_dev_unref(&dev_priv->drm);
30c964a6
RB		 1277 return ret;
1278}
1279
42f5551d 1280void i915_driver_unload(struct drm_device *dev)
3bad0781 1281{
fac5e23e 1282 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1283 struct pci_dev *pdev = dev_priv->drm.pdev;
3bad0781 1284
0673ad47
CW		 1285 intel_fbdev_fini(dev);
1286
bf9e8429 1287 if (i915_gem_suspend(dev_priv))
42f5551d 1288 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1289
0673ad47
CW		 1290 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1291
26f837e8
ZW		 1292 intel_gvt_cleanup(dev_priv);
1293
0673ad47
CW		 1294 i915_driver_unregister(dev_priv);
1295
1296 drm_vblank_cleanup(dev);
1297
1298 intel_modeset_cleanup(dev);
1299
3bad0781 1300 /*
0673ad47
CW		 1301 * free the memory space allocated for the child device
1302 * config parsed from VBT
3bad0781 1303 */
0673ad47
CW		 1304 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1305 kfree(dev_priv->vbt.child_dev);
1306 dev_priv->vbt.child_dev = NULL;
1307 dev_priv->vbt.child_dev_num = 0;
1308 }
1309 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1310 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1311 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1312 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1313
52a05c30
DW		 1314 vga_switcheroo_unregister_client(pdev);
1315 vga_client_register(pdev, NULL, NULL, NULL);
bcdb72ac 1316
0673ad47 1317 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1318
0673ad47
CW		 1319 /* Free error state after interrupts are fully disabled. */
1320 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
12ff05e7 1321 i915_destroy_error_state(dev_priv);
0673ad47
CW		 1322
1323 /* Flush any outstanding unpin_work. */
b7137e0c 1324 drain_workqueue(dev_priv->wq);
0673ad47 1325
bf9e8429 1326 intel_guc_fini(dev_priv);
bd132858 1327 intel_huc_fini(dev_priv);
fbbd37b3 1328 i915_gem_fini(dev_priv);
0673ad47
CW		 1329 intel_fbc_cleanup_cfb(dev_priv);
1330
1331 intel_power_domains_fini(dev_priv);
1332
1333 i915_driver_cleanup_hw(dev_priv);
1334 i915_driver_cleanup_mmio(dev_priv);
1335
1336 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1337
1338 i915_driver_cleanup_early(dev_priv);
3bad0781
ZW		 1339}
1340
0673ad47 1341static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1342{
0673ad47 1343 int ret;
2911a35b 1344
0673ad47
CW		 1345 ret = i915_gem_open(dev, file);
1346 if (ret)
1347 return ret;
2911a35b 1348
0673ad47
CW		 1349 return 0;
1350}
71386ef9 1351
0673ad47
CW		 1352/**
1353 * i915_driver_lastclose - clean up after all DRM clients have exited
1354 * @dev: DRM device
1355 *
1356 * Take care of cleaning up after all DRM clients have exited. In the
1357 * mode setting case, we want to restore the kernel's initial mode (just
1358 * in case the last client left us in a bad state).
1359 *
1360 * Additionally, in the non-mode setting case, we'll tear down the GTT
1361 * and DMA structures, since the kernel won't be using them, and clea
1362 * up any GEM state.
1363 */
1364static void i915_driver_lastclose(struct drm_device *dev)
1365{
1366 intel_fbdev_restore_mode(dev);
1367 vga_switcheroo_process_delayed_switch();
1368}
2911a35b 1369
0673ad47
CW		 1370static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1371{
1372 mutex_lock(&dev->struct_mutex);
1373 i915_gem_context_close(dev, file);
1374 i915_gem_release(dev, file);
1375 mutex_unlock(&dev->struct_mutex);
1376}
1377
1378static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1379{
1380 struct drm_i915_file_private *file_priv = file->driver_priv;
1381
1382 kfree(file_priv);
2911a35b
BW		 1383}
1384
07f9cd0b
ID		 1385static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1386{
91c8a326 1387 struct drm_device *dev = &dev_priv->drm;
19c8054c 1388 struct intel_encoder *encoder;
07f9cd0b
ID		 1389
1390 drm_modeset_lock_all(dev);
19c8054c
JN		 1391 for_each_intel_encoder(dev, encoder)
1392 if (encoder->suspend)
1393 encoder->suspend(encoder);
07f9cd0b
ID		 1394 drm_modeset_unlock_all(dev);
1395}
1396
1a5df187
PZ		 1397static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1398 bool rpm_resume);
507e126e 1399static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1400
bc87229f
ID		 1401static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1402{
1403#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1404 if (acpi_target_system_state() < ACPI_STATE_S3)
1405 return true;
1406#endif
1407 return false;
1408}
ebc32824 1409
5e365c39 1410static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1411{
fac5e23e 1412 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1413 struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3a 1414 pci_power_t opregion_target_state;
d5818938 1415 int error;
61caf87c 1416
b8efb17b
ZR		 1417 /* ignore lid events during suspend */
1418 mutex_lock(&dev_priv->modeset_restore_lock);
1419 dev_priv->modeset_restore = MODESET_SUSPENDED;
1420 mutex_unlock(&dev_priv->modeset_restore_lock);
1421
1f814dac
ID		 1422 disable_rpm_wakeref_asserts(dev_priv);
1423
c67a470b
PZ		 1424 /* We do a lot of poking in a lot of registers, make sure they work
1425 * properly. */
da7e29bd 1426 intel_display_set_init_power(dev_priv, true);
cb10799c 1427
5bcf719b
DA		 1428 drm_kms_helper_poll_disable(dev);
1429
52a05c30 1430 pci_save_state(pdev);
ba8bbcf6 1431
bf9e8429 1432 error = i915_gem_suspend(dev_priv);
d5818938 1433 if (error) {
52a05c30 1434 dev_err(&pdev->dev,
d5818938 1435 "GEM idle failed, resume might fail\n");
1f814dac 1436 goto out;
d5818938 1437 }
db1b76ca 1438
bf9e8429 1439 intel_guc_suspend(dev_priv);
a1c41994 1440
6b72d486 1441 intel_display_suspend(dev);
2eb5252e 1442
d5818938 1443 intel_dp_mst_suspend(dev);
7d708ee4 1444
d5818938
DV		 1445 intel_runtime_pm_disable_interrupts(dev_priv);
1446 intel_hpd_cancel_work(dev_priv);
09b64267 1447
d5818938 1448 intel_suspend_encoders(dev_priv);
0e32b39c 1449
712bf364 1450 intel_suspend_hw(dev_priv);
5669fcac 1451
275a991c 1452 i915_gem_suspend_gtt_mappings(dev_priv);
828c7908 1453
af6dc742 1454 i915_save_state(dev_priv);
9e06dd39 1455
bc87229f 1456 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1457 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1458
dc97997a 1459 intel_uncore_forcewake_reset(dev_priv, false);
03d92e47 1460 intel_opregion_unregister(dev_priv);
8ee1c3db 1461
82e3b8c1 1462 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1463
62d5d69b
MK		 1464 dev_priv->suspend_count++;
1465
f74ed08d 1466 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1467
1f814dac
ID		 1468out:
1469 enable_rpm_wakeref_asserts(dev_priv);
1470
1471 return error;
84b79f8d
RW		 1472}
1473
c49d13ee 1474static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
c3c09c95 1475{
c49d13ee 1476 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1477 struct pci_dev *pdev = dev_priv->drm.pdev;
bc87229f 1478 bool fw_csr;
c3c09c95
ID		 1479 int ret;
1480
1f814dac
ID		 1481 disable_rpm_wakeref_asserts(dev_priv);
1482
4c494a57
ID		 1483 intel_display_set_init_power(dev_priv, false);
1484
b9fd799e 1485 fw_csr = !IS_GEN9_LP(dev_priv) &&
a7c8125f 1486 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1487 /*
1488 * In case of firmware assisted context save/restore don't manually
1489 * deinit the power domains. This also means the CSR/DMC firmware will
1490 * stay active, it will power down any HW resources as required and
1491 * also enable deeper system power states that would be blocked if the
1492 * firmware was inactive.
1493 */
1494 if (!fw_csr)
1495 intel_power_domains_suspend(dev_priv);
73dfc227 1496
507e126e 1497 ret = 0;
b9fd799e 1498 if (IS_GEN9_LP(dev_priv))
507e126e 1499 bxt_enable_dc9(dev_priv);
b8aea3d1 1500 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1501 hsw_enable_pc8(dev_priv);
1502 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1503 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1504
1505 if (ret) {
1506 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1507 if (!fw_csr)
1508 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1509
1f814dac 1510 goto out;
c3c09c95
ID		 1511 }
1512
52a05c30 1513 pci_disable_device(pdev);
ab3be73f 1514 /*
54875571 1515 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1516 * the device even though it's already in D3 and hang the machine. So
1517 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1518 * power down the device properly. The issue was seen on multiple old
1519 * GENs with different BIOS vendors, so having an explicit blacklist
1520 * is inpractical; apply the workaround on everything pre GEN6. The
1521 * platforms where the issue was seen:
1522 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1523 * Fujitsu FSC S7110
1524 * Acer Aspire 1830T
ab3be73f 1525 */
514e1d64 1526 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
52a05c30 1527 pci_set_power_state(pdev, PCI_D3hot);
c3c09c95 1528
bc87229f
ID		 1529 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1530
1f814dac
ID		 1531out:
1532 enable_rpm_wakeref_asserts(dev_priv);
1533
1534 return ret;
c3c09c95
ID		 1535}
1536
a9a251c2 1537static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1538{
1539 int error;
1540
ded8b07d 1541 if (!dev) {
84b79f8d
RW		 1542 DRM_ERROR("dev: %p\n", dev);
1543 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1544 return -ENODEV;
1545 }
1546
0b14cbd2
ID		 1547 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1548 state.event != PM_EVENT_FREEZE))
1549 return -EINVAL;
5bcf719b
DA		 1550
1551 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1552 return 0;
6eecba33 1553
5e365c39 1554 error = i915_drm_suspend(dev);
84b79f8d
RW		 1555 if (error)
1556 return error;
1557
ab3be73f 1558 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1559}
1560
5e365c39 1561static int i915_drm_resume(struct drm_device *dev)
76c4b250 1562{
fac5e23e 1563 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1564 int ret;
9d49c0ef 1565
1f814dac 1566 disable_rpm_wakeref_asserts(dev_priv);
abc80abd 1567 intel_sanitize_gt_powersave(dev_priv);
1f814dac 1568
97d6d7ab 1569 ret = i915_ggtt_enable_hw(dev_priv);
ac840ae5
VS		 1570 if (ret)
1571 DRM_ERROR("failed to re-enable GGTT\n");
1572
f74ed08d
ID		 1573 intel_csr_ucode_resume(dev_priv);
1574
bf9e8429 1575 i915_gem_resume(dev_priv);
9d49c0ef 1576
af6dc742 1577 i915_restore_state(dev_priv);
8090ba8c 1578 intel_pps_unlock_regs_wa(dev_priv);
6f9f4b7a 1579 intel_opregion_setup(dev_priv);
61caf87c 1580
c39055b0 1581 intel_init_pch_refclk(dev_priv);
1833b134 1582
364aece0
PA		 1583 /*
1584 * Interrupts have to be enabled before any batches are run. If not the
1585 * GPU will hang. i915_gem_init_hw() will initiate batches to
1586 * update/restore the context.
1587 *
908764f6
ID		 1588 * drm_mode_config_reset() needs AUX interrupts.
1589 *
364aece0
PA		 1590 * Modeset enabling in intel_modeset_init_hw() also needs working
1591 * interrupts.
1592 */
1593 intel_runtime_pm_enable_interrupts(dev_priv);
1594
908764f6
ID		 1595 drm_mode_config_reset(dev);
1596
d5818938 1597 mutex_lock(&dev->struct_mutex);
bf9e8429 1598 if (i915_gem_init_hw(dev_priv)) {
d5818938 1599 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
821ed7df 1600 i915_gem_set_wedged(dev_priv);
d5818938
DV		 1601 }
1602 mutex_unlock(&dev->struct_mutex);
226485e9 1603
bf9e8429 1604 intel_guc_resume(dev_priv);
a1c41994 1605
d5818938 1606 intel_modeset_init_hw(dev);
24576d23 1607
d5818938
DV		 1608 spin_lock_irq(&dev_priv->irq_lock);
1609 if (dev_priv->display.hpd_irq_setup)
91d14251 1610 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1611 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1612
d5818938 1613 intel_dp_mst_resume(dev);
e7d6f7d7 1614
a16b7658
L		 1615 intel_display_resume(dev);
1616
e0b70061
L		 1617 drm_kms_helper_poll_enable(dev);
1618
d5818938
DV		 1619 /*
1620 * ... but also need to make sure that hotplug processing
1621 * doesn't cause havoc. Like in the driver load code we don't
1622 * bother with the tiny race here where we might loose hotplug
1623 * notifications.
1624 * */
1625 intel_hpd_init(dev_priv);
1daed3fb 1626
03d92e47 1627 intel_opregion_register(dev_priv);
44834a67 1628
82e3b8c1 1629 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1630
b8efb17b
ZR		 1631 mutex_lock(&dev_priv->modeset_restore_lock);
1632 dev_priv->modeset_restore = MODESET_DONE;
1633 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1634
6f9f4b7a 1635 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1636
54b4f68f 1637 intel_autoenable_gt_powersave(dev_priv);
ee6f280e 1638
1f814dac
ID		 1639 enable_rpm_wakeref_asserts(dev_priv);
1640
074c6ada 1641 return 0;
84b79f8d
RW		 1642}
1643
5e365c39 1644static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1645{
fac5e23e 1646 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1647 struct pci_dev *pdev = dev_priv->drm.pdev;
44410cd0 1648 int ret;
36d61e67 1649
76c4b250
ID		 1650 /*
1651 * We have a resume ordering issue with the snd-hda driver also
1652 * requiring our device to be power up. Due to the lack of a
1653 * parent/child relationship we currently solve this with an early
1654 * resume hook.
1655 *
1656 * FIXME: This should be solved with a special hdmi sink device or
1657 * similar so that power domains can be employed.
1658 */
44410cd0
ID		 1659
1660 /*
1661 * Note that we need to set the power state explicitly, since we
1662 * powered off the device during freeze and the PCI core won't power
1663 * it back up for us during thaw. Powering off the device during
1664 * freeze is not a hard requirement though, and during the
1665 * suspend/resume phases the PCI core makes sure we get here with the
1666 * device powered on. So in case we change our freeze logic and keep
1667 * the device powered we can also remove the following set power state
1668 * call.
1669 */
52a05c30 1670 ret = pci_set_power_state(pdev, PCI_D0);
44410cd0
ID		 1671 if (ret) {
1672 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1673 goto out;
1674 }
1675
1676 /*
1677 * Note that pci_enable_device() first enables any parent bridge
1678 * device and only then sets the power state for this device. The
1679 * bridge enabling is a nop though, since bridge devices are resumed
1680 * first. The order of enabling power and enabling the device is
1681 * imposed by the PCI core as described above, so here we preserve the
1682 * same order for the freeze/thaw phases.
1683 *
1684 * TODO: eventually we should remove pci_disable_device() /
1685 * pci_enable_enable_device() from suspend/resume. Due to how they
1686 * depend on the device enable refcount we can't anyway depend on them
1687 * disabling/enabling the device.
1688 */
52a05c30 1689 if (pci_enable_device(pdev)) {
bc87229f
ID		 1690 ret = -EIO;
1691 goto out;
1692 }
84b79f8d 1693
52a05c30 1694 pci_set_master(pdev);
84b79f8d 1695
1f814dac
ID		 1696 disable_rpm_wakeref_asserts(dev_priv);
1697
666a4537 1698 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1699 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1700 if (ret)
ff0b187f
DL		 1701 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1702 ret);
36d61e67 1703
dc97997a 1704 intel_uncore_early_sanitize(dev_priv, true);
efee833a 1705
b9fd799e 1706 if (IS_GEN9_LP(dev_priv)) {
da2f41d1
ID		 1707 if (!dev_priv->suspended_to_idle)
1708 gen9_sanitize_dc_state(dev_priv);
507e126e 1709 bxt_disable_dc9(dev_priv);
da2f41d1 1710 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1711 hsw_disable_pc8(dev_priv);
da2f41d1 1712 }
efee833a 1713
dc97997a 1714 intel_uncore_sanitize(dev_priv);
bc87229f 1715
b9fd799e 1716 if (IS_GEN9_LP(dev_priv) ||
a7c8125f 1717 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 1718 intel_power_domains_init_hw(dev_priv, true);
1719
6e35e8ab
ID		 1720 enable_rpm_wakeref_asserts(dev_priv);
1721
bc87229f
ID		 1722out:
1723 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1724
1725 return ret;
76c4b250
ID		 1726}
1727
7f26cb88 1728static int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1729{
50a0072f 1730 int ret;
76c4b250 1731
097dd837
ID		 1732 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1733 return 0;
1734
5e365c39 1735 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1736 if (ret)
1737 return ret;
1738
5a17514e
ID		 1739 return i915_drm_resume(dev);
1740}
1741
11ed50ec 1742/**
f3953dcb 1743 * i915_reset - reset chip after a hang
df210574 1744 * @dev_priv: device private to reset
11ed50ec 1745 *
780f262a
CW		 1746 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1747 * on failure.
11ed50ec 1748 *
221fe799
CW		 1749 * Caller must hold the struct_mutex.
1750 *
11ed50ec
BG		 1751 * Procedure is fairly simple:
1752 * - reset the chip using the reset reg
1753 * - re-init context state
1754 * - re-init hardware status page
1755 * - re-init ring buffer
1756 * - re-init interrupt state
1757 * - re-init display
1758 */
780f262a 1759void i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 1760{
d98c52cf 1761 struct i915_gpu_error *error = &dev_priv->gpu_error;
0573ed4a 1762 int ret;
11ed50ec 1763
bf9e8429 1764 lockdep_assert_held(&dev_priv->drm.struct_mutex);
221fe799
CW		 1765
1766 if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
780f262a 1767 return;
11ed50ec 1768
d98c52cf 1769 /* Clear any previous failed attempts at recovery. Time to try again. */
8af29b0c
CW		 1770 __clear_bit(I915_WEDGED, &error->flags);
1771 error->reset_count++;
d98c52cf 1772
7b4d3a16 1773 pr_notice("drm/i915: Resetting chip after gpu hang\n");
4c965543 1774 disable_irq(dev_priv->drm.irq);
0e178aef
CW		 1775 ret = i915_gem_reset_prepare(dev_priv);
1776 if (ret) {
1777 DRM_ERROR("GPU recovery failed\n");
1778 intel_gpu_reset(dev_priv, ALL_ENGINES);
1779 goto error;
1780 }
9e60ab03 1781
dc97997a 1782 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
0573ed4a 1783 if (ret) {
804e59a8
CW		 1784 if (ret != -ENODEV)
1785 DRM_ERROR("Failed to reset chip: %i\n", ret);
1786 else
1787 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 1788 goto error;
11ed50ec
BG		 1789 }
1790
da9a796f 1791 i915_gem_reset(dev_priv);
1362b776
VS		 1792 intel_overlay_reset(dev_priv);
1793
11ed50ec
BG		 1794 /* Ok, now get things going again... */
1795
1796 /*
1797 * Everything depends on having the GTT running, so we need to start
1798 * there. Fortunately we don't need to do this unless we reset the
1799 * chip at a PCI level.
1800 *
1801 * Next we need to restore the context, but we don't use those
1802 * yet either...
1803 *
1804 * Ring buffer needs to be re-initialized in the KMS case, or if X
1805 * was running at the time of the reset (i.e. we weren't VT
1806 * switched away).
1807 */
bf9e8429 1808 ret = i915_gem_init_hw(dev_priv);
33d30a9c
DV		 1809 if (ret) {
1810 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1811 goto error;
11ed50ec
BG		 1812 }
1813
da9a796f 1814 i915_gem_reset_finish(dev_priv);
c2a126a4
CW		 1815 i915_queue_hangcheck(dev_priv);
1816
780f262a 1817wakeup:
4c965543 1818 enable_irq(dev_priv->drm.irq);
780f262a
CW		 1819 wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1820 return;
d98c52cf
CW		 1821
1822error:
821ed7df 1823 i915_gem_set_wedged(dev_priv);
780f262a 1824 goto wakeup;
11ed50ec
BG		 1825}
1826
c49d13ee 1827static int i915_pm_suspend(struct device *kdev)
112b715e 1828{
c49d13ee
DW		 1829 struct pci_dev *pdev = to_pci_dev(kdev);
1830 struct drm_device *dev = pci_get_drvdata(pdev);
112b715e 1831
c49d13ee
DW		 1832 if (!dev) {
1833 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
84b79f8d
RW		 1834 return -ENODEV;
1835 }
112b715e 1836
c49d13ee 1837 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
5bcf719b
DA		 1838 return 0;
1839
c49d13ee 1840 return i915_drm_suspend(dev);
76c4b250
ID		 1841}
1842
c49d13ee 1843static int i915_pm_suspend_late(struct device *kdev)
76c4b250 1844{
c49d13ee 1845 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250
ID		 1846
1847 /*
c965d995 1848 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 1849 * requiring our device to be power up. Due to the lack of a
1850 * parent/child relationship we currently solve this with an late
1851 * suspend hook.
1852 *
1853 * FIXME: This should be solved with a special hdmi sink device or
1854 * similar so that power domains can be employed.
1855 */
c49d13ee 1856 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
76c4b250 1857 return 0;
112b715e 1858
c49d13ee 1859 return i915_drm_suspend_late(dev, false);
ab3be73f
ID		 1860}
1861
c49d13ee 1862static int i915_pm_poweroff_late(struct device *kdev)
ab3be73f 1863{
c49d13ee 1864 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
ab3be73f 1865
c49d13ee 1866 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
ab3be73f
ID		 1867 return 0;
1868
c49d13ee 1869 return i915_drm_suspend_late(dev, true);
cbda12d7
ZW		 1870}
1871
c49d13ee 1872static int i915_pm_resume_early(struct device *kdev)
76c4b250 1873{
c49d13ee 1874 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250 1875
c49d13ee 1876 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1877 return 0;
1878
c49d13ee 1879 return i915_drm_resume_early(dev);
76c4b250
ID		 1880}
1881
c49d13ee 1882static int i915_pm_resume(struct device *kdev)
cbda12d7 1883{
c49d13ee 1884 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
84b79f8d 1885
c49d13ee 1886 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1887 return 0;
1888
c49d13ee 1889 return i915_drm_resume(dev);
cbda12d7
ZW		 1890}
1891
1f19ac2a 1892/* freeze: before creating the hibernation_image */
c49d13ee 1893static int i915_pm_freeze(struct device *kdev)
1f19ac2a 1894{
6a800eab
CW		 1895 int ret;
1896
1897 ret = i915_pm_suspend(kdev);
1898 if (ret)
1899 return ret;
1900
1901 ret = i915_gem_freeze(kdev_to_i915(kdev));
1902 if (ret)
1903 return ret;
1904
1905 return 0;
1f19ac2a
CW		 1906}
1907
c49d13ee 1908static int i915_pm_freeze_late(struct device *kdev)
1f19ac2a 1909{
461fb99c
CW		 1910 int ret;
1911
c49d13ee 1912 ret = i915_pm_suspend_late(kdev);
461fb99c
CW		 1913 if (ret)
1914 return ret;
1915
c49d13ee 1916 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
461fb99c
CW		 1917 if (ret)
1918 return ret;
1919
1920 return 0;
1f19ac2a
CW		 1921}
1922
1923/* thaw: called after creating the hibernation image, but before turning off. */
c49d13ee 1924static int i915_pm_thaw_early(struct device *kdev)
1f19ac2a 1925{
c49d13ee 1926 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1927}
1928
c49d13ee 1929static int i915_pm_thaw(struct device *kdev)
1f19ac2a 1930{
c49d13ee 1931 return i915_pm_resume(kdev);
1f19ac2a
CW		 1932}
1933
1934/* restore: called after loading the hibernation image. */
c49d13ee 1935static int i915_pm_restore_early(struct device *kdev)
1f19ac2a 1936{
c49d13ee 1937 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1938}
1939
c49d13ee 1940static int i915_pm_restore(struct device *kdev)
1f19ac2a 1941{
c49d13ee 1942 return i915_pm_resume(kdev);
1f19ac2a
CW		 1943}
1944
ddeea5b0
ID		 1945/*
1946 * Save all Gunit registers that may be lost after a D3 and a subsequent
1947 * S0i[R123] transition. The list of registers needing a save/restore is
1948 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1949 * registers in the following way:
1950 * - Driver: saved/restored by the driver
1951 * - Punit : saved/restored by the Punit firmware
1952 * - No, w/o marking: no need to save/restore, since the register is R/O or
1953 * used internally by the HW in a way that doesn't depend
1954 * keeping the content across a suspend/resume.
1955 * - Debug : used for debugging
1956 *
1957 * We save/restore all registers marked with 'Driver', with the following
1958 * exceptions:
1959 * - Registers out of use, including also registers marked with 'Debug'.
1960 * These have no effect on the driver's operation, so we don't save/restore
1961 * them to reduce the overhead.
1962 * - Registers that are fully setup by an initialization function called from
1963 * the resume path. For example many clock gating and RPS/RC6 registers.
1964 * - Registers that provide the right functionality with their reset defaults.
1965 *
1966 * TODO: Except for registers that based on the above 3 criteria can be safely
1967 * ignored, we save/restore all others, practically treating the HW context as
1968 * a black-box for the driver. Further investigation is needed to reduce the
1969 * saved/restored registers even further, by following the same 3 criteria.
1970 */
1971static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1972{
1973 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1974 int i;
1975
1976 /* GAM 0x4000-0x4770 */
1977 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1978 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1979 s->arb_mode = I915_READ(ARB_MODE);
1980 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1981 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1982
1983 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 1984 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 1985
1986 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 1987 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 1988
1989 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1990 s->ecochk = I915_READ(GAM_ECOCHK);
1991 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1992 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1993
1994 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1995
1996 /* MBC 0x9024-0x91D0, 0x8500 */
1997 s->g3dctl = I915_READ(VLV_G3DCTL);
1998 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1999 s->mbctl = I915_READ(GEN6_MBCTL);
2000
2001 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2002 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2003 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2004 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2005 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2006 s->rstctl = I915_READ(GEN6_RSTCTL);
2007 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2008
2009 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2010 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2011 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2012 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2013 s->ecobus = I915_READ(ECOBUS);
2014 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2015 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2016 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2017 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2018 s->rcedata = I915_READ(VLV_RCEDATA);
2019 s->spare2gh = I915_READ(VLV_SPAREG2H);
2020
2021 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2022 s->gt_imr = I915_READ(GTIMR);
2023 s->gt_ier = I915_READ(GTIER);
2024 s->pm_imr = I915_READ(GEN6_PMIMR);
2025 s->pm_ier = I915_READ(GEN6_PMIER);
2026
2027 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2028 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2029
2030 /* GT SA CZ domain, 0x100000-0x138124 */
2031 s->tilectl = I915_READ(TILECTL);
2032 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2033 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2034 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2035 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2036
2037 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2038 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2039 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2040 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2041 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2042
2043 /*
2044 * Not saving any of:
2045 * DFT, 0x9800-0x9EC0
2046 * SARB, 0xB000-0xB1FC
2047 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2048 * PCI CFG
2049 */
2050}
2051
2052static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2053{
2054 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2055 u32 val;
2056 int i;
2057
2058 /* GAM 0x4000-0x4770 */
2059 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2060 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2061 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2062 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2063 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2064
2065 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2066 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2067
2068 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2069 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2070
2071 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2072 I915_WRITE(GAM_ECOCHK, s->ecochk);
2073 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2074 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2075
2076 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2077
2078 /* MBC 0x9024-0x91D0, 0x8500 */
2079 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2080 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2081 I915_WRITE(GEN6_MBCTL, s->mbctl);
2082
2083 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2084 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2085 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2086 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2087 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2088 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2089 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2090
2091 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2092 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2093 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2094 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2095 I915_WRITE(ECOBUS, s->ecobus);
2096 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2097 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2098 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2099 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2100 I915_WRITE(VLV_RCEDATA, s->rcedata);
2101 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2102
2103 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2104 I915_WRITE(GTIMR, s->gt_imr);
2105 I915_WRITE(GTIER, s->gt_ier);
2106 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2107 I915_WRITE(GEN6_PMIER, s->pm_ier);
2108
2109 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2110 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2111
2112 /* GT SA CZ domain, 0x100000-0x138124 */
2113 I915_WRITE(TILECTL, s->tilectl);
2114 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2115 /*
2116 * Preserve the GT allow wake and GFX force clock bit, they are not
2117 * be restored, as they are used to control the s0ix suspend/resume
2118 * sequence by the caller.
2119 */
2120 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2121 val &= VLV_GTLC_ALLOWWAKEREQ;
2122 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2123 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2124
2125 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2126 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2127 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2128 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2129
2130 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2131
2132 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2133 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2134 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2135 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2136 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2137}
2138
650ad970
ID		 2139int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2140{
2141 u32 val;
2142 int err;
2143
650ad970
ID		 2144 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2145 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2146 if (force_on)
2147 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2148 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2149
2150 if (!force_on)
2151 return 0;
2152
c6ddc5f3
CW		 2153 err = intel_wait_for_register(dev_priv,
2154 VLV_GTLC_SURVIVABILITY_REG,
2155 VLV_GFX_CLK_STATUS_BIT,
2156 VLV_GFX_CLK_STATUS_BIT,
2157 20);
650ad970
ID		 2158 if (err)
2159 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2160 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2161
2162 return err;
650ad970
ID		 2163}
2164
ddeea5b0
ID		 2165static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2166{
2167 u32 val;
2168 int err = 0;
2169
2170 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2171 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2172 if (allow)
2173 val |= VLV_GTLC_ALLOWWAKEREQ;
2174 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2175 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2176
b2736695
CW		 2177 err = intel_wait_for_register(dev_priv,
2178 VLV_GTLC_PW_STATUS,
2179 VLV_GTLC_ALLOWWAKEACK,
2180 allow,
2181 1);
ddeea5b0
ID		 2182 if (err)
2183 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2184
ddeea5b0 2185 return err;
ddeea5b0
ID		 2186}
2187
2188static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2189 bool wait_for_on)
2190{
2191 u32 mask;
2192 u32 val;
2193 int err;
2194
2195 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2196 val = wait_for_on ? mask : 0;
41ce405e 2197 if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
ddeea5b0
ID		 2198 return 0;
2199
2200 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
87ad3212
JN		 2201 onoff(wait_for_on),
2202 I915_READ(VLV_GTLC_PW_STATUS));
ddeea5b0
ID		 2203
2204 /*
2205 * RC6 transitioning can be delayed up to 2 msec (see
2206 * valleyview_enable_rps), use 3 msec for safety.
2207 */
41ce405e
CW		 2208 err = intel_wait_for_register(dev_priv,
2209 VLV_GTLC_PW_STATUS, mask, val,
2210 3);
ddeea5b0
ID		 2211 if (err)
2212 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2213 onoff(wait_for_on));
ddeea5b0
ID		 2214
2215 return err;
ddeea5b0
ID		 2216}
2217
2218static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2219{
2220 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2221 return;
2222
6fa283b0 2223 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2224 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2225}
2226
ebc32824 2227static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2228{
2229 u32 mask;
2230 int err;
2231
2232 /*
2233 * Bspec defines the following GT well on flags as debug only, so
2234 * don't treat them as hard failures.
2235 */
2236 (void)vlv_wait_for_gt_wells(dev_priv, false);
2237
2238 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2239 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2240
2241 vlv_check_no_gt_access(dev_priv);
2242
2243 err = vlv_force_gfx_clock(dev_priv, true);
2244 if (err)
2245 goto err1;
2246
2247 err = vlv_allow_gt_wake(dev_priv, false);
2248 if (err)
2249 goto err2;
98711167 2250
2d1fe073 2251 if (!IS_CHERRYVIEW(dev_priv))
98711167 2252 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2253
2254 err = vlv_force_gfx_clock(dev_priv, false);
2255 if (err)
2256 goto err2;
2257
2258 return 0;
2259
2260err2:
2261 /* For safety always re-enable waking and disable gfx clock forcing */
2262 vlv_allow_gt_wake(dev_priv, true);
2263err1:
2264 vlv_force_gfx_clock(dev_priv, false);
2265
2266 return err;
2267}
2268
016970be
SK		 2269static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2270 bool rpm_resume)
ddeea5b0 2271{
ddeea5b0
ID		 2272 int err;
2273 int ret;
2274
2275 /*
2276 * If any of the steps fail just try to continue, that's the best we
2277 * can do at this point. Return the first error code (which will also
2278 * leave RPM permanently disabled).
2279 */
2280 ret = vlv_force_gfx_clock(dev_priv, true);
2281
2d1fe073 2282 if (!IS_CHERRYVIEW(dev_priv))
98711167 2283 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2284
2285 err = vlv_allow_gt_wake(dev_priv, true);
2286 if (!ret)
2287 ret = err;
2288
2289 err = vlv_force_gfx_clock(dev_priv, false);
2290 if (!ret)
2291 ret = err;
2292
2293 vlv_check_no_gt_access(dev_priv);
2294
7c108fd8 2295 if (rpm_resume)
46f16e63 2296 intel_init_clock_gating(dev_priv);
ddeea5b0
ID		 2297
2298 return ret;
2299}
2300
c49d13ee 2301static int intel_runtime_suspend(struct device *kdev)
8a187455 2302{
c49d13ee 2303 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2304 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2305 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2306 int ret;
8a187455 2307
dc97997a 2308 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2309 return -ENODEV;
2310
6772ffe0 2311 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7
ID		 2312 return -ENODEV;
2313
8a187455
PZ		 2314 DRM_DEBUG_KMS("Suspending device\n");
2315
1f814dac
ID		 2316 disable_rpm_wakeref_asserts(dev_priv);
2317
d6102977
ID		 2318 /*
2319 * We are safe here against re-faults, since the fault handler takes
2320 * an RPM reference.
2321 */
7c108fd8 2322 i915_gem_runtime_suspend(dev_priv);
d6102977 2323
bf9e8429 2324 intel_guc_suspend(dev_priv);
a1c41994 2325
2eb5252e 2326 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2327
507e126e 2328 ret = 0;
b9fd799e 2329 if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2330 bxt_display_core_uninit(dev_priv);
2331 bxt_enable_dc9(dev_priv);
2332 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2333 hsw_enable_pc8(dev_priv);
2334 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2335 ret = vlv_suspend_complete(dev_priv);
2336 }
2337
0ab9cfeb
ID		 2338 if (ret) {
2339 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2340 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2341
1f814dac
ID		 2342 enable_rpm_wakeref_asserts(dev_priv);
2343
0ab9cfeb
ID		 2344 return ret;
2345 }
a8a8bd54 2346
dc97997a 2347 intel_uncore_forcewake_reset(dev_priv, false);
1f814dac
ID		 2348
2349 enable_rpm_wakeref_asserts(dev_priv);
2350 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2351
bc3b9346 2352 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2353 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2354
8a187455 2355 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2356
2357 /*
c8a0bd42
PZ		 2358 * FIXME: We really should find a document that references the arguments
2359 * used below!
1fb2362b 2360 */
6f9f4b7a 2361 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2362 /*
2363 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2364 * being detected, and the call we do at intel_runtime_resume()
2365 * won't be able to restore them. Since PCI_D3hot matches the
2366 * actual specification and appears to be working, use it.
2367 */
6f9f4b7a 2368 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2369 } else {
c8a0bd42
PZ		 2370 /*
2371 * current versions of firmware which depend on this opregion
2372 * notification have repurposed the D1 definition to mean
2373 * "runtime suspended" vs. what you would normally expect (D3)
2374 * to distinguish it from notifications that might be sent via
2375 * the suspend path.
2376 */
6f9f4b7a 2377 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2378 }
8a187455 2379
59bad947 2380 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2381
21d6e0bd 2382 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
19625e85
L		 2383 intel_hpd_poll_init(dev_priv);
2384
a8a8bd54 2385 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2386 return 0;
2387}
2388
c49d13ee 2389static int intel_runtime_resume(struct device *kdev)
8a187455 2390{
c49d13ee 2391 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2392 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2393 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2394 int ret = 0;
8a187455 2395
6772ffe0 2396 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7 2397 return -ENODEV;
8a187455
PZ		 2398
2399 DRM_DEBUG_KMS("Resuming device\n");
2400
1f814dac
ID		 2401 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2402 disable_rpm_wakeref_asserts(dev_priv);
2403
6f9f4b7a 2404 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2405 dev_priv->pm.suspended = false;
55ec45c2
MK		 2406 if (intel_uncore_unclaimed_mmio(dev_priv))
2407 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2408
bf9e8429 2409 intel_guc_resume(dev_priv);
a1c41994 2410
1a5df187 2411 if (IS_GEN6(dev_priv))
c39055b0 2412 intel_init_pch_refclk(dev_priv);
31335cec 2413
b9fd799e 2414 if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2415 bxt_disable_dc9(dev_priv);
2416 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2417 if (dev_priv->csr.dmc_payload &&
2418 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2419 gen9_enable_dc5(dev_priv);
507e126e 2420 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2421 hsw_disable_pc8(dev_priv);
507e126e 2422 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2423 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2424 }
1a5df187 2425
0ab9cfeb
ID		 2426 /*
2427 * No point of rolling back things in case of an error, as the best
2428 * we can do is to hope that things will still work (and disable RPM).
2429 */
c6be607a 2430 i915_gem_init_swizzling(dev_priv);
83bf6d55 2431 i915_gem_restore_fences(dev_priv);
92b806d3 2432
b963291c 2433 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2434
2435 /*
2436 * On VLV/CHV display interrupts are part of the display
2437 * power well, so hpd is reinitialized from there. For
2438 * everyone else do it here.
2439 */
666a4537 2440 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2441 intel_hpd_init(dev_priv);
2442
1f814dac
ID		 2443 enable_rpm_wakeref_asserts(dev_priv);
2444
0ab9cfeb
ID		 2445 if (ret)
2446 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2447 else
2448 DRM_DEBUG_KMS("Device resumed\n");
2449
2450 return ret;
8a187455
PZ		 2451}
2452
42f5551d 2453const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2454 /*
2455 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2456 * PMSG_RESUME]
2457 */
0206e353 2458 .suspend = i915_pm_suspend,
76c4b250
ID		 2459 .suspend_late = i915_pm_suspend_late,
2460 .resume_early = i915_pm_resume_early,
0206e353 2461 .resume = i915_pm_resume,
5545dbbf
ID		 2462
2463 /*
2464 * S4 event handlers
2465 * @freeze, @freeze_late : called (1) before creating the
2466 * hibernation image [PMSG_FREEZE] and
2467 * (2) after rebooting, before restoring
2468 * the image [PMSG_QUIESCE]
2469 * @thaw, @thaw_early : called (1) after creating the hibernation
2470 * image, before writing it [PMSG_THAW]
2471 * and (2) after failing to create or
2472 * restore the image [PMSG_RECOVER]
2473 * @poweroff, @poweroff_late: called after writing the hibernation
2474 * image, before rebooting [PMSG_HIBERNATE]
2475 * @restore, @restore_early : called after rebooting and restoring the
2476 * hibernation image [PMSG_RESTORE]
2477 */
1f19ac2a
CW		 2478 .freeze = i915_pm_freeze,
2479 .freeze_late = i915_pm_freeze_late,
2480 .thaw_early = i915_pm_thaw_early,
2481 .thaw = i915_pm_thaw,
36d61e67 2482 .poweroff = i915_pm_suspend,
ab3be73f 2483 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2484 .restore_early = i915_pm_restore_early,
2485 .restore = i915_pm_restore,
5545dbbf
ID		 2486
2487 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2488 .runtime_suspend = intel_runtime_suspend,
2489 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2490};
2491
78b68556 2492static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2493 .fault = i915_gem_fault,
ab00b3e5
JB		 2494 .open = drm_gem_vm_open,
2495 .close = drm_gem_vm_close,
de151cf6
JB		 2496};
2497
e08e96de
AV		 2498static const struct file_operations i915_driver_fops = {
2499 .owner = THIS_MODULE,
2500 .open = drm_open,
2501 .release = drm_release,
2502 .unlocked_ioctl = drm_ioctl,
2503 .mmap = drm_gem_mmap,
2504 .poll = drm_poll,
e08e96de 2505 .read = drm_read,
e08e96de 2506 .compat_ioctl = i915_compat_ioctl,
e08e96de
AV		 2507 .llseek = noop_llseek,
2508};
2509
0673ad47
CW		 2510static int
2511i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2512 struct drm_file *file)
2513{
2514 return -ENODEV;
2515}
2516
2517static const struct drm_ioctl_desc i915_ioctls[] = {
2518 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2519 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2520 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2521 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2522 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2523 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2524 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2525 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2526 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2527 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2528 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2529 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2530 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2531 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2532 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2533 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2534 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2535 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2536 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2537 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2538 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2539 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2540 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2541 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2542 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2543 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2544 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2545 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2546 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2547 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2548 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2549 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2550 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2551 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2552 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
111dbcab
CW		 2553 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2554 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
0673ad47
CW		 2555 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2556 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2557 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2558 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2559 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2560 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2561 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2562 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2563 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2564 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2565 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2566 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2567 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2568 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2569 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
eec688e1 2570 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
0673ad47
CW		 2571};
2572
1da177e4 2573static struct drm_driver driver = {
0c54781b
MW		 2574 /* Don't use MTRRs here; the Xserver or userspace app should
2575 * deal with them for Intel hardware.
792d2b9a 2576 */
673a394b 2577 .driver_features =
10ba5012 2578 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1751fcf9 2579 DRIVER_RENDER | DRIVER_MODESET,
673a394b 2580 .open = i915_driver_open,
22eae947
DA		 2581 .lastclose = i915_driver_lastclose,
2582 .preclose = i915_driver_preclose,
673a394b 2583 .postclose = i915_driver_postclose,
915b4d11 2584 .set_busid = drm_pci_set_busid,
d8e29209 2585
b1f788c6 2586 .gem_close_object = i915_gem_close_object,
f0cd5182 2587 .gem_free_object_unlocked = i915_gem_free_object,
de151cf6 2588 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2589
2590 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2591 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2592 .gem_prime_export = i915_gem_prime_export,
2593 .gem_prime_import = i915_gem_prime_import,
2594
ff72145b 2595 .dumb_create = i915_gem_dumb_create,
da6b51d0 2596 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 2597 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 2598 .ioctls = i915_ioctls,
0673ad47 2599 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2600 .fops = &i915_driver_fops,
22eae947
DA		 2601 .name = DRIVER_NAME,
2602 .desc = DRIVER_DESC,
2603 .date = DRIVER_DATE,
2604 .major = DRIVER_MAJOR,
2605 .minor = DRIVER_MINOR,
2606 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2607};
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