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drm/i915/huc: Support HuC authentication
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
0673ad47
CW		 46#include <drm/i915_drm.h>
47
48#include "i915_drv.h"
49#include "i915_trace.h"
50#include "i915_vgpu.h"
51#include "intel_drv.h"
79e53945 52
112b715e
KH		 53static struct drm_driver driver;
54
0673ad47
CW		 55static unsigned int i915_load_fail_count;
56
57bool __i915_inject_load_failure(const char *func, int line)
58{
59 if (i915_load_fail_count >= i915.inject_load_failure)
60 return false;
61
62 if (++i915_load_fail_count == i915.inject_load_failure) {
63 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
64 i915.inject_load_failure, func, line);
65 return true;
66 }
67
68 return false;
69}
70
71#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
72#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
73 "providing the dmesg log by booting with drm.debug=0xf"
74
75void
76__i915_printk(struct drm_i915_private *dev_priv, const char *level,
77 const char *fmt, ...)
78{
79 static bool shown_bug_once;
c49d13ee 80 struct device *kdev = dev_priv->drm.dev;
0673ad47
CW		 81 bool is_error = level[1] <= KERN_ERR[1];
82 bool is_debug = level[1] == KERN_DEBUG[1];
83 struct va_format vaf;
84 va_list args;
85
86 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
87 return;
88
89 va_start(args, fmt);
90
91 vaf.fmt = fmt;
92 vaf.va = &args;
93
c49d13ee 94 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
0673ad47
CW		 95 __builtin_return_address(0), &vaf);
96
97 if (is_error && !shown_bug_once) {
c49d13ee 98 dev_notice(kdev, "%s", FDO_BUG_MSG);
0673ad47
CW		 99 shown_bug_once = true;
100 }
101
102 va_end(args);
103}
104
105static bool i915_error_injected(struct drm_i915_private *dev_priv)
106{
107 return i915.inject_load_failure &&
108 i915_load_fail_count == i915.inject_load_failure;
109}
110
111#define i915_load_error(dev_priv, fmt, ...) \
112 __i915_printk(dev_priv, \
113 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
114 fmt, ##__VA_ARGS__)
115
116
fd6b8f43 117static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
0673ad47
CW		 118{
119 enum intel_pch ret = PCH_NOP;
120
121 /*
122 * In a virtualized passthrough environment we can be in a
123 * setup where the ISA bridge is not able to be passed through.
124 * In this case, a south bridge can be emulated and we have to
125 * make an educated guess as to which PCH is really there.
126 */
127
fd6b8f43 128 if (IS_GEN5(dev_priv)) {
0673ad47
CW		 129 ret = PCH_IBX;
130 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
fd6b8f43 131 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
0673ad47
CW		 132 ret = PCH_CPT;
133 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
fd6b8f43 134 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0673ad47
CW		 135 ret = PCH_LPT;
136 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
fd6b8f43 137 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
0673ad47
CW		 138 ret = PCH_SPT;
139 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
140 }
141
142 return ret;
143}
144
da5f53bf 145static void intel_detect_pch(struct drm_i915_private *dev_priv)
0673ad47 146{
0673ad47
CW		 147 struct pci_dev *pch = NULL;
148
149 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
150 * (which really amounts to a PCH but no South Display).
151 */
b7f05d4a 152 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
0673ad47
CW		 153 dev_priv->pch_type = PCH_NOP;
154 return;
155 }
156
157 /*
158 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
159 * make graphics device passthrough work easy for VMM, that only
160 * need to expose ISA bridge to let driver know the real hardware
161 * underneath. This is a requirement from virtualization team.
162 *
163 * In some virtualized environments (e.g. XEN), there is irrelevant
164 * ISA bridge in the system. To work reliably, we should scan trhough
165 * all the ISA bridge devices and check for the first match, instead
166 * of only checking the first one.
167 */
168 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
169 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
170 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
171 dev_priv->pch_id = id;
172
173 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
174 dev_priv->pch_type = PCH_IBX;
175 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
5db94019 176 WARN_ON(!IS_GEN5(dev_priv));
0673ad47
CW		 177 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
178 dev_priv->pch_type = PCH_CPT;
179 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
fd6b8f43
TU		 180 WARN_ON(!(IS_GEN6(dev_priv) ||
181 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 182 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
183 /* PantherPoint is CPT compatible */
184 dev_priv->pch_type = PCH_CPT;
185 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
fd6b8f43
TU		 186 WARN_ON(!(IS_GEN6(dev_priv) ||
187 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 188 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
189 dev_priv->pch_type = PCH_LPT;
190 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
8652744b
TU		 191 WARN_ON(!IS_HASWELL(dev_priv) &&
192 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 193 WARN_ON(IS_HSW_ULT(dev_priv) ||
194 IS_BDW_ULT(dev_priv));
0673ad47
CW		 195 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
196 dev_priv->pch_type = PCH_LPT;
197 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
8652744b
TU		 198 WARN_ON(!IS_HASWELL(dev_priv) &&
199 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 200 WARN_ON(!IS_HSW_ULT(dev_priv) &&
201 !IS_BDW_ULT(dev_priv));
0673ad47
CW		 202 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
203 dev_priv->pch_type = PCH_SPT;
204 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
0853723b
TU		 205 WARN_ON(!IS_SKYLAKE(dev_priv) &&
206 !IS_KABYLAKE(dev_priv));
0673ad47
CW		 207 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
208 dev_priv->pch_type = PCH_SPT;
209 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
0853723b
TU		 210 WARN_ON(!IS_SKYLAKE(dev_priv) &&
211 !IS_KABYLAKE(dev_priv));
22dea0be
RV		 212 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
213 dev_priv->pch_type = PCH_KBP;
214 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
0853723b 215 WARN_ON(!IS_KABYLAKE(dev_priv));
0673ad47
CW		 216 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
217 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
218 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
219 pch->subsystem_vendor ==
220 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
221 pch->subsystem_device ==
222 PCI_SUBDEVICE_ID_QEMU)) {
fd6b8f43
TU		 223 dev_priv->pch_type =
224 intel_virt_detect_pch(dev_priv);
0673ad47
CW		 225 } else
226 continue;
227
228 break;
229 }
230 }
231 if (!pch)
232 DRM_DEBUG_KMS("No PCH found.\n");
233
234 pci_dev_put(pch);
235}
236
0673ad47
CW		 237static int i915_getparam(struct drm_device *dev, void *data,
238 struct drm_file *file_priv)
239{
fac5e23e 240 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 241 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 242 drm_i915_getparam_t *param = data;
243 int value;
244
245 switch (param->param) {
246 case I915_PARAM_IRQ_ACTIVE:
247 case I915_PARAM_ALLOW_BATCHBUFFER:
248 case I915_PARAM_LAST_DISPATCH:
249 /* Reject all old ums/dri params. */
250 return -ENODEV;
251 case I915_PARAM_CHIPSET_ID:
52a05c30 252 value = pdev->device;
0673ad47
CW		 253 break;
254 case I915_PARAM_REVISION:
52a05c30 255 value = pdev->revision;
0673ad47 256 break;
0673ad47
CW		 257 case I915_PARAM_NUM_FENCES_AVAIL:
258 value = dev_priv->num_fence_regs;
259 break;
260 case I915_PARAM_HAS_OVERLAY:
261 value = dev_priv->overlay ? 1 : 0;
262 break;
0673ad47 263 case I915_PARAM_HAS_BSD:
3b3f1650 264 value = !!dev_priv->engine[VCS];
0673ad47
CW		 265 break;
266 case I915_PARAM_HAS_BLT:
3b3f1650 267 value = !!dev_priv->engine[BCS];
0673ad47
CW		 268 break;
269 case I915_PARAM_HAS_VEBOX:
3b3f1650 270 value = !!dev_priv->engine[VECS];
0673ad47
CW		 271 break;
272 case I915_PARAM_HAS_BSD2:
3b3f1650 273 value = !!dev_priv->engine[VCS2];
0673ad47 274 break;
0673ad47 275 case I915_PARAM_HAS_EXEC_CONSTANTS:
16162470 276 value = INTEL_GEN(dev_priv) >= 4;
0673ad47
CW		 277 break;
278 case I915_PARAM_HAS_LLC:
16162470 279 value = HAS_LLC(dev_priv);
0673ad47
CW		 280 break;
281 case I915_PARAM_HAS_WT:
16162470 282 value = HAS_WT(dev_priv);
0673ad47
CW		 283 break;
284 case I915_PARAM_HAS_ALIASING_PPGTT:
16162470 285 value = USES_PPGTT(dev_priv);
0673ad47
CW		 286 break;
287 case I915_PARAM_HAS_SEMAPHORES:
39df9190 288 value = i915.semaphores;
0673ad47 289 break;
0673ad47
CW		 290 case I915_PARAM_HAS_SECURE_BATCHES:
291 value = capable(CAP_SYS_ADMIN);
292 break;
0673ad47
CW		 293 case I915_PARAM_CMD_PARSER_VERSION:
294 value = i915_cmd_parser_get_version(dev_priv);
295 break;
0673ad47 296 case I915_PARAM_SUBSLICE_TOTAL:
57ec171e 297 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
0673ad47
CW		 298 if (!value)
299 return -ENODEV;
300 break;
301 case I915_PARAM_EU_TOTAL:
43b67998 302 value = INTEL_INFO(dev_priv)->sseu.eu_total;
0673ad47
CW		 303 if (!value)
304 return -ENODEV;
305 break;
306 case I915_PARAM_HAS_GPU_RESET:
307 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
308 break;
309 case I915_PARAM_HAS_RESOURCE_STREAMER:
16162470 310 value = HAS_RESOURCE_STREAMER(dev_priv);
0673ad47 311 break;
37f501af 312 case I915_PARAM_HAS_POOLED_EU:
16162470 313 value = HAS_POOLED_EU(dev_priv);
37f501af 314 break;
315 case I915_PARAM_MIN_EU_IN_POOL:
43b67998 316 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
37f501af 317 break;
4cc69075
CW		 318 case I915_PARAM_MMAP_GTT_VERSION:
319 /* Though we've started our numbering from 1, and so class all
320 * earlier versions as 0, in effect their value is undefined as
321 * the ioctl will report EINVAL for the unknown param!
322 */
323 value = i915_gem_mmap_gtt_version();
324 break;
0de9136d
CW		 325 case I915_PARAM_HAS_SCHEDULER:
326 value = dev_priv->engine[RCS] &&
327 dev_priv->engine[RCS]->schedule;
328 break;
16162470
DW		 329 case I915_PARAM_MMAP_VERSION:
330 /* Remember to bump this if the version changes! */
331 case I915_PARAM_HAS_GEM:
332 case I915_PARAM_HAS_PAGEFLIPPING:
333 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
334 case I915_PARAM_HAS_RELAXED_FENCING:
335 case I915_PARAM_HAS_COHERENT_RINGS:
336 case I915_PARAM_HAS_RELAXED_DELTA:
337 case I915_PARAM_HAS_GEN7_SOL_RESET:
338 case I915_PARAM_HAS_WAIT_TIMEOUT:
339 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
340 case I915_PARAM_HAS_PINNED_BATCHES:
341 case I915_PARAM_HAS_EXEC_NO_RELOC:
342 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
343 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
344 case I915_PARAM_HAS_EXEC_SOFTPIN:
345 /* For the time being all of these are always true;
346 * if some supported hardware does not have one of these
347 * features this value needs to be provided from
348 * INTEL_INFO(), a feature macro, or similar.
349 */
350 value = 1;
351 break;
0673ad47
CW		 352 default:
353 DRM_DEBUG("Unknown parameter %d\n", param->param);
354 return -EINVAL;
355 }
356
dda33009 357 if (put_user(value, param->value))
0673ad47 358 return -EFAULT;
0673ad47
CW		 359
360 return 0;
361}
362
da5f53bf 363static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
0673ad47 364{
0673ad47
CW		 365 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
366 if (!dev_priv->bridge_dev) {
367 DRM_ERROR("bridge device not found\n");
368 return -1;
369 }
370 return 0;
371}
372
373/* Allocate space for the MCH regs if needed, return nonzero on error */
374static int
da5f53bf 375intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
0673ad47 376{
514e1d64 377 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 378 u32 temp_lo, temp_hi = 0;
379 u64 mchbar_addr;
380 int ret;
381
514e1d64 382 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 383 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
384 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
385 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
386
387 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
388#ifdef CONFIG_PNP
389 if (mchbar_addr &&
390 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
391 return 0;
392#endif
393
394 /* Get some space for it */
395 dev_priv->mch_res.name = "i915 MCHBAR";
396 dev_priv->mch_res.flags = IORESOURCE_MEM;
397 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
398 &dev_priv->mch_res,
399 MCHBAR_SIZE, MCHBAR_SIZE,
400 PCIBIOS_MIN_MEM,
401 0, pcibios_align_resource,
402 dev_priv->bridge_dev);
403 if (ret) {
404 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
405 dev_priv->mch_res.start = 0;
406 return ret;
407 }
408
514e1d64 409 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 410 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
411 upper_32_bits(dev_priv->mch_res.start));
412
413 pci_write_config_dword(dev_priv->bridge_dev, reg,
414 lower_32_bits(dev_priv->mch_res.start));
415 return 0;
416}
417
418/* Setup MCHBAR if possible, return true if we should disable it again */
419static void
da5f53bf 420intel_setup_mchbar(struct drm_i915_private *dev_priv)
0673ad47 421{
514e1d64 422 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 423 u32 temp;
424 bool enabled;
425
920a14b2 426 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0673ad47
CW		 427 return;
428
429 dev_priv->mchbar_need_disable = false;
430
50a0bc90 431 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 432 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
433 enabled = !!(temp & DEVEN_MCHBAR_EN);
434 } else {
435 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
436 enabled = temp & 1;
437 }
438
439 /* If it's already enabled, don't have to do anything */
440 if (enabled)
441 return;
442
da5f53bf 443 if (intel_alloc_mchbar_resource(dev_priv))
0673ad47
CW		 444 return;
445
446 dev_priv->mchbar_need_disable = true;
447
448 /* Space is allocated or reserved, so enable it. */
50a0bc90 449 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 450 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
451 temp | DEVEN_MCHBAR_EN);
452 } else {
453 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
454 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
455 }
456}
457
458static void
da5f53bf 459intel_teardown_mchbar(struct drm_i915_private *dev_priv)
0673ad47 460{
514e1d64 461 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 462
463 if (dev_priv->mchbar_need_disable) {
50a0bc90 464 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 465 u32 deven_val;
466
467 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
468 &deven_val);
469 deven_val &= ~DEVEN_MCHBAR_EN;
470 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
471 deven_val);
472 } else {
473 u32 mchbar_val;
474
475 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
476 &mchbar_val);
477 mchbar_val &= ~1;
478 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
479 mchbar_val);
480 }
481 }
482
483 if (dev_priv->mch_res.start)
484 release_resource(&dev_priv->mch_res);
485}
486
487/* true = enable decode, false = disable decoder */
488static unsigned int i915_vga_set_decode(void *cookie, bool state)
489{
da5f53bf 490 struct drm_i915_private *dev_priv = cookie;
0673ad47 491
da5f53bf 492 intel_modeset_vga_set_state(dev_priv, state);
0673ad47
CW		 493 if (state)
494 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
495 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
496 else
497 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
498}
499
7f26cb88
TU		 500static int i915_resume_switcheroo(struct drm_device *dev);
501static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
502
0673ad47
CW		 503static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
504{
505 struct drm_device *dev = pci_get_drvdata(pdev);
506 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
507
508 if (state == VGA_SWITCHEROO_ON) {
509 pr_info("switched on\n");
510 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
511 /* i915 resume handler doesn't set to D0 */
52a05c30 512 pci_set_power_state(pdev, PCI_D0);
0673ad47
CW		 513 i915_resume_switcheroo(dev);
514 dev->switch_power_state = DRM_SWITCH_POWER_ON;
515 } else {
516 pr_info("switched off\n");
517 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
518 i915_suspend_switcheroo(dev, pmm);
519 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
520 }
521}
522
523static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
524{
525 struct drm_device *dev = pci_get_drvdata(pdev);
526
527 /*
528 * FIXME: open_count is protected by drm_global_mutex but that would lead to
529 * locking inversion with the driver load path. And the access here is
530 * completely racy anyway. So don't bother with locking for now.
531 */
532 return dev->open_count == 0;
533}
534
535static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
536 .set_gpu_state = i915_switcheroo_set_state,
537 .reprobe = NULL,
538 .can_switch = i915_switcheroo_can_switch,
539};
540
fbbd37b3 541static void i915_gem_fini(struct drm_i915_private *dev_priv)
0673ad47 542{
fbbd37b3 543 mutex_lock(&dev_priv->drm.struct_mutex);
cb15d9f8
TU		 544 i915_gem_cleanup_engines(dev_priv);
545 i915_gem_context_fini(dev_priv);
fbbd37b3 546 mutex_unlock(&dev_priv->drm.struct_mutex);
0673ad47 547
bdeb9785 548 i915_gem_drain_freed_objects(dev_priv);
fbbd37b3
CW		 549
550 WARN_ON(!list_empty(&dev_priv->context_list));
0673ad47
CW		 551}
552
553static int i915_load_modeset_init(struct drm_device *dev)
554{
fac5e23e 555 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 556 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 557 int ret;
558
559 if (i915_inject_load_failure())
560 return -ENODEV;
561
562 ret = intel_bios_init(dev_priv);
563 if (ret)
564 DRM_INFO("failed to find VBIOS tables\n");
565
566 /* If we have > 1 VGA cards, then we need to arbitrate access
567 * to the common VGA resources.
568 *
569 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
570 * then we do not take part in VGA arbitration and the
571 * vga_client_register() fails with -ENODEV.
572 */
da5f53bf 573 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
0673ad47
CW		 574 if (ret && ret != -ENODEV)
575 goto out;
576
577 intel_register_dsm_handler();
578
52a05c30 579 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
0673ad47
CW		 580 if (ret)
581 goto cleanup_vga_client;
582
583 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
584 intel_update_rawclk(dev_priv);
585
586 intel_power_domains_init_hw(dev_priv, false);
587
588 intel_csr_ucode_init(dev_priv);
589
590 ret = intel_irq_install(dev_priv);
591 if (ret)
592 goto cleanup_csr;
593
40196446 594 intel_setup_gmbus(dev_priv);
0673ad47
CW		 595
596 /* Important: The output setup functions called by modeset_init need
597 * working irqs for e.g. gmbus and dp aux transfers. */
b079bd17
VS		 598 ret = intel_modeset_init(dev);
599 if (ret)
600 goto cleanup_irq;
0673ad47 601
bd132858 602 intel_huc_init(dev_priv);
bf9e8429 603 intel_guc_init(dev_priv);
0673ad47 604
bf9e8429 605 ret = i915_gem_init(dev_priv);
0673ad47
CW		 606 if (ret)
607 goto cleanup_irq;
608
609 intel_modeset_gem_init(dev);
610
b7f05d4a 611 if (INTEL_INFO(dev_priv)->num_pipes == 0)
0673ad47
CW		 612 return 0;
613
614 ret = intel_fbdev_init(dev);
615 if (ret)
616 goto cleanup_gem;
617
618 /* Only enable hotplug handling once the fbdev is fully set up. */
619 intel_hpd_init(dev_priv);
620
621 drm_kms_helper_poll_init(dev);
622
623 return 0;
624
625cleanup_gem:
bf9e8429 626 if (i915_gem_suspend(dev_priv))
1c777c5d 627 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
fbbd37b3 628 i915_gem_fini(dev_priv);
0673ad47 629cleanup_irq:
bf9e8429 630 intel_guc_fini(dev_priv);
bd132858 631 intel_huc_fini(dev_priv);
0673ad47 632 drm_irq_uninstall(dev);
40196446 633 intel_teardown_gmbus(dev_priv);
0673ad47
CW		 634cleanup_csr:
635 intel_csr_ucode_fini(dev_priv);
636 intel_power_domains_fini(dev_priv);
52a05c30 637 vga_switcheroo_unregister_client(pdev);
0673ad47 638cleanup_vga_client:
52a05c30 639 vga_client_register(pdev, NULL, NULL, NULL);
0673ad47
CW		 640out:
641 return ret;
642}
643
0673ad47
CW		 644static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
645{
646 struct apertures_struct *ap;
91c8a326 647 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 648 struct i915_ggtt *ggtt = &dev_priv->ggtt;
649 bool primary;
650 int ret;
651
652 ap = alloc_apertures(1);
653 if (!ap)
654 return -ENOMEM;
655
656 ap->ranges[0].base = ggtt->mappable_base;
657 ap->ranges[0].size = ggtt->mappable_end;
658
659 primary =
660 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
661
44adece5 662 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
0673ad47
CW		 663
664 kfree(ap);
665
666 return ret;
667}
0673ad47
CW		 668
669#if !defined(CONFIG_VGA_CONSOLE)
670static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
671{
672 return 0;
673}
674#elif !defined(CONFIG_DUMMY_CONSOLE)
675static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
676{
677 return -ENODEV;
678}
679#else
680static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
681{
682 int ret = 0;
683
684 DRM_INFO("Replacing VGA console driver\n");
685
686 console_lock();
687 if (con_is_bound(&vga_con))
688 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
689 if (ret == 0) {
690 ret = do_unregister_con_driver(&vga_con);
691
692 /* Ignore "already unregistered". */
693 if (ret == -ENODEV)
694 ret = 0;
695 }
696 console_unlock();
697
698 return ret;
699}
700#endif
701
0673ad47
CW		 702static void intel_init_dpio(struct drm_i915_private *dev_priv)
703{
704 /*
705 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
706 * CHV x1 PHY (DP/HDMI D)
707 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
708 */
709 if (IS_CHERRYVIEW(dev_priv)) {
710 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
711 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
712 } else if (IS_VALLEYVIEW(dev_priv)) {
713 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
714 }
715}
716
717static int i915_workqueues_init(struct drm_i915_private *dev_priv)
718{
719 /*
720 * The i915 workqueue is primarily used for batched retirement of
721 * requests (and thus managing bo) once the task has been completed
722 * by the GPU. i915_gem_retire_requests() is called directly when we
723 * need high-priority retirement, such as waiting for an explicit
724 * bo.
725 *
726 * It is also used for periodic low-priority events, such as
727 * idle-timers and recording error state.
728 *
729 * All tasks on the workqueue are expected to acquire the dev mutex
730 * so there is no point in running more than one instance of the
731 * workqueue at any time. Use an ordered one.
732 */
733 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
734 if (dev_priv->wq == NULL)
735 goto out_err;
736
737 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
738 if (dev_priv->hotplug.dp_wq == NULL)
739 goto out_free_wq;
740
0673ad47
CW		 741 return 0;
742
0673ad47
CW		 743out_free_wq:
744 destroy_workqueue(dev_priv->wq);
745out_err:
746 DRM_ERROR("Failed to allocate workqueues.\n");
747
748 return -ENOMEM;
749}
750
751static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
752{
0673ad47
CW		 753 destroy_workqueue(dev_priv->hotplug.dp_wq);
754 destroy_workqueue(dev_priv->wq);
755}
756
4fc7e845
PZ		 757/*
758 * We don't keep the workarounds for pre-production hardware, so we expect our
759 * driver to fail on these machines in one way or another. A little warning on
760 * dmesg may help both the user and the bug triagers.
761 */
762static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
763{
764 if (IS_HSW_EARLY_SDV(dev_priv) ||
765 IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
766 DRM_ERROR("This is a pre-production stepping. "
767 "It may not be fully functional.\n");
768}
769
0673ad47
CW		 770/**
771 * i915_driver_init_early - setup state not requiring device access
772 * @dev_priv: device private
773 *
774 * Initialize everything that is a "SW-only" state, that is state not
775 * requiring accessing the device or exposing the driver via kernel internal
776 * or userspace interfaces. Example steps belonging here: lock initialization,
777 * system memory allocation, setting up device specific attributes and
778 * function hooks not requiring accessing the device.
779 */
780static int i915_driver_init_early(struct drm_i915_private *dev_priv,
781 const struct pci_device_id *ent)
782{
783 const struct intel_device_info *match_info =
784 (struct intel_device_info *)ent->driver_data;
785 struct intel_device_info *device_info;
786 int ret = 0;
787
788 if (i915_inject_load_failure())
789 return -ENODEV;
790
791 /* Setup the write-once "constant" device info */
94b4f3ba 792 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 793 memcpy(device_info, match_info, sizeof(*device_info));
794 device_info->device_id = dev_priv->drm.pdev->device;
795
796 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
797 device_info->gen_mask = BIT(device_info->gen - 1);
798
799 spin_lock_init(&dev_priv->irq_lock);
800 spin_lock_init(&dev_priv->gpu_error.lock);
801 mutex_init(&dev_priv->backlight_lock);
802 spin_lock_init(&dev_priv->uncore.lock);
803 spin_lock_init(&dev_priv->mm.object_stat_lock);
804 spin_lock_init(&dev_priv->mmio_flip_lock);
467a14d9 805 spin_lock_init(&dev_priv->wm.dsparb_lock);
0673ad47
CW		 806 mutex_init(&dev_priv->sb_lock);
807 mutex_init(&dev_priv->modeset_restore_lock);
808 mutex_init(&dev_priv->av_mutex);
809 mutex_init(&dev_priv->wm.wm_mutex);
810 mutex_init(&dev_priv->pps_mutex);
811
413e8fdb
AH		 812 intel_uc_init_early(dev_priv);
813
0b1de5d5
CW		 814 i915_memcpy_init_early(dev_priv);
815
0673ad47
CW		 816 ret = i915_workqueues_init(dev_priv);
817 if (ret < 0)
818 return ret;
819
820 ret = intel_gvt_init(dev_priv);
821 if (ret < 0)
822 goto err_workqueues;
823
824 /* This must be called before any calls to HAS_PCH_* */
da5f53bf 825 intel_detect_pch(dev_priv);
0673ad47 826
192aa181 827 intel_pm_setup(dev_priv);
0673ad47
CW		 828 intel_init_dpio(dev_priv);
829 intel_power_domains_init(dev_priv);
830 intel_irq_init(dev_priv);
3ac168a7 831 intel_hangcheck_init(dev_priv);
0673ad47
CW		 832 intel_init_display_hooks(dev_priv);
833 intel_init_clock_gating_hooks(dev_priv);
834 intel_init_audio_hooks(dev_priv);
cb15d9f8 835 ret = i915_gem_load_init(dev_priv);
73cb9701
CW		 836 if (ret < 0)
837 goto err_gvt;
0673ad47 838
36cdd013 839 intel_display_crc_init(dev_priv);
0673ad47 840
94b4f3ba 841 intel_device_info_dump(dev_priv);
0673ad47 842
4fc7e845 843 intel_detect_preproduction_hw(dev_priv);
0673ad47 844
eec688e1
RB		 845 i915_perf_init(dev_priv);
846
0673ad47
CW		 847 return 0;
848
73cb9701
CW		 849err_gvt:
850 intel_gvt_cleanup(dev_priv);
0673ad47
CW		 851err_workqueues:
852 i915_workqueues_cleanup(dev_priv);
853 return ret;
854}
855
856/**
857 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
858 * @dev_priv: device private
859 */
860static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
861{
eec688e1 862 i915_perf_fini(dev_priv);
cb15d9f8 863 i915_gem_load_cleanup(dev_priv);
0673ad47
CW		 864 i915_workqueues_cleanup(dev_priv);
865}
866
da5f53bf 867static int i915_mmio_setup(struct drm_i915_private *dev_priv)
0673ad47 868{
52a05c30 869 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 870 int mmio_bar;
871 int mmio_size;
872
5db94019 873 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
0673ad47
CW		 874 /*
875 * Before gen4, the registers and the GTT are behind different BARs.
876 * However, from gen4 onwards, the registers and the GTT are shared
877 * in the same BAR, so we want to restrict this ioremap from
878 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
879 * the register BAR remains the same size for all the earlier
880 * generations up to Ironlake.
881 */
514e1d64 882 if (INTEL_GEN(dev_priv) < 5)
0673ad47
CW		 883 mmio_size = 512 * 1024;
884 else
885 mmio_size = 2 * 1024 * 1024;
52a05c30 886 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
0673ad47
CW		 887 if (dev_priv->regs == NULL) {
888 DRM_ERROR("failed to map registers\n");
889
890 return -EIO;
891 }
892
893 /* Try to make sure MCHBAR is enabled before poking at it */
da5f53bf 894 intel_setup_mchbar(dev_priv);
0673ad47
CW		 895
896 return 0;
897}
898
da5f53bf 899static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
0673ad47 900{
52a05c30 901 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 902
da5f53bf 903 intel_teardown_mchbar(dev_priv);
52a05c30 904 pci_iounmap(pdev, dev_priv->regs);
0673ad47
CW		 905}
906
907/**
908 * i915_driver_init_mmio - setup device MMIO
909 * @dev_priv: device private
910 *
911 * Setup minimal device state necessary for MMIO accesses later in the
912 * initialization sequence. The setup here should avoid any other device-wide
913 * side effects or exposing the driver via kernel internal or user space
914 * interfaces.
915 */
916static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
917{
0673ad47
CW		 918 int ret;
919
920 if (i915_inject_load_failure())
921 return -ENODEV;
922
da5f53bf 923 if (i915_get_bridge_dev(dev_priv))
0673ad47
CW		 924 return -EIO;
925
da5f53bf 926 ret = i915_mmio_setup(dev_priv);
0673ad47
CW		 927 if (ret < 0)
928 goto put_bridge;
929
930 intel_uncore_init(dev_priv);
931
932 return 0;
933
934put_bridge:
935 pci_dev_put(dev_priv->bridge_dev);
936
937 return ret;
938}
939
940/**
941 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
942 * @dev_priv: device private
943 */
944static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
945{
0673ad47 946 intel_uncore_fini(dev_priv);
da5f53bf 947 i915_mmio_cleanup(dev_priv);
0673ad47
CW		 948 pci_dev_put(dev_priv->bridge_dev);
949}
950
94b4f3ba
CW		 951static void intel_sanitize_options(struct drm_i915_private *dev_priv)
952{
953 i915.enable_execlists =
954 intel_sanitize_enable_execlists(dev_priv,
955 i915.enable_execlists);
956
957 /*
958 * i915.enable_ppgtt is read-only, so do an early pass to validate the
959 * user's requested state against the hardware/driver capabilities. We
960 * do this now so that we can print out any log messages once rather
961 * than every time we check intel_enable_ppgtt().
962 */
963 i915.enable_ppgtt =
964 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
965 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
39df9190
CW		 966
967 i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
968 DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
94b4f3ba
CW		 969}
970
0673ad47
CW		 971/**
972 * i915_driver_init_hw - setup state requiring device access
973 * @dev_priv: device private
974 *
975 * Setup state that requires accessing the device, but doesn't require
976 * exposing the driver via kernel internal or userspace interfaces.
977 */
978static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
979{
52a05c30 980 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 981 int ret;
982
983 if (i915_inject_load_failure())
984 return -ENODEV;
985
94b4f3ba
CW		 986 intel_device_info_runtime_init(dev_priv);
987
988 intel_sanitize_options(dev_priv);
0673ad47 989
97d6d7ab 990 ret = i915_ggtt_probe_hw(dev_priv);
0673ad47
CW		 991 if (ret)
992 return ret;
993
0673ad47
CW		 994 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
995 * otherwise the vga fbdev driver falls over. */
996 ret = i915_kick_out_firmware_fb(dev_priv);
997 if (ret) {
998 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
999 goto out_ggtt;
1000 }
1001
1002 ret = i915_kick_out_vgacon(dev_priv);
1003 if (ret) {
1004 DRM_ERROR("failed to remove conflicting VGA console\n");
1005 goto out_ggtt;
1006 }
1007
97d6d7ab 1008 ret = i915_ggtt_init_hw(dev_priv);
0088e522
CW		 1009 if (ret)
1010 return ret;
1011
97d6d7ab 1012 ret = i915_ggtt_enable_hw(dev_priv);
0088e522
CW		 1013 if (ret) {
1014 DRM_ERROR("failed to enable GGTT\n");
1015 goto out_ggtt;
1016 }
1017
52a05c30 1018 pci_set_master(pdev);
0673ad47
CW		 1019
1020 /* overlay on gen2 is broken and can't address above 1G */
5db94019 1021 if (IS_GEN2(dev_priv)) {
52a05c30 1022 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
0673ad47
CW		 1023 if (ret) {
1024 DRM_ERROR("failed to set DMA mask\n");
1025
1026 goto out_ggtt;
1027 }
1028 }
1029
0673ad47
CW		 1030 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1031 * using 32bit addressing, overwriting memory if HWS is located
1032 * above 4GB.
1033 *
1034 * The documentation also mentions an issue with undefined
1035 * behaviour if any general state is accessed within a page above 4GB,
1036 * which also needs to be handled carefully.
1037 */
c0f86832 1038 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
52a05c30 1039 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0673ad47
CW		 1040
1041 if (ret) {
1042 DRM_ERROR("failed to set DMA mask\n");
1043
1044 goto out_ggtt;
1045 }
1046 }
1047
0673ad47
CW		 1048 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1049 PM_QOS_DEFAULT_VALUE);
1050
1051 intel_uncore_sanitize(dev_priv);
1052
1053 intel_opregion_setup(dev_priv);
1054
1055 i915_gem_load_init_fences(dev_priv);
1056
1057 /* On the 945G/GM, the chipset reports the MSI capability on the
1058 * integrated graphics even though the support isn't actually there
1059 * according to the published specs. It doesn't appear to function
1060 * correctly in testing on 945G.
1061 * This may be a side effect of MSI having been made available for PEG
1062 * and the registers being closely associated.
1063 *
1064 * According to chipset errata, on the 965GM, MSI interrupts may
1065 * be lost or delayed, but we use them anyways to avoid
1066 * stuck interrupts on some machines.
1067 */
50a0bc90 1068 if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
52a05c30 1069 if (pci_enable_msi(pdev) < 0)
0673ad47
CW		 1070 DRM_DEBUG_DRIVER("can't enable MSI");
1071 }
1072
1073 return 0;
1074
1075out_ggtt:
97d6d7ab 1076 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1077
1078 return ret;
1079}
1080
1081/**
1082 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1083 * @dev_priv: device private
1084 */
1085static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1086{
52a05c30 1087 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 1088
52a05c30
DW		 1089 if (pdev->msi_enabled)
1090 pci_disable_msi(pdev);
0673ad47
CW		 1091
1092 pm_qos_remove_request(&dev_priv->pm_qos);
97d6d7ab 1093 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1094}
1095
1096/**
1097 * i915_driver_register - register the driver with the rest of the system
1098 * @dev_priv: device private
1099 *
1100 * Perform any steps necessary to make the driver available via kernel
1101 * internal or userspace interfaces.
1102 */
1103static void i915_driver_register(struct drm_i915_private *dev_priv)
1104{
91c8a326 1105 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1106
1107 i915_gem_shrinker_init(dev_priv);
1108
1109 /*
1110 * Notify a valid surface after modesetting,
1111 * when running inside a VM.
1112 */
1113 if (intel_vgpu_active(dev_priv))
1114 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1115
1116 /* Reveal our presence to userspace */
1117 if (drm_dev_register(dev, 0) == 0) {
1118 i915_debugfs_register(dev_priv);
f9cda048 1119 i915_guc_log_register(dev_priv);
694c2828 1120 i915_setup_sysfs(dev_priv);
442b8c06
RB		 1121
1122 /* Depends on sysfs having been initialized */
1123 i915_perf_register(dev_priv);
0673ad47
CW		 1124 } else
1125 DRM_ERROR("Failed to register driver for userspace access!\n");
1126
1127 if (INTEL_INFO(dev_priv)->num_pipes) {
1128 /* Must be done after probing outputs */
1129 intel_opregion_register(dev_priv);
1130 acpi_video_register();
1131 }
1132
1133 if (IS_GEN5(dev_priv))
1134 intel_gpu_ips_init(dev_priv);
1135
1136 i915_audio_component_init(dev_priv);
1137
1138 /*
1139 * Some ports require correctly set-up hpd registers for detection to
1140 * work properly (leading to ghost connected connector status), e.g. VGA
1141 * on gm45. Hence we can only set up the initial fbdev config after hpd
1142 * irqs are fully enabled. We do it last so that the async config
1143 * cannot run before the connectors are registered.
1144 */
1145 intel_fbdev_initial_config_async(dev);
1146}
1147
1148/**
1149 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1150 * @dev_priv: device private
1151 */
1152static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1153{
1154 i915_audio_component_cleanup(dev_priv);
1155
1156 intel_gpu_ips_teardown();
1157 acpi_video_unregister();
1158 intel_opregion_unregister(dev_priv);
1159
442b8c06
RB		 1160 i915_perf_unregister(dev_priv);
1161
694c2828 1162 i915_teardown_sysfs(dev_priv);
f9cda048 1163 i915_guc_log_unregister(dev_priv);
0673ad47 1164 i915_debugfs_unregister(dev_priv);
91c8a326 1165 drm_dev_unregister(&dev_priv->drm);
0673ad47
CW		 1166
1167 i915_gem_shrinker_cleanup(dev_priv);
1168}
1169
1170/**
1171 * i915_driver_load - setup chip and create an initial config
d2ad3ae4
JL		 1172 * @pdev: PCI device
1173 * @ent: matching PCI ID entry
0673ad47
CW		 1174 *
1175 * The driver load routine has to do several things:
1176 * - drive output discovery via intel_modeset_init()
1177 * - initialize the memory manager
1178 * - allocate initial config memory
1179 * - setup the DRM framebuffer with the allocated memory
1180 */
42f5551d 1181int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47
CW		 1182{
1183 struct drm_i915_private *dev_priv;
1184 int ret;
7d87a7f7 1185
a09d0ba1
CW		 1186 if (i915.nuclear_pageflip)
1187 driver.driver_features |= DRIVER_ATOMIC;
1188
0673ad47
CW		 1189 ret = -ENOMEM;
1190 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1191 if (dev_priv)
1192 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1193 if (ret) {
87a6752c 1194 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
0673ad47
CW		 1195 kfree(dev_priv);
1196 return ret;
1197 }
72bbf0af 1198
0673ad47
CW		 1199 dev_priv->drm.pdev = pdev;
1200 dev_priv->drm.dev_private = dev_priv;
719388e1 1201
0673ad47
CW		 1202 ret = pci_enable_device(pdev);
1203 if (ret)
1204 goto out_free_priv;
1347f5b4 1205
0673ad47 1206 pci_set_drvdata(pdev, &dev_priv->drm);
ef11bdb3 1207
0673ad47
CW		 1208 ret = i915_driver_init_early(dev_priv, ent);
1209 if (ret < 0)
1210 goto out_pci_disable;
ef11bdb3 1211
0673ad47 1212 intel_runtime_pm_get(dev_priv);
1da177e4 1213
0673ad47
CW		 1214 ret = i915_driver_init_mmio(dev_priv);
1215 if (ret < 0)
1216 goto out_runtime_pm_put;
79e53945 1217
0673ad47
CW		 1218 ret = i915_driver_init_hw(dev_priv);
1219 if (ret < 0)
1220 goto out_cleanup_mmio;
30c964a6
RB		 1221
1222 /*
0673ad47
CW		 1223 * TODO: move the vblank init and parts of modeset init steps into one
1224 * of the i915_driver_init_/i915_driver_register functions according
1225 * to the role/effect of the given init step.
30c964a6 1226 */
0673ad47 1227 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1228 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1229 INTEL_INFO(dev_priv)->num_pipes);
1230 if (ret)
1231 goto out_cleanup_hw;
30c964a6
RB		 1232 }
1233
91c8a326 1234 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47
CW		 1235 if (ret < 0)
1236 goto out_cleanup_vblank;
1237
1238 i915_driver_register(dev_priv);
1239
1240 intel_runtime_pm_enable(dev_priv);
1241
a3a8986c
MK		 1242 dev_priv->ipc_enabled = false;
1243
bc5ca47c
CW		 1244 /* Everything is in place, we can now relax! */
1245 DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1246 driver.name, driver.major, driver.minor, driver.patchlevel,
1247 driver.date, pci_name(pdev), dev_priv->drm.primary->index);
0525a062
CW		 1248 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1249 DRM_INFO("DRM_I915_DEBUG enabled\n");
1250 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1251 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
bc5ca47c 1252
0673ad47
CW		 1253 intel_runtime_pm_put(dev_priv);
1254
1255 return 0;
1256
1257out_cleanup_vblank:
91c8a326 1258 drm_vblank_cleanup(&dev_priv->drm);
0673ad47
CW		 1259out_cleanup_hw:
1260 i915_driver_cleanup_hw(dev_priv);
1261out_cleanup_mmio:
1262 i915_driver_cleanup_mmio(dev_priv);
1263out_runtime_pm_put:
1264 intel_runtime_pm_put(dev_priv);
1265 i915_driver_cleanup_early(dev_priv);
1266out_pci_disable:
1267 pci_disable_device(pdev);
1268out_free_priv:
1269 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1270 drm_dev_unref(&dev_priv->drm);
30c964a6
RB		 1271 return ret;
1272}
1273
42f5551d 1274void i915_driver_unload(struct drm_device *dev)
3bad0781 1275{
fac5e23e 1276 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1277 struct pci_dev *pdev = dev_priv->drm.pdev;
3bad0781 1278
0673ad47
CW		 1279 intel_fbdev_fini(dev);
1280
bf9e8429 1281 if (i915_gem_suspend(dev_priv))
42f5551d 1282 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1283
0673ad47
CW		 1284 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1285
1286 i915_driver_unregister(dev_priv);
1287
1288 drm_vblank_cleanup(dev);
1289
1290 intel_modeset_cleanup(dev);
1291
3bad0781 1292 /*
0673ad47
CW		 1293 * free the memory space allocated for the child device
1294 * config parsed from VBT
3bad0781 1295 */
0673ad47
CW		 1296 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1297 kfree(dev_priv->vbt.child_dev);
1298 dev_priv->vbt.child_dev = NULL;
1299 dev_priv->vbt.child_dev_num = 0;
1300 }
1301 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1302 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1303 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1304 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1305
52a05c30
DW		 1306 vga_switcheroo_unregister_client(pdev);
1307 vga_client_register(pdev, NULL, NULL, NULL);
bcdb72ac 1308
0673ad47 1309 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1310
0673ad47
CW		 1311 /* Free error state after interrupts are fully disabled. */
1312 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
12ff05e7 1313 i915_destroy_error_state(dev_priv);
0673ad47
CW		 1314
1315 /* Flush any outstanding unpin_work. */
b7137e0c 1316 drain_workqueue(dev_priv->wq);
0673ad47 1317
bf9e8429 1318 intel_guc_fini(dev_priv);
bd132858 1319 intel_huc_fini(dev_priv);
fbbd37b3 1320 i915_gem_fini(dev_priv);
0673ad47
CW		 1321 intel_fbc_cleanup_cfb(dev_priv);
1322
1323 intel_power_domains_fini(dev_priv);
1324
1325 i915_driver_cleanup_hw(dev_priv);
1326 i915_driver_cleanup_mmio(dev_priv);
1327
1328 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1329
1330 i915_driver_cleanup_early(dev_priv);
3bad0781
ZW		 1331}
1332
0673ad47 1333static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1334{
0673ad47 1335 int ret;
2911a35b 1336
0673ad47
CW		 1337 ret = i915_gem_open(dev, file);
1338 if (ret)
1339 return ret;
2911a35b 1340
0673ad47
CW		 1341 return 0;
1342}
71386ef9 1343
0673ad47
CW		 1344/**
1345 * i915_driver_lastclose - clean up after all DRM clients have exited
1346 * @dev: DRM device
1347 *
1348 * Take care of cleaning up after all DRM clients have exited. In the
1349 * mode setting case, we want to restore the kernel's initial mode (just
1350 * in case the last client left us in a bad state).
1351 *
1352 * Additionally, in the non-mode setting case, we'll tear down the GTT
1353 * and DMA structures, since the kernel won't be using them, and clea
1354 * up any GEM state.
1355 */
1356static void i915_driver_lastclose(struct drm_device *dev)
1357{
1358 intel_fbdev_restore_mode(dev);
1359 vga_switcheroo_process_delayed_switch();
1360}
2911a35b 1361
0673ad47
CW		 1362static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1363{
1364 mutex_lock(&dev->struct_mutex);
1365 i915_gem_context_close(dev, file);
1366 i915_gem_release(dev, file);
1367 mutex_unlock(&dev->struct_mutex);
1368}
1369
1370static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1371{
1372 struct drm_i915_file_private *file_priv = file->driver_priv;
1373
1374 kfree(file_priv);
2911a35b
BW		 1375}
1376
07f9cd0b
ID		 1377static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1378{
91c8a326 1379 struct drm_device *dev = &dev_priv->drm;
19c8054c 1380 struct intel_encoder *encoder;
07f9cd0b
ID		 1381
1382 drm_modeset_lock_all(dev);
19c8054c
JN		 1383 for_each_intel_encoder(dev, encoder)
1384 if (encoder->suspend)
1385 encoder->suspend(encoder);
07f9cd0b
ID		 1386 drm_modeset_unlock_all(dev);
1387}
1388
1a5df187
PZ		 1389static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1390 bool rpm_resume);
507e126e 1391static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1392
bc87229f
ID		 1393static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1394{
1395#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1396 if (acpi_target_system_state() < ACPI_STATE_S3)
1397 return true;
1398#endif
1399 return false;
1400}
ebc32824 1401
5e365c39 1402static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1403{
fac5e23e 1404 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1405 struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3a 1406 pci_power_t opregion_target_state;
d5818938 1407 int error;
61caf87c 1408
b8efb17b
ZR		 1409 /* ignore lid events during suspend */
1410 mutex_lock(&dev_priv->modeset_restore_lock);
1411 dev_priv->modeset_restore = MODESET_SUSPENDED;
1412 mutex_unlock(&dev_priv->modeset_restore_lock);
1413
1f814dac
ID		 1414 disable_rpm_wakeref_asserts(dev_priv);
1415
c67a470b
PZ		 1416 /* We do a lot of poking in a lot of registers, make sure they work
1417 * properly. */
da7e29bd 1418 intel_display_set_init_power(dev_priv, true);
cb10799c 1419
5bcf719b
DA		 1420 drm_kms_helper_poll_disable(dev);
1421
52a05c30 1422 pci_save_state(pdev);
ba8bbcf6 1423
bf9e8429 1424 error = i915_gem_suspend(dev_priv);
d5818938 1425 if (error) {
52a05c30 1426 dev_err(&pdev->dev,
d5818938 1427 "GEM idle failed, resume might fail\n");
1f814dac 1428 goto out;
d5818938 1429 }
db1b76ca 1430
bf9e8429 1431 intel_guc_suspend(dev_priv);
a1c41994 1432
6b72d486 1433 intel_display_suspend(dev);
2eb5252e 1434
d5818938 1435 intel_dp_mst_suspend(dev);
7d708ee4 1436
d5818938
DV		 1437 intel_runtime_pm_disable_interrupts(dev_priv);
1438 intel_hpd_cancel_work(dev_priv);
09b64267 1439
d5818938 1440 intel_suspend_encoders(dev_priv);
0e32b39c 1441
712bf364 1442 intel_suspend_hw(dev_priv);
5669fcac 1443
275a991c 1444 i915_gem_suspend_gtt_mappings(dev_priv);
828c7908 1445
af6dc742 1446 i915_save_state(dev_priv);
9e06dd39 1447
bc87229f 1448 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1449 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1450
dc97997a 1451 intel_uncore_forcewake_reset(dev_priv, false);
03d92e47 1452 intel_opregion_unregister(dev_priv);
8ee1c3db 1453
82e3b8c1 1454 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1455
62d5d69b
MK		 1456 dev_priv->suspend_count++;
1457
f74ed08d 1458 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1459
1f814dac
ID		 1460out:
1461 enable_rpm_wakeref_asserts(dev_priv);
1462
1463 return error;
84b79f8d
RW		 1464}
1465
c49d13ee 1466static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
c3c09c95 1467{
c49d13ee 1468 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1469 struct pci_dev *pdev = dev_priv->drm.pdev;
bc87229f 1470 bool fw_csr;
c3c09c95
ID		 1471 int ret;
1472
1f814dac
ID		 1473 disable_rpm_wakeref_asserts(dev_priv);
1474
4c494a57
ID		 1475 intel_display_set_init_power(dev_priv, false);
1476
b9fd799e 1477 fw_csr = !IS_GEN9_LP(dev_priv) &&
a7c8125f 1478 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1479 /*
1480 * In case of firmware assisted context save/restore don't manually
1481 * deinit the power domains. This also means the CSR/DMC firmware will
1482 * stay active, it will power down any HW resources as required and
1483 * also enable deeper system power states that would be blocked if the
1484 * firmware was inactive.
1485 */
1486 if (!fw_csr)
1487 intel_power_domains_suspend(dev_priv);
73dfc227 1488
507e126e 1489 ret = 0;
b9fd799e 1490 if (IS_GEN9_LP(dev_priv))
507e126e 1491 bxt_enable_dc9(dev_priv);
b8aea3d1 1492 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1493 hsw_enable_pc8(dev_priv);
1494 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1495 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1496
1497 if (ret) {
1498 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1499 if (!fw_csr)
1500 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1501
1f814dac 1502 goto out;
c3c09c95
ID		 1503 }
1504
52a05c30 1505 pci_disable_device(pdev);
ab3be73f 1506 /*
54875571 1507 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1508 * the device even though it's already in D3 and hang the machine. So
1509 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1510 * power down the device properly. The issue was seen on multiple old
1511 * GENs with different BIOS vendors, so having an explicit blacklist
1512 * is inpractical; apply the workaround on everything pre GEN6. The
1513 * platforms where the issue was seen:
1514 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1515 * Fujitsu FSC S7110
1516 * Acer Aspire 1830T
ab3be73f 1517 */
514e1d64 1518 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
52a05c30 1519 pci_set_power_state(pdev, PCI_D3hot);
c3c09c95 1520
bc87229f
ID		 1521 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1522
1f814dac
ID		 1523out:
1524 enable_rpm_wakeref_asserts(dev_priv);
1525
1526 return ret;
c3c09c95
ID		 1527}
1528
a9a251c2 1529static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1530{
1531 int error;
1532
ded8b07d 1533 if (!dev) {
84b79f8d
RW		 1534 DRM_ERROR("dev: %p\n", dev);
1535 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1536 return -ENODEV;
1537 }
1538
0b14cbd2
ID		 1539 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1540 state.event != PM_EVENT_FREEZE))
1541 return -EINVAL;
5bcf719b
DA		 1542
1543 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1544 return 0;
6eecba33 1545
5e365c39 1546 error = i915_drm_suspend(dev);
84b79f8d
RW		 1547 if (error)
1548 return error;
1549
ab3be73f 1550 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1551}
1552
5e365c39 1553static int i915_drm_resume(struct drm_device *dev)
76c4b250 1554{
fac5e23e 1555 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1556 int ret;
9d49c0ef 1557
1f814dac 1558 disable_rpm_wakeref_asserts(dev_priv);
abc80abd 1559 intel_sanitize_gt_powersave(dev_priv);
1f814dac 1560
97d6d7ab 1561 ret = i915_ggtt_enable_hw(dev_priv);
ac840ae5
VS		 1562 if (ret)
1563 DRM_ERROR("failed to re-enable GGTT\n");
1564
f74ed08d
ID		 1565 intel_csr_ucode_resume(dev_priv);
1566
bf9e8429 1567 i915_gem_resume(dev_priv);
9d49c0ef 1568
af6dc742 1569 i915_restore_state(dev_priv);
8090ba8c 1570 intel_pps_unlock_regs_wa(dev_priv);
6f9f4b7a 1571 intel_opregion_setup(dev_priv);
61caf87c 1572
c39055b0 1573 intel_init_pch_refclk(dev_priv);
1833b134 1574
364aece0
PA		 1575 /*
1576 * Interrupts have to be enabled before any batches are run. If not the
1577 * GPU will hang. i915_gem_init_hw() will initiate batches to
1578 * update/restore the context.
1579 *
908764f6
ID		 1580 * drm_mode_config_reset() needs AUX interrupts.
1581 *
364aece0
PA		 1582 * Modeset enabling in intel_modeset_init_hw() also needs working
1583 * interrupts.
1584 */
1585 intel_runtime_pm_enable_interrupts(dev_priv);
1586
908764f6
ID		 1587 drm_mode_config_reset(dev);
1588
d5818938 1589 mutex_lock(&dev->struct_mutex);
bf9e8429 1590 if (i915_gem_init_hw(dev_priv)) {
d5818938 1591 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
821ed7df 1592 i915_gem_set_wedged(dev_priv);
d5818938
DV		 1593 }
1594 mutex_unlock(&dev->struct_mutex);
226485e9 1595
bf9e8429 1596 intel_guc_resume(dev_priv);
a1c41994 1597
d5818938 1598 intel_modeset_init_hw(dev);
24576d23 1599
d5818938
DV		 1600 spin_lock_irq(&dev_priv->irq_lock);
1601 if (dev_priv->display.hpd_irq_setup)
91d14251 1602 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1603 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1604
d5818938 1605 intel_dp_mst_resume(dev);
e7d6f7d7 1606
a16b7658
L		 1607 intel_display_resume(dev);
1608
e0b70061
L		 1609 drm_kms_helper_poll_enable(dev);
1610
d5818938
DV		 1611 /*
1612 * ... but also need to make sure that hotplug processing
1613 * doesn't cause havoc. Like in the driver load code we don't
1614 * bother with the tiny race here where we might loose hotplug
1615 * notifications.
1616 * */
1617 intel_hpd_init(dev_priv);
1daed3fb 1618
03d92e47 1619 intel_opregion_register(dev_priv);
44834a67 1620
82e3b8c1 1621 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1622
b8efb17b
ZR		 1623 mutex_lock(&dev_priv->modeset_restore_lock);
1624 dev_priv->modeset_restore = MODESET_DONE;
1625 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1626
6f9f4b7a 1627 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1628
54b4f68f 1629 intel_autoenable_gt_powersave(dev_priv);
ee6f280e 1630
1f814dac
ID		 1631 enable_rpm_wakeref_asserts(dev_priv);
1632
074c6ada 1633 return 0;
84b79f8d
RW		 1634}
1635
5e365c39 1636static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1637{
fac5e23e 1638 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1639 struct pci_dev *pdev = dev_priv->drm.pdev;
44410cd0 1640 int ret;
36d61e67 1641
76c4b250
ID		 1642 /*
1643 * We have a resume ordering issue with the snd-hda driver also
1644 * requiring our device to be power up. Due to the lack of a
1645 * parent/child relationship we currently solve this with an early
1646 * resume hook.
1647 *
1648 * FIXME: This should be solved with a special hdmi sink device or
1649 * similar so that power domains can be employed.
1650 */
44410cd0
ID		 1651
1652 /*
1653 * Note that we need to set the power state explicitly, since we
1654 * powered off the device during freeze and the PCI core won't power
1655 * it back up for us during thaw. Powering off the device during
1656 * freeze is not a hard requirement though, and during the
1657 * suspend/resume phases the PCI core makes sure we get here with the
1658 * device powered on. So in case we change our freeze logic and keep
1659 * the device powered we can also remove the following set power state
1660 * call.
1661 */
52a05c30 1662 ret = pci_set_power_state(pdev, PCI_D0);
44410cd0
ID		 1663 if (ret) {
1664 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1665 goto out;
1666 }
1667
1668 /*
1669 * Note that pci_enable_device() first enables any parent bridge
1670 * device and only then sets the power state for this device. The
1671 * bridge enabling is a nop though, since bridge devices are resumed
1672 * first. The order of enabling power and enabling the device is
1673 * imposed by the PCI core as described above, so here we preserve the
1674 * same order for the freeze/thaw phases.
1675 *
1676 * TODO: eventually we should remove pci_disable_device() /
1677 * pci_enable_enable_device() from suspend/resume. Due to how they
1678 * depend on the device enable refcount we can't anyway depend on them
1679 * disabling/enabling the device.
1680 */
52a05c30 1681 if (pci_enable_device(pdev)) {
bc87229f
ID		 1682 ret = -EIO;
1683 goto out;
1684 }
84b79f8d 1685
52a05c30 1686 pci_set_master(pdev);
84b79f8d 1687
1f814dac
ID		 1688 disable_rpm_wakeref_asserts(dev_priv);
1689
666a4537 1690 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1691 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1692 if (ret)
ff0b187f
DL		 1693 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1694 ret);
36d61e67 1695
dc97997a 1696 intel_uncore_early_sanitize(dev_priv, true);
efee833a 1697
b9fd799e 1698 if (IS_GEN9_LP(dev_priv)) {
da2f41d1
ID		 1699 if (!dev_priv->suspended_to_idle)
1700 gen9_sanitize_dc_state(dev_priv);
507e126e 1701 bxt_disable_dc9(dev_priv);
da2f41d1 1702 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1703 hsw_disable_pc8(dev_priv);
da2f41d1 1704 }
efee833a 1705
dc97997a 1706 intel_uncore_sanitize(dev_priv);
bc87229f 1707
b9fd799e 1708 if (IS_GEN9_LP(dev_priv) ||
a7c8125f 1709 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 1710 intel_power_domains_init_hw(dev_priv, true);
1711
6e35e8ab
ID		 1712 enable_rpm_wakeref_asserts(dev_priv);
1713
bc87229f
ID		 1714out:
1715 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1716
1717 return ret;
76c4b250
ID		 1718}
1719
7f26cb88 1720static int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1721{
50a0072f 1722 int ret;
76c4b250 1723
097dd837
ID		 1724 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1725 return 0;
1726
5e365c39 1727 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1728 if (ret)
1729 return ret;
1730
5a17514e
ID		 1731 return i915_drm_resume(dev);
1732}
1733
11ed50ec 1734/**
f3953dcb 1735 * i915_reset - reset chip after a hang
df210574 1736 * @dev_priv: device private to reset
11ed50ec 1737 *
780f262a
CW		 1738 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1739 * on failure.
11ed50ec 1740 *
221fe799
CW		 1741 * Caller must hold the struct_mutex.
1742 *
11ed50ec
BG		 1743 * Procedure is fairly simple:
1744 * - reset the chip using the reset reg
1745 * - re-init context state
1746 * - re-init hardware status page
1747 * - re-init ring buffer
1748 * - re-init interrupt state
1749 * - re-init display
1750 */
780f262a 1751void i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 1752{
d98c52cf 1753 struct i915_gpu_error *error = &dev_priv->gpu_error;
0573ed4a 1754 int ret;
11ed50ec 1755
bf9e8429 1756 lockdep_assert_held(&dev_priv->drm.struct_mutex);
221fe799
CW		 1757
1758 if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
780f262a 1759 return;
11ed50ec 1760
d98c52cf 1761 /* Clear any previous failed attempts at recovery. Time to try again. */
8af29b0c
CW		 1762 __clear_bit(I915_WEDGED, &error->flags);
1763 error->reset_count++;
d98c52cf 1764
7b4d3a16 1765 pr_notice("drm/i915: Resetting chip after gpu hang\n");
4c965543 1766 disable_irq(dev_priv->drm.irq);
0e178aef
CW		 1767 ret = i915_gem_reset_prepare(dev_priv);
1768 if (ret) {
1769 DRM_ERROR("GPU recovery failed\n");
1770 intel_gpu_reset(dev_priv, ALL_ENGINES);
1771 goto error;
1772 }
9e60ab03 1773
dc97997a 1774 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
0573ed4a 1775 if (ret) {
804e59a8
CW		 1776 if (ret != -ENODEV)
1777 DRM_ERROR("Failed to reset chip: %i\n", ret);
1778 else
1779 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 1780 goto error;
11ed50ec
BG		 1781 }
1782
b1ed35d9 1783 i915_gem_reset_finish(dev_priv);
1362b776
VS		 1784 intel_overlay_reset(dev_priv);
1785
11ed50ec
BG		 1786 /* Ok, now get things going again... */
1787
1788 /*
1789 * Everything depends on having the GTT running, so we need to start
1790 * there. Fortunately we don't need to do this unless we reset the
1791 * chip at a PCI level.
1792 *
1793 * Next we need to restore the context, but we don't use those
1794 * yet either...
1795 *
1796 * Ring buffer needs to be re-initialized in the KMS case, or if X
1797 * was running at the time of the reset (i.e. we weren't VT
1798 * switched away).
1799 */
bf9e8429 1800 ret = i915_gem_init_hw(dev_priv);
33d30a9c
DV		 1801 if (ret) {
1802 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1803 goto error;
11ed50ec
BG		 1804 }
1805
c2a126a4
CW		 1806 i915_queue_hangcheck(dev_priv);
1807
780f262a 1808wakeup:
4c965543 1809 enable_irq(dev_priv->drm.irq);
780f262a
CW		 1810 wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1811 return;
d98c52cf
CW		 1812
1813error:
821ed7df 1814 i915_gem_set_wedged(dev_priv);
780f262a 1815 goto wakeup;
11ed50ec
BG		 1816}
1817
c49d13ee 1818static int i915_pm_suspend(struct device *kdev)
112b715e 1819{
c49d13ee
DW		 1820 struct pci_dev *pdev = to_pci_dev(kdev);
1821 struct drm_device *dev = pci_get_drvdata(pdev);
112b715e 1822
c49d13ee
DW		 1823 if (!dev) {
1824 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
84b79f8d
RW		 1825 return -ENODEV;
1826 }
112b715e 1827
c49d13ee 1828 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
5bcf719b
DA		 1829 return 0;
1830
c49d13ee 1831 return i915_drm_suspend(dev);
76c4b250
ID		 1832}
1833
c49d13ee 1834static int i915_pm_suspend_late(struct device *kdev)
76c4b250 1835{
c49d13ee 1836 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250
ID		 1837
1838 /*
c965d995 1839 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 1840 * requiring our device to be power up. Due to the lack of a
1841 * parent/child relationship we currently solve this with an late
1842 * suspend hook.
1843 *
1844 * FIXME: This should be solved with a special hdmi sink device or
1845 * similar so that power domains can be employed.
1846 */
c49d13ee 1847 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
76c4b250 1848 return 0;
112b715e 1849
c49d13ee 1850 return i915_drm_suspend_late(dev, false);
ab3be73f
ID		 1851}
1852
c49d13ee 1853static int i915_pm_poweroff_late(struct device *kdev)
ab3be73f 1854{
c49d13ee 1855 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
ab3be73f 1856
c49d13ee 1857 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
ab3be73f
ID		 1858 return 0;
1859
c49d13ee 1860 return i915_drm_suspend_late(dev, true);
cbda12d7
ZW		 1861}
1862
c49d13ee 1863static int i915_pm_resume_early(struct device *kdev)
76c4b250 1864{
c49d13ee 1865 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250 1866
c49d13ee 1867 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1868 return 0;
1869
c49d13ee 1870 return i915_drm_resume_early(dev);
76c4b250
ID		 1871}
1872
c49d13ee 1873static int i915_pm_resume(struct device *kdev)
cbda12d7 1874{
c49d13ee 1875 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
84b79f8d 1876
c49d13ee 1877 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1878 return 0;
1879
c49d13ee 1880 return i915_drm_resume(dev);
cbda12d7
ZW		 1881}
1882
1f19ac2a 1883/* freeze: before creating the hibernation_image */
c49d13ee 1884static int i915_pm_freeze(struct device *kdev)
1f19ac2a 1885{
6a800eab
CW		 1886 int ret;
1887
1888 ret = i915_pm_suspend(kdev);
1889 if (ret)
1890 return ret;
1891
1892 ret = i915_gem_freeze(kdev_to_i915(kdev));
1893 if (ret)
1894 return ret;
1895
1896 return 0;
1f19ac2a
CW		 1897}
1898
c49d13ee 1899static int i915_pm_freeze_late(struct device *kdev)
1f19ac2a 1900{
461fb99c
CW		 1901 int ret;
1902
c49d13ee 1903 ret = i915_pm_suspend_late(kdev);
461fb99c
CW		 1904 if (ret)
1905 return ret;
1906
c49d13ee 1907 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
461fb99c
CW		 1908 if (ret)
1909 return ret;
1910
1911 return 0;
1f19ac2a
CW		 1912}
1913
1914/* thaw: called after creating the hibernation image, but before turning off. */
c49d13ee 1915static int i915_pm_thaw_early(struct device *kdev)
1f19ac2a 1916{
c49d13ee 1917 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1918}
1919
c49d13ee 1920static int i915_pm_thaw(struct device *kdev)
1f19ac2a 1921{
c49d13ee 1922 return i915_pm_resume(kdev);
1f19ac2a
CW		 1923}
1924
1925/* restore: called after loading the hibernation image. */
c49d13ee 1926static int i915_pm_restore_early(struct device *kdev)
1f19ac2a 1927{
c49d13ee 1928 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1929}
1930
c49d13ee 1931static int i915_pm_restore(struct device *kdev)
1f19ac2a 1932{
c49d13ee 1933 return i915_pm_resume(kdev);
1f19ac2a
CW		 1934}
1935
ddeea5b0
ID		 1936/*
1937 * Save all Gunit registers that may be lost after a D3 and a subsequent
1938 * S0i[R123] transition. The list of registers needing a save/restore is
1939 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1940 * registers in the following way:
1941 * - Driver: saved/restored by the driver
1942 * - Punit : saved/restored by the Punit firmware
1943 * - No, w/o marking: no need to save/restore, since the register is R/O or
1944 * used internally by the HW in a way that doesn't depend
1945 * keeping the content across a suspend/resume.
1946 * - Debug : used for debugging
1947 *
1948 * We save/restore all registers marked with 'Driver', with the following
1949 * exceptions:
1950 * - Registers out of use, including also registers marked with 'Debug'.
1951 * These have no effect on the driver's operation, so we don't save/restore
1952 * them to reduce the overhead.
1953 * - Registers that are fully setup by an initialization function called from
1954 * the resume path. For example many clock gating and RPS/RC6 registers.
1955 * - Registers that provide the right functionality with their reset defaults.
1956 *
1957 * TODO: Except for registers that based on the above 3 criteria can be safely
1958 * ignored, we save/restore all others, practically treating the HW context as
1959 * a black-box for the driver. Further investigation is needed to reduce the
1960 * saved/restored registers even further, by following the same 3 criteria.
1961 */
1962static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1963{
1964 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1965 int i;
1966
1967 /* GAM 0x4000-0x4770 */
1968 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1969 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1970 s->arb_mode = I915_READ(ARB_MODE);
1971 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1972 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1973
1974 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 1975 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 1976
1977 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 1978 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 1979
1980 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1981 s->ecochk = I915_READ(GAM_ECOCHK);
1982 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1983 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1984
1985 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1986
1987 /* MBC 0x9024-0x91D0, 0x8500 */
1988 s->g3dctl = I915_READ(VLV_G3DCTL);
1989 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1990 s->mbctl = I915_READ(GEN6_MBCTL);
1991
1992 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1993 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1994 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1995 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1996 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1997 s->rstctl = I915_READ(GEN6_RSTCTL);
1998 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1999
2000 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2001 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2002 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2003 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2004 s->ecobus = I915_READ(ECOBUS);
2005 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2006 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2007 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2008 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2009 s->rcedata = I915_READ(VLV_RCEDATA);
2010 s->spare2gh = I915_READ(VLV_SPAREG2H);
2011
2012 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2013 s->gt_imr = I915_READ(GTIMR);
2014 s->gt_ier = I915_READ(GTIER);
2015 s->pm_imr = I915_READ(GEN6_PMIMR);
2016 s->pm_ier = I915_READ(GEN6_PMIER);
2017
2018 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2019 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2020
2021 /* GT SA CZ domain, 0x100000-0x138124 */
2022 s->tilectl = I915_READ(TILECTL);
2023 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2024 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2025 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2026 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2027
2028 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2029 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2030 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2031 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2032 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2033
2034 /*
2035 * Not saving any of:
2036 * DFT, 0x9800-0x9EC0
2037 * SARB, 0xB000-0xB1FC
2038 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2039 * PCI CFG
2040 */
2041}
2042
2043static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2044{
2045 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2046 u32 val;
2047 int i;
2048
2049 /* GAM 0x4000-0x4770 */
2050 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2051 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2052 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2053 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2054 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2055
2056 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2057 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2058
2059 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2060 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2061
2062 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2063 I915_WRITE(GAM_ECOCHK, s->ecochk);
2064 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2065 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2066
2067 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2068
2069 /* MBC 0x9024-0x91D0, 0x8500 */
2070 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2071 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2072 I915_WRITE(GEN6_MBCTL, s->mbctl);
2073
2074 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2075 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2076 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2077 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2078 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2079 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2080 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2081
2082 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2083 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2084 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2085 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2086 I915_WRITE(ECOBUS, s->ecobus);
2087 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2088 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2089 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2090 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2091 I915_WRITE(VLV_RCEDATA, s->rcedata);
2092 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2093
2094 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2095 I915_WRITE(GTIMR, s->gt_imr);
2096 I915_WRITE(GTIER, s->gt_ier);
2097 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2098 I915_WRITE(GEN6_PMIER, s->pm_ier);
2099
2100 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2101 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2102
2103 /* GT SA CZ domain, 0x100000-0x138124 */
2104 I915_WRITE(TILECTL, s->tilectl);
2105 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2106 /*
2107 * Preserve the GT allow wake and GFX force clock bit, they are not
2108 * be restored, as they are used to control the s0ix suspend/resume
2109 * sequence by the caller.
2110 */
2111 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2112 val &= VLV_GTLC_ALLOWWAKEREQ;
2113 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2114 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2115
2116 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2117 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2118 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2119 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2120
2121 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2122
2123 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2124 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2125 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2126 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2127 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2128}
2129
650ad970
ID		 2130int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2131{
2132 u32 val;
2133 int err;
2134
650ad970
ID		 2135 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2136 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2137 if (force_on)
2138 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2139 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2140
2141 if (!force_on)
2142 return 0;
2143
c6ddc5f3
CW		 2144 err = intel_wait_for_register(dev_priv,
2145 VLV_GTLC_SURVIVABILITY_REG,
2146 VLV_GFX_CLK_STATUS_BIT,
2147 VLV_GFX_CLK_STATUS_BIT,
2148 20);
650ad970
ID		 2149 if (err)
2150 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2151 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2152
2153 return err;
650ad970
ID		 2154}
2155
ddeea5b0
ID		 2156static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2157{
2158 u32 val;
2159 int err = 0;
2160
2161 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2162 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2163 if (allow)
2164 val |= VLV_GTLC_ALLOWWAKEREQ;
2165 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2166 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2167
b2736695
CW		 2168 err = intel_wait_for_register(dev_priv,
2169 VLV_GTLC_PW_STATUS,
2170 VLV_GTLC_ALLOWWAKEACK,
2171 allow,
2172 1);
ddeea5b0
ID		 2173 if (err)
2174 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2175
ddeea5b0 2176 return err;
ddeea5b0
ID		 2177}
2178
2179static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2180 bool wait_for_on)
2181{
2182 u32 mask;
2183 u32 val;
2184 int err;
2185
2186 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2187 val = wait_for_on ? mask : 0;
41ce405e 2188 if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
ddeea5b0
ID		 2189 return 0;
2190
2191 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
87ad3212
JN		 2192 onoff(wait_for_on),
2193 I915_READ(VLV_GTLC_PW_STATUS));
ddeea5b0
ID		 2194
2195 /*
2196 * RC6 transitioning can be delayed up to 2 msec (see
2197 * valleyview_enable_rps), use 3 msec for safety.
2198 */
41ce405e
CW		 2199 err = intel_wait_for_register(dev_priv,
2200 VLV_GTLC_PW_STATUS, mask, val,
2201 3);
ddeea5b0
ID		 2202 if (err)
2203 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2204 onoff(wait_for_on));
ddeea5b0
ID		 2205
2206 return err;
ddeea5b0
ID		 2207}
2208
2209static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2210{
2211 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2212 return;
2213
6fa283b0 2214 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2215 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2216}
2217
ebc32824 2218static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2219{
2220 u32 mask;
2221 int err;
2222
2223 /*
2224 * Bspec defines the following GT well on flags as debug only, so
2225 * don't treat them as hard failures.
2226 */
2227 (void)vlv_wait_for_gt_wells(dev_priv, false);
2228
2229 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2230 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2231
2232 vlv_check_no_gt_access(dev_priv);
2233
2234 err = vlv_force_gfx_clock(dev_priv, true);
2235 if (err)
2236 goto err1;
2237
2238 err = vlv_allow_gt_wake(dev_priv, false);
2239 if (err)
2240 goto err2;
98711167 2241
2d1fe073 2242 if (!IS_CHERRYVIEW(dev_priv))
98711167 2243 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2244
2245 err = vlv_force_gfx_clock(dev_priv, false);
2246 if (err)
2247 goto err2;
2248
2249 return 0;
2250
2251err2:
2252 /* For safety always re-enable waking and disable gfx clock forcing */
2253 vlv_allow_gt_wake(dev_priv, true);
2254err1:
2255 vlv_force_gfx_clock(dev_priv, false);
2256
2257 return err;
2258}
2259
016970be
SK		 2260static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2261 bool rpm_resume)
ddeea5b0 2262{
ddeea5b0
ID		 2263 int err;
2264 int ret;
2265
2266 /*
2267 * If any of the steps fail just try to continue, that's the best we
2268 * can do at this point. Return the first error code (which will also
2269 * leave RPM permanently disabled).
2270 */
2271 ret = vlv_force_gfx_clock(dev_priv, true);
2272
2d1fe073 2273 if (!IS_CHERRYVIEW(dev_priv))
98711167 2274 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2275
2276 err = vlv_allow_gt_wake(dev_priv, true);
2277 if (!ret)
2278 ret = err;
2279
2280 err = vlv_force_gfx_clock(dev_priv, false);
2281 if (!ret)
2282 ret = err;
2283
2284 vlv_check_no_gt_access(dev_priv);
2285
7c108fd8 2286 if (rpm_resume)
46f16e63 2287 intel_init_clock_gating(dev_priv);
ddeea5b0
ID		 2288
2289 return ret;
2290}
2291
c49d13ee 2292static int intel_runtime_suspend(struct device *kdev)
8a187455 2293{
c49d13ee 2294 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2295 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2296 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2297 int ret;
8a187455 2298
dc97997a 2299 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2300 return -ENODEV;
2301
6772ffe0 2302 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7
ID		 2303 return -ENODEV;
2304
8a187455
PZ		 2305 DRM_DEBUG_KMS("Suspending device\n");
2306
1f814dac
ID		 2307 disable_rpm_wakeref_asserts(dev_priv);
2308
d6102977
ID		 2309 /*
2310 * We are safe here against re-faults, since the fault handler takes
2311 * an RPM reference.
2312 */
7c108fd8 2313 i915_gem_runtime_suspend(dev_priv);
d6102977 2314
bf9e8429 2315 intel_guc_suspend(dev_priv);
a1c41994 2316
2eb5252e 2317 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2318
507e126e 2319 ret = 0;
b9fd799e 2320 if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2321 bxt_display_core_uninit(dev_priv);
2322 bxt_enable_dc9(dev_priv);
2323 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2324 hsw_enable_pc8(dev_priv);
2325 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2326 ret = vlv_suspend_complete(dev_priv);
2327 }
2328
0ab9cfeb
ID		 2329 if (ret) {
2330 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2331 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2332
1f814dac
ID		 2333 enable_rpm_wakeref_asserts(dev_priv);
2334
0ab9cfeb
ID		 2335 return ret;
2336 }
a8a8bd54 2337
dc97997a 2338 intel_uncore_forcewake_reset(dev_priv, false);
1f814dac
ID		 2339
2340 enable_rpm_wakeref_asserts(dev_priv);
2341 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2342
bc3b9346 2343 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2344 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2345
8a187455 2346 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2347
2348 /*
c8a0bd42
PZ		 2349 * FIXME: We really should find a document that references the arguments
2350 * used below!
1fb2362b 2351 */
6f9f4b7a 2352 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2353 /*
2354 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2355 * being detected, and the call we do at intel_runtime_resume()
2356 * won't be able to restore them. Since PCI_D3hot matches the
2357 * actual specification and appears to be working, use it.
2358 */
6f9f4b7a 2359 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2360 } else {
c8a0bd42
PZ		 2361 /*
2362 * current versions of firmware which depend on this opregion
2363 * notification have repurposed the D1 definition to mean
2364 * "runtime suspended" vs. what you would normally expect (D3)
2365 * to distinguish it from notifications that might be sent via
2366 * the suspend path.
2367 */
6f9f4b7a 2368 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2369 }
8a187455 2370
59bad947 2371 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2372
19625e85
L		 2373 if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2374 intel_hpd_poll_init(dev_priv);
2375
a8a8bd54 2376 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2377 return 0;
2378}
2379
c49d13ee 2380static int intel_runtime_resume(struct device *kdev)
8a187455 2381{
c49d13ee 2382 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2383 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2384 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2385 int ret = 0;
8a187455 2386
6772ffe0 2387 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7 2388 return -ENODEV;
8a187455
PZ		 2389
2390 DRM_DEBUG_KMS("Resuming device\n");
2391
1f814dac
ID		 2392 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2393 disable_rpm_wakeref_asserts(dev_priv);
2394
6f9f4b7a 2395 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2396 dev_priv->pm.suspended = false;
55ec45c2
MK		 2397 if (intel_uncore_unclaimed_mmio(dev_priv))
2398 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2399
bf9e8429 2400 intel_guc_resume(dev_priv);
a1c41994 2401
1a5df187 2402 if (IS_GEN6(dev_priv))
c39055b0 2403 intel_init_pch_refclk(dev_priv);
31335cec 2404
b9fd799e 2405 if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2406 bxt_disable_dc9(dev_priv);
2407 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2408 if (dev_priv->csr.dmc_payload &&
2409 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2410 gen9_enable_dc5(dev_priv);
507e126e 2411 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2412 hsw_disable_pc8(dev_priv);
507e126e 2413 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2414 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2415 }
1a5df187 2416
0ab9cfeb
ID		 2417 /*
2418 * No point of rolling back things in case of an error, as the best
2419 * we can do is to hope that things will still work (and disable RPM).
2420 */
c6be607a 2421 i915_gem_init_swizzling(dev_priv);
92b806d3 2422
b963291c 2423 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2424
2425 /*
2426 * On VLV/CHV display interrupts are part of the display
2427 * power well, so hpd is reinitialized from there. For
2428 * everyone else do it here.
2429 */
666a4537 2430 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2431 intel_hpd_init(dev_priv);
2432
1f814dac
ID		 2433 enable_rpm_wakeref_asserts(dev_priv);
2434
0ab9cfeb
ID		 2435 if (ret)
2436 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2437 else
2438 DRM_DEBUG_KMS("Device resumed\n");
2439
2440 return ret;
8a187455
PZ		 2441}
2442
42f5551d 2443const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2444 /*
2445 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2446 * PMSG_RESUME]
2447 */
0206e353 2448 .suspend = i915_pm_suspend,
76c4b250
ID		 2449 .suspend_late = i915_pm_suspend_late,
2450 .resume_early = i915_pm_resume_early,
0206e353 2451 .resume = i915_pm_resume,
5545dbbf
ID		 2452
2453 /*
2454 * S4 event handlers
2455 * @freeze, @freeze_late : called (1) before creating the
2456 * hibernation image [PMSG_FREEZE] and
2457 * (2) after rebooting, before restoring
2458 * the image [PMSG_QUIESCE]
2459 * @thaw, @thaw_early : called (1) after creating the hibernation
2460 * image, before writing it [PMSG_THAW]
2461 * and (2) after failing to create or
2462 * restore the image [PMSG_RECOVER]
2463 * @poweroff, @poweroff_late: called after writing the hibernation
2464 * image, before rebooting [PMSG_HIBERNATE]
2465 * @restore, @restore_early : called after rebooting and restoring the
2466 * hibernation image [PMSG_RESTORE]
2467 */
1f19ac2a
CW		 2468 .freeze = i915_pm_freeze,
2469 .freeze_late = i915_pm_freeze_late,
2470 .thaw_early = i915_pm_thaw_early,
2471 .thaw = i915_pm_thaw,
36d61e67 2472 .poweroff = i915_pm_suspend,
ab3be73f 2473 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2474 .restore_early = i915_pm_restore_early,
2475 .restore = i915_pm_restore,
5545dbbf
ID		 2476
2477 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2478 .runtime_suspend = intel_runtime_suspend,
2479 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2480};
2481
78b68556 2482static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2483 .fault = i915_gem_fault,
ab00b3e5
JB		 2484 .open = drm_gem_vm_open,
2485 .close = drm_gem_vm_close,
de151cf6
JB		 2486};
2487
e08e96de
AV		 2488static const struct file_operations i915_driver_fops = {
2489 .owner = THIS_MODULE,
2490 .open = drm_open,
2491 .release = drm_release,
2492 .unlocked_ioctl = drm_ioctl,
2493 .mmap = drm_gem_mmap,
2494 .poll = drm_poll,
e08e96de 2495 .read = drm_read,
e08e96de 2496 .compat_ioctl = i915_compat_ioctl,
e08e96de
AV		 2497 .llseek = noop_llseek,
2498};
2499
0673ad47
CW		 2500static int
2501i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2502 struct drm_file *file)
2503{
2504 return -ENODEV;
2505}
2506
2507static const struct drm_ioctl_desc i915_ioctls[] = {
2508 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2509 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2510 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2511 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2512 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2513 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2514 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2515 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2516 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2517 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2518 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2519 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2520 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2521 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2522 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2523 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2524 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2525 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2526 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2527 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2528 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2529 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2530 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2531 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2532 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2533 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2534 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2535 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2536 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2537 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2538 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2539 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2540 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2541 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2542 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
111dbcab
CW		 2543 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2544 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
0673ad47
CW		 2545 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2546 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2547 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2548 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2549 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2550 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2551 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2552 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2553 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2554 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2555 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2556 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2557 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2558 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2559 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
eec688e1 2560 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
0673ad47
CW		 2561};
2562
1da177e4 2563static struct drm_driver driver = {
0c54781b
MW		 2564 /* Don't use MTRRs here; the Xserver or userspace app should
2565 * deal with them for Intel hardware.
792d2b9a 2566 */
673a394b 2567 .driver_features =
10ba5012 2568 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1751fcf9 2569 DRIVER_RENDER | DRIVER_MODESET,
673a394b 2570 .open = i915_driver_open,
22eae947
DA		 2571 .lastclose = i915_driver_lastclose,
2572 .preclose = i915_driver_preclose,
673a394b 2573 .postclose = i915_driver_postclose,
915b4d11 2574 .set_busid = drm_pci_set_busid,
d8e29209 2575
b1f788c6 2576 .gem_close_object = i915_gem_close_object,
f0cd5182 2577 .gem_free_object_unlocked = i915_gem_free_object,
de151cf6 2578 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2579
2580 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2581 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2582 .gem_prime_export = i915_gem_prime_export,
2583 .gem_prime_import = i915_gem_prime_import,
2584
ff72145b 2585 .dumb_create = i915_gem_dumb_create,
da6b51d0 2586 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 2587 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 2588 .ioctls = i915_ioctls,
0673ad47 2589 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2590 .fops = &i915_driver_fops,
22eae947
DA		 2591 .name = DRIVER_NAME,
2592 .desc = DRIVER_DESC,
2593 .date = DRIVER_DATE,
2594 .major = DRIVER_MAJOR,
2595 .minor = DRIVER_MINOR,
2596 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2597};
Ubuntu Hirsute Linux kernel mirror