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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a726915c | 50 | int i915_panel_ignore_lid __read_mostly = 1; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 | 52 | MODULE_PARM_DESC(panel_ignore_lid, |
a726915c DV |
53 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " |
54 | "-1=force lid closed, -2=force lid open)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
f57f9c16 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
0a3af268 RV |
121 | unsigned int i915_preliminary_hw_support __read_mostly = 0; |
122 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); | |
123 | MODULE_PARM_DESC(preliminary_hw_support, | |
c4aaf350 | 124 | "Enable preliminary hardware support. (default: false)"); |
0a3af268 | 125 | |
2124b72e PZ |
126 | int i915_disable_power_well __read_mostly = 0; |
127 | module_param_named(disable_power_well, i915_disable_power_well, int, 0600); | |
128 | MODULE_PARM_DESC(disable_power_well, | |
129 | "Disable the power well when possible (default: false)"); | |
130 | ||
3c4ca58c PZ |
131 | int i915_enable_ips __read_mostly = 1; |
132 | module_param_named(enable_ips, i915_enable_ips, int, 0600); | |
133 | MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); | |
134 | ||
2385bdf0 JB |
135 | bool i915_fastboot __read_mostly = 0; |
136 | module_param_named(fastboot, i915_fastboot, bool, 0600); | |
137 | MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time " | |
138 | "(default: false)"); | |
139 | ||
112b715e | 140 | static struct drm_driver driver; |
1f7a6e37 | 141 | extern int intel_agp_enabled; |
112b715e | 142 | |
cfdf1fa2 | 143 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 144 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 145 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
146 | .vendor = 0x8086, \ |
147 | .device = id, \ | |
148 | .subvendor = PCI_ANY_ID, \ | |
149 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
150 | .driver_data = (unsigned long) info } |
151 | ||
999bcdea BW |
152 | #define INTEL_QUANTA_VGA_DEVICE(info) { \ |
153 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ | |
154 | .class_mask = 0xff0000, \ | |
155 | .vendor = 0x8086, \ | |
156 | .device = 0x16a, \ | |
157 | .subvendor = 0x152d, \ | |
158 | .subdevice = 0x8990, \ | |
159 | .driver_data = (unsigned long) info } | |
160 | ||
161 | ||
9a7e8492 | 162 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 163 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 164 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
165 | }; |
166 | ||
9a7e8492 | 167 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 168 | .gen = 2, .num_pipes = 1, |
31578148 | 169 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
170 | }; |
171 | ||
9a7e8492 | 172 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 173 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 174 | .cursor_needs_physical = 1, |
31578148 | 175 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
176 | }; |
177 | ||
9a7e8492 | 178 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 179 | .gen = 2, .num_pipes = 1, |
31578148 | 180 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
181 | }; |
182 | ||
9a7e8492 | 183 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 184 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 185 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 186 | }; |
9a7e8492 | 187 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 188 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 189 | .cursor_needs_physical = 1, |
31578148 | 190 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 191 | .supports_tv = 1, |
cfdf1fa2 | 192 | }; |
9a7e8492 | 193 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 194 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 195 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 196 | }; |
9a7e8492 | 197 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 198 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 199 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 200 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 201 | .supports_tv = 1, |
cfdf1fa2 KH |
202 | }; |
203 | ||
9a7e8492 | 204 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 205 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 206 | .has_hotplug = 1, |
31578148 | 207 | .has_overlay = 1, |
cfdf1fa2 KH |
208 | }; |
209 | ||
9a7e8492 | 210 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 211 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 212 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 213 | .has_overlay = 1, |
a6c45cf0 | 214 | .supports_tv = 1, |
cfdf1fa2 KH |
215 | }; |
216 | ||
9a7e8492 | 217 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 218 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 219 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 220 | .has_overlay = 1, |
cfdf1fa2 KH |
221 | }; |
222 | ||
9a7e8492 | 223 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 224 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 225 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 226 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
227 | }; |
228 | ||
9a7e8492 | 229 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 230 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 231 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 232 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 233 | .supports_tv = 1, |
92f49d9c | 234 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
235 | }; |
236 | ||
9a7e8492 | 237 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 238 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 239 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 240 | .has_overlay = 1, |
cfdf1fa2 KH |
241 | }; |
242 | ||
9a7e8492 | 243 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 244 | .gen = 5, .num_pipes = 2, |
5a117db7 | 245 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 246 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
247 | }; |
248 | ||
9a7e8492 | 249 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 250 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 251 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 252 | .has_fbc = 1, |
92f49d9c | 253 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
254 | }; |
255 | ||
9a7e8492 | 256 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 257 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 258 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 259 | .has_bsd_ring = 1, |
549f7365 | 260 | .has_blt_ring = 1, |
3d29b842 | 261 | .has_llc = 1, |
b7884eb4 | 262 | .has_force_wake = 1, |
f6e450a6 EA |
263 | }; |
264 | ||
9a7e8492 | 265 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 266 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 267 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 268 | .has_fbc = 1, |
881f47b6 | 269 | .has_bsd_ring = 1, |
549f7365 | 270 | .has_blt_ring = 1, |
3d29b842 | 271 | .has_llc = 1, |
b7884eb4 | 272 | .has_force_wake = 1, |
a13e4093 EA |
273 | }; |
274 | ||
219f4fdb BW |
275 | #define GEN7_FEATURES \ |
276 | .gen = 7, .num_pipes = 3, \ | |
277 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
278 | .has_bsd_ring = 1, \ | |
279 | .has_blt_ring = 1, \ | |
280 | .has_llc = 1, \ | |
281 | .has_force_wake = 1 | |
282 | ||
c76b615c | 283 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
284 | GEN7_FEATURES, |
285 | .is_ivybridge = 1, | |
c76b615c JB |
286 | }; |
287 | ||
288 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
289 | GEN7_FEATURES, |
290 | .is_ivybridge = 1, | |
291 | .is_mobile = 1, | |
abe959c7 | 292 | .has_fbc = 1, |
c76b615c JB |
293 | }; |
294 | ||
999bcdea BW |
295 | static const struct intel_device_info intel_ivybridge_q_info = { |
296 | GEN7_FEATURES, | |
297 | .is_ivybridge = 1, | |
298 | .num_pipes = 0, /* legal, last one wins */ | |
299 | }; | |
300 | ||
70a3eb7a | 301 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
302 | GEN7_FEATURES, |
303 | .is_mobile = 1, | |
304 | .num_pipes = 2, | |
70a3eb7a | 305 | .is_valleyview = 1, |
fba5d532 | 306 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 307 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
308 | }; |
309 | ||
310 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
311 | GEN7_FEATURES, |
312 | .num_pipes = 2, | |
70a3eb7a | 313 | .is_valleyview = 1, |
fba5d532 | 314 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 315 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
316 | }; |
317 | ||
4cae9ae0 | 318 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
319 | GEN7_FEATURES, |
320 | .is_haswell = 1, | |
dd93be58 | 321 | .has_ddi = 1, |
30568c45 | 322 | .has_fpga_dbg = 1, |
f72a1183 | 323 | .has_vebox_ring = 1, |
4cae9ae0 ED |
324 | }; |
325 | ||
326 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
327 | GEN7_FEATURES, |
328 | .is_haswell = 1, | |
329 | .is_mobile = 1, | |
dd93be58 | 330 | .has_ddi = 1, |
30568c45 | 331 | .has_fpga_dbg = 1, |
891348b2 | 332 | .has_fbc = 1, |
f72a1183 | 333 | .has_vebox_ring = 1, |
c76b615c JB |
334 | }; |
335 | ||
6103da0d CW |
336 | static const struct pci_device_id pciidlist[] = { /* aka */ |
337 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
338 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
339 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 340 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
341 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
342 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
343 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
344 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
345 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
346 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
347 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
348 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
349 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
350 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
351 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
352 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
353 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
354 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
355 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
356 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
357 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
358 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
359 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
360 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
361 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
362 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 363 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
364 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
365 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
366 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
367 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 368 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
369 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
370 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 371 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 372 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 373 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 374 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
375 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
376 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
377 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
378 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
379 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
999bcdea | 380 | INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */ |
cc22a938 | 381 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
c14f5286 ED |
382 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
383 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ | |
1c98b487 | 384 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */ |
c14f5286 ED |
385 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
386 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ | |
1c98b487 | 387 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */ |
c14f5286 ED |
388 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
389 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ | |
da612d88 | 390 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
1c98b487 RV |
391 | INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */ |
392 | INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */ | |
393 | INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */ | |
394 | INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */ | |
395 | INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */ | |
396 | INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */ | |
da612d88 PZ |
397 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
398 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ | |
1c98b487 | 399 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */ |
da612d88 PZ |
400 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
401 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ | |
1c98b487 | 402 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */ |
da612d88 PZ |
403 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
404 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ | |
1c98b487 RV |
405 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */ |
406 | INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */ | |
407 | INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */ | |
408 | INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */ | |
409 | INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */ | |
410 | INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */ | |
411 | INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */ | |
da612d88 PZ |
412 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
413 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ | |
1c98b487 | 414 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */ |
da612d88 PZ |
415 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
416 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ | |
1c98b487 | 417 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */ |
da612d88 PZ |
418 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
419 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ | |
1c98b487 RV |
420 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */ |
421 | INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */ | |
422 | INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */ | |
423 | INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */ | |
424 | INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */ | |
425 | INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */ | |
426 | INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */ | |
86c268ed KG |
427 | INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */ |
428 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */ | |
1c98b487 | 429 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */ |
86c268ed KG |
430 | INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */ |
431 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */ | |
1c98b487 | 432 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */ |
86c268ed KG |
433 | INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */ |
434 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */ | |
1c98b487 RV |
435 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */ |
436 | INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */ | |
437 | INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */ | |
438 | INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */ | |
439 | INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */ | |
440 | INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */ | |
441 | INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */ | |
ff049b6c | 442 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
d7fee5f6 JB |
443 | INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info), |
444 | INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info), | |
445 | INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info), | |
ff049b6c JB |
446 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
447 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), | |
49ae35f2 | 448 | {0, 0, 0} |
1da177e4 LT |
449 | }; |
450 | ||
79e53945 JB |
451 | #if defined(CONFIG_DRM_I915_KMS) |
452 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
453 | #endif | |
454 | ||
0206e353 | 455 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
456 | { |
457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
458 | struct pci_dev *pch; | |
459 | ||
ce1bb329 BW |
460 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
461 | * (which really amounts to a PCH but no South Display). | |
462 | */ | |
463 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
464 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
465 | return; |
466 | } | |
467 | ||
3bad0781 ZW |
468 | /* |
469 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
470 | * make graphics device passthrough work easy for VMM, that only | |
471 | * need to expose ISA bridge to let driver know the real hardware | |
472 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
473 | * |
474 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
475 | * ISA bridge in the system. To work reliably, we should scan trhough | |
476 | * all the ISA bridge devices and check for the first match, instead | |
477 | * of only checking the first one. | |
3bad0781 ZW |
478 | */ |
479 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
6a9c4b35 RG |
480 | while (pch) { |
481 | struct pci_dev *curr = pch; | |
3bad0781 | 482 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
17a303ec | 483 | unsigned short id; |
3bad0781 | 484 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 485 | dev_priv->pch_id = id; |
3bad0781 | 486 | |
90711d50 JB |
487 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
488 | dev_priv->pch_type = PCH_IBX; | |
489 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 490 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 491 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
492 | dev_priv->pch_type = PCH_CPT; |
493 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 494 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
495 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
496 | /* PantherPoint is CPT compatible */ | |
497 | dev_priv->pch_type = PCH_CPT; | |
498 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | |
7fcb83cd | 499 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
500 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
501 | dev_priv->pch_type = PCH_LPT; | |
502 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 503 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 504 | WARN_ON(IS_ULT(dev)); |
ae6935dd WSC |
505 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
506 | dev_priv->pch_type = PCH_LPT; | |
ae6935dd WSC |
507 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
508 | WARN_ON(!IS_HASWELL(dev)); | |
08e1413d | 509 | WARN_ON(!IS_ULT(dev)); |
6a9c4b35 RG |
510 | } else { |
511 | goto check_next; | |
3bad0781 | 512 | } |
6a9c4b35 RG |
513 | pci_dev_put(pch); |
514 | break; | |
3bad0781 | 515 | } |
6a9c4b35 RG |
516 | check_next: |
517 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr); | |
518 | pci_dev_put(curr); | |
3bad0781 | 519 | } |
6a9c4b35 RG |
520 | if (!pch) |
521 | DRM_DEBUG_KMS("No PCH found?\n"); | |
3bad0781 ZW |
522 | } |
523 | ||
2911a35b BW |
524 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
525 | { | |
526 | if (INTEL_INFO(dev)->gen < 6) | |
527 | return 0; | |
528 | ||
529 | if (i915_semaphores >= 0) | |
530 | return i915_semaphores; | |
531 | ||
59de3295 | 532 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 533 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
534 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
535 | return false; | |
536 | #endif | |
2911a35b BW |
537 | |
538 | return 1; | |
539 | } | |
540 | ||
84b79f8d | 541 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 542 | { |
61caf87c | 543 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 544 | struct drm_crtc *crtc; |
61caf87c | 545 | |
b8efb17b ZR |
546 | /* ignore lid events during suspend */ |
547 | mutex_lock(&dev_priv->modeset_restore_lock); | |
548 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
549 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
550 | ||
cb10799c PZ |
551 | intel_set_power_well(dev, true); |
552 | ||
5bcf719b DA |
553 | drm_kms_helper_poll_disable(dev); |
554 | ||
ba8bbcf6 | 555 | pci_save_state(dev->pdev); |
ba8bbcf6 | 556 | |
5669fcac | 557 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 558 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
559 | int error; |
560 | ||
561 | mutex_lock(&dev->struct_mutex); | |
562 | error = i915_gem_idle(dev); | |
563 | mutex_unlock(&dev->struct_mutex); | |
84b79f8d | 564 | if (error) { |
226485e9 | 565 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
566 | "GEM idle failed, resume might fail\n"); |
567 | return error; | |
568 | } | |
a261b246 | 569 | |
1a01ab3b JB |
570 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
571 | ||
226485e9 | 572 | drm_irq_uninstall(dev); |
15239099 | 573 | dev_priv->enable_hotplug_processing = false; |
24576d23 JB |
574 | /* |
575 | * Disable CRTCs directly since we want to preserve sw state | |
576 | * for _thaw. | |
577 | */ | |
578 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
579 | dev_priv->display.crtc_disable(crtc); | |
7d708ee4 ID |
580 | |
581 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
582 | } |
583 | ||
9e06dd39 JB |
584 | i915_save_state(dev); |
585 | ||
44834a67 | 586 | intel_opregion_fini(dev); |
8ee1c3db | 587 | |
3fa016a0 | 588 | console_lock(); |
b6f3eff7 | 589 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
590 | console_unlock(); |
591 | ||
61caf87c | 592 | return 0; |
84b79f8d RW |
593 | } |
594 | ||
6a9ee8af | 595 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
596 | { |
597 | int error; | |
598 | ||
599 | if (!dev || !dev->dev_private) { | |
600 | DRM_ERROR("dev: %p\n", dev); | |
601 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
602 | return -ENODEV; | |
603 | } | |
604 | ||
605 | if (state.event == PM_EVENT_PRETHAW) | |
606 | return 0; | |
607 | ||
5bcf719b DA |
608 | |
609 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
610 | return 0; | |
6eecba33 | 611 | |
84b79f8d RW |
612 | error = i915_drm_freeze(dev); |
613 | if (error) | |
614 | return error; | |
615 | ||
b932ccb5 DA |
616 | if (state.event == PM_EVENT_SUSPEND) { |
617 | /* Shut down the device */ | |
618 | pci_disable_device(dev->pdev); | |
619 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
620 | } | |
ba8bbcf6 JB |
621 | |
622 | return 0; | |
623 | } | |
624 | ||
073f34d9 JB |
625 | void intel_console_resume(struct work_struct *work) |
626 | { | |
627 | struct drm_i915_private *dev_priv = | |
628 | container_of(work, struct drm_i915_private, | |
629 | console_resume_work); | |
630 | struct drm_device *dev = dev_priv->dev; | |
631 | ||
632 | console_lock(); | |
b6f3eff7 | 633 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
634 | console_unlock(); |
635 | } | |
636 | ||
bb60b969 JB |
637 | static void intel_resume_hotplug(struct drm_device *dev) |
638 | { | |
639 | struct drm_mode_config *mode_config = &dev->mode_config; | |
640 | struct intel_encoder *encoder; | |
641 | ||
642 | mutex_lock(&mode_config->mutex); | |
643 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); | |
644 | ||
645 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
646 | if (encoder->hot_plug) | |
647 | encoder->hot_plug(encoder); | |
648 | ||
649 | mutex_unlock(&mode_config->mutex); | |
650 | ||
651 | /* Just fire off a uevent and let userspace tell us what to do */ | |
652 | drm_helper_hpd_irq_event(dev); | |
653 | } | |
654 | ||
1abd02e2 | 655 | static int __i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 656 | { |
5669fcac | 657 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 658 | int error = 0; |
8ee1c3db | 659 | |
61caf87c | 660 | i915_restore_state(dev); |
44834a67 | 661 | intel_opregion_setup(dev); |
61caf87c | 662 | |
5669fcac JB |
663 | /* KMS EnterVT equivalent */ |
664 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 665 | intel_init_pch_refclk(dev); |
1833b134 | 666 | |
5669fcac | 667 | mutex_lock(&dev->struct_mutex); |
5669fcac | 668 | |
f691e2f4 | 669 | error = i915_gem_init_hw(dev); |
5669fcac | 670 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 671 | |
15239099 DV |
672 | /* We need working interrupts for modeset enabling ... */ |
673 | drm_irq_install(dev); | |
674 | ||
1833b134 | 675 | intel_modeset_init_hw(dev); |
24576d23 JB |
676 | |
677 | drm_modeset_lock_all(dev); | |
678 | intel_modeset_setup_hw_state(dev, true); | |
679 | drm_modeset_unlock_all(dev); | |
15239099 DV |
680 | |
681 | /* | |
682 | * ... but also need to make sure that hotplug processing | |
683 | * doesn't cause havoc. Like in the driver load code we don't | |
684 | * bother with the tiny race here where we might loose hotplug | |
685 | * notifications. | |
686 | * */ | |
20afbda2 | 687 | intel_hpd_init(dev); |
15239099 | 688 | dev_priv->enable_hotplug_processing = true; |
bb60b969 JB |
689 | /* Config may have changed between suspend and resume */ |
690 | intel_resume_hotplug(dev); | |
d5bb081b | 691 | } |
1daed3fb | 692 | |
44834a67 CW |
693 | intel_opregion_init(dev); |
694 | ||
073f34d9 JB |
695 | /* |
696 | * The console lock can be pretty contented on resume due | |
697 | * to all the printk activity. Try to keep it out of the hot | |
698 | * path of resume if possible. | |
699 | */ | |
700 | if (console_trylock()) { | |
b6f3eff7 | 701 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
702 | console_unlock(); |
703 | } else { | |
704 | schedule_work(&dev_priv->console_resume_work); | |
705 | } | |
706 | ||
b8efb17b ZR |
707 | mutex_lock(&dev_priv->modeset_restore_lock); |
708 | dev_priv->modeset_restore = MODESET_DONE; | |
709 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
84b79f8d RW |
710 | return error; |
711 | } | |
712 | ||
1abd02e2 JB |
713 | static int i915_drm_thaw(struct drm_device *dev) |
714 | { | |
715 | int error = 0; | |
716 | ||
717 | intel_gt_reset(dev); | |
718 | ||
719 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
720 | mutex_lock(&dev->struct_mutex); | |
721 | i915_gem_restore_gtt_mappings(dev); | |
722 | mutex_unlock(&dev->struct_mutex); | |
723 | } | |
724 | ||
725 | __i915_drm_thaw(dev); | |
726 | ||
84b79f8d RW |
727 | return error; |
728 | } | |
729 | ||
6a9ee8af | 730 | int i915_resume(struct drm_device *dev) |
84b79f8d | 731 | { |
1abd02e2 | 732 | struct drm_i915_private *dev_priv = dev->dev_private; |
6eecba33 CW |
733 | int ret; |
734 | ||
5bcf719b DA |
735 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
736 | return 0; | |
737 | ||
84b79f8d RW |
738 | if (pci_enable_device(dev->pdev)) |
739 | return -EIO; | |
740 | ||
741 | pci_set_master(dev->pdev); | |
742 | ||
1abd02e2 JB |
743 | intel_gt_reset(dev); |
744 | ||
745 | /* | |
746 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
747 | * earlier) need this since the BIOS might clear all our scratch PTEs. | |
748 | */ | |
749 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
750 | !dev_priv->opregion.header) { | |
751 | mutex_lock(&dev->struct_mutex); | |
752 | i915_gem_restore_gtt_mappings(dev); | |
753 | mutex_unlock(&dev->struct_mutex); | |
754 | } | |
755 | ||
756 | ret = __i915_drm_thaw(dev); | |
6eecba33 CW |
757 | if (ret) |
758 | return ret; | |
759 | ||
760 | drm_kms_helper_poll_enable(dev); | |
761 | return 0; | |
ba8bbcf6 JB |
762 | } |
763 | ||
d4b8bb2a | 764 | static int i8xx_do_reset(struct drm_device *dev) |
dc96e9b8 CW |
765 | { |
766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
767 | ||
768 | if (IS_I85X(dev)) | |
769 | return -ENODEV; | |
770 | ||
771 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
772 | POSTING_READ(D_STATE); | |
773 | ||
774 | if (IS_I830(dev) || IS_845G(dev)) { | |
775 | I915_WRITE(DEBUG_RESET_I830, | |
776 | DEBUG_RESET_DISPLAY | | |
777 | DEBUG_RESET_RENDER | | |
778 | DEBUG_RESET_FULL); | |
779 | POSTING_READ(DEBUG_RESET_I830); | |
780 | msleep(1); | |
781 | ||
782 | I915_WRITE(DEBUG_RESET_I830, 0); | |
783 | POSTING_READ(DEBUG_RESET_I830); | |
784 | } | |
785 | ||
786 | msleep(1); | |
787 | ||
788 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
789 | POSTING_READ(D_STATE); | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
f49f0586 KG |
794 | static int i965_reset_complete(struct drm_device *dev) |
795 | { | |
796 | u8 gdrst; | |
eeccdcac | 797 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
5fe9fe8c | 798 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
f49f0586 KG |
799 | } |
800 | ||
d4b8bb2a | 801 | static int i965_do_reset(struct drm_device *dev) |
0573ed4a | 802 | { |
5ccce180 | 803 | int ret; |
0573ed4a | 804 | |
ae681d96 CW |
805 | /* |
806 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
807 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
808 | * triggers the reset; when done, the hardware will clear it. | |
809 | */ | |
d4b8bb2a | 810 | pci_write_config_byte(dev->pdev, I965_GDRST, |
36c0cc61 | 811 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
5ccce180 DV |
812 | ret = wait_for(i965_reset_complete(dev), 500); |
813 | if (ret) | |
814 | return ret; | |
815 | ||
816 | /* We can't reset render&media without also resetting display ... */ | |
5ccce180 | 817 | pci_write_config_byte(dev->pdev, I965_GDRST, |
36c0cc61 | 818 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
0573ed4a | 819 | |
36c0cc61 DV |
820 | ret = wait_for(i965_reset_complete(dev), 500); |
821 | if (ret) | |
822 | return ret; | |
823 | ||
824 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); | |
825 | ||
826 | return 0; | |
0573ed4a KG |
827 | } |
828 | ||
d4b8bb2a | 829 | static int ironlake_do_reset(struct drm_device *dev) |
0573ed4a KG |
830 | { |
831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5ccce180 DV |
832 | u32 gdrst; |
833 | int ret; | |
834 | ||
835 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
8a5c2ae7 | 836 | gdrst &= ~GRDOM_MASK; |
5ccce180 DV |
837 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
838 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
839 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
840 | if (ret) | |
841 | return ret; | |
842 | ||
843 | /* We can't reset render&media without also resetting display ... */ | |
844 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
8a5c2ae7 | 845 | gdrst &= ~GRDOM_MASK; |
d4b8bb2a | 846 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
5ccce180 | 847 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
0573ed4a | 848 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
ba8bbcf6 JB |
849 | } |
850 | ||
d4b8bb2a | 851 | static int gen6_do_reset(struct drm_device *dev) |
cff458c2 EA |
852 | { |
853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b6e45f86 KP |
854 | int ret; |
855 | unsigned long irqflags; | |
cff458c2 | 856 | |
286fed41 KP |
857 | /* Hold gt_lock across reset to prevent any register access |
858 | * with forcewake not set correctly | |
859 | */ | |
b6e45f86 | 860 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
286fed41 KP |
861 | |
862 | /* Reset the chip */ | |
863 | ||
864 | /* GEN6_GDRST is not in the gt power well, no need to check | |
865 | * for fifo space for the write or forcewake the chip for | |
866 | * the read | |
867 | */ | |
868 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
869 | ||
870 | /* Spin waiting for the device to ack the reset request */ | |
871 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
872 | ||
873 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | |
b6e45f86 | 874 | if (dev_priv->forcewake_count) |
990bbdad | 875 | dev_priv->gt.force_wake_get(dev_priv); |
286fed41 | 876 | else |
990bbdad | 877 | dev_priv->gt.force_wake_put(dev_priv); |
286fed41 KP |
878 | |
879 | /* Restore fifo count */ | |
880 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
881 | ||
b6e45f86 KP |
882 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
883 | return ret; | |
cff458c2 EA |
884 | } |
885 | ||
8e96d9c4 | 886 | int intel_gpu_reset(struct drm_device *dev) |
350d2706 | 887 | { |
350d2706 DV |
888 | switch (INTEL_INFO(dev)->gen) { |
889 | case 7: | |
2e7c8ee7 CW |
890 | case 6: return gen6_do_reset(dev); |
891 | case 5: return ironlake_do_reset(dev); | |
892 | case 4: return i965_do_reset(dev); | |
893 | case 2: return i8xx_do_reset(dev); | |
894 | default: return -ENODEV; | |
350d2706 | 895 | } |
350d2706 DV |
896 | } |
897 | ||
11ed50ec | 898 | /** |
f3953dcb | 899 | * i915_reset - reset chip after a hang |
11ed50ec | 900 | * @dev: drm device to reset |
11ed50ec BG |
901 | * |
902 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
903 | * reset or otherwise an error code. | |
904 | * | |
905 | * Procedure is fairly simple: | |
906 | * - reset the chip using the reset reg | |
907 | * - re-init context state | |
908 | * - re-init hardware status page | |
909 | * - re-init ring buffer | |
910 | * - re-init interrupt state | |
911 | * - re-init display | |
912 | */ | |
d4b8bb2a | 913 | int i915_reset(struct drm_device *dev) |
11ed50ec BG |
914 | { |
915 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2e7c8ee7 | 916 | bool simulated; |
0573ed4a | 917 | int ret; |
11ed50ec | 918 | |
d78cb50b CW |
919 | if (!i915_try_reset) |
920 | return 0; | |
921 | ||
d54a02c0 | 922 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 923 | |
069efc1d | 924 | i915_gem_reset(dev); |
77f01230 | 925 | |
2e7c8ee7 CW |
926 | simulated = dev_priv->gpu_error.stop_rings != 0; |
927 | ||
928 | if (!simulated && get_seconds() - dev_priv->gpu_error.last_reset < 5) { | |
ae681d96 | 929 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
2e7c8ee7 CW |
930 | ret = -ENODEV; |
931 | } else { | |
d4b8bb2a | 932 | ret = intel_gpu_reset(dev); |
350d2706 | 933 | |
2e7c8ee7 CW |
934 | /* Also reset the gpu hangman. */ |
935 | if (simulated) { | |
936 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
937 | dev_priv->gpu_error.stop_rings = 0; | |
938 | if (ret == -ENODEV) { | |
939 | DRM_ERROR("Reset not implemented, but ignoring " | |
940 | "error for simulated gpu hangs\n"); | |
941 | ret = 0; | |
942 | } | |
943 | } else | |
944 | dev_priv->gpu_error.last_reset = get_seconds(); | |
945 | } | |
0573ed4a | 946 | if (ret) { |
f803aa55 | 947 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 948 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 949 | return ret; |
11ed50ec BG |
950 | } |
951 | ||
952 | /* Ok, now get things going again... */ | |
953 | ||
954 | /* | |
955 | * Everything depends on having the GTT running, so we need to start | |
956 | * there. Fortunately we don't need to do this unless we reset the | |
957 | * chip at a PCI level. | |
958 | * | |
959 | * Next we need to restore the context, but we don't use those | |
960 | * yet either... | |
961 | * | |
962 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
963 | * was running at the time of the reset (i.e. we weren't VT | |
964 | * switched away). | |
965 | */ | |
966 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 967 | !dev_priv->ums.mm_suspended) { |
b4519513 CW |
968 | struct intel_ring_buffer *ring; |
969 | int i; | |
970 | ||
db1b76ca | 971 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 972 | |
f691e2f4 DV |
973 | i915_gem_init_swizzling(dev); |
974 | ||
b4519513 CW |
975 | for_each_ring(ring, dev_priv, i) |
976 | ring->init(ring); | |
75a6898f | 977 | |
254f965c | 978 | i915_gem_context_init(dev); |
b7c36d25 BW |
979 | if (dev_priv->mm.aliasing_ppgtt) { |
980 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
981 | if (ret) | |
982 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
983 | } | |
e21af88d | 984 | |
8e88a2bd DV |
985 | /* |
986 | * It would make sense to re-init all the other hw state, at | |
987 | * least the rps/rc6/emon init done within modeset_init_hw. For | |
988 | * some unknown reason, this blows up my ilk, so don't. | |
989 | */ | |
f817586c | 990 | |
8e88a2bd | 991 | mutex_unlock(&dev->struct_mutex); |
f817586c | 992 | |
11ed50ec BG |
993 | drm_irq_uninstall(dev); |
994 | drm_irq_install(dev); | |
20afbda2 | 995 | intel_hpd_init(dev); |
bcbc324a DV |
996 | } else { |
997 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
998 | } |
999 | ||
11ed50ec BG |
1000 | return 0; |
1001 | } | |
1002 | ||
56550d94 | 1003 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 1004 | { |
01a06850 DV |
1005 | struct intel_device_info *intel_info = |
1006 | (struct intel_device_info *) ent->driver_data; | |
1007 | ||
5fe49d86 CW |
1008 | /* Only bind to function 0 of the device. Early generations |
1009 | * used function 1 as a placeholder for multi-head. This causes | |
1010 | * us confusion instead, especially on the systems where both | |
1011 | * functions have the same PCI-ID! | |
1012 | */ | |
1013 | if (PCI_FUNC(pdev->devfn)) | |
1014 | return -ENODEV; | |
1015 | ||
01a06850 DV |
1016 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
1017 | * implementation for gen3 (and only gen3) that used legacy drm maps | |
1018 | * (gasp!) to share buffers between X and the client. Hence we need to | |
1019 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ | |
1020 | if (intel_info->gen != 3) { | |
1021 | driver.driver_features &= | |
1022 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); | |
1023 | } else if (!intel_agp_enabled) { | |
1024 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
1025 | return -ENODEV; | |
1026 | } | |
1027 | ||
dcdb1674 | 1028 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
1029 | } |
1030 | ||
1031 | static void | |
1032 | i915_pci_remove(struct pci_dev *pdev) | |
1033 | { | |
1034 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1035 | ||
1036 | drm_put_dev(dev); | |
1037 | } | |
1038 | ||
84b79f8d | 1039 | static int i915_pm_suspend(struct device *dev) |
112b715e | 1040 | { |
84b79f8d RW |
1041 | struct pci_dev *pdev = to_pci_dev(dev); |
1042 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1043 | int error; | |
112b715e | 1044 | |
84b79f8d RW |
1045 | if (!drm_dev || !drm_dev->dev_private) { |
1046 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
1047 | return -ENODEV; | |
1048 | } | |
112b715e | 1049 | |
5bcf719b DA |
1050 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1051 | return 0; | |
1052 | ||
84b79f8d RW |
1053 | error = i915_drm_freeze(drm_dev); |
1054 | if (error) | |
1055 | return error; | |
112b715e | 1056 | |
84b79f8d RW |
1057 | pci_disable_device(pdev); |
1058 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 1059 | |
84b79f8d | 1060 | return 0; |
cbda12d7 ZW |
1061 | } |
1062 | ||
84b79f8d | 1063 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 1064 | { |
84b79f8d RW |
1065 | struct pci_dev *pdev = to_pci_dev(dev); |
1066 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1067 | ||
1068 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
1069 | } |
1070 | ||
84b79f8d | 1071 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 1072 | { |
84b79f8d RW |
1073 | struct pci_dev *pdev = to_pci_dev(dev); |
1074 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1075 | ||
1076 | if (!drm_dev || !drm_dev->dev_private) { | |
1077 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
1078 | return -ENODEV; | |
1079 | } | |
1080 | ||
1081 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
1082 | } |
1083 | ||
84b79f8d | 1084 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 1085 | { |
84b79f8d RW |
1086 | struct pci_dev *pdev = to_pci_dev(dev); |
1087 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1088 | ||
1089 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
1090 | } |
1091 | ||
84b79f8d | 1092 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 1093 | { |
84b79f8d RW |
1094 | struct pci_dev *pdev = to_pci_dev(dev); |
1095 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 1096 | |
61caf87c | 1097 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
1098 | } |
1099 | ||
b4b78d12 | 1100 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
1101 | .suspend = i915_pm_suspend, |
1102 | .resume = i915_pm_resume, | |
1103 | .freeze = i915_pm_freeze, | |
1104 | .thaw = i915_pm_thaw, | |
1105 | .poweroff = i915_pm_poweroff, | |
1106 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
1107 | }; |
1108 | ||
78b68556 | 1109 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1110 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1111 | .open = drm_gem_vm_open, |
1112 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1113 | }; |
1114 | ||
e08e96de AV |
1115 | static const struct file_operations i915_driver_fops = { |
1116 | .owner = THIS_MODULE, | |
1117 | .open = drm_open, | |
1118 | .release = drm_release, | |
1119 | .unlocked_ioctl = drm_ioctl, | |
1120 | .mmap = drm_gem_mmap, | |
1121 | .poll = drm_poll, | |
1122 | .fasync = drm_fasync, | |
1123 | .read = drm_read, | |
1124 | #ifdef CONFIG_COMPAT | |
1125 | .compat_ioctl = i915_compat_ioctl, | |
1126 | #endif | |
1127 | .llseek = noop_llseek, | |
1128 | }; | |
1129 | ||
1da177e4 | 1130 | static struct drm_driver driver = { |
0c54781b MW |
1131 | /* Don't use MTRRs here; the Xserver or userspace app should |
1132 | * deal with them for Intel hardware. | |
792d2b9a | 1133 | */ |
673a394b EA |
1134 | .driver_features = |
1135 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
1286ff73 | 1136 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME, |
22eae947 | 1137 | .load = i915_driver_load, |
ba8bbcf6 | 1138 | .unload = i915_driver_unload, |
673a394b | 1139 | .open = i915_driver_open, |
22eae947 DA |
1140 | .lastclose = i915_driver_lastclose, |
1141 | .preclose = i915_driver_preclose, | |
673a394b | 1142 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1143 | |
1144 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1145 | .suspend = i915_suspend, | |
1146 | .resume = i915_resume, | |
1147 | ||
cda17380 | 1148 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
1149 | .master_create = i915_master_create, |
1150 | .master_destroy = i915_master_destroy, | |
955b12de | 1151 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1152 | .debugfs_init = i915_debugfs_init, |
1153 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1154 | #endif |
673a394b EA |
1155 | .gem_init_object = i915_gem_init_object, |
1156 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 1157 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1158 | |
1159 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1160 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1161 | .gem_prime_export = i915_gem_prime_export, | |
1162 | .gem_prime_import = i915_gem_prime_import, | |
1163 | ||
ff72145b DA |
1164 | .dumb_create = i915_gem_dumb_create, |
1165 | .dumb_map_offset = i915_gem_mmap_gtt, | |
1166 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 | 1167 | .ioctls = i915_ioctls, |
e08e96de | 1168 | .fops = &i915_driver_fops, |
22eae947 DA |
1169 | .name = DRIVER_NAME, |
1170 | .desc = DRIVER_DESC, | |
1171 | .date = DRIVER_DATE, | |
1172 | .major = DRIVER_MAJOR, | |
1173 | .minor = DRIVER_MINOR, | |
1174 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1175 | }; |
1176 | ||
8410ea3b DA |
1177 | static struct pci_driver i915_pci_driver = { |
1178 | .name = DRIVER_NAME, | |
1179 | .id_table = pciidlist, | |
1180 | .probe = i915_pci_probe, | |
1181 | .remove = i915_pci_remove, | |
1182 | .driver.pm = &i915_pm_ops, | |
1183 | }; | |
1184 | ||
1da177e4 LT |
1185 | static int __init i915_init(void) |
1186 | { | |
1187 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1188 | |
1189 | /* | |
1190 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1191 | * explicitly disabled with the module pararmeter. | |
1192 | * | |
1193 | * Otherwise, just follow the parameter (defaulting to off). | |
1194 | * | |
1195 | * Allow optional vga_text_mode_force boot option to override | |
1196 | * the default behavior. | |
1197 | */ | |
1198 | #if defined(CONFIG_DRM_I915_KMS) | |
1199 | if (i915_modeset != 0) | |
1200 | driver.driver_features |= DRIVER_MODESET; | |
1201 | #endif | |
1202 | if (i915_modeset == 1) | |
1203 | driver.driver_features |= DRIVER_MODESET; | |
1204 | ||
1205 | #ifdef CONFIG_VGA_CONSOLE | |
1206 | if (vgacon_text_force() && i915_modeset == -1) | |
1207 | driver.driver_features &= ~DRIVER_MODESET; | |
1208 | #endif | |
1209 | ||
3885c6bb CW |
1210 | if (!(driver.driver_features & DRIVER_MODESET)) |
1211 | driver.get_vblank_timestamp = NULL; | |
1212 | ||
8410ea3b | 1213 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1214 | } |
1215 | ||
1216 | static void __exit i915_exit(void) | |
1217 | { | |
8410ea3b | 1218 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1219 | } |
1220 | ||
1221 | module_init(i915_init); | |
1222 | module_exit(i915_exit); | |
1223 | ||
b5e89ed5 DA |
1224 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1225 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1226 | MODULE_LICENSE("GPL and additional rights"); |
f7000883 | 1227 | |
b7d84096 JB |
1228 | /* We give fast paths for the really cool registers */ |
1229 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
b7884eb4 DV |
1230 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
1231 | ((reg) < 0x40000) && \ | |
1232 | ((reg) != FORCEWAKE)) | |
a8b1397d DV |
1233 | static void |
1234 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
1235 | { | |
ecdb4eb7 DL |
1236 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
1237 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
1238 | * hence harmless to write 0 into. */ | |
a8b1397d DV |
1239 | I915_WRITE_NOTRACE(MI_MODE, 0); |
1240 | } | |
1241 | ||
115bc2de PZ |
1242 | static void |
1243 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) | |
1244 | { | |
e76ebff8 | 1245 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
3f1e109a | 1246 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
115bc2de PZ |
1247 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
1248 | reg); | |
3f1e109a | 1249 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
115bc2de PZ |
1250 | } |
1251 | } | |
1252 | ||
1253 | static void | |
1254 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) | |
1255 | { | |
e76ebff8 | 1256 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
3f1e109a | 1257 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
115bc2de | 1258 | DRM_ERROR("Unclaimed write to %x\n", reg); |
3f1e109a | 1259 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
115bc2de PZ |
1260 | } |
1261 | } | |
1262 | ||
f7000883 AK |
1263 | #define __i915_read(x, y) \ |
1264 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
1265 | u##x val = 0; \ | |
a8b1397d DV |
1266 | if (IS_GEN5(dev_priv->dev)) \ |
1267 | ilk_dummy_write(dev_priv); \ | |
f7000883 | 1268 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
c937504e KP |
1269 | unsigned long irqflags; \ |
1270 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | |
1271 | if (dev_priv->forcewake_count == 0) \ | |
990bbdad | 1272 | dev_priv->gt.force_wake_get(dev_priv); \ |
f7000883 | 1273 | val = read##y(dev_priv->regs + reg); \ |
c937504e | 1274 | if (dev_priv->forcewake_count == 0) \ |
990bbdad | 1275 | dev_priv->gt.force_wake_put(dev_priv); \ |
c937504e | 1276 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
f7000883 AK |
1277 | } else { \ |
1278 | val = read##y(dev_priv->regs + reg); \ | |
1279 | } \ | |
1280 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | |
1281 | return val; \ | |
1282 | } | |
1283 | ||
1284 | __i915_read(8, b) | |
1285 | __i915_read(16, w) | |
1286 | __i915_read(32, l) | |
1287 | __i915_read(64, q) | |
1288 | #undef __i915_read | |
1289 | ||
1290 | #define __i915_write(x, y) \ | |
1291 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
67a3744f | 1292 | u32 __fifo_ret = 0; \ |
f7000883 AK |
1293 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1294 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
67a3744f | 1295 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
f7000883 | 1296 | } \ |
a8b1397d DV |
1297 | if (IS_GEN5(dev_priv->dev)) \ |
1298 | ilk_dummy_write(dev_priv); \ | |
115bc2de | 1299 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
fe31b574 | 1300 | write##y(val, dev_priv->regs + reg); \ |
67a3744f BW |
1301 | if (unlikely(__fifo_ret)) { \ |
1302 | gen6_gt_check_fifodbg(dev_priv); \ | |
1303 | } \ | |
115bc2de | 1304 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
f7000883 AK |
1305 | } |
1306 | __i915_write(8, b) | |
1307 | __i915_write(16, w) | |
1308 | __i915_write(32, l) | |
1309 | __i915_write(64, q) | |
1310 | #undef __i915_write | |
c0c7babc BW |
1311 | |
1312 | static const struct register_whitelist { | |
1313 | uint64_t offset; | |
1314 | uint32_t size; | |
1315 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ | |
1316 | } whitelist[] = { | |
1317 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, | |
1318 | }; | |
1319 | ||
1320 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1321 | void *data, struct drm_file *file) | |
1322 | { | |
1323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1324 | struct drm_i915_reg_read *reg = data; | |
1325 | struct register_whitelist const *entry = whitelist; | |
1326 | int i; | |
1327 | ||
1328 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
1329 | if (entry->offset == reg->offset && | |
1330 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | |
1331 | break; | |
1332 | } | |
1333 | ||
1334 | if (i == ARRAY_SIZE(whitelist)) | |
1335 | return -EINVAL; | |
1336 | ||
1337 | switch (entry->size) { | |
1338 | case 8: | |
1339 | reg->val = I915_READ64(reg->offset); | |
1340 | break; | |
1341 | case 4: | |
1342 | reg->val = I915_READ(reg->offset); | |
1343 | break; | |
1344 | case 2: | |
1345 | reg->val = I915_READ16(reg->offset); | |
1346 | break; | |
1347 | case 1: | |
1348 | reg->val = I915_READ8(reg->offset); | |
1349 | break; | |
1350 | default: | |
1351 | WARN_ON(1); | |
1352 | return -EINVAL; | |
1353 | } | |
1354 | ||
1355 | return 0; | |
1356 | } |