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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
354ff967 | 39 | #include "drm_crtc_helper.h" |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a35d9d3c | 50 | int i915_panel_ignore_lid __read_mostly = 0; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 BW |
52 | MODULE_PARM_DESC(panel_ignore_lid, |
53 | "Override lid status (0=autodetect [default], 1=lid open, " | |
54 | "-1=lid closed)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
a35d9d3c | 61 | unsigned int i915_semaphores __read_mostly = 0; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 BW |
63 | MODULE_PARM_DESC(semaphores, |
64 | "Use semaphores for inter-ring sync (default: false)"); | |
a1656b90 | 65 | |
a35d9d3c | 66 | unsigned int i915_enable_rc6 __read_mostly = 0; |
ac668088 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); |
6e96e775 BW |
68 | MODULE_PARM_DESC(i915_enable_rc6, |
69 | "Enable power-saving render C-state 6 (default: true)"); | |
ac668088 | 70 | |
4415e63b | 71 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 72 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
73 | MODULE_PARM_DESC(i915_enable_fbc, |
74 | "Enable frame buffer compression for power savings " | |
cd0de039 | 75 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 76 | |
a35d9d3c | 77 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 78 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
79 | MODULE_PARM_DESC(lvds_downclock, |
80 | "Use panel (LVDS/eDP) downclocking for power savings " | |
81 | "(default: false)"); | |
33814341 | 82 | |
4415e63b | 83 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 84 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
85 | MODULE_PARM_DESC(lvds_use_ssc, |
86 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 87 | "(default: auto from VBT)"); |
a7615030 | 88 | |
a35d9d3c | 89 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 90 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 BW |
91 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
92 | "Override selection of SDVO panel mode in the VBT " | |
93 | "(default: auto)"); | |
5a1e5b6c | 94 | |
a35d9d3c | 95 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 96 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 97 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 98 | |
a35d9d3c | 99 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 100 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
101 | MODULE_PARM_DESC(enable_hangcheck, |
102 | "Periodically check GPU activity for detecting hangs. " | |
103 | "WARNING: Disabling this can cause system wide hangs. " | |
104 | "(default: true)"); | |
3e0dc6b0 | 105 | |
112b715e | 106 | static struct drm_driver driver; |
1f7a6e37 | 107 | extern int intel_agp_enabled; |
112b715e | 108 | |
cfdf1fa2 | 109 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 110 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 111 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
112 | .vendor = 0x8086, \ |
113 | .device = id, \ | |
114 | .subvendor = PCI_ANY_ID, \ | |
115 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
116 | .driver_data = (unsigned long) info } |
117 | ||
9a7e8492 | 118 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 119 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 120 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
121 | }; |
122 | ||
9a7e8492 | 123 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 124 | .gen = 2, |
31578148 | 125 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
126 | }; |
127 | ||
9a7e8492 | 128 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 129 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 130 | .cursor_needs_physical = 1, |
31578148 | 131 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
132 | }; |
133 | ||
9a7e8492 | 134 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 135 | .gen = 2, |
31578148 | 136 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
137 | }; |
138 | ||
9a7e8492 | 139 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 140 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 141 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 142 | }; |
9a7e8492 | 143 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 144 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 145 | .cursor_needs_physical = 1, |
31578148 | 146 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 147 | .supports_tv = 1, |
cfdf1fa2 | 148 | }; |
9a7e8492 | 149 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 150 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 151 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 152 | }; |
9a7e8492 | 153 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 154 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 155 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 156 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 157 | .supports_tv = 1, |
cfdf1fa2 KH |
158 | }; |
159 | ||
9a7e8492 | 160 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 161 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 162 | .has_hotplug = 1, |
31578148 | 163 | .has_overlay = 1, |
cfdf1fa2 KH |
164 | }; |
165 | ||
9a7e8492 | 166 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 167 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 168 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 169 | .has_overlay = 1, |
a6c45cf0 | 170 | .supports_tv = 1, |
cfdf1fa2 KH |
171 | }; |
172 | ||
9a7e8492 | 173 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 174 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 175 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 176 | .has_overlay = 1, |
cfdf1fa2 KH |
177 | }; |
178 | ||
9a7e8492 | 179 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 180 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 181 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 182 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
183 | }; |
184 | ||
9a7e8492 | 185 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 186 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 187 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 188 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 189 | .supports_tv = 1, |
92f49d9c | 190 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
191 | }; |
192 | ||
9a7e8492 | 193 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 194 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 195 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 196 | .has_overlay = 1, |
cfdf1fa2 KH |
197 | }; |
198 | ||
9a7e8492 | 199 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 200 | .gen = 5, |
c96c3a8c | 201 | .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 202 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
203 | }; |
204 | ||
9a7e8492 | 205 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 206 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 207 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 208 | .has_fbc = 1, |
92f49d9c | 209 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
210 | }; |
211 | ||
9a7e8492 | 212 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 213 | .gen = 6, |
c96c3a8c | 214 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 215 | .has_bsd_ring = 1, |
549f7365 | 216 | .has_blt_ring = 1, |
f6e450a6 EA |
217 | }; |
218 | ||
9a7e8492 | 219 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 220 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 221 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 222 | .has_fbc = 1, |
881f47b6 | 223 | .has_bsd_ring = 1, |
549f7365 | 224 | .has_blt_ring = 1, |
a13e4093 EA |
225 | }; |
226 | ||
c76b615c JB |
227 | static const struct intel_device_info intel_ivybridge_d_info = { |
228 | .is_ivybridge = 1, .gen = 7, | |
229 | .need_gfx_hws = 1, .has_hotplug = 1, | |
230 | .has_bsd_ring = 1, | |
231 | .has_blt_ring = 1, | |
232 | }; | |
233 | ||
234 | static const struct intel_device_info intel_ivybridge_m_info = { | |
235 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, | |
236 | .need_gfx_hws = 1, .has_hotplug = 1, | |
237 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ | |
238 | .has_bsd_ring = 1, | |
239 | .has_blt_ring = 1, | |
240 | }; | |
241 | ||
6103da0d CW |
242 | static const struct pci_device_id pciidlist[] = { /* aka */ |
243 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
244 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
245 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 246 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
247 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
248 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
249 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
250 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
251 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
252 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
253 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
254 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
255 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
256 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
257 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
258 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
259 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
260 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
261 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
262 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
263 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
264 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
265 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
266 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
267 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
268 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 269 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
270 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
271 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
272 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
273 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 274 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
275 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
276 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 277 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 278 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 279 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 280 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
281 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
282 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
283 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
284 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
285 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
49ae35f2 | 286 | {0, 0, 0} |
1da177e4 LT |
287 | }; |
288 | ||
79e53945 JB |
289 | #if defined(CONFIG_DRM_I915_KMS) |
290 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
291 | #endif | |
292 | ||
3bad0781 | 293 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
90711d50 | 294 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
3bad0781 | 295 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
c792513b | 296 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
3bad0781 | 297 | |
0206e353 | 298 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
299 | { |
300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
301 | struct pci_dev *pch; | |
302 | ||
303 | /* | |
304 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
305 | * make graphics device passthrough work easy for VMM, that only | |
306 | * need to expose ISA bridge to let driver know the real hardware | |
307 | * underneath. This is a requirement from virtualization team. | |
308 | */ | |
309 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
310 | if (pch) { | |
311 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
312 | int id; | |
313 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
314 | ||
90711d50 JB |
315 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
316 | dev_priv->pch_type = PCH_IBX; | |
317 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
318 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
3bad0781 ZW |
319 | dev_priv->pch_type = PCH_CPT; |
320 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
c792513b JB |
321 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
322 | /* PantherPoint is CPT compatible */ | |
323 | dev_priv->pch_type = PCH_CPT; | |
324 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | |
3bad0781 ZW |
325 | } |
326 | } | |
327 | pci_dev_put(pch); | |
328 | } | |
329 | } | |
330 | ||
fcca7926 | 331 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
eb43f4af CW |
332 | { |
333 | int count; | |
334 | ||
335 | count = 0; | |
336 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
337 | udelay(10); | |
338 | ||
339 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
340 | POSTING_READ(FORCEWAKE); | |
341 | ||
342 | count = 0; | |
343 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) | |
344 | udelay(10); | |
345 | } | |
346 | ||
fcca7926 BW |
347 | /* |
348 | * Generally this is called implicitly by the register read function. However, | |
349 | * if some sequence requires the GT to not power down then this function should | |
350 | * be called at the beginning of the sequence followed by a call to | |
351 | * gen6_gt_force_wake_put() at the end of the sequence. | |
352 | */ | |
353 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
354 | { | |
355 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); | |
356 | ||
357 | /* Forcewake is atomic in case we get in here without the lock */ | |
358 | if (atomic_add_return(1, &dev_priv->forcewake_count) == 1) | |
359 | __gen6_gt_force_wake_get(dev_priv); | |
360 | } | |
361 | ||
362 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
eb43f4af CW |
363 | { |
364 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
365 | POSTING_READ(FORCEWAKE); | |
366 | } | |
367 | ||
fcca7926 BW |
368 | /* |
369 | * see gen6_gt_force_wake_get() | |
370 | */ | |
371 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
372 | { | |
373 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); | |
374 | ||
375 | if (atomic_dec_and_test(&dev_priv->forcewake_count)) | |
376 | __gen6_gt_force_wake_put(dev_priv); | |
377 | } | |
378 | ||
91355834 CW |
379 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
380 | { | |
0206e353 | 381 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
95736720 CW |
382 | int loop = 500; |
383 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
384 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { | |
385 | udelay(10); | |
386 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
387 | } | |
388 | WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES); | |
389 | dev_priv->gt_fifo_count = fifo; | |
91355834 | 390 | } |
95736720 | 391 | dev_priv->gt_fifo_count--; |
91355834 CW |
392 | } |
393 | ||
84b79f8d | 394 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 395 | { |
61caf87c RW |
396 | struct drm_i915_private *dev_priv = dev->dev_private; |
397 | ||
5bcf719b DA |
398 | drm_kms_helper_poll_disable(dev); |
399 | ||
ba8bbcf6 | 400 | pci_save_state(dev->pdev); |
ba8bbcf6 | 401 | |
5669fcac | 402 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 403 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
404 | int error = i915_gem_idle(dev); |
405 | if (error) { | |
226485e9 | 406 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
407 | "GEM idle failed, resume might fail\n"); |
408 | return error; | |
409 | } | |
226485e9 | 410 | drm_irq_uninstall(dev); |
5669fcac JB |
411 | } |
412 | ||
9e06dd39 JB |
413 | i915_save_state(dev); |
414 | ||
44834a67 | 415 | intel_opregion_fini(dev); |
8ee1c3db | 416 | |
84b79f8d RW |
417 | /* Modeset on resume, not lid events */ |
418 | dev_priv->modeset_on_lid = 0; | |
61caf87c RW |
419 | |
420 | return 0; | |
84b79f8d RW |
421 | } |
422 | ||
6a9ee8af | 423 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
424 | { |
425 | int error; | |
426 | ||
427 | if (!dev || !dev->dev_private) { | |
428 | DRM_ERROR("dev: %p\n", dev); | |
429 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
430 | return -ENODEV; | |
431 | } | |
432 | ||
433 | if (state.event == PM_EVENT_PRETHAW) | |
434 | return 0; | |
435 | ||
5bcf719b DA |
436 | |
437 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
438 | return 0; | |
6eecba33 | 439 | |
84b79f8d RW |
440 | error = i915_drm_freeze(dev); |
441 | if (error) | |
442 | return error; | |
443 | ||
b932ccb5 DA |
444 | if (state.event == PM_EVENT_SUSPEND) { |
445 | /* Shut down the device */ | |
446 | pci_disable_device(dev->pdev); | |
447 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
448 | } | |
ba8bbcf6 JB |
449 | |
450 | return 0; | |
451 | } | |
452 | ||
84b79f8d | 453 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 454 | { |
5669fcac | 455 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 456 | int error = 0; |
8ee1c3db | 457 | |
d1c3b177 CW |
458 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
459 | mutex_lock(&dev->struct_mutex); | |
460 | i915_gem_restore_gtt_mappings(dev); | |
461 | mutex_unlock(&dev->struct_mutex); | |
462 | } | |
463 | ||
61caf87c | 464 | i915_restore_state(dev); |
44834a67 | 465 | intel_opregion_setup(dev); |
61caf87c | 466 | |
5669fcac JB |
467 | /* KMS EnterVT equivalent */ |
468 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
469 | mutex_lock(&dev->struct_mutex); | |
470 | dev_priv->mm.suspended = 0; | |
471 | ||
84b79f8d | 472 | error = i915_gem_init_ringbuffer(dev); |
5669fcac | 473 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 474 | |
9fb526db KP |
475 | if (HAS_PCH_SPLIT(dev)) |
476 | ironlake_init_pch_refclk(dev); | |
477 | ||
500f7147 | 478 | drm_mode_config_reset(dev); |
226485e9 | 479 | drm_irq_install(dev); |
84b79f8d | 480 | |
354ff967 ZY |
481 | /* Resume the modeset for every activated CRTC */ |
482 | drm_helper_resume_force_mode(dev); | |
5669fcac | 483 | |
ac668088 | 484 | if (IS_IRONLAKE_M(dev)) |
d5bb081b JB |
485 | ironlake_enable_rc6(dev); |
486 | } | |
1daed3fb | 487 | |
44834a67 CW |
488 | intel_opregion_init(dev); |
489 | ||
c9354c85 | 490 | dev_priv->modeset_on_lid = 0; |
06891e27 | 491 | |
84b79f8d RW |
492 | return error; |
493 | } | |
494 | ||
6a9ee8af | 495 | int i915_resume(struct drm_device *dev) |
84b79f8d | 496 | { |
6eecba33 CW |
497 | int ret; |
498 | ||
5bcf719b DA |
499 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
500 | return 0; | |
501 | ||
84b79f8d RW |
502 | if (pci_enable_device(dev->pdev)) |
503 | return -EIO; | |
504 | ||
505 | pci_set_master(dev->pdev); | |
506 | ||
6eecba33 CW |
507 | ret = i915_drm_thaw(dev); |
508 | if (ret) | |
509 | return ret; | |
510 | ||
511 | drm_kms_helper_poll_enable(dev); | |
512 | return 0; | |
ba8bbcf6 JB |
513 | } |
514 | ||
dc96e9b8 CW |
515 | static int i8xx_do_reset(struct drm_device *dev, u8 flags) |
516 | { | |
517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
518 | ||
519 | if (IS_I85X(dev)) | |
520 | return -ENODEV; | |
521 | ||
522 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
523 | POSTING_READ(D_STATE); | |
524 | ||
525 | if (IS_I830(dev) || IS_845G(dev)) { | |
526 | I915_WRITE(DEBUG_RESET_I830, | |
527 | DEBUG_RESET_DISPLAY | | |
528 | DEBUG_RESET_RENDER | | |
529 | DEBUG_RESET_FULL); | |
530 | POSTING_READ(DEBUG_RESET_I830); | |
531 | msleep(1); | |
532 | ||
533 | I915_WRITE(DEBUG_RESET_I830, 0); | |
534 | POSTING_READ(DEBUG_RESET_I830); | |
535 | } | |
536 | ||
537 | msleep(1); | |
538 | ||
539 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
540 | POSTING_READ(D_STATE); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
f49f0586 KG |
545 | static int i965_reset_complete(struct drm_device *dev) |
546 | { | |
547 | u8 gdrst; | |
eeccdcac | 548 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
f49f0586 KG |
549 | return gdrst & 0x1; |
550 | } | |
551 | ||
0573ed4a KG |
552 | static int i965_do_reset(struct drm_device *dev, u8 flags) |
553 | { | |
554 | u8 gdrst; | |
555 | ||
ae681d96 CW |
556 | /* |
557 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
558 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
559 | * triggers the reset; when done, the hardware will clear it. | |
560 | */ | |
0573ed4a KG |
561 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
562 | pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1); | |
563 | ||
564 | return wait_for(i965_reset_complete(dev), 500); | |
565 | } | |
566 | ||
567 | static int ironlake_do_reset(struct drm_device *dev, u8 flags) | |
568 | { | |
569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
570 | u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
571 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); | |
572 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
ba8bbcf6 JB |
573 | } |
574 | ||
cff458c2 EA |
575 | static int gen6_do_reset(struct drm_device *dev, u8 flags) |
576 | { | |
577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
578 | ||
579 | I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
580 | return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
581 | } | |
582 | ||
11ed50ec BG |
583 | /** |
584 | * i965_reset - reset chip after a hang | |
585 | * @dev: drm device to reset | |
586 | * @flags: reset domains | |
587 | * | |
588 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
589 | * reset or otherwise an error code. | |
590 | * | |
591 | * Procedure is fairly simple: | |
592 | * - reset the chip using the reset reg | |
593 | * - re-init context state | |
594 | * - re-init hardware status page | |
595 | * - re-init ring buffer | |
596 | * - re-init interrupt state | |
597 | * - re-init display | |
598 | */ | |
f803aa55 | 599 | int i915_reset(struct drm_device *dev, u8 flags) |
11ed50ec BG |
600 | { |
601 | drm_i915_private_t *dev_priv = dev->dev_private; | |
11ed50ec BG |
602 | /* |
603 | * We really should only reset the display subsystem if we actually | |
604 | * need to | |
605 | */ | |
606 | bool need_display = true; | |
0573ed4a | 607 | int ret; |
11ed50ec | 608 | |
d78cb50b CW |
609 | if (!i915_try_reset) |
610 | return 0; | |
611 | ||
340479aa CW |
612 | if (!mutex_trylock(&dev->struct_mutex)) |
613 | return -EBUSY; | |
11ed50ec | 614 | |
069efc1d | 615 | i915_gem_reset(dev); |
77f01230 | 616 | |
f803aa55 | 617 | ret = -ENODEV; |
ae681d96 CW |
618 | if (get_seconds() - dev_priv->last_gpu_reset < 5) { |
619 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); | |
620 | } else switch (INTEL_INFO(dev)->gen) { | |
1083694a | 621 | case 7: |
cff458c2 EA |
622 | case 6: |
623 | ret = gen6_do_reset(dev, flags); | |
25732821 BW |
624 | /* If reset with a user forcewake, try to restore */ |
625 | if (atomic_read(&dev_priv->forcewake_count)) | |
626 | __gen6_gt_force_wake_get(dev_priv); | |
cff458c2 | 627 | break; |
f803aa55 | 628 | case 5: |
0573ed4a | 629 | ret = ironlake_do_reset(dev, flags); |
f803aa55 CW |
630 | break; |
631 | case 4: | |
0573ed4a | 632 | ret = i965_do_reset(dev, flags); |
f803aa55 | 633 | break; |
dc96e9b8 CW |
634 | case 2: |
635 | ret = i8xx_do_reset(dev, flags); | |
636 | break; | |
f803aa55 | 637 | } |
ae681d96 | 638 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 639 | if (ret) { |
f803aa55 | 640 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 641 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 642 | return ret; |
11ed50ec BG |
643 | } |
644 | ||
645 | /* Ok, now get things going again... */ | |
646 | ||
647 | /* | |
648 | * Everything depends on having the GTT running, so we need to start | |
649 | * there. Fortunately we don't need to do this unless we reset the | |
650 | * chip at a PCI level. | |
651 | * | |
652 | * Next we need to restore the context, but we don't use those | |
653 | * yet either... | |
654 | * | |
655 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
656 | * was running at the time of the reset (i.e. we weren't VT | |
657 | * switched away). | |
658 | */ | |
659 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 660 | !dev_priv->mm.suspended) { |
11ed50ec | 661 | dev_priv->mm.suspended = 0; |
75a6898f | 662 | |
1ec14ad3 | 663 | dev_priv->ring[RCS].init(&dev_priv->ring[RCS]); |
75a6898f | 664 | if (HAS_BSD(dev)) |
1ec14ad3 | 665 | dev_priv->ring[VCS].init(&dev_priv->ring[VCS]); |
75a6898f | 666 | if (HAS_BLT(dev)) |
1ec14ad3 | 667 | dev_priv->ring[BCS].init(&dev_priv->ring[BCS]); |
75a6898f | 668 | |
11ed50ec BG |
669 | mutex_unlock(&dev->struct_mutex); |
670 | drm_irq_uninstall(dev); | |
500f7147 | 671 | drm_mode_config_reset(dev); |
11ed50ec BG |
672 | drm_irq_install(dev); |
673 | mutex_lock(&dev->struct_mutex); | |
674 | } | |
675 | ||
9fd98141 CW |
676 | mutex_unlock(&dev->struct_mutex); |
677 | ||
11ed50ec | 678 | /* |
9fd98141 CW |
679 | * Perform a full modeset as on later generations, e.g. Ironlake, we may |
680 | * need to retrain the display link and cannot just restore the register | |
681 | * values. | |
11ed50ec | 682 | */ |
9fd98141 CW |
683 | if (need_display) { |
684 | mutex_lock(&dev->mode_config.mutex); | |
685 | drm_helper_resume_force_mode(dev); | |
686 | mutex_unlock(&dev->mode_config.mutex); | |
687 | } | |
11ed50ec | 688 | |
11ed50ec BG |
689 | return 0; |
690 | } | |
691 | ||
692 | ||
112b715e KH |
693 | static int __devinit |
694 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
695 | { | |
5fe49d86 CW |
696 | /* Only bind to function 0 of the device. Early generations |
697 | * used function 1 as a placeholder for multi-head. This causes | |
698 | * us confusion instead, especially on the systems where both | |
699 | * functions have the same PCI-ID! | |
700 | */ | |
701 | if (PCI_FUNC(pdev->devfn)) | |
702 | return -ENODEV; | |
703 | ||
dcdb1674 | 704 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
705 | } |
706 | ||
707 | static void | |
708 | i915_pci_remove(struct pci_dev *pdev) | |
709 | { | |
710 | struct drm_device *dev = pci_get_drvdata(pdev); | |
711 | ||
712 | drm_put_dev(dev); | |
713 | } | |
714 | ||
84b79f8d | 715 | static int i915_pm_suspend(struct device *dev) |
112b715e | 716 | { |
84b79f8d RW |
717 | struct pci_dev *pdev = to_pci_dev(dev); |
718 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
719 | int error; | |
112b715e | 720 | |
84b79f8d RW |
721 | if (!drm_dev || !drm_dev->dev_private) { |
722 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
723 | return -ENODEV; | |
724 | } | |
112b715e | 725 | |
5bcf719b DA |
726 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
727 | return 0; | |
728 | ||
84b79f8d RW |
729 | error = i915_drm_freeze(drm_dev); |
730 | if (error) | |
731 | return error; | |
112b715e | 732 | |
84b79f8d RW |
733 | pci_disable_device(pdev); |
734 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 735 | |
84b79f8d | 736 | return 0; |
cbda12d7 ZW |
737 | } |
738 | ||
84b79f8d | 739 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 740 | { |
84b79f8d RW |
741 | struct pci_dev *pdev = to_pci_dev(dev); |
742 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
743 | ||
744 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
745 | } |
746 | ||
84b79f8d | 747 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 748 | { |
84b79f8d RW |
749 | struct pci_dev *pdev = to_pci_dev(dev); |
750 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
751 | ||
752 | if (!drm_dev || !drm_dev->dev_private) { | |
753 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
754 | return -ENODEV; | |
755 | } | |
756 | ||
757 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
758 | } |
759 | ||
84b79f8d | 760 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 761 | { |
84b79f8d RW |
762 | struct pci_dev *pdev = to_pci_dev(dev); |
763 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
764 | ||
765 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
766 | } |
767 | ||
84b79f8d | 768 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 769 | { |
84b79f8d RW |
770 | struct pci_dev *pdev = to_pci_dev(dev); |
771 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 772 | |
61caf87c | 773 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
774 | } |
775 | ||
b4b78d12 | 776 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
777 | .suspend = i915_pm_suspend, |
778 | .resume = i915_pm_resume, | |
779 | .freeze = i915_pm_freeze, | |
780 | .thaw = i915_pm_thaw, | |
781 | .poweroff = i915_pm_poweroff, | |
782 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
783 | }; |
784 | ||
de151cf6 JB |
785 | static struct vm_operations_struct i915_gem_vm_ops = { |
786 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
787 | .open = drm_gem_vm_open, |
788 | .close = drm_gem_vm_close, | |
de151cf6 JB |
789 | }; |
790 | ||
1da177e4 | 791 | static struct drm_driver driver = { |
0c54781b MW |
792 | /* Don't use MTRRs here; the Xserver or userspace app should |
793 | * deal with them for Intel hardware. | |
792d2b9a | 794 | */ |
673a394b EA |
795 | .driver_features = |
796 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
797 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 798 | .load = i915_driver_load, |
ba8bbcf6 | 799 | .unload = i915_driver_unload, |
673a394b | 800 | .open = i915_driver_open, |
22eae947 DA |
801 | .lastclose = i915_driver_lastclose, |
802 | .preclose = i915_driver_preclose, | |
673a394b | 803 | .postclose = i915_driver_postclose, |
d8e29209 RW |
804 | |
805 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
806 | .suspend = i915_suspend, | |
807 | .resume = i915_resume, | |
808 | ||
cda17380 | 809 | .device_is_agp = i915_driver_device_is_agp, |
1da177e4 | 810 | .reclaim_buffers = drm_core_reclaim_buffers, |
7c1c2871 DA |
811 | .master_create = i915_master_create, |
812 | .master_destroy = i915_master_destroy, | |
955b12de | 813 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
814 | .debugfs_init = i915_debugfs_init, |
815 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 816 | #endif |
673a394b EA |
817 | .gem_init_object = i915_gem_init_object, |
818 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 819 | .gem_vm_ops = &i915_gem_vm_ops, |
ff72145b DA |
820 | .dumb_create = i915_gem_dumb_create, |
821 | .dumb_map_offset = i915_gem_mmap_gtt, | |
822 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 LT |
823 | .ioctls = i915_ioctls, |
824 | .fops = { | |
b5e89ed5 DA |
825 | .owner = THIS_MODULE, |
826 | .open = drm_open, | |
827 | .release = drm_release, | |
ed8b6704 | 828 | .unlocked_ioctl = drm_ioctl, |
de151cf6 | 829 | .mmap = drm_gem_mmap, |
b5e89ed5 DA |
830 | .poll = drm_poll, |
831 | .fasync = drm_fasync, | |
c9a9c5e0 | 832 | .read = drm_read, |
8ca7c1df | 833 | #ifdef CONFIG_COMPAT |
b5e89ed5 | 834 | .compat_ioctl = i915_compat_ioctl, |
8ca7c1df | 835 | #endif |
dc880abe | 836 | .llseek = noop_llseek, |
22eae947 DA |
837 | }, |
838 | ||
22eae947 DA |
839 | .name = DRIVER_NAME, |
840 | .desc = DRIVER_DESC, | |
841 | .date = DRIVER_DATE, | |
842 | .major = DRIVER_MAJOR, | |
843 | .minor = DRIVER_MINOR, | |
844 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
845 | }; |
846 | ||
8410ea3b DA |
847 | static struct pci_driver i915_pci_driver = { |
848 | .name = DRIVER_NAME, | |
849 | .id_table = pciidlist, | |
850 | .probe = i915_pci_probe, | |
851 | .remove = i915_pci_remove, | |
852 | .driver.pm = &i915_pm_ops, | |
853 | }; | |
854 | ||
1da177e4 LT |
855 | static int __init i915_init(void) |
856 | { | |
1f7a6e37 ZW |
857 | if (!intel_agp_enabled) { |
858 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
859 | return -ENODEV; | |
860 | } | |
861 | ||
1da177e4 | 862 | driver.num_ioctls = i915_max_ioctl; |
79e53945 JB |
863 | |
864 | /* | |
865 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
866 | * explicitly disabled with the module pararmeter. | |
867 | * | |
868 | * Otherwise, just follow the parameter (defaulting to off). | |
869 | * | |
870 | * Allow optional vga_text_mode_force boot option to override | |
871 | * the default behavior. | |
872 | */ | |
873 | #if defined(CONFIG_DRM_I915_KMS) | |
874 | if (i915_modeset != 0) | |
875 | driver.driver_features |= DRIVER_MODESET; | |
876 | #endif | |
877 | if (i915_modeset == 1) | |
878 | driver.driver_features |= DRIVER_MODESET; | |
879 | ||
880 | #ifdef CONFIG_VGA_CONSOLE | |
881 | if (vgacon_text_force() && i915_modeset == -1) | |
882 | driver.driver_features &= ~DRIVER_MODESET; | |
883 | #endif | |
884 | ||
3885c6bb CW |
885 | if (!(driver.driver_features & DRIVER_MODESET)) |
886 | driver.get_vblank_timestamp = NULL; | |
887 | ||
8410ea3b | 888 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
889 | } |
890 | ||
891 | static void __exit i915_exit(void) | |
892 | { | |
8410ea3b | 893 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
894 | } |
895 | ||
896 | module_init(i915_init); | |
897 | module_exit(i915_exit); | |
898 | ||
b5e89ed5 DA |
899 | MODULE_AUTHOR(DRIVER_AUTHOR); |
900 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 901 | MODULE_LICENSE("GPL and additional rights"); |
f7000883 AK |
902 | |
903 | /* We give fast paths for the really cool registers */ | |
904 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
905 | (((dev_priv)->info->gen >= 6) && \ | |
906 | ((reg) < 0x40000) && \ | |
907 | ((reg) != FORCEWAKE)) | |
908 | ||
909 | #define __i915_read(x, y) \ | |
910 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
911 | u##x val = 0; \ | |
912 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
913 | gen6_gt_force_wake_get(dev_priv); \ | |
914 | val = read##y(dev_priv->regs + reg); \ | |
915 | gen6_gt_force_wake_put(dev_priv); \ | |
916 | } else { \ | |
917 | val = read##y(dev_priv->regs + reg); \ | |
918 | } \ | |
919 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | |
920 | return val; \ | |
921 | } | |
922 | ||
923 | __i915_read(8, b) | |
924 | __i915_read(16, w) | |
925 | __i915_read(32, l) | |
926 | __i915_read(64, q) | |
927 | #undef __i915_read | |
928 | ||
929 | #define __i915_write(x, y) \ | |
930 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
931 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ | |
932 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
933 | __gen6_gt_wait_for_fifo(dev_priv); \ | |
934 | } \ | |
935 | write##y(val, dev_priv->regs + reg); \ | |
936 | } | |
937 | __i915_write(8, b) | |
938 | __i915_write(16, w) | |
939 | __i915_write(32, l) | |
940 | __i915_write(64, q) | |
941 | #undef __i915_write |