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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
112b715e KH |
41 | static struct drm_driver driver; |
42 | ||
a57c774a AK |
43 | #define GEN_DEFAULT_PIPEOFFSETS \ |
44 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
45 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
46 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
47 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
48 | .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \ | |
49 | .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \ | |
50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } | |
51 | ||
84fd4f4e RB |
52 | #define GEN_CHV_PIPEOFFSETS \ |
53 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
54 | CHV_PIPE_C_OFFSET }, \ | |
55 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
56 | CHV_TRANSCODER_C_OFFSET, }, \ | |
57 | .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \ | |
58 | CHV_DPLL_C_OFFSET }, \ | |
59 | .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \ | |
60 | CHV_DPLL_C_MD_OFFSET }, \ | |
61 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ | |
62 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 63 | |
5efb3e28 VS |
64 | #define CURSOR_OFFSETS \ |
65 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
66 | ||
67 | #define IVB_CURSOR_OFFSETS \ | |
68 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
69 | ||
9a7e8492 | 70 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 71 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 72 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 73 | .ring_mask = RENDER_RING, |
a57c774a | 74 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 75 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
76 | }; |
77 | ||
9a7e8492 | 78 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 79 | .gen = 2, .num_pipes = 1, |
31578148 | 80 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 81 | .ring_mask = RENDER_RING, |
a57c774a | 82 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 83 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
84 | }; |
85 | ||
9a7e8492 | 86 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 87 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 88 | .cursor_needs_physical = 1, |
31578148 | 89 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 90 | .has_fbc = 1, |
73ae478c | 91 | .ring_mask = RENDER_RING, |
a57c774a | 92 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 93 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
94 | }; |
95 | ||
9a7e8492 | 96 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 97 | .gen = 2, .num_pipes = 1, |
31578148 | 98 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 99 | .ring_mask = RENDER_RING, |
a57c774a | 100 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 101 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
102 | }; |
103 | ||
9a7e8492 | 104 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 105 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 106 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 107 | .ring_mask = RENDER_RING, |
a57c774a | 108 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 109 | CURSOR_OFFSETS, |
cfdf1fa2 | 110 | }; |
9a7e8492 | 111 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 112 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 113 | .cursor_needs_physical = 1, |
31578148 | 114 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 115 | .supports_tv = 1, |
fd70d52a | 116 | .has_fbc = 1, |
73ae478c | 117 | .ring_mask = RENDER_RING, |
a57c774a | 118 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 119 | CURSOR_OFFSETS, |
cfdf1fa2 | 120 | }; |
9a7e8492 | 121 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 122 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 123 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 124 | .ring_mask = RENDER_RING, |
a57c774a | 125 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 126 | CURSOR_OFFSETS, |
cfdf1fa2 | 127 | }; |
9a7e8492 | 128 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 129 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 130 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 131 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 132 | .supports_tv = 1, |
fd70d52a | 133 | .has_fbc = 1, |
73ae478c | 134 | .ring_mask = RENDER_RING, |
a57c774a | 135 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 136 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
137 | }; |
138 | ||
9a7e8492 | 139 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 140 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 141 | .has_hotplug = 1, |
31578148 | 142 | .has_overlay = 1, |
73ae478c | 143 | .ring_mask = RENDER_RING, |
a57c774a | 144 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 145 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
146 | }; |
147 | ||
9a7e8492 | 148 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 149 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 150 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 151 | .has_overlay = 1, |
a6c45cf0 | 152 | .supports_tv = 1, |
73ae478c | 153 | .ring_mask = RENDER_RING, |
a57c774a | 154 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 155 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
156 | }; |
157 | ||
9a7e8492 | 158 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 159 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 160 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 161 | .has_overlay = 1, |
73ae478c | 162 | .ring_mask = RENDER_RING, |
a57c774a | 163 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 164 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
165 | }; |
166 | ||
9a7e8492 | 167 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 168 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 169 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 170 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 171 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 172 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
173 | }; |
174 | ||
9a7e8492 | 175 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 176 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 177 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 178 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 179 | .supports_tv = 1, |
73ae478c | 180 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 181 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 182 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
183 | }; |
184 | ||
9a7e8492 | 185 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 186 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 187 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 188 | .has_overlay = 1, |
a57c774a | 189 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 190 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
191 | }; |
192 | ||
9a7e8492 | 193 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 194 | .gen = 5, .num_pipes = 2, |
5a117db7 | 195 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 196 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 197 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 198 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
199 | }; |
200 | ||
9a7e8492 | 201 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 202 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 203 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 204 | .has_fbc = 1, |
73ae478c | 205 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 206 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 207 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
208 | }; |
209 | ||
9a7e8492 | 210 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 211 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 212 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 213 | .has_fbc = 1, |
73ae478c | 214 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 215 | .has_llc = 1, |
a57c774a | 216 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 217 | CURSOR_OFFSETS, |
f6e450a6 EA |
218 | }; |
219 | ||
9a7e8492 | 220 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 221 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 222 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 223 | .has_fbc = 1, |
73ae478c | 224 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 225 | .has_llc = 1, |
a57c774a | 226 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 227 | CURSOR_OFFSETS, |
a13e4093 EA |
228 | }; |
229 | ||
219f4fdb BW |
230 | #define GEN7_FEATURES \ |
231 | .gen = 7, .num_pipes = 3, \ | |
232 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 233 | .has_fbc = 1, \ |
73ae478c | 234 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 235 | .has_llc = 1 |
219f4fdb | 236 | |
c76b615c | 237 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
238 | GEN7_FEATURES, |
239 | .is_ivybridge = 1, | |
a57c774a | 240 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 241 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
242 | }; |
243 | ||
244 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
245 | GEN7_FEATURES, |
246 | .is_ivybridge = 1, | |
247 | .is_mobile = 1, | |
a57c774a | 248 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 249 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
250 | }; |
251 | ||
999bcdea BW |
252 | static const struct intel_device_info intel_ivybridge_q_info = { |
253 | GEN7_FEATURES, | |
254 | .is_ivybridge = 1, | |
255 | .num_pipes = 0, /* legal, last one wins */ | |
a57c774a | 256 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 257 | IVB_CURSOR_OFFSETS, |
999bcdea BW |
258 | }; |
259 | ||
70a3eb7a | 260 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
261 | GEN7_FEATURES, |
262 | .is_mobile = 1, | |
263 | .num_pipes = 2, | |
70a3eb7a | 264 | .is_valleyview = 1, |
fba5d532 | 265 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 266 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 267 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 268 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 269 | CURSOR_OFFSETS, |
70a3eb7a JB |
270 | }; |
271 | ||
272 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
273 | GEN7_FEATURES, |
274 | .num_pipes = 2, | |
70a3eb7a | 275 | .is_valleyview = 1, |
fba5d532 | 276 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 277 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 278 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 279 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 280 | CURSOR_OFFSETS, |
70a3eb7a JB |
281 | }; |
282 | ||
4cae9ae0 | 283 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
284 | GEN7_FEATURES, |
285 | .is_haswell = 1, | |
dd93be58 | 286 | .has_ddi = 1, |
30568c45 | 287 | .has_fpga_dbg = 1, |
73ae478c | 288 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 289 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 290 | IVB_CURSOR_OFFSETS, |
4cae9ae0 ED |
291 | }; |
292 | ||
293 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
294 | GEN7_FEATURES, |
295 | .is_haswell = 1, | |
296 | .is_mobile = 1, | |
dd93be58 | 297 | .has_ddi = 1, |
30568c45 | 298 | .has_fpga_dbg = 1, |
73ae478c | 299 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 300 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 301 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
302 | }; |
303 | ||
4d4dead6 | 304 | static const struct intel_device_info intel_broadwell_d_info = { |
4b30553d | 305 | .gen = 8, .num_pipes = 3, |
4d4dead6 BW |
306 | .need_gfx_hws = 1, .has_hotplug = 1, |
307 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
308 | .has_llc = 1, | |
309 | .has_ddi = 1, | |
8f94d24b | 310 | .has_fbc = 1, |
a57c774a | 311 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 312 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
313 | }; |
314 | ||
315 | static const struct intel_device_info intel_broadwell_m_info = { | |
4b30553d | 316 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
4d4dead6 BW |
317 | .need_gfx_hws = 1, .has_hotplug = 1, |
318 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
319 | .has_llc = 1, | |
320 | .has_ddi = 1, | |
8f94d24b | 321 | .has_fbc = 1, |
a57c774a | 322 | GEN_DEFAULT_PIPEOFFSETS, |
4d4dead6 BW |
323 | }; |
324 | ||
fd3c269f ZY |
325 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
326 | .gen = 8, .num_pipes = 3, | |
327 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 328 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
329 | .has_llc = 1, |
330 | .has_ddi = 1, | |
331 | .has_fbc = 1, | |
332 | GEN_DEFAULT_PIPEOFFSETS, | |
333 | }; | |
334 | ||
335 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
336 | .gen = 8, .is_mobile = 1, .num_pipes = 3, | |
337 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 338 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
339 | .has_llc = 1, |
340 | .has_ddi = 1, | |
341 | .has_fbc = 1, | |
342 | GEN_DEFAULT_PIPEOFFSETS, | |
5efb3e28 | 343 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
344 | }; |
345 | ||
7d87a7f7 VS |
346 | static const struct intel_device_info intel_cherryview_info = { |
347 | .is_preliminary = 1, | |
07fddb14 | 348 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
349 | .need_gfx_hws = 1, .has_hotplug = 1, |
350 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
351 | .is_valleyview = 1, | |
352 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
84fd4f4e | 353 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 354 | CURSOR_OFFSETS, |
7d87a7f7 VS |
355 | }; |
356 | ||
a0a18075 JB |
357 | /* |
358 | * Make sure any device matches here are from most specific to most | |
359 | * general. For example, since the Quanta match is based on the subsystem | |
360 | * and subvendor IDs, we need it to come before the more general IVB | |
361 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
362 | */ | |
363 | #define INTEL_PCI_IDS \ | |
364 | INTEL_I830_IDS(&intel_i830_info), \ | |
365 | INTEL_I845G_IDS(&intel_845g_info), \ | |
366 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
367 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
368 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
369 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
370 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
371 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
372 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
373 | INTEL_G33_IDS(&intel_g33_info), \ | |
374 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
375 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
376 | INTEL_G45_IDS(&intel_g45_info), \ | |
377 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
378 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
379 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
380 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
381 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
382 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
383 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
384 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
385 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
386 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
387 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
4d4dead6 | 388 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ |
fd3c269f ZY |
389 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ |
390 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ | |
391 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ | |
7d87a7f7 VS |
392 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \ |
393 | INTEL_CHV_IDS(&intel_cherryview_info) | |
a0a18075 | 394 | |
6103da0d | 395 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 396 | INTEL_PCI_IDS, |
49ae35f2 | 397 | {0, 0, 0} |
1da177e4 LT |
398 | }; |
399 | ||
79e53945 JB |
400 | #if defined(CONFIG_DRM_I915_KMS) |
401 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
402 | #endif | |
403 | ||
0206e353 | 404 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
405 | { |
406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 407 | struct pci_dev *pch = NULL; |
3bad0781 | 408 | |
ce1bb329 BW |
409 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
410 | * (which really amounts to a PCH but no South Display). | |
411 | */ | |
412 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
413 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
414 | return; |
415 | } | |
416 | ||
3bad0781 ZW |
417 | /* |
418 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
419 | * make graphics device passthrough work easy for VMM, that only | |
420 | * need to expose ISA bridge to let driver know the real hardware | |
421 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
422 | * |
423 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
424 | * ISA bridge in the system. To work reliably, we should scan trhough | |
425 | * all the ISA bridge devices and check for the first match, instead | |
426 | * of only checking the first one. | |
3bad0781 | 427 | */ |
bcdb72ac | 428 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 429 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 430 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 431 | dev_priv->pch_id = id; |
3bad0781 | 432 | |
90711d50 JB |
433 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
434 | dev_priv->pch_type = PCH_IBX; | |
435 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 436 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 437 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
438 | dev_priv->pch_type = PCH_CPT; |
439 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 440 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
441 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
442 | /* PantherPoint is CPT compatible */ | |
443 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 444 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 445 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
446 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
447 | dev_priv->pch_type = PCH_LPT; | |
448 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 449 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 450 | WARN_ON(IS_ULT(dev)); |
018f52c9 PZ |
451 | } else if (IS_BROADWELL(dev)) { |
452 | dev_priv->pch_type = PCH_LPT; | |
453 | dev_priv->pch_id = | |
454 | INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
455 | DRM_DEBUG_KMS("This is Broadwell, assuming " | |
456 | "LynxPoint LP PCH\n"); | |
e76e0634 BW |
457 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
458 | dev_priv->pch_type = PCH_LPT; | |
459 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
460 | WARN_ON(!IS_HASWELL(dev)); | |
461 | WARN_ON(!IS_ULT(dev)); | |
bcdb72ac ID |
462 | } else |
463 | continue; | |
464 | ||
6a9c4b35 | 465 | break; |
3bad0781 | 466 | } |
3bad0781 | 467 | } |
6a9c4b35 | 468 | if (!pch) |
bcdb72ac ID |
469 | DRM_DEBUG_KMS("No PCH found.\n"); |
470 | ||
471 | pci_dev_put(pch); | |
3bad0781 ZW |
472 | } |
473 | ||
2911a35b BW |
474 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
475 | { | |
476 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 477 | return false; |
2911a35b | 478 | |
d330a953 JN |
479 | if (i915.semaphores >= 0) |
480 | return i915.semaphores; | |
2911a35b | 481 | |
c923facd JN |
482 | /* Until we get further testing... */ |
483 | if (IS_GEN8(dev)) | |
484 | return false; | |
485 | ||
59de3295 | 486 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 487 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
488 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
489 | return false; | |
490 | #endif | |
2911a35b | 491 | |
a08acaf2 | 492 | return true; |
2911a35b BW |
493 | } |
494 | ||
84b79f8d | 495 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 496 | { |
61caf87c | 497 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 498 | struct drm_crtc *crtc; |
61caf87c | 499 | |
8a187455 PZ |
500 | intel_runtime_pm_get(dev_priv); |
501 | ||
b8efb17b ZR |
502 | /* ignore lid events during suspend */ |
503 | mutex_lock(&dev_priv->modeset_restore_lock); | |
504 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
505 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
506 | ||
c67a470b PZ |
507 | /* We do a lot of poking in a lot of registers, make sure they work |
508 | * properly. */ | |
da7e29bd | 509 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 510 | |
5bcf719b DA |
511 | drm_kms_helper_poll_disable(dev); |
512 | ||
ba8bbcf6 | 513 | pci_save_state(dev->pdev); |
ba8bbcf6 | 514 | |
5669fcac | 515 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 516 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
517 | int error; |
518 | ||
45c5f202 | 519 | error = i915_gem_suspend(dev); |
84b79f8d | 520 | if (error) { |
226485e9 | 521 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
522 | "GEM idle failed, resume might fail\n"); |
523 | return error; | |
524 | } | |
a261b246 | 525 | |
1a01ab3b JB |
526 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
527 | ||
226485e9 | 528 | drm_irq_uninstall(dev); |
15239099 | 529 | dev_priv->enable_hotplug_processing = false; |
24576d23 JB |
530 | /* |
531 | * Disable CRTCs directly since we want to preserve sw state | |
532 | * for _thaw. | |
533 | */ | |
7c063c72 | 534 | mutex_lock(&dev->mode_config.mutex); |
f7ef3fa7 CW |
535 | for_each_crtc(dev, crtc) { |
536 | mutex_lock(&crtc->mutex); | |
24576d23 | 537 | dev_priv->display.crtc_disable(crtc); |
f7ef3fa7 CW |
538 | mutex_unlock(&crtc->mutex); |
539 | } | |
7c063c72 | 540 | mutex_unlock(&dev->mode_config.mutex); |
7d708ee4 ID |
541 | |
542 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
543 | } |
544 | ||
828c7908 BW |
545 | i915_gem_suspend_gtt_mappings(dev); |
546 | ||
9e06dd39 JB |
547 | i915_save_state(dev); |
548 | ||
44834a67 | 549 | intel_opregion_fini(dev); |
28d85cd3 | 550 | intel_uncore_fini(dev); |
8ee1c3db | 551 | |
3fa016a0 | 552 | console_lock(); |
b6f3eff7 | 553 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
554 | console_unlock(); |
555 | ||
62d5d69b MK |
556 | dev_priv->suspend_count++; |
557 | ||
61caf87c | 558 | return 0; |
84b79f8d RW |
559 | } |
560 | ||
6a9ee8af | 561 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
562 | { |
563 | int error; | |
564 | ||
565 | if (!dev || !dev->dev_private) { | |
566 | DRM_ERROR("dev: %p\n", dev); | |
567 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
568 | return -ENODEV; | |
569 | } | |
570 | ||
571 | if (state.event == PM_EVENT_PRETHAW) | |
572 | return 0; | |
573 | ||
5bcf719b DA |
574 | |
575 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
576 | return 0; | |
6eecba33 | 577 | |
84b79f8d RW |
578 | error = i915_drm_freeze(dev); |
579 | if (error) | |
580 | return error; | |
581 | ||
b932ccb5 DA |
582 | if (state.event == PM_EVENT_SUSPEND) { |
583 | /* Shut down the device */ | |
584 | pci_disable_device(dev->pdev); | |
585 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
586 | } | |
ba8bbcf6 JB |
587 | |
588 | return 0; | |
589 | } | |
590 | ||
073f34d9 JB |
591 | void intel_console_resume(struct work_struct *work) |
592 | { | |
593 | struct drm_i915_private *dev_priv = | |
594 | container_of(work, struct drm_i915_private, | |
595 | console_resume_work); | |
596 | struct drm_device *dev = dev_priv->dev; | |
597 | ||
598 | console_lock(); | |
b6f3eff7 | 599 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
600 | console_unlock(); |
601 | } | |
602 | ||
76c4b250 | 603 | static int i915_drm_thaw_early(struct drm_device *dev) |
ba8bbcf6 | 604 | { |
5669fcac | 605 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ee1c3db | 606 | |
c9f7fbf9 | 607 | intel_uncore_early_sanitize(dev); |
9d49c0ef | 608 | intel_uncore_sanitize(dev); |
76c4b250 ID |
609 | intel_power_domains_init_hw(dev_priv); |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
614 | static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) | |
615 | { | |
616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9d49c0ef PZ |
617 | |
618 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
619 | restore_gtt_mappings) { | |
620 | mutex_lock(&dev->struct_mutex); | |
621 | i915_gem_restore_gtt_mappings(dev); | |
622 | mutex_unlock(&dev->struct_mutex); | |
623 | } | |
624 | ||
61caf87c | 625 | i915_restore_state(dev); |
44834a67 | 626 | intel_opregion_setup(dev); |
61caf87c | 627 | |
5669fcac JB |
628 | /* KMS EnterVT equivalent */ |
629 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 630 | intel_init_pch_refclk(dev); |
754970ee | 631 | drm_mode_config_reset(dev); |
1833b134 | 632 | |
5669fcac | 633 | mutex_lock(&dev->struct_mutex); |
074c6ada CW |
634 | if (i915_gem_init_hw(dev)) { |
635 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
636 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
637 | } | |
5669fcac | 638 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 639 | |
15239099 | 640 | /* We need working interrupts for modeset enabling ... */ |
bb0f1b5c | 641 | drm_irq_install(dev, dev->pdev->irq); |
15239099 | 642 | |
1833b134 | 643 | intel_modeset_init_hw(dev); |
24576d23 JB |
644 | |
645 | drm_modeset_lock_all(dev); | |
646 | intel_modeset_setup_hw_state(dev, true); | |
647 | drm_modeset_unlock_all(dev); | |
15239099 DV |
648 | |
649 | /* | |
650 | * ... but also need to make sure that hotplug processing | |
651 | * doesn't cause havoc. Like in the driver load code we don't | |
652 | * bother with the tiny race here where we might loose hotplug | |
653 | * notifications. | |
654 | * */ | |
20afbda2 | 655 | intel_hpd_init(dev); |
15239099 | 656 | dev_priv->enable_hotplug_processing = true; |
bb60b969 | 657 | /* Config may have changed between suspend and resume */ |
1ff74cf1 | 658 | drm_helper_hpd_irq_event(dev); |
d5bb081b | 659 | } |
1daed3fb | 660 | |
44834a67 CW |
661 | intel_opregion_init(dev); |
662 | ||
073f34d9 JB |
663 | /* |
664 | * The console lock can be pretty contented on resume due | |
665 | * to all the printk activity. Try to keep it out of the hot | |
666 | * path of resume if possible. | |
667 | */ | |
668 | if (console_trylock()) { | |
b6f3eff7 | 669 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
670 | console_unlock(); |
671 | } else { | |
672 | schedule_work(&dev_priv->console_resume_work); | |
673 | } | |
674 | ||
b8efb17b ZR |
675 | mutex_lock(&dev_priv->modeset_restore_lock); |
676 | dev_priv->modeset_restore = MODESET_DONE; | |
677 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 PZ |
678 | |
679 | intel_runtime_pm_put(dev_priv); | |
074c6ada | 680 | return 0; |
84b79f8d RW |
681 | } |
682 | ||
1abd02e2 JB |
683 | static int i915_drm_thaw(struct drm_device *dev) |
684 | { | |
7f16e5c1 | 685 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
828c7908 | 686 | i915_check_and_clear_faults(dev); |
1abd02e2 | 687 | |
9d49c0ef | 688 | return __i915_drm_thaw(dev, true); |
84b79f8d RW |
689 | } |
690 | ||
76c4b250 | 691 | static int i915_resume_early(struct drm_device *dev) |
84b79f8d | 692 | { |
5bcf719b DA |
693 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
694 | return 0; | |
695 | ||
76c4b250 ID |
696 | /* |
697 | * We have a resume ordering issue with the snd-hda driver also | |
698 | * requiring our device to be power up. Due to the lack of a | |
699 | * parent/child relationship we currently solve this with an early | |
700 | * resume hook. | |
701 | * | |
702 | * FIXME: This should be solved with a special hdmi sink device or | |
703 | * similar so that power domains can be employed. | |
704 | */ | |
84b79f8d RW |
705 | if (pci_enable_device(dev->pdev)) |
706 | return -EIO; | |
707 | ||
708 | pci_set_master(dev->pdev); | |
709 | ||
76c4b250 ID |
710 | return i915_drm_thaw_early(dev); |
711 | } | |
712 | ||
713 | int i915_resume(struct drm_device *dev) | |
714 | { | |
715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
716 | int ret; | |
717 | ||
1abd02e2 JB |
718 | /* |
719 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
9d49c0ef PZ |
720 | * earlier) need to restore the GTT mappings since the BIOS might clear |
721 | * all our scratch PTEs. | |
1abd02e2 | 722 | */ |
9d49c0ef | 723 | ret = __i915_drm_thaw(dev, !dev_priv->opregion.header); |
6eecba33 CW |
724 | if (ret) |
725 | return ret; | |
726 | ||
727 | drm_kms_helper_poll_enable(dev); | |
728 | return 0; | |
ba8bbcf6 JB |
729 | } |
730 | ||
76c4b250 ID |
731 | static int i915_resume_legacy(struct drm_device *dev) |
732 | { | |
733 | i915_resume_early(dev); | |
734 | i915_resume(dev); | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
11ed50ec | 739 | /** |
f3953dcb | 740 | * i915_reset - reset chip after a hang |
11ed50ec | 741 | * @dev: drm device to reset |
11ed50ec BG |
742 | * |
743 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
744 | * reset or otherwise an error code. | |
745 | * | |
746 | * Procedure is fairly simple: | |
747 | * - reset the chip using the reset reg | |
748 | * - re-init context state | |
749 | * - re-init hardware status page | |
750 | * - re-init ring buffer | |
751 | * - re-init interrupt state | |
752 | * - re-init display | |
753 | */ | |
d4b8bb2a | 754 | int i915_reset(struct drm_device *dev) |
11ed50ec | 755 | { |
50227e1c | 756 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 757 | bool simulated; |
0573ed4a | 758 | int ret; |
11ed50ec | 759 | |
d330a953 | 760 | if (!i915.reset) |
d78cb50b CW |
761 | return 0; |
762 | ||
d54a02c0 | 763 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 764 | |
069efc1d | 765 | i915_gem_reset(dev); |
77f01230 | 766 | |
2e7c8ee7 CW |
767 | simulated = dev_priv->gpu_error.stop_rings != 0; |
768 | ||
be62acb4 MK |
769 | ret = intel_gpu_reset(dev); |
770 | ||
771 | /* Also reset the gpu hangman. */ | |
772 | if (simulated) { | |
773 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
774 | dev_priv->gpu_error.stop_rings = 0; | |
775 | if (ret == -ENODEV) { | |
f2d91a2c DV |
776 | DRM_INFO("Reset not implemented, but ignoring " |
777 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
778 | ret = 0; |
779 | } | |
2e7c8ee7 | 780 | } |
be62acb4 | 781 | |
0573ed4a | 782 | if (ret) { |
f2d91a2c | 783 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 784 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 785 | return ret; |
11ed50ec BG |
786 | } |
787 | ||
788 | /* Ok, now get things going again... */ | |
789 | ||
790 | /* | |
791 | * Everything depends on having the GTT running, so we need to start | |
792 | * there. Fortunately we don't need to do this unless we reset the | |
793 | * chip at a PCI level. | |
794 | * | |
795 | * Next we need to restore the context, but we don't use those | |
796 | * yet either... | |
797 | * | |
798 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
799 | * was running at the time of the reset (i.e. we weren't VT | |
800 | * switched away). | |
801 | */ | |
802 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 803 | !dev_priv->ums.mm_suspended) { |
db1b76ca | 804 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 805 | |
3d57e5bd | 806 | ret = i915_gem_init_hw(dev); |
8e88a2bd | 807 | mutex_unlock(&dev->struct_mutex); |
3d57e5bd BW |
808 | if (ret) { |
809 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
810 | return ret; | |
811 | } | |
f817586c | 812 | |
e090c53b DV |
813 | /* |
814 | * FIXME: This is horribly race against concurrent pageflip and | |
815 | * vblank wait ioctls since they can observe dev->irqs_disabled | |
816 | * being false when they shouldn't be able to. | |
817 | */ | |
11ed50ec | 818 | drm_irq_uninstall(dev); |
bb0f1b5c | 819 | drm_irq_install(dev, dev->pdev->irq); |
dd0a1aa1 JM |
820 | |
821 | /* rps/rc6 re-init is necessary to restore state lost after the | |
822 | * reset and the re-install of drm irq. Skip for ironlake per | |
823 | * previous concerns that it doesn't respond well to some forms | |
824 | * of re-init after reset. */ | |
dc1d0136 | 825 | if (INTEL_INFO(dev)->gen > 5) |
c6df39b5 | 826 | intel_reset_gt_powersave(dev); |
dd0a1aa1 | 827 | |
20afbda2 | 828 | intel_hpd_init(dev); |
bcbc324a DV |
829 | } else { |
830 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
831 | } |
832 | ||
11ed50ec BG |
833 | return 0; |
834 | } | |
835 | ||
56550d94 | 836 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 837 | { |
01a06850 DV |
838 | struct intel_device_info *intel_info = |
839 | (struct intel_device_info *) ent->driver_data; | |
840 | ||
d330a953 | 841 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
842 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
843 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
844 | return -ENODEV; | |
845 | } | |
846 | ||
5fe49d86 CW |
847 | /* Only bind to function 0 of the device. Early generations |
848 | * used function 1 as a placeholder for multi-head. This causes | |
849 | * us confusion instead, especially on the systems where both | |
850 | * functions have the same PCI-ID! | |
851 | */ | |
852 | if (PCI_FUNC(pdev->devfn)) | |
853 | return -ENODEV; | |
854 | ||
24986ee0 | 855 | driver.driver_features &= ~(DRIVER_USE_AGP); |
01a06850 | 856 | |
dcdb1674 | 857 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
858 | } |
859 | ||
860 | static void | |
861 | i915_pci_remove(struct pci_dev *pdev) | |
862 | { | |
863 | struct drm_device *dev = pci_get_drvdata(pdev); | |
864 | ||
865 | drm_put_dev(dev); | |
866 | } | |
867 | ||
84b79f8d | 868 | static int i915_pm_suspend(struct device *dev) |
112b715e | 869 | { |
84b79f8d RW |
870 | struct pci_dev *pdev = to_pci_dev(dev); |
871 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 872 | |
84b79f8d RW |
873 | if (!drm_dev || !drm_dev->dev_private) { |
874 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
875 | return -ENODEV; | |
876 | } | |
112b715e | 877 | |
5bcf719b DA |
878 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
879 | return 0; | |
880 | ||
76c4b250 ID |
881 | return i915_drm_freeze(drm_dev); |
882 | } | |
883 | ||
884 | static int i915_pm_suspend_late(struct device *dev) | |
885 | { | |
886 | struct pci_dev *pdev = to_pci_dev(dev); | |
887 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
888 | ||
889 | /* | |
890 | * We have a suspedn ordering issue with the snd-hda driver also | |
891 | * requiring our device to be power up. Due to the lack of a | |
892 | * parent/child relationship we currently solve this with an late | |
893 | * suspend hook. | |
894 | * | |
895 | * FIXME: This should be solved with a special hdmi sink device or | |
896 | * similar so that power domains can be employed. | |
897 | */ | |
898 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
899 | return 0; | |
112b715e | 900 | |
84b79f8d RW |
901 | pci_disable_device(pdev); |
902 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 903 | |
84b79f8d | 904 | return 0; |
cbda12d7 ZW |
905 | } |
906 | ||
76c4b250 ID |
907 | static int i915_pm_resume_early(struct device *dev) |
908 | { | |
909 | struct pci_dev *pdev = to_pci_dev(dev); | |
910 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
911 | ||
912 | return i915_resume_early(drm_dev); | |
913 | } | |
914 | ||
84b79f8d | 915 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 916 | { |
84b79f8d RW |
917 | struct pci_dev *pdev = to_pci_dev(dev); |
918 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
919 | ||
920 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
921 | } |
922 | ||
84b79f8d | 923 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 924 | { |
84b79f8d RW |
925 | struct pci_dev *pdev = to_pci_dev(dev); |
926 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
927 | ||
928 | if (!drm_dev || !drm_dev->dev_private) { | |
929 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
930 | return -ENODEV; | |
931 | } | |
932 | ||
933 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
934 | } |
935 | ||
76c4b250 ID |
936 | static int i915_pm_thaw_early(struct device *dev) |
937 | { | |
938 | struct pci_dev *pdev = to_pci_dev(dev); | |
939 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
940 | ||
941 | return i915_drm_thaw_early(drm_dev); | |
942 | } | |
943 | ||
84b79f8d | 944 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 945 | { |
84b79f8d RW |
946 | struct pci_dev *pdev = to_pci_dev(dev); |
947 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
948 | ||
949 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
950 | } |
951 | ||
84b79f8d | 952 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 953 | { |
84b79f8d RW |
954 | struct pci_dev *pdev = to_pci_dev(dev); |
955 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 956 | |
61caf87c | 957 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
958 | } |
959 | ||
0ab9cfeb | 960 | static int hsw_runtime_suspend(struct drm_i915_private *dev_priv) |
97bea207 | 961 | { |
414de7a0 | 962 | hsw_enable_pc8(dev_priv); |
0ab9cfeb ID |
963 | |
964 | return 0; | |
97bea207 PZ |
965 | } |
966 | ||
0ab9cfeb | 967 | static int snb_runtime_resume(struct drm_i915_private *dev_priv) |
9a952a0d PZ |
968 | { |
969 | struct drm_device *dev = dev_priv->dev; | |
970 | ||
9a952a0d | 971 | intel_init_pch_refclk(dev); |
0ab9cfeb ID |
972 | |
973 | return 0; | |
9a952a0d PZ |
974 | } |
975 | ||
0ab9cfeb | 976 | static int hsw_runtime_resume(struct drm_i915_private *dev_priv) |
97bea207 | 977 | { |
414de7a0 | 978 | hsw_disable_pc8(dev_priv); |
0ab9cfeb ID |
979 | |
980 | return 0; | |
97bea207 PZ |
981 | } |
982 | ||
ddeea5b0 ID |
983 | /* |
984 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
985 | * S0i[R123] transition. The list of registers needing a save/restore is | |
986 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
987 | * registers in the following way: | |
988 | * - Driver: saved/restored by the driver | |
989 | * - Punit : saved/restored by the Punit firmware | |
990 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
991 | * used internally by the HW in a way that doesn't depend | |
992 | * keeping the content across a suspend/resume. | |
993 | * - Debug : used for debugging | |
994 | * | |
995 | * We save/restore all registers marked with 'Driver', with the following | |
996 | * exceptions: | |
997 | * - Registers out of use, including also registers marked with 'Debug'. | |
998 | * These have no effect on the driver's operation, so we don't save/restore | |
999 | * them to reduce the overhead. | |
1000 | * - Registers that are fully setup by an initialization function called from | |
1001 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1002 | * - Registers that provide the right functionality with their reset defaults. | |
1003 | * | |
1004 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1005 | * ignored, we save/restore all others, practically treating the HW context as | |
1006 | * a black-box for the driver. Further investigation is needed to reduce the | |
1007 | * saved/restored registers even further, by following the same 3 criteria. | |
1008 | */ | |
1009 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1010 | { | |
1011 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1012 | int i; | |
1013 | ||
1014 | /* GAM 0x4000-0x4770 */ | |
1015 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1016 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1017 | s->arb_mode = I915_READ(ARB_MODE); | |
1018 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1019 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1020 | ||
1021 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1022 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); | |
1023 | ||
1024 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
1025 | s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
1026 | ||
1027 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1028 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1029 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1030 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1031 | ||
1032 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1033 | ||
1034 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1035 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1036 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1037 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1038 | ||
1039 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1040 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1041 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1042 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1043 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1044 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1045 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1046 | ||
1047 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1048 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1049 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1050 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1051 | s->ecobus = I915_READ(ECOBUS); | |
1052 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1053 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1054 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1055 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1056 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1057 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1058 | ||
1059 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1060 | s->gt_imr = I915_READ(GTIMR); | |
1061 | s->gt_ier = I915_READ(GTIER); | |
1062 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1063 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1064 | ||
1065 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1066 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); | |
1067 | ||
1068 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1069 | s->tilectl = I915_READ(TILECTL); | |
1070 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1071 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1072 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1073 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1074 | ||
1075 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1076 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1077 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
1078 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); | |
1079 | ||
1080 | /* | |
1081 | * Not saving any of: | |
1082 | * DFT, 0x9800-0x9EC0 | |
1083 | * SARB, 0xB000-0xB1FC | |
1084 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1085 | * PCI CFG | |
1086 | */ | |
1087 | } | |
1088 | ||
1089 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1090 | { | |
1091 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1092 | u32 val; | |
1093 | int i; | |
1094 | ||
1095 | /* GAM 0x4000-0x4770 */ | |
1096 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1097 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1098 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1099 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1100 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1101 | ||
1102 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1103 | I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); | |
1104 | ||
1105 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
1106 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count); | |
1107 | ||
1108 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1109 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1110 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1111 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1112 | ||
1113 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1114 | ||
1115 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1116 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1117 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1118 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1119 | ||
1120 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1121 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1122 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1123 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1124 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1125 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1126 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1127 | ||
1128 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1129 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1130 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1131 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1132 | I915_WRITE(ECOBUS, s->ecobus); | |
1133 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1134 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1135 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1136 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1137 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1138 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1139 | ||
1140 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1141 | I915_WRITE(GTIMR, s->gt_imr); | |
1142 | I915_WRITE(GTIER, s->gt_ier); | |
1143 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1144 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1145 | ||
1146 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1147 | I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); | |
1148 | ||
1149 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1150 | I915_WRITE(TILECTL, s->tilectl); | |
1151 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1152 | /* | |
1153 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1154 | * be restored, as they are used to control the s0ix suspend/resume | |
1155 | * sequence by the caller. | |
1156 | */ | |
1157 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1158 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1159 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1160 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1161 | ||
1162 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1163 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1164 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1165 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1166 | ||
1167 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1168 | ||
1169 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1170 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1171 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
1172 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); | |
1173 | } | |
1174 | ||
650ad970 ID |
1175 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1176 | { | |
1177 | u32 val; | |
1178 | int err; | |
1179 | ||
1180 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1181 | WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); | |
1182 | ||
1183 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) | |
1184 | /* Wait for a previous force-off to settle */ | |
1185 | if (force_on) { | |
8d4eee9c | 1186 | err = wait_for(!COND, 20); |
650ad970 ID |
1187 | if (err) { |
1188 | DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", | |
1189 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1190 | return err; | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1195 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1196 | if (force_on) | |
1197 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1198 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1199 | ||
1200 | if (!force_on) | |
1201 | return 0; | |
1202 | ||
8d4eee9c | 1203 | err = wait_for(COND, 20); |
650ad970 ID |
1204 | if (err) |
1205 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1206 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1207 | ||
1208 | return err; | |
1209 | #undef COND | |
1210 | } | |
1211 | ||
ddeea5b0 ID |
1212 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1213 | { | |
1214 | u32 val; | |
1215 | int err = 0; | |
1216 | ||
1217 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1218 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1219 | if (allow) | |
1220 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1221 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1222 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1223 | ||
1224 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1225 | allow) | |
1226 | err = wait_for(COND, 1); | |
1227 | if (err) | |
1228 | DRM_ERROR("timeout disabling GT waking\n"); | |
1229 | return err; | |
1230 | #undef COND | |
1231 | } | |
1232 | ||
1233 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1234 | bool wait_for_on) | |
1235 | { | |
1236 | u32 mask; | |
1237 | u32 val; | |
1238 | int err; | |
1239 | ||
1240 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1241 | val = wait_for_on ? mask : 0; | |
1242 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1243 | if (COND) | |
1244 | return 0; | |
1245 | ||
1246 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
1247 | wait_for_on ? "on" : "off", | |
1248 | I915_READ(VLV_GTLC_PW_STATUS)); | |
1249 | ||
1250 | /* | |
1251 | * RC6 transitioning can be delayed up to 2 msec (see | |
1252 | * valleyview_enable_rps), use 3 msec for safety. | |
1253 | */ | |
1254 | err = wait_for(COND, 3); | |
1255 | if (err) | |
1256 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
1257 | wait_for_on ? "on" : "off"); | |
1258 | ||
1259 | return err; | |
1260 | #undef COND | |
1261 | } | |
1262 | ||
1263 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1264 | { | |
1265 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1266 | return; | |
1267 | ||
1268 | DRM_ERROR("GT register access while GT waking disabled\n"); | |
1269 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); | |
1270 | } | |
1271 | ||
1272 | static int vlv_runtime_suspend(struct drm_i915_private *dev_priv) | |
1273 | { | |
1274 | u32 mask; | |
1275 | int err; | |
1276 | ||
1277 | /* | |
1278 | * Bspec defines the following GT well on flags as debug only, so | |
1279 | * don't treat them as hard failures. | |
1280 | */ | |
1281 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1282 | ||
1283 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1284 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1285 | ||
1286 | vlv_check_no_gt_access(dev_priv); | |
1287 | ||
1288 | err = vlv_force_gfx_clock(dev_priv, true); | |
1289 | if (err) | |
1290 | goto err1; | |
1291 | ||
1292 | err = vlv_allow_gt_wake(dev_priv, false); | |
1293 | if (err) | |
1294 | goto err2; | |
1295 | vlv_save_gunit_s0ix_state(dev_priv); | |
1296 | ||
1297 | err = vlv_force_gfx_clock(dev_priv, false); | |
1298 | if (err) | |
1299 | goto err2; | |
1300 | ||
1301 | return 0; | |
1302 | ||
1303 | err2: | |
1304 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1305 | vlv_allow_gt_wake(dev_priv, true); | |
1306 | err1: | |
1307 | vlv_force_gfx_clock(dev_priv, false); | |
1308 | ||
1309 | return err; | |
1310 | } | |
1311 | ||
1312 | static int vlv_runtime_resume(struct drm_i915_private *dev_priv) | |
1313 | { | |
1314 | struct drm_device *dev = dev_priv->dev; | |
1315 | int err; | |
1316 | int ret; | |
1317 | ||
1318 | /* | |
1319 | * If any of the steps fail just try to continue, that's the best we | |
1320 | * can do at this point. Return the first error code (which will also | |
1321 | * leave RPM permanently disabled). | |
1322 | */ | |
1323 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1324 | ||
1325 | vlv_restore_gunit_s0ix_state(dev_priv); | |
1326 | ||
1327 | err = vlv_allow_gt_wake(dev_priv, true); | |
1328 | if (!ret) | |
1329 | ret = err; | |
1330 | ||
1331 | err = vlv_force_gfx_clock(dev_priv, false); | |
1332 | if (!ret) | |
1333 | ret = err; | |
1334 | ||
1335 | vlv_check_no_gt_access(dev_priv); | |
1336 | ||
1337 | intel_init_clock_gating(dev); | |
1338 | i915_gem_restore_fences(dev); | |
1339 | ||
1340 | return ret; | |
1341 | } | |
1342 | ||
97bea207 | 1343 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1344 | { |
1345 | struct pci_dev *pdev = to_pci_dev(device); | |
1346 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1348 | int ret; |
8a187455 | 1349 | |
aeab0b5a | 1350 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1351 | return -ENODEV; |
1352 | ||
8a187455 | 1353 | WARN_ON(!HAS_RUNTIME_PM(dev)); |
e998c40f | 1354 | assert_force_wake_inactive(dev_priv); |
8a187455 PZ |
1355 | |
1356 | DRM_DEBUG_KMS("Suspending device\n"); | |
1357 | ||
9486db61 ID |
1358 | /* |
1359 | * rps.work can't be rearmed here, since we get here only after making | |
1360 | * sure the GPU is idle and the RPS freq is set to the minimum. See | |
1361 | * intel_mark_idle(). | |
1362 | */ | |
1363 | cancel_work_sync(&dev_priv->rps.work); | |
b5478bcd ID |
1364 | intel_runtime_pm_disable_interrupts(dev); |
1365 | ||
0ab9cfeb ID |
1366 | if (IS_GEN6(dev)) { |
1367 | ret = 0; | |
1368 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
1369 | ret = hsw_runtime_suspend(dev_priv); | |
ddeea5b0 ID |
1370 | } else if (IS_VALLEYVIEW(dev)) { |
1371 | ret = vlv_runtime_suspend(dev_priv); | |
0ab9cfeb ID |
1372 | } else { |
1373 | ret = -ENODEV; | |
6157d3c8 | 1374 | WARN_ON(1); |
0ab9cfeb ID |
1375 | } |
1376 | ||
1377 | if (ret) { | |
1378 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
1379 | intel_runtime_pm_restore_interrupts(dev); | |
1380 | ||
1381 | return ret; | |
1382 | } | |
a8a8bd54 | 1383 | |
48018a57 PZ |
1384 | i915_gem_release_all_mmaps(dev_priv); |
1385 | ||
16a3d6ef | 1386 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
8a187455 | 1387 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1388 | |
1389 | /* | |
1390 | * current versions of firmware which depend on this opregion | |
1391 | * notification have repurposed the D1 definition to mean | |
1392 | * "runtime suspended" vs. what you would normally expect (D3) | |
1393 | * to distinguish it from notifications that might be sent | |
1394 | * via the suspend path. | |
1395 | */ | |
1396 | intel_opregion_notify_adapter(dev, PCI_D1); | |
8a187455 | 1397 | |
a8a8bd54 | 1398 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1399 | return 0; |
1400 | } | |
1401 | ||
97bea207 | 1402 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1403 | { |
1404 | struct pci_dev *pdev = to_pci_dev(device); | |
1405 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1407 | int ret; |
8a187455 PZ |
1408 | |
1409 | WARN_ON(!HAS_RUNTIME_PM(dev)); | |
1410 | ||
1411 | DRM_DEBUG_KMS("Resuming device\n"); | |
1412 | ||
cd2e9e90 | 1413 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 PZ |
1414 | dev_priv->pm.suspended = false; |
1415 | ||
0ab9cfeb ID |
1416 | if (IS_GEN6(dev)) { |
1417 | ret = snb_runtime_resume(dev_priv); | |
1418 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
1419 | ret = hsw_runtime_resume(dev_priv); | |
ddeea5b0 ID |
1420 | } else if (IS_VALLEYVIEW(dev)) { |
1421 | ret = vlv_runtime_resume(dev_priv); | |
0ab9cfeb | 1422 | } else { |
6157d3c8 | 1423 | WARN_ON(1); |
0ab9cfeb ID |
1424 | ret = -ENODEV; |
1425 | } | |
a8a8bd54 | 1426 | |
0ab9cfeb ID |
1427 | /* |
1428 | * No point of rolling back things in case of an error, as the best | |
1429 | * we can do is to hope that things will still work (and disable RPM). | |
1430 | */ | |
92b806d3 ID |
1431 | i915_gem_init_swizzling(dev); |
1432 | gen6_update_ring_freq(dev); | |
1433 | ||
b5478bcd | 1434 | intel_runtime_pm_restore_interrupts(dev); |
9486db61 | 1435 | intel_reset_gt_powersave(dev); |
b5478bcd | 1436 | |
0ab9cfeb ID |
1437 | if (ret) |
1438 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1439 | else | |
1440 | DRM_DEBUG_KMS("Device resumed\n"); | |
1441 | ||
1442 | return ret; | |
8a187455 PZ |
1443 | } |
1444 | ||
b4b78d12 | 1445 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 | 1446 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1447 | .suspend_late = i915_pm_suspend_late, |
1448 | .resume_early = i915_pm_resume_early, | |
0206e353 AJ |
1449 | .resume = i915_pm_resume, |
1450 | .freeze = i915_pm_freeze, | |
76c4b250 | 1451 | .thaw_early = i915_pm_thaw_early, |
0206e353 AJ |
1452 | .thaw = i915_pm_thaw, |
1453 | .poweroff = i915_pm_poweroff, | |
76c4b250 | 1454 | .restore_early = i915_pm_resume_early, |
0206e353 | 1455 | .restore = i915_pm_resume, |
97bea207 PZ |
1456 | .runtime_suspend = intel_runtime_suspend, |
1457 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1458 | }; |
1459 | ||
78b68556 | 1460 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1461 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1462 | .open = drm_gem_vm_open, |
1463 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1464 | }; |
1465 | ||
e08e96de AV |
1466 | static const struct file_operations i915_driver_fops = { |
1467 | .owner = THIS_MODULE, | |
1468 | .open = drm_open, | |
1469 | .release = drm_release, | |
1470 | .unlocked_ioctl = drm_ioctl, | |
1471 | .mmap = drm_gem_mmap, | |
1472 | .poll = drm_poll, | |
e08e96de AV |
1473 | .read = drm_read, |
1474 | #ifdef CONFIG_COMPAT | |
1475 | .compat_ioctl = i915_compat_ioctl, | |
1476 | #endif | |
1477 | .llseek = noop_llseek, | |
1478 | }; | |
1479 | ||
1da177e4 | 1480 | static struct drm_driver driver = { |
0c54781b MW |
1481 | /* Don't use MTRRs here; the Xserver or userspace app should |
1482 | * deal with them for Intel hardware. | |
792d2b9a | 1483 | */ |
673a394b | 1484 | .driver_features = |
24986ee0 | 1485 | DRIVER_USE_AGP | |
10ba5012 KH |
1486 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1487 | DRIVER_RENDER, | |
22eae947 | 1488 | .load = i915_driver_load, |
ba8bbcf6 | 1489 | .unload = i915_driver_unload, |
673a394b | 1490 | .open = i915_driver_open, |
22eae947 DA |
1491 | .lastclose = i915_driver_lastclose, |
1492 | .preclose = i915_driver_preclose, | |
673a394b | 1493 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1494 | |
1495 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1496 | .suspend = i915_suspend, | |
76c4b250 | 1497 | .resume = i915_resume_legacy, |
d8e29209 | 1498 | |
cda17380 | 1499 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
1500 | .master_create = i915_master_create, |
1501 | .master_destroy = i915_master_destroy, | |
955b12de | 1502 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1503 | .debugfs_init = i915_debugfs_init, |
1504 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1505 | #endif |
673a394b | 1506 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1507 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1508 | |
1509 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1510 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1511 | .gem_prime_export = i915_gem_prime_export, | |
1512 | .gem_prime_import = i915_gem_prime_import, | |
1513 | ||
ff72145b DA |
1514 | .dumb_create = i915_gem_dumb_create, |
1515 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 1516 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1517 | .ioctls = i915_ioctls, |
e08e96de | 1518 | .fops = &i915_driver_fops, |
22eae947 DA |
1519 | .name = DRIVER_NAME, |
1520 | .desc = DRIVER_DESC, | |
1521 | .date = DRIVER_DATE, | |
1522 | .major = DRIVER_MAJOR, | |
1523 | .minor = DRIVER_MINOR, | |
1524 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1525 | }; |
1526 | ||
8410ea3b DA |
1527 | static struct pci_driver i915_pci_driver = { |
1528 | .name = DRIVER_NAME, | |
1529 | .id_table = pciidlist, | |
1530 | .probe = i915_pci_probe, | |
1531 | .remove = i915_pci_remove, | |
1532 | .driver.pm = &i915_pm_ops, | |
1533 | }; | |
1534 | ||
1da177e4 LT |
1535 | static int __init i915_init(void) |
1536 | { | |
1537 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1538 | |
1539 | /* | |
1540 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1541 | * explicitly disabled with the module pararmeter. | |
1542 | * | |
1543 | * Otherwise, just follow the parameter (defaulting to off). | |
1544 | * | |
1545 | * Allow optional vga_text_mode_force boot option to override | |
1546 | * the default behavior. | |
1547 | */ | |
1548 | #if defined(CONFIG_DRM_I915_KMS) | |
d330a953 | 1549 | if (i915.modeset != 0) |
79e53945 JB |
1550 | driver.driver_features |= DRIVER_MODESET; |
1551 | #endif | |
d330a953 | 1552 | if (i915.modeset == 1) |
79e53945 JB |
1553 | driver.driver_features |= DRIVER_MODESET; |
1554 | ||
1555 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 1556 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
1557 | driver.driver_features &= ~DRIVER_MODESET; |
1558 | #endif | |
1559 | ||
b30324ad | 1560 | if (!(driver.driver_features & DRIVER_MODESET)) { |
3885c6bb | 1561 | driver.get_vblank_timestamp = NULL; |
b30324ad DV |
1562 | #ifndef CONFIG_DRM_I915_UMS |
1563 | /* Silently fail loading to not upset userspace. */ | |
1564 | return 0; | |
1565 | #endif | |
1566 | } | |
3885c6bb | 1567 | |
8410ea3b | 1568 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1569 | } |
1570 | ||
1571 | static void __exit i915_exit(void) | |
1572 | { | |
b33ecdd1 DV |
1573 | #ifndef CONFIG_DRM_I915_UMS |
1574 | if (!(driver.driver_features & DRIVER_MODESET)) | |
1575 | return; /* Never loaded a driver. */ | |
1576 | #endif | |
1577 | ||
8410ea3b | 1578 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1579 | } |
1580 | ||
1581 | module_init(i915_init); | |
1582 | module_exit(i915_exit); | |
1583 | ||
b5e89ed5 DA |
1584 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1585 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1586 | MODULE_LICENSE("GPL and additional rights"); |