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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
e5747e3a | 31 | #include <linux/acpi.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/i915_drm.h> | |
1da177e4 | 34 | #include "i915_drv.h" |
990bbdad | 35 | #include "i915_trace.h" |
f49f0586 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
79e53945 | 38 | #include <linux/console.h> |
e0cd3608 | 39 | #include <linux/module.h> |
d6102977 | 40 | #include <linux/pm_runtime.h> |
760285e7 | 41 | #include <drm/drm_crtc_helper.h> |
79e53945 | 42 | |
112b715e KH |
43 | static struct drm_driver driver; |
44 | ||
a57c774a AK |
45 | #define GEN_DEFAULT_PIPEOFFSETS \ |
46 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
47 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
48 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
49 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
a57c774a AK |
50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
51 | ||
84fd4f4e RB |
52 | #define GEN_CHV_PIPEOFFSETS \ |
53 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
54 | CHV_PIPE_C_OFFSET }, \ | |
55 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
56 | CHV_TRANSCODER_C_OFFSET, }, \ | |
84fd4f4e RB |
57 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
58 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 59 | |
5efb3e28 VS |
60 | #define CURSOR_OFFSETS \ |
61 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
62 | ||
63 | #define IVB_CURSOR_OFFSETS \ | |
64 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
65 | ||
9a7e8492 | 66 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 67 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 68 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 69 | .ring_mask = RENDER_RING, |
a57c774a | 70 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 71 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
72 | }; |
73 | ||
9a7e8492 | 74 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 75 | .gen = 2, .num_pipes = 1, |
31578148 | 76 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 77 | .ring_mask = RENDER_RING, |
a57c774a | 78 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 79 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
80 | }; |
81 | ||
9a7e8492 | 82 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 83 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 84 | .cursor_needs_physical = 1, |
31578148 | 85 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 86 | .has_fbc = 1, |
73ae478c | 87 | .ring_mask = RENDER_RING, |
a57c774a | 88 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 89 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
90 | }; |
91 | ||
9a7e8492 | 92 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 93 | .gen = 2, .num_pipes = 1, |
31578148 | 94 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 95 | .ring_mask = RENDER_RING, |
a57c774a | 96 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 97 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
98 | }; |
99 | ||
9a7e8492 | 100 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 101 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 102 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 103 | .ring_mask = RENDER_RING, |
a57c774a | 104 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 105 | CURSOR_OFFSETS, |
cfdf1fa2 | 106 | }; |
9a7e8492 | 107 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 108 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 109 | .cursor_needs_physical = 1, |
31578148 | 110 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 111 | .supports_tv = 1, |
fd70d52a | 112 | .has_fbc = 1, |
73ae478c | 113 | .ring_mask = RENDER_RING, |
a57c774a | 114 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 115 | CURSOR_OFFSETS, |
cfdf1fa2 | 116 | }; |
9a7e8492 | 117 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 118 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 119 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 120 | .ring_mask = RENDER_RING, |
a57c774a | 121 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 122 | CURSOR_OFFSETS, |
cfdf1fa2 | 123 | }; |
9a7e8492 | 124 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 125 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 126 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 127 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 128 | .supports_tv = 1, |
fd70d52a | 129 | .has_fbc = 1, |
73ae478c | 130 | .ring_mask = RENDER_RING, |
a57c774a | 131 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 132 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
133 | }; |
134 | ||
9a7e8492 | 135 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 136 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 137 | .has_hotplug = 1, |
31578148 | 138 | .has_overlay = 1, |
73ae478c | 139 | .ring_mask = RENDER_RING, |
a57c774a | 140 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 141 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
142 | }; |
143 | ||
9a7e8492 | 144 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 145 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 146 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 147 | .has_overlay = 1, |
a6c45cf0 | 148 | .supports_tv = 1, |
73ae478c | 149 | .ring_mask = RENDER_RING, |
a57c774a | 150 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 151 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
152 | }; |
153 | ||
9a7e8492 | 154 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 155 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 156 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 157 | .has_overlay = 1, |
73ae478c | 158 | .ring_mask = RENDER_RING, |
a57c774a | 159 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 160 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
161 | }; |
162 | ||
9a7e8492 | 163 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 164 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 165 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 166 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 167 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 168 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
169 | }; |
170 | ||
9a7e8492 | 171 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 172 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 173 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 174 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 175 | .supports_tv = 1, |
73ae478c | 176 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 177 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 178 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
179 | }; |
180 | ||
9a7e8492 | 181 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 182 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 183 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 184 | .has_overlay = 1, |
a57c774a | 185 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 186 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
187 | }; |
188 | ||
9a7e8492 | 189 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 190 | .gen = 5, .num_pipes = 2, |
5a117db7 | 191 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 192 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 193 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 194 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
195 | }; |
196 | ||
9a7e8492 | 197 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 198 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 199 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 200 | .has_fbc = 1, |
73ae478c | 201 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 202 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 203 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
204 | }; |
205 | ||
9a7e8492 | 206 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 207 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 208 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 209 | .has_fbc = 1, |
73ae478c | 210 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 211 | .has_llc = 1, |
a57c774a | 212 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 213 | CURSOR_OFFSETS, |
f6e450a6 EA |
214 | }; |
215 | ||
9a7e8492 | 216 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 217 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 218 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 219 | .has_fbc = 1, |
73ae478c | 220 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 221 | .has_llc = 1, |
a57c774a | 222 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 223 | CURSOR_OFFSETS, |
a13e4093 EA |
224 | }; |
225 | ||
219f4fdb BW |
226 | #define GEN7_FEATURES \ |
227 | .gen = 7, .num_pipes = 3, \ | |
228 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 229 | .has_fbc = 1, \ |
73ae478c | 230 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 231 | .has_llc = 1 |
219f4fdb | 232 | |
c76b615c | 233 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
234 | GEN7_FEATURES, |
235 | .is_ivybridge = 1, | |
a57c774a | 236 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 237 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
238 | }; |
239 | ||
240 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
241 | GEN7_FEATURES, |
242 | .is_ivybridge = 1, | |
243 | .is_mobile = 1, | |
a57c774a | 244 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 245 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
246 | }; |
247 | ||
999bcdea BW |
248 | static const struct intel_device_info intel_ivybridge_q_info = { |
249 | GEN7_FEATURES, | |
250 | .is_ivybridge = 1, | |
251 | .num_pipes = 0, /* legal, last one wins */ | |
a57c774a | 252 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 253 | IVB_CURSOR_OFFSETS, |
999bcdea BW |
254 | }; |
255 | ||
70a3eb7a | 256 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
257 | GEN7_FEATURES, |
258 | .is_mobile = 1, | |
259 | .num_pipes = 2, | |
70a3eb7a | 260 | .is_valleyview = 1, |
fba5d532 | 261 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 262 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 263 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 264 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 265 | CURSOR_OFFSETS, |
70a3eb7a JB |
266 | }; |
267 | ||
268 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
269 | GEN7_FEATURES, |
270 | .num_pipes = 2, | |
70a3eb7a | 271 | .is_valleyview = 1, |
fba5d532 | 272 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 273 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 274 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 275 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 276 | CURSOR_OFFSETS, |
70a3eb7a JB |
277 | }; |
278 | ||
4cae9ae0 | 279 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
280 | GEN7_FEATURES, |
281 | .is_haswell = 1, | |
dd93be58 | 282 | .has_ddi = 1, |
30568c45 | 283 | .has_fpga_dbg = 1, |
73ae478c | 284 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 285 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 286 | IVB_CURSOR_OFFSETS, |
4cae9ae0 ED |
287 | }; |
288 | ||
289 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
290 | GEN7_FEATURES, |
291 | .is_haswell = 1, | |
292 | .is_mobile = 1, | |
dd93be58 | 293 | .has_ddi = 1, |
30568c45 | 294 | .has_fpga_dbg = 1, |
73ae478c | 295 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 296 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 297 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
298 | }; |
299 | ||
4d4dead6 | 300 | static const struct intel_device_info intel_broadwell_d_info = { |
4b30553d | 301 | .gen = 8, .num_pipes = 3, |
4d4dead6 BW |
302 | .need_gfx_hws = 1, .has_hotplug = 1, |
303 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
304 | .has_llc = 1, | |
305 | .has_ddi = 1, | |
66bc2cab | 306 | .has_fpga_dbg = 1, |
8f94d24b | 307 | .has_fbc = 1, |
a57c774a | 308 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 309 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
310 | }; |
311 | ||
312 | static const struct intel_device_info intel_broadwell_m_info = { | |
4b30553d | 313 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
4d4dead6 BW |
314 | .need_gfx_hws = 1, .has_hotplug = 1, |
315 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
316 | .has_llc = 1, | |
317 | .has_ddi = 1, | |
66bc2cab | 318 | .has_fpga_dbg = 1, |
8f94d24b | 319 | .has_fbc = 1, |
a57c774a | 320 | GEN_DEFAULT_PIPEOFFSETS, |
15d24aa5 | 321 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
322 | }; |
323 | ||
fd3c269f ZY |
324 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
325 | .gen = 8, .num_pipes = 3, | |
326 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 327 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
328 | .has_llc = 1, |
329 | .has_ddi = 1, | |
66bc2cab | 330 | .has_fpga_dbg = 1, |
fd3c269f ZY |
331 | .has_fbc = 1, |
332 | GEN_DEFAULT_PIPEOFFSETS, | |
15d24aa5 | 333 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
334 | }; |
335 | ||
336 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
337 | .gen = 8, .is_mobile = 1, .num_pipes = 3, | |
338 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 339 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
340 | .has_llc = 1, |
341 | .has_ddi = 1, | |
66bc2cab | 342 | .has_fpga_dbg = 1, |
fd3c269f ZY |
343 | .has_fbc = 1, |
344 | GEN_DEFAULT_PIPEOFFSETS, | |
5efb3e28 | 345 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
346 | }; |
347 | ||
7d87a7f7 VS |
348 | static const struct intel_device_info intel_cherryview_info = { |
349 | .is_preliminary = 1, | |
07fddb14 | 350 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
351 | .need_gfx_hws = 1, .has_hotplug = 1, |
352 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
353 | .is_valleyview = 1, | |
354 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
84fd4f4e | 355 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 356 | CURSOR_OFFSETS, |
7d87a7f7 VS |
357 | }; |
358 | ||
72bbf0af DL |
359 | static const struct intel_device_info intel_skylake_info = { |
360 | .is_preliminary = 1, | |
7201c0b3 | 361 | .is_skylake = 1, |
72bbf0af DL |
362 | .gen = 9, .num_pipes = 3, |
363 | .need_gfx_hws = 1, .has_hotplug = 1, | |
364 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
365 | .has_llc = 1, | |
366 | .has_ddi = 1, | |
043efb11 | 367 | .has_fbc = 1, |
72bbf0af DL |
368 | GEN_DEFAULT_PIPEOFFSETS, |
369 | IVB_CURSOR_OFFSETS, | |
370 | }; | |
371 | ||
a0a18075 JB |
372 | /* |
373 | * Make sure any device matches here are from most specific to most | |
374 | * general. For example, since the Quanta match is based on the subsystem | |
375 | * and subvendor IDs, we need it to come before the more general IVB | |
376 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
377 | */ | |
378 | #define INTEL_PCI_IDS \ | |
379 | INTEL_I830_IDS(&intel_i830_info), \ | |
380 | INTEL_I845G_IDS(&intel_845g_info), \ | |
381 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
382 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
383 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
384 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
385 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
386 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
387 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
388 | INTEL_G33_IDS(&intel_g33_info), \ | |
389 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
390 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
391 | INTEL_G45_IDS(&intel_g45_info), \ | |
392 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
393 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
394 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
395 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
396 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
397 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
398 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
399 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
400 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
401 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
402 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
4d4dead6 | 403 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ |
fd3c269f ZY |
404 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ |
405 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ | |
406 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ | |
7d87a7f7 | 407 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \ |
72bbf0af DL |
408 | INTEL_CHV_IDS(&intel_cherryview_info), \ |
409 | INTEL_SKL_IDS(&intel_skylake_info) | |
a0a18075 | 410 | |
6103da0d | 411 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 412 | INTEL_PCI_IDS, |
49ae35f2 | 413 | {0, 0, 0} |
1da177e4 LT |
414 | }; |
415 | ||
79e53945 JB |
416 | #if defined(CONFIG_DRM_I915_KMS) |
417 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
418 | #endif | |
419 | ||
0206e353 | 420 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
421 | { |
422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 423 | struct pci_dev *pch = NULL; |
3bad0781 | 424 | |
ce1bb329 BW |
425 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
426 | * (which really amounts to a PCH but no South Display). | |
427 | */ | |
428 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
429 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
430 | return; |
431 | } | |
432 | ||
3bad0781 ZW |
433 | /* |
434 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
435 | * make graphics device passthrough work easy for VMM, that only | |
436 | * need to expose ISA bridge to let driver know the real hardware | |
437 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
438 | * |
439 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
440 | * ISA bridge in the system. To work reliably, we should scan trhough | |
441 | * all the ISA bridge devices and check for the first match, instead | |
442 | * of only checking the first one. | |
3bad0781 | 443 | */ |
bcdb72ac | 444 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 445 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 446 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 447 | dev_priv->pch_id = id; |
3bad0781 | 448 | |
90711d50 JB |
449 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
450 | dev_priv->pch_type = PCH_IBX; | |
451 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 452 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 453 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
454 | dev_priv->pch_type = PCH_CPT; |
455 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 456 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
457 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
458 | /* PantherPoint is CPT compatible */ | |
459 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 460 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 461 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
462 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
463 | dev_priv->pch_type = PCH_LPT; | |
464 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 465 | WARN_ON(!IS_HASWELL(dev)); |
bcef6d5a | 466 | WARN_ON(IS_HSW_ULT(dev)); |
018f52c9 PZ |
467 | } else if (IS_BROADWELL(dev)) { |
468 | dev_priv->pch_type = PCH_LPT; | |
469 | dev_priv->pch_id = | |
470 | INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
471 | DRM_DEBUG_KMS("This is Broadwell, assuming " | |
472 | "LynxPoint LP PCH\n"); | |
e76e0634 BW |
473 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
474 | dev_priv->pch_type = PCH_LPT; | |
475 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
476 | WARN_ON(!IS_HASWELL(dev)); | |
bcef6d5a | 477 | WARN_ON(!IS_HSW_ULT(dev)); |
e7e7ea20 S |
478 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
479 | dev_priv->pch_type = PCH_SPT; | |
480 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
481 | WARN_ON(!IS_SKYLAKE(dev)); | |
e7e7ea20 S |
482 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
483 | dev_priv->pch_type = PCH_SPT; | |
484 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
485 | WARN_ON(!IS_SKYLAKE(dev)); | |
bcdb72ac ID |
486 | } else |
487 | continue; | |
488 | ||
6a9c4b35 | 489 | break; |
3bad0781 | 490 | } |
3bad0781 | 491 | } |
6a9c4b35 | 492 | if (!pch) |
bcdb72ac ID |
493 | DRM_DEBUG_KMS("No PCH found.\n"); |
494 | ||
495 | pci_dev_put(pch); | |
3bad0781 ZW |
496 | } |
497 | ||
2911a35b BW |
498 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
499 | { | |
500 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 501 | return false; |
2911a35b | 502 | |
d330a953 JN |
503 | if (i915.semaphores >= 0) |
504 | return i915.semaphores; | |
2911a35b | 505 | |
71386ef9 OM |
506 | /* TODO: make semaphores and Execlists play nicely together */ |
507 | if (i915.enable_execlists) | |
508 | return false; | |
509 | ||
be71eabe RV |
510 | /* Until we get further testing... */ |
511 | if (IS_GEN8(dev)) | |
512 | return false; | |
513 | ||
59de3295 | 514 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 515 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
516 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
517 | return false; | |
518 | #endif | |
2911a35b | 519 | |
a08acaf2 | 520 | return true; |
2911a35b BW |
521 | } |
522 | ||
1d0d343a ID |
523 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) |
524 | { | |
525 | spin_lock_irq(&dev_priv->irq_lock); | |
526 | ||
527 | dev_priv->long_hpd_port_mask = 0; | |
528 | dev_priv->short_hpd_port_mask = 0; | |
529 | dev_priv->hpd_event_bits = 0; | |
530 | ||
531 | spin_unlock_irq(&dev_priv->irq_lock); | |
532 | ||
533 | cancel_work_sync(&dev_priv->dig_port_work); | |
534 | cancel_work_sync(&dev_priv->hotplug_work); | |
535 | cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work); | |
536 | } | |
537 | ||
07f9cd0b ID |
538 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
539 | { | |
540 | struct drm_device *dev = dev_priv->dev; | |
541 | struct drm_encoder *encoder; | |
542 | ||
543 | drm_modeset_lock_all(dev); | |
544 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
545 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
546 | ||
547 | if (intel_encoder->suspend) | |
548 | intel_encoder->suspend(intel_encoder); | |
549 | } | |
550 | drm_modeset_unlock_all(dev); | |
551 | } | |
552 | ||
ebc32824 | 553 | static int intel_suspend_complete(struct drm_i915_private *dev_priv); |
016970be SK |
554 | static int intel_resume_prepare(struct drm_i915_private *dev_priv, |
555 | bool rpm_resume); | |
ebc32824 | 556 | |
5e365c39 | 557 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 558 | { |
61caf87c | 559 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 560 | struct drm_crtc *crtc; |
e5747e3a | 561 | pci_power_t opregion_target_state; |
61caf87c | 562 | |
b8efb17b ZR |
563 | /* ignore lid events during suspend */ |
564 | mutex_lock(&dev_priv->modeset_restore_lock); | |
565 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
566 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
567 | ||
c67a470b PZ |
568 | /* We do a lot of poking in a lot of registers, make sure they work |
569 | * properly. */ | |
da7e29bd | 570 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 571 | |
5bcf719b DA |
572 | drm_kms_helper_poll_disable(dev); |
573 | ||
ba8bbcf6 | 574 | pci_save_state(dev->pdev); |
ba8bbcf6 | 575 | |
5669fcac | 576 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 577 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
578 | int error; |
579 | ||
45c5f202 | 580 | error = i915_gem_suspend(dev); |
84b79f8d | 581 | if (error) { |
226485e9 | 582 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
583 | "GEM idle failed, resume might fail\n"); |
584 | return error; | |
585 | } | |
a261b246 | 586 | |
24576d23 JB |
587 | /* |
588 | * Disable CRTCs directly since we want to preserve sw state | |
b04c5bd6 | 589 | * for _thaw. Also, power gate the CRTC power wells. |
24576d23 | 590 | */ |
6e9f798d | 591 | drm_modeset_lock_all(dev); |
b04c5bd6 BF |
592 | for_each_crtc(dev, crtc) |
593 | intel_crtc_control(crtc, false); | |
6e9f798d | 594 | drm_modeset_unlock_all(dev); |
7d708ee4 | 595 | |
0e32b39c | 596 | intel_dp_mst_suspend(dev); |
09b64267 DA |
597 | |
598 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
599 | ||
b963291c | 600 | intel_runtime_pm_disable_interrupts(dev_priv); |
1d0d343a | 601 | intel_hpd_cancel_work(dev_priv); |
0e32b39c | 602 | |
07f9cd0b ID |
603 | intel_suspend_encoders(dev_priv); |
604 | ||
09b64267 DA |
605 | intel_suspend_gt_powersave(dev); |
606 | ||
970104fa | 607 | intel_suspend_hw(dev); |
5669fcac JB |
608 | } |
609 | ||
828c7908 BW |
610 | i915_gem_suspend_gtt_mappings(dev); |
611 | ||
9e06dd39 JB |
612 | i915_save_state(dev); |
613 | ||
95fa2eee ID |
614 | opregion_target_state = PCI_D3cold; |
615 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
616 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
e5747e3a | 617 | opregion_target_state = PCI_D1; |
95fa2eee | 618 | #endif |
e5747e3a JB |
619 | intel_opregion_notify_adapter(dev, opregion_target_state); |
620 | ||
156c7ca0 | 621 | intel_uncore_forcewake_reset(dev, false); |
44834a67 | 622 | intel_opregion_fini(dev); |
8ee1c3db | 623 | |
82e3b8c1 | 624 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 625 | |
62d5d69b MK |
626 | dev_priv->suspend_count++; |
627 | ||
85e90679 KCA |
628 | intel_display_set_init_power(dev_priv, false); |
629 | ||
61caf87c | 630 | return 0; |
84b79f8d RW |
631 | } |
632 | ||
c3c09c95 ID |
633 | static int i915_drm_suspend_late(struct drm_device *drm_dev) |
634 | { | |
635 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
636 | int ret; | |
637 | ||
638 | ret = intel_suspend_complete(dev_priv); | |
639 | ||
640 | if (ret) { | |
641 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
642 | ||
643 | return ret; | |
644 | } | |
645 | ||
646 | pci_disable_device(drm_dev->pdev); | |
647 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
fc49b3da | 652 | int i915_suspend_legacy(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
653 | { |
654 | int error; | |
655 | ||
656 | if (!dev || !dev->dev_private) { | |
657 | DRM_ERROR("dev: %p\n", dev); | |
658 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
659 | return -ENODEV; | |
660 | } | |
661 | ||
0b14cbd2 ID |
662 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
663 | state.event != PM_EVENT_FREEZE)) | |
664 | return -EINVAL; | |
5bcf719b DA |
665 | |
666 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
667 | return 0; | |
6eecba33 | 668 | |
5e365c39 | 669 | error = i915_drm_suspend(dev); |
84b79f8d RW |
670 | if (error) |
671 | return error; | |
672 | ||
5a17514e | 673 | return i915_drm_suspend_late(dev); |
ba8bbcf6 JB |
674 | } |
675 | ||
5e365c39 | 676 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 ID |
677 | { |
678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9d49c0ef | 679 | |
f4a12ead | 680 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
9d49c0ef PZ |
681 | mutex_lock(&dev->struct_mutex); |
682 | i915_gem_restore_gtt_mappings(dev); | |
683 | mutex_unlock(&dev->struct_mutex); | |
684 | } | |
685 | ||
61caf87c | 686 | i915_restore_state(dev); |
44834a67 | 687 | intel_opregion_setup(dev); |
61caf87c | 688 | |
5669fcac JB |
689 | /* KMS EnterVT equivalent */ |
690 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 691 | intel_init_pch_refclk(dev); |
754970ee | 692 | drm_mode_config_reset(dev); |
1833b134 | 693 | |
5669fcac | 694 | mutex_lock(&dev->struct_mutex); |
074c6ada CW |
695 | if (i915_gem_init_hw(dev)) { |
696 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
697 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
698 | } | |
5669fcac | 699 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 700 | |
2363d8c9 | 701 | /* We need working interrupts for modeset enabling ... */ |
b963291c | 702 | intel_runtime_pm_enable_interrupts(dev_priv); |
15239099 | 703 | |
1833b134 | 704 | intel_modeset_init_hw(dev); |
24576d23 | 705 | |
0e32b39c | 706 | { |
13321786 | 707 | spin_lock_irq(&dev_priv->irq_lock); |
0e32b39c DA |
708 | if (dev_priv->display.hpd_irq_setup) |
709 | dev_priv->display.hpd_irq_setup(dev); | |
13321786 | 710 | spin_unlock_irq(&dev_priv->irq_lock); |
0e32b39c DA |
711 | } |
712 | ||
713 | intel_dp_mst_resume(dev); | |
24576d23 JB |
714 | drm_modeset_lock_all(dev); |
715 | intel_modeset_setup_hw_state(dev, true); | |
716 | drm_modeset_unlock_all(dev); | |
15239099 DV |
717 | |
718 | /* | |
719 | * ... but also need to make sure that hotplug processing | |
720 | * doesn't cause havoc. Like in the driver load code we don't | |
721 | * bother with the tiny race here where we might loose hotplug | |
722 | * notifications. | |
723 | * */ | |
b963291c | 724 | intel_hpd_init(dev_priv); |
bb60b969 | 725 | /* Config may have changed between suspend and resume */ |
1ff74cf1 | 726 | drm_helper_hpd_irq_event(dev); |
d5bb081b | 727 | } |
1daed3fb | 728 | |
44834a67 CW |
729 | intel_opregion_init(dev); |
730 | ||
82e3b8c1 | 731 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 732 | |
b8efb17b ZR |
733 | mutex_lock(&dev_priv->modeset_restore_lock); |
734 | dev_priv->modeset_restore = MODESET_DONE; | |
735 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 736 | |
e5747e3a JB |
737 | intel_opregion_notify_adapter(dev, PCI_D0); |
738 | ||
ee6f280e ID |
739 | drm_kms_helper_poll_enable(dev); |
740 | ||
074c6ada | 741 | return 0; |
84b79f8d RW |
742 | } |
743 | ||
5e365c39 | 744 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 745 | { |
36d61e67 ID |
746 | struct drm_i915_private *dev_priv = dev->dev_private; |
747 | int ret; | |
748 | ||
76c4b250 ID |
749 | /* |
750 | * We have a resume ordering issue with the snd-hda driver also | |
751 | * requiring our device to be power up. Due to the lack of a | |
752 | * parent/child relationship we currently solve this with an early | |
753 | * resume hook. | |
754 | * | |
755 | * FIXME: This should be solved with a special hdmi sink device or | |
756 | * similar so that power domains can be employed. | |
757 | */ | |
84b79f8d RW |
758 | if (pci_enable_device(dev->pdev)) |
759 | return -EIO; | |
760 | ||
761 | pci_set_master(dev->pdev); | |
762 | ||
36d61e67 ID |
763 | ret = intel_resume_prepare(dev_priv, false); |
764 | if (ret) | |
765 | DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret); | |
766 | ||
767 | intel_uncore_early_sanitize(dev, true); | |
768 | intel_uncore_sanitize(dev); | |
769 | intel_power_domains_init_hw(dev_priv); | |
770 | ||
771 | return ret; | |
76c4b250 ID |
772 | } |
773 | ||
fc49b3da | 774 | int i915_resume_legacy(struct drm_device *dev) |
76c4b250 | 775 | { |
50a0072f | 776 | int ret; |
76c4b250 | 777 | |
097dd837 ID |
778 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
779 | return 0; | |
780 | ||
5e365c39 | 781 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
782 | if (ret) |
783 | return ret; | |
784 | ||
5a17514e ID |
785 | return i915_drm_resume(dev); |
786 | } | |
787 | ||
11ed50ec | 788 | /** |
f3953dcb | 789 | * i915_reset - reset chip after a hang |
11ed50ec | 790 | * @dev: drm device to reset |
11ed50ec BG |
791 | * |
792 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
793 | * reset or otherwise an error code. | |
794 | * | |
795 | * Procedure is fairly simple: | |
796 | * - reset the chip using the reset reg | |
797 | * - re-init context state | |
798 | * - re-init hardware status page | |
799 | * - re-init ring buffer | |
800 | * - re-init interrupt state | |
801 | * - re-init display | |
802 | */ | |
d4b8bb2a | 803 | int i915_reset(struct drm_device *dev) |
11ed50ec | 804 | { |
50227e1c | 805 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 806 | bool simulated; |
0573ed4a | 807 | int ret; |
11ed50ec | 808 | |
d330a953 | 809 | if (!i915.reset) |
d78cb50b CW |
810 | return 0; |
811 | ||
d54a02c0 | 812 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 813 | |
069efc1d | 814 | i915_gem_reset(dev); |
77f01230 | 815 | |
2e7c8ee7 CW |
816 | simulated = dev_priv->gpu_error.stop_rings != 0; |
817 | ||
be62acb4 MK |
818 | ret = intel_gpu_reset(dev); |
819 | ||
820 | /* Also reset the gpu hangman. */ | |
821 | if (simulated) { | |
822 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
823 | dev_priv->gpu_error.stop_rings = 0; | |
824 | if (ret == -ENODEV) { | |
f2d91a2c DV |
825 | DRM_INFO("Reset not implemented, but ignoring " |
826 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
827 | ret = 0; |
828 | } | |
2e7c8ee7 | 829 | } |
be62acb4 | 830 | |
d8f2716a DV |
831 | if (i915_stop_ring_allow_warn(dev_priv)) |
832 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); | |
833 | ||
0573ed4a | 834 | if (ret) { |
f2d91a2c | 835 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 836 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 837 | return ret; |
11ed50ec BG |
838 | } |
839 | ||
840 | /* Ok, now get things going again... */ | |
841 | ||
842 | /* | |
843 | * Everything depends on having the GTT running, so we need to start | |
844 | * there. Fortunately we don't need to do this unless we reset the | |
845 | * chip at a PCI level. | |
846 | * | |
847 | * Next we need to restore the context, but we don't use those | |
848 | * yet either... | |
849 | * | |
850 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
851 | * was running at the time of the reset (i.e. we weren't VT | |
852 | * switched away). | |
853 | */ | |
854 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 855 | !dev_priv->ums.mm_suspended) { |
db1b76ca | 856 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 857 | |
6689c167 MA |
858 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
859 | dev_priv->gpu_error.reload_in_reset = true; | |
860 | ||
3d57e5bd | 861 | ret = i915_gem_init_hw(dev); |
6689c167 MA |
862 | |
863 | dev_priv->gpu_error.reload_in_reset = false; | |
864 | ||
8e88a2bd | 865 | mutex_unlock(&dev->struct_mutex); |
3d57e5bd BW |
866 | if (ret) { |
867 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
868 | return ret; | |
869 | } | |
f817586c | 870 | |
e090c53b | 871 | /* |
78ad455f DV |
872 | * FIXME: This races pretty badly against concurrent holders of |
873 | * ring interrupts. This is possible since we've started to drop | |
874 | * dev->struct_mutex in select places when waiting for the gpu. | |
e090c53b | 875 | */ |
dd0a1aa1 | 876 | |
78ad455f DV |
877 | /* |
878 | * rps/rc6 re-init is necessary to restore state lost after the | |
879 | * reset and the re-install of gt irqs. Skip for ironlake per | |
dd0a1aa1 | 880 | * previous concerns that it doesn't respond well to some forms |
78ad455f DV |
881 | * of re-init after reset. |
882 | */ | |
dc1d0136 | 883 | if (INTEL_INFO(dev)->gen > 5) |
c6df39b5 | 884 | intel_reset_gt_powersave(dev); |
bcbc324a DV |
885 | } else { |
886 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
887 | } |
888 | ||
11ed50ec BG |
889 | return 0; |
890 | } | |
891 | ||
56550d94 | 892 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 893 | { |
01a06850 DV |
894 | struct intel_device_info *intel_info = |
895 | (struct intel_device_info *) ent->driver_data; | |
896 | ||
d330a953 | 897 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
898 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
899 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
900 | return -ENODEV; | |
901 | } | |
902 | ||
5fe49d86 CW |
903 | /* Only bind to function 0 of the device. Early generations |
904 | * used function 1 as a placeholder for multi-head. This causes | |
905 | * us confusion instead, especially on the systems where both | |
906 | * functions have the same PCI-ID! | |
907 | */ | |
908 | if (PCI_FUNC(pdev->devfn)) | |
909 | return -ENODEV; | |
910 | ||
24986ee0 | 911 | driver.driver_features &= ~(DRIVER_USE_AGP); |
01a06850 | 912 | |
dcdb1674 | 913 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
914 | } |
915 | ||
916 | static void | |
917 | i915_pci_remove(struct pci_dev *pdev) | |
918 | { | |
919 | struct drm_device *dev = pci_get_drvdata(pdev); | |
920 | ||
921 | drm_put_dev(dev); | |
922 | } | |
923 | ||
84b79f8d | 924 | static int i915_pm_suspend(struct device *dev) |
112b715e | 925 | { |
84b79f8d RW |
926 | struct pci_dev *pdev = to_pci_dev(dev); |
927 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 928 | |
84b79f8d RW |
929 | if (!drm_dev || !drm_dev->dev_private) { |
930 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
931 | return -ENODEV; | |
932 | } | |
112b715e | 933 | |
5bcf719b DA |
934 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
935 | return 0; | |
936 | ||
5e365c39 | 937 | return i915_drm_suspend(drm_dev); |
76c4b250 ID |
938 | } |
939 | ||
940 | static int i915_pm_suspend_late(struct device *dev) | |
941 | { | |
942 | struct pci_dev *pdev = to_pci_dev(dev); | |
943 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
944 | ||
945 | /* | |
946 | * We have a suspedn ordering issue with the snd-hda driver also | |
947 | * requiring our device to be power up. Due to the lack of a | |
948 | * parent/child relationship we currently solve this with an late | |
949 | * suspend hook. | |
950 | * | |
951 | * FIXME: This should be solved with a special hdmi sink device or | |
952 | * similar so that power domains can be employed. | |
953 | */ | |
954 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
955 | return 0; | |
112b715e | 956 | |
c3c09c95 | 957 | return i915_drm_suspend_late(drm_dev); |
cbda12d7 ZW |
958 | } |
959 | ||
76c4b250 ID |
960 | static int i915_pm_resume_early(struct device *dev) |
961 | { | |
962 | struct pci_dev *pdev = to_pci_dev(dev); | |
963 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
964 | ||
097dd837 ID |
965 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
966 | return 0; | |
967 | ||
5e365c39 | 968 | return i915_drm_resume_early(drm_dev); |
76c4b250 ID |
969 | } |
970 | ||
84b79f8d | 971 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 972 | { |
84b79f8d RW |
973 | struct pci_dev *pdev = to_pci_dev(dev); |
974 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
975 | ||
097dd837 ID |
976 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
977 | return 0; | |
978 | ||
5a17514e | 979 | return i915_drm_resume(drm_dev); |
cbda12d7 ZW |
980 | } |
981 | ||
ebc32824 | 982 | static int hsw_suspend_complete(struct drm_i915_private *dev_priv) |
97bea207 | 983 | { |
414de7a0 | 984 | hsw_enable_pc8(dev_priv); |
0ab9cfeb ID |
985 | |
986 | return 0; | |
97bea207 PZ |
987 | } |
988 | ||
016970be SK |
989 | static int snb_resume_prepare(struct drm_i915_private *dev_priv, |
990 | bool rpm_resume) | |
9a952a0d PZ |
991 | { |
992 | struct drm_device *dev = dev_priv->dev; | |
993 | ||
016970be SK |
994 | if (rpm_resume) |
995 | intel_init_pch_refclk(dev); | |
0ab9cfeb ID |
996 | |
997 | return 0; | |
9a952a0d PZ |
998 | } |
999 | ||
016970be SK |
1000 | static int hsw_resume_prepare(struct drm_i915_private *dev_priv, |
1001 | bool rpm_resume) | |
97bea207 | 1002 | { |
414de7a0 | 1003 | hsw_disable_pc8(dev_priv); |
0ab9cfeb ID |
1004 | |
1005 | return 0; | |
97bea207 PZ |
1006 | } |
1007 | ||
ddeea5b0 ID |
1008 | /* |
1009 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
1010 | * S0i[R123] transition. The list of registers needing a save/restore is | |
1011 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
1012 | * registers in the following way: | |
1013 | * - Driver: saved/restored by the driver | |
1014 | * - Punit : saved/restored by the Punit firmware | |
1015 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
1016 | * used internally by the HW in a way that doesn't depend | |
1017 | * keeping the content across a suspend/resume. | |
1018 | * - Debug : used for debugging | |
1019 | * | |
1020 | * We save/restore all registers marked with 'Driver', with the following | |
1021 | * exceptions: | |
1022 | * - Registers out of use, including also registers marked with 'Debug'. | |
1023 | * These have no effect on the driver's operation, so we don't save/restore | |
1024 | * them to reduce the overhead. | |
1025 | * - Registers that are fully setup by an initialization function called from | |
1026 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1027 | * - Registers that provide the right functionality with their reset defaults. | |
1028 | * | |
1029 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1030 | * ignored, we save/restore all others, practically treating the HW context as | |
1031 | * a black-box for the driver. Further investigation is needed to reduce the | |
1032 | * saved/restored registers even further, by following the same 3 criteria. | |
1033 | */ | |
1034 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1035 | { | |
1036 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1037 | int i; | |
1038 | ||
1039 | /* GAM 0x4000-0x4770 */ | |
1040 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1041 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1042 | s->arb_mode = I915_READ(ARB_MODE); | |
1043 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1044 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1045 | ||
1046 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1047 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); | |
1048 | ||
1049 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
1050 | s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
1051 | ||
1052 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1053 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1054 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1055 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1056 | ||
1057 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1058 | ||
1059 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1060 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1061 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1062 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1063 | ||
1064 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1065 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1066 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1067 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1068 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1069 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1070 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1071 | ||
1072 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1073 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1074 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1075 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1076 | s->ecobus = I915_READ(ECOBUS); | |
1077 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1078 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1079 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1080 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1081 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1082 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1083 | ||
1084 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1085 | s->gt_imr = I915_READ(GTIMR); | |
1086 | s->gt_ier = I915_READ(GTIER); | |
1087 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1088 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1089 | ||
1090 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1091 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); | |
1092 | ||
1093 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1094 | s->tilectl = I915_READ(TILECTL); | |
1095 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1096 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1097 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1098 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1099 | ||
1100 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1101 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1102 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
1103 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); | |
1104 | ||
1105 | /* | |
1106 | * Not saving any of: | |
1107 | * DFT, 0x9800-0x9EC0 | |
1108 | * SARB, 0xB000-0xB1FC | |
1109 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1110 | * PCI CFG | |
1111 | */ | |
1112 | } | |
1113 | ||
1114 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1115 | { | |
1116 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1117 | u32 val; | |
1118 | int i; | |
1119 | ||
1120 | /* GAM 0x4000-0x4770 */ | |
1121 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1122 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1123 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1124 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1125 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1126 | ||
1127 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1128 | I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); | |
1129 | ||
1130 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
1131 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count); | |
1132 | ||
1133 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1134 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1135 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1136 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1137 | ||
1138 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1139 | ||
1140 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1141 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1142 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1143 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1144 | ||
1145 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1146 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1147 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1148 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1149 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1150 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1151 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1152 | ||
1153 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1154 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1155 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1156 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1157 | I915_WRITE(ECOBUS, s->ecobus); | |
1158 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1159 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1160 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1161 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1162 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1163 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1164 | ||
1165 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1166 | I915_WRITE(GTIMR, s->gt_imr); | |
1167 | I915_WRITE(GTIER, s->gt_ier); | |
1168 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1169 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1170 | ||
1171 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1172 | I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); | |
1173 | ||
1174 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1175 | I915_WRITE(TILECTL, s->tilectl); | |
1176 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1177 | /* | |
1178 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1179 | * be restored, as they are used to control the s0ix suspend/resume | |
1180 | * sequence by the caller. | |
1181 | */ | |
1182 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1183 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1184 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1185 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1186 | ||
1187 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1188 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1189 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1190 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1191 | ||
1192 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1193 | ||
1194 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1195 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1196 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
1197 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); | |
1198 | } | |
1199 | ||
650ad970 ID |
1200 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1201 | { | |
1202 | u32 val; | |
1203 | int err; | |
1204 | ||
1205 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1206 | WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); | |
1207 | ||
1208 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) | |
1209 | /* Wait for a previous force-off to settle */ | |
1210 | if (force_on) { | |
8d4eee9c | 1211 | err = wait_for(!COND, 20); |
650ad970 ID |
1212 | if (err) { |
1213 | DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", | |
1214 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1215 | return err; | |
1216 | } | |
1217 | } | |
1218 | ||
1219 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1220 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1221 | if (force_on) | |
1222 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1223 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1224 | ||
1225 | if (!force_on) | |
1226 | return 0; | |
1227 | ||
8d4eee9c | 1228 | err = wait_for(COND, 20); |
650ad970 ID |
1229 | if (err) |
1230 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1231 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1232 | ||
1233 | return err; | |
1234 | #undef COND | |
1235 | } | |
1236 | ||
ddeea5b0 ID |
1237 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1238 | { | |
1239 | u32 val; | |
1240 | int err = 0; | |
1241 | ||
1242 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1243 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1244 | if (allow) | |
1245 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1246 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1247 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1248 | ||
1249 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1250 | allow) | |
1251 | err = wait_for(COND, 1); | |
1252 | if (err) | |
1253 | DRM_ERROR("timeout disabling GT waking\n"); | |
1254 | return err; | |
1255 | #undef COND | |
1256 | } | |
1257 | ||
1258 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1259 | bool wait_for_on) | |
1260 | { | |
1261 | u32 mask; | |
1262 | u32 val; | |
1263 | int err; | |
1264 | ||
1265 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1266 | val = wait_for_on ? mask : 0; | |
1267 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1268 | if (COND) | |
1269 | return 0; | |
1270 | ||
1271 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
1272 | wait_for_on ? "on" : "off", | |
1273 | I915_READ(VLV_GTLC_PW_STATUS)); | |
1274 | ||
1275 | /* | |
1276 | * RC6 transitioning can be delayed up to 2 msec (see | |
1277 | * valleyview_enable_rps), use 3 msec for safety. | |
1278 | */ | |
1279 | err = wait_for(COND, 3); | |
1280 | if (err) | |
1281 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
1282 | wait_for_on ? "on" : "off"); | |
1283 | ||
1284 | return err; | |
1285 | #undef COND | |
1286 | } | |
1287 | ||
1288 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1289 | { | |
1290 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1291 | return; | |
1292 | ||
1293 | DRM_ERROR("GT register access while GT waking disabled\n"); | |
1294 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); | |
1295 | } | |
1296 | ||
ebc32824 | 1297 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
1298 | { |
1299 | u32 mask; | |
1300 | int err; | |
1301 | ||
1302 | /* | |
1303 | * Bspec defines the following GT well on flags as debug only, so | |
1304 | * don't treat them as hard failures. | |
1305 | */ | |
1306 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1307 | ||
1308 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1309 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1310 | ||
1311 | vlv_check_no_gt_access(dev_priv); | |
1312 | ||
1313 | err = vlv_force_gfx_clock(dev_priv, true); | |
1314 | if (err) | |
1315 | goto err1; | |
1316 | ||
1317 | err = vlv_allow_gt_wake(dev_priv, false); | |
1318 | if (err) | |
1319 | goto err2; | |
1320 | vlv_save_gunit_s0ix_state(dev_priv); | |
1321 | ||
1322 | err = vlv_force_gfx_clock(dev_priv, false); | |
1323 | if (err) | |
1324 | goto err2; | |
1325 | ||
1326 | return 0; | |
1327 | ||
1328 | err2: | |
1329 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1330 | vlv_allow_gt_wake(dev_priv, true); | |
1331 | err1: | |
1332 | vlv_force_gfx_clock(dev_priv, false); | |
1333 | ||
1334 | return err; | |
1335 | } | |
1336 | ||
016970be SK |
1337 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1338 | bool rpm_resume) | |
ddeea5b0 ID |
1339 | { |
1340 | struct drm_device *dev = dev_priv->dev; | |
1341 | int err; | |
1342 | int ret; | |
1343 | ||
1344 | /* | |
1345 | * If any of the steps fail just try to continue, that's the best we | |
1346 | * can do at this point. Return the first error code (which will also | |
1347 | * leave RPM permanently disabled). | |
1348 | */ | |
1349 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1350 | ||
1351 | vlv_restore_gunit_s0ix_state(dev_priv); | |
1352 | ||
1353 | err = vlv_allow_gt_wake(dev_priv, true); | |
1354 | if (!ret) | |
1355 | ret = err; | |
1356 | ||
1357 | err = vlv_force_gfx_clock(dev_priv, false); | |
1358 | if (!ret) | |
1359 | ret = err; | |
1360 | ||
1361 | vlv_check_no_gt_access(dev_priv); | |
1362 | ||
016970be SK |
1363 | if (rpm_resume) { |
1364 | intel_init_clock_gating(dev); | |
1365 | i915_gem_restore_fences(dev); | |
1366 | } | |
ddeea5b0 ID |
1367 | |
1368 | return ret; | |
1369 | } | |
1370 | ||
97bea207 | 1371 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1372 | { |
1373 | struct pci_dev *pdev = to_pci_dev(device); | |
1374 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1376 | int ret; |
8a187455 | 1377 | |
aeab0b5a | 1378 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1379 | return -ENODEV; |
1380 | ||
604effb7 ID |
1381 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1382 | return -ENODEV; | |
1383 | ||
e998c40f | 1384 | assert_force_wake_inactive(dev_priv); |
8a187455 PZ |
1385 | |
1386 | DRM_DEBUG_KMS("Suspending device\n"); | |
1387 | ||
d6102977 ID |
1388 | /* |
1389 | * We could deadlock here in case another thread holding struct_mutex | |
1390 | * calls RPM suspend concurrently, since the RPM suspend will wait | |
1391 | * first for this RPM suspend to finish. In this case the concurrent | |
1392 | * RPM resume will be followed by its RPM suspend counterpart. Still | |
1393 | * for consistency return -EAGAIN, which will reschedule this suspend. | |
1394 | */ | |
1395 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1396 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); | |
1397 | /* | |
1398 | * Bump the expiration timestamp, otherwise the suspend won't | |
1399 | * be rescheduled. | |
1400 | */ | |
1401 | pm_runtime_mark_last_busy(device); | |
1402 | ||
1403 | return -EAGAIN; | |
1404 | } | |
1405 | /* | |
1406 | * We are safe here against re-faults, since the fault handler takes | |
1407 | * an RPM reference. | |
1408 | */ | |
1409 | i915_gem_release_all_mmaps(dev_priv); | |
1410 | mutex_unlock(&dev->struct_mutex); | |
1411 | ||
9486db61 ID |
1412 | /* |
1413 | * rps.work can't be rearmed here, since we get here only after making | |
1414 | * sure the GPU is idle and the RPS freq is set to the minimum. See | |
1415 | * intel_mark_idle(). | |
1416 | */ | |
1417 | cancel_work_sync(&dev_priv->rps.work); | |
b963291c | 1418 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 1419 | |
ebc32824 | 1420 | ret = intel_suspend_complete(dev_priv); |
0ab9cfeb ID |
1421 | if (ret) { |
1422 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
b963291c | 1423 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb ID |
1424 | |
1425 | return ret; | |
1426 | } | |
a8a8bd54 | 1427 | |
16a3d6ef | 1428 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
8a187455 | 1429 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1430 | |
1431 | /* | |
c8a0bd42 PZ |
1432 | * FIXME: We really should find a document that references the arguments |
1433 | * used below! | |
1fb2362b | 1434 | */ |
c8a0bd42 PZ |
1435 | if (IS_HASWELL(dev)) { |
1436 | /* | |
1437 | * current versions of firmware which depend on this opregion | |
1438 | * notification have repurposed the D1 definition to mean | |
1439 | * "runtime suspended" vs. what you would normally expect (D3) | |
1440 | * to distinguish it from notifications that might be sent via | |
1441 | * the suspend path. | |
1442 | */ | |
1443 | intel_opregion_notify_adapter(dev, PCI_D1); | |
1444 | } else { | |
1445 | /* | |
1446 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
1447 | * being detected, and the call we do at intel_runtime_resume() | |
1448 | * won't be able to restore them. Since PCI_D3hot matches the | |
1449 | * actual specification and appears to be working, use it. Let's | |
1450 | * assume the other non-Haswell platforms will stay the same as | |
1451 | * Broadwell. | |
1452 | */ | |
1453 | intel_opregion_notify_adapter(dev, PCI_D3hot); | |
1454 | } | |
8a187455 | 1455 | |
a8a8bd54 | 1456 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1457 | return 0; |
1458 | } | |
1459 | ||
97bea207 | 1460 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1461 | { |
1462 | struct pci_dev *pdev = to_pci_dev(device); | |
1463 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1465 | int ret; |
8a187455 | 1466 | |
604effb7 ID |
1467 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1468 | return -ENODEV; | |
8a187455 PZ |
1469 | |
1470 | DRM_DEBUG_KMS("Resuming device\n"); | |
1471 | ||
cd2e9e90 | 1472 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 PZ |
1473 | dev_priv->pm.suspended = false; |
1474 | ||
016970be | 1475 | ret = intel_resume_prepare(dev_priv, true); |
0ab9cfeb ID |
1476 | /* |
1477 | * No point of rolling back things in case of an error, as the best | |
1478 | * we can do is to hope that things will still work (and disable RPM). | |
1479 | */ | |
92b806d3 ID |
1480 | i915_gem_init_swizzling(dev); |
1481 | gen6_update_ring_freq(dev); | |
1482 | ||
b963291c | 1483 | intel_runtime_pm_enable_interrupts(dev_priv); |
9486db61 | 1484 | intel_reset_gt_powersave(dev); |
b5478bcd | 1485 | |
0ab9cfeb ID |
1486 | if (ret) |
1487 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1488 | else | |
1489 | DRM_DEBUG_KMS("Device resumed\n"); | |
1490 | ||
1491 | return ret; | |
8a187455 PZ |
1492 | } |
1493 | ||
016970be SK |
1494 | /* |
1495 | * This function implements common functionality of runtime and system | |
1496 | * suspend sequence. | |
1497 | */ | |
ebc32824 SK |
1498 | static int intel_suspend_complete(struct drm_i915_private *dev_priv) |
1499 | { | |
1500 | struct drm_device *dev = dev_priv->dev; | |
1501 | int ret; | |
1502 | ||
604effb7 | 1503 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ebc32824 | 1504 | ret = hsw_suspend_complete(dev_priv); |
604effb7 | 1505 | else if (IS_VALLEYVIEW(dev)) |
ebc32824 | 1506 | ret = vlv_suspend_complete(dev_priv); |
604effb7 ID |
1507 | else |
1508 | ret = 0; | |
ebc32824 SK |
1509 | |
1510 | return ret; | |
1511 | } | |
1512 | ||
016970be SK |
1513 | /* |
1514 | * This function implements common functionality of runtime and system | |
1515 | * resume sequence. Variable rpm_resume used for implementing different | |
1516 | * code paths. | |
1517 | */ | |
1518 | static int intel_resume_prepare(struct drm_i915_private *dev_priv, | |
1519 | bool rpm_resume) | |
ebc32824 SK |
1520 | { |
1521 | struct drm_device *dev = dev_priv->dev; | |
1522 | int ret; | |
1523 | ||
604effb7 | 1524 | if (IS_GEN6(dev)) |
016970be | 1525 | ret = snb_resume_prepare(dev_priv, rpm_resume); |
604effb7 | 1526 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
016970be | 1527 | ret = hsw_resume_prepare(dev_priv, rpm_resume); |
604effb7 | 1528 | else if (IS_VALLEYVIEW(dev)) |
016970be | 1529 | ret = vlv_resume_prepare(dev_priv, rpm_resume); |
604effb7 ID |
1530 | else |
1531 | ret = 0; | |
ebc32824 SK |
1532 | |
1533 | return ret; | |
1534 | } | |
1535 | ||
b4b78d12 | 1536 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 | 1537 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1538 | .suspend_late = i915_pm_suspend_late, |
1539 | .resume_early = i915_pm_resume_early, | |
0206e353 | 1540 | .resume = i915_pm_resume, |
36d61e67 ID |
1541 | .freeze = i915_pm_suspend, |
1542 | .freeze_late = i915_pm_suspend_late, | |
1543 | .thaw_early = i915_pm_resume_early, | |
1544 | .thaw = i915_pm_resume, | |
1545 | .poweroff = i915_pm_suspend, | |
da2bc1b9 | 1546 | .poweroff_late = i915_pm_suspend_late, |
76c4b250 | 1547 | .restore_early = i915_pm_resume_early, |
0206e353 | 1548 | .restore = i915_pm_resume, |
97bea207 PZ |
1549 | .runtime_suspend = intel_runtime_suspend, |
1550 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1551 | }; |
1552 | ||
78b68556 | 1553 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1554 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1555 | .open = drm_gem_vm_open, |
1556 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1557 | }; |
1558 | ||
e08e96de AV |
1559 | static const struct file_operations i915_driver_fops = { |
1560 | .owner = THIS_MODULE, | |
1561 | .open = drm_open, | |
1562 | .release = drm_release, | |
1563 | .unlocked_ioctl = drm_ioctl, | |
1564 | .mmap = drm_gem_mmap, | |
1565 | .poll = drm_poll, | |
e08e96de AV |
1566 | .read = drm_read, |
1567 | #ifdef CONFIG_COMPAT | |
1568 | .compat_ioctl = i915_compat_ioctl, | |
1569 | #endif | |
1570 | .llseek = noop_llseek, | |
1571 | }; | |
1572 | ||
1da177e4 | 1573 | static struct drm_driver driver = { |
0c54781b MW |
1574 | /* Don't use MTRRs here; the Xserver or userspace app should |
1575 | * deal with them for Intel hardware. | |
792d2b9a | 1576 | */ |
673a394b | 1577 | .driver_features = |
24986ee0 | 1578 | DRIVER_USE_AGP | |
10ba5012 KH |
1579 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1580 | DRIVER_RENDER, | |
22eae947 | 1581 | .load = i915_driver_load, |
ba8bbcf6 | 1582 | .unload = i915_driver_unload, |
673a394b | 1583 | .open = i915_driver_open, |
22eae947 DA |
1584 | .lastclose = i915_driver_lastclose, |
1585 | .preclose = i915_driver_preclose, | |
673a394b | 1586 | .postclose = i915_driver_postclose, |
915b4d11 | 1587 | .set_busid = drm_pci_set_busid, |
d8e29209 RW |
1588 | |
1589 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
fc49b3da | 1590 | .suspend = i915_suspend_legacy, |
76c4b250 | 1591 | .resume = i915_resume_legacy, |
d8e29209 | 1592 | |
cda17380 | 1593 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
1594 | .master_create = i915_master_create, |
1595 | .master_destroy = i915_master_destroy, | |
955b12de | 1596 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1597 | .debugfs_init = i915_debugfs_init, |
1598 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1599 | #endif |
673a394b | 1600 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1601 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1602 | |
1603 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1604 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1605 | .gem_prime_export = i915_gem_prime_export, | |
1606 | .gem_prime_import = i915_gem_prime_import, | |
1607 | ||
ff72145b DA |
1608 | .dumb_create = i915_gem_dumb_create, |
1609 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 1610 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1611 | .ioctls = i915_ioctls, |
e08e96de | 1612 | .fops = &i915_driver_fops, |
22eae947 DA |
1613 | .name = DRIVER_NAME, |
1614 | .desc = DRIVER_DESC, | |
1615 | .date = DRIVER_DATE, | |
1616 | .major = DRIVER_MAJOR, | |
1617 | .minor = DRIVER_MINOR, | |
1618 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1619 | }; |
1620 | ||
8410ea3b DA |
1621 | static struct pci_driver i915_pci_driver = { |
1622 | .name = DRIVER_NAME, | |
1623 | .id_table = pciidlist, | |
1624 | .probe = i915_pci_probe, | |
1625 | .remove = i915_pci_remove, | |
1626 | .driver.pm = &i915_pm_ops, | |
1627 | }; | |
1628 | ||
1da177e4 LT |
1629 | static int __init i915_init(void) |
1630 | { | |
1631 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1632 | |
1633 | /* | |
1634 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1635 | * explicitly disabled with the module pararmeter. | |
1636 | * | |
1637 | * Otherwise, just follow the parameter (defaulting to off). | |
1638 | * | |
1639 | * Allow optional vga_text_mode_force boot option to override | |
1640 | * the default behavior. | |
1641 | */ | |
1642 | #if defined(CONFIG_DRM_I915_KMS) | |
d330a953 | 1643 | if (i915.modeset != 0) |
79e53945 JB |
1644 | driver.driver_features |= DRIVER_MODESET; |
1645 | #endif | |
d330a953 | 1646 | if (i915.modeset == 1) |
79e53945 JB |
1647 | driver.driver_features |= DRIVER_MODESET; |
1648 | ||
1649 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 1650 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
1651 | driver.driver_features &= ~DRIVER_MODESET; |
1652 | #endif | |
1653 | ||
b30324ad | 1654 | if (!(driver.driver_features & DRIVER_MODESET)) { |
3885c6bb | 1655 | driver.get_vblank_timestamp = NULL; |
b30324ad DV |
1656 | #ifndef CONFIG_DRM_I915_UMS |
1657 | /* Silently fail loading to not upset userspace. */ | |
c9cd7b65 | 1658 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
b30324ad DV |
1659 | return 0; |
1660 | #endif | |
1661 | } | |
3885c6bb | 1662 | |
8410ea3b | 1663 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1664 | } |
1665 | ||
1666 | static void __exit i915_exit(void) | |
1667 | { | |
b33ecdd1 DV |
1668 | #ifndef CONFIG_DRM_I915_UMS |
1669 | if (!(driver.driver_features & DRIVER_MODESET)) | |
1670 | return; /* Never loaded a driver. */ | |
1671 | #endif | |
1672 | ||
8410ea3b | 1673 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1674 | } |
1675 | ||
1676 | module_init(i915_init); | |
1677 | module_exit(i915_exit); | |
1678 | ||
0a6d1631 | 1679 | MODULE_AUTHOR("Tungsten Graphics, Inc."); |
1eab9234 | 1680 | MODULE_AUTHOR("Intel Corporation"); |
0a6d1631 | 1681 | |
b5e89ed5 | 1682 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 | 1683 | MODULE_LICENSE("GPL and additional rights"); |