]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
585fb111 | 36 | #include "i915_reg.h" |
79e53945 | 37 | #include "intel_bios.h" |
8187a2b7 | 38 | #include "intel_ringbuffer.h" |
b20385f1 | 39 | #include "intel_lrc.h" |
0260c420 | 40 | #include "i915_gem_gtt.h" |
564ddb2f | 41 | #include "i915_gem_render_state.h" |
0839ccb8 | 42 | #include <linux/io-mapping.h> |
f899fc64 | 43 | #include <linux/i2c.h> |
c167a6fc | 44 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 45 | #include <drm/intel-gtt.h> |
ba8286fa | 46 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
d9fc9413 | 47 | #include <drm/drm_gem.h> |
aaa6fd2a | 48 | #include <linux/backlight.h> |
5cc9ed4b | 49 | #include <linux/hashtable.h> |
2911a35b | 50 | #include <linux/intel-iommu.h> |
742cbee8 | 51 | #include <linux/kref.h> |
9ee32fea | 52 | #include <linux/pm_qos.h> |
33a732f4 | 53 | #include "intel_guc.h" |
585fb111 | 54 | |
1da177e4 LT |
55 | /* General customization: |
56 | */ | |
57 | ||
1da177e4 LT |
58 | #define DRIVER_NAME "i915" |
59 | #define DRIVER_DESC "Intel Graphics" | |
01302d4d | 60 | #define DRIVER_DATE "20150828" |
1da177e4 | 61 | |
c883ef1b | 62 | #undef WARN_ON |
5f77eeb0 DV |
63 | /* Many gcc seem to no see through this and fall over :( */ |
64 | #if 0 | |
65 | #define WARN_ON(x) ({ \ | |
66 | bool __i915_warn_cond = (x); \ | |
67 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
68 | BUILD_BUG_ON(__i915_warn_cond); \ | |
69 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
70 | #else | |
4eee4920 | 71 | #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x ) |
5f77eeb0 DV |
72 | #endif |
73 | ||
cd9bfacb | 74 | #undef WARN_ON_ONCE |
4eee4920 | 75 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x ) |
cd9bfacb | 76 | |
5f77eeb0 DV |
77 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
78 | (long) (x), __func__); | |
c883ef1b | 79 | |
e2c719b7 RC |
80 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
81 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
82 | * which may not necessarily be a user visible problem. This will either | |
83 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
84 | * enable distros and users to tailor their preferred amount of i915 abrt | |
85 | * spam. | |
86 | */ | |
87 | #define I915_STATE_WARN(condition, format...) ({ \ | |
88 | int __ret_warn_on = !!(condition); \ | |
89 | if (unlikely(__ret_warn_on)) { \ | |
90 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 91 | WARN(1, format); \ |
e2c719b7 RC |
92 | else \ |
93 | DRM_ERROR(format); \ | |
94 | } \ | |
95 | unlikely(__ret_warn_on); \ | |
96 | }) | |
97 | ||
98 | #define I915_STATE_WARN_ON(condition) ({ \ | |
99 | int __ret_warn_on = !!(condition); \ | |
100 | if (unlikely(__ret_warn_on)) { \ | |
101 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 102 | WARN(1, "WARN_ON(" #condition ")\n"); \ |
e2c719b7 RC |
103 | else \ |
104 | DRM_ERROR("WARN_ON(" #condition ")\n"); \ | |
105 | } \ | |
106 | unlikely(__ret_warn_on); \ | |
107 | }) | |
c883ef1b | 108 | |
317c35d1 | 109 | enum pipe { |
752aa88a | 110 | INVALID_PIPE = -1, |
317c35d1 JB |
111 | PIPE_A = 0, |
112 | PIPE_B, | |
9db4a9c7 | 113 | PIPE_C, |
a57c774a AK |
114 | _PIPE_EDP, |
115 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 116 | }; |
9db4a9c7 | 117 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 118 | |
a5c961d1 PZ |
119 | enum transcoder { |
120 | TRANSCODER_A = 0, | |
121 | TRANSCODER_B, | |
122 | TRANSCODER_C, | |
a57c774a AK |
123 | TRANSCODER_EDP, |
124 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
125 | }; |
126 | #define transcoder_name(t) ((t) + 'A') | |
127 | ||
84139d1e DL |
128 | /* |
129 | * This is the maximum (across all platforms) number of planes (primary + | |
130 | * sprites) that can be active at the same time on one pipe. | |
131 | * | |
132 | * This value doesn't count the cursor plane. | |
133 | */ | |
8232edb5 | 134 | #define I915_MAX_PLANES 4 |
84139d1e | 135 | |
80824003 JB |
136 | enum plane { |
137 | PLANE_A = 0, | |
138 | PLANE_B, | |
9db4a9c7 | 139 | PLANE_C, |
80824003 | 140 | }; |
9db4a9c7 | 141 | #define plane_name(p) ((p) + 'A') |
52440211 | 142 | |
d615a166 | 143 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 144 | |
2b139522 ED |
145 | enum port { |
146 | PORT_A = 0, | |
147 | PORT_B, | |
148 | PORT_C, | |
149 | PORT_D, | |
150 | PORT_E, | |
151 | I915_MAX_PORTS | |
152 | }; | |
153 | #define port_name(p) ((p) + 'A') | |
154 | ||
a09caddd | 155 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
156 | |
157 | enum dpio_channel { | |
158 | DPIO_CH0, | |
159 | DPIO_CH1 | |
160 | }; | |
161 | ||
162 | enum dpio_phy { | |
163 | DPIO_PHY0, | |
164 | DPIO_PHY1 | |
165 | }; | |
166 | ||
b97186f0 PZ |
167 | enum intel_display_power_domain { |
168 | POWER_DOMAIN_PIPE_A, | |
169 | POWER_DOMAIN_PIPE_B, | |
170 | POWER_DOMAIN_PIPE_C, | |
171 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
172 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
173 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
174 | POWER_DOMAIN_TRANSCODER_A, | |
175 | POWER_DOMAIN_TRANSCODER_B, | |
176 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 177 | POWER_DOMAIN_TRANSCODER_EDP, |
319be8ae ID |
178 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
179 | POWER_DOMAIN_PORT_DDI_A_4_LANES, | |
180 | POWER_DOMAIN_PORT_DDI_B_2_LANES, | |
181 | POWER_DOMAIN_PORT_DDI_B_4_LANES, | |
182 | POWER_DOMAIN_PORT_DDI_C_2_LANES, | |
183 | POWER_DOMAIN_PORT_DDI_C_4_LANES, | |
184 | POWER_DOMAIN_PORT_DDI_D_2_LANES, | |
185 | POWER_DOMAIN_PORT_DDI_D_4_LANES, | |
186 | POWER_DOMAIN_PORT_DSI, | |
187 | POWER_DOMAIN_PORT_CRT, | |
188 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 189 | POWER_DOMAIN_VGA, |
fbeeaa23 | 190 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 191 | POWER_DOMAIN_PLLS, |
1407121a S |
192 | POWER_DOMAIN_AUX_A, |
193 | POWER_DOMAIN_AUX_B, | |
194 | POWER_DOMAIN_AUX_C, | |
195 | POWER_DOMAIN_AUX_D, | |
baa70707 | 196 | POWER_DOMAIN_INIT, |
bddc7645 ID |
197 | |
198 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
199 | }; |
200 | ||
201 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
202 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
203 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
204 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
205 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
206 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 207 | |
1d843f9d EE |
208 | enum hpd_pin { |
209 | HPD_NONE = 0, | |
1d843f9d EE |
210 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
211 | HPD_CRT, | |
212 | HPD_SDVO_B, | |
213 | HPD_SDVO_C, | |
cc24fcdc | 214 | HPD_PORT_A, |
1d843f9d EE |
215 | HPD_PORT_B, |
216 | HPD_PORT_C, | |
217 | HPD_PORT_D, | |
218 | HPD_NUM_PINS | |
219 | }; | |
220 | ||
c91711f9 JN |
221 | #define for_each_hpd_pin(__pin) \ |
222 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
223 | ||
5fcece80 JN |
224 | struct i915_hotplug { |
225 | struct work_struct hotplug_work; | |
226 | ||
227 | struct { | |
228 | unsigned long last_jiffies; | |
229 | int count; | |
230 | enum { | |
231 | HPD_ENABLED = 0, | |
232 | HPD_DISABLED = 1, | |
233 | HPD_MARK_DISABLED = 2 | |
234 | } state; | |
235 | } stats[HPD_NUM_PINS]; | |
236 | u32 event_bits; | |
237 | struct delayed_work reenable_work; | |
238 | ||
239 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
240 | u32 long_port_mask; | |
241 | u32 short_port_mask; | |
242 | struct work_struct dig_port_work; | |
243 | ||
244 | /* | |
245 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
246 | * the non-DP HPD could block the workqueue on a mode config | |
247 | * mutex getting, that userspace may have taken. However | |
248 | * userspace is waiting on the DP workqueue to run which is | |
249 | * blocked behind the non-DP one. | |
250 | */ | |
251 | struct workqueue_struct *dp_wq; | |
252 | }; | |
253 | ||
2a2d5482 CW |
254 | #define I915_GEM_GPU_DOMAINS \ |
255 | (I915_GEM_DOMAIN_RENDER | \ | |
256 | I915_GEM_DOMAIN_SAMPLER | \ | |
257 | I915_GEM_DOMAIN_COMMAND | \ | |
258 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
259 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 260 | |
055e393f DL |
261 | #define for_each_pipe(__dev_priv, __p) \ |
262 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
dd740780 DL |
263 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
264 | for ((__p) = 0; \ | |
265 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
266 | (__p)++) | |
3bdcfc0c DL |
267 | #define for_each_sprite(__dev_priv, __p, __s) \ |
268 | for ((__s) = 0; \ | |
269 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
270 | (__s)++) | |
9db4a9c7 | 271 | |
d79b814d DL |
272 | #define for_each_crtc(dev, crtc) \ |
273 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
274 | ||
27321ae8 ML |
275 | #define for_each_intel_plane(dev, intel_plane) \ |
276 | list_for_each_entry(intel_plane, \ | |
277 | &dev->mode_config.plane_list, \ | |
278 | base.head) | |
279 | ||
262cd2e1 VS |
280 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
281 | list_for_each_entry(intel_plane, \ | |
282 | &(dev)->mode_config.plane_list, \ | |
283 | base.head) \ | |
284 | if ((intel_plane)->pipe == (intel_crtc)->pipe) | |
285 | ||
d063ae48 DL |
286 | #define for_each_intel_crtc(dev, intel_crtc) \ |
287 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
288 | ||
b2784e15 DL |
289 | #define for_each_intel_encoder(dev, intel_encoder) \ |
290 | list_for_each_entry(intel_encoder, \ | |
291 | &(dev)->mode_config.encoder_list, \ | |
292 | base.head) | |
293 | ||
3a3371ff ACO |
294 | #define for_each_intel_connector(dev, intel_connector) \ |
295 | list_for_each_entry(intel_connector, \ | |
296 | &dev->mode_config.connector_list, \ | |
297 | base.head) | |
298 | ||
6c2b7c12 DV |
299 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
300 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
301 | if ((intel_encoder)->base.crtc == (__crtc)) | |
302 | ||
53f5e3ca JB |
303 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
304 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
305 | if ((intel_connector)->base.encoder == (__encoder)) | |
306 | ||
b04c5bd6 BF |
307 | #define for_each_power_domain(domain, mask) \ |
308 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
309 | if ((1 << (domain)) & (mask)) | |
310 | ||
e7b903d2 | 311 | struct drm_i915_private; |
ad46cb53 | 312 | struct i915_mm_struct; |
5cc9ed4b | 313 | struct i915_mmu_object; |
e7b903d2 | 314 | |
a6f766f3 CW |
315 | struct drm_i915_file_private { |
316 | struct drm_i915_private *dev_priv; | |
317 | struct drm_file *file; | |
318 | ||
319 | struct { | |
320 | spinlock_t lock; | |
321 | struct list_head request_list; | |
d0bc54f2 CW |
322 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
323 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
324 | * (when using lax throttling for the frontbuffer). We also use it to | |
325 | * offer free GPU waitboosts for severely congested workloads. | |
326 | */ | |
327 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
328 | } mm; |
329 | struct idr context_idr; | |
330 | ||
2e1b8730 CW |
331 | struct intel_rps_client { |
332 | struct list_head link; | |
333 | unsigned boosts; | |
334 | } rps; | |
a6f766f3 | 335 | |
2e1b8730 | 336 | struct intel_engine_cs *bsd_ring; |
a6f766f3 CW |
337 | }; |
338 | ||
46edb027 DV |
339 | enum intel_dpll_id { |
340 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
341 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
342 | DPLL_ID_PCH_PLL_A = 0, |
343 | DPLL_ID_PCH_PLL_B = 1, | |
429d47d5 | 344 | /* hsw/bdw */ |
9cd86933 DV |
345 | DPLL_ID_WRPLL1 = 0, |
346 | DPLL_ID_WRPLL2 = 1, | |
429d47d5 S |
347 | /* skl */ |
348 | DPLL_ID_SKL_DPLL1 = 0, | |
349 | DPLL_ID_SKL_DPLL2 = 1, | |
350 | DPLL_ID_SKL_DPLL3 = 2, | |
46edb027 | 351 | }; |
429d47d5 | 352 | #define I915_NUM_PLLS 3 |
46edb027 | 353 | |
5358901f | 354 | struct intel_dpll_hw_state { |
dcfc3552 | 355 | /* i9xx, pch plls */ |
66e985c0 | 356 | uint32_t dpll; |
8bcc2795 | 357 | uint32_t dpll_md; |
66e985c0 DV |
358 | uint32_t fp0; |
359 | uint32_t fp1; | |
dcfc3552 DL |
360 | |
361 | /* hsw, bdw */ | |
d452c5b6 | 362 | uint32_t wrpll; |
d1a2dc78 S |
363 | |
364 | /* skl */ | |
365 | /* | |
366 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in | |
71cd8423 | 367 | * lower part of ctrl1 and they get shifted into position when writing |
d1a2dc78 S |
368 | * the register. This allows us to easily compare the state to share |
369 | * the DPLL. | |
370 | */ | |
371 | uint32_t ctrl1; | |
372 | /* HDMI only, 0 when used for DP */ | |
373 | uint32_t cfgcr1, cfgcr2; | |
dfb82408 S |
374 | |
375 | /* bxt */ | |
05712c15 ID |
376 | uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, |
377 | pcsdw12; | |
5358901f DV |
378 | }; |
379 | ||
3e369b76 | 380 | struct intel_shared_dpll_config { |
1e6f2ddc | 381 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
3e369b76 ACO |
382 | struct intel_dpll_hw_state hw_state; |
383 | }; | |
384 | ||
385 | struct intel_shared_dpll { | |
386 | struct intel_shared_dpll_config config; | |
8bd31e67 | 387 | |
ee7b9f93 JB |
388 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
389 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
390 | const char *name; |
391 | /* should match the index in the dev_priv->shared_dplls array */ | |
392 | enum intel_dpll_id id; | |
96f6128c DV |
393 | /* The mode_set hook is optional and should be used together with the |
394 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
395 | void (*mode_set)(struct drm_i915_private *dev_priv, |
396 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
397 | void (*enable)(struct drm_i915_private *dev_priv, |
398 | struct intel_shared_dpll *pll); | |
399 | void (*disable)(struct drm_i915_private *dev_priv, | |
400 | struct intel_shared_dpll *pll); | |
5358901f DV |
401 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
402 | struct intel_shared_dpll *pll, | |
403 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 404 | }; |
ee7b9f93 | 405 | |
429d47d5 S |
406 | #define SKL_DPLL0 0 |
407 | #define SKL_DPLL1 1 | |
408 | #define SKL_DPLL2 2 | |
409 | #define SKL_DPLL3 3 | |
410 | ||
e69d0bc1 DV |
411 | /* Used by dp and fdi links */ |
412 | struct intel_link_m_n { | |
413 | uint32_t tu; | |
414 | uint32_t gmch_m; | |
415 | uint32_t gmch_n; | |
416 | uint32_t link_m; | |
417 | uint32_t link_n; | |
418 | }; | |
419 | ||
420 | void intel_link_compute_m_n(int bpp, int nlanes, | |
421 | int pixel_clock, int link_clock, | |
422 | struct intel_link_m_n *m_n); | |
423 | ||
1da177e4 LT |
424 | /* Interface history: |
425 | * | |
426 | * 1.1: Original. | |
0d6aa60b DA |
427 | * 1.2: Add Power Management |
428 | * 1.3: Add vblank support | |
de227f5f | 429 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 430 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
431 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
432 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
433 | */ |
434 | #define DRIVER_MAJOR 1 | |
2228ed67 | 435 | #define DRIVER_MINOR 6 |
1da177e4 LT |
436 | #define DRIVER_PATCHLEVEL 0 |
437 | ||
23bc5982 | 438 | #define WATCH_LISTS 0 |
673a394b | 439 | |
0a3e67a4 JB |
440 | struct opregion_header; |
441 | struct opregion_acpi; | |
442 | struct opregion_swsci; | |
443 | struct opregion_asle; | |
444 | ||
8ee1c3db | 445 | struct intel_opregion { |
5bc4418b BW |
446 | struct opregion_header __iomem *header; |
447 | struct opregion_acpi __iomem *acpi; | |
448 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
449 | u32 swsci_gbda_sub_functions; |
450 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
451 | struct opregion_asle __iomem *asle; |
452 | void __iomem *vbt; | |
01fe9dbd | 453 | u32 __iomem *lid_state; |
91a60f20 | 454 | struct work_struct asle_work; |
8ee1c3db | 455 | }; |
44834a67 | 456 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 457 | |
6ef3d427 CW |
458 | struct intel_overlay; |
459 | struct intel_overlay_error_state; | |
460 | ||
de151cf6 | 461 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
462 | #define I915_MAX_NUM_FENCES 32 |
463 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
464 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
465 | |
466 | struct drm_i915_fence_reg { | |
007cc8ac | 467 | struct list_head lru_list; |
caea7476 | 468 | struct drm_i915_gem_object *obj; |
1690e1eb | 469 | int pin_count; |
de151cf6 | 470 | }; |
7c1c2871 | 471 | |
9b9d172d | 472 | struct sdvo_device_mapping { |
e957d772 | 473 | u8 initialized; |
9b9d172d | 474 | u8 dvo_port; |
475 | u8 slave_addr; | |
476 | u8 dvo_wiring; | |
e957d772 | 477 | u8 i2c_pin; |
b1083333 | 478 | u8 ddc_pin; |
9b9d172d | 479 | }; |
480 | ||
c4a1d9e4 CW |
481 | struct intel_display_error_state; |
482 | ||
63eeaf38 | 483 | struct drm_i915_error_state { |
742cbee8 | 484 | struct kref ref; |
585b0288 BW |
485 | struct timeval time; |
486 | ||
cb383002 | 487 | char error_msg[128]; |
eb5be9d0 | 488 | int iommu; |
48b031e3 | 489 | u32 reset_count; |
62d5d69b | 490 | u32 suspend_count; |
cb383002 | 491 | |
585b0288 | 492 | /* Generic register state */ |
63eeaf38 JB |
493 | u32 eir; |
494 | u32 pgtbl_er; | |
be998e2e | 495 | u32 ier; |
885ea5a8 | 496 | u32 gtier[4]; |
b9a3906b | 497 | u32 ccid; |
0f3b6849 CW |
498 | u32 derrmr; |
499 | u32 forcewake; | |
585b0288 BW |
500 | u32 error; /* gen6+ */ |
501 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
502 | u32 fault_data0; /* gen8, gen9 */ |
503 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 504 | u32 done_reg; |
91ec5d11 BW |
505 | u32 gac_eco; |
506 | u32 gam_ecochk; | |
507 | u32 gab_ctl; | |
508 | u32 gfx_mode; | |
585b0288 | 509 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
510 | u64 fence[I915_MAX_NUM_FENCES]; |
511 | struct intel_overlay_error_state *overlay; | |
512 | struct intel_display_error_state *display; | |
0ca36d78 | 513 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 514 | |
52d39a21 | 515 | struct drm_i915_error_ring { |
372fbb8e | 516 | bool valid; |
362b8af7 BW |
517 | /* Software tracked state */ |
518 | bool waiting; | |
519 | int hangcheck_score; | |
520 | enum intel_ring_hangcheck_action hangcheck_action; | |
521 | int num_requests; | |
522 | ||
523 | /* our own tracking of ring head and tail */ | |
524 | u32 cpu_ring_head; | |
525 | u32 cpu_ring_tail; | |
526 | ||
527 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
528 | ||
529 | /* Register state */ | |
94f8cf10 | 530 | u32 start; |
362b8af7 BW |
531 | u32 tail; |
532 | u32 head; | |
533 | u32 ctl; | |
534 | u32 hws; | |
535 | u32 ipeir; | |
536 | u32 ipehr; | |
537 | u32 instdone; | |
362b8af7 BW |
538 | u32 bbstate; |
539 | u32 instpm; | |
540 | u32 instps; | |
541 | u32 seqno; | |
542 | u64 bbaddr; | |
50877445 | 543 | u64 acthd; |
362b8af7 | 544 | u32 fault_reg; |
13ffadd1 | 545 | u64 faddr; |
362b8af7 BW |
546 | u32 rc_psmi; /* sleep state */ |
547 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
548 | ||
52d39a21 CW |
549 | struct drm_i915_error_object { |
550 | int page_count; | |
e1f12325 | 551 | u64 gtt_offset; |
52d39a21 | 552 | u32 *pages[0]; |
ab0e7ff9 | 553 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 554 | |
52d39a21 CW |
555 | struct drm_i915_error_request { |
556 | long jiffies; | |
557 | u32 seqno; | |
ee4f42b1 | 558 | u32 tail; |
52d39a21 | 559 | } *requests; |
6c7a01ec BW |
560 | |
561 | struct { | |
562 | u32 gfx_mode; | |
563 | union { | |
564 | u64 pdp[4]; | |
565 | u32 pp_dir_base; | |
566 | }; | |
567 | } vm_info; | |
ab0e7ff9 CW |
568 | |
569 | pid_t pid; | |
570 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 571 | } ring[I915_NUM_RINGS]; |
3a448734 | 572 | |
9df30794 | 573 | struct drm_i915_error_buffer { |
a779e5ab | 574 | u32 size; |
9df30794 | 575 | u32 name; |
b4716185 | 576 | u32 rseqno[I915_NUM_RINGS], wseqno; |
e1f12325 | 577 | u64 gtt_offset; |
9df30794 CW |
578 | u32 read_domains; |
579 | u32 write_domain; | |
4b9de737 | 580 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
581 | s32 pinned:2; |
582 | u32 tiling:2; | |
583 | u32 dirty:1; | |
584 | u32 purgeable:1; | |
5cc9ed4b | 585 | u32 userptr:1; |
5d1333fc | 586 | s32 ring:4; |
f56383cb | 587 | u32 cache_level:3; |
95f5301d | 588 | } **active_bo, **pinned_bo; |
6c7a01ec | 589 | |
95f5301d | 590 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 591 | u32 vm_count; |
63eeaf38 JB |
592 | }; |
593 | ||
7bd688cd | 594 | struct intel_connector; |
820d2d77 | 595 | struct intel_encoder; |
5cec258b | 596 | struct intel_crtc_state; |
5724dbd1 | 597 | struct intel_initial_plane_config; |
0e8ffe1b | 598 | struct intel_crtc; |
ee9300bb DV |
599 | struct intel_limit; |
600 | struct dpll; | |
b8cecdf5 | 601 | |
e70236a8 | 602 | struct drm_i915_display_funcs { |
e70236a8 JB |
603 | int (*get_display_clock_speed)(struct drm_device *dev); |
604 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
605 | /** |
606 | * find_dpll() - Find the best values for the PLL | |
607 | * @limit: limits for the PLL | |
608 | * @crtc: current CRTC | |
609 | * @target: target frequency in kHz | |
610 | * @refclk: reference clock frequency in kHz | |
611 | * @match_clock: if provided, @best_clock P divider must | |
612 | * match the P divider from @match_clock | |
613 | * used for LVDS downclocking | |
614 | * @best_clock: best PLL values found | |
615 | * | |
616 | * Returns true on success, false on failure. | |
617 | */ | |
618 | bool (*find_dpll)(const struct intel_limit *limit, | |
a93e255f | 619 | struct intel_crtc_state *crtc_state, |
ee9300bb DV |
620 | int target, int refclk, |
621 | struct dpll *match_clock, | |
622 | struct dpll *best_clock); | |
46ba614c | 623 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
624 | void (*update_sprite_wm)(struct drm_plane *plane, |
625 | struct drm_crtc *crtc, | |
ed57cb8a DL |
626 | uint32_t sprite_width, uint32_t sprite_height, |
627 | int pixel_size, bool enable, bool scaled); | |
27c329ed ML |
628 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
629 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
630 | /* Returns the active state of the crtc, and if the crtc is active, |
631 | * fills out the pipe-config with the hw state. */ | |
632 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 633 | struct intel_crtc_state *); |
5724dbd1 DL |
634 | void (*get_initial_plane_config)(struct intel_crtc *, |
635 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
636 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
637 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
638 | void (*crtc_enable)(struct drm_crtc *crtc); |
639 | void (*crtc_disable)(struct drm_crtc *crtc); | |
69bfe1a9 JN |
640 | void (*audio_codec_enable)(struct drm_connector *connector, |
641 | struct intel_encoder *encoder, | |
642 | struct drm_display_mode *mode); | |
643 | void (*audio_codec_disable)(struct intel_encoder *encoder); | |
674cf967 | 644 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 645 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
646 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
647 | struct drm_framebuffer *fb, | |
ed8d1975 | 648 | struct drm_i915_gem_object *obj, |
6258fbe2 | 649 | struct drm_i915_gem_request *req, |
ed8d1975 | 650 | uint32_t flags); |
29b9bde6 DV |
651 | void (*update_primary_plane)(struct drm_crtc *crtc, |
652 | struct drm_framebuffer *fb, | |
653 | int x, int y); | |
20afbda2 | 654 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
655 | /* clock updates for mode set */ |
656 | /* cursor updates */ | |
657 | /* render clock increase/decrease */ | |
658 | /* display clock increase/decrease */ | |
659 | /* pll clock increase/decrease */ | |
7bd688cd | 660 | |
6517d273 | 661 | int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); |
7bd688cd JN |
662 | uint32_t (*get_backlight)(struct intel_connector *connector); |
663 | void (*set_backlight)(struct intel_connector *connector, | |
664 | uint32_t level); | |
665 | void (*disable_backlight)(struct intel_connector *connector); | |
666 | void (*enable_backlight)(struct intel_connector *connector); | |
e70236a8 JB |
667 | }; |
668 | ||
48c1026a MK |
669 | enum forcewake_domain_id { |
670 | FW_DOMAIN_ID_RENDER = 0, | |
671 | FW_DOMAIN_ID_BLITTER, | |
672 | FW_DOMAIN_ID_MEDIA, | |
673 | ||
674 | FW_DOMAIN_ID_COUNT | |
675 | }; | |
676 | ||
677 | enum forcewake_domains { | |
678 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
679 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
680 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
681 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
682 | FORCEWAKE_BLITTER | | |
683 | FORCEWAKE_MEDIA) | |
684 | }; | |
685 | ||
907b28c5 | 686 | struct intel_uncore_funcs { |
c8d9a590 | 687 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 688 | enum forcewake_domains domains); |
c8d9a590 | 689 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 690 | enum forcewake_domains domains); |
0b274481 BW |
691 | |
692 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
693 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
694 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
695 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
696 | ||
697 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
698 | uint8_t val, bool trace); | |
699 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
700 | uint16_t val, bool trace); | |
701 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
702 | uint32_t val, bool trace); | |
703 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
704 | uint64_t val, bool trace); | |
990bbdad CW |
705 | }; |
706 | ||
907b28c5 CW |
707 | struct intel_uncore { |
708 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
709 | ||
710 | struct intel_uncore_funcs funcs; | |
711 | ||
712 | unsigned fifo_count; | |
48c1026a | 713 | enum forcewake_domains fw_domains; |
b2cff0db CW |
714 | |
715 | struct intel_uncore_forcewake_domain { | |
716 | struct drm_i915_private *i915; | |
48c1026a | 717 | enum forcewake_domain_id id; |
b2cff0db CW |
718 | unsigned wake_count; |
719 | struct timer_list timer; | |
05a2fb15 MK |
720 | u32 reg_set; |
721 | u32 val_set; | |
722 | u32 val_clear; | |
723 | u32 reg_ack; | |
724 | u32 reg_post; | |
725 | u32 val_reset; | |
b2cff0db | 726 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
b2cff0db CW |
727 | }; |
728 | ||
729 | /* Iterate over initialised fw domains */ | |
730 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ | |
731 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
732 | (i__) < FW_DOMAIN_ID_COUNT; \ | |
733 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ | |
734 | if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) | |
735 | ||
736 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ | |
737 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) | |
907b28c5 | 738 | |
dc174300 SS |
739 | enum csr_state { |
740 | FW_UNINITIALIZED = 0, | |
741 | FW_LOADED, | |
742 | FW_FAILED | |
743 | }; | |
744 | ||
eb805623 DV |
745 | struct intel_csr { |
746 | const char *fw_path; | |
a7f749f9 | 747 | uint32_t *dmc_payload; |
eb805623 DV |
748 | uint32_t dmc_fw_size; |
749 | uint32_t mmio_count; | |
750 | uint32_t mmioaddr[8]; | |
751 | uint32_t mmiodata[8]; | |
dc174300 | 752 | enum csr_state state; |
eb805623 DV |
753 | }; |
754 | ||
79fc46df DL |
755 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
756 | func(is_mobile) sep \ | |
757 | func(is_i85x) sep \ | |
758 | func(is_i915g) sep \ | |
759 | func(is_i945gm) sep \ | |
760 | func(is_g33) sep \ | |
761 | func(need_gfx_hws) sep \ | |
762 | func(is_g4x) sep \ | |
763 | func(is_pineview) sep \ | |
764 | func(is_broadwater) sep \ | |
765 | func(is_crestline) sep \ | |
766 | func(is_ivybridge) sep \ | |
767 | func(is_valleyview) sep \ | |
768 | func(is_haswell) sep \ | |
7201c0b3 | 769 | func(is_skylake) sep \ |
b833d685 | 770 | func(is_preliminary) sep \ |
79fc46df DL |
771 | func(has_fbc) sep \ |
772 | func(has_pipe_cxsr) sep \ | |
773 | func(has_hotplug) sep \ | |
774 | func(cursor_needs_physical) sep \ | |
775 | func(has_overlay) sep \ | |
776 | func(overlay_needs_physical) sep \ | |
777 | func(supports_tv) sep \ | |
dd93be58 | 778 | func(has_llc) sep \ |
30568c45 DL |
779 | func(has_ddi) sep \ |
780 | func(has_fpga_dbg) | |
c96ea64e | 781 | |
a587f779 DL |
782 | #define DEFINE_FLAG(name) u8 name:1 |
783 | #define SEP_SEMICOLON ; | |
c96ea64e | 784 | |
cfdf1fa2 | 785 | struct intel_device_info { |
10fce67a | 786 | u32 display_mmio_offset; |
87f1f465 | 787 | u16 device_id; |
7eb552ae | 788 | u8 num_pipes:3; |
d615a166 | 789 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 790 | u8 gen; |
73ae478c | 791 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 792 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
793 | /* Register offsets for the various display pipes and transcoders */ |
794 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
795 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 796 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 797 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
798 | |
799 | /* Slice/subslice/EU info */ | |
800 | u8 slice_total; | |
801 | u8 subslice_total; | |
802 | u8 subslice_per_slice; | |
803 | u8 eu_total; | |
804 | u8 eu_per_subslice; | |
b7668791 DL |
805 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
806 | u8 subslice_7eu[3]; | |
3873218f JM |
807 | u8 has_slice_pg:1; |
808 | u8 has_subslice_pg:1; | |
809 | u8 has_eu_pg:1; | |
cfdf1fa2 KH |
810 | }; |
811 | ||
a587f779 DL |
812 | #undef DEFINE_FLAG |
813 | #undef SEP_SEMICOLON | |
814 | ||
7faf1ab2 DV |
815 | enum i915_cache_level { |
816 | I915_CACHE_NONE = 0, | |
350ec881 CW |
817 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
818 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
819 | caches, eg sampler/render caches, and the | |
820 | large Last-Level-Cache. LLC is coherent with | |
821 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 822 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
823 | }; |
824 | ||
e59ec13d MK |
825 | struct i915_ctx_hang_stats { |
826 | /* This context had batch pending when hang was declared */ | |
827 | unsigned batch_pending; | |
828 | ||
829 | /* This context had batch active when hang was declared */ | |
830 | unsigned batch_active; | |
be62acb4 MK |
831 | |
832 | /* Time when this context was last blamed for a GPU reset */ | |
833 | unsigned long guilty_ts; | |
834 | ||
676fa572 CW |
835 | /* If the contexts causes a second GPU hang within this time, |
836 | * it is permanently banned from submitting any more work. | |
837 | */ | |
838 | unsigned long ban_period_seconds; | |
839 | ||
be62acb4 MK |
840 | /* This context is banned to submit more work */ |
841 | bool banned; | |
e59ec13d | 842 | }; |
40521054 BW |
843 | |
844 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 845 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 DW |
846 | |
847 | #define CONTEXT_NO_ZEROMAP (1<<0) | |
31b7a88d OM |
848 | /** |
849 | * struct intel_context - as the name implies, represents a context. | |
850 | * @ref: reference count. | |
851 | * @user_handle: userspace tracking identity for this context. | |
852 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
853 | * @flags: context specific flags: |
854 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
855 | * @file_priv: filp associated with this context (NULL for global default |
856 | * context). | |
857 | * @hang_stats: information about the role of this context in possible GPU | |
858 | * hangs. | |
7df113e4 | 859 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
860 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
861 | * initialized (legacy ring submission mechanism only). | |
862 | * @link: link in the global list of contexts. | |
863 | * | |
864 | * Contexts are memory images used by the hardware to store copies of their | |
865 | * internal state. | |
866 | */ | |
273497e5 | 867 | struct intel_context { |
dce3271b | 868 | struct kref ref; |
821d66dd | 869 | int user_handle; |
3ccfd19d | 870 | uint8_t remap_slice; |
9ea4feec | 871 | struct drm_i915_private *i915; |
b1b38278 | 872 | int flags; |
40521054 | 873 | struct drm_i915_file_private *file_priv; |
e59ec13d | 874 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 875 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 876 | |
c9e003af | 877 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
878 | struct { |
879 | struct drm_i915_gem_object *rcs_state; | |
880 | bool initialized; | |
881 | } legacy_hw_ctx; | |
882 | ||
c9e003af | 883 | /* Execlists */ |
564ddb2f | 884 | bool rcs_initialized; |
c9e003af OM |
885 | struct { |
886 | struct drm_i915_gem_object *state; | |
84c2377f | 887 | struct intel_ringbuffer *ringbuf; |
a7cbedec | 888 | int pin_count; |
c9e003af OM |
889 | } engine[I915_NUM_RINGS]; |
890 | ||
a33afea5 | 891 | struct list_head link; |
40521054 BW |
892 | }; |
893 | ||
a4001f1b PZ |
894 | enum fb_op_origin { |
895 | ORIGIN_GTT, | |
896 | ORIGIN_CPU, | |
897 | ORIGIN_CS, | |
898 | ORIGIN_FLIP, | |
74b4ea1e | 899 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
900 | }; |
901 | ||
5c3fe8b0 | 902 | struct i915_fbc { |
25ad93fd PZ |
903 | /* This is always the inner lock when overlapping with struct_mutex and |
904 | * it's the outer lock when overlapping with stolen_lock. */ | |
905 | struct mutex lock; | |
60ee5cd2 | 906 | unsigned long uncompressed_size; |
5e59f717 | 907 | unsigned threshold; |
5c3fe8b0 | 908 | unsigned int fb_id; |
dbef0f15 PZ |
909 | unsigned int possible_framebuffer_bits; |
910 | unsigned int busy_bits; | |
e35fef21 | 911 | struct intel_crtc *crtc; |
5c3fe8b0 BW |
912 | int y; |
913 | ||
c4213885 | 914 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
915 | struct drm_mm_node *compressed_llb; |
916 | ||
da46f936 RV |
917 | bool false_color; |
918 | ||
9adccc60 PZ |
919 | /* Tracks whether the HW is actually enabled, not whether the feature is |
920 | * possible. */ | |
921 | bool enabled; | |
922 | ||
5c3fe8b0 BW |
923 | struct intel_fbc_work { |
924 | struct delayed_work work; | |
220285f2 | 925 | struct intel_crtc *crtc; |
5c3fe8b0 | 926 | struct drm_framebuffer *fb; |
5c3fe8b0 BW |
927 | } *fbc_work; |
928 | ||
29ebf90f CW |
929 | enum no_fbc_reason { |
930 | FBC_OK, /* FBC is enabled */ | |
931 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
932 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
933 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
934 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
935 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
936 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
937 | FBC_NOT_TILED, /* buffer not tiled */ | |
938 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
939 | FBC_MODULE_PARAM, | |
940 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
87f5ff01 | 941 | FBC_ROTATION, /* rotation is not supported */ |
89351085 | 942 | FBC_IN_DBG_MASTER, /* kernel debugger is active */ |
5c3fe8b0 | 943 | } no_fbc_reason; |
ff2a3117 | 944 | |
7733b49b | 945 | bool (*fbc_enabled)(struct drm_i915_private *dev_priv); |
220285f2 | 946 | void (*enable_fbc)(struct intel_crtc *crtc); |
7733b49b | 947 | void (*disable_fbc)(struct drm_i915_private *dev_priv); |
b5e50c3f JB |
948 | }; |
949 | ||
96178eeb VK |
950 | /** |
951 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
952 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
953 | * parsing for same resolution. | |
954 | */ | |
955 | enum drrs_refresh_rate_type { | |
956 | DRRS_HIGH_RR, | |
957 | DRRS_LOW_RR, | |
958 | DRRS_MAX_RR, /* RR count */ | |
959 | }; | |
960 | ||
961 | enum drrs_support_type { | |
962 | DRRS_NOT_SUPPORTED = 0, | |
963 | STATIC_DRRS_SUPPORT = 1, | |
964 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
965 | }; |
966 | ||
2807cf69 | 967 | struct intel_dp; |
96178eeb VK |
968 | struct i915_drrs { |
969 | struct mutex mutex; | |
970 | struct delayed_work work; | |
971 | struct intel_dp *dp; | |
972 | unsigned busy_frontbuffer_bits; | |
973 | enum drrs_refresh_rate_type refresh_rate_type; | |
974 | enum drrs_support_type type; | |
975 | }; | |
976 | ||
a031d709 | 977 | struct i915_psr { |
f0355c4a | 978 | struct mutex lock; |
a031d709 RV |
979 | bool sink_support; |
980 | bool source_ok; | |
2807cf69 | 981 | struct intel_dp *enabled; |
7c8f8a70 RV |
982 | bool active; |
983 | struct delayed_work work; | |
9ca15301 | 984 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
985 | bool psr2_support; |
986 | bool aux_frame_sync; | |
3f51e471 | 987 | }; |
5c3fe8b0 | 988 | |
3bad0781 | 989 | enum intel_pch { |
f0350830 | 990 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
991 | PCH_IBX, /* Ibexpeak PCH */ |
992 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 993 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 994 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 995 | PCH_NOP, |
3bad0781 ZW |
996 | }; |
997 | ||
988d6ee8 PZ |
998 | enum intel_sbi_destination { |
999 | SBI_ICLK, | |
1000 | SBI_MPHY, | |
1001 | }; | |
1002 | ||
b690e96c | 1003 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 1004 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1005 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1006 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 1007 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 1008 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 1009 | |
8be48d92 | 1010 | struct intel_fbdev; |
1630fe75 | 1011 | struct intel_fbc_work; |
38651674 | 1012 | |
c2b9152f DV |
1013 | struct intel_gmbus { |
1014 | struct i2c_adapter adapter; | |
f2ce9faf | 1015 | u32 force_bit; |
c2b9152f | 1016 | u32 reg0; |
36c785f0 | 1017 | u32 gpio_reg; |
c167a6fc | 1018 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1019 | struct drm_i915_private *dev_priv; |
1020 | }; | |
1021 | ||
f4c956ad | 1022 | struct i915_suspend_saved_registers { |
e948e994 | 1023 | u32 saveDSPARB; |
ba8bbcf6 | 1024 | u32 saveLVDS; |
585fb111 JB |
1025 | u32 savePP_ON_DELAYS; |
1026 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
1027 | u32 savePP_ON; |
1028 | u32 savePP_OFF; | |
1029 | u32 savePP_CONTROL; | |
585fb111 | 1030 | u32 savePP_DIVISOR; |
ba8bbcf6 | 1031 | u32 saveFBC_CONTROL; |
1f84e550 | 1032 | u32 saveCACHE_MODE_0; |
1f84e550 | 1033 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1034 | u32 saveSWF0[16]; |
1035 | u32 saveSWF1[16]; | |
1036 | u32 saveSWF2[3]; | |
4b9de737 | 1037 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1038 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1039 | u16 saveGCDGMBUS; |
f4c956ad | 1040 | }; |
c85aa885 | 1041 | |
ddeea5b0 ID |
1042 | struct vlv_s0ix_state { |
1043 | /* GAM */ | |
1044 | u32 wr_watermark; | |
1045 | u32 gfx_prio_ctrl; | |
1046 | u32 arb_mode; | |
1047 | u32 gfx_pend_tlb0; | |
1048 | u32 gfx_pend_tlb1; | |
1049 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1050 | u32 media_max_req_count; | |
1051 | u32 gfx_max_req_count; | |
1052 | u32 render_hwsp; | |
1053 | u32 ecochk; | |
1054 | u32 bsd_hwsp; | |
1055 | u32 blt_hwsp; | |
1056 | u32 tlb_rd_addr; | |
1057 | ||
1058 | /* MBC */ | |
1059 | u32 g3dctl; | |
1060 | u32 gsckgctl; | |
1061 | u32 mbctl; | |
1062 | ||
1063 | /* GCP */ | |
1064 | u32 ucgctl1; | |
1065 | u32 ucgctl3; | |
1066 | u32 rcgctl1; | |
1067 | u32 rcgctl2; | |
1068 | u32 rstctl; | |
1069 | u32 misccpctl; | |
1070 | ||
1071 | /* GPM */ | |
1072 | u32 gfxpause; | |
1073 | u32 rpdeuhwtc; | |
1074 | u32 rpdeuc; | |
1075 | u32 ecobus; | |
1076 | u32 pwrdwnupctl; | |
1077 | u32 rp_down_timeout; | |
1078 | u32 rp_deucsw; | |
1079 | u32 rcubmabdtmr; | |
1080 | u32 rcedata; | |
1081 | u32 spare2gh; | |
1082 | ||
1083 | /* Display 1 CZ domain */ | |
1084 | u32 gt_imr; | |
1085 | u32 gt_ier; | |
1086 | u32 pm_imr; | |
1087 | u32 pm_ier; | |
1088 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1089 | ||
1090 | /* GT SA CZ domain */ | |
1091 | u32 tilectl; | |
1092 | u32 gt_fifoctl; | |
1093 | u32 gtlc_wake_ctrl; | |
1094 | u32 gtlc_survive; | |
1095 | u32 pmwgicz; | |
1096 | ||
1097 | /* Display 2 CZ domain */ | |
1098 | u32 gu_ctl0; | |
1099 | u32 gu_ctl1; | |
9c25210f | 1100 | u32 pcbr; |
ddeea5b0 ID |
1101 | u32 clock_gate_dis2; |
1102 | }; | |
1103 | ||
bf225f20 CW |
1104 | struct intel_rps_ei { |
1105 | u32 cz_clock; | |
1106 | u32 render_c0; | |
1107 | u32 media_c0; | |
31685c25 D |
1108 | }; |
1109 | ||
c85aa885 | 1110 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1111 | /* |
1112 | * work, interrupts_enabled and pm_iir are protected by | |
1113 | * dev_priv->irq_lock | |
1114 | */ | |
c85aa885 | 1115 | struct work_struct work; |
d4d70aa5 | 1116 | bool interrupts_enabled; |
c85aa885 | 1117 | u32 pm_iir; |
59cdb63d | 1118 | |
b39fb297 BW |
1119 | /* Frequencies are stored in potentially platform dependent multiples. |
1120 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1121 | * Soft limits are those which are used for the dynamic reclocking done | |
1122 | * by the driver (raise frequencies under heavy loads, and lower for | |
1123 | * lighter loads). Hard limits are those imposed by the hardware. | |
1124 | * | |
1125 | * A distinction is made for overclocking, which is never enabled by | |
1126 | * default, and is considered to be above the hard limit if it's | |
1127 | * possible at all. | |
1128 | */ | |
1129 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1130 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1131 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1132 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1133 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
aed242ff | 1134 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1135 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1136 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1137 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
67c3bf6f | 1138 | u32 cz_freq; |
1a01ab3b | 1139 | |
8fb55197 CW |
1140 | u8 up_threshold; /* Current %busy required to uplock */ |
1141 | u8 down_threshold; /* Current %busy required to downclock */ | |
1142 | ||
dd75fdc8 CW |
1143 | int last_adj; |
1144 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1145 | ||
8d3afd7d CW |
1146 | spinlock_t client_lock; |
1147 | struct list_head clients; | |
1148 | bool client_boost; | |
1149 | ||
c0951f0c | 1150 | bool enabled; |
1a01ab3b | 1151 | struct delayed_work delayed_resume_work; |
1854d5ca | 1152 | unsigned boosts; |
4fc688ce | 1153 | |
2e1b8730 | 1154 | struct intel_rps_client semaphores, mmioflips; |
a6f766f3 | 1155 | |
bf225f20 CW |
1156 | /* manual wa residency calculations */ |
1157 | struct intel_rps_ei up_ei, down_ei; | |
1158 | ||
4fc688ce JB |
1159 | /* |
1160 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1161 | * Must be taken after struct_mutex if nested. Note that |
1162 | * this lock may be held for long periods of time when | |
1163 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1164 | */ |
1165 | struct mutex hw_lock; | |
c85aa885 DV |
1166 | }; |
1167 | ||
1a240d4d DV |
1168 | /* defined intel_pm.c */ |
1169 | extern spinlock_t mchdev_lock; | |
1170 | ||
c85aa885 DV |
1171 | struct intel_ilk_power_mgmt { |
1172 | u8 cur_delay; | |
1173 | u8 min_delay; | |
1174 | u8 max_delay; | |
1175 | u8 fmax; | |
1176 | u8 fstart; | |
1177 | ||
1178 | u64 last_count1; | |
1179 | unsigned long last_time1; | |
1180 | unsigned long chipset_power; | |
1181 | u64 last_count2; | |
5ed0bdf2 | 1182 | u64 last_time2; |
c85aa885 DV |
1183 | unsigned long gfx_power; |
1184 | u8 corr; | |
1185 | ||
1186 | int c_m; | |
1187 | int r_t; | |
1188 | }; | |
1189 | ||
c6cb582e ID |
1190 | struct drm_i915_private; |
1191 | struct i915_power_well; | |
1192 | ||
1193 | struct i915_power_well_ops { | |
1194 | /* | |
1195 | * Synchronize the well's hw state to match the current sw state, for | |
1196 | * example enable/disable it based on the current refcount. Called | |
1197 | * during driver init and resume time, possibly after first calling | |
1198 | * the enable/disable handlers. | |
1199 | */ | |
1200 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1201 | struct i915_power_well *power_well); | |
1202 | /* | |
1203 | * Enable the well and resources that depend on it (for example | |
1204 | * interrupts located on the well). Called after the 0->1 refcount | |
1205 | * transition. | |
1206 | */ | |
1207 | void (*enable)(struct drm_i915_private *dev_priv, | |
1208 | struct i915_power_well *power_well); | |
1209 | /* | |
1210 | * Disable the well and resources that depend on it. Called after | |
1211 | * the 1->0 refcount transition. | |
1212 | */ | |
1213 | void (*disable)(struct drm_i915_private *dev_priv, | |
1214 | struct i915_power_well *power_well); | |
1215 | /* Returns the hw enabled state. */ | |
1216 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1217 | struct i915_power_well *power_well); | |
1218 | }; | |
1219 | ||
a38911a3 WX |
1220 | /* Power well structure for haswell */ |
1221 | struct i915_power_well { | |
c1ca727f | 1222 | const char *name; |
6f3ef5dd | 1223 | bool always_on; |
a38911a3 WX |
1224 | /* power well enable/disable usage count */ |
1225 | int count; | |
bfafe93a ID |
1226 | /* cached hw enabled state */ |
1227 | bool hw_enabled; | |
c1ca727f | 1228 | unsigned long domains; |
77961eb9 | 1229 | unsigned long data; |
c6cb582e | 1230 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1231 | }; |
1232 | ||
83c00f55 | 1233 | struct i915_power_domains { |
baa70707 ID |
1234 | /* |
1235 | * Power wells needed for initialization at driver init and suspend | |
1236 | * time are on. They are kept on until after the first modeset. | |
1237 | */ | |
1238 | bool init_power_on; | |
0d116a29 | 1239 | bool initializing; |
c1ca727f | 1240 | int power_well_count; |
baa70707 | 1241 | |
83c00f55 | 1242 | struct mutex lock; |
1da51581 | 1243 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1244 | struct i915_power_well *power_wells; |
83c00f55 ID |
1245 | }; |
1246 | ||
35a85ac6 | 1247 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1248 | struct intel_l3_parity { |
35a85ac6 | 1249 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1250 | struct work_struct error_work; |
35a85ac6 | 1251 | int which_slice; |
a4da4fa4 DV |
1252 | }; |
1253 | ||
4b5aed62 | 1254 | struct i915_gem_mm { |
4b5aed62 DV |
1255 | /** Memory allocator for GTT stolen memory */ |
1256 | struct drm_mm stolen; | |
92e97d2f PZ |
1257 | /** Protects the usage of the GTT stolen memory allocator. This is |
1258 | * always the inner lock when overlapping with struct_mutex. */ | |
1259 | struct mutex stolen_lock; | |
1260 | ||
4b5aed62 DV |
1261 | /** List of all objects in gtt_space. Used to restore gtt |
1262 | * mappings on resume */ | |
1263 | struct list_head bound_list; | |
1264 | /** | |
1265 | * List of objects which are not bound to the GTT (thus | |
1266 | * are idle and not used by the GPU) but still have | |
1267 | * (presumably uncached) pages still attached. | |
1268 | */ | |
1269 | struct list_head unbound_list; | |
1270 | ||
1271 | /** Usable portion of the GTT for GEM */ | |
1272 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1273 | ||
4b5aed62 DV |
1274 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1275 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1276 | ||
2cfcd32a | 1277 | struct notifier_block oom_notifier; |
ceabbba5 | 1278 | struct shrinker shrinker; |
4b5aed62 DV |
1279 | bool shrinker_no_lock_stealing; |
1280 | ||
4b5aed62 DV |
1281 | /** LRU list of objects with fence regs on them. */ |
1282 | struct list_head fence_list; | |
1283 | ||
1284 | /** | |
1285 | * We leave the user IRQ off as much as possible, | |
1286 | * but this means that requests will finish and never | |
1287 | * be retired once the system goes idle. Set a timer to | |
1288 | * fire periodically while the ring is running. When it | |
1289 | * fires, go retire requests. | |
1290 | */ | |
1291 | struct delayed_work retire_work; | |
1292 | ||
b29c19b6 CW |
1293 | /** |
1294 | * When we detect an idle GPU, we want to turn on | |
1295 | * powersaving features. So once we see that there | |
1296 | * are no more requests outstanding and no more | |
1297 | * arrive within a small period of time, we fire | |
1298 | * off the idle_work. | |
1299 | */ | |
1300 | struct delayed_work idle_work; | |
1301 | ||
4b5aed62 DV |
1302 | /** |
1303 | * Are we in a non-interruptible section of code like | |
1304 | * modesetting? | |
1305 | */ | |
1306 | bool interruptible; | |
1307 | ||
f62a0076 CW |
1308 | /** |
1309 | * Is the GPU currently considered idle, or busy executing userspace | |
1310 | * requests? Whilst idle, we attempt to power down the hardware and | |
1311 | * display clocks. In order to reduce the effect on performance, there | |
1312 | * is a slight delay before we do so. | |
1313 | */ | |
1314 | bool busy; | |
1315 | ||
bdf1e7e3 DV |
1316 | /* the indicator for dispatch video commands on two BSD rings */ |
1317 | int bsd_ring_dispatch_index; | |
1318 | ||
4b5aed62 DV |
1319 | /** Bit 6 swizzling required for X tiling */ |
1320 | uint32_t bit_6_swizzle_x; | |
1321 | /** Bit 6 swizzling required for Y tiling */ | |
1322 | uint32_t bit_6_swizzle_y; | |
1323 | ||
4b5aed62 | 1324 | /* accounting, useful for userland debugging */ |
c20e8355 | 1325 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1326 | size_t object_memory; |
1327 | u32 object_count; | |
1328 | }; | |
1329 | ||
edc3d884 | 1330 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1331 | struct drm_i915_private *i915; |
edc3d884 MK |
1332 | unsigned bytes; |
1333 | unsigned size; | |
1334 | int err; | |
1335 | u8 *buf; | |
1336 | loff_t start; | |
1337 | loff_t pos; | |
1338 | }; | |
1339 | ||
fc16b48b MK |
1340 | struct i915_error_state_file_priv { |
1341 | struct drm_device *dev; | |
1342 | struct drm_i915_error_state *error; | |
1343 | }; | |
1344 | ||
99584db3 DV |
1345 | struct i915_gpu_error { |
1346 | /* For hangcheck timer */ | |
1347 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1348 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1349 | /* Hang gpu twice in this window and your context gets banned */ |
1350 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1351 | ||
737b1506 CW |
1352 | struct workqueue_struct *hangcheck_wq; |
1353 | struct delayed_work hangcheck_work; | |
99584db3 DV |
1354 | |
1355 | /* For reset and error_state handling. */ | |
1356 | spinlock_t lock; | |
1357 | /* Protected by the above dev->gpu_error.lock. */ | |
1358 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1359 | |
1360 | unsigned long missed_irq_rings; | |
1361 | ||
1f83fee0 | 1362 | /** |
2ac0f450 | 1363 | * State variable controlling the reset flow and count |
1f83fee0 | 1364 | * |
2ac0f450 MK |
1365 | * This is a counter which gets incremented when reset is triggered, |
1366 | * and again when reset has been handled. So odd values (lowest bit set) | |
1367 | * means that reset is in progress and even values that | |
1368 | * (reset_counter >> 1):th reset was successfully completed. | |
1369 | * | |
1370 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1371 | * set meaning that hardware is terminally sour and there is no | |
1372 | * recovery. All waiters on the reset_queue will be woken when | |
1373 | * that happens. | |
1374 | * | |
1375 | * This counter is used by the wait_seqno code to notice that reset | |
1376 | * event happened and it needs to restart the entire ioctl (since most | |
1377 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1378 | * |
1379 | * This is important for lock-free wait paths, where no contended lock | |
1380 | * naturally enforces the correct ordering between the bail-out of the | |
1381 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1382 | */ |
1383 | atomic_t reset_counter; | |
1384 | ||
1f83fee0 | 1385 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1386 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1387 | |
1388 | /** | |
1389 | * Waitqueue to signal when the reset has completed. Used by clients | |
1390 | * that wait for dev_priv->mm.wedged to settle. | |
1391 | */ | |
1392 | wait_queue_head_t reset_queue; | |
33196ded | 1393 | |
88b4aa87 MK |
1394 | /* Userspace knobs for gpu hang simulation; |
1395 | * combines both a ring mask, and extra flags | |
1396 | */ | |
1397 | u32 stop_rings; | |
1398 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1399 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1400 | |
1401 | /* For missed irq/seqno simulation. */ | |
1402 | unsigned int test_irq_rings; | |
6689c167 MA |
1403 | |
1404 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1405 | bool reload_in_reset; | |
99584db3 DV |
1406 | }; |
1407 | ||
b8efb17b ZR |
1408 | enum modeset_restore { |
1409 | MODESET_ON_LID_OPEN, | |
1410 | MODESET_DONE, | |
1411 | MODESET_SUSPENDED, | |
1412 | }; | |
1413 | ||
500ea70d RV |
1414 | #define DP_AUX_A 0x40 |
1415 | #define DP_AUX_B 0x10 | |
1416 | #define DP_AUX_C 0x20 | |
1417 | #define DP_AUX_D 0x30 | |
1418 | ||
6acab15a | 1419 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1420 | /* |
1421 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1422 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1423 | * populate this field. | |
1424 | */ | |
1425 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1426 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1427 | |
1428 | uint8_t supports_dvi:1; | |
1429 | uint8_t supports_hdmi:1; | |
1430 | uint8_t supports_dp:1; | |
500ea70d RV |
1431 | |
1432 | uint8_t alternate_aux_channel; | |
75067dde AK |
1433 | |
1434 | uint8_t dp_boost_level; | |
1435 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1436 | }; |
1437 | ||
bfd7ebda RV |
1438 | enum psr_lines_to_wait { |
1439 | PSR_0_LINES_TO_WAIT = 0, | |
1440 | PSR_1_LINE_TO_WAIT, | |
1441 | PSR_4_LINES_TO_WAIT, | |
1442 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1443 | }; |
1444 | ||
41aa3448 RV |
1445 | struct intel_vbt_data { |
1446 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1447 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1448 | ||
1449 | /* Feature bits */ | |
1450 | unsigned int int_tv_support:1; | |
1451 | unsigned int lvds_dither:1; | |
1452 | unsigned int lvds_vbt:1; | |
1453 | unsigned int int_crt_support:1; | |
1454 | unsigned int lvds_use_ssc:1; | |
1455 | unsigned int display_clock_mode:1; | |
1456 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1457 | unsigned int has_mipi:1; |
41aa3448 RV |
1458 | int lvds_ssc_freq; |
1459 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1460 | ||
83a7280e PB |
1461 | enum drrs_support_type drrs_type; |
1462 | ||
41aa3448 RV |
1463 | /* eDP */ |
1464 | int edp_rate; | |
1465 | int edp_lanes; | |
1466 | int edp_preemphasis; | |
1467 | int edp_vswing; | |
1468 | bool edp_initialized; | |
1469 | bool edp_support; | |
1470 | int edp_bpp; | |
1471 | struct edp_power_seq edp_pps; | |
1472 | ||
bfd7ebda RV |
1473 | struct { |
1474 | bool full_link; | |
1475 | bool require_aux_wakeup; | |
1476 | int idle_frames; | |
1477 | enum psr_lines_to_wait lines_to_wait; | |
1478 | int tp1_wakeup_time; | |
1479 | int tp2_tp3_wakeup_time; | |
1480 | } psr; | |
1481 | ||
f00076d2 JN |
1482 | struct { |
1483 | u16 pwm_freq_hz; | |
39fbc9c8 | 1484 | bool present; |
f00076d2 | 1485 | bool active_low_pwm; |
1de6068e | 1486 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1487 | } backlight; |
1488 | ||
d17c5443 SK |
1489 | /* MIPI DSI */ |
1490 | struct { | |
3e6bd011 | 1491 | u16 port; |
d17c5443 | 1492 | u16 panel_id; |
d3b542fc SK |
1493 | struct mipi_config *config; |
1494 | struct mipi_pps_data *pps; | |
1495 | u8 seq_version; | |
1496 | u32 size; | |
1497 | u8 *data; | |
1498 | u8 *sequence[MIPI_SEQ_MAX]; | |
d17c5443 SK |
1499 | } dsi; |
1500 | ||
41aa3448 RV |
1501 | int crt_ddc_pin; |
1502 | ||
1503 | int child_dev_num; | |
768f69c9 | 1504 | union child_device_config *child_dev; |
6acab15a PZ |
1505 | |
1506 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1507 | }; |
1508 | ||
77c122bc VS |
1509 | enum intel_ddb_partitioning { |
1510 | INTEL_DDB_PART_1_2, | |
1511 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1512 | }; | |
1513 | ||
1fd527cc VS |
1514 | struct intel_wm_level { |
1515 | bool enable; | |
1516 | uint32_t pri_val; | |
1517 | uint32_t spr_val; | |
1518 | uint32_t cur_val; | |
1519 | uint32_t fbc_val; | |
1520 | }; | |
1521 | ||
820c1980 | 1522 | struct ilk_wm_values { |
609cedef VS |
1523 | uint32_t wm_pipe[3]; |
1524 | uint32_t wm_lp[3]; | |
1525 | uint32_t wm_lp_spr[3]; | |
1526 | uint32_t wm_linetime[3]; | |
1527 | bool enable_fbc_wm; | |
1528 | enum intel_ddb_partitioning partitioning; | |
1529 | }; | |
1530 | ||
262cd2e1 VS |
1531 | struct vlv_pipe_wm { |
1532 | uint16_t primary; | |
1533 | uint16_t sprite[2]; | |
1534 | uint8_t cursor; | |
1535 | }; | |
ae80152d | 1536 | |
262cd2e1 VS |
1537 | struct vlv_sr_wm { |
1538 | uint16_t plane; | |
1539 | uint8_t cursor; | |
1540 | }; | |
ae80152d | 1541 | |
262cd2e1 VS |
1542 | struct vlv_wm_values { |
1543 | struct vlv_pipe_wm pipe[3]; | |
1544 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1545 | struct { |
1546 | uint8_t cursor; | |
1547 | uint8_t sprite[2]; | |
1548 | uint8_t primary; | |
1549 | } ddl[3]; | |
6eb1a681 VS |
1550 | uint8_t level; |
1551 | bool cxsr; | |
0018fda1 VS |
1552 | }; |
1553 | ||
c193924e | 1554 | struct skl_ddb_entry { |
16160e3d | 1555 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1556 | }; |
1557 | ||
1558 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1559 | { | |
16160e3d | 1560 | return entry->end - entry->start; |
c193924e DL |
1561 | } |
1562 | ||
08db6652 DL |
1563 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1564 | const struct skl_ddb_entry *e2) | |
1565 | { | |
1566 | if (e1->start == e2->start && e1->end == e2->end) | |
1567 | return true; | |
1568 | ||
1569 | return false; | |
1570 | } | |
1571 | ||
c193924e | 1572 | struct skl_ddb_allocation { |
34bb56af | 1573 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 CK |
1574 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
1575 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */ | |
c193924e DL |
1576 | struct skl_ddb_entry cursor[I915_MAX_PIPES]; |
1577 | }; | |
1578 | ||
2ac96d2a PB |
1579 | struct skl_wm_values { |
1580 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1581 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1582 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1583 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
1584 | uint32_t cursor[I915_MAX_PIPES][8]; | |
1585 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1586 | uint32_t cursor_trans[I915_MAX_PIPES]; | |
1587 | }; | |
1588 | ||
1589 | struct skl_wm_level { | |
1590 | bool plane_en[I915_MAX_PLANES]; | |
b99f58da | 1591 | bool cursor_en; |
2ac96d2a PB |
1592 | uint16_t plane_res_b[I915_MAX_PLANES]; |
1593 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1594 | uint16_t cursor_res_b; |
1595 | uint8_t cursor_res_l; | |
1596 | }; | |
1597 | ||
c67a470b | 1598 | /* |
765dab67 PZ |
1599 | * This struct helps tracking the state needed for runtime PM, which puts the |
1600 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1601 | * graphics device works, even register access, so we don't get interrupts nor | |
1602 | * anything else. | |
c67a470b | 1603 | * |
765dab67 PZ |
1604 | * Every piece of our code that needs to actually touch the hardware needs to |
1605 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1606 | * appropriate power domain. | |
a8a8bd54 | 1607 | * |
765dab67 PZ |
1608 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1609 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1610 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1611 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1612 | * |
1613 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1614 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1615 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1616 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1617 | * case it happens. |
c67a470b | 1618 | * |
765dab67 | 1619 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1620 | */ |
5d584b2e PZ |
1621 | struct i915_runtime_pm { |
1622 | bool suspended; | |
2aeb7d3a | 1623 | bool irqs_enabled; |
c67a470b PZ |
1624 | }; |
1625 | ||
926321d5 DV |
1626 | enum intel_pipe_crc_source { |
1627 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1628 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1629 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1630 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1631 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1632 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1633 | INTEL_PIPE_CRC_SOURCE_TV, | |
1634 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1635 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1636 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1637 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1638 | INTEL_PIPE_CRC_SOURCE_MAX, |
1639 | }; | |
1640 | ||
8bf1e9f1 | 1641 | struct intel_pipe_crc_entry { |
ac2300d4 | 1642 | uint32_t frame; |
8bf1e9f1 SH |
1643 | uint32_t crc[5]; |
1644 | }; | |
1645 | ||
b2c88f5b | 1646 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1647 | struct intel_pipe_crc { |
d538bbdf DL |
1648 | spinlock_t lock; |
1649 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1650 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1651 | enum intel_pipe_crc_source source; |
d538bbdf | 1652 | int head, tail; |
07144428 | 1653 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1654 | }; |
1655 | ||
f99d7069 DV |
1656 | struct i915_frontbuffer_tracking { |
1657 | struct mutex lock; | |
1658 | ||
1659 | /* | |
1660 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1661 | * scheduled flips. | |
1662 | */ | |
1663 | unsigned busy_bits; | |
1664 | unsigned flip_bits; | |
1665 | }; | |
1666 | ||
7225342a MK |
1667 | struct i915_wa_reg { |
1668 | u32 addr; | |
1669 | u32 value; | |
1670 | /* bitmask representing WA bits */ | |
1671 | u32 mask; | |
1672 | }; | |
1673 | ||
1674 | #define I915_MAX_WA_REGS 16 | |
1675 | ||
1676 | struct i915_workarounds { | |
1677 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1678 | u32 count; | |
1679 | }; | |
1680 | ||
cf9d2890 YZ |
1681 | struct i915_virtual_gpu { |
1682 | bool active; | |
1683 | }; | |
1684 | ||
5f19e2bf JH |
1685 | struct i915_execbuffer_params { |
1686 | struct drm_device *dev; | |
1687 | struct drm_file *file; | |
1688 | uint32_t dispatch_flags; | |
1689 | uint32_t args_batch_start_offset; | |
af98714e | 1690 | uint64_t batch_obj_vm_offset; |
5f19e2bf JH |
1691 | struct intel_engine_cs *ring; |
1692 | struct drm_i915_gem_object *batch_obj; | |
1693 | struct intel_context *ctx; | |
6a6ae79a | 1694 | struct drm_i915_gem_request *request; |
5f19e2bf JH |
1695 | }; |
1696 | ||
77fec556 | 1697 | struct drm_i915_private { |
f4c956ad | 1698 | struct drm_device *dev; |
efab6d8d | 1699 | struct kmem_cache *objects; |
e20d2ab7 | 1700 | struct kmem_cache *vmas; |
efab6d8d | 1701 | struct kmem_cache *requests; |
f4c956ad | 1702 | |
5c969aa7 | 1703 | const struct intel_device_info info; |
f4c956ad DV |
1704 | |
1705 | int relative_constants_mode; | |
1706 | ||
1707 | void __iomem *regs; | |
1708 | ||
907b28c5 | 1709 | struct intel_uncore uncore; |
f4c956ad | 1710 | |
cf9d2890 YZ |
1711 | struct i915_virtual_gpu vgpu; |
1712 | ||
33a732f4 AD |
1713 | struct intel_guc guc; |
1714 | ||
eb805623 DV |
1715 | struct intel_csr csr; |
1716 | ||
1717 | /* Display CSR-related protection */ | |
1718 | struct mutex csr_lock; | |
1719 | ||
5ea6e5e3 | 1720 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1721 | |
f4c956ad DV |
1722 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1723 | * controller on different i2c buses. */ | |
1724 | struct mutex gmbus_mutex; | |
1725 | ||
1726 | /** | |
1727 | * Base address of the gmbus and gpio block. | |
1728 | */ | |
1729 | uint32_t gpio_mmio_base; | |
1730 | ||
b6fdd0f2 SS |
1731 | /* MMIO base address for MIPI regs */ |
1732 | uint32_t mipi_mmio_base; | |
1733 | ||
28c70f16 DV |
1734 | wait_queue_head_t gmbus_wait_queue; |
1735 | ||
f4c956ad | 1736 | struct pci_dev *bridge_dev; |
a4872ba6 | 1737 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1738 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1739 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1740 | |
ba8286fa | 1741 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1742 | struct resource mch_res; |
1743 | ||
f4c956ad DV |
1744 | /* protects the irq masks */ |
1745 | spinlock_t irq_lock; | |
1746 | ||
84c33a64 SG |
1747 | /* protects the mmio flip data */ |
1748 | spinlock_t mmio_flip_lock; | |
1749 | ||
f8b79e58 ID |
1750 | bool display_irqs_enabled; |
1751 | ||
9ee32fea DV |
1752 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1753 | struct pm_qos_request pm_qos; | |
1754 | ||
a580516d VS |
1755 | /* Sideband mailbox protection */ |
1756 | struct mutex sb_lock; | |
f4c956ad DV |
1757 | |
1758 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1759 | union { |
1760 | u32 irq_mask; | |
1761 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1762 | }; | |
f4c956ad | 1763 | u32 gt_irq_mask; |
605cd25b | 1764 | u32 pm_irq_mask; |
a6706b45 | 1765 | u32 pm_rps_events; |
91d181dd | 1766 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1767 | |
5fcece80 | 1768 | struct i915_hotplug hotplug; |
5c3fe8b0 | 1769 | struct i915_fbc fbc; |
439d7ac0 | 1770 | struct i915_drrs drrs; |
f4c956ad | 1771 | struct intel_opregion opregion; |
41aa3448 | 1772 | struct intel_vbt_data vbt; |
f4c956ad | 1773 | |
d9ceb816 JB |
1774 | bool preserve_bios_swizzle; |
1775 | ||
f4c956ad DV |
1776 | /* overlay */ |
1777 | struct intel_overlay *overlay; | |
f4c956ad | 1778 | |
58c68779 | 1779 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1780 | struct mutex backlight_lock; |
31ad8ec6 | 1781 | |
f4c956ad | 1782 | /* LVDS info */ |
f4c956ad DV |
1783 | bool no_aux_handshake; |
1784 | ||
e39b999a VS |
1785 | /* protects panel power sequencer state */ |
1786 | struct mutex pps_mutex; | |
1787 | ||
f4c956ad DV |
1788 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1789 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1790 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1791 | ||
1792 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
5d96d8af | 1793 | unsigned int skl_boot_cdclk; |
44913155 | 1794 | unsigned int cdclk_freq, max_cdclk_freq; |
adafdc6f | 1795 | unsigned int max_dotclk_freq; |
6bcda4f0 | 1796 | unsigned int hpll_freq; |
f4c956ad | 1797 | |
645416f5 DV |
1798 | /** |
1799 | * wq - Driver workqueue for GEM. | |
1800 | * | |
1801 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1802 | * locks, for otherwise the flushing done in the pageflip code will | |
1803 | * result in deadlocks. | |
1804 | */ | |
f4c956ad DV |
1805 | struct workqueue_struct *wq; |
1806 | ||
1807 | /* Display functions */ | |
1808 | struct drm_i915_display_funcs display; | |
1809 | ||
1810 | /* PCH chipset type */ | |
1811 | enum intel_pch pch_type; | |
17a303ec | 1812 | unsigned short pch_id; |
f4c956ad DV |
1813 | |
1814 | unsigned long quirks; | |
1815 | ||
b8efb17b ZR |
1816 | enum modeset_restore modeset_restore; |
1817 | struct mutex modeset_restore_lock; | |
673a394b | 1818 | |
a7bbbd63 | 1819 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1820 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1821 | |
4b5aed62 | 1822 | struct i915_gem_mm mm; |
ad46cb53 CW |
1823 | DECLARE_HASHTABLE(mm_structs, 7); |
1824 | struct mutex mm_lock; | |
8781342d | 1825 | |
8781342d DV |
1826 | /* Kernel Modesetting */ |
1827 | ||
9b9d172d | 1828 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1829 | |
76c4ac04 DL |
1830 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1831 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1832 | wait_queue_head_t pending_flip_queue; |
1833 | ||
c4597872 DV |
1834 | #ifdef CONFIG_DEBUG_FS |
1835 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1836 | #endif | |
1837 | ||
e72f9fbf DV |
1838 | int num_shared_dpll; |
1839 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
e4607fcf | 1840 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1841 | |
7225342a | 1842 | struct i915_workarounds workarounds; |
888b5995 | 1843 | |
652c393a JB |
1844 | /* Reclocking support */ |
1845 | bool render_reclock_avail; | |
f99d7069 DV |
1846 | |
1847 | struct i915_frontbuffer_tracking fb_tracking; | |
1848 | ||
652c393a | 1849 | u16 orig_clock; |
f97108d1 | 1850 | |
c4804411 | 1851 | bool mchbar_need_disable; |
f97108d1 | 1852 | |
a4da4fa4 DV |
1853 | struct intel_l3_parity l3_parity; |
1854 | ||
59124506 BW |
1855 | /* Cannot be determined by PCIID. You must always read a register. */ |
1856 | size_t ellc_size; | |
1857 | ||
c6a828d3 | 1858 | /* gen6+ rps state */ |
c85aa885 | 1859 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1860 | |
20e4d407 DV |
1861 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1862 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1863 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1864 | |
83c00f55 | 1865 | struct i915_power_domains power_domains; |
a38911a3 | 1866 | |
a031d709 | 1867 | struct i915_psr psr; |
3f51e471 | 1868 | |
99584db3 | 1869 | struct i915_gpu_error gpu_error; |
ae681d96 | 1870 | |
c9cddffc JB |
1871 | struct drm_i915_gem_object *vlv_pctx; |
1872 | ||
4520f53a | 1873 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1874 | /* list of fbdev register on this device */ |
1875 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1876 | struct work_struct fbdev_suspend_work; |
4520f53a | 1877 | #endif |
e953fd7b CW |
1878 | |
1879 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1880 | struct drm_property *force_audio_property; |
e3689190 | 1881 | |
58fddc28 ID |
1882 | /* hda/i915 audio component */ |
1883 | bool audio_component_registered; | |
1884 | ||
254f965c | 1885 | uint32_t hw_context_size; |
a33afea5 | 1886 | struct list_head context_list; |
f4c956ad | 1887 | |
3e68320e | 1888 | u32 fdi_rx_config; |
68d18ad7 | 1889 | |
70722468 VS |
1890 | u32 chv_phy_control; |
1891 | ||
842f1c8b | 1892 | u32 suspend_count; |
f4c956ad | 1893 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1894 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1895 | |
53615a5e VS |
1896 | struct { |
1897 | /* | |
1898 | * Raw watermark latency values: | |
1899 | * in 0.1us units for WM0, | |
1900 | * in 0.5us units for WM1+. | |
1901 | */ | |
1902 | /* primary */ | |
1903 | uint16_t pri_latency[5]; | |
1904 | /* sprite */ | |
1905 | uint16_t spr_latency[5]; | |
1906 | /* cursor */ | |
1907 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1908 | /* |
1909 | * Raw watermark memory latency values | |
1910 | * for SKL for all 8 levels | |
1911 | * in 1us units. | |
1912 | */ | |
1913 | uint16_t skl_latency[8]; | |
609cedef | 1914 | |
2d41c0b5 PB |
1915 | /* |
1916 | * The skl_wm_values structure is a bit too big for stack | |
1917 | * allocation, so we keep the staging struct where we store | |
1918 | * intermediate results here instead. | |
1919 | */ | |
1920 | struct skl_wm_values skl_results; | |
1921 | ||
609cedef | 1922 | /* current hardware state */ |
2d41c0b5 PB |
1923 | union { |
1924 | struct ilk_wm_values hw; | |
1925 | struct skl_wm_values skl_hw; | |
0018fda1 | 1926 | struct vlv_wm_values vlv; |
2d41c0b5 | 1927 | }; |
53615a5e VS |
1928 | } wm; |
1929 | ||
8a187455 PZ |
1930 | struct i915_runtime_pm pm; |
1931 | ||
a83014d3 OM |
1932 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1933 | struct { | |
5f19e2bf | 1934 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
f3dc74c0 | 1935 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1936 | struct list_head *vmas); |
a83014d3 OM |
1937 | int (*init_rings)(struct drm_device *dev); |
1938 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1939 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1940 | } gt; | |
1941 | ||
9e458034 SJ |
1942 | bool edp_low_vswing; |
1943 | ||
bdf1e7e3 DV |
1944 | /* |
1945 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1946 | * will be rejected. Instead look for a better place. | |
1947 | */ | |
77fec556 | 1948 | }; |
1da177e4 | 1949 | |
2c1792a1 CW |
1950 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1951 | { | |
1952 | return dev->dev_private; | |
1953 | } | |
1954 | ||
888d0d42 ID |
1955 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
1956 | { | |
1957 | return to_i915(dev_get_drvdata(dev)); | |
1958 | } | |
1959 | ||
33a732f4 AD |
1960 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
1961 | { | |
1962 | return container_of(guc, struct drm_i915_private, guc); | |
1963 | } | |
1964 | ||
b4519513 CW |
1965 | /* Iterate over initialised rings */ |
1966 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1967 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1968 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1969 | ||
b1d7e4b4 WF |
1970 | enum hdmi_force_audio { |
1971 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1972 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1973 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1974 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1975 | }; | |
1976 | ||
190d6cd5 | 1977 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1978 | |
37e680a1 CW |
1979 | struct drm_i915_gem_object_ops { |
1980 | /* Interface between the GEM object and its backing storage. | |
1981 | * get_pages() is called once prior to the use of the associated set | |
1982 | * of pages before to binding them into the GTT, and put_pages() is | |
1983 | * called after we no longer need them. As we expect there to be | |
1984 | * associated cost with migrating pages between the backing storage | |
1985 | * and making them available for the GPU (e.g. clflush), we may hold | |
1986 | * onto the pages after they are no longer referenced by the GPU | |
1987 | * in case they may be used again shortly (for example migrating the | |
1988 | * pages to a different memory domain within the GTT). put_pages() | |
1989 | * will therefore most likely be called when the object itself is | |
1990 | * being released or under memory pressure (where we attempt to | |
1991 | * reap pages for the shrinker). | |
1992 | */ | |
1993 | int (*get_pages)(struct drm_i915_gem_object *); | |
1994 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
1995 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
1996 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
1997 | }; |
1998 | ||
a071fa00 DV |
1999 | /* |
2000 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
2001 | * considered to be the frontbuffer for the given plane interface-vise. This | |
2002 | * doesn't mean that the hw necessarily already scans it out, but that any | |
2003 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2004 | * | |
2005 | * We have one bit per pipe and per scanout plane type. | |
2006 | */ | |
2007 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 | |
2008 | #define INTEL_FRONTBUFFER_BITS \ | |
2009 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
2010 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
2011 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2012 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
2013 | (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
2014 | #define INTEL_FRONTBUFFER_SPRITE(pipe) \ | |
2015 | (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
2016 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
2017 | (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
cc36513c DV |
2018 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
2019 | (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
a071fa00 | 2020 | |
673a394b | 2021 | struct drm_i915_gem_object { |
c397b908 | 2022 | struct drm_gem_object base; |
673a394b | 2023 | |
37e680a1 CW |
2024 | const struct drm_i915_gem_object_ops *ops; |
2025 | ||
2f633156 BW |
2026 | /** List of VMAs backed by this object */ |
2027 | struct list_head vma_list; | |
2028 | ||
c1ad11fc CW |
2029 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2030 | struct drm_mm_node *stolen; | |
35c20a60 | 2031 | struct list_head global_list; |
673a394b | 2032 | |
b4716185 | 2033 | struct list_head ring_list[I915_NUM_RINGS]; |
b25cb2f8 BW |
2034 | /** Used in execbuf to temporarily hold a ref */ |
2035 | struct list_head obj_exec_link; | |
673a394b | 2036 | |
8d9d5744 | 2037 | struct list_head batch_pool_link; |
493018dc | 2038 | |
673a394b | 2039 | /** |
65ce3027 CW |
2040 | * This is set if the object is on the active lists (has pending |
2041 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2042 | * inactive (ready to be unbound) list. | |
673a394b | 2043 | */ |
b4716185 | 2044 | unsigned int active:I915_NUM_RINGS; |
673a394b EA |
2045 | |
2046 | /** | |
2047 | * This is set if the object has been written to since last bound | |
2048 | * to the GTT | |
2049 | */ | |
0206e353 | 2050 | unsigned int dirty:1; |
778c3544 DV |
2051 | |
2052 | /** | |
2053 | * Fence register bits (if any) for this object. Will be set | |
2054 | * as needed when mapped into the GTT. | |
2055 | * Protected by dev->struct_mutex. | |
778c3544 | 2056 | */ |
4b9de737 | 2057 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 2058 | |
778c3544 DV |
2059 | /** |
2060 | * Advice: are the backing pages purgeable? | |
2061 | */ | |
0206e353 | 2062 | unsigned int madv:2; |
778c3544 | 2063 | |
778c3544 DV |
2064 | /** |
2065 | * Current tiling mode for the object. | |
2066 | */ | |
0206e353 | 2067 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
2068 | /** |
2069 | * Whether the tiling parameters for the currently associated fence | |
2070 | * register have changed. Note that for the purposes of tracking | |
2071 | * tiling changes we also treat the unfenced register, the register | |
2072 | * slot that the object occupies whilst it executes a fenced | |
2073 | * command (such as BLT on gen2/3), as a "fence". | |
2074 | */ | |
2075 | unsigned int fence_dirty:1; | |
778c3544 | 2076 | |
75e9e915 DV |
2077 | /** |
2078 | * Is the object at the current location in the gtt mappable and | |
2079 | * fenceable? Used to avoid costly recalculations. | |
2080 | */ | |
0206e353 | 2081 | unsigned int map_and_fenceable:1; |
75e9e915 | 2082 | |
fb7d516a DV |
2083 | /** |
2084 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2085 | * mappable by accident). Track pin and fault separate for a more | |
2086 | * accurate mappable working set. | |
2087 | */ | |
0206e353 | 2088 | unsigned int fault_mappable:1; |
fb7d516a | 2089 | |
24f3a8cf AG |
2090 | /* |
2091 | * Is the object to be mapped as read-only to the GPU | |
2092 | * Only honoured if hardware has relevant pte bit | |
2093 | */ | |
2094 | unsigned long gt_ro:1; | |
651d794f | 2095 | unsigned int cache_level:3; |
0f71979a | 2096 | unsigned int cache_dirty:1; |
93dfb40c | 2097 | |
a071fa00 DV |
2098 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2099 | ||
8a0c39b1 TU |
2100 | unsigned int pin_display; |
2101 | ||
9da3da66 | 2102 | struct sg_table *pages; |
a5570178 | 2103 | int pages_pin_count; |
ee286370 CW |
2104 | struct get_page { |
2105 | struct scatterlist *sg; | |
2106 | int last; | |
2107 | } get_page; | |
673a394b | 2108 | |
1286ff73 | 2109 | /* prime dma-buf support */ |
9a70cc2a DA |
2110 | void *dma_buf_vmapping; |
2111 | int vmapping_count; | |
2112 | ||
b4716185 CW |
2113 | /** Breadcrumb of last rendering to the buffer. |
2114 | * There can only be one writer, but we allow for multiple readers. | |
2115 | * If there is a writer that necessarily implies that all other | |
2116 | * read requests are complete - but we may only be lazily clearing | |
2117 | * the read requests. A read request is naturally the most recent | |
2118 | * request on a ring, so we may have two different write and read | |
2119 | * requests on one ring where the write request is older than the | |
2120 | * read request. This allows for the CPU to read from an active | |
2121 | * buffer by only waiting for the write to complete. | |
2122 | * */ | |
2123 | struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; | |
97b2a6a1 | 2124 | struct drm_i915_gem_request *last_write_req; |
caea7476 | 2125 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 2126 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 2127 | |
778c3544 | 2128 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 2129 | uint32_t stride; |
673a394b | 2130 | |
80075d49 DV |
2131 | /** References from framebuffers, locks out tiling changes. */ |
2132 | unsigned long framebuffer_references; | |
2133 | ||
280b713b | 2134 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2135 | unsigned long *bit_17; |
280b713b | 2136 | |
5cc9ed4b | 2137 | union { |
6a2c4232 CW |
2138 | /** for phy allocated objects */ |
2139 | struct drm_dma_handle *phys_handle; | |
2140 | ||
5cc9ed4b CW |
2141 | struct i915_gem_userptr { |
2142 | uintptr_t ptr; | |
2143 | unsigned read_only :1; | |
2144 | unsigned workers :4; | |
2145 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2146 | ||
ad46cb53 CW |
2147 | struct i915_mm_struct *mm; |
2148 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2149 | struct work_struct *work; |
2150 | } userptr; | |
2151 | }; | |
2152 | }; | |
62b8b215 | 2153 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 2154 | |
a071fa00 DV |
2155 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2156 | struct drm_i915_gem_object *new, | |
2157 | unsigned frontbuffer_bits); | |
2158 | ||
673a394b EA |
2159 | /** |
2160 | * Request queue structure. | |
2161 | * | |
2162 | * The request queue allows us to note sequence numbers that have been emitted | |
2163 | * and may be associated with active buffers to be retired. | |
2164 | * | |
97b2a6a1 JH |
2165 | * By keeping this list, we can avoid having to do questionable sequence |
2166 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2167 | * emission time to be associated with the request for tracking how far ahead | |
2168 | * of the GPU the submission is. | |
b3a38998 NH |
2169 | * |
2170 | * The requests are reference counted, so upon creation they should have an | |
2171 | * initial reference taken using kref_init | |
673a394b EA |
2172 | */ |
2173 | struct drm_i915_gem_request { | |
abfe262a JH |
2174 | struct kref ref; |
2175 | ||
852835f3 | 2176 | /** On Which ring this request was generated */ |
efab6d8d | 2177 | struct drm_i915_private *i915; |
a4872ba6 | 2178 | struct intel_engine_cs *ring; |
852835f3 | 2179 | |
673a394b EA |
2180 | /** GEM sequence number associated with this request. */ |
2181 | uint32_t seqno; | |
2182 | ||
7d736f4f MK |
2183 | /** Position in the ringbuffer of the start of the request */ |
2184 | u32 head; | |
2185 | ||
72f95afa NH |
2186 | /** |
2187 | * Position in the ringbuffer of the start of the postfix. | |
2188 | * This is required to calculate the maximum available ringbuffer | |
2189 | * space without overwriting the postfix. | |
2190 | */ | |
2191 | u32 postfix; | |
2192 | ||
2193 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2194 | u32 tail; |
2195 | ||
b3a38998 | 2196 | /** |
a8c6ecb3 | 2197 | * Context and ring buffer related to this request |
b3a38998 NH |
2198 | * Contexts are refcounted, so when this request is associated with a |
2199 | * context, we must increment the context's refcount, to guarantee that | |
2200 | * it persists while any request is linked to it. Requests themselves | |
2201 | * are also refcounted, so the request will only be freed when the last | |
2202 | * reference to it is dismissed, and the code in | |
2203 | * i915_gem_request_free() will then decrement the refcount on the | |
2204 | * context. | |
2205 | */ | |
273497e5 | 2206 | struct intel_context *ctx; |
98e1bd4a | 2207 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2208 | |
dc4be607 JH |
2209 | /** Batch buffer related to this request if any (used for |
2210 | error state dump only) */ | |
7d736f4f MK |
2211 | struct drm_i915_gem_object *batch_obj; |
2212 | ||
673a394b EA |
2213 | /** Time at which this request was emitted, in jiffies. */ |
2214 | unsigned long emitted_jiffies; | |
2215 | ||
b962442e | 2216 | /** global list entry for this request */ |
673a394b | 2217 | struct list_head list; |
b962442e | 2218 | |
f787a5f5 | 2219 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2220 | /** file_priv list entry for this request */ |
2221 | struct list_head client_list; | |
67e2937b | 2222 | |
071c92de MK |
2223 | /** process identifier submitting this request */ |
2224 | struct pid *pid; | |
2225 | ||
6d3d8274 NH |
2226 | /** |
2227 | * The ELSP only accepts two elements at a time, so we queue | |
2228 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2229 | * hardware is available. The queue serves a double purpose: we also use | |
2230 | * it to keep track of the up to 2 contexts currently in the hardware | |
2231 | * (usually one in execution and the other queued up by the GPU): We | |
2232 | * only remove elements from the head of the queue when the hardware | |
2233 | * informs us that an element has been completed. | |
2234 | * | |
2235 | * All accesses to the queue are mediated by a spinlock | |
2236 | * (ring->execlist_lock). | |
2237 | */ | |
2238 | ||
2239 | /** Execlist link in the submission queue.*/ | |
2240 | struct list_head execlist_link; | |
2241 | ||
2242 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2243 | int elsp_submitted; | |
2244 | ||
673a394b EA |
2245 | }; |
2246 | ||
6689cb2b | 2247 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
217e46b5 JH |
2248 | struct intel_context *ctx, |
2249 | struct drm_i915_gem_request **req_out); | |
29b1b415 | 2250 | void i915_gem_request_cancel(struct drm_i915_gem_request *req); |
abfe262a | 2251 | void i915_gem_request_free(struct kref *req_ref); |
fcfa423c JH |
2252 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
2253 | struct drm_file *file); | |
abfe262a | 2254 | |
b793a00a JH |
2255 | static inline uint32_t |
2256 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2257 | { | |
2258 | return req ? req->seqno : 0; | |
2259 | } | |
2260 | ||
2261 | static inline struct intel_engine_cs * | |
2262 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2263 | { | |
2264 | return req ? req->ring : NULL; | |
2265 | } | |
2266 | ||
b2cfe0ab | 2267 | static inline struct drm_i915_gem_request * |
abfe262a JH |
2268 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2269 | { | |
b2cfe0ab CW |
2270 | if (req) |
2271 | kref_get(&req->ref); | |
2272 | return req; | |
abfe262a JH |
2273 | } |
2274 | ||
2275 | static inline void | |
2276 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2277 | { | |
f245860e | 2278 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
abfe262a JH |
2279 | kref_put(&req->ref, i915_gem_request_free); |
2280 | } | |
2281 | ||
41037f9f CW |
2282 | static inline void |
2283 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) | |
2284 | { | |
b833bb61 ML |
2285 | struct drm_device *dev; |
2286 | ||
2287 | if (!req) | |
2288 | return; | |
41037f9f | 2289 | |
b833bb61 ML |
2290 | dev = req->ring->dev; |
2291 | if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) | |
41037f9f | 2292 | mutex_unlock(&dev->struct_mutex); |
41037f9f CW |
2293 | } |
2294 | ||
abfe262a JH |
2295 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
2296 | struct drm_i915_gem_request *src) | |
2297 | { | |
2298 | if (src) | |
2299 | i915_gem_request_reference(src); | |
2300 | ||
2301 | if (*pdst) | |
2302 | i915_gem_request_unreference(*pdst); | |
2303 | ||
2304 | *pdst = src; | |
2305 | } | |
2306 | ||
1b5a433a JH |
2307 | /* |
2308 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2309 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2310 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2311 | */ | |
2312 | ||
351e3db2 BV |
2313 | /* |
2314 | * A command that requires special handling by the command parser. | |
2315 | */ | |
2316 | struct drm_i915_cmd_descriptor { | |
2317 | /* | |
2318 | * Flags describing how the command parser processes the command. | |
2319 | * | |
2320 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2321 | * a length mask if not set | |
2322 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2323 | * standard length encoding for the opcode range in | |
2324 | * which it falls | |
2325 | * CMD_DESC_REJECT: The command is never allowed | |
2326 | * CMD_DESC_REGISTER: The command should be checked against the | |
2327 | * register whitelist for the appropriate ring | |
2328 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2329 | * is the DRM master | |
2330 | */ | |
2331 | u32 flags; | |
2332 | #define CMD_DESC_FIXED (1<<0) | |
2333 | #define CMD_DESC_SKIP (1<<1) | |
2334 | #define CMD_DESC_REJECT (1<<2) | |
2335 | #define CMD_DESC_REGISTER (1<<3) | |
2336 | #define CMD_DESC_BITMASK (1<<4) | |
2337 | #define CMD_DESC_MASTER (1<<5) | |
2338 | ||
2339 | /* | |
2340 | * The command's unique identification bits and the bitmask to get them. | |
2341 | * This isn't strictly the opcode field as defined in the spec and may | |
2342 | * also include type, subtype, and/or subop fields. | |
2343 | */ | |
2344 | struct { | |
2345 | u32 value; | |
2346 | u32 mask; | |
2347 | } cmd; | |
2348 | ||
2349 | /* | |
2350 | * The command's length. The command is either fixed length (i.e. does | |
2351 | * not include a length field) or has a length field mask. The flag | |
2352 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2353 | * a length mask. All command entries in a command table must include | |
2354 | * length information. | |
2355 | */ | |
2356 | union { | |
2357 | u32 fixed; | |
2358 | u32 mask; | |
2359 | } length; | |
2360 | ||
2361 | /* | |
2362 | * Describes where to find a register address in the command to check | |
2363 | * against the ring's register whitelist. Only valid if flags has the | |
2364 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2365 | * |
2366 | * A non-zero step value implies that the command may access multiple | |
2367 | * registers in sequence (e.g. LRI), in that case step gives the | |
2368 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2369 | */ |
2370 | struct { | |
2371 | u32 offset; | |
2372 | u32 mask; | |
6a65c5b9 | 2373 | u32 step; |
351e3db2 BV |
2374 | } reg; |
2375 | ||
2376 | #define MAX_CMD_DESC_BITMASKS 3 | |
2377 | /* | |
2378 | * Describes command checks where a particular dword is masked and | |
2379 | * compared against an expected value. If the command does not match | |
2380 | * the expected value, the parser rejects it. Only valid if flags has | |
2381 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2382 | * are valid. | |
d4d48035 BV |
2383 | * |
2384 | * If the check specifies a non-zero condition_mask then the parser | |
2385 | * only performs the check when the bits specified by condition_mask | |
2386 | * are non-zero. | |
351e3db2 BV |
2387 | */ |
2388 | struct { | |
2389 | u32 offset; | |
2390 | u32 mask; | |
2391 | u32 expected; | |
d4d48035 BV |
2392 | u32 condition_offset; |
2393 | u32 condition_mask; | |
351e3db2 BV |
2394 | } bits[MAX_CMD_DESC_BITMASKS]; |
2395 | }; | |
2396 | ||
2397 | /* | |
2398 | * A table of commands requiring special handling by the command parser. | |
2399 | * | |
2400 | * Each ring has an array of tables. Each table consists of an array of command | |
2401 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2402 | */ | |
2403 | struct drm_i915_cmd_table { | |
2404 | const struct drm_i915_cmd_descriptor *table; | |
2405 | int count; | |
2406 | }; | |
2407 | ||
dbbe9127 | 2408 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2409 | #define __I915__(p) ({ \ |
2410 | struct drm_i915_private *__p; \ | |
2411 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2412 | __p = (struct drm_i915_private *)p; \ | |
2413 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2414 | __p = to_i915((struct drm_device *)p); \ | |
2415 | else \ | |
2416 | BUILD_BUG(); \ | |
2417 | __p; \ | |
2418 | }) | |
dbbe9127 | 2419 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2420 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
e90a21d4 | 2421 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
cae5852d | 2422 | |
87f1f465 CW |
2423 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2424 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2425 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2426 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2427 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2428 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2429 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2430 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2431 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2432 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2433 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2434 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2435 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2436 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2437 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2438 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2439 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2440 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2441 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2442 | INTEL_DEVID(dev) == 0x0152 || \ | |
2443 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2444 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
6df4027b | 2445 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
4cae9ae0 | 2446 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
8179f1f0 | 2447 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
7201c0b3 | 2448 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
1feed885 | 2449 | #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) |
cae5852d | 2450 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2451 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2452 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2453 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2454 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2455 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2456 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2457 | /* ULX machines are also considered ULT. */ |
2458 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2459 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2460 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2461 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2462 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2463 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2464 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2465 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2466 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2467 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2468 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2469 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2470 | INTEL_DEVID(dev) == 0x1913 || \ | |
2471 | INTEL_DEVID(dev) == 0x1916 || \ | |
2472 | INTEL_DEVID(dev) == 0x1921 || \ | |
2473 | INTEL_DEVID(dev) == 0x1926) | |
2474 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2475 | INTEL_DEVID(dev) == 0x1915 || \ | |
2476 | INTEL_DEVID(dev) == 0x191E) | |
b833d685 | 2477 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2478 | |
e90a21d4 HN |
2479 | #define SKL_REVID_A0 (0x0) |
2480 | #define SKL_REVID_B0 (0x1) | |
2481 | #define SKL_REVID_C0 (0x2) | |
2482 | #define SKL_REVID_D0 (0x3) | |
8bc0ccf6 | 2483 | #define SKL_REVID_E0 (0x4) |
b88baa2a | 2484 | #define SKL_REVID_F0 (0x5) |
e90a21d4 | 2485 | |
6c74c87f NH |
2486 | #define BXT_REVID_A0 (0x0) |
2487 | #define BXT_REVID_B0 (0x3) | |
2488 | #define BXT_REVID_C0 (0x6) | |
2489 | ||
85436696 JB |
2490 | /* |
2491 | * The genX designation typically refers to the render engine, so render | |
2492 | * capability related checks should use IS_GEN, while display and other checks | |
2493 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2494 | * chips, etc.). | |
2495 | */ | |
cae5852d ZN |
2496 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2497 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2498 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2499 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2500 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2501 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2502 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2503 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2504 | |
73ae478c BW |
2505 | #define RENDER_RING (1<<RCS) |
2506 | #define BSD_RING (1<<VCS) | |
2507 | #define BLT_RING (1<<BCS) | |
2508 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2509 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2510 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2511 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2512 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2513 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2514 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2515 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
f2fbc690 | 2516 | __I915__(dev)->ellc_size) |
cae5852d ZN |
2517 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2518 | ||
254f965c | 2519 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2520 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c | 2521 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2522 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2523 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2524 | |
05394f39 | 2525 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2526 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2527 | ||
b45305fc DV |
2528 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2529 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
4e6b788c DV |
2530 | /* |
2531 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2532 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2533 | * legacy irq no. is shared with another device. The kernel then disables that | |
2534 | * interrupt source and so prevents the other device from working properly. | |
2535 | */ | |
2536 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2537 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2538 | |
cae5852d ZN |
2539 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2540 | * rows, which changed the alignment requirements and fence programming. | |
2541 | */ | |
2542 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2543 | IS_I915GM(dev))) | |
cae5852d ZN |
2544 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2545 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2546 | |
2547 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2548 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2549 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2550 | |
dbf7786e | 2551 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2552 | |
0c9b3715 JN |
2553 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2554 | INTEL_INFO(dev)->gen >= 9) | |
2555 | ||
dd93be58 | 2556 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2557 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2558 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 SJ |
2559 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
2560 | IS_SKYLAKE(dev)) | |
6157d3c8 | 2561 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 SS |
2562 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
2563 | IS_SKYLAKE(dev)) | |
58abf1da RV |
2564 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2565 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2566 | |
eb805623 DV |
2567 | #define HAS_CSR(dev) (IS_SKYLAKE(dev)) |
2568 | ||
33a732f4 AD |
2569 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev)) |
2570 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev)) | |
2571 | ||
a9ed33ca AJ |
2572 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2573 | INTEL_INFO(dev)->gen >= 8) | |
2574 | ||
97d3308a | 2575 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
430b7ad5 | 2576 | !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
97d3308a | 2577 | |
17a303ec PZ |
2578 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2579 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2580 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2581 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2582 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2583 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2584 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2585 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
17a303ec | 2586 | |
f2fbc690 | 2587 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2588 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2589 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
2590 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2591 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2592 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2593 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2594 | |
5fafe292 SJ |
2595 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2596 | ||
040d2baa BW |
2597 | /* DPF == dynamic parity feature */ |
2598 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2599 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2600 | |
c8735b0c | 2601 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2602 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2603 | |
05394f39 CW |
2604 | #include "i915_trace.h" |
2605 | ||
baa70943 | 2606 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2607 | extern int i915_max_ioctl; |
2608 | ||
fc49b3da ID |
2609 | extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); |
2610 | extern int i915_resume_legacy(struct drm_device *dev); | |
7c1c2871 | 2611 | |
d330a953 JN |
2612 | /* i915_params.c */ |
2613 | struct i915_params { | |
2614 | int modeset; | |
2615 | int panel_ignore_lid; | |
d330a953 | 2616 | int semaphores; |
d330a953 JN |
2617 | int lvds_channel_mode; |
2618 | int panel_use_ssc; | |
2619 | int vbt_sdvo_panel_type; | |
2620 | int enable_rc6; | |
2621 | int enable_fbc; | |
d330a953 | 2622 | int enable_ppgtt; |
127f1003 | 2623 | int enable_execlists; |
d330a953 JN |
2624 | int enable_psr; |
2625 | unsigned int preliminary_hw_support; | |
2626 | int disable_power_well; | |
2627 | int enable_ips; | |
e5aa6541 | 2628 | int invert_brightness; |
351e3db2 | 2629 | int enable_cmd_parser; |
e5aa6541 DL |
2630 | /* leave bools at the end to not create holes */ |
2631 | bool enable_hangcheck; | |
2632 | bool fastboot; | |
d330a953 | 2633 | bool prefault_disable; |
5bedeb2d | 2634 | bool load_detect_test; |
d330a953 | 2635 | bool reset; |
a0bae57f | 2636 | bool disable_display; |
7a10dfa6 | 2637 | bool disable_vtd_wa; |
63dc0449 AD |
2638 | bool enable_guc_submission; |
2639 | int guc_log_level; | |
84c33a64 | 2640 | int use_mmio_flip; |
48572edd | 2641 | int mmio_debug; |
e2c719b7 | 2642 | bool verbose_state_checks; |
c5b852f3 | 2643 | bool nuclear_pageflip; |
9e458034 | 2644 | int edp_vswing; |
d330a953 JN |
2645 | }; |
2646 | extern struct i915_params i915 __read_mostly; | |
2647 | ||
1da177e4 | 2648 | /* i915_dma.c */ |
22eae947 | 2649 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2650 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2651 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2652 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2653 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2654 | struct drm_file *file); |
673a394b | 2655 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2656 | struct drm_file *file); |
c43b5634 | 2657 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2658 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2659 | unsigned long arg); | |
c43b5634 | 2660 | #endif |
8e96d9c4 | 2661 | extern int intel_gpu_reset(struct drm_device *dev); |
49e4d842 | 2662 | extern bool intel_has_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2663 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2664 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2665 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2666 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2667 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2668 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
eb805623 | 2669 | void i915_firmware_load_error_print(const char *fw_path, int err); |
7648fa99 | 2670 | |
77913b39 JN |
2671 | /* intel_hotplug.c */ |
2672 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); | |
2673 | void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2674 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2675 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2676 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
77913b39 | 2677 | |
1da177e4 | 2678 | /* i915_irq.c */ |
10cd45b6 | 2679 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2680 | __printf(3, 4) |
2681 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2682 | const char *fmt, ...); | |
1da177e4 | 2683 | |
b963291c | 2684 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2685 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2686 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2687 | |
2688 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2689 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2690 | bool restore_forcewake); | |
907b28c5 | 2691 | extern void intel_uncore_init(struct drm_device *dev); |
907b28c5 | 2692 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2693 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2694 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
48c1026a | 2695 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2696 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2697 | enum forcewake_domains domains); |
59bad947 | 2698 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2699 | enum forcewake_domains domains); |
a6111f7b CW |
2700 | /* Like above but the caller must manage the uncore.lock itself. |
2701 | * Must be used with I915_READ_FW and friends. | |
2702 | */ | |
2703 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2704 | enum forcewake_domains domains); | |
2705 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2706 | enum forcewake_domains domains); | |
59bad947 | 2707 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
cf9d2890 YZ |
2708 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2709 | { | |
2710 | return to_i915(dev)->vgpu.active; | |
2711 | } | |
b1f14ad0 | 2712 | |
7c463586 | 2713 | void |
50227e1c | 2714 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2715 | u32 status_mask); |
7c463586 KP |
2716 | |
2717 | void | |
50227e1c | 2718 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2719 | u32 status_mask); |
7c463586 | 2720 | |
f8b79e58 ID |
2721 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2722 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
2723 | void |
2724 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2725 | void | |
2726 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2727 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
2728 | uint32_t interrupt_mask, | |
2729 | uint32_t enabled_irq_mask); | |
2730 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
2731 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
2732 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
2733 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
f8b79e58 | 2734 | |
673a394b | 2735 | /* i915_gem.c */ |
673a394b EA |
2736 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2737 | struct drm_file *file_priv); | |
2738 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2739 | struct drm_file *file_priv); | |
2740 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2741 | struct drm_file *file_priv); | |
2742 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2743 | struct drm_file *file_priv); | |
de151cf6 JB |
2744 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2745 | struct drm_file *file_priv); | |
673a394b EA |
2746 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2747 | struct drm_file *file_priv); | |
2748 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2749 | struct drm_file *file_priv); | |
ba8b7ccb | 2750 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 2751 | struct drm_i915_gem_request *req); |
adeca76d | 2752 | void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params); |
5f19e2bf | 2753 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 2754 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 2755 | struct list_head *vmas); |
673a394b EA |
2756 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2757 | struct drm_file *file_priv); | |
76446cac JB |
2758 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2759 | struct drm_file *file_priv); | |
673a394b EA |
2760 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2761 | struct drm_file *file_priv); | |
199adf40 BW |
2762 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2763 | struct drm_file *file); | |
2764 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2765 | struct drm_file *file); | |
673a394b EA |
2766 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2767 | struct drm_file *file_priv); | |
3ef94daa CW |
2768 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2769 | struct drm_file *file_priv); | |
673a394b EA |
2770 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2771 | struct drm_file *file_priv); | |
2772 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2773 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2774 | int i915_gem_init_userptr(struct drm_device *dev); |
2775 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2776 | struct drm_file *file); | |
5a125c3c EA |
2777 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2778 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2779 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2780 | struct drm_file *file_priv); | |
673a394b | 2781 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
2782 | void *i915_gem_object_alloc(struct drm_device *dev); |
2783 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2784 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2785 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2786 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2787 | size_t size); | |
ea70299d DG |
2788 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
2789 | struct drm_device *dev, const void *data, size_t size); | |
7e0d96bc BW |
2790 | void i915_init_vm(struct drm_i915_private *dev_priv, |
2791 | struct i915_address_space *vm); | |
673a394b | 2792 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2793 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2794 | |
0875546c DV |
2795 | /* Flags used by pin/bind&friends. */ |
2796 | #define PIN_MAPPABLE (1<<0) | |
2797 | #define PIN_NONBLOCK (1<<1) | |
2798 | #define PIN_GLOBAL (1<<2) | |
2799 | #define PIN_OFFSET_BIAS (1<<3) | |
2800 | #define PIN_USER (1<<4) | |
2801 | #define PIN_UPDATE (1<<5) | |
d23db88c | 2802 | #define PIN_OFFSET_MASK (~4095) |
ec7adb6e JL |
2803 | int __must_check |
2804 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
2805 | struct i915_address_space *vm, | |
2806 | uint32_t alignment, | |
2807 | uint64_t flags); | |
2808 | int __must_check | |
2809 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
2810 | const struct i915_ggtt_view *view, | |
2811 | uint32_t alignment, | |
2812 | uint64_t flags); | |
fe14d5f4 TU |
2813 | |
2814 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2815 | u32 flags); | |
07fe0b12 | 2816 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
dd624afd | 2817 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2818 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2819 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2820 | |
4c914c0c BV |
2821 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2822 | int *needs_clflush); | |
2823 | ||
37e680a1 | 2824 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
2825 | |
2826 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 2827 | { |
ee286370 CW |
2828 | return sg->length >> PAGE_SHIFT; |
2829 | } | |
67d5a50c | 2830 | |
ee286370 CW |
2831 | static inline struct page * |
2832 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 2833 | { |
ee286370 CW |
2834 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2835 | return NULL; | |
67d5a50c | 2836 | |
ee286370 CW |
2837 | if (n < obj->get_page.last) { |
2838 | obj->get_page.sg = obj->pages->sgl; | |
2839 | obj->get_page.last = 0; | |
2840 | } | |
67d5a50c | 2841 | |
ee286370 CW |
2842 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
2843 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
2844 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
2845 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
2846 | } | |
67d5a50c | 2847 | |
ee286370 | 2848 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 2849 | } |
ee286370 | 2850 | |
a5570178 CW |
2851 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2852 | { | |
2853 | BUG_ON(obj->pages == NULL); | |
2854 | obj->pages_pin_count++; | |
2855 | } | |
2856 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2857 | { | |
2858 | BUG_ON(obj->pages_pin_count == 0); | |
2859 | obj->pages_pin_count--; | |
2860 | } | |
2861 | ||
54cf91dc | 2862 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2863 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
91af127f JH |
2864 | struct intel_engine_cs *to, |
2865 | struct drm_i915_gem_request **to_req); | |
e2d05a8b | 2866 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2867 | struct drm_i915_gem_request *req); |
ff72145b DA |
2868 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2869 | struct drm_device *dev, | |
2870 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
2871 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2872 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2873 | /** |
2874 | * Returns true if seq1 is later than seq2. | |
2875 | */ | |
2876 | static inline bool | |
2877 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2878 | { | |
2879 | return (int32_t)(seq1 - seq2) >= 0; | |
2880 | } | |
2881 | ||
1b5a433a JH |
2882 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
2883 | bool lazy_coherency) | |
2884 | { | |
2885 | u32 seqno; | |
2886 | ||
2887 | BUG_ON(req == NULL); | |
2888 | ||
2889 | seqno = req->ring->get_seqno(req->ring, lazy_coherency); | |
2890 | ||
2891 | return i915_seqno_passed(seqno, req->seqno); | |
2892 | } | |
2893 | ||
fca26bb4 MK |
2894 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2895 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
1690e1eb | 2896 | |
8d9fc7fd | 2897 | struct drm_i915_gem_request * |
a4872ba6 | 2898 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2899 | |
b29c19b6 | 2900 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2901 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2902 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2903 | bool interruptible); |
84c33a64 | 2904 | |
1f83fee0 DV |
2905 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2906 | { | |
2907 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2908 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2909 | } |
2910 | ||
2911 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2912 | { | |
2ac0f450 MK |
2913 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2914 | } | |
2915 | ||
2916 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2917 | { | |
2918 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2919 | } |
a71d8d94 | 2920 | |
88b4aa87 MK |
2921 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2922 | { | |
2923 | return dev_priv->gpu_error.stop_rings == 0 || | |
2924 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2925 | } | |
2926 | ||
2927 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2928 | { | |
2929 | return dev_priv->gpu_error.stop_rings == 0 || | |
2930 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2931 | } | |
2932 | ||
069efc1d | 2933 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2934 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 2935 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 2936 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 2937 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
6909a666 | 2938 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice); |
f691e2f4 | 2939 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2940 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2941 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2942 | int __must_check i915_gem_suspend(struct drm_device *dev); |
75289874 | 2943 | void __i915_add_request(struct drm_i915_gem_request *req, |
5b4a60c2 JH |
2944 | struct drm_i915_gem_object *batch_obj, |
2945 | bool flush_caches); | |
75289874 | 2946 | #define i915_add_request(req) \ |
fcfa423c | 2947 | __i915_add_request(req, NULL, true) |
75289874 | 2948 | #define i915_add_request_no_flush(req) \ |
fcfa423c | 2949 | __i915_add_request(req, NULL, false) |
9c654818 | 2950 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
2951 | unsigned reset_counter, |
2952 | bool interruptible, | |
2953 | s64 *timeout, | |
2e1b8730 | 2954 | struct intel_rps_client *rps); |
a4b3a571 | 2955 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 2956 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 2957 | int __must_check |
2e2f351d CW |
2958 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
2959 | bool readonly); | |
2960 | int __must_check | |
2021746e CW |
2961 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
2962 | bool write); | |
2963 | int __must_check | |
dabdfe02 CW |
2964 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2965 | int __must_check | |
2da3b9b9 CW |
2966 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2967 | u32 alignment, | |
e6617330 | 2968 | struct intel_engine_cs *pipelined, |
91af127f | 2969 | struct drm_i915_gem_request **pipelined_request, |
e6617330 TU |
2970 | const struct i915_ggtt_view *view); |
2971 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
2972 | const struct i915_ggtt_view *view); | |
00731155 | 2973 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 2974 | int align); |
b29c19b6 | 2975 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2976 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2977 | |
0fa87796 ID |
2978 | uint32_t |
2979 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2980 | uint32_t |
d865110c ID |
2981 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2982 | int tiling_mode, bool fenced); | |
467cffba | 2983 | |
e4ffd173 CW |
2984 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2985 | enum i915_cache_level cache_level); | |
2986 | ||
1286ff73 DV |
2987 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2988 | struct dma_buf *dma_buf); | |
2989 | ||
2990 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2991 | struct drm_gem_object *gem_obj, int flags); | |
2992 | ||
088e0df4 MT |
2993 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
2994 | const struct i915_ggtt_view *view); | |
2995 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
2996 | struct i915_address_space *vm); | |
2997 | static inline u64 | |
ec7adb6e | 2998 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
fe14d5f4 | 2999 | { |
9abc4648 | 3000 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 3001 | } |
ec7adb6e | 3002 | |
a70a3148 | 3003 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
ec7adb6e | 3004 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 3005 | const struct i915_ggtt_view *view); |
a70a3148 | 3006 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 3007 | struct i915_address_space *vm); |
fe14d5f4 | 3008 | |
a70a3148 BW |
3009 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
3010 | struct i915_address_space *vm); | |
fe14d5f4 | 3011 | struct i915_vma * |
ec7adb6e JL |
3012 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3013 | struct i915_address_space *vm); | |
3014 | struct i915_vma * | |
3015 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
3016 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3017 | |
accfef2e BW |
3018 | struct i915_vma * |
3019 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
3020 | struct i915_address_space *vm); |
3021 | struct i915_vma * | |
3022 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
3023 | const struct i915_ggtt_view *view); | |
5c2abbea | 3024 | |
ec7adb6e JL |
3025 | static inline struct i915_vma * |
3026 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
3027 | { | |
3028 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 3029 | } |
ec7adb6e | 3030 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 3031 | |
a70a3148 | 3032 | /* Some GGTT VM helpers */ |
5dc383b0 | 3033 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 BW |
3034 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
3035 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
3036 | { | |
3037 | struct i915_address_space *ggtt = | |
3038 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
3039 | return vm == ggtt; | |
3040 | } | |
3041 | ||
841cd773 DV |
3042 | static inline struct i915_hw_ppgtt * |
3043 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3044 | { | |
3045 | WARN_ON(i915_is_ggtt(vm)); | |
3046 | ||
3047 | return container_of(vm, struct i915_hw_ppgtt, base); | |
3048 | } | |
3049 | ||
3050 | ||
a70a3148 BW |
3051 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3052 | { | |
9abc4648 | 3053 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
3054 | } |
3055 | ||
3056 | static inline unsigned long | |
3057 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
3058 | { | |
5dc383b0 | 3059 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 3060 | } |
c37e2204 BW |
3061 | |
3062 | static inline int __must_check | |
3063 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
3064 | uint32_t alignment, | |
1ec9e26d | 3065 | unsigned flags) |
c37e2204 | 3066 | { |
5dc383b0 DV |
3067 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
3068 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 3069 | } |
a70a3148 | 3070 | |
b287110e DV |
3071 | static inline int |
3072 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
3073 | { | |
3074 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
3075 | } | |
3076 | ||
e6617330 TU |
3077 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3078 | const struct i915_ggtt_view *view); | |
3079 | static inline void | |
3080 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3081 | { | |
3082 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3083 | } | |
b287110e | 3084 | |
41a36b73 DV |
3085 | /* i915_gem_fence.c */ |
3086 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
3087 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
3088 | ||
3089 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
3090 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
3091 | ||
3092 | void i915_gem_restore_fences(struct drm_device *dev); | |
3093 | ||
7f96ecaf DV |
3094 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3095 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3096 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3097 | ||
254f965c | 3098 | /* i915_gem_context.c */ |
8245be31 | 3099 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 3100 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3101 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3102 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
b3dd6b96 | 3103 | int i915_gem_context_enable(struct drm_i915_gem_request *req); |
254f965c | 3104 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3105 | int i915_switch_context(struct drm_i915_gem_request *req); |
273497e5 | 3106 | struct intel_context * |
41bde553 | 3107 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 3108 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3109 | struct drm_i915_gem_object * |
3110 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 3111 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 3112 | { |
691e6415 | 3113 | kref_get(&ctx->ref); |
dce3271b MK |
3114 | } |
3115 | ||
273497e5 | 3116 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 3117 | { |
691e6415 | 3118 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3119 | } |
3120 | ||
273497e5 | 3121 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 3122 | { |
821d66dd | 3123 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3124 | } |
3125 | ||
84624813 BW |
3126 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3127 | struct drm_file *file); | |
3128 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3129 | struct drm_file *file); | |
c9dc0f35 CW |
3130 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3131 | struct drm_file *file_priv); | |
3132 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3133 | struct drm_file *file_priv); | |
1286ff73 | 3134 | |
679845ed BW |
3135 | /* i915_gem_evict.c */ |
3136 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3137 | struct i915_address_space *vm, | |
3138 | int min_size, | |
3139 | unsigned alignment, | |
3140 | unsigned cache_level, | |
d23db88c CW |
3141 | unsigned long start, |
3142 | unsigned long end, | |
1ec9e26d | 3143 | unsigned flags); |
679845ed BW |
3144 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
3145 | int i915_gem_evict_everything(struct drm_device *dev); | |
1d2a314c | 3146 | |
0260c420 | 3147 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 3148 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
3149 | { |
3150 | if (INTEL_INFO(dev)->gen < 6) | |
3151 | intel_gtt_chipset_flush(); | |
3152 | } | |
246cbfb5 | 3153 | |
9797fbfb | 3154 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3155 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3156 | struct drm_mm_node *node, u64 size, | |
3157 | unsigned alignment); | |
3158 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, | |
3159 | struct drm_mm_node *node); | |
9797fbfb CW |
3160 | int i915_gem_init_stolen(struct drm_device *dev); |
3161 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3162 | struct drm_i915_gem_object * |
3163 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3164 | struct drm_i915_gem_object * |
3165 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3166 | u32 stolen_offset, | |
3167 | u32 gtt_offset, | |
3168 | u32 size); | |
9797fbfb | 3169 | |
be6a0376 DV |
3170 | /* i915_gem_shrinker.c */ |
3171 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
3172 | long target, | |
3173 | unsigned flags); | |
3174 | #define I915_SHRINK_PURGEABLE 0x1 | |
3175 | #define I915_SHRINK_UNBOUND 0x2 | |
3176 | #define I915_SHRINK_BOUND 0x4 | |
3177 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
3178 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
3179 | ||
3180 | ||
673a394b | 3181 | /* i915_gem_tiling.c */ |
2c1792a1 | 3182 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3183 | { |
50227e1c | 3184 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
3185 | |
3186 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3187 | obj->tiling_mode != I915_TILING_NONE; | |
3188 | } | |
3189 | ||
673a394b | 3190 | /* i915_gem_debug.c */ |
23bc5982 CW |
3191 | #if WATCH_LISTS |
3192 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 3193 | #else |
23bc5982 | 3194 | #define i915_verify_lists(dev) 0 |
673a394b | 3195 | #endif |
1da177e4 | 3196 | |
2017263e | 3197 | /* i915_debugfs.c */ |
27c202ad BG |
3198 | int i915_debugfs_init(struct drm_minor *minor); |
3199 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 3200 | #ifdef CONFIG_DEBUG_FS |
249e87de | 3201 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3202 | void intel_display_crc_init(struct drm_device *dev); |
3203 | #else | |
101057fa DV |
3204 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3205 | { return 0; } | |
f8c168fa | 3206 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3207 | #endif |
84734a04 MK |
3208 | |
3209 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3210 | __printf(2, 3) |
3211 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3212 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3213 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3214 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3215 | struct drm_i915_private *i915, |
4dc955f7 MK |
3216 | size_t count, loff_t pos); |
3217 | static inline void i915_error_state_buf_release( | |
3218 | struct drm_i915_error_state_buf *eb) | |
3219 | { | |
3220 | kfree(eb->buf); | |
3221 | } | |
58174462 MK |
3222 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
3223 | const char *error_msg); | |
84734a04 MK |
3224 | void i915_error_state_get(struct drm_device *dev, |
3225 | struct i915_error_state_file_priv *error_priv); | |
3226 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3227 | void i915_destroy_error_state(struct drm_device *dev); | |
3228 | ||
3229 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 3230 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3231 | |
351e3db2 | 3232 | /* i915_cmd_parser.c */ |
d728c8ef | 3233 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
3234 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
3235 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
3236 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
3237 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 | 3238 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3239 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3240 | u32 batch_start_offset, |
b9ffd80e | 3241 | u32 batch_len, |
351e3db2 BV |
3242 | bool is_master); |
3243 | ||
317c35d1 JB |
3244 | /* i915_suspend.c */ |
3245 | extern int i915_save_state(struct drm_device *dev); | |
3246 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3247 | |
0136db58 BW |
3248 | /* i915_sysfs.c */ |
3249 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3250 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3251 | ||
f899fc64 CW |
3252 | /* intel_i2c.c */ |
3253 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3254 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3255 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3256 | unsigned int pin); | |
3bd7d909 | 3257 | |
0184df46 JN |
3258 | extern struct i2c_adapter * |
3259 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3260 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3261 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3262 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3263 | { |
3264 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3265 | } | |
f899fc64 CW |
3266 | extern void intel_i2c_reset(struct drm_device *dev); |
3267 | ||
3b617967 | 3268 | /* intel_opregion.c */ |
44834a67 | 3269 | #ifdef CONFIG_ACPI |
27d50c82 | 3270 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
3271 | extern void intel_opregion_init(struct drm_device *dev); |
3272 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 3273 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
3274 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3275 | bool enable); | |
ecbc5cf3 JN |
3276 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3277 | pci_power_t state); | |
65e082c9 | 3278 | #else |
27d50c82 | 3279 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
3280 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3281 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 3282 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
3283 | static inline int |
3284 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3285 | { | |
3286 | return 0; | |
3287 | } | |
ecbc5cf3 JN |
3288 | static inline int |
3289 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3290 | { | |
3291 | return 0; | |
3292 | } | |
65e082c9 | 3293 | #endif |
8ee1c3db | 3294 | |
723bfd70 JB |
3295 | /* intel_acpi.c */ |
3296 | #ifdef CONFIG_ACPI | |
3297 | extern void intel_register_dsm_handler(void); | |
3298 | extern void intel_unregister_dsm_handler(void); | |
3299 | #else | |
3300 | static inline void intel_register_dsm_handler(void) { return; } | |
3301 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3302 | #endif /* CONFIG_ACPI */ | |
3303 | ||
79e53945 | 3304 | /* modesetting */ |
f817586c | 3305 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3306 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3307 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3308 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 3309 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 3310 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3311 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3312 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3313 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
7648fa99 | 3314 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 3315 | extern void intel_init_pch_refclk(struct drm_device *dev); |
ffe02b40 | 3316 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
3317 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3318 | bool enable); | |
0206e353 AJ |
3319 | extern void intel_detect_pch(struct drm_device *dev); |
3320 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 3321 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 3322 | |
2911a35b | 3323 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
3324 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3325 | struct drm_file *file); | |
b6359918 MK |
3326 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3327 | struct drm_file *file); | |
575155a9 | 3328 | |
6ef3d427 CW |
3329 | /* overlay */ |
3330 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
3331 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3332 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
3333 | |
3334 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 3335 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3336 | struct drm_device *dev, |
3337 | struct intel_display_error_state *error); | |
6ef3d427 | 3338 | |
151a49d0 TR |
3339 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3340 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3341 | |
3342 | /* intel_sideband.c */ | |
707b6e3d D |
3343 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3344 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3345 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
e9f882a3 JN |
3346 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
3347 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3348 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
3349 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3350 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3351 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3352 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3353 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
3354 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3355 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3356 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3357 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3358 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3359 | enum intel_sbi_destination destination); | |
3360 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3361 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3362 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3363 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3364 | |
616bc820 VS |
3365 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3366 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3367 | |
0b274481 BW |
3368 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3369 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3370 | ||
3371 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3372 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3373 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3374 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3375 | ||
3376 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3377 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3378 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3379 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3380 | ||
698b3135 CW |
3381 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3382 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3383 | * an arbitrary delay between them. This can cause the hardware to | |
3384 | * act upon the intermediate value, possibly leading to corruption and | |
3385 | * machine death. You have been warned. | |
3386 | */ | |
0b274481 BW |
3387 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3388 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3389 | |
50877445 | 3390 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
ee0a227b CW |
3391 | u32 upper, lower, tmp; \ |
3392 | tmp = I915_READ(upper_reg); \ | |
3393 | do { \ | |
3394 | upper = tmp; \ | |
3395 | lower = I915_READ(lower_reg); \ | |
3396 | tmp = I915_READ(upper_reg); \ | |
3397 | } while (upper != tmp); \ | |
3398 | (u64)upper << 32 | lower; }) | |
50877445 | 3399 | |
cae5852d ZN |
3400 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3401 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3402 | ||
a6111f7b CW |
3403 | /* These are untraced mmio-accessors that are only valid to be used inside |
3404 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3405 | * controlled. | |
3406 | * Think twice, and think again, before using these. | |
3407 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3408 | * intel_uncore_forcewake_irqunlock(). | |
3409 | */ | |
3410 | #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__)) | |
3411 | #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__)) | |
3412 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) | |
3413 | ||
55bc60db VS |
3414 | /* "Broadcast RGB" property */ |
3415 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3416 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3417 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3418 | |
766aa1c4 VS |
3419 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
3420 | { | |
92e23b99 | 3421 | if (IS_VALLEYVIEW(dev)) |
766aa1c4 | 3422 | return VLV_VGACNTRL; |
92e23b99 SJ |
3423 | else if (INTEL_INFO(dev)->gen >= 5) |
3424 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3425 | else |
3426 | return VGACNTRL; | |
3427 | } | |
3428 | ||
2bb4629a VS |
3429 | static inline void __user *to_user_ptr(u64 address) |
3430 | { | |
3431 | return (void __user *)(uintptr_t)address; | |
3432 | } | |
3433 | ||
df97729f ID |
3434 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3435 | { | |
3436 | unsigned long j = msecs_to_jiffies(m); | |
3437 | ||
3438 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3439 | } | |
3440 | ||
7bd0e226 DV |
3441 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3442 | { | |
3443 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3444 | } | |
3445 | ||
df97729f ID |
3446 | static inline unsigned long |
3447 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3448 | { | |
3449 | unsigned long j = timespec_to_jiffies(value); | |
3450 | ||
3451 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3452 | } | |
3453 | ||
dce56b3c PZ |
3454 | /* |
3455 | * If you need to wait X milliseconds between events A and B, but event B | |
3456 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3457 | * when event A happened, then just before event B you call this function and | |
3458 | * pass the timestamp as the first argument, and X as the second argument. | |
3459 | */ | |
3460 | static inline void | |
3461 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3462 | { | |
ec5e0cfb | 3463 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3464 | |
3465 | /* | |
3466 | * Don't re-read the value of "jiffies" every time since it may change | |
3467 | * behind our back and break the math. | |
3468 | */ | |
3469 | tmp_jiffies = jiffies; | |
3470 | target_jiffies = timestamp_jiffies + | |
3471 | msecs_to_jiffies_timeout(to_wait_ms); | |
3472 | ||
3473 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3474 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3475 | while (remaining_jiffies) | |
3476 | remaining_jiffies = | |
3477 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3478 | } |
3479 | } | |
3480 | ||
581c26e8 JH |
3481 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3482 | struct drm_i915_gem_request *req) | |
3483 | { | |
3484 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) | |
3485 | i915_gem_request_assign(&ring->trace_irq_req, req); | |
3486 | } | |
3487 | ||
1da177e4 | 3488 | #endif |