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CommitLineData
1da177e4
LT
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
e9b73c67 33#include <uapi/drm/i915_drm.h>
93b81f51 34#include <uapi/drm/drm_fourcc.h>
e9b73c67 35
585fb111 36#include "i915_reg.h"
79e53945 37#include "intel_bios.h"
8187a2b7 38#include "intel_ringbuffer.h"
b20385f1 39#include "intel_lrc.h"
0260c420 40#include "i915_gem_gtt.h"
564ddb2f 41#include "i915_gem_render_state.h"
0839ccb8 42#include <linux/io-mapping.h>
f899fc64 43#include <linux/i2c.h>
c167a6fc 44#include <linux/i2c-algo-bit.h>
0ade6386 45#include <drm/intel-gtt.h>
ba8286fa 46#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
d9fc9413 47#include <drm/drm_gem.h>
aaa6fd2a 48#include <linux/backlight.h>
5cc9ed4b 49#include <linux/hashtable.h>
2911a35b 50#include <linux/intel-iommu.h>
742cbee8 51#include <linux/kref.h>
9ee32fea 52#include <linux/pm_qos.h>
585fb111 53
1da177e4
LT
54/* General customization:
55 */
56
1da177e4
LT
57#define DRIVER_NAME "i915"
58#define DRIVER_DESC "Intel Graphics"
f89fe1ff 59#define DRIVER_DATE "20150227"
1da177e4 60
c883ef1b 61#undef WARN_ON
5f77eeb0
DV
62/* Many gcc seem to no see through this and fall over :( */
63#if 0
64#define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
69#else
70#define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
71#endif
72
73#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
74 (long) (x), __func__);
c883ef1b 75
e2c719b7
RC
76/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
77 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
78 * which may not necessarily be a user visible problem. This will either
79 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
80 * enable distros and users to tailor their preferred amount of i915 abrt
81 * spam.
82 */
83#define I915_STATE_WARN(condition, format...) ({ \
84 int __ret_warn_on = !!(condition); \
85 if (unlikely(__ret_warn_on)) { \
86 if (i915.verbose_state_checks) \
2f3408c7 87 WARN(1, format); \
e2c719b7
RC
88 else \
89 DRM_ERROR(format); \
90 } \
91 unlikely(__ret_warn_on); \
92})
93
94#define I915_STATE_WARN_ON(condition) ({ \
95 int __ret_warn_on = !!(condition); \
96 if (unlikely(__ret_warn_on)) { \
97 if (i915.verbose_state_checks) \
2f3408c7 98 WARN(1, "WARN_ON(" #condition ")\n"); \
e2c719b7
RC
99 else \
100 DRM_ERROR("WARN_ON(" #condition ")\n"); \
101 } \
102 unlikely(__ret_warn_on); \
103})
c883ef1b 104
317c35d1 105enum pipe {
752aa88a 106 INVALID_PIPE = -1,
317c35d1
JB
107 PIPE_A = 0,
108 PIPE_B,
9db4a9c7 109 PIPE_C,
a57c774a
AK
110 _PIPE_EDP,
111 I915_MAX_PIPES = _PIPE_EDP
317c35d1 112};
9db4a9c7 113#define pipe_name(p) ((p) + 'A')
317c35d1 114
a5c961d1
PZ
115enum transcoder {
116 TRANSCODER_A = 0,
117 TRANSCODER_B,
118 TRANSCODER_C,
a57c774a
AK
119 TRANSCODER_EDP,
120 I915_MAX_TRANSCODERS
a5c961d1
PZ
121};
122#define transcoder_name(t) ((t) + 'A')
123
84139d1e
DL
124/*
125 * This is the maximum (across all platforms) number of planes (primary +
126 * sprites) that can be active at the same time on one pipe.
127 *
128 * This value doesn't count the cursor plane.
129 */
130#define I915_MAX_PLANES 3
131
80824003
JB
132enum plane {
133 PLANE_A = 0,
134 PLANE_B,
9db4a9c7 135 PLANE_C,
80824003 136};
9db4a9c7 137#define plane_name(p) ((p) + 'A')
52440211 138
d615a166 139#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
06da8da2 140
2b139522
ED
141enum port {
142 PORT_A = 0,
143 PORT_B,
144 PORT_C,
145 PORT_D,
146 PORT_E,
147 I915_MAX_PORTS
148};
149#define port_name(p) ((p) + 'A')
150
a09caddd 151#define I915_NUM_PHYS_VLV 2
e4607fcf
CML
152
153enum dpio_channel {
154 DPIO_CH0,
155 DPIO_CH1
156};
157
158enum dpio_phy {
159 DPIO_PHY0,
160 DPIO_PHY1
161};
162
b97186f0
PZ
163enum intel_display_power_domain {
164 POWER_DOMAIN_PIPE_A,
165 POWER_DOMAIN_PIPE_B,
166 POWER_DOMAIN_PIPE_C,
167 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
168 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
169 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
170 POWER_DOMAIN_TRANSCODER_A,
171 POWER_DOMAIN_TRANSCODER_B,
172 POWER_DOMAIN_TRANSCODER_C,
f52e353e 173 POWER_DOMAIN_TRANSCODER_EDP,
319be8ae
ID
174 POWER_DOMAIN_PORT_DDI_A_2_LANES,
175 POWER_DOMAIN_PORT_DDI_A_4_LANES,
176 POWER_DOMAIN_PORT_DDI_B_2_LANES,
177 POWER_DOMAIN_PORT_DDI_B_4_LANES,
178 POWER_DOMAIN_PORT_DDI_C_2_LANES,
179 POWER_DOMAIN_PORT_DDI_C_4_LANES,
180 POWER_DOMAIN_PORT_DDI_D_2_LANES,
181 POWER_DOMAIN_PORT_DDI_D_4_LANES,
182 POWER_DOMAIN_PORT_DSI,
183 POWER_DOMAIN_PORT_CRT,
184 POWER_DOMAIN_PORT_OTHER,
cdf8dd7f 185 POWER_DOMAIN_VGA,
fbeeaa23 186 POWER_DOMAIN_AUDIO,
bd2bb1b9 187 POWER_DOMAIN_PLLS,
1407121a
S
188 POWER_DOMAIN_AUX_A,
189 POWER_DOMAIN_AUX_B,
190 POWER_DOMAIN_AUX_C,
191 POWER_DOMAIN_AUX_D,
baa70707 192 POWER_DOMAIN_INIT,
bddc7645
ID
193
194 POWER_DOMAIN_NUM,
b97186f0
PZ
195};
196
197#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
198#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
199 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
f52e353e
ID
200#define POWER_DOMAIN_TRANSCODER(tran) \
201 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
202 (tran) + POWER_DOMAIN_TRANSCODER_A)
b97186f0 203
1d843f9d
EE
204enum hpd_pin {
205 HPD_NONE = 0,
206 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
207 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
208 HPD_CRT,
209 HPD_SDVO_B,
210 HPD_SDVO_C,
211 HPD_PORT_B,
212 HPD_PORT_C,
213 HPD_PORT_D,
214 HPD_NUM_PINS
215};
216
2a2d5482
CW
217#define I915_GEM_GPU_DOMAINS \
218 (I915_GEM_DOMAIN_RENDER | \
219 I915_GEM_DOMAIN_SAMPLER | \
220 I915_GEM_DOMAIN_COMMAND | \
221 I915_GEM_DOMAIN_INSTRUCTION | \
222 I915_GEM_DOMAIN_VERTEX)
62fdfeaf 223
055e393f
DL
224#define for_each_pipe(__dev_priv, __p) \
225 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
dd740780
DL
226#define for_each_plane(__dev_priv, __pipe, __p) \
227 for ((__p) = 0; \
228 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
229 (__p)++)
3bdcfc0c
DL
230#define for_each_sprite(__dev_priv, __p, __s) \
231 for ((__s) = 0; \
232 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
233 (__s)++)
9db4a9c7 234
d79b814d
DL
235#define for_each_crtc(dev, crtc) \
236 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
237
d063ae48
DL
238#define for_each_intel_crtc(dev, intel_crtc) \
239 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
240
b2784e15
DL
241#define for_each_intel_encoder(dev, intel_encoder) \
242 list_for_each_entry(intel_encoder, \
243 &(dev)->mode_config.encoder_list, \
244 base.head)
245
3a3371ff
ACO
246#define for_each_intel_connector(dev, intel_connector) \
247 list_for_each_entry(intel_connector, \
248 &dev->mode_config.connector_list, \
249 base.head)
250
251
6c2b7c12
DV
252#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
253 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
254 if ((intel_encoder)->base.crtc == (__crtc))
255
53f5e3ca
JB
256#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
257 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
258 if ((intel_connector)->base.encoder == (__encoder))
259
b04c5bd6
BF
260#define for_each_power_domain(domain, mask) \
261 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
262 if ((1 << (domain)) & (mask))
263
e7b903d2 264struct drm_i915_private;
ad46cb53 265struct i915_mm_struct;
5cc9ed4b 266struct i915_mmu_object;
e7b903d2 267
46edb027
DV
268enum intel_dpll_id {
269 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
270 /* real shared dpll ids must be >= 0 */
9cd86933
DV
271 DPLL_ID_PCH_PLL_A = 0,
272 DPLL_ID_PCH_PLL_B = 1,
429d47d5 273 /* hsw/bdw */
9cd86933
DV
274 DPLL_ID_WRPLL1 = 0,
275 DPLL_ID_WRPLL2 = 1,
429d47d5
S
276 /* skl */
277 DPLL_ID_SKL_DPLL1 = 0,
278 DPLL_ID_SKL_DPLL2 = 1,
279 DPLL_ID_SKL_DPLL3 = 2,
46edb027 280};
429d47d5 281#define I915_NUM_PLLS 3
46edb027 282
5358901f 283struct intel_dpll_hw_state {
dcfc3552 284 /* i9xx, pch plls */
66e985c0 285 uint32_t dpll;
8bcc2795 286 uint32_t dpll_md;
66e985c0
DV
287 uint32_t fp0;
288 uint32_t fp1;
dcfc3552
DL
289
290 /* hsw, bdw */
d452c5b6 291 uint32_t wrpll;
d1a2dc78
S
292
293 /* skl */
294 /*
295 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
296 * lower part of crtl1 and they get shifted into position when writing
297 * the register. This allows us to easily compare the state to share
298 * the DPLL.
299 */
300 uint32_t ctrl1;
301 /* HDMI only, 0 when used for DP */
302 uint32_t cfgcr1, cfgcr2;
5358901f
DV
303};
304
3e369b76 305struct intel_shared_dpll_config {
1e6f2ddc 306 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
3e369b76
ACO
307 struct intel_dpll_hw_state hw_state;
308};
309
310struct intel_shared_dpll {
311 struct intel_shared_dpll_config config;
8bd31e67
ACO
312 struct intel_shared_dpll_config *new_config;
313
ee7b9f93
JB
314 int active; /* count of number of active CRTCs (i.e. DPMS on) */
315 bool on; /* is the PLL actually active? Disabled during modeset */
46edb027
DV
316 const char *name;
317 /* should match the index in the dev_priv->shared_dplls array */
318 enum intel_dpll_id id;
96f6128c
DV
319 /* The mode_set hook is optional and should be used together with the
320 * intel_prepare_shared_dpll function. */
15bdd4cf
DV
321 void (*mode_set)(struct drm_i915_private *dev_priv,
322 struct intel_shared_dpll *pll);
e7b903d2
DV
323 void (*enable)(struct drm_i915_private *dev_priv,
324 struct intel_shared_dpll *pll);
325 void (*disable)(struct drm_i915_private *dev_priv,
326 struct intel_shared_dpll *pll);
5358901f
DV
327 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
328 struct intel_shared_dpll *pll,
329 struct intel_dpll_hw_state *hw_state);
ee7b9f93 330};
ee7b9f93 331
429d47d5
S
332#define SKL_DPLL0 0
333#define SKL_DPLL1 1
334#define SKL_DPLL2 2
335#define SKL_DPLL3 3
336
e69d0bc1
DV
337/* Used by dp and fdi links */
338struct intel_link_m_n {
339 uint32_t tu;
340 uint32_t gmch_m;
341 uint32_t gmch_n;
342 uint32_t link_m;
343 uint32_t link_n;
344};
345
346void intel_link_compute_m_n(int bpp, int nlanes,
347 int pixel_clock, int link_clock,
348 struct intel_link_m_n *m_n);
349
1da177e4
LT
350/* Interface history:
351 *
352 * 1.1: Original.
0d6aa60b
DA
353 * 1.2: Add Power Management
354 * 1.3: Add vblank support
de227f5f 355 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 356 * 1.5: Add vblank pipe configuration
2228ed67
MD
357 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
358 * - Support vertical blank on secondary display pipe
1da177e4
LT
359 */
360#define DRIVER_MAJOR 1
2228ed67 361#define DRIVER_MINOR 6
1da177e4
LT
362#define DRIVER_PATCHLEVEL 0
363
23bc5982 364#define WATCH_LISTS 0
673a394b 365
0a3e67a4
JB
366struct opregion_header;
367struct opregion_acpi;
368struct opregion_swsci;
369struct opregion_asle;
370
8ee1c3db 371struct intel_opregion {
5bc4418b
BW
372 struct opregion_header __iomem *header;
373 struct opregion_acpi __iomem *acpi;
374 struct opregion_swsci __iomem *swsci;
ebde53c7
JN
375 u32 swsci_gbda_sub_functions;
376 u32 swsci_sbcb_sub_functions;
5bc4418b
BW
377 struct opregion_asle __iomem *asle;
378 void __iomem *vbt;
01fe9dbd 379 u32 __iomem *lid_state;
91a60f20 380 struct work_struct asle_work;
8ee1c3db 381};
44834a67 382#define OPREGION_SIZE (8*1024)
8ee1c3db 383
6ef3d427
CW
384struct intel_overlay;
385struct intel_overlay_error_state;
386
de151cf6 387#define I915_FENCE_REG_NONE -1
42b5aeab
VS
388#define I915_MAX_NUM_FENCES 32
389/* 32 fences + sign bit for FENCE_REG_NONE */
390#define I915_MAX_NUM_FENCE_BITS 6
de151cf6
JB
391
392struct drm_i915_fence_reg {
007cc8ac 393 struct list_head lru_list;
caea7476 394 struct drm_i915_gem_object *obj;
1690e1eb 395 int pin_count;
de151cf6 396};
7c1c2871 397
9b9d172d 398struct sdvo_device_mapping {
e957d772 399 u8 initialized;
9b9d172d 400 u8 dvo_port;
401 u8 slave_addr;
402 u8 dvo_wiring;
e957d772 403 u8 i2c_pin;
b1083333 404 u8 ddc_pin;
9b9d172d 405};
406
c4a1d9e4
CW
407struct intel_display_error_state;
408
63eeaf38 409struct drm_i915_error_state {
742cbee8 410 struct kref ref;
585b0288
BW
411 struct timeval time;
412
cb383002 413 char error_msg[128];
48b031e3 414 u32 reset_count;
62d5d69b 415 u32 suspend_count;
cb383002 416
585b0288 417 /* Generic register state */
63eeaf38
JB
418 u32 eir;
419 u32 pgtbl_er;
be998e2e 420 u32 ier;
885ea5a8 421 u32 gtier[4];
b9a3906b 422 u32 ccid;
0f3b6849
CW
423 u32 derrmr;
424 u32 forcewake;
585b0288
BW
425 u32 error; /* gen6+ */
426 u32 err_int; /* gen7 */
427 u32 done_reg;
91ec5d11
BW
428 u32 gac_eco;
429 u32 gam_ecochk;
430 u32 gab_ctl;
431 u32 gfx_mode;
585b0288 432 u32 extra_instdone[I915_NUM_INSTDONE_REG];
585b0288
BW
433 u64 fence[I915_MAX_NUM_FENCES];
434 struct intel_overlay_error_state *overlay;
435 struct intel_display_error_state *display;
0ca36d78 436 struct drm_i915_error_object *semaphore_obj;
585b0288 437
52d39a21 438 struct drm_i915_error_ring {
372fbb8e 439 bool valid;
362b8af7
BW
440 /* Software tracked state */
441 bool waiting;
442 int hangcheck_score;
443 enum intel_ring_hangcheck_action hangcheck_action;
444 int num_requests;
445
446 /* our own tracking of ring head and tail */
447 u32 cpu_ring_head;
448 u32 cpu_ring_tail;
449
450 u32 semaphore_seqno[I915_NUM_RINGS - 1];
451
452 /* Register state */
453 u32 tail;
454 u32 head;
455 u32 ctl;
456 u32 hws;
457 u32 ipeir;
458 u32 ipehr;
459 u32 instdone;
362b8af7
BW
460 u32 bbstate;
461 u32 instpm;
462 u32 instps;
463 u32 seqno;
464 u64 bbaddr;
50877445 465 u64 acthd;
362b8af7 466 u32 fault_reg;
13ffadd1 467 u64 faddr;
362b8af7
BW
468 u32 rc_psmi; /* sleep state */
469 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
470
52d39a21
CW
471 struct drm_i915_error_object {
472 int page_count;
473 u32 gtt_offset;
474 u32 *pages[0];
ab0e7ff9 475 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
362b8af7 476
52d39a21
CW
477 struct drm_i915_error_request {
478 long jiffies;
479 u32 seqno;
ee4f42b1 480 u32 tail;
52d39a21 481 } *requests;
6c7a01ec
BW
482
483 struct {
484 u32 gfx_mode;
485 union {
486 u64 pdp[4];
487 u32 pp_dir_base;
488 };
489 } vm_info;
ab0e7ff9
CW
490
491 pid_t pid;
492 char comm[TASK_COMM_LEN];
52d39a21 493 } ring[I915_NUM_RINGS];
3a448734 494
9df30794 495 struct drm_i915_error_buffer {
a779e5ab 496 u32 size;
9df30794 497 u32 name;
0201f1ec 498 u32 rseqno, wseqno;
9df30794
CW
499 u32 gtt_offset;
500 u32 read_domains;
501 u32 write_domain;
4b9de737 502 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
9df30794
CW
503 s32 pinned:2;
504 u32 tiling:2;
505 u32 dirty:1;
506 u32 purgeable:1;
5cc9ed4b 507 u32 userptr:1;
5d1333fc 508 s32 ring:4;
f56383cb 509 u32 cache_level:3;
95f5301d 510 } **active_bo, **pinned_bo;
6c7a01ec 511
95f5301d 512 u32 *active_bo_count, *pinned_bo_count;
3a448734 513 u32 vm_count;
63eeaf38
JB
514};
515
7bd688cd 516struct intel_connector;
820d2d77 517struct intel_encoder;
5cec258b 518struct intel_crtc_state;
5724dbd1 519struct intel_initial_plane_config;
0e8ffe1b 520struct intel_crtc;
ee9300bb
DV
521struct intel_limit;
522struct dpll;
b8cecdf5 523
e70236a8 524struct drm_i915_display_funcs {
ee5382ae 525 bool (*fbc_enabled)(struct drm_device *dev);
993495ae 526 void (*enable_fbc)(struct drm_crtc *crtc);
e70236a8
JB
527 void (*disable_fbc)(struct drm_device *dev);
528 int (*get_display_clock_speed)(struct drm_device *dev);
529 int (*get_fifo_size)(struct drm_device *dev, int plane);
ee9300bb
DV
530 /**
531 * find_dpll() - Find the best values for the PLL
532 * @limit: limits for the PLL
533 * @crtc: current CRTC
534 * @target: target frequency in kHz
535 * @refclk: reference clock frequency in kHz
536 * @match_clock: if provided, @best_clock P divider must
537 * match the P divider from @match_clock
538 * used for LVDS downclocking
539 * @best_clock: best PLL values found
540 *
541 * Returns true on success, false on failure.
542 */
543 bool (*find_dpll)(const struct intel_limit *limit,
a919ff14 544 struct intel_crtc *crtc,
ee9300bb
DV
545 int target, int refclk,
546 struct dpll *match_clock,
547 struct dpll *best_clock);
46ba614c 548 void (*update_wm)(struct drm_crtc *crtc);
adf3d35e
VS
549 void (*update_sprite_wm)(struct drm_plane *plane,
550 struct drm_crtc *crtc,
ed57cb8a
DL
551 uint32_t sprite_width, uint32_t sprite_height,
552 int pixel_size, bool enable, bool scaled);
47fab737 553 void (*modeset_global_resources)(struct drm_device *dev);
0e8ffe1b
DV
554 /* Returns the active state of the crtc, and if the crtc is active,
555 * fills out the pipe-config with the hw state. */
556 bool (*get_pipe_config)(struct intel_crtc *,
5cec258b 557 struct intel_crtc_state *);
5724dbd1
DL
558 void (*get_initial_plane_config)(struct intel_crtc *,
559 struct intel_initial_plane_config *);
190f68c5
ACO
560 int (*crtc_compute_clock)(struct intel_crtc *crtc,
561 struct intel_crtc_state *crtc_state);
76e5a89c
DV
562 void (*crtc_enable)(struct drm_crtc *crtc);
563 void (*crtc_disable)(struct drm_crtc *crtc);
ee7b9f93 564 void (*off)(struct drm_crtc *crtc);
69bfe1a9
JN
565 void (*audio_codec_enable)(struct drm_connector *connector,
566 struct intel_encoder *encoder,
567 struct drm_display_mode *mode);
568 void (*audio_codec_disable)(struct intel_encoder *encoder);
674cf967 569 void (*fdi_link_train)(struct drm_crtc *crtc);
6067aaea 570 void (*init_clock_gating)(struct drm_device *dev);
8c9f3aaf
JB
571 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
572 struct drm_framebuffer *fb,
ed8d1975 573 struct drm_i915_gem_object *obj,
a4872ba6 574 struct intel_engine_cs *ring,
ed8d1975 575 uint32_t flags);
29b9bde6
DV
576 void (*update_primary_plane)(struct drm_crtc *crtc,
577 struct drm_framebuffer *fb,
578 int x, int y);
20afbda2 579 void (*hpd_irq_setup)(struct drm_device *dev);
e70236a8
JB
580 /* clock updates for mode set */
581 /* cursor updates */
582 /* render clock increase/decrease */
583 /* display clock increase/decrease */
584 /* pll clock increase/decrease */
7bd688cd 585
6517d273 586 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
7bd688cd
JN
587 uint32_t (*get_backlight)(struct intel_connector *connector);
588 void (*set_backlight)(struct intel_connector *connector,
589 uint32_t level);
590 void (*disable_backlight)(struct intel_connector *connector);
591 void (*enable_backlight)(struct intel_connector *connector);
e70236a8
JB
592};
593
48c1026a
MK
594enum forcewake_domain_id {
595 FW_DOMAIN_ID_RENDER = 0,
596 FW_DOMAIN_ID_BLITTER,
597 FW_DOMAIN_ID_MEDIA,
598
599 FW_DOMAIN_ID_COUNT
600};
601
602enum forcewake_domains {
603 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
604 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
605 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
606 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
607 FORCEWAKE_BLITTER |
608 FORCEWAKE_MEDIA)
609};
610
907b28c5 611struct intel_uncore_funcs {
c8d9a590 612 void (*force_wake_get)(struct drm_i915_private *dev_priv,
48c1026a 613 enum forcewake_domains domains);
c8d9a590 614 void (*force_wake_put)(struct drm_i915_private *dev_priv,
48c1026a 615 enum forcewake_domains domains);
0b274481
BW
616
617 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
618 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
619 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
620 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
621
622 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
623 uint8_t val, bool trace);
624 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
625 uint16_t val, bool trace);
626 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
627 uint32_t val, bool trace);
628 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
629 uint64_t val, bool trace);
990bbdad
CW
630};
631
907b28c5
CW
632struct intel_uncore {
633 spinlock_t lock; /** lock is also taken in irq contexts. */
634
635 struct intel_uncore_funcs funcs;
636
637 unsigned fifo_count;
48c1026a 638 enum forcewake_domains fw_domains;
b2cff0db
CW
639
640 struct intel_uncore_forcewake_domain {
641 struct drm_i915_private *i915;
48c1026a 642 enum forcewake_domain_id id;
b2cff0db
CW
643 unsigned wake_count;
644 struct timer_list timer;
05a2fb15
MK
645 u32 reg_set;
646 u32 val_set;
647 u32 val_clear;
648 u32 reg_ack;
649 u32 reg_post;
650 u32 val_reset;
b2cff0db 651 } fw_domain[FW_DOMAIN_ID_COUNT];
b2cff0db
CW
652};
653
654/* Iterate over initialised fw domains */
655#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
656 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
657 (i__) < FW_DOMAIN_ID_COUNT; \
658 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
659 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
660
661#define for_each_fw_domain(domain__, dev_priv__, i__) \
662 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
907b28c5 663
79fc46df
DL
664#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
665 func(is_mobile) sep \
666 func(is_i85x) sep \
667 func(is_i915g) sep \
668 func(is_i945gm) sep \
669 func(is_g33) sep \
670 func(need_gfx_hws) sep \
671 func(is_g4x) sep \
672 func(is_pineview) sep \
673 func(is_broadwater) sep \
674 func(is_crestline) sep \
675 func(is_ivybridge) sep \
676 func(is_valleyview) sep \
677 func(is_haswell) sep \
7201c0b3 678 func(is_skylake) sep \
b833d685 679 func(is_preliminary) sep \
79fc46df
DL
680 func(has_fbc) sep \
681 func(has_pipe_cxsr) sep \
682 func(has_hotplug) sep \
683 func(cursor_needs_physical) sep \
684 func(has_overlay) sep \
685 func(overlay_needs_physical) sep \
686 func(supports_tv) sep \
dd93be58 687 func(has_llc) sep \
30568c45
DL
688 func(has_ddi) sep \
689 func(has_fpga_dbg)
c96ea64e 690
a587f779
DL
691#define DEFINE_FLAG(name) u8 name:1
692#define SEP_SEMICOLON ;
c96ea64e 693
cfdf1fa2 694struct intel_device_info {
10fce67a 695 u32 display_mmio_offset;
87f1f465 696 u16 device_id;
7eb552ae 697 u8 num_pipes:3;
d615a166 698 u8 num_sprites[I915_MAX_PIPES];
c96c3a8c 699 u8 gen;
73ae478c 700 u8 ring_mask; /* Rings supported by the HW */
a587f779 701 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
a57c774a
AK
702 /* Register offsets for the various display pipes and transcoders */
703 int pipe_offsets[I915_MAX_TRANSCODERS];
704 int trans_offsets[I915_MAX_TRANSCODERS];
a57c774a 705 int palette_offsets[I915_MAX_PIPES];
5efb3e28 706 int cursor_offsets[I915_MAX_PIPES];
3873218f
JM
707
708 /* Slice/subslice/EU info */
709 u8 slice_total;
710 u8 subslice_total;
711 u8 subslice_per_slice;
712 u8 eu_total;
713 u8 eu_per_subslice;
b7668791
DL
714 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
715 u8 subslice_7eu[3];
3873218f
JM
716 u8 has_slice_pg:1;
717 u8 has_subslice_pg:1;
718 u8 has_eu_pg:1;
cfdf1fa2
KH
719};
720
a587f779
DL
721#undef DEFINE_FLAG
722#undef SEP_SEMICOLON
723
7faf1ab2
DV
724enum i915_cache_level {
725 I915_CACHE_NONE = 0,
350ec881
CW
726 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
727 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
728 caches, eg sampler/render caches, and the
729 large Last-Level-Cache. LLC is coherent with
730 the CPU, but L3 is only visible to the GPU. */
651d794f 731 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
7faf1ab2
DV
732};
733
e59ec13d
MK
734struct i915_ctx_hang_stats {
735 /* This context had batch pending when hang was declared */
736 unsigned batch_pending;
737
738 /* This context had batch active when hang was declared */
739 unsigned batch_active;
be62acb4
MK
740
741 /* Time when this context was last blamed for a GPU reset */
742 unsigned long guilty_ts;
743
676fa572
CW
744 /* If the contexts causes a second GPU hang within this time,
745 * it is permanently banned from submitting any more work.
746 */
747 unsigned long ban_period_seconds;
748
be62acb4
MK
749 /* This context is banned to submit more work */
750 bool banned;
e59ec13d 751};
40521054
BW
752
753/* This must match up with the value previously used for execbuf2.rsvd1. */
821d66dd 754#define DEFAULT_CONTEXT_HANDLE 0
31b7a88d
OM
755/**
756 * struct intel_context - as the name implies, represents a context.
757 * @ref: reference count.
758 * @user_handle: userspace tracking identity for this context.
759 * @remap_slice: l3 row remapping information.
760 * @file_priv: filp associated with this context (NULL for global default
761 * context).
762 * @hang_stats: information about the role of this context in possible GPU
763 * hangs.
764 * @vm: virtual memory space used by this context.
765 * @legacy_hw_ctx: render context backing object and whether it is correctly
766 * initialized (legacy ring submission mechanism only).
767 * @link: link in the global list of contexts.
768 *
769 * Contexts are memory images used by the hardware to store copies of their
770 * internal state.
771 */
273497e5 772struct intel_context {
dce3271b 773 struct kref ref;
821d66dd 774 int user_handle;
3ccfd19d 775 uint8_t remap_slice;
40521054 776 struct drm_i915_file_private *file_priv;
e59ec13d 777 struct i915_ctx_hang_stats hang_stats;
ae6c4806 778 struct i915_hw_ppgtt *ppgtt;
a33afea5 779
c9e003af 780 /* Legacy ring buffer submission */
ea0c76f8
OM
781 struct {
782 struct drm_i915_gem_object *rcs_state;
783 bool initialized;
784 } legacy_hw_ctx;
785
c9e003af 786 /* Execlists */
564ddb2f 787 bool rcs_initialized;
c9e003af
OM
788 struct {
789 struct drm_i915_gem_object *state;
84c2377f 790 struct intel_ringbuffer *ringbuf;
a7cbedec 791 int pin_count;
c9e003af
OM
792 } engine[I915_NUM_RINGS];
793
a33afea5 794 struct list_head link;
40521054
BW
795};
796
a4001f1b
PZ
797enum fb_op_origin {
798 ORIGIN_GTT,
799 ORIGIN_CPU,
800 ORIGIN_CS,
801 ORIGIN_FLIP,
802};
803
5c3fe8b0 804struct i915_fbc {
60ee5cd2 805 unsigned long uncompressed_size;
5e59f717 806 unsigned threshold;
5c3fe8b0 807 unsigned int fb_id;
dbef0f15
PZ
808 unsigned int possible_framebuffer_bits;
809 unsigned int busy_bits;
e35fef21 810 struct intel_crtc *crtc;
5c3fe8b0
BW
811 int y;
812
c4213885 813 struct drm_mm_node compressed_fb;
5c3fe8b0
BW
814 struct drm_mm_node *compressed_llb;
815
da46f936
RV
816 bool false_color;
817
9adccc60
PZ
818 /* Tracks whether the HW is actually enabled, not whether the feature is
819 * possible. */
820 bool enabled;
821
5c3fe8b0
BW
822 struct intel_fbc_work {
823 struct delayed_work work;
824 struct drm_crtc *crtc;
825 struct drm_framebuffer *fb;
5c3fe8b0
BW
826 } *fbc_work;
827
29ebf90f
CW
828 enum no_fbc_reason {
829 FBC_OK, /* FBC is enabled */
830 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
5c3fe8b0
BW
831 FBC_NO_OUTPUT, /* no outputs enabled to compress */
832 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
833 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
834 FBC_MODE_TOO_LARGE, /* mode too large for compression */
835 FBC_BAD_PLANE, /* fbc not supported on plane */
836 FBC_NOT_TILED, /* buffer not tiled */
837 FBC_MULTIPLE_PIPES, /* more than one pipe active */
838 FBC_MODULE_PARAM,
839 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
840 } no_fbc_reason;
b5e50c3f
JB
841};
842
96178eeb
VK
843/**
844 * HIGH_RR is the highest eDP panel refresh rate read from EDID
845 * LOW_RR is the lowest eDP panel refresh rate found from EDID
846 * parsing for same resolution.
847 */
848enum drrs_refresh_rate_type {
849 DRRS_HIGH_RR,
850 DRRS_LOW_RR,
851 DRRS_MAX_RR, /* RR count */
852};
853
854enum drrs_support_type {
855 DRRS_NOT_SUPPORTED = 0,
856 STATIC_DRRS_SUPPORT = 1,
857 SEAMLESS_DRRS_SUPPORT = 2
439d7ac0
PB
858};
859
2807cf69 860struct intel_dp;
96178eeb
VK
861struct i915_drrs {
862 struct mutex mutex;
863 struct delayed_work work;
864 struct intel_dp *dp;
865 unsigned busy_frontbuffer_bits;
866 enum drrs_refresh_rate_type refresh_rate_type;
867 enum drrs_support_type type;
868};
869
a031d709 870struct i915_psr {
f0355c4a 871 struct mutex lock;
a031d709
RV
872 bool sink_support;
873 bool source_ok;
2807cf69 874 struct intel_dp *enabled;
7c8f8a70
RV
875 bool active;
876 struct delayed_work work;
9ca15301 877 unsigned busy_frontbuffer_bits;
0243f7ba 878 bool link_standby;
3f51e471 879};
5c3fe8b0 880
3bad0781 881enum intel_pch {
f0350830 882 PCH_NONE = 0, /* No PCH present */
3bad0781
ZW
883 PCH_IBX, /* Ibexpeak PCH */
884 PCH_CPT, /* Cougarpoint PCH */
eb877ebf 885 PCH_LPT, /* Lynxpoint PCH */
e7e7ea20 886 PCH_SPT, /* Sunrisepoint PCH */
40c7ead9 887 PCH_NOP,
3bad0781
ZW
888};
889
988d6ee8
PZ
890enum intel_sbi_destination {
891 SBI_ICLK,
892 SBI_MPHY,
893};
894
b690e96c 895#define QUIRK_PIPEA_FORCE (1<<0)
435793df 896#define QUIRK_LVDS_SSC_DISABLE (1<<1)
4dca20ef 897#define QUIRK_INVERT_BRIGHTNESS (1<<2)
9c72cc6f 898#define QUIRK_BACKLIGHT_PRESENT (1<<3)
b6b5d049 899#define QUIRK_PIPEB_FORCE (1<<4)
656bfa3a 900#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
b690e96c 901
8be48d92 902struct intel_fbdev;
1630fe75 903struct intel_fbc_work;
38651674 904
c2b9152f
DV
905struct intel_gmbus {
906 struct i2c_adapter adapter;
f2ce9faf 907 u32 force_bit;
c2b9152f 908 u32 reg0;
36c785f0 909 u32 gpio_reg;
c167a6fc 910 struct i2c_algo_bit_data bit_algo;
c2b9152f
DV
911 struct drm_i915_private *dev_priv;
912};
913
f4c956ad 914struct i915_suspend_saved_registers {
e948e994 915 u32 saveDSPARB;
ba8bbcf6 916 u32 saveLVDS;
585fb111
JB
917 u32 savePP_ON_DELAYS;
918 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB
919 u32 savePP_ON;
920 u32 savePP_OFF;
921 u32 savePP_CONTROL;
585fb111 922 u32 savePP_DIVISOR;
ba8bbcf6 923 u32 saveFBC_CONTROL;
1f84e550 924 u32 saveCACHE_MODE_0;
1f84e550 925 u32 saveMI_ARB_STATE;
ba8bbcf6
JB
926 u32 saveSWF0[16];
927 u32 saveSWF1[16];
928 u32 saveSWF2[3];
4b9de737 929 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
cda2bb78 930 u32 savePCH_PORT_HOTPLUG;
9f49c376 931 u16 saveGCDGMBUS;
f4c956ad 932};
c85aa885 933
ddeea5b0
ID
934struct vlv_s0ix_state {
935 /* GAM */
936 u32 wr_watermark;
937 u32 gfx_prio_ctrl;
938 u32 arb_mode;
939 u32 gfx_pend_tlb0;
940 u32 gfx_pend_tlb1;
941 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
942 u32 media_max_req_count;
943 u32 gfx_max_req_count;
944 u32 render_hwsp;
945 u32 ecochk;
946 u32 bsd_hwsp;
947 u32 blt_hwsp;
948 u32 tlb_rd_addr;
949
950 /* MBC */
951 u32 g3dctl;
952 u32 gsckgctl;
953 u32 mbctl;
954
955 /* GCP */
956 u32 ucgctl1;
957 u32 ucgctl3;
958 u32 rcgctl1;
959 u32 rcgctl2;
960 u32 rstctl;
961 u32 misccpctl;
962
963 /* GPM */
964 u32 gfxpause;
965 u32 rpdeuhwtc;
966 u32 rpdeuc;
967 u32 ecobus;
968 u32 pwrdwnupctl;
969 u32 rp_down_timeout;
970 u32 rp_deucsw;
971 u32 rcubmabdtmr;
972 u32 rcedata;
973 u32 spare2gh;
974
975 /* Display 1 CZ domain */
976 u32 gt_imr;
977 u32 gt_ier;
978 u32 pm_imr;
979 u32 pm_ier;
980 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
981
982 /* GT SA CZ domain */
983 u32 tilectl;
984 u32 gt_fifoctl;
985 u32 gtlc_wake_ctrl;
986 u32 gtlc_survive;
987 u32 pmwgicz;
988
989 /* Display 2 CZ domain */
990 u32 gu_ctl0;
991 u32 gu_ctl1;
992 u32 clock_gate_dis2;
993};
994
bf225f20
CW
995struct intel_rps_ei {
996 u32 cz_clock;
997 u32 render_c0;
998 u32 media_c0;
31685c25
D
999};
1000
c85aa885 1001struct intel_gen6_power_mgmt {
d4d70aa5
ID
1002 /*
1003 * work, interrupts_enabled and pm_iir are protected by
1004 * dev_priv->irq_lock
1005 */
c85aa885 1006 struct work_struct work;
d4d70aa5 1007 bool interrupts_enabled;
c85aa885 1008 u32 pm_iir;
59cdb63d 1009
b39fb297
BW
1010 /* Frequencies are stored in potentially platform dependent multiples.
1011 * In other words, *_freq needs to be multiplied by X to be interesting.
1012 * Soft limits are those which are used for the dynamic reclocking done
1013 * by the driver (raise frequencies under heavy loads, and lower for
1014 * lighter loads). Hard limits are those imposed by the hardware.
1015 *
1016 * A distinction is made for overclocking, which is never enabled by
1017 * default, and is considered to be above the hard limit if it's
1018 * possible at all.
1019 */
1020 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1021 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1022 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1023 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1024 u8 min_freq; /* AKA RPn. Minimum frequency */
1025 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1026 u8 rp1_freq; /* "less than" RP0 power/freqency */
1027 u8 rp0_freq; /* Non-overclocked max frequency. */
67c3bf6f 1028 u32 cz_freq;
1a01ab3b 1029
31685c25 1030 u32 ei_interrupt_count;
1a01ab3b 1031
dd75fdc8
CW
1032 int last_adj;
1033 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1034
c0951f0c 1035 bool enabled;
1a01ab3b 1036 struct delayed_work delayed_resume_work;
4fc688ce 1037
bf225f20
CW
1038 /* manual wa residency calculations */
1039 struct intel_rps_ei up_ei, down_ei;
1040
4fc688ce
JB
1041 /*
1042 * Protects RPS/RC6 register access and PCU communication.
1043 * Must be taken after struct_mutex if nested.
1044 */
1045 struct mutex hw_lock;
c85aa885
DV
1046};
1047
1a240d4d
DV
1048/* defined intel_pm.c */
1049extern spinlock_t mchdev_lock;
1050
c85aa885
DV
1051struct intel_ilk_power_mgmt {
1052 u8 cur_delay;
1053 u8 min_delay;
1054 u8 max_delay;
1055 u8 fmax;
1056 u8 fstart;
1057
1058 u64 last_count1;
1059 unsigned long last_time1;
1060 unsigned long chipset_power;
1061 u64 last_count2;
5ed0bdf2 1062 u64 last_time2;
c85aa885
DV
1063 unsigned long gfx_power;
1064 u8 corr;
1065
1066 int c_m;
1067 int r_t;
1068};
1069
c6cb582e
ID
1070struct drm_i915_private;
1071struct i915_power_well;
1072
1073struct i915_power_well_ops {
1074 /*
1075 * Synchronize the well's hw state to match the current sw state, for
1076 * example enable/disable it based on the current refcount. Called
1077 * during driver init and resume time, possibly after first calling
1078 * the enable/disable handlers.
1079 */
1080 void (*sync_hw)(struct drm_i915_private *dev_priv,
1081 struct i915_power_well *power_well);
1082 /*
1083 * Enable the well and resources that depend on it (for example
1084 * interrupts located on the well). Called after the 0->1 refcount
1085 * transition.
1086 */
1087 void (*enable)(struct drm_i915_private *dev_priv,
1088 struct i915_power_well *power_well);
1089 /*
1090 * Disable the well and resources that depend on it. Called after
1091 * the 1->0 refcount transition.
1092 */
1093 void (*disable)(struct drm_i915_private *dev_priv,
1094 struct i915_power_well *power_well);
1095 /* Returns the hw enabled state. */
1096 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1097 struct i915_power_well *power_well);
1098};
1099
a38911a3
WX
1100/* Power well structure for haswell */
1101struct i915_power_well {
c1ca727f 1102 const char *name;
6f3ef5dd 1103 bool always_on;
a38911a3
WX
1104 /* power well enable/disable usage count */
1105 int count;
bfafe93a
ID
1106 /* cached hw enabled state */
1107 bool hw_enabled;
c1ca727f 1108 unsigned long domains;
77961eb9 1109 unsigned long data;
c6cb582e 1110 const struct i915_power_well_ops *ops;
a38911a3
WX
1111};
1112
83c00f55 1113struct i915_power_domains {
baa70707
ID
1114 /*
1115 * Power wells needed for initialization at driver init and suspend
1116 * time are on. They are kept on until after the first modeset.
1117 */
1118 bool init_power_on;
0d116a29 1119 bool initializing;
c1ca727f 1120 int power_well_count;
baa70707 1121
83c00f55 1122 struct mutex lock;
1da51581 1123 int domain_use_count[POWER_DOMAIN_NUM];
c1ca727f 1124 struct i915_power_well *power_wells;
83c00f55
ID
1125};
1126
35a85ac6 1127#define MAX_L3_SLICES 2
a4da4fa4 1128struct intel_l3_parity {
35a85ac6 1129 u32 *remap_info[MAX_L3_SLICES];
a4da4fa4 1130 struct work_struct error_work;
35a85ac6 1131 int which_slice;
a4da4fa4
DV
1132};
1133
493018dc
BV
1134struct i915_gem_batch_pool {
1135 struct drm_device *dev;
1136 struct list_head cache_list;
1137};
1138
4b5aed62 1139struct i915_gem_mm {
4b5aed62
DV
1140 /** Memory allocator for GTT stolen memory */
1141 struct drm_mm stolen;
4b5aed62
DV
1142 /** List of all objects in gtt_space. Used to restore gtt
1143 * mappings on resume */
1144 struct list_head bound_list;
1145 /**
1146 * List of objects which are not bound to the GTT (thus
1147 * are idle and not used by the GPU) but still have
1148 * (presumably uncached) pages still attached.
1149 */
1150 struct list_head unbound_list;
1151
493018dc
BV
1152 /*
1153 * A pool of objects to use as shadow copies of client batch buffers
1154 * when the command parser is enabled. Prevents the client from
1155 * modifying the batch contents after software parsing.
1156 */
1157 struct i915_gem_batch_pool batch_pool;
1158
4b5aed62
DV
1159 /** Usable portion of the GTT for GEM */
1160 unsigned long stolen_base; /* limited to low memory (32-bit) */
1161
4b5aed62
DV
1162 /** PPGTT used for aliasing the PPGTT with the GTT */
1163 struct i915_hw_ppgtt *aliasing_ppgtt;
1164
2cfcd32a 1165 struct notifier_block oom_notifier;
ceabbba5 1166 struct shrinker shrinker;
4b5aed62
DV
1167 bool shrinker_no_lock_stealing;
1168
4b5aed62
DV
1169 /** LRU list of objects with fence regs on them. */
1170 struct list_head fence_list;
1171
1172 /**
1173 * We leave the user IRQ off as much as possible,
1174 * but this means that requests will finish and never
1175 * be retired once the system goes idle. Set a timer to
1176 * fire periodically while the ring is running. When it
1177 * fires, go retire requests.
1178 */
1179 struct delayed_work retire_work;
1180
b29c19b6
CW
1181 /**
1182 * When we detect an idle GPU, we want to turn on
1183 * powersaving features. So once we see that there
1184 * are no more requests outstanding and no more
1185 * arrive within a small period of time, we fire
1186 * off the idle_work.
1187 */
1188 struct delayed_work idle_work;
1189
4b5aed62
DV
1190 /**
1191 * Are we in a non-interruptible section of code like
1192 * modesetting?
1193 */
1194 bool interruptible;
1195
f62a0076
CW
1196 /**
1197 * Is the GPU currently considered idle, or busy executing userspace
1198 * requests? Whilst idle, we attempt to power down the hardware and
1199 * display clocks. In order to reduce the effect on performance, there
1200 * is a slight delay before we do so.
1201 */
1202 bool busy;
1203
bdf1e7e3
DV
1204 /* the indicator for dispatch video commands on two BSD rings */
1205 int bsd_ring_dispatch_index;
1206
4b5aed62
DV
1207 /** Bit 6 swizzling required for X tiling */
1208 uint32_t bit_6_swizzle_x;
1209 /** Bit 6 swizzling required for Y tiling */
1210 uint32_t bit_6_swizzle_y;
1211
4b5aed62 1212 /* accounting, useful for userland debugging */
c20e8355 1213 spinlock_t object_stat_lock;
4b5aed62
DV
1214 size_t object_memory;
1215 u32 object_count;
1216};
1217
edc3d884 1218struct drm_i915_error_state_buf {
0a4cd7c8 1219 struct drm_i915_private *i915;
edc3d884
MK
1220 unsigned bytes;
1221 unsigned size;
1222 int err;
1223 u8 *buf;
1224 loff_t start;
1225 loff_t pos;
1226};
1227
fc16b48b
MK
1228struct i915_error_state_file_priv {
1229 struct drm_device *dev;
1230 struct drm_i915_error_state *error;
1231};
1232
99584db3
DV
1233struct i915_gpu_error {
1234 /* For hangcheck timer */
1235#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1236#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
be62acb4
MK
1237 /* Hang gpu twice in this window and your context gets banned */
1238#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1239
737b1506
CW
1240 struct workqueue_struct *hangcheck_wq;
1241 struct delayed_work hangcheck_work;
99584db3
DV
1242
1243 /* For reset and error_state handling. */
1244 spinlock_t lock;
1245 /* Protected by the above dev->gpu_error.lock. */
1246 struct drm_i915_error_state *first_error;
094f9a54
CW
1247
1248 unsigned long missed_irq_rings;
1249
1f83fee0 1250 /**
2ac0f450 1251 * State variable controlling the reset flow and count
1f83fee0 1252 *
2ac0f450
MK
1253 * This is a counter which gets incremented when reset is triggered,
1254 * and again when reset has been handled. So odd values (lowest bit set)
1255 * means that reset is in progress and even values that
1256 * (reset_counter >> 1):th reset was successfully completed.
1257 *
1258 * If reset is not completed succesfully, the I915_WEDGE bit is
1259 * set meaning that hardware is terminally sour and there is no
1260 * recovery. All waiters on the reset_queue will be woken when
1261 * that happens.
1262 *
1263 * This counter is used by the wait_seqno code to notice that reset
1264 * event happened and it needs to restart the entire ioctl (since most
1265 * likely the seqno it waited for won't ever signal anytime soon).
f69061be
DV
1266 *
1267 * This is important for lock-free wait paths, where no contended lock
1268 * naturally enforces the correct ordering between the bail-out of the
1269 * waiter and the gpu reset work code.
1f83fee0
DV
1270 */
1271 atomic_t reset_counter;
1272
1f83fee0 1273#define I915_RESET_IN_PROGRESS_FLAG 1
2ac0f450 1274#define I915_WEDGED (1 << 31)
1f83fee0
DV
1275
1276 /**
1277 * Waitqueue to signal when the reset has completed. Used by clients
1278 * that wait for dev_priv->mm.wedged to settle.
1279 */
1280 wait_queue_head_t reset_queue;
33196ded 1281
88b4aa87
MK
1282 /* Userspace knobs for gpu hang simulation;
1283 * combines both a ring mask, and extra flags
1284 */
1285 u32 stop_rings;
1286#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1287#define I915_STOP_RING_ALLOW_WARN (1 << 30)
094f9a54
CW
1288
1289 /* For missed irq/seqno simulation. */
1290 unsigned int test_irq_rings;
6689c167
MA
1291
1292 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1293 bool reload_in_reset;
99584db3
DV
1294};
1295
b8efb17b
ZR
1296enum modeset_restore {
1297 MODESET_ON_LID_OPEN,
1298 MODESET_DONE,
1299 MODESET_SUSPENDED,
1300};
1301
6acab15a 1302struct ddi_vbt_port_info {
ce4dd49e
DL
1303 /*
1304 * This is an index in the HDMI/DVI DDI buffer translation table.
1305 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1306 * populate this field.
1307 */
1308#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
6acab15a 1309 uint8_t hdmi_level_shift;
311a2094
PZ
1310
1311 uint8_t supports_dvi:1;
1312 uint8_t supports_hdmi:1;
1313 uint8_t supports_dp:1;
6acab15a
PZ
1314};
1315
bfd7ebda
RV
1316enum psr_lines_to_wait {
1317 PSR_0_LINES_TO_WAIT = 0,
1318 PSR_1_LINE_TO_WAIT,
1319 PSR_4_LINES_TO_WAIT,
1320 PSR_8_LINES_TO_WAIT
83a7280e
PB
1321};
1322
41aa3448
RV
1323struct intel_vbt_data {
1324 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1325 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1326
1327 /* Feature bits */
1328 unsigned int int_tv_support:1;
1329 unsigned int lvds_dither:1;
1330 unsigned int lvds_vbt:1;
1331 unsigned int int_crt_support:1;
1332 unsigned int lvds_use_ssc:1;
1333 unsigned int display_clock_mode:1;
1334 unsigned int fdi_rx_polarity_inverted:1;
3e6bd011 1335 unsigned int has_mipi:1;
41aa3448
RV
1336 int lvds_ssc_freq;
1337 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1338
83a7280e
PB
1339 enum drrs_support_type drrs_type;
1340
41aa3448
RV
1341 /* eDP */
1342 int edp_rate;
1343 int edp_lanes;
1344 int edp_preemphasis;
1345 int edp_vswing;
1346 bool edp_initialized;
1347 bool edp_support;
1348 int edp_bpp;
9a57f5bb 1349 bool edp_low_vswing;
41aa3448
RV
1350 struct edp_power_seq edp_pps;
1351
bfd7ebda
RV
1352 struct {
1353 bool full_link;
1354 bool require_aux_wakeup;
1355 int idle_frames;
1356 enum psr_lines_to_wait lines_to_wait;
1357 int tp1_wakeup_time;
1358 int tp2_tp3_wakeup_time;
1359 } psr;
1360
f00076d2
JN
1361 struct {
1362 u16 pwm_freq_hz;
39fbc9c8 1363 bool present;
f00076d2 1364 bool active_low_pwm;
1de6068e 1365 u8 min_brightness; /* min_brightness/255 of max */
f00076d2
JN
1366 } backlight;
1367
d17c5443
SK
1368 /* MIPI DSI */
1369 struct {
3e6bd011 1370 u16 port;
d17c5443 1371 u16 panel_id;
d3b542fc
SK
1372 struct mipi_config *config;
1373 struct mipi_pps_data *pps;
1374 u8 seq_version;
1375 u32 size;
1376 u8 *data;
1377 u8 *sequence[MIPI_SEQ_MAX];
d17c5443
SK
1378 } dsi;
1379
41aa3448
RV
1380 int crt_ddc_pin;
1381
1382 int child_dev_num;
768f69c9 1383 union child_device_config *child_dev;
6acab15a
PZ
1384
1385 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
41aa3448
RV
1386};
1387
77c122bc
VS
1388enum intel_ddb_partitioning {
1389 INTEL_DDB_PART_1_2,
1390 INTEL_DDB_PART_5_6, /* IVB+ */
1391};
1392
1fd527cc
VS
1393struct intel_wm_level {
1394 bool enable;
1395 uint32_t pri_val;
1396 uint32_t spr_val;
1397 uint32_t cur_val;
1398 uint32_t fbc_val;
1399};
1400
820c1980 1401struct ilk_wm_values {
609cedef
VS
1402 uint32_t wm_pipe[3];
1403 uint32_t wm_lp[3];
1404 uint32_t wm_lp_spr[3];
1405 uint32_t wm_linetime[3];
1406 bool enable_fbc_wm;
1407 enum intel_ddb_partitioning partitioning;
1408};
1409
0018fda1
VS
1410struct vlv_wm_values {
1411 struct {
1412 uint8_t cursor;
1413 uint8_t sprite[2];
1414 uint8_t primary;
1415 } ddl[3];
1416};
1417
c193924e 1418struct skl_ddb_entry {
16160e3d 1419 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
c193924e
DL
1420};
1421
1422static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1423{
16160e3d 1424 return entry->end - entry->start;
c193924e
DL
1425}
1426
08db6652
DL
1427static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1428 const struct skl_ddb_entry *e2)
1429{
1430 if (e1->start == e2->start && e1->end == e2->end)
1431 return true;
1432
1433 return false;
1434}
1435
c193924e 1436struct skl_ddb_allocation {
34bb56af 1437 struct skl_ddb_entry pipe[I915_MAX_PIPES];
c193924e
DL
1438 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1439 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1440};
1441
2ac96d2a
PB
1442struct skl_wm_values {
1443 bool dirty[I915_MAX_PIPES];
c193924e 1444 struct skl_ddb_allocation ddb;
2ac96d2a
PB
1445 uint32_t wm_linetime[I915_MAX_PIPES];
1446 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1447 uint32_t cursor[I915_MAX_PIPES][8];
1448 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1449 uint32_t cursor_trans[I915_MAX_PIPES];
1450};
1451
1452struct skl_wm_level {
1453 bool plane_en[I915_MAX_PLANES];
b99f58da 1454 bool cursor_en;
2ac96d2a
PB
1455 uint16_t plane_res_b[I915_MAX_PLANES];
1456 uint8_t plane_res_l[I915_MAX_PLANES];
2ac96d2a
PB
1457 uint16_t cursor_res_b;
1458 uint8_t cursor_res_l;
1459};
1460
c67a470b 1461/*
765dab67
PZ
1462 * This struct helps tracking the state needed for runtime PM, which puts the
1463 * device in PCI D3 state. Notice that when this happens, nothing on the
1464 * graphics device works, even register access, so we don't get interrupts nor
1465 * anything else.
c67a470b 1466 *
765dab67
PZ
1467 * Every piece of our code that needs to actually touch the hardware needs to
1468 * either call intel_runtime_pm_get or call intel_display_power_get with the
1469 * appropriate power domain.
a8a8bd54 1470 *
765dab67
PZ
1471 * Our driver uses the autosuspend delay feature, which means we'll only really
1472 * suspend if we stay with zero refcount for a certain amount of time. The
f458ebbc 1473 * default value is currently very conservative (see intel_runtime_pm_enable), but
765dab67 1474 * it can be changed with the standard runtime PM files from sysfs.
c67a470b
PZ
1475 *
1476 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1477 * goes back to false exactly before we reenable the IRQs. We use this variable
1478 * to check if someone is trying to enable/disable IRQs while they're supposed
1479 * to be disabled. This shouldn't happen and we'll print some error messages in
730488b2 1480 * case it happens.
c67a470b 1481 *
765dab67 1482 * For more, read the Documentation/power/runtime_pm.txt.
c67a470b 1483 */
5d584b2e
PZ
1484struct i915_runtime_pm {
1485 bool suspended;
2aeb7d3a 1486 bool irqs_enabled;
c67a470b
PZ
1487};
1488
926321d5
DV
1489enum intel_pipe_crc_source {
1490 INTEL_PIPE_CRC_SOURCE_NONE,
1491 INTEL_PIPE_CRC_SOURCE_PLANE1,
1492 INTEL_PIPE_CRC_SOURCE_PLANE2,
1493 INTEL_PIPE_CRC_SOURCE_PF,
5b3a856b 1494 INTEL_PIPE_CRC_SOURCE_PIPE,
3d099a05
DV
1495 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1496 INTEL_PIPE_CRC_SOURCE_TV,
1497 INTEL_PIPE_CRC_SOURCE_DP_B,
1498 INTEL_PIPE_CRC_SOURCE_DP_C,
1499 INTEL_PIPE_CRC_SOURCE_DP_D,
46a19188 1500 INTEL_PIPE_CRC_SOURCE_AUTO,
926321d5
DV
1501 INTEL_PIPE_CRC_SOURCE_MAX,
1502};
1503
8bf1e9f1 1504struct intel_pipe_crc_entry {
ac2300d4 1505 uint32_t frame;
8bf1e9f1
SH
1506 uint32_t crc[5];
1507};
1508
b2c88f5b 1509#define INTEL_PIPE_CRC_ENTRIES_NR 128
8bf1e9f1 1510struct intel_pipe_crc {
d538bbdf
DL
1511 spinlock_t lock;
1512 bool opened; /* exclusive access to the result file */
e5f75aca 1513 struct intel_pipe_crc_entry *entries;
926321d5 1514 enum intel_pipe_crc_source source;
d538bbdf 1515 int head, tail;
07144428 1516 wait_queue_head_t wq;
8bf1e9f1
SH
1517};
1518
f99d7069
DV
1519struct i915_frontbuffer_tracking {
1520 struct mutex lock;
1521
1522 /*
1523 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1524 * scheduled flips.
1525 */
1526 unsigned busy_bits;
1527 unsigned flip_bits;
1528};
1529
7225342a
MK
1530struct i915_wa_reg {
1531 u32 addr;
1532 u32 value;
1533 /* bitmask representing WA bits */
1534 u32 mask;
1535};
1536
1537#define I915_MAX_WA_REGS 16
1538
1539struct i915_workarounds {
1540 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1541 u32 count;
1542};
1543
cf9d2890
YZ
1544struct i915_virtual_gpu {
1545 bool active;
1546};
1547
77fec556 1548struct drm_i915_private {
f4c956ad 1549 struct drm_device *dev;
42dcedd4 1550 struct kmem_cache *slab;
f4c956ad 1551
5c969aa7 1552 const struct intel_device_info info;
f4c956ad
DV
1553
1554 int relative_constants_mode;
1555
1556 void __iomem *regs;
1557
907b28c5 1558 struct intel_uncore uncore;
f4c956ad 1559
cf9d2890
YZ
1560 struct i915_virtual_gpu vgpu;
1561
f4c956ad
DV
1562 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1563
28c70f16 1564
f4c956ad
DV
1565 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1566 * controller on different i2c buses. */
1567 struct mutex gmbus_mutex;
1568
1569 /**
1570 * Base address of the gmbus and gpio block.
1571 */
1572 uint32_t gpio_mmio_base;
1573
b6fdd0f2
SS
1574 /* MMIO base address for MIPI regs */
1575 uint32_t mipi_mmio_base;
1576
28c70f16
DV
1577 wait_queue_head_t gmbus_wait_queue;
1578
f4c956ad 1579 struct pci_dev *bridge_dev;
a4872ba6 1580 struct intel_engine_cs ring[I915_NUM_RINGS];
3e78998a 1581 struct drm_i915_gem_object *semaphore_obj;
f72b3435 1582 uint32_t last_seqno, next_seqno;
f4c956ad 1583
ba8286fa 1584 struct drm_dma_handle *status_page_dmah;
f4c956ad
DV
1585 struct resource mch_res;
1586
f4c956ad
DV
1587 /* protects the irq masks */
1588 spinlock_t irq_lock;
1589
84c33a64
SG
1590 /* protects the mmio flip data */
1591 spinlock_t mmio_flip_lock;
1592
f8b79e58
ID
1593 bool display_irqs_enabled;
1594
9ee32fea
DV
1595 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1596 struct pm_qos_request pm_qos;
1597
f4c956ad 1598 /* DPIO indirect register protection */
09153000 1599 struct mutex dpio_lock;
f4c956ad
DV
1600
1601 /** Cached value of IMR to avoid reads in updating the bitfield */
abd58f01
BW
1602 union {
1603 u32 irq_mask;
1604 u32 de_irq_mask[I915_MAX_PIPES];
1605 };
f4c956ad 1606 u32 gt_irq_mask;
605cd25b 1607 u32 pm_irq_mask;
a6706b45 1608 u32 pm_rps_events;
91d181dd 1609 u32 pipestat_irq_mask[I915_MAX_PIPES];
f4c956ad 1610
f4c956ad 1611 struct work_struct hotplug_work;
b543fb04
EE
1612 struct {
1613 unsigned long hpd_last_jiffies;
1614 int hpd_cnt;
1615 enum {
1616 HPD_ENABLED = 0,
1617 HPD_DISABLED = 1,
1618 HPD_MARK_DISABLED = 2
1619 } hpd_mark;
1620 } hpd_stats[HPD_NUM_PINS];
142e2398 1621 u32 hpd_event_bits;
6323751d 1622 struct delayed_work hotplug_reenable_work;
f4c956ad 1623
5c3fe8b0 1624 struct i915_fbc fbc;
439d7ac0 1625 struct i915_drrs drrs;
f4c956ad 1626 struct intel_opregion opregion;
41aa3448 1627 struct intel_vbt_data vbt;
f4c956ad 1628
d9ceb816
JB
1629 bool preserve_bios_swizzle;
1630
f4c956ad
DV
1631 /* overlay */
1632 struct intel_overlay *overlay;
f4c956ad 1633
58c68779 1634 /* backlight registers and fields in struct intel_panel */
07f11d49 1635 struct mutex backlight_lock;
31ad8ec6 1636
f4c956ad 1637 /* LVDS info */
f4c956ad
DV
1638 bool no_aux_handshake;
1639
e39b999a
VS
1640 /* protects panel power sequencer state */
1641 struct mutex pps_mutex;
1642
f4c956ad
DV
1643 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1644 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1645 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1646
1647 unsigned int fsb_freq, mem_freq, is_ddr3;
d60c4473 1648 unsigned int vlv_cdclk_freq;
6bcda4f0 1649 unsigned int hpll_freq;
f4c956ad 1650
645416f5
DV
1651 /**
1652 * wq - Driver workqueue for GEM.
1653 *
1654 * NOTE: Work items scheduled here are not allowed to grab any modeset
1655 * locks, for otherwise the flushing done in the pageflip code will
1656 * result in deadlocks.
1657 */
f4c956ad
DV
1658 struct workqueue_struct *wq;
1659
1660 /* Display functions */
1661 struct drm_i915_display_funcs display;
1662
1663 /* PCH chipset type */
1664 enum intel_pch pch_type;
17a303ec 1665 unsigned short pch_id;
f4c956ad
DV
1666
1667 unsigned long quirks;
1668
b8efb17b
ZR
1669 enum modeset_restore modeset_restore;
1670 struct mutex modeset_restore_lock;
673a394b 1671
a7bbbd63 1672 struct list_head vm_list; /* Global list of all address spaces */
0260c420 1673 struct i915_gtt gtt; /* VM representing the global address space */
5d4545ae 1674
4b5aed62 1675 struct i915_gem_mm mm;
ad46cb53
CW
1676 DECLARE_HASHTABLE(mm_structs, 7);
1677 struct mutex mm_lock;
8781342d 1678
8781342d
DV
1679 /* Kernel Modesetting */
1680
9b9d172d 1681 struct sdvo_device_mapping sdvo_mappings[2];
652c393a 1682
76c4ac04
DL
1683 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1684 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
6b95a207
KH
1685 wait_queue_head_t pending_flip_queue;
1686
c4597872
DV
1687#ifdef CONFIG_DEBUG_FS
1688 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1689#endif
1690
e72f9fbf
DV
1691 int num_shared_dpll;
1692 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
e4607fcf 1693 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
ee7b9f93 1694
7225342a 1695 struct i915_workarounds workarounds;
888b5995 1696
652c393a
JB
1697 /* Reclocking support */
1698 bool render_reclock_avail;
1699 bool lvds_downclock_avail;
18f9ed12
ZY
1700 /* indicates the reduced downclock for LVDS*/
1701 int lvds_downclock;
f99d7069
DV
1702
1703 struct i915_frontbuffer_tracking fb_tracking;
1704
652c393a 1705 u16 orig_clock;
f97108d1 1706
c4804411 1707 bool mchbar_need_disable;
f97108d1 1708
a4da4fa4
DV
1709 struct intel_l3_parity l3_parity;
1710
59124506
BW
1711 /* Cannot be determined by PCIID. You must always read a register. */
1712 size_t ellc_size;
1713
c6a828d3 1714 /* gen6+ rps state */
c85aa885 1715 struct intel_gen6_power_mgmt rps;
c6a828d3 1716
20e4d407
DV
1717 /* ilk-only ips/rps state. Everything in here is protected by the global
1718 * mchdev_lock in intel_pm.c */
c85aa885 1719 struct intel_ilk_power_mgmt ips;
b5e50c3f 1720
83c00f55 1721 struct i915_power_domains power_domains;
a38911a3 1722
a031d709 1723 struct i915_psr psr;
3f51e471 1724
99584db3 1725 struct i915_gpu_error gpu_error;
ae681d96 1726
c9cddffc
JB
1727 struct drm_i915_gem_object *vlv_pctx;
1728
4520f53a 1729#ifdef CONFIG_DRM_I915_FBDEV
8be48d92
DA
1730 /* list of fbdev register on this device */
1731 struct intel_fbdev *fbdev;
82e3b8c1 1732 struct work_struct fbdev_suspend_work;
4520f53a 1733#endif
e953fd7b
CW
1734
1735 struct drm_property *broadcast_rgb_property;
3f43c48d 1736 struct drm_property *force_audio_property;
e3689190 1737
58fddc28
ID
1738 /* hda/i915 audio component */
1739 bool audio_component_registered;
1740
254f965c 1741 uint32_t hw_context_size;
a33afea5 1742 struct list_head context_list;
f4c956ad 1743
3e68320e 1744 u32 fdi_rx_config;
68d18ad7 1745
842f1c8b 1746 u32 suspend_count;
f4c956ad 1747 struct i915_suspend_saved_registers regfile;
ddeea5b0 1748 struct vlv_s0ix_state vlv_s0ix_state;
231f42a4 1749
53615a5e
VS
1750 struct {
1751 /*
1752 * Raw watermark latency values:
1753 * in 0.1us units for WM0,
1754 * in 0.5us units for WM1+.
1755 */
1756 /* primary */
1757 uint16_t pri_latency[5];
1758 /* sprite */
1759 uint16_t spr_latency[5];
1760 /* cursor */
1761 uint16_t cur_latency[5];
2af30a5c
PB
1762 /*
1763 * Raw watermark memory latency values
1764 * for SKL for all 8 levels
1765 * in 1us units.
1766 */
1767 uint16_t skl_latency[8];
609cedef 1768
2d41c0b5
PB
1769 /*
1770 * The skl_wm_values structure is a bit too big for stack
1771 * allocation, so we keep the staging struct where we store
1772 * intermediate results here instead.
1773 */
1774 struct skl_wm_values skl_results;
1775
609cedef 1776 /* current hardware state */
2d41c0b5
PB
1777 union {
1778 struct ilk_wm_values hw;
1779 struct skl_wm_values skl_hw;
0018fda1 1780 struct vlv_wm_values vlv;
2d41c0b5 1781 };
53615a5e
VS
1782 } wm;
1783
8a187455
PZ
1784 struct i915_runtime_pm pm;
1785
13cf5504
DA
1786 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1787 u32 long_hpd_port_mask;
1788 u32 short_hpd_port_mask;
1789 struct work_struct dig_port_work;
1790
0e32b39c
DA
1791 /*
1792 * if we get a HPD irq from DP and a HPD irq from non-DP
1793 * the non-DP HPD could block the workqueue on a mode config
1794 * mutex getting, that userspace may have taken. However
1795 * userspace is waiting on the DP workqueue to run which is
1796 * blocked behind the non-DP one.
1797 */
1798 struct workqueue_struct *dp_wq;
1799
a83014d3
OM
1800 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1801 struct {
1802 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1803 struct intel_engine_cs *ring,
1804 struct intel_context *ctx,
1805 struct drm_i915_gem_execbuffer2 *args,
1806 struct list_head *vmas,
1807 struct drm_i915_gem_object *batch_obj,
1808 u64 exec_start, u32 flags);
1809 int (*init_rings)(struct drm_device *dev);
1810 void (*cleanup_ring)(struct intel_engine_cs *ring);
1811 void (*stop_ring)(struct intel_engine_cs *ring);
1812 } gt;
1813
67e2937b
JH
1814 uint32_t request_uniq;
1815
bdf1e7e3
DV
1816 /*
1817 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1818 * will be rejected. Instead look for a better place.
1819 */
77fec556 1820};
1da177e4 1821
2c1792a1
CW
1822static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1823{
1824 return dev->dev_private;
1825}
1826
888d0d42
ID
1827static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1828{
1829 return to_i915(dev_get_drvdata(dev));
1830}
1831
b4519513
CW
1832/* Iterate over initialised rings */
1833#define for_each_ring(ring__, dev_priv__, i__) \
1834 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1835 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1836
b1d7e4b4
WF
1837enum hdmi_force_audio {
1838 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1839 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1840 HDMI_AUDIO_AUTO, /* trust EDID */
1841 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1842};
1843
190d6cd5 1844#define I915_GTT_OFFSET_NONE ((u32)-1)
ed2f3452 1845
37e680a1
CW
1846struct drm_i915_gem_object_ops {
1847 /* Interface between the GEM object and its backing storage.
1848 * get_pages() is called once prior to the use of the associated set
1849 * of pages before to binding them into the GTT, and put_pages() is
1850 * called after we no longer need them. As we expect there to be
1851 * associated cost with migrating pages between the backing storage
1852 * and making them available for the GPU (e.g. clflush), we may hold
1853 * onto the pages after they are no longer referenced by the GPU
1854 * in case they may be used again shortly (for example migrating the
1855 * pages to a different memory domain within the GTT). put_pages()
1856 * will therefore most likely be called when the object itself is
1857 * being released or under memory pressure (where we attempt to
1858 * reap pages for the shrinker).
1859 */
1860 int (*get_pages)(struct drm_i915_gem_object *);
1861 void (*put_pages)(struct drm_i915_gem_object *);
5cc9ed4b
CW
1862 int (*dmabuf_export)(struct drm_i915_gem_object *);
1863 void (*release)(struct drm_i915_gem_object *);
37e680a1
CW
1864};
1865
a071fa00
DV
1866/*
1867 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1868 * considered to be the frontbuffer for the given plane interface-vise. This
1869 * doesn't mean that the hw necessarily already scans it out, but that any
1870 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1871 *
1872 * We have one bit per pipe and per scanout plane type.
1873 */
1874#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1875#define INTEL_FRONTBUFFER_BITS \
1876 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1877#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1878 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1879#define INTEL_FRONTBUFFER_CURSOR(pipe) \
1880 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1881#define INTEL_FRONTBUFFER_SPRITE(pipe) \
1882 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1883#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1884 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
cc36513c
DV
1885#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1886 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
a071fa00 1887
673a394b 1888struct drm_i915_gem_object {
c397b908 1889 struct drm_gem_object base;
673a394b 1890
37e680a1
CW
1891 const struct drm_i915_gem_object_ops *ops;
1892
2f633156
BW
1893 /** List of VMAs backed by this object */
1894 struct list_head vma_list;
1895
c1ad11fc
CW
1896 /** Stolen memory for this object, instead of being backed by shmem. */
1897 struct drm_mm_node *stolen;
35c20a60 1898 struct list_head global_list;
673a394b 1899
69dc4987 1900 struct list_head ring_list;
b25cb2f8
BW
1901 /** Used in execbuf to temporarily hold a ref */
1902 struct list_head obj_exec_link;
673a394b 1903
493018dc
BV
1904 struct list_head batch_pool_list;
1905
673a394b 1906 /**
65ce3027
CW
1907 * This is set if the object is on the active lists (has pending
1908 * rendering and so a non-zero seqno), and is not set if it i s on
1909 * inactive (ready to be unbound) list.
673a394b 1910 */
0206e353 1911 unsigned int active:1;
673a394b
EA
1912
1913 /**
1914 * This is set if the object has been written to since last bound
1915 * to the GTT
1916 */
0206e353 1917 unsigned int dirty:1;
778c3544
DV
1918
1919 /**
1920 * Fence register bits (if any) for this object. Will be set
1921 * as needed when mapped into the GTT.
1922 * Protected by dev->struct_mutex.
778c3544 1923 */
4b9de737 1924 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
778c3544 1925
778c3544
DV
1926 /**
1927 * Advice: are the backing pages purgeable?
1928 */
0206e353 1929 unsigned int madv:2;
778c3544 1930
778c3544
DV
1931 /**
1932 * Current tiling mode for the object.
1933 */
0206e353 1934 unsigned int tiling_mode:2;
5d82e3e6
CW
1935 /**
1936 * Whether the tiling parameters for the currently associated fence
1937 * register have changed. Note that for the purposes of tracking
1938 * tiling changes we also treat the unfenced register, the register
1939 * slot that the object occupies whilst it executes a fenced
1940 * command (such as BLT on gen2/3), as a "fence".
1941 */
1942 unsigned int fence_dirty:1;
778c3544 1943
75e9e915
DV
1944 /**
1945 * Is the object at the current location in the gtt mappable and
1946 * fenceable? Used to avoid costly recalculations.
1947 */
0206e353 1948 unsigned int map_and_fenceable:1;
75e9e915 1949
fb7d516a
DV
1950 /**
1951 * Whether the current gtt mapping needs to be mappable (and isn't just
1952 * mappable by accident). Track pin and fault separate for a more
1953 * accurate mappable working set.
1954 */
0206e353
AJ
1955 unsigned int fault_mappable:1;
1956 unsigned int pin_mappable:1;
cc98b413 1957 unsigned int pin_display:1;
fb7d516a 1958
24f3a8cf
AG
1959 /*
1960 * Is the object to be mapped as read-only to the GPU
1961 * Only honoured if hardware has relevant pte bit
1962 */
1963 unsigned long gt_ro:1;
651d794f 1964 unsigned int cache_level:3;
0f71979a 1965 unsigned int cache_dirty:1;
93dfb40c 1966
9da3da66 1967 unsigned int has_dma_mapping:1;
7bddb01f 1968
a071fa00
DV
1969 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1970
9da3da66 1971 struct sg_table *pages;
a5570178 1972 int pages_pin_count;
673a394b 1973
1286ff73 1974 /* prime dma-buf support */
9a70cc2a
DA
1975 void *dma_buf_vmapping;
1976 int vmapping_count;
1977
1c293ea3 1978 /** Breadcrumb of last rendering to the buffer. */
97b2a6a1
JH
1979 struct drm_i915_gem_request *last_read_req;
1980 struct drm_i915_gem_request *last_write_req;
caea7476 1981 /** Breadcrumb of last fenced GPU access to the buffer. */
97b2a6a1 1982 struct drm_i915_gem_request *last_fenced_req;
673a394b 1983
778c3544 1984 /** Current tiling stride for the object, if it's tiled. */
de151cf6 1985 uint32_t stride;
673a394b 1986
80075d49
DV
1987 /** References from framebuffers, locks out tiling changes. */
1988 unsigned long framebuffer_references;
1989
280b713b 1990 /** Record of address bit 17 of each page at last unbind. */
d312ec25 1991 unsigned long *bit_17;
280b713b 1992
5cc9ed4b 1993 union {
6a2c4232
CW
1994 /** for phy allocated objects */
1995 struct drm_dma_handle *phys_handle;
1996
5cc9ed4b
CW
1997 struct i915_gem_userptr {
1998 uintptr_t ptr;
1999 unsigned read_only :1;
2000 unsigned workers :4;
2001#define I915_GEM_USERPTR_MAX_WORKERS 15
2002
ad46cb53
CW
2003 struct i915_mm_struct *mm;
2004 struct i915_mmu_object *mmu_object;
5cc9ed4b
CW
2005 struct work_struct *work;
2006 } userptr;
2007 };
2008};
62b8b215 2009#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
23010e43 2010
a071fa00
DV
2011void i915_gem_track_fb(struct drm_i915_gem_object *old,
2012 struct drm_i915_gem_object *new,
2013 unsigned frontbuffer_bits);
2014
673a394b
EA
2015/**
2016 * Request queue structure.
2017 *
2018 * The request queue allows us to note sequence numbers that have been emitted
2019 * and may be associated with active buffers to be retired.
2020 *
97b2a6a1
JH
2021 * By keeping this list, we can avoid having to do questionable sequence
2022 * number comparisons on buffer last_read|write_seqno. It also allows an
2023 * emission time to be associated with the request for tracking how far ahead
2024 * of the GPU the submission is.
b3a38998
NH
2025 *
2026 * The requests are reference counted, so upon creation they should have an
2027 * initial reference taken using kref_init
673a394b
EA
2028 */
2029struct drm_i915_gem_request {
abfe262a
JH
2030 struct kref ref;
2031
852835f3 2032 /** On Which ring this request was generated */
a4872ba6 2033 struct intel_engine_cs *ring;
852835f3 2034
673a394b
EA
2035 /** GEM sequence number associated with this request. */
2036 uint32_t seqno;
2037
7d736f4f
MK
2038 /** Position in the ringbuffer of the start of the request */
2039 u32 head;
2040
72f95afa
NH
2041 /**
2042 * Position in the ringbuffer of the start of the postfix.
2043 * This is required to calculate the maximum available ringbuffer
2044 * space without overwriting the postfix.
2045 */
2046 u32 postfix;
2047
2048 /** Position in the ringbuffer of the end of the whole request */
a71d8d94
CW
2049 u32 tail;
2050
b3a38998 2051 /**
a8c6ecb3 2052 * Context and ring buffer related to this request
b3a38998
NH
2053 * Contexts are refcounted, so when this request is associated with a
2054 * context, we must increment the context's refcount, to guarantee that
2055 * it persists while any request is linked to it. Requests themselves
2056 * are also refcounted, so the request will only be freed when the last
2057 * reference to it is dismissed, and the code in
2058 * i915_gem_request_free() will then decrement the refcount on the
2059 * context.
2060 */
273497e5 2061 struct intel_context *ctx;
98e1bd4a 2062 struct intel_ringbuffer *ringbuf;
0e50e96b 2063
7d736f4f
MK
2064 /** Batch buffer related to this request if any */
2065 struct drm_i915_gem_object *batch_obj;
2066
673a394b
EA
2067 /** Time at which this request was emitted, in jiffies. */
2068 unsigned long emitted_jiffies;
2069
b962442e 2070 /** global list entry for this request */
673a394b 2071 struct list_head list;
b962442e 2072
f787a5f5 2073 struct drm_i915_file_private *file_priv;
b962442e
EA
2074 /** file_priv list entry for this request */
2075 struct list_head client_list;
67e2937b 2076
071c92de
MK
2077 /** process identifier submitting this request */
2078 struct pid *pid;
2079
67e2937b 2080 uint32_t uniq;
6d3d8274
NH
2081
2082 /**
2083 * The ELSP only accepts two elements at a time, so we queue
2084 * context/tail pairs on a given queue (ring->execlist_queue) until the
2085 * hardware is available. The queue serves a double purpose: we also use
2086 * it to keep track of the up to 2 contexts currently in the hardware
2087 * (usually one in execution and the other queued up by the GPU): We
2088 * only remove elements from the head of the queue when the hardware
2089 * informs us that an element has been completed.
2090 *
2091 * All accesses to the queue are mediated by a spinlock
2092 * (ring->execlist_lock).
2093 */
2094
2095 /** Execlist link in the submission queue.*/
2096 struct list_head execlist_link;
2097
2098 /** Execlists no. of times this request has been sent to the ELSP */
2099 int elsp_submitted;
2100
673a394b
EA
2101};
2102
abfe262a
JH
2103void i915_gem_request_free(struct kref *req_ref);
2104
b793a00a
JH
2105static inline uint32_t
2106i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2107{
2108 return req ? req->seqno : 0;
2109}
2110
2111static inline struct intel_engine_cs *
2112i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2113{
2114 return req ? req->ring : NULL;
2115}
2116
abfe262a
JH
2117static inline void
2118i915_gem_request_reference(struct drm_i915_gem_request *req)
2119{
2120 kref_get(&req->ref);
2121}
2122
2123static inline void
2124i915_gem_request_unreference(struct drm_i915_gem_request *req)
2125{
f245860e 2126 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
abfe262a
JH
2127 kref_put(&req->ref, i915_gem_request_free);
2128}
2129
2130static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2131 struct drm_i915_gem_request *src)
2132{
2133 if (src)
2134 i915_gem_request_reference(src);
2135
2136 if (*pdst)
2137 i915_gem_request_unreference(*pdst);
2138
2139 *pdst = src;
2140}
2141
1b5a433a
JH
2142/*
2143 * XXX: i915_gem_request_completed should be here but currently needs the
2144 * definition of i915_seqno_passed() which is below. It will be moved in
2145 * a later patch when the call to i915_seqno_passed() is obsoleted...
2146 */
2147
673a394b 2148struct drm_i915_file_private {
b29c19b6 2149 struct drm_i915_private *dev_priv;
ab0e7ff9 2150 struct drm_file *file;
b29c19b6 2151
673a394b 2152 struct {
99057c81 2153 spinlock_t lock;
b962442e 2154 struct list_head request_list;
b29c19b6 2155 struct delayed_work idle_work;
673a394b 2156 } mm;
40521054 2157 struct idr context_idr;
e59ec13d 2158
b29c19b6 2159 atomic_t rps_wait_boost;
a4872ba6 2160 struct intel_engine_cs *bsd_ring;
673a394b
EA
2161};
2162
351e3db2
BV
2163/*
2164 * A command that requires special handling by the command parser.
2165 */
2166struct drm_i915_cmd_descriptor {
2167 /*
2168 * Flags describing how the command parser processes the command.
2169 *
2170 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2171 * a length mask if not set
2172 * CMD_DESC_SKIP: The command is allowed but does not follow the
2173 * standard length encoding for the opcode range in
2174 * which it falls
2175 * CMD_DESC_REJECT: The command is never allowed
2176 * CMD_DESC_REGISTER: The command should be checked against the
2177 * register whitelist for the appropriate ring
2178 * CMD_DESC_MASTER: The command is allowed if the submitting process
2179 * is the DRM master
2180 */
2181 u32 flags;
2182#define CMD_DESC_FIXED (1<<0)
2183#define CMD_DESC_SKIP (1<<1)
2184#define CMD_DESC_REJECT (1<<2)
2185#define CMD_DESC_REGISTER (1<<3)
2186#define CMD_DESC_BITMASK (1<<4)
2187#define CMD_DESC_MASTER (1<<5)
2188
2189 /*
2190 * The command's unique identification bits and the bitmask to get them.
2191 * This isn't strictly the opcode field as defined in the spec and may
2192 * also include type, subtype, and/or subop fields.
2193 */
2194 struct {
2195 u32 value;
2196 u32 mask;
2197 } cmd;
2198
2199 /*
2200 * The command's length. The command is either fixed length (i.e. does
2201 * not include a length field) or has a length field mask. The flag
2202 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2203 * a length mask. All command entries in a command table must include
2204 * length information.
2205 */
2206 union {
2207 u32 fixed;
2208 u32 mask;
2209 } length;
2210
2211 /*
2212 * Describes where to find a register address in the command to check
2213 * against the ring's register whitelist. Only valid if flags has the
2214 * CMD_DESC_REGISTER bit set.
2215 */
2216 struct {
2217 u32 offset;
2218 u32 mask;
2219 } reg;
2220
2221#define MAX_CMD_DESC_BITMASKS 3
2222 /*
2223 * Describes command checks where a particular dword is masked and
2224 * compared against an expected value. If the command does not match
2225 * the expected value, the parser rejects it. Only valid if flags has
2226 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2227 * are valid.
d4d48035
BV
2228 *
2229 * If the check specifies a non-zero condition_mask then the parser
2230 * only performs the check when the bits specified by condition_mask
2231 * are non-zero.
351e3db2
BV
2232 */
2233 struct {
2234 u32 offset;
2235 u32 mask;
2236 u32 expected;
d4d48035
BV
2237 u32 condition_offset;
2238 u32 condition_mask;
351e3db2
BV
2239 } bits[MAX_CMD_DESC_BITMASKS];
2240};
2241
2242/*
2243 * A table of commands requiring special handling by the command parser.
2244 *
2245 * Each ring has an array of tables. Each table consists of an array of command
2246 * descriptors, which must be sorted with command opcodes in ascending order.
2247 */
2248struct drm_i915_cmd_table {
2249 const struct drm_i915_cmd_descriptor *table;
2250 int count;
2251};
2252
dbbe9127 2253/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
7312e2dd
CW
2254#define __I915__(p) ({ \
2255 struct drm_i915_private *__p; \
2256 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2257 __p = (struct drm_i915_private *)p; \
2258 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2259 __p = to_i915((struct drm_device *)p); \
2260 else \
2261 BUILD_BUG(); \
2262 __p; \
2263})
dbbe9127 2264#define INTEL_INFO(p) (&__I915__(p)->info)
87f1f465 2265#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
e90a21d4 2266#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
cae5852d 2267
87f1f465
CW
2268#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2269#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
cae5852d 2270#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
87f1f465 2271#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
cae5852d 2272#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
87f1f465
CW
2273#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2274#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
cae5852d
ZN
2275#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2276#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2277#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
87f1f465 2278#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
cae5852d 2279#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
87f1f465
CW
2280#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2281#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
cae5852d
ZN
2282#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2283#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
87f1f465 2284#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
4b65177b 2285#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
87f1f465
CW
2286#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2287 INTEL_DEVID(dev) == 0x0152 || \
2288 INTEL_DEVID(dev) == 0x015a)
70a3eb7a 2289#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
6df4027b 2290#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
4cae9ae0 2291#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
8179f1f0 2292#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
7201c0b3 2293#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
cae5852d 2294#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
ed1c9e2c 2295#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
87f1f465 2296 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
5dd8c4c3 2297#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
6b96d705 2298 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
0dc6f20b 2299 (INTEL_DEVID(dev) & 0xf) == 0xb || \
87f1f465 2300 (INTEL_DEVID(dev) & 0xf) == 0xe))
a0fcbd95
RV
2301#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2302 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
5dd8c4c3 2303#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
87f1f465 2304 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
9435373e 2305#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
87f1f465 2306 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
9bbfd20a 2307/* ULX machines are also considered ULT. */
87f1f465
CW
2308#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2309 INTEL_DEVID(dev) == 0x0A1E)
b833d685 2310#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
cae5852d 2311
e90a21d4
HN
2312#define SKL_REVID_A0 (0x0)
2313#define SKL_REVID_B0 (0x1)
2314#define SKL_REVID_C0 (0x2)
2315#define SKL_REVID_D0 (0x3)
8bc0ccf6 2316#define SKL_REVID_E0 (0x4)
e90a21d4 2317
85436696
JB
2318/*
2319 * The genX designation typically refers to the render engine, so render
2320 * capability related checks should use IS_GEN, while display and other checks
2321 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2322 * chips, etc.).
2323 */
cae5852d
ZN
2324#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2325#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2326#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2327#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2328#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
85436696 2329#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
d2980845 2330#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
b71252dc 2331#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
cae5852d 2332
73ae478c
BW
2333#define RENDER_RING (1<<RCS)
2334#define BSD_RING (1<<VCS)
2335#define BLT_RING (1<<BCS)
2336#define VEBOX_RING (1<<VECS)
845f74a7 2337#define BSD2_RING (1<<VCS2)
63c42e56 2338#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
845f74a7 2339#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
63c42e56
BW
2340#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2341#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2342#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2343#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
f2fbc690 2344 __I915__(dev)->ellc_size)
cae5852d
ZN
2345#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2346
254f965c 2347#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
d7f621e5 2348#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
692ef70c
JB
2349#define USES_PPGTT(dev) (i915.enable_ppgtt)
2350#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
1d2a314c 2351
05394f39 2352#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
cae5852d
ZN
2353#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2354
b45305fc
DV
2355/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2356#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
4e6b788c
DV
2357/*
2358 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2359 * even when in MSI mode. This results in spurious interrupt warnings if the
2360 * legacy irq no. is shared with another device. The kernel then disables that
2361 * interrupt source and so prevents the other device from working properly.
2362 */
2363#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2364#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
b45305fc 2365
cae5852d
ZN
2366/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2367 * rows, which changed the alignment requirements and fence programming.
2368 */
2369#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2370 IS_I915GM(dev)))
2371#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2372#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2373#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
cae5852d
ZN
2374#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2375#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
cae5852d
ZN
2376
2377#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2378#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
3a77c4c4 2379#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
cae5852d 2380
dbf7786e 2381#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
f5adf94e 2382
dd93be58 2383#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
30568c45 2384#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
b32c6f48 2385#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
e3d99845
SJ
2386 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2387 IS_SKYLAKE(dev))
6157d3c8 2388#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
fd7f8cce 2389 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
58abf1da
RV
2390#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2391#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
affa9354 2392
17a303ec
PZ
2393#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2394#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2395#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2396#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2397#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2398#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
e7e7ea20
S
2399#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2400#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
17a303ec 2401
f2fbc690 2402#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
e7e7ea20 2403#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
eb877ebf 2404#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
cae5852d
ZN
2405#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2406#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
40c7ead9 2407#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
45e6e3a1 2408#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
cae5852d 2409
5fafe292
SJ
2410#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2411
040d2baa
BW
2412/* DPF == dynamic parity feature */
2413#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2414#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
e1ef7cc2 2415
c8735b0c
BW
2416#define GT_FREQUENCY_MULTIPLIER 50
2417
05394f39
CW
2418#include "i915_trace.h"
2419
baa70943 2420extern const struct drm_ioctl_desc i915_ioctls[];
b3a83639
DA
2421extern int i915_max_ioctl;
2422
fc49b3da
ID
2423extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2424extern int i915_resume_legacy(struct drm_device *dev);
7c1c2871 2425
d330a953
JN
2426/* i915_params.c */
2427struct i915_params {
2428 int modeset;
2429 int panel_ignore_lid;
2430 unsigned int powersave;
2431 int semaphores;
2432 unsigned int lvds_downclock;
2433 int lvds_channel_mode;
2434 int panel_use_ssc;
2435 int vbt_sdvo_panel_type;
2436 int enable_rc6;
2437 int enable_fbc;
d330a953 2438 int enable_ppgtt;
127f1003 2439 int enable_execlists;
d330a953
JN
2440 int enable_psr;
2441 unsigned int preliminary_hw_support;
2442 int disable_power_well;
2443 int enable_ips;
e5aa6541 2444 int invert_brightness;
351e3db2 2445 int enable_cmd_parser;
e5aa6541
DL
2446 /* leave bools at the end to not create holes */
2447 bool enable_hangcheck;
2448 bool fastboot;
d330a953
JN
2449 bool prefault_disable;
2450 bool reset;
a0bae57f 2451 bool disable_display;
7a10dfa6 2452 bool disable_vtd_wa;
84c33a64 2453 int use_mmio_flip;
48572edd 2454 int mmio_debug;
e2c719b7 2455 bool verbose_state_checks;
b2e7723b 2456 bool nuclear_pageflip;
d330a953
JN
2457};
2458extern struct i915_params i915 __read_mostly;
2459
1da177e4 2460 /* i915_dma.c */
22eae947 2461extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 2462extern int i915_driver_unload(struct drm_device *);
2885f6ac 2463extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
84b1fd10 2464extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac 2465extern void i915_driver_preclose(struct drm_device *dev,
2885f6ac 2466 struct drm_file *file);
673a394b 2467extern void i915_driver_postclose(struct drm_device *dev,
2885f6ac 2468 struct drm_file *file);
84b1fd10 2469extern int i915_driver_device_is_agp(struct drm_device * dev);
c43b5634 2470#ifdef CONFIG_COMPAT
0d6aa60b
DA
2471extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2472 unsigned long arg);
c43b5634 2473#endif
8e96d9c4 2474extern int intel_gpu_reset(struct drm_device *dev);
d4b8bb2a 2475extern int i915_reset(struct drm_device *dev);
7648fa99
JB
2476extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2477extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2478extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2479extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
650ad970 2480int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1d0d343a 2481void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
7648fa99 2482
1da177e4 2483/* i915_irq.c */
10cd45b6 2484void i915_queue_hangcheck(struct drm_device *dev);
58174462
MK
2485__printf(3, 4)
2486void i915_handle_error(struct drm_device *dev, bool wedged,
2487 const char *fmt, ...);
1da177e4 2488
b963291c
DV
2489extern void intel_irq_init(struct drm_i915_private *dev_priv);
2490extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2aeb7d3a
DV
2491int intel_irq_install(struct drm_i915_private *dev_priv);
2492void intel_irq_uninstall(struct drm_i915_private *dev_priv);
907b28c5
CW
2493
2494extern void intel_uncore_sanitize(struct drm_device *dev);
10018603
ID
2495extern void intel_uncore_early_sanitize(struct drm_device *dev,
2496 bool restore_forcewake);
907b28c5 2497extern void intel_uncore_init(struct drm_device *dev);
907b28c5 2498extern void intel_uncore_check_errors(struct drm_device *dev);
aec347ab 2499extern void intel_uncore_fini(struct drm_device *dev);
156c7ca0 2500extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
48c1026a 2501const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
59bad947 2502void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
48c1026a 2503 enum forcewake_domains domains);
59bad947 2504void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
48c1026a 2505 enum forcewake_domains domains);
59bad947 2506void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
cf9d2890
YZ
2507static inline bool intel_vgpu_active(struct drm_device *dev)
2508{
2509 return to_i915(dev)->vgpu.active;
2510}
b1f14ad0 2511
7c463586 2512void
50227e1c 2513i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2514 u32 status_mask);
7c463586
KP
2515
2516void
50227e1c 2517i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2518 u32 status_mask);
7c463586 2519
f8b79e58
ID
2520void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2521void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
47339cd9
DV
2522void
2523ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2524void
2525ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2526void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2527 uint32_t interrupt_mask,
2528 uint32_t enabled_irq_mask);
2529#define ibx_enable_display_interrupt(dev_priv, bits) \
2530 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2531#define ibx_disable_display_interrupt(dev_priv, bits) \
2532 ibx_display_interrupt_update((dev_priv), (bits), 0)
f8b79e58 2533
673a394b 2534/* i915_gem.c */
673a394b
EA
2535int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2536 struct drm_file *file_priv);
2537int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2538 struct drm_file *file_priv);
2539int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2540 struct drm_file *file_priv);
2541int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2542 struct drm_file *file_priv);
de151cf6
JB
2543int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2544 struct drm_file *file_priv);
673a394b
EA
2545int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2546 struct drm_file *file_priv);
2547int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2548 struct drm_file *file_priv);
ba8b7ccb
OM
2549void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2550 struct intel_engine_cs *ring);
2551void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2552 struct drm_file *file,
2553 struct intel_engine_cs *ring,
2554 struct drm_i915_gem_object *obj);
a83014d3
OM
2555int i915_gem_ringbuffer_submission(struct drm_device *dev,
2556 struct drm_file *file,
2557 struct intel_engine_cs *ring,
2558 struct intel_context *ctx,
2559 struct drm_i915_gem_execbuffer2 *args,
2560 struct list_head *vmas,
2561 struct drm_i915_gem_object *batch_obj,
2562 u64 exec_start, u32 flags);
673a394b
EA
2563int i915_gem_execbuffer(struct drm_device *dev, void *data,
2564 struct drm_file *file_priv);
76446cac
JB
2565int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2566 struct drm_file *file_priv);
673a394b
EA
2567int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2568 struct drm_file *file_priv);
199adf40
BW
2569int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2570 struct drm_file *file);
2571int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2572 struct drm_file *file);
673a394b
EA
2573int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2574 struct drm_file *file_priv);
3ef94daa
CW
2575int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2576 struct drm_file *file_priv);
673a394b
EA
2577int i915_gem_set_tiling(struct drm_device *dev, void *data,
2578 struct drm_file *file_priv);
2579int i915_gem_get_tiling(struct drm_device *dev, void *data,
2580 struct drm_file *file_priv);
5cc9ed4b
CW
2581int i915_gem_init_userptr(struct drm_device *dev);
2582int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2583 struct drm_file *file);
5a125c3c
EA
2584int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2585 struct drm_file *file_priv);
23ba4fd0
BW
2586int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2587 struct drm_file *file_priv);
673a394b 2588void i915_gem_load(struct drm_device *dev);
21ab4e74
CW
2589unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2590 long target,
2591 unsigned flags);
2592#define I915_SHRINK_PURGEABLE 0x1
2593#define I915_SHRINK_UNBOUND 0x2
2594#define I915_SHRINK_BOUND 0x4
42dcedd4
CW
2595void *i915_gem_object_alloc(struct drm_device *dev);
2596void i915_gem_object_free(struct drm_i915_gem_object *obj);
37e680a1
CW
2597void i915_gem_object_init(struct drm_i915_gem_object *obj,
2598 const struct drm_i915_gem_object_ops *ops);
05394f39
CW
2599struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2600 size_t size);
7e0d96bc
BW
2601void i915_init_vm(struct drm_i915_private *dev_priv,
2602 struct i915_address_space *vm);
673a394b 2603void i915_gem_free_object(struct drm_gem_object *obj);
2f633156 2604void i915_gem_vma_destroy(struct i915_vma *vma);
42dcedd4 2605
1ec9e26d
DV
2606#define PIN_MAPPABLE 0x1
2607#define PIN_NONBLOCK 0x2
bf3d149b 2608#define PIN_GLOBAL 0x4
d23db88c
CW
2609#define PIN_OFFSET_BIAS 0x8
2610#define PIN_OFFSET_MASK (~4095)
fe14d5f4
TU
2611int __must_check i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
2612 struct i915_address_space *vm,
2613 uint32_t alignment,
2614 uint64_t flags,
2615 const struct i915_ggtt_view *view);
2616static inline
2021746e 2617int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
c37e2204 2618 struct i915_address_space *vm,
2021746e 2619 uint32_t alignment,
fe14d5f4
TU
2620 uint64_t flags)
2621{
2622 return i915_gem_object_pin_view(obj, vm, alignment, flags,
2623 &i915_ggtt_view_normal);
2624}
2625
2626int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2627 u32 flags);
07fe0b12 2628int __must_check i915_vma_unbind(struct i915_vma *vma);
dd624afd 2629int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
48018a57 2630void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
05394f39 2631void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
f787a5f5 2632
4c914c0c
BV
2633int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2634 int *needs_clflush);
2635
37e680a1 2636int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
9da3da66
CW
2637static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2638{
67d5a50c
ID
2639 struct sg_page_iter sg_iter;
2640
2641 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2db76d7c 2642 return sg_page_iter_page(&sg_iter);
67d5a50c
ID
2643
2644 return NULL;
9da3da66 2645}
a5570178
CW
2646static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2647{
2648 BUG_ON(obj->pages == NULL);
2649 obj->pages_pin_count++;
2650}
2651static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2652{
2653 BUG_ON(obj->pages_pin_count == 0);
2654 obj->pages_pin_count--;
2655}
2656
54cf91dc 2657int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2911a35b 2658int i915_gem_object_sync(struct drm_i915_gem_object *obj,
a4872ba6 2659 struct intel_engine_cs *to);
e2d05a8b 2660void i915_vma_move_to_active(struct i915_vma *vma,
a4872ba6 2661 struct intel_engine_cs *ring);
ff72145b
DA
2662int i915_gem_dumb_create(struct drm_file *file_priv,
2663 struct drm_device *dev,
2664 struct drm_mode_create_dumb *args);
da6b51d0
DA
2665int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2666 uint32_t handle, uint64_t *offset);
f787a5f5
CW
2667/**
2668 * Returns true if seq1 is later than seq2.
2669 */
2670static inline bool
2671i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2672{
2673 return (int32_t)(seq1 - seq2) >= 0;
2674}
2675
1b5a433a
JH
2676static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2677 bool lazy_coherency)
2678{
2679 u32 seqno;
2680
2681 BUG_ON(req == NULL);
2682
2683 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2684
2685 return i915_seqno_passed(seqno, req->seqno);
2686}
2687
fca26bb4
MK
2688int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2689int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
06d98131 2690int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
d9e86c0e 2691int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2021746e 2692
d8ffa60b
DV
2693bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2694void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
1690e1eb 2695
8d9fc7fd 2696struct drm_i915_gem_request *
a4872ba6 2697i915_gem_find_active_request(struct intel_engine_cs *ring);
8d9fc7fd 2698
b29c19b6 2699bool i915_gem_retire_requests(struct drm_device *dev);
a4872ba6 2700void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
33196ded 2701int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
d6b2c790 2702 bool interruptible);
b6660d59 2703int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
84c33a64 2704
1f83fee0
DV
2705static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2706{
2707 return unlikely(atomic_read(&error->reset_counter)
2ac0f450 2708 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
1f83fee0
DV
2709}
2710
2711static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2712{
2ac0f450
MK
2713 return atomic_read(&error->reset_counter) & I915_WEDGED;
2714}
2715
2716static inline u32 i915_reset_count(struct i915_gpu_error *error)
2717{
2718 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
1f83fee0 2719}
a71d8d94 2720
88b4aa87
MK
2721static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2722{
2723 return dev_priv->gpu_error.stop_rings == 0 ||
2724 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2725}
2726
2727static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2728{
2729 return dev_priv->gpu_error.stop_rings == 0 ||
2730 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2731}
2732
069efc1d 2733void i915_gem_reset(struct drm_device *dev);
000433b6 2734bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
a8198eea 2735int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1070a42b 2736int __must_check i915_gem_init(struct drm_device *dev);
a83014d3 2737int i915_gem_init_rings(struct drm_device *dev);
f691e2f4 2738int __must_check i915_gem_init_hw(struct drm_device *dev);
a4872ba6 2739int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
f691e2f4 2740void i915_gem_init_swizzling(struct drm_device *dev);
79e53945 2741void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
b2da9fe5 2742int __must_check i915_gpu_idle(struct drm_device *dev);
45c5f202 2743int __must_check i915_gem_suspend(struct drm_device *dev);
a4872ba6 2744int __i915_add_request(struct intel_engine_cs *ring,
0025c077 2745 struct drm_file *file,
9400ae5c
JH
2746 struct drm_i915_gem_object *batch_obj);
2747#define i915_add_request(ring) \
2748 __i915_add_request(ring, NULL, NULL)
9c654818 2749int __i915_wait_request(struct drm_i915_gem_request *req,
16e9a21f
ACO
2750 unsigned reset_counter,
2751 bool interruptible,
2752 s64 *timeout,
2753 struct drm_i915_file_private *file_priv);
a4b3a571 2754int __must_check i915_wait_request(struct drm_i915_gem_request *req);
de151cf6 2755int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2021746e
CW
2756int __must_check
2757i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2758 bool write);
2759int __must_check
dabdfe02
CW
2760i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2761int __must_check
2da3b9b9
CW
2762i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2763 u32 alignment,
a4872ba6 2764 struct intel_engine_cs *pipelined);
cc98b413 2765void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
00731155 2766int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
6eeefaf3 2767 int align);
b29c19b6 2768int i915_gem_open(struct drm_device *dev, struct drm_file *file);
05394f39 2769void i915_gem_release(struct drm_device *dev, struct drm_file *file);
673a394b 2770
0fa87796
ID
2771uint32_t
2772i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
467cffba 2773uint32_t
d865110c
ID
2774i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2775 int tiling_mode, bool fenced);
467cffba 2776
e4ffd173
CW
2777int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2778 enum i915_cache_level cache_level);
2779
1286ff73
DV
2780struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2781 struct dma_buf *dma_buf);
2782
2783struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2784 struct drm_gem_object *gem_obj, int flags);
2785
19b2dbde
CW
2786void i915_gem_restore_fences(struct drm_device *dev);
2787
fe14d5f4
TU
2788unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
2789 struct i915_address_space *vm,
2790 enum i915_ggtt_view_type view);
2791static inline
a70a3148 2792unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
fe14d5f4
TU
2793 struct i915_address_space *vm)
2794{
2795 return i915_gem_obj_offset_view(o, vm, I915_GGTT_VIEW_NORMAL);
2796}
a70a3148 2797bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
fe14d5f4
TU
2798bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
2799 struct i915_address_space *vm,
2800 enum i915_ggtt_view_type view);
2801static inline
a70a3148 2802bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
fe14d5f4
TU
2803 struct i915_address_space *vm)
2804{
2805 return i915_gem_obj_bound_view(o, vm, I915_GGTT_VIEW_NORMAL);
2806}
2807
a70a3148
BW
2808unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2809 struct i915_address_space *vm);
fe14d5f4
TU
2810struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
2811 struct i915_address_space *vm,
2812 const struct i915_ggtt_view *view);
2813static inline
a70a3148 2814struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
fe14d5f4
TU
2815 struct i915_address_space *vm)
2816{
2817 return i915_gem_obj_to_vma_view(obj, vm, &i915_ggtt_view_normal);
2818}
2819
2820struct i915_vma *
2821i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj,
2822 struct i915_address_space *vm,
2823 const struct i915_ggtt_view *view);
2824
2825static inline
accfef2e
BW
2826struct i915_vma *
2827i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
fe14d5f4
TU
2828 struct i915_address_space *vm)
2829{
2830 return i915_gem_obj_lookup_or_create_vma_view(obj, vm,
2831 &i915_ggtt_view_normal);
2832}
5c2abbea
BW
2833
2834struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
d7f46fc4
BW
2835static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2836 struct i915_vma *vma;
2837 list_for_each_entry(vma, &obj->vma_list, vma_link)
2838 if (vma->pin_count > 0)
2839 return true;
2840 return false;
2841}
5c2abbea 2842
a70a3148 2843/* Some GGTT VM helpers */
5dc383b0 2844#define i915_obj_to_ggtt(obj) \
a70a3148
BW
2845 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2846static inline bool i915_is_ggtt(struct i915_address_space *vm)
2847{
2848 struct i915_address_space *ggtt =
2849 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2850 return vm == ggtt;
2851}
2852
841cd773
DV
2853static inline struct i915_hw_ppgtt *
2854i915_vm_to_ppgtt(struct i915_address_space *vm)
2855{
2856 WARN_ON(i915_is_ggtt(vm));
2857
2858 return container_of(vm, struct i915_hw_ppgtt, base);
2859}
2860
2861
a70a3148
BW
2862static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2863{
5dc383b0 2864 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
a70a3148
BW
2865}
2866
2867static inline unsigned long
2868i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2869{
5dc383b0 2870 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
a70a3148
BW
2871}
2872
2873static inline unsigned long
2874i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2875{
5dc383b0 2876 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
a70a3148 2877}
c37e2204
BW
2878
2879static inline int __must_check
2880i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2881 uint32_t alignment,
1ec9e26d 2882 unsigned flags)
c37e2204 2883{
5dc383b0
DV
2884 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2885 alignment, flags | PIN_GLOBAL);
c37e2204 2886}
a70a3148 2887
b287110e
DV
2888static inline int
2889i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2890{
2891 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2892}
2893
2894void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2895
254f965c 2896/* i915_gem_context.c */
8245be31 2897int __must_check i915_gem_context_init(struct drm_device *dev);
254f965c 2898void i915_gem_context_fini(struct drm_device *dev);
acce9ffa 2899void i915_gem_context_reset(struct drm_device *dev);
e422b888 2900int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2fa48d8d 2901int i915_gem_context_enable(struct drm_i915_private *dev_priv);
254f965c 2902void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
a4872ba6 2903int i915_switch_context(struct intel_engine_cs *ring,
273497e5
OM
2904 struct intel_context *to);
2905struct intel_context *
41bde553 2906i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
dce3271b 2907void i915_gem_context_free(struct kref *ctx_ref);
8c857917
OM
2908struct drm_i915_gem_object *
2909i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
273497e5 2910static inline void i915_gem_context_reference(struct intel_context *ctx)
dce3271b 2911{
691e6415 2912 kref_get(&ctx->ref);
dce3271b
MK
2913}
2914
273497e5 2915static inline void i915_gem_context_unreference(struct intel_context *ctx)
dce3271b 2916{
691e6415 2917 kref_put(&ctx->ref, i915_gem_context_free);
dce3271b
MK
2918}
2919
273497e5 2920static inline bool i915_gem_context_is_default(const struct intel_context *c)
3fac8978 2921{
821d66dd 2922 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3fac8978
MK
2923}
2924
84624813
BW
2925int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2926 struct drm_file *file);
2927int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2928 struct drm_file *file);
c9dc0f35
CW
2929int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2930 struct drm_file *file_priv);
2931int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2932 struct drm_file *file_priv);
1286ff73 2933
679845ed
BW
2934/* i915_gem_evict.c */
2935int __must_check i915_gem_evict_something(struct drm_device *dev,
2936 struct i915_address_space *vm,
2937 int min_size,
2938 unsigned alignment,
2939 unsigned cache_level,
d23db88c
CW
2940 unsigned long start,
2941 unsigned long end,
1ec9e26d 2942 unsigned flags);
679845ed
BW
2943int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2944int i915_gem_evict_everything(struct drm_device *dev);
1d2a314c 2945
0260c420 2946/* belongs in i915_gem_gtt.h */
d09105c6 2947static inline void i915_gem_chipset_flush(struct drm_device *dev)
e76e9aeb
BW
2948{
2949 if (INTEL_INFO(dev)->gen < 6)
2950 intel_gtt_chipset_flush();
2951}
246cbfb5 2952
9797fbfb
CW
2953/* i915_gem_stolen.c */
2954int i915_gem_init_stolen(struct drm_device *dev);
5e59f717 2955int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
11be49eb 2956void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
9797fbfb 2957void i915_gem_cleanup_stolen(struct drm_device *dev);
0104fdbb
CW
2958struct drm_i915_gem_object *
2959i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
866d12b4
CW
2960struct drm_i915_gem_object *
2961i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2962 u32 stolen_offset,
2963 u32 gtt_offset,
2964 u32 size);
9797fbfb 2965
673a394b 2966/* i915_gem_tiling.c */
2c1792a1 2967static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
e9b73c67 2968{
50227e1c 2969 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
e9b73c67
CW
2970
2971 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2972 obj->tiling_mode != I915_TILING_NONE;
2973}
2974
673a394b 2975void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
05394f39
CW
2976void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2977void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
673a394b
EA
2978
2979/* i915_gem_debug.c */
23bc5982
CW
2980#if WATCH_LISTS
2981int i915_verify_lists(struct drm_device *dev);
673a394b 2982#else
23bc5982 2983#define i915_verify_lists(dev) 0
673a394b 2984#endif
1da177e4 2985
2017263e 2986/* i915_debugfs.c */
27c202ad
BG
2987int i915_debugfs_init(struct drm_minor *minor);
2988void i915_debugfs_cleanup(struct drm_minor *minor);
f8c168fa 2989#ifdef CONFIG_DEBUG_FS
07144428
DL
2990void intel_display_crc_init(struct drm_device *dev);
2991#else
f8c168fa 2992static inline void intel_display_crc_init(struct drm_device *dev) {}
07144428 2993#endif
84734a04
MK
2994
2995/* i915_gpu_error.c */
edc3d884
MK
2996__printf(2, 3)
2997void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
fc16b48b
MK
2998int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2999 const struct i915_error_state_file_priv *error);
4dc955f7 3000int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
0a4cd7c8 3001 struct drm_i915_private *i915,
4dc955f7
MK
3002 size_t count, loff_t pos);
3003static inline void i915_error_state_buf_release(
3004 struct drm_i915_error_state_buf *eb)
3005{
3006 kfree(eb->buf);
3007}
58174462
MK
3008void i915_capture_error_state(struct drm_device *dev, bool wedge,
3009 const char *error_msg);
84734a04
MK
3010void i915_error_state_get(struct drm_device *dev,
3011 struct i915_error_state_file_priv *error_priv);
3012void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3013void i915_destroy_error_state(struct drm_device *dev);
3014
3015void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
0a4cd7c8 3016const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2017263e 3017
493018dc
BV
3018/* i915_gem_batch_pool.c */
3019void i915_gem_batch_pool_init(struct drm_device *dev,
3020 struct i915_gem_batch_pool *pool);
3021void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
3022struct drm_i915_gem_object*
3023i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size);
3024
351e3db2 3025/* i915_cmd_parser.c */
d728c8ef 3026int i915_cmd_parser_get_version(void);
a4872ba6
OM
3027int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3028void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3029bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3030int i915_parse_cmds(struct intel_engine_cs *ring,
351e3db2 3031 struct drm_i915_gem_object *batch_obj,
78a42377 3032 struct drm_i915_gem_object *shadow_batch_obj,
351e3db2 3033 u32 batch_start_offset,
b9ffd80e 3034 u32 batch_len,
351e3db2
BV
3035 bool is_master);
3036
317c35d1
JB
3037/* i915_suspend.c */
3038extern int i915_save_state(struct drm_device *dev);
3039extern int i915_restore_state(struct drm_device *dev);
0a3e67a4 3040
0136db58
BW
3041/* i915_sysfs.c */
3042void i915_setup_sysfs(struct drm_device *dev_priv);
3043void i915_teardown_sysfs(struct drm_device *dev_priv);
3044
f899fc64
CW
3045/* intel_i2c.c */
3046extern int intel_setup_gmbus(struct drm_device *dev);
3047extern void intel_teardown_gmbus(struct drm_device *dev);
8f375e10 3048static inline bool intel_gmbus_is_port_valid(unsigned port)
3bd7d909 3049{
2ed06c93 3050 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
3bd7d909
DK
3051}
3052
3053extern struct i2c_adapter *intel_gmbus_get_adapter(
3054 struct drm_i915_private *dev_priv, unsigned port);
e957d772
CW
3055extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3056extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
8f375e10 3057static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
b8232e90
CW
3058{
3059 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3060}
f899fc64
CW
3061extern void intel_i2c_reset(struct drm_device *dev);
3062
3b617967 3063/* intel_opregion.c */
44834a67 3064#ifdef CONFIG_ACPI
27d50c82 3065extern int intel_opregion_setup(struct drm_device *dev);
44834a67
CW
3066extern void intel_opregion_init(struct drm_device *dev);
3067extern void intel_opregion_fini(struct drm_device *dev);
3b617967 3068extern void intel_opregion_asle_intr(struct drm_device *dev);
9c4b0a68
JN
3069extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3070 bool enable);
ecbc5cf3
JN
3071extern int intel_opregion_notify_adapter(struct drm_device *dev,
3072 pci_power_t state);
65e082c9 3073#else
27d50c82 3074static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
44834a67
CW
3075static inline void intel_opregion_init(struct drm_device *dev) { return; }
3076static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3b617967 3077static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
9c4b0a68
JN
3078static inline int
3079intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3080{
3081 return 0;
3082}
ecbc5cf3
JN
3083static inline int
3084intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3085{
3086 return 0;
3087}
65e082c9 3088#endif
8ee1c3db 3089
723bfd70
JB
3090/* intel_acpi.c */
3091#ifdef CONFIG_ACPI
3092extern void intel_register_dsm_handler(void);
3093extern void intel_unregister_dsm_handler(void);
3094#else
3095static inline void intel_register_dsm_handler(void) { return; }
3096static inline void intel_unregister_dsm_handler(void) { return; }
3097#endif /* CONFIG_ACPI */
3098
79e53945 3099/* modesetting */
f817586c 3100extern void intel_modeset_init_hw(struct drm_device *dev);
79e53945 3101extern void intel_modeset_init(struct drm_device *dev);
2c7111db 3102extern void intel_modeset_gem_init(struct drm_device *dev);
79e53945 3103extern void intel_modeset_cleanup(struct drm_device *dev);
4932e2c3 3104extern void intel_connector_unregister(struct intel_connector *);
28d52043 3105extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
45e2b5f6
DV
3106extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3107 bool force_restore);
44cec740 3108extern void i915_redisable_vga(struct drm_device *dev);
04098753 3109extern void i915_redisable_vga_power_on(struct drm_device *dev);
7648fa99 3110extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
dde86e2d 3111extern void intel_init_pch_refclk(struct drm_device *dev);
ffe02b40 3112extern void intel_set_rps(struct drm_device *dev, u8 val);
5209b1f4
ID
3113extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3114 bool enable);
0206e353
AJ
3115extern void intel_detect_pch(struct drm_device *dev);
3116extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
0136db58 3117extern int intel_enable_rc6(const struct drm_device *dev);
3bad0781 3118
2911a35b 3119extern bool i915_semaphore_is_enabled(struct drm_device *dev);
c0c7babc
BW
3120int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3121 struct drm_file *file);
b6359918
MK
3122int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3123 struct drm_file *file);
575155a9 3124
6ef3d427
CW
3125/* overlay */
3126extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
edc3d884
MK
3127extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3128 struct intel_overlay_error_state *error);
c4a1d9e4
CW
3129
3130extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
edc3d884 3131extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
c4a1d9e4
CW
3132 struct drm_device *dev,
3133 struct intel_display_error_state *error);
6ef3d427 3134
151a49d0
TR
3135int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3136int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
59de0813
JN
3137
3138/* intel_sideband.c */
707b6e3d
D
3139u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3140void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
64936258 3141u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
e9f882a3
JN
3142u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3143void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3144u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3145void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3146u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3147void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
f3419158
JB
3148u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3149void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
e9f882a3
JN
3150u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3151void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
5e69f97f
CML
3152u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3153void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
59de0813
JN
3154u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3155 enum intel_sbi_destination destination);
3156void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3157 enum intel_sbi_destination destination);
e9fe51c6
SK
3158u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3159void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
0a073b84 3160
616bc820
VS
3161int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3162int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
c8d9a590 3163
0b274481
BW
3164#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3165#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3166
3167#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3168#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3169#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3170#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3171
3172#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3173#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3174#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3175#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3176
698b3135
CW
3177/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3178 * will be implemented using 2 32-bit writes in an arbitrary order with
3179 * an arbitrary delay between them. This can cause the hardware to
3180 * act upon the intermediate value, possibly leading to corruption and
3181 * machine death. You have been warned.
3182 */
0b274481
BW
3183#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3184#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
cae5852d 3185
50877445
CW
3186#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3187 u32 upper = I915_READ(upper_reg); \
3188 u32 lower = I915_READ(lower_reg); \
3189 u32 tmp = I915_READ(upper_reg); \
3190 if (upper != tmp) { \
3191 upper = tmp; \
3192 lower = I915_READ(lower_reg); \
3193 WARN_ON(I915_READ(upper_reg) != upper); \
3194 } \
3195 (u64)upper << 32 | lower; })
3196
cae5852d
ZN
3197#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3198#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3199
55bc60db
VS
3200/* "Broadcast RGB" property */
3201#define INTEL_BROADCAST_RGB_AUTO 0
3202#define INTEL_BROADCAST_RGB_FULL 1
3203#define INTEL_BROADCAST_RGB_LIMITED 2
ba4f01a3 3204
766aa1c4
VS
3205static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3206{
92e23b99 3207 if (IS_VALLEYVIEW(dev))
766aa1c4 3208 return VLV_VGACNTRL;
92e23b99
SJ
3209 else if (INTEL_INFO(dev)->gen >= 5)
3210 return CPU_VGACNTRL;
766aa1c4
VS
3211 else
3212 return VGACNTRL;
3213}
3214
2bb4629a
VS
3215static inline void __user *to_user_ptr(u64 address)
3216{
3217 return (void __user *)(uintptr_t)address;
3218}
3219
df97729f
ID
3220static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3221{
3222 unsigned long j = msecs_to_jiffies(m);
3223
3224 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3225}
3226
7bd0e226
DV
3227static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3228{
3229 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3230}
3231
df97729f
ID
3232static inline unsigned long
3233timespec_to_jiffies_timeout(const struct timespec *value)
3234{
3235 unsigned long j = timespec_to_jiffies(value);
3236
3237 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3238}
3239
dce56b3c
PZ
3240/*
3241 * If you need to wait X milliseconds between events A and B, but event B
3242 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3243 * when event A happened, then just before event B you call this function and
3244 * pass the timestamp as the first argument, and X as the second argument.
3245 */
3246static inline void
3247wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3248{
ec5e0cfb 3249 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
dce56b3c
PZ
3250
3251 /*
3252 * Don't re-read the value of "jiffies" every time since it may change
3253 * behind our back and break the math.
3254 */
3255 tmp_jiffies = jiffies;
3256 target_jiffies = timestamp_jiffies +
3257 msecs_to_jiffies_timeout(to_wait_ms);
3258
3259 if (time_after(target_jiffies, tmp_jiffies)) {
ec5e0cfb
ID
3260 remaining_jiffies = target_jiffies - tmp_jiffies;
3261 while (remaining_jiffies)
3262 remaining_jiffies =
3263 schedule_timeout_uninterruptible(remaining_jiffies);
dce56b3c
PZ
3264 }
3265}
3266
581c26e8
JH
3267static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3268 struct drm_i915_gem_request *req)
3269{
3270 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3271 i915_gem_request_assign(&ring->trace_irq_req, req);
3272}
3273
1da177e4 3274#endif